MSP430 Universal Synchronous Asynchronous Receive/T ransmit Communication Interface

Application Report

April 1999

Mixed Signal Products
SLAA049

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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Attributes of the MSP430 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 UART Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 3 4

2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Baud Rate Generation With the MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Baud Rate Generation With the ACLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Software Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Non-Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 MCLK Used as UART Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 ACLK Used as UART Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Subroutines and .MACROs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 .MACROs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 12 12 16 20 20 21

4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Appendix A Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

List of Figures
1 2 3 4 5 6 7 MSP430 USART Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART Switched to the UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS232 Format (Levels at the MSP430) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS232 Format (Levels on the Transmission Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART Control Registers Used in the UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function of the Baud Rate Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 4 5 6 8

List of Tables
1 Content of Baud Rate Registers UBR (MCLK = 1.048 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Content of Baud Rate Registers UBR (ACLK = 32,768 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface

iii

iv SLAA049 .

MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface Lutz Bierl ABSTRACT This application report gives a short overview for the use of the MSP430 universal synchronous. Future MSP430 family members may have different hardware addresses—especially for the I/O ports used. 1 Introduction The universal synchronous/asynchronous receive/transmit communication interface of the MSP430 family can operate in two different modes: synchronous and asynchronous. also called a serial-controller interface (SCI). with and without the use of the interrupt capability. This application report describes the software routines used with the asynchronous mode (SCI. with or without the interrupt capability. The hardware features of the USART module greatly exceed the capabilities illustrated in the examples included in this application report. A second report will handle the synchronous mode (serial protocol interface SPI). NOTE: The examples and hardware definitions use MSP430x33x addresses. NOTE: Reading the data book MSP430 Family Architecture Guide and Module Library is recommended. Full duplex mode is used for all examples running in active mode and low power mode 3 (LPM3). 1 . asynchronous receive/transmit communication interface (USART) as an RS232 interface. It complements the information contained in this application report. This report is intended as a fast way to get the USART running in the UART mode. Features frequently used are included in the examples. RS232). are given for the transmission and the reception of UART (universal asynchronous receive/transmit) signals. Tested software examples.

MSP430 USART Module 2 SLAA049 . Receive Status Receive Buffer URXBUF SYNC RXE Listen 0 MM 1 SYNC SOMI Receive Shift Register 1 SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud Rate Generator SYNC UCLKS UTXD Baud Rate Register UBR Baud Rate Generator SYNC 0 STE 0 SYNC URXD WUT Transmit Shift Register 1 SIMO 0 TXWake Transmit Buffer UTXBUF CKPH SYNC CKPL UCLK Clock Phase and Polarity Control Registers UCLKI UCLKS Figure 1.Introduction Figure 1 shows the block diagram of the MSP430 USART module.

1 Attributes of the MSP430 UART The following is a short overview of the USART running in the UART mode: • Selectable seven and eight-bit data lengths • The error detection for the receive path is as follows: – Frame error. one for reception • Full functionality during LPM3 • End-of-frame flag usable with interrupt or polling 1. and Figure 4 shows how the format is defined on the transmission line. The next character is read in before the last one is read out by the software. Parity is enabled and the parity bit has the wrong value. The format shown in Figures 3 and 4 has: MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 3 . – Overrun error. Figure 3 shows how this format is seen at the MSP430 ports (URXD and UTXD). The URXD pin has low potential for more than 10 bits. – Parity error. – Break detect.2 Data Format The data format used is RS232.Introduction Figure 2 shows the situation when the USART is switched to the UART mode by setting the SYNC bit UCTL. The stop bits have space potential. USART Switched to the UART Mode 1.2 to zero SYNC = 0 Receive Status Receive Buffer URXBUF RXE Listen 0 Data URXD Receive Shift Register 1 SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud Rate Generator Data UTXD Baud Rate Register UBR Baud Rate Generator UCLKS WUT Transmit Shift Register LSB first TXWake Transmit Buffer UTXBUF CKPL Control Registers UCLKI UCLKS Clock Polarity UCLK Figure 2. • Baud-rate generation made possible by 32-kHz crystal due to the modulation register • Interrupt-driven transmit and receive functions • Two independent interrupt vectors: one for transmission.

Parity enabled. This is the normal case. The parity bit follows the most-significant bit of the data. The register and bit definitions are found in Appendix A. The least-significant bit follows the start bit. This is illustrated in Figure 4. assembler mnemonics. and their initial states. hardware addresses. Figure 5 gives an overview of these eight registers including the names. 4 SLAA049 . RS232 Format (Levels at the MSP430) The signal on the transmission line has the inverted state when observed at the MSP430 ports.Introduction • • • • Seven data bits. All of them are 8-bit registers and consequently should only be accessed with byte instructions. and different voltage potentials. RS232 Format (Levels on the Transmission Line) 1. Two stop bits Data 1 Signal Level VCC Start Bit LSB 0 Parity MSB Bit Stop Bits 0V Name Mark Space Figure 3. No address bit. Name Space Start Bit Mark 1 LSB MSB Parity Bit Stop Bits <–3V Data 0 Signal Level >+3V Figure 4.3 UART Hardware Registers The USART is controlled by seven control registers and one read-only register.

USART Control Registers Used in the UART Mode MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 5 .Introduction Register Name USART Control Register Transmit Control Register Receive Control Register Modulation Control Register Baud-Rate Register 0 Baud-Rate Register 1 Receive Buffer Transmit Buffer Mnemonic UCTL UTCTL URCTL UMCTL UBR0 UBR1 URXBUF UTXBUF Register Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Address 070h 071h 072h 073h 074h 075h 076h 077h Initial State See below See below See below unchanged unchanged unchanged unchanged unchanged 7 UCTL 070h PENA rw-0 7 UTCTL 071 unused rw-0 7 URCTL 072h FE rw-0 7 URXBUF 076h 27 r 26 r 25 r 24 r 23 r 22 r 21 r PE rw-0 OE rw-0 BRK rw-0 URXEIE rw-0 URXWIE rw-0 RXWake rw-0 CKPL rw-0 SSEL 1 rw-0 SSEL0 rw-0 URXSE rw-0 TXWake rw-0 unused rw-0 PEV rw-0 SP rw-0 CHAR rw-0 Listen rw-0 SYNC rw-0 MM rw-0 0 SWRST rw-1 0 TXEPT rw-1 0 RXERR rw-0 0 20 r UTXBUF 077h UMCTL 073h UBR1 075h UBR0 074h 7 27 rw 7 215 rw 7 m7 rw 7 27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw m6 rw m5 rw m4 rw m3 rw m2 rw m1 rw 214 rw 213 rw 212 rw 211 rw 210 rw 29 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw 0 21 rw 0 28 rw 0 m0 rw 0 20 rw Figure 5.

the bit sequence m0 thru m7 is repeated. and so on.Baud Rate Generation 2 Baud Rate Generation It is easy to generate the desired baud rate from a relatively high frequency (1 MHz to 5 MHz): the resulting baud rate error is small due to the large integer-part of the quotient compared to the truncated fractional-part. After using bit m7. the next bit (m1) for the LSB of the data. 6 SLAA049 ÎÎÎ ÎÎÎ ÎÎ ÎÎ . The content of UBR1/UBR0 is not changed. For this reason. m = 0 INT(n/2)+m(=1) Divide By n(Even). This is not the case when the time base used is a 32-kHz crystal. 0 SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 BRCLK 15-Bit Prescaler/Divider Q1 Compare 0 or 1 Q15 Toggle FF BITCLK Shift Modulation Register Data m Shift_out Shift_in 1 UBR0 7 7 0 UBR1 8 15 7 Start 0 Modulation Register UMCTL Start BRCLK Counter H L H L n/2 n/2-1 n/2-2 1 1 1 7 0 n/2 n/2-1 n/2 n/2-1 n/2-2 n/2 n/2-1 n/2-2 2 1 1 0 1 n/2 0 n/2 n/2 n/2-1 n/2-1 n/2-2 H BITCLK L INT(n/2). Baud Rate Generator The LSB (m0) of register UMCTL is used for the start bit. the MSP430 USART uses a correction to keep the baud rate error small. since the error due to the truncated fractional-part of the quotient becomes large and leads to the loss of synchrony at the trailing bits of the frame. These bits determine the use of the predivider information contained in the two baud-rate registers UBR0 and UBR1: • A Zero bit in the UMCTL register means that the information contained in UBR1/UBR0 is used as is. m = 0 n(Odd) or n(Even)+m(=1) n(Odd)+m(=1) Figure 6. The modulation register UMCTL contains 8 bits of information to correct the baud rate of the received or transmitted UART signal. See Figure 7 for a graphic explanation. • A One bit means that the 16-bit content of UBR1/UBR0 is incremented by one before it is used.

82667 = 6.m0 is EFh (11101111b).768 Hz.65333 + 0.13333 4.44000 Carry to next integer UMCTL Bits Yes m0 1 Yes m1 1 Yes m2 1 Yes m3 1 No m4 0 Yes m5 1 Yes m6 1 Yes m7 1 The result of the calculated bits m7. This is necessary because the UART also has to run during low power mode 3.48000 2.82667 4800 This means that the baud-rate register UBR1 (MSBs) is loaded with zero.96000 + 0. Section 3. the theoretical division factor—the truncated value is the content of baud-rate register UBR (UBR1/UBR0)—is: UBR + 32768 + 6. For the above example.82667 = 1. An example using the fraction 0.. A second software macro (CALC_UBR) calculates the values of the two UBR registers. With only the ACLK available.13333 + 0.82667 = 7.48000 + 0.65333 1.61333 6.. the actual m-bit is set if a carry to the integer part occurs. The corrected baud rate with the UMCTL register containing 7 ones is: baud rate 7 32768 7 1 6 8 ) + 4766. the fractional part 0.78667 + 0. and the UBR0 register contains a 6.826667 is multiplied by 8 (the number of bits in register UMCTL): UMCTL + 0.30667 3.703% To get the best-fitting bit sequence for modulation register UMCTL.2545 * 4800 4800 + * 0.82667 = 4.3.82667 + 8 + 6.2545 100 This results in an average baud rate error of: baud rate error + 4766.82667 = 3.82667 = 4. MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 7 .30667 + 0. the following algorithm can be used: the fractional part of the theoretical division factor is summed up eight times. To get a rough estimate of the 8-bit modulation register UMCTL.Baud Rate Generation EXAMPLE: a baud rate of 4800 baud is required with a crystal frequency of 32. and is cleared otherwise.2 contains a software macro (CALC_UMCTL) that uses this algorithm to calculate the optimum value for the modulation register UMCTL for every combination of USART clock and desired baud rate.61333 + 0.96000 4.82667 = 5.82667 = 2.78667 5.82667 previously calculated follows: Fraction Addition 0.613 The rounded result 7 is the number of ones to be placed into the modulation register UMCTL.82667 + 0. the algorithm also finds EFh with its seven ones.

Baud Rate Generation EXAMPLE: Figure 7 presents an example using a 2400-baud rate generated with the ACLK frequency (32. Function of the Baud Rate Correction Tables 1 and 2 contain the average errors (full frame) for commonly used baud rates when using the described baud rate generation.3 bit-lengths after the second stop bit.65 13. The data format for Figure 7 is: eight data bits.1 Baud Rate Generation With the MCLK Table 1 shows the optimum values for the UBR and UMCTL registers. with 14 ACLK cycles for the bit length.65 13.3.768/2400 = 13.65 13.mnolist assembler directive. 2. The crystal error is not included.65 13. may be hidden in the listing by a .65 0V Rough Approximation Start Bit 14 LSB 14 14 14 14 14 14 14 MSB 14 Parity Bit 14 Stop Bit(s) 14 14 Error Corrected Timing Start Bit 14 m0 1 LSB 13 m1 0 14 m2 1 14 m3 1 13 m4 0 14 m5 1 14 m6 1 13 m7 0 MSB 14 m0 1 Parity Bit 13 m1 0 Stop Bit(s) 14 m2 1 14 m3 1 Error UNCTL Bits (6Dh) Figure 7. The values for the UMCTL and UBR1/UBR0 registers are calculated by the software MACROs in section 3.768 Hz).65 13. which do not need ROM or RAM.65 Parity Bit 13.65333).048 MHz). adds to the above error.65 13. The error of the crystal clock. The UART clock is the MCLK (1. • The lower frame shows a corrected frame using the best fit (6Dh) for the modulation register. It can be observed that the approximation with 14 ACLK cycles produces a cumulative error of more than 0.65 Stop Bit(s) 13. • The middle frame uses a rough estimate.2. not yet included. two stop bits. The error of the corrected frame is only 0.65 LSB 13.011 bit-lengths.65 MSB 13. no address bit. Figure 7 shows three different frames: • The upper frame is the correct one. 8 SLAA049 .65333 ACLK cycles (32. parity enabled. The software MACROs. with a bit-length of 13. The software examples in section 3 contain MACROs that automatically insert the correct values in the UBR registers and in the modulation register UMCTL. VCC Precise Timing Start Bit 13.65 13.

It is calculated by the software macro CALC_UMCTL.000 –0.002 –0.91 218. Table 2 shows the optimum values for the UBR and UMCTL registers for commonly used baud rates generated with the ACLK (32.048 MHz) BAUD RATE 110 300 600 1200 2400 4800 9600 19200 38400 DIVISION FACTOR 9532.768Hz).625 0.000 0.875 1.25 0.2.31 UBR1/UBR0 CONTENT 253Ch 0DA7h 06D3h 0369h 01B4h 00DAh 006Dh 0036h 001Bh CALCULATED UMCTL CONTENT 55h 44h 6Dh EFh FFh AAh 88h ADh 24h USED FRACTION 0.61 27.220 2. • Division Factor: The quotient UARTCLK/baud rate. MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 9 . • Calculated UMCTL Content: The 8-bit result that best fits the modulation register. The crystal is assumed to have no frequency-error.023 –0. The table values are calculated by the MACROs described in section 3.25 MEAN ERROR [%] +0.000 +0.1. It is an approximation to the truncated fractional-part of the division factor.81 436. The high byte is the UBR1 value.027 +0.45 109. Its value is calculated by software macro CALC_UBR.63 873. caused by the approximation to the division factor. Table 1. • UBR1/UBR0 Content: The truncated 16-bit hexadecimal result of the division factor (UARTCLK/baud rate).51 3495. • Used Fraction: The number of ones in the modulation register divided by eight.Baud Rate Generation Table 1 contains the following columns: • Baud Rate: The baud rate for data exchange (transmit and receive use the same baud rate).50 0. the low byte is the UBR0 value. • Mean Error: The resulting error of a complete character. The meaning of the table columns is explained in section 2.018 –0. Content of Baud Rate Registers UBR (MCLK = 1.3.23 54.625 0.007 –0. the importance of the modulation register UMCTL is much greater than with the normally high MCLK frequency used for the UART timing.50 0.25 1747.25 0.2 Baud Rate Generation With the ACLK With the relatively low ACLK frequency (32.00 0.768Hz).

The following control bits are held in the one state: UTXIFG and TXEPT. It is designed for: • Baud rate: 1200 baud • MCLK (1. . RXERROR. OE.8909 109. and software MACROs for the UART mode of the USART.6133 27. and if a new character has been received (URXIFG = 1). PE.3067 13.1 Non-Interrupt Processing The simplest way to use the USART in UART mode is this: interrupt is not enabled.00 0. URXIFG. the following control bits are held in the zero state: TXWAKE. NOTE: The program sequence for the initialization of the UART is important: as long as the SWRST bit (UCTL.625 0.7067 0.25 0. FE.12 3 Software Routines The following sections show proven software routines.8533 UBR1/UBR0 CONTENT 0129h 006Dh 0036h 001Bh 000Dh 0006h 0003h – – CALCULATED UMCTL CONTENT FFh 88h ADh 24h 6Dh EFh 4Ah USED FRACTION 1.375 MEAN ERROR [%] –0.768 Hz) BAUD RATE 110 300 600 1200 2400 4800 9600 19200 38400 DIVISION FACTOR 297. BRK.4133 1.625 0.048MHz) used as the UART clock • Eight data bits • Two stop bits • Parity enabled with odd parity • Receive of error-free characters only STACK . the software checks if it can output the next byte (UTXIFG = 1).21 +0. While the SWRST bit is zero.04 –0. The program sequences given in the software examples are recommended because they comply with this rule. UTXIE.21 –0.Software Routines Table 2.0) is set.equ 0600h . EXAMPLE: full duplex UART software code running without the use of the UART interrupt is shown. URXIE. RXWAKE.6533 6.2267 54.02 +0. subroutines. 3.25 0. Content of Baud Rate Registers UBR (ACLK = 32. Stack start address 10 SLAA049 . the receive and transmit control registers URCTL and UTCTL can not be initialized. Definitions for the UART part: user defined .8267 3.02 –0. .875 0.71 +1.

.048MHz FLLMPY*32768 . Continue with initialization BIC. The contents of the UMCTL and UBR registers are calculated.. UART parts within the main loop.equ 1200 32 . The software checks these two parts regularly. 2 stop bits . Software start address . .&UBR0 MOV. . . L$3 . .&UBR1 BIS.&P4SEL BIS.&UMCTL MOV. BIT. Baud Rate Register high . . Enable USART Modules #STACK. Initialize Stack Pointer .text .&UCTL . MCLK is used for UARTCLK MOV. Receive Control Register .B #UTXE+URXE. Modulation Reg. Baud rate is 1200 Baud . .&URCTL .&URCTL JZ . they only .B #CUBR0. Error handling . Init.B #FE+PE+OE+BRK+RXERR.. FLL multiplier for 1. Error during receive? . CALC_UMCTL CALC_UBR . R7 contains the received information. Modulation Register .. define the variables CUMCTL. Initialize the UART: odd parity.B #SSEL1+SSEL0. INIT MOV CALL .&UTCTL . Calculate UBR1/UBR0 contents .B #URXD+UTXD. 8 data bits.B #0.Software Routines Baudr FLLMPY UARTCLK . MCLK MOV. Select RXD + TXD at Port4 . No . USART Control Register MOV. MAINLOOP ..equ . content .&URCTL . Start Mainloop .B #CUMCTL. . . Continue in mainloop 11 MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface . Baud Rate Register low . MCLK for UART clock . check if a new character is received . MOV. Proceed with initialization . Clear error flags JMP L$2 . . ...B #PENA+SP_+CHAR.. UART registers UMCTL.SP #INITSR . FLL and RAM .equ .&ME2 .B #RXERR. The two software macros do not use RAM or ROM. Transmit Control Reg.B #CUBR1. Calc. CUBR1 and CUBR0 for the . UART Receive part: . UBR1 and UBR0.

B R6. wait .2 Interrupt Processing This is the normal mode to use the UART.B #SSEL0. .&UTCTL . . FE. ACLK is used for UARTCLK Macros CALC_UMCTL and CALC_UBRAll automatically make any other modifications necessary.B &URXBUF.B src. and the receive interrupt is enabled (IE2. No. Program Start Address . Otherwise the set-error flags will block the next interrupt.1 MCLK Used as UART Clock The following example covers the use of the MCLK to generate the UART clock or external frequencies in the MCLK range (500 kHz to 3. ... BIT.R6 L$1 . move character to R7 . and the transmit interrupt is enabled (IE2.R7. 3.&IFG2 JZ L$2 MOV.&UTXBUF MOV.0FFFEh .0 = 1) NOTE: If an error occurred during the reception of a character. Transmit Control Register ACLK .1 = 1).equ 32768 . Yes. R6 contains information to be transmitted. Interrupt Vectors . BRK. End of mainloop . Empty: move info to TX buffer . and: • A character is transmitted.2. and RXERR) must be reset within the UART interrupt handler. Continue in mainloop Only the following two source lines need to be modified if the previous software is to be used with the ACLK as the UART clock: UARTCLK .B #URXIFG. 12 SLAA049 . or • A character is received.8 MHz).Software Routines . MOV. Reset Vector . 3.&IFG2 JZ L$1 MOV. Continue with mainloop . BR #MAINLOOP .B #UTXIFG. . Transmit buffer empty? . . check if the next character can be transmitted. . L$2 .sect ”INITVEC”. L$3 BIT. UART Transmit part: . This does not apply to the overrun-error flag OE. Character received? . the error flags in the receive control register (PE.word INIT .. No.. Interrupt is requested if the general interrupt enable bit GIE (SR.3) is set. Next character to R6 . proceed to mainloop .

Pointer to receive buffer . Baudr FLLMPY UARTCLK . The two software macros do not use RAM or ROM .2 TXCNT. Counter/status for receive . content .144 MHz) used as the UART clock • Seven data bits • One stop bit • Parity enabled with even-parity • Receive of error-free characters only Transmit Part: the start address xxxx is loaded into pointer TXPOI. Initialize Stack Pointer 13 . STACK . Software start address . Definitions for the UART part . CALC_UMCTL CALC_UBR . INIT MOV #STACK. time for saving and restoring the register is not required.bss . Stack start address MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface . The content for the UMCTL and UBR registers are calculated . Calculate UBR1/UBR0 contents TXPOI. MCLK is used for UARTCLK . . Counter/status for transmit . The interrupt routine outputs the programmed character sequence starting at address xxxx. Word boundary .144MHz .equ 0600h .bss .equ .400 baud—dedicated CPU registers may be necessary to lower the interrupt overhead.2 uses dedicated registers. The software example shown in section 3. Only error-free characters are accepted.text .SP .2. The interrupt routine receives the characters and stores them into the buffer.equ .1 RCCNT. Receive Part: the start address yyyy of a RAM buffer is loaded into pointer RCPOI. Calculate Mod.bss . and the number of characters to be received is loaded into character count RCCNT. Pointer to transmit buffer .2 RCPOI. . FLL multiplier for 3.1 .bss . . . Baud rate is 19200 Baud .equ 19200 96 FLLMPY*32768 .even . and the number of characters to be output is loaded into character count TXCNT. It is designed for: • Baud rate: 19200 baud • The MCLK (3. Reg. EXAMPLE: a full-duplex UART software using the two UART interrupts is shown.Software Routines For high baud-rates—higher than 38.

Transmit Control Reg.B #m. EINT . TST.. Number of bytes to RCCNT .Software Routines CALL .B TXCNT CLR. Continue SLAA049 . Preparation for reception of m bytes.B #CUMCTL. . Modulation Register . Transmit part ready? . . . Status to zero . Initialize the UART: Even parity. No. . .B #TXEPT. Receive Control Register .B #CUBR0.&UMCTL MOV.B RCCNT . The currently received character .B #URXD+UTXD. Data input completed? . only error-free characters to URXBUF . BIT. buffer starts at address yyyy .&UBR1 BIS. Continue with initialization #INITSR ..&UCTL MOV.B RCCNT .B #CUBR1. Select RXD + TXD at Port4 . is input completely .RCCNT L$1 . Buffer start address to RCPOI . Preparation for the transmission of n bytes starting at .. 7 data bits.B #UTXE+URXE. Disable transmit .&P4SEL BIS. CLR..&UTCTL JZ 14 L$2 . 1 stop bit .B #0. Enable interrupt . . MAINLOOP . Enable USART interrupts ..&IE2 CLR. Continue in mainloop ..B RCCNT JNZ MOV L$1 #yyyy.B #UTXIE+URXIE. Stop the reception of data.. The input .B #PENA+PEV.RCPOI .&UTCTL MOV.. MCLK for UART clock. No. FLL and RAM . Proceed with initialization MOV.. Disable receive . Enable USART Modules . Init. Baud Rate Register high . . is really completed. Start of Mainloop . wait .B #SSEL1+SSEL0. Check if last transmit operation . MCLK .&URCTL BIS.. Baud Rate Register low . . USART Control Register .&UBR0 MOV. MOV.&ME2 MOV. address xxxx. buffers are not yet empty . .

Stop the transmission of data. status is 0 .. byte count . transmit buffer pointer . Clear error flags RETI . . . . Interrupt handler for the UART Receive part. TXINT TST. Save R5 . To next buffer byte .. Interrupt handler for the UART Transmit part.&URCTL JNZ RCERR DEC. MOV. Restore R5 . No.B TXCNT JZ TXRET . Interrupt Handlers .TXPOI R5 MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 15 . RCINT TST. Next byte for output .&URCTL .0(R5) INC MOV POP RCRET RETI . . R5 R5. init. Yes .B TXCNT . First info byte to TX buffer . .B RCCNT JZ RCRET .B #FE+PE+OE+BRK+RXERR.B RCCNT PUSH MOV R5 RCPOI. Update pointer .B xxxx. No. CLR... buffer is empty .B &URXBUF.TXPOI . The currently sent character . Init. No. Pointer to buffer .R5 MOV. Continue in background MOV.B #RXERR. Ready. Byte count –1 .B #n–1. RCERR ..R5 . Status to zero BIT.B TXCNT PUSH MOV R5 TXPOI. Error handling BIC. Byte count –1 DEC. is transmitted completely . .&UTXBUF MOV POP TXRET RETI R5. Next byte to buffer .Software Routines .RCPOI R5 . .B @R5+.&UTXBUF L$2 . Update pointer MOV.TXCNT MOV #xxxx+1. Error during receive? . Reception allowed? .. Something to transmit? . Pointer to buffer .

This manipulation omits the return to LPM3 and allows initialization of the next transmit sequence. The interrupt routine receives the characters and stores them in the buffer until RCCNT reaches zero (input completed). This section shows a different approach: here the CPU is normally off. .1 for an explanation.2 ACLK Used as UART Clock The following example deals with the ACLK used to generate the UART clock. when TXCNT reaches zero (output completed).word RCINT .sect ”SCIVEC”. and the number of characters m is loaded into character count TXCNT. R6 is exclusively used for the transmit part. and the number of characters n is loaded into character count RCCNT. See section 3. Receive Part: the start address yyyy of a RAM buffer is loaded into pointer RCPOI. . EXAMPLE: full-duplex UART software code using the UART interrupt is shown.sect ”INITVEC”.0FFFEh . Transmit vector . Interrupt Vectors . USART interrupt vectors .word INIT .2. Reset vector . it resets the CPUoff bit of the stored status register on the stack.768Hz) used as the UART clock • Eight data bits • Two stop bits • Parity enabled with odd-parity • Receive of error-free characters only • The CPU normally uses the low-power mode 3 (LPM3) Transmit Part: the start address xxxx of the output sequence is loaded into pointer TXPOI.0FFECh . and leaves the LPM3 only when the number of received or transmitted characters programmed is reached. Receive vector . R7 is exclusively used for the receive part. Only error-free characters are accepted. The interrupt routine outputs the character sequence and then. Then it resets the CPUoff bit of the stored status register on the stack.word TXINT . or external frequencies lower than 100 kHz.1 can be applied to the ACLK used as the UART clock. 16 SLAA049 . Basically the same method used in section 3. It is designed for: • Baud rate: 2400 baud • The ACLK (32.2.2. This manipulation omits the return to LPM3 and allows to process the received data.Software Routines . Program start address 3.

2 stop bits . ACLK used for the UART clock . Enable USART modules . Baud rate is 2400 Baud .B RCCNT JNZ L$1 . Ready? .&UBR0 MOV.B #SSEL0. Buffer starts . content .B #URXD+UTXD. . Continue with initialization .&UCTL MOV. ACLK is used for UARTCLK .B #CUBR0. Modulation Register .Software Routines STACK .. USART control register .. . at address yyyy. Select RXD + TXD at Port4 . Disable receive . .B TXCNT CLR. Preparation for the reception of m bytes. Calculate Mod.B #CUBR1. FLL multiplier for 2.equ 0600h .text .SP #INITSR .equ .equ 2400 64 32768 .. Software start address . Initialize the UART: Odd parity.&UBR1 BIS. Stack start address CALC_UMCTL CALC_UBR . #STACK. RCCNT > 0 17 . EINT . reg.&P4SEL BIS. Calculate UBR1/UBR0 contents . . Disable transmit .B RCCNT .equ .1 RCCNT. Baud rate register low .B #UTXE+URXE. Enable USART interrupts . Reg. Counter/status for transmit . FLL and RAM .. MAINLOOP . .096MHz .1 . ACLK . R7 is a dedicated register for receive . Counter/status for receive .B #CUMCTL.. Enable interrupt (GIE = 1) MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface . Initialize Stack Pointer . Start Mainloop .bss TXCNT. . Baudr FLLMPY UARTCLK .&UTCTL MOV. No. TST. MOV. Init. 8 data bits. INIT MOV CALL .&ME2 MOV.B #PENA+SP_+CHAR. Baud rate register high ..&IE2 CLR. Proceed with initialization .&UMCTL MOV.bss . Transmit contr.&URCTL BIS.B #UTXIE+URXIE.B #0. Definitions for the UART part . Receive control register .

No.B RCCNT . Ready for next characters? .. Ready. the program enters LPM3 . The check for the empty TX buffer is faster. PLPM3 .B RCCNT JZ PROCRC TST. TX part also ready? .. .B #n–1. Transmit: ..B #UTXIFG.Software Routines MOV L$1 . #xxxx+1.B TXCNT JNZ JZ . . Status is zero . Receive buffer start address . Transmit completed? receive input buffer full transmit buffer output completely other interrupt handlers BIS #CPUoff+GIE+SCG1+SCG0.R6 MOV. CLR. .. Number of bytes MOV. init. TST. .B xxxx. No. Preparation for transmission of n bytes starting at .B #m.&UTXBUF . . Init.B TXCNT . byte count . MOV. An interrupt handler cleared the CPUoff bit on the stack. Enter LPM3 . . TXCNT > 0 .. . .. . The actually received character . ..RCCNT SLAA049 . First info byte to TX buffer . Stop the reception of data. Checks are made to see if activity is needed: : Receive: . R6 is a dedicated register for transmit. Yes. process received data .TXCNT MOV L$2 .R7 . Status is zero #yyyy. is transmitted completely . transmit buffer pointer . busy . ROM bytes. Stop transmission of data.SR .. .. is input completely . .B TXCNT 18 . TST. Receive completed? .. but needs more . The actually sent character . CLR.&IFG2 . . address xxxx. Continue in background L$2 L$2 BIT. After completion of all tasks.

Receive vector . Error during receive? . RCERR . only for the receive part.. . TXINT TST.&UTXBUF TST. proceed DEC.0(SP) . RCINT TST. Something to transmit? .B RCCNT JNZ BIC RCRET . Program start address 19 MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface . R7 is used . Yes. R6 is used . No.B #FE+PE+OE+BRK+RXERR.B TXCNT JZ TXRET .B TXCNT MOV. Buffer output? .&URCTL JNZ RCERR DEC. To next buffer byte . No. status is 0 .. only for the transmit part . Active Mode after RETI . Interrupt Handlers . proceed PLPM3 NXTTX . Interrupt handler for the UART Receive part. Buffer filled? . . buffer is empty . Yes . . Active Mode after RETI .B &URXBUF. No. Reset vector . JMP . Next byte to buffer . Byte count –1 . Back to LPM3 BIT. USART Interrupt vectors .B @R6+.B #RXERR. Other handlers? .Software Routines JZ . RETI RCRET #CPUoff+SCI1+SCI0. Interrupt handler for the UART Transmit part. Interrupt vectors . Transmit vector .0FFECh TXINT RCINT ”INITVEC”. Byte count –1 .&URCTL.0(R7) INC R7 TST.0(SP) . No. Error handling BIC.0FFFEh INIT #CPUoff+SCI1+SCI0. Reception allowed? .. prepare next characters . Clear error flags RETI .B TXCNT JNZ TXRET BIC TXRET RETI .B RCCNT JZ RCRET . . Next byte for output . sect word word sect word ”SCIVEC”.B RCCNT MOV..

MCLK > 3.&SCFI0 . FN_2 on .if FLLMPY < 48 . Yes. otherwise Vcc was switched on: complete initialization . .B #FN_3. 3.&SCFQCTL .&SCFI0 . 2.MACROs used in the previous examples. Define “initialized state” MOV. and waits 30.if MOV. Yes.B #FN_2. Check the INITKEY value first: .1 Subroutines The initialization subroutine INITSR—which is explained in detail in the MSP430 Application Report—first checks if a power-up clear (PUC).else . otherwise.5MHz? . Common Initialization Subroutine . 1.endif .else .5MHz < MCLK < 3.3 Subroutines and . the power-up clear state is assumed.MACROs This section contains the subroutines and assembler .endif . continue program .Software Routines 3. the RAM is cleared. or a power-on reset (POR) event has taken place: • Power-Up Clear: the supply voltage is switched on. The subroutine selects the correct current switch FN_x for the system clock generator. MCLK < 1. Restart completely: clear RAM .&SCFI0 . Use the right DCO current: .B #FN_4. If value is 0F05Ah: a reset occurred. Key is ok.5MHz? .5MHz < MCLK < 2. If it contains 0F05Ah. INITSR CMP JEQ CALL MOV .INITKEY . 20 .else MOV.&SCFI0 . Define MCLK frequency #0F05Ah.if FLLMPY < 80 . .5MHz: FN_4 on SLAA049 .INITKEY IN0 #RAMCLR #0F05Ah.B #FLLMPY–1.000 clock cycles to ensure that it has locked to the correct oscillator tap. • Power-On Reset: a reset occurred (RST/NMI-pin or by watchdog). FLLMPY < 112 . PUC or POR? .B #0. These two situations differ by the content of the INITKEY word.5MHz: FN_x off MOV. FN_3 on MOV. IN0 . the RAM is not changed.endif .3. RAM is not cleared . the power-on reset state is assumed.

. Prepare index register .2 . .0200h 0200h 05FEh . during 30000 cycles . CUBR1.equ .mnolist .bss RAMSTRT RAMEND .xxxxxxx . Modulation Register content: the rounded fraction of .3.equ . . RAMCLR RCL CLR CLR INCD CMP JLO RET R5 RAMSTRT(R5) R5 RCL .macro . High (UARTCLK/Baudr)–256*CUBR1 . No.MACROs The two following software macros calculate the best-fit values of the UART baud-rate generator. Output: CUMCTL . 8–bit UMCTL register value MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 21 . Baud Rate Reg.R5 . Return from initialization #RAMEND–RAMSTRT+2. CALC_UMCTL .Software Routines MOV IN1 DEC JNZ RET . Allow the FLL to settle . CALC_UBR CUBR1 CUBR0 . and CUMCTL. UBR0. and UMCTL. RAM cleared? 3. . once more .equ . Inputs: UARTCLK. 0F05Ah: initialized state . Subroutine for clearing of the RAM block . Next word address . . . .endm UARTCLK/(Baudr*256) . Seven bits of resolution are used. Frequencies [Hz] . The values for the modulation registers UBR1/UBR0 are . CMOD = UARTCLK/Baudr is calculated . at the correct DCO tap . calculated: CUBR1 and CUBR0 contain the truncated result . Low . Binary format of CMOD: 0. Highest RAM address (33x) #10000. . Yes.R5 R5 IN1 . Then the 8 bits of UMCTL are built. return . Do not list macro calls The calculation of the modulation register UMCTL content follows. Start of RAM . used during initialization of UART registers UBR1. They do not use ROM or RAM. Baud Rate Reg. of the UARTCLK/Baudr division.macro . and they define the three variables. CUBR0.equ INITKEY. Baudr . 1st RAM address .2.

if M$20 C$1 . Overflow to integer? .000000 .equ .equ . add fraction . UMCTL.equ . Overflow to integer? .1 = 1 M$00+CMOD 0 .equ . UMCTL.2 = 0 M$20>127 M$20–128+CMOD 4 . UMCTL.equ .else M$10 C$0 . No.if M$10 C$0 .equ .equ . UMCTL.0 = 1 SLAA049 .000000 . Yes. UMCTL.endif .Software Routines CMOD M$00 .000000 . Yes. subtract 1. subtract 1. Yes. subtract 1. subtract 1. No. Fraction x 2 .else M$20 C$1 .else M$30 C$2 . No.4 = 1 M$30+CMOD 0 .3 = 1 M$20+CMOD 0 . Yes.000000 .equ .if M$30 C$2 .equ . UMCTL. add fraction . add fraction .equ .endif .equ . UMCTL.5 = 1 M$40+CMOD 0 . Yes. Overflow to integer? . add fraction .if M$40 C$3 M$40 C$3 . UMCTL.equ .equ .equ .equ . Overflow to integer? .000000 . No. No.if M$60 C$5 . Yes.equ .equ .000000 .equ . add fraction . subtract 1.equ .5 = 0 M$50>127 M$50–128+CMOD 20h . Overflow to integer? .endif .equ .3 = 0 M$30>127 M$30–128+CMOD 8 . UMCTL. subtract 1.1 = 0 M$10>127 M$10–128+CMOD 2 . add fraction .equ .2 = 1 M$10+CMOD 0 .4 = 0 M$40>127 M$40–128+CMOD 10h .equ . No. UMCTL. UMCTL.equ . UMCTL.if M$50 C$4 . Overflow to integer? .endif .equ M$50+CMOD 0 .endif .else M$60 C$5 22 .equ .equ .0 = 0 ((((256*UARTCLK)/Baudr)–256*(UARTCLK/Baudr))+1)/2 CMOD+CMOD M$00>127 M$00–128+CMOD 1 .else .else M$50 C$4 .

endif .equ . UMCTL.endif . Overflow to integer? .equ . subtract 1.else M$70 C$6 .Software Routines . Yes.else .if C$7 C$7 CUMCTL .7 = 0 M$70>127 80h .equ .equ .endif . UMCTL.7 = 1 M$60+CMOD 0 . Overflow to integer? .equ .000000 .endm C$7+C$6+C$5+C$4+C$3+C$2+C$1+C$0 .6 = 0 M$60>127 M$60–128+CMOD 40h .equ .if M$70 C$6 . add fraction .equ . No. UMCTL.6 = 1 MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface 23 . UMCTL. Add bits 0 .

1998. SLAAE10C 3. Literature No. Literature No. Literature No.References 4 References 1. MSP430 Family Architecture Guide and Module Library. 1996. SLAS163 24 SLAA049 . MSP430 Application Report. Data Sheet MSP430x33x. 1998. SLAUE10B 2.

equ .equ 003h 001h 002h .m0 .equ .equ . Modulation Control Reg. 1: Receive Error .equ 072h 001h 008h 010h 020h 040h 080h ..equ 073h 074h 075h 076h 077h . ME2 .equ . Transmit Intrpt Enable Bit IE2. 1: UART Mode . UCTL SWRST SYNC CHAR SP PEV PENA . .equ 071h 001h 008h 010h 020h . 1: Even Parity 0: SCI Mode 0: 7 Data Bits 0: 1 Stop Bit 0: Odd Parity . Baud Rate Register 1 .equ . .3: MCLK .1 . SFRs: Flags . Transmit Flag IFG2.equ . IE2 URXIE UTXIE .equ . SFRs: Mode Enable Bits A-1 . Receive Buffer . 1: all Char.equ . 1: 8 Data Bits .0 .equ . 1: Parity enabled 0: Parity dis.equ .equ . 1: Frame Error 0: No Error 0: only w/o Error 0: ok 0: ok 0: ok . Receive Control Register .equ 005h .equ 001h 001h 002h . UTCTL TXEPT URXSE SSEL0 SSEL1 . which is a predefined symbol of the MSP430 assembler for the system Stack pointer (SP). except for the stop bit definition (SP). 1: Software Reset 0: Run . 1: Transmitter empty . . IFG2 URXIFG UTXIFG . 1: Break detected 0: ok MSP430 Universal Synchronous Asynchronous Receive/Transmit Communication Interface .equ 070h 001h 004h 010h 020h 040h 080h .0 . 1: Overrun Error .1 .equ .equ . 1: Parity Error .equ . USART Control Register . Receive Intrpt Enable Bit IE2.equ .equ . Receive Flag IFG2. 1: 2 Stop Bits . 1: ACLK 0: Ext. Baud Rate Register 0 . Clock Selection .equ .equ .Definitions Appendix A Definitions The abbreviations used in the hardware definitions are in conformance with the Architecture User’s Guide. HARDWARE DEFINITIONS . Transmit Control Register .equ .equ . m7.equ . SFRs: Interrupt Enable Bits . Transmit Buffer .equ . URCTL RXERR URXEIE BRK OE PE FE . Clock 2. UMCTL UBR0 UBR1 URXBUF UTXBUF .equ . .equ .

0 .equ 080h 040h 010h 008h . Transmitter Mod. Switch for 2 MHz .equ 052h 050h 004h 008h 010h .equ .equ .equ . Switch for 3 MHz . Reg.equ . Transmit Output P4. SCG1 SCG0 CPUoff GIE .equ 001h 002h .equ 01Fh 080h 040h . FLL multiplier and M bit . Receiver Module Enable Bit ME2. Low Power Mode bit 0 .7 . Receive Input P4. Switches CPU off .equ .1 A-2 SLAA049 .6 . Enable Bit ME2.equ . Port4 Sel.equ . (I/O <–> USART) .equ . Switch for 4 MHz . P4SEL URXD UTXD .Definitions URXE UTXE . SCFQCTL SCFI0 FN_2 FN_3 FN_4 . General Interrupt Enable Bit .equ . Low Power Mode bit 1 . FLL current switches .equ .

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