80286

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References 

Advanced Microprocessors and Peripherals : A K Ray (Chapter 9: page 444) The Intel Microprocessors: Barry B Brey 

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80286
The second generation of 16-bit micro processors  Released in 1982 by Intel  68 pin IC  First microprocessor with memory management and protection abilities  It has 24-bit address bus  Able to address 16MB of memory and 1GB of virtual memory 

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5 MHz. 10 MHz and 8 MHz clock frequencies  Upwardly compatible with the instruction set of 8086  First CPU to incorporate the integrated memory management unit(MMU)  Functions of MMU:  Memory Management  Data protection or Unauthorized access prevention   First processor that support virtual memory 5/31/2011 4 .Various versions of 80286 are available that run on 12.

Virtual Memory  80286 can address 1 GB of virtual memory  The concept of virtual memory is implemented using physical memory that the CPU can directly access and secondary memory that is used as a storage for data and program  Virtual memory doesn¶t exist physically in a system 5/31/2011 5 .

The program may be divided into a set of segments  At any instant. exists in the physical memory at the time of execution  The segments of the program which have been already executed or are not required for execution at that instant. are available in the secondary memory  5/31/2011 6 . a segment portion of actual program required for execution at that instant.

This is called as swapping in of the program  A portion of the program or important partial results required for further execution. it is fetched from the secondary memory and placed in the physical memory. This is called as swapping out of the program  5/31/2011 7 . may be saved back on secondary storage to make the physical memory free for further execution of another required portion of the program.Whenever the portion of a program is required for execution by the CPU.

 Swapping In (Swapping) Secondary memory  Swapping Out (Un Swapping) Secondary memory 5/31/2011 8 .

80286.Internal Architecture 5/31/2011 9 .

BP. SP. BX. SI. DX. DI)    Four 16 bit segment registers Status and control registers (Flag Resgister) Instruction Pointer 5/31/2011 10 .Register Organisation  80286 contains almost the same set of registers as in 8086  Eight 16 bit general purpose registers (AX.80286. CX.

80286.Register Organisation AH BH CH DH AL BL CL DL BP SI DI SP CS DS SS ES General purpose registers Segment Registers 5/31/2011 11 .

80286.Internal Block Diagram  Contains 4 functional parts: 1) Address Unit(AU) 2) Bus Unit (BU) 3) Instruction Unit (IU) 4) Execution Unit (EU) 5/31/2011 12 .

80286 Internal Block Diagram 5/31/2011 13 .

Address Unit(AU) :   Responsible for calculating the physical address of instructions and data that the CPU wants to access Address lines derived by this unit may be used to address different peripherals 5/31/2011 14 .

Bus Unit (BU) : Physical address computed by AU is handed over to BU  BU transmit this physical address over the address bus A0 ± A23  BU fetch instruction bytes from memory  When one instruction is getting executed. decoded and kept ready for execution (instruction pipelining)  This task is done by the prefetcher module in the Bus Unit  These fetched instructions are arranged in a 6 5/31/2011 byte prefetch queue  15 . the subsequent instruction is prefetched.

Instruction Unit (IU) :   IU accepts instructions from the prefetch queue and an instruction decoder decodes them one by one The decoded instructions are stored in a decoded instruction queue 5/31/2011 16 .

which carries out all the arithmetic and logical operations and sends the results either over the data bus or back to the register bank 5/31/2011 17 .Execution Unit (EU) :     Output of decoding circuit drives a control circuit in EU It is responsible for executing the instructions received frm the decoded instruction queue EU contains the register bank and ALU ALU is the heart of EU.

80286 ± Operating Modes 5/31/2011 18 .

Operating Modes  80286 works in two operating mode Real Address Mode Protected Virtual Address Mode 5/31/2011 19 .

Real Addressing Mode Just act as a fast 8086.  Instruction set is upward compatible with that of 8086  80286 only address 1Mbytes of physical memory using A0.A19 in Real address mode  Lines A20-A23 are not used  5/31/2011 20 .

Real Addressing Mode ± Address Calculation 5/31/2011 21 .

 The 80286 reserves two fixed areas of physical memory for System Initialization (FFFF0H to FFFFFH) Interrupt Vector Table (00000H to 003FFH) 5/31/2011 22 .

Protected Virtual Address Mode (PVAM) The first processor to support the concepts of virtual memory  Swapping and Unswapping  Able to address 1 GB of virtual memory  5/31/2011 23 .

which contains the information regarding the segment  A set of such descriptors arranged in a proper sequence describes the complete program  5/31/2011 24 . for the complete execution of program  A data structure called descriptor is associated with this segment.Large programs are divided into smaller segments which are arranged in appropriate sequence and are swapped in or out of primary memory as per the requirements.

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How it works? 5/31/2011 26 .

Descriptors .

Descriptors Large programs are divided into smaller segments which are arranged in appropriate sequence and are swapped in or out of primary memory as per the requirements. which contains the information regarding the segment  A set of such descriptors arranged in a proper sequence describes the complete program  5/31/2011 28 . for the complete execution of program  A data structure called descriptor is associated with this segment.

  It carry all relevant information regarding a segment and its access rights. like Segment base address Segment limit Segment type Privilege level Segment availability in physical memory Descriptor type Segment use by another task The set of descriptors is called as descriptor table 5/31/2011 29  Each descriptor is 8 bytes long  . The descriptor contains information of a segment.

Descriptor Types  Types of descriptors: Segment Descriptors System Control Descriptors 5/31/2011 30 .

Segment Descriptors For code. stack and data segments  Code segment descriptors are used to refer code segment  Data segment descriptors are used to refer data segment  5/31/2011 31 .

 Contains 16 bit segment limit 24 bit segment base address 8 bit access byte rights Remaining 16 bits are reserved by Intel for future use and compatibility with future processors INTEL RESERVED P DPL S TYPE A BASE(16-23) BASE(0-15) LIMIT(0-15) 5/31/2011 32 .

 8 bit access byte rights (Refer Page: 458 ) P DPL S E TYPE A  P (Present) Used to indicate whether segment is available in physical memory P=1 Segment is mapped into physical memory  P=0 No mapping to physical memory   DPL (Descriptor Privilege Level) Defines the range of privilege level  S (Segment Descriptor) S=1 Code/Data/Stack Descriptor  S=0 System Segment ( Gate) Descriptor  33 5/31/2011 .

 E (Executable) Used to distinguish between code & data segments E=0  E=1  Data Segment Code Segment  A (Accessed) A indicates whether it is accessed previously or not 5/31/2011 34 .

System Segment Descriptors Used by 80286 to store system data and execution state of a task (for multitasking systems)  System segment descriptors are of 7 types  The types 1-3 are called system descriptors The types 4-7 are called gate descriptors 5/31/2011 35 .

Busy Task State Segment 36    5/31/2011 .System Descriptors  This descriptor contains 16-bit segment limit 24-bit segment base address Access byte right contains  P-bit  2-bit DPL  S-bit(0)  type field  Last word of the descriptor is reserved by the Intel.Local descriptor table Type 3. Type 1 ± Available Task State Segment(TSS) Type 2.

Gate Descriptors The gate descriptors control the access to entry points of the code to be executed  Contains the information regarding  The destination of the control transfer Required stack manipulations Whether it is present in the physical memory or not Privilege level Type 5/31/2011 37 .

 Hence CPU can perform protection checks and controls the entry points of the destination code  There are four types of gate descriptors  Call gate Task gate Interrupt gate Trap gate 5/31/2011 38 .Gate descriptors provide mechanism to keep track of source and destination of control transfer.

Interrupt and trap gates are used to specify the corresponding routines. Refer Gate Descriptor format (page: 460) 5/31/2011 39 .    Call gates are used to alter the privilege Task gates are used to switch from one task to another.

Descriptors Segment Descriptors System Control Descriptors Code Segment descriptors Data Segment descriptors Stack Segment descriptors System Descriptors Type 1 Type 2 Interrupt Gate Type 3 5/31/2011 Gate Descriptors Call Gate Task Gate Trap Gate 40 .

Segment Descriptor Cache registers The concept of caching was introduced in 80286  Caching is a method to minimize the time required for fetching the frequently required descriptor information from the memory  Caching is the process of maintaining the most frequently required data for execution in a high speed memory called cache memory  5/31/2011 41 .

    6-byte segment descriptor cache register is assigned to each of the four segments A segment descriptor is automatically loaded in a segment descriptor cache register. all the information regarding the segment is obtained from the cache register instead of referring to the main memory for the descriptor again and again These cache registers are not available for programming 5/31/2011 42 . whenever the associated segment register is loaded Once a cache register is loaded.

Program/Visible Segment Selectors CS DS SS ES 15 0 Segment Registers (loaded by program) 5/31/2011 43 .

Program Invisible Access Rights Segment Size Segment Physical Base Address 47 40 30 16 15 0 Segment Descriptor Cache Registers (Automatically loaded by CPU) 5/31/2011 44 .

Selector Fields In protected mode the contents of segment register is called selectors  16-bit  5/31/2011 45 .

Table Indicator TI=0 : GDT TI=1: LDT  Index ± Descriptor base  .RPL (Requested Privilege Level). refers the privilege of that segment.  TI.

Descriptor Tables The array of descriptors is called as descriptor table  Upper 13bits of selector field points to a particular entry in the descriptor table  Descriptor Table Types  Local Descriptor Table (LDT) Global Descriptor Table (GDT) Interrupt Descriptor Table (IDT) 5/31/2011 47 .

Local and Global Descriptor Table
A Global Descriptor Table (GDT) contains global descriptors common for all the tasks  A Local Descriptor Table (LDT) contains descriptor specific to a particular task  All the tasks may have their private LDTs 

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A segment cannot be accessed, if its descriptor does not exist in either LDT or GDT.  LGDT (Load Global Descriptor Table) and LLDT (Load Local Descriptor Table) Instructions are used to load the base and limit fields of GDT and LDT 

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Interrupt Descriptor Table
IDT is used to store interrupt gates and trap gates  LIDT instruction is used to Load Interrupt Descriptor table. 

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Privilege .

 Level 0 is the highest privilege level  Level 3 is the lowest privilege level.PRIVILEGE Supports four level hierarchical privilege mechanism to control the access to descriptors and hence to the corresponding segments of the task.  5/31/2011 52 .

Privilege Types Task Privilege  Descriptor Privilege  Selector Privilege  .

Task Privilege      Each task assigned a privilege level. Once CPL is selected. it cannot be changed during the execution normally in a single code segment 54 5/31/2011 . which indicate the priority or privilege of that task Any one of the four privilege level may used to execute a task The task privilege level at that instant is called the current privilege level (CPL) The CPL is defined by the lower order 2-bits of CS register for an executable segment.

the most privileged level. to a new segment  A task executing at level 0. the least privileged level. can access all the data segment defined in GDT and LDT of the task  A task executing at level 3. will have the most limited access to data and other descriptors  5/31/2011 55 . using gate descriptors.It can only changed by transferring the control.

Descriptor Privilege   The descriptor privilege is specified by the DPL field of the access rights byte. The DPL specifies the least privilege level that may be used to refer the descriptor. 5/31/2011 56 .

Selector Privilege     This privilege is specified by the RPL field of the segment register (selector) A selector may use a less trusted privilege than the current privilege level for further use. This is called the effective privilege level (EPL) of the task. RPL is used to ensure that the pointer parameter passed to a more privileged procedure are not given the access of data at privilege higher than the caller routine. 57 5/31/2011 .

Protection .

Protection  1. Restricted access to Segment: This is accomplished using descriptor usages limitations and the rules of privilege check. ie DPL. 2.CPL 59 5/31/2011 . The 80286 supports the following three basic mechanism to provide protection Restricted use of segments: The segment usages are restricted by classifying the corresponding descriptors under LDT and GDT.

5/31/2011 60 .Protection 3 . Privileged Instructions or Operations: These are to be executed or carried out at certain privilege levels determined by CPL and I/O privilege level (IOPL) as defined by flag register.

trigonometric and logarithmic calculations 5/31/2011 61 . floating point. BCD.80287 Math Coprocessor    Numeric data coprocessor specially designed to operate with 80286 80287 adds nearly 70 more instructions to the instruction set of 80286 80287 offers an instruction set that supports integer.

Questions? 5/31/2011 62 .

30 pm on 4/04/2011 ) 5/31/2011 63 .Assignment 2   Features of Pentium processors Brief study of latest processors of Intel & AMD (Submit before 1.

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