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UC1840 UC2840 UC3840

PROGRAMMABLE, OFF-LINE, PWM CONTROLLER
• ALL CONTROL, DRIVING, MONITORING, AND PROTECTION FUNCTIONS INCLUDED • LOW-CURRENT, OFF-LINE START CIRCUIT • FEED-FORWARD LINE REGULATION OVER 4 TO 1 INPUT RANGE • PWM LATCH FOR SINGLE PULSE PER PERIOD • PULSE-BY-PULSE CURRENT LIMITING PLUS SHUTDOWN FOR OVER-CURRENT FAULT • NO START-UP OR SHUTDOWN TRANSIENTS • SLOW TURN-ON AND MAXIMUM DUTY-CYCLE CLAMP • SHUTDOWN UPON OVER-OR UNDERVOLTAGE SENSING • LATCH OFF OR CONTINUOUS RETRY AFTER FAULT • REMOTE, PULSE-COMMANDABLE START/ STOP • PWM OUTPUT SWITCH USABLE TO 1A PEAK CURRENT • 1% REFERENCE ACCURACY • 500 kHz OPERATION

DIP-18 (Plastic and Ceramic)

DESCRIPTION Although containing most of the features required by all types of switching power supply controllers, the UC1840 family has been optimized for highlyefficient boot-strapped primaryside operation in forward or flyback power converters. Two important features for this mode are a starting circuit which requires little current from the primary input voltage and feed-forward control for constant volt-second operation over a wide input voltage range. In addition to startup and normal regulating PWM functions, these devices ofter built-in protection from over-voltage, under-voltage, and over-current fault conditions. This monitoring circuitry contains the added features that any fault will initiate a complete shutdown with provisions for either latch off or automatic restart. In the latch-off mode, the controller may be started and stopped with external pulsed or steady-state commands.
September 1988

Other performance features of these devices include a 1% accurate reference, provision for slowturn-on and duty-cycle limiting, and highspeed pulse-by-pulse current limiting in addition to current fault shutdown. The UC1840's PWM output stage includes a latch to insure only a single pulse per period and is designed to optimize the turn off of an external switching device by conducting during the "OFF" time with a capability for both high peak current and low saturation Voltage. These devices are available in an 18pin dual-in-line plastic or ceramic package. The UC1840 is characterized for operation over the full military temperature range of -55C to +125C. The UC2840 and UC3840 are designed for operation from -25 C to +85 C and OC to +70C, respectively.
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0.fHI 1l'J INV INPUT ov STOP SENSE " . (pin 15) Voltage Driven Current Driven 100 mA Maximum PWM Output Vol age (pin 12) PWM Output Current. 7) Comparator Inputs (pins 2. 17. \() Sf NC)f : " f. 4." flfl.50 20 10 ..Vj SUPPLY Type UC1840 UC2840 UC3840 Plastic UC2840N UC3840N Ceramic UC1840J UC2840J UC3840J r?( s r r CUI~Il[NT O!~I"'U{ mAS HH1[SHOLD rU.65 to + 150 "C DATA Thermal Resistance Junction-ambient Max 80 2/10 1096 n III . THERMAL Storage Temperature .55 to + 125 .'lNS[ OUH'UT '.UC1840-UC2840-UC3840 PIN CONNECTION AND ORDER CODES (OMP(NSATION ~'''l ~I " NO N INV INPUT <)Tt\. Steady-state (pin 12) 32 Self Limiting 40 400 20 -200 . Sense Current (pin 11) Current Limit Inputs (pin 6. 5. qE FI PWM Output Peak Energy Discharge Driver Bias Current (pin 14) Reference Outpul Current (prn 16) Slow Start Sink Current (pin 8) V. MAXIMUM RATINGS Parameter Test Conditions Unit V V mA ~J mA mA mA mA V V mW °C Supply Voltage + V.55 to + 150 Vo 10 Eop I.HlrNl 'J 'I PWM [.!IOUND ~. 18) Power Dissipation Junction Operating at T amb = 70 "C Range Range : UC1840 UC2840 UC3840 PIOI TJ Top Temperature Ambient Temperature .3 to + 32 1000 ..5 to + 55 .0.c'<.-:)W 1111 ( 'JTAlll v."'IP ABSOLUTE Symbol V. 3.25 to + 85 to + 70 o "C "C -c r.

-Transistor capable of sinking current to ground wlch IS off dUring the PWM on-time and turns on to terminate the power pulse. or the error latch. Current capacity IS 400 mA saturated with peak capacitance discharge in excess of one amp 3/10 1097 n III . PWM OUTPUT SWITCH Terminates the PWM output pulse when set by Inputs for either the PWM comparator. tJ"'~ FUNCTIONAL ---~ .UC1840"UC2840-UC3840 BLOCK DIAGRAM '--"--~~- ~~--@RAMP RT/ey ®------- co. tOO mA maximum Generates output pulse w. the pulse-by-pulse current limit comparator. '0 PWM COMPARATOR PWM LATCH of clock pulse and ends when Inputs.2). unity-gain stable.~8>--DESCRIPTION Name L __ s ..-----------~J .0 V reference for Internal usage only with nominal 40 V clamp zener for chip O. Precision 5. \I (LA~ -® GROUNO DuT" ~~\:'' CYClE at SEN~'f ~. CR terminal can be used as an input port for current ERROR AMPLIFIER REFERENCE GENERATOR Conventional operaltonal amplifier for closed-loop Low output impedance.'~ CO".0 V for Internal and external usage to 50 mA. Tracking 3.p INY. mode control.ch starts at termination the ramp Input crosses the lowest of two positive accuracy current of :! 2 0.3 log (CT x 10. SlQP 0--- '". ---- Kc where Kc is a first-order factor RAMP GENERATOR Develops dv a linear ramp with a slope defined C R IS normally externally < by = sensevo!taSjIJ selected C T and dt RR CR its value will have some effect upon valley voltage. V protection. .LINPVT STARt/IN 'NT -. Function Generates a fixed-frequency Internal clock from an external correction R T and C T PWM CONTROL OSCILLATOR Frequency = RTCT 0. Resets wicn each Internal clock pulse.INPUT N. gain and phase compensation.10 'I. ~1 r. REf RUE'l EXT.

V. 4110 1098 Dill . by RsCs --- Supplies drive current to external power switch to provide turn-on Clamps low to hold PWM OFF_ Upon release. high c. it generates a U. FUNCTIONS V. Inputs to Error Latch are: a. U. V fault. allowing a restart. low threshold. V. this latch insures no reset signal to either Start or Error latches so that first fault will lock the PWM off. V. this latch resets the Start and Error latches at the U. When set. . Keeps low input voltage at initial turn-on at start level to monitor for U. fault. When sense voltage rises to 400 mV above threshold. this latch insures immediate hold off until reset. DRIVE SWITCH DRIVE BIAS SLOW START low. V. With an Increasing voltage. it also resets the Error Latch if the Reset Latch has been set. rises with rate controlled for slow increase of output pulse width. SENSE This comparator performs three functions. Also used to clamp maximum duty cycle with divider Rs Roc. At the U.---------------------- UC1840-UC2840-UC3840 DESCRIPTION (continued) ------_-------- --------- FUNCTIONAL Name Function SEQUENCING START/U. Disables most of the chip to hold internal current consumption Bias OFF. V low (after turn-on) b. V_ fault signal at a lower level separated by a 200 I1A hysteresis current. threshold if Reset Latch is set. and Driver bias. it generates a turn-on signal at a start threshold With a decreasing voltage. Current Sense 400 mV over threshold Error Latch resets at U. PROTECTION FUNCTIONS When set by momentary input. PWM shutdown and ERROR LATCH CURRENT LIMITING Differential input comparator terminates Individual output pulses each time sense voltage rises above threshold. until input voltage reaches start threshold. Step low d. threshold. from being defined START LATCH as a U. 0 V. Sets RESET LATCH When reset. a shutdown signal it sent to Error Latch.

0. Temp. UC3840 Min. Temp.9 0. .= 30 V.7 4.UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (refer to the test circuit.5 53 45 50 0.9 . Range RT = 2 Kn.1 10 40 5. Pin 2 = 3. Range V REF = O..5 4. CR = 0.8 500 500 ± 0.0.C.1 20 30 ± 0.11 . = 8 to 30 V ---------------------_ . = 8 to 30 V Over Op.3 3. = 20 m A 5 33 10 40 -----_--------- __ V_so_v_~ Supply O.v.2 -14 !lA mA Ramp Current Ramp Valley 0. Clamp 48 V REFERENCE SECTION ------~---------- VREF :. - 4.95 0. Unit POWER INPUTS 1ST _____ __ Start-up Current T.5 V V Ramp Peak --.11 -0. __ Ty~. these specifications apply for T.9 5 10 10 5. = . = 30 V. UC1840 UC2840 Typ. Pin 2 =2. Max.1 5. mV/oC mA Short Circuit Curro .5 4.Gil •I.8 Maxim.10 !lA ISENSE = 1 mA . Max. V.001 ~F.--------------- Min.5 TI = 25 -c V. = 20 V. SGS·THOMSON I>lfl(._ Max.2 .4 4.>VREF :'>VREF/:'>r lsc Reference Voltage - Line Regulation Load Regulation Temperature __ TI = 25 'C V. TI = 25 'C V.100 OSCILLATOR ----------------- fs Nominal Voltage Frequency Stability Coeff.05 15 20 ± 0. RT = 20 KQ.2 15 45 5 33 4 .4 V mV mV IL = 0 to 20mA Over Op.5 V O~p_e_ra_ti_ng~C_u_rr_e_nt V_.0.3 Clamping Level 3. CT = 0. CT = 330 pF 47 50 0.0.55 to + 125 'C for the UC1840.5 .5 0.i'I@~~~Ii:1r~@~!IG$ ----------- 5il0 1099 n--- III .5 55 KHz % %I'C 'Temperature fs(ma)(j ± 0.14 -0.95 0.25 'C to + 85 'C for the UC2840 and 0 to + 70 'C for the UC3840.0.100 . Frequency KHz RAMP GENERATOR Ramp Current .9 .7 4.0. 4 .9 0. TI = 25 'C Coeff. ISENSE = . V.2 15 mA %I'C mA 'S_t_ar_t-up Current V.95 5 10 10 5. =30 V.80 .001 ~F.>VREF :. Unless otherwise stated. Pin 2 = 2. current limit threshold = 200 mV) Symbol Parameter __________________ Test Conditions M_in.5 .80 .5 V I.

7 0.2 2.5 2 1 10 5 0.4 2.2 1.10 70 40 80 50 -4 -10 dB dB mA MHz V/~S Supply Voltage Rejection Short Circuit Current Gain Bandwidth Slew Rate B' SA' 1 2 0.5 V V.1 0.1 0. PWM SECTION "Continuous Duty Cycle Range (other than zero) Vo(san Vo(sa!) Min.5 to 5.1 300 95 0.2 0.2 1.2 10 500 % V V ~IA ns Output Saturation 10 =20 mA 10 = 200 mA Vo = 40 V Pin 8 to pin 12 T I = 25°C. RI = 1 Output Saturation Output Leakage Delay _!Ol Cd 'Comparator KIl SEQUENCING VT FUNCTIONS Pins 2.8 1 2 0.5 0.1 300 95 0. T.1 -10 0.0.5 VCM = 5 V 0. 4.1 2 Input Leakage Driver Bias Saturation Voltage V. = 25 'C Vi = 20 V IB=-50mA 120 -3 240 10 120 180 0.5 2 ~IA V >tA 6/10 1100 n III .2 -3 240 10 3 V ~A ~A ~IA V ------ 10 Input Bias Current Start!UV Current Hysteresis Pins 3. Range Ramp Peak < 4. 5 = OV Pin 2 = 2.1 2 180 0.3 66 3. Symbol Parameter Test Conditions Min.2 0.5 mV ~A ~A dB V v.5 60 0.1 .5 5 2 0.8 3 -1 3.2 10 500 5 0..3 66 3.UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (continued) UC1840 UC2840 UC3840 Min.8 T.N-VOH Driver Bias Leakage Slow-start Slo~-start Saturation Leakage 3 VB = OV Is = 2 mA Vs = 4. -r Typ. Gv =0 dB Gv = 0 dB 70 40 80 50 -4 . = 25 'C. I Max.10 0. 4. I Max.7 0. Ib los Gv CMR SVR lsc Common Rejection Mode VCM = 1. 5 ---_.5 V. Comparator Threshold 2. = 8 to 30 V V camp T. 3.5 2 .5 V . Unit ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain Output Swing (max Out s Ramp Peak 100 mY) .4 2. =25 = OV "C.0.1Vo=lto3V Minimum Total Range 60 0.2 V 5 0.8 3 -1 3. Total Cant.1 Typ.

HI 6 7 -t[-~ I 48 tUl 2K 43 KO n ~°EtRRENT TEST SENSE Nominal frequency ~ Start voltage ~ 3 (R1 +R2 +~~ R2 + R3 ~ 50 kHz + 0. Unit I Typ.0 RESET R3 N_I Cfl{-} C/L{+-) 5L. ~___. I Max. Pin 7 to 12 RL ~ 1 Kl2 200 340 0 400 -2 5 440 340 0 400 -2 . CURRENT CONTROL Current Current Offset Ib Limit Offset Shutdown Pin 7 ~ OV .0. fault voltage ~ 3 --R3--Current limit ~ 200mV (R1 + R2 + R3) ~ 32 V uv.. Figure 1 : Open Loop Test Circuit.....2 R1 ~ 12 V Ov._-· .UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. I Max. Not 100 % tested in production. UC1840 UC2840 UC3840 Min.0. UC1840 RI GNO 1]1-----.3 TJ ~ 25 "C.3 200 10 440 mV mV Input Bias Current "Common Range mode -5 3 400 -5 3 400 "A V ns Td· Current Limit Delay • Guaranteed by desiqn. I Typ. fault Current fault voltage ~ 600mV Duty cycle clamp ~ 50% voltage ~ 3 (f'l_1_"':_ R2 +R3)_ ~ 8 V R2 + R3 7/10 1101 n III . SUPPlY VOLTAGE 1.

Figure 5 : PWM Output Minimum Pulse Width. VCE(sal I (V) "in=20V LOW DUTY-C'I'CLE PULSE JEST r-! 115 200 115 I---f-- Tj. G.: 10 20 ]0 50 lao 200 to (Io(. Figure 3 : PWM Output Saturation Voltage.L.S 10 ZEJlO BELOW VALUE iNDICATED) 10 0. . --~ov 60 40 J I 20 "a no roo IK lOOK 1M I (Hoz) 10K 8/10 1102 n III .5 03 O.~~ lao ~ I--: p:=' - I-"'" --r-- Tj rOc) 200 300 40010 {mAl Figure 4 : Oscillator Frequency.l 0. Hysteresis Current. /' 150 '" lOa ~V -50 -15 25 50 75 lQO !l! r.Hz) Figure 6 : Error Amplifier Open-loop Gain and Phase. (0'.) (PULSE WIDTH GOE.-S5°C Tj:25'C .V. (dBl Figure 7 : Shutdown Timing.UC1840-UC2840-UC3840 Figure 2: Start U.1 10 20 50 100 200 RT O([l..

DC INPUT LINE Figure 8 : Programmable ]~. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling . Control power is provided by RIN and CIN during start-up. and by a primary-referenced low voltage winding. Not shown are protective snubbers or additional interface circuitry which may be required by the choice of the high-voltage switch.8] complete control is maintained on the primary side. for efficient operation after start. The UC1840 will readily accept digital start/stop commands transmitted from the secondary side by means of optical couplers.UC1840-UC2840-UC3840 APPLICATION INFORMATION PWM Controller in a Simplified Flyback Regulator. N2.a task made even easier with the UC1840's feed-forward line regulation.~JIT ~I (0 1 ~NS I 0 -0 L__ In this application [see Fig.I . Os. or the application 9/10 1103 n III .

comparator and. results are the same for any fault Input which sets the Error Latch. M I N0 J a I I I I U R5 v . Although mput to External Stop.UC1840-UC2840-UC3840 Figure 9 : Power Sequencing Functions. must Normal Complete Cycle to Turn-on Reset Start and Error Latches Start Initiated U J K Error Latch Reset at U. V. Pin 4. Set Start Turns Still Set 0 P Q R S T Error Latch does not reset as Reset Latch is reset Error Latch Remain V c and Driver Bias Recycle with no Turn-on Reset Latch Set is Set with Momentary Reset Signal on Driver Bias Bus Error Latch G H V c and Driver Bias Continue Stop Command Removed to Cycle v . the voltaqe monitored by the start/U. Operating Event V c Rises with Light Load Driver Bias Loads V c Time L M N off Return to Normal Event Run State Reset Latch Set Signal Removed Error Latch Set with Momentary Fault PWM Regulates v. Notes: 1. Low Threshold. VC represents an analog of the output voltage generated by a pnrnary-retersnced secondary winding of the power transformer. STOP o I I E III HI I. VI. is shown. B C I nE I I HI III J MN III 0 a III R5 Vc (NOlEn DRIYER BIAS SlOWSTART PWM OUTPUT _--"UU'UUU EXT. rn most cases.V. Low Threshold Start Threshold Clam Now Removes Slow-start V Return to Normal Run State 10/10 1104 n III . It is POWER FREQUENCY FUNCTIONS Time A B C D E F Initial Turn-on. Stop Input Sets Error Latch Turning PWM U. V. Start Threshold. for the UC 1840 2. is the supply voltage.

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