2004 Feb.

陳獻文 國家晶片系統設計中心
03-5773693 ext.159 swchen@cic.org.tw

Douglas J Smith, “HDL Chip Design,” 1997. 林傳生, “使用VHDL電路設計語言之數位電 路設計,” 儒林, 1998. Mentor, “ModelSim SE Tutorial,” 2002.

Introduction CIC Design Flow VHDL Fundamentals
Structure Simulation Data Types Attribute Expression Hierarchy Generic

VHDL Syntax
Sequential Statements Concurrent Statements

Modeling logic circuits
Combinational Logic Sequential Logic Finite State Machine

Testbench Gate-Level Simulation


VHDL 2004.2


Very High Speed Integrated Circuit Hardware Description Language

The USA Department of Defense (DOD) project under the Very High Speed Integrated Circuit (VHSIC)


VHDL 2004.2


(1987) The F22 advanced tactical fighter aircraft S. IEEE standard 1076 . 1996 Both commercial simulation and synthesis tools became available adhering to IEEE 1076 '93 standard.1983 IBM.4 (VITAL) S.W.CHEN VHDL 2004. IEEE 1076.3 (NUMERIC_STD) IEEE 1076. A VHDL package for use with synthesis tools.CHEN VHDL 2004. Texas Instruments and Intermetrics.W. The DOD mandated that all digital electronic circuits be described in VHDL.2 1-4 .2 1-3 1993 IEEE 1076 '93.

2 1-5 Clear definition of design requirements Efficiency in design cycle time Reuse of designs and packages Technology independent Easy analysis of various architecture/implementations S.CHEN VHDL 2004.W.1997 VHDL-AMS(IEEE1076.W. analog.2 1-6 .1) supporting the description and simulation of digital.CHEN VHDL 2004. S. and mixed-signal systems in a single language.

W.W.CHEN VHDL 2004.Design verification VHDL is recommended for government contracts VHDL commercial models are available for purchase VHDL is a documentation language VHDL is a simulation language S.2 1-7 Behavioral level of abstraction system algorithm RTL Logic Gate verilog VHDL vital HDL modeling capability S.2 1-8 .CHEN VHDL 2004.

IBM.Silicon Valley – Verilog Europe – VHDL Japan – Verilog Korea – 70-80% VHDL Taiwan S.VHDL Compilation Libraries Resuability Readability Compile Yes Package ADA Verilog interpretative No Include C & ADA Easy to Learn Less intuitive EASY S.W.2 1-10 . INTEL – VHDL USA .W. TI.2 1-9 USA . AT&T.CHEN VHDL 2004.CHEN VHDL 2004.

S.W.W.2 2-1 Artisan VHDL Gate Level model VHDL RTL Level ModelSim Design Compiler ModelSim co-simulation Verilog Gate Level Code Verilog in SE Schematic S.CHEN VHDL 2004.2 2-2 .CHEN VHDL 2004.

Define and verify the function operation for every block.W. Define and verify the operation for the whole of design. S.W.Partition design into several block. the use of a VHDL testbench Timing verification can be verify via adding violation checks in the simulation model. S.CHEN VHDL 2004. Define and verify the timing operation for every block.2 2-3 Functional verification have the following method: the use of simulator command files.2 2-4 .CHEN VHDL 2004.

2 3-2 .2 3-1 S.W.S.CHEN VHDL 2004.CHEN VHDL 2004.W.

CHEN VHDL 2004.S.the first two hyphens start the comment S.W.2 3-4 .processing of line is complete -----. -.W.2 3-3 Starts with two adjacent hyphens --. extends up to the end of the line.this line is comments end.CHEN VHDL 2004. -.

W. The last character of an identifier shall be not a underscore characters. An identifier shall be any sequence of letters (a-z.W.digits (0-9) and underscore characters (_). can’t have two adjacent underscore characters.CHEN VHDL 2004. S.CHEN VHDL 2004.Identifiers are used as names but can’t be reserved words. S.2 3-6 . The first character of an identifier must be a letter.2 3-5 Identifier shall be case insensitive. A-Z) .

3-8 .2 3-7 Entity I/O port spec. -.CHEN VHDL 2004.W.pragma translate_off & -.pragma translate_on Z <= A and B. -.2 choose a architecture to run simulation. of the block Entity Architecture function of the block can have more than one Arch1 (version 1) Arch2 (version 2) Configuration Package Package body S.-.pragma translate_on control the VHDL Compiler translation of VHDL code off & on. S.W.CHEN VHDL 2004.pragma translate_off Z <= string(“don’t translate”).

INOUT Connect with IN or OUT. B : in std_logic.W.2 3-10 .CHEN VHDL 2004. end nand2. A Z B NAND2 S.Entity NAND2 is port ( A : in std_logic. S. Z : out std_logic).CHEN VHDL 2004.W. BUFFER Connect with BUFFER only.2 3-9 IN Connect with OUT or INOUT. OUT Connect with IN or INOUT.




VHDL 2004.2




VHDL 2004.2


NAND2 architecture #1
Architecture STRUCT of NAND2 is signal I : std_logic; begin U0 : and2x1 port map(A, B, I); U1 : invx1 port map(I, Z); end STRUCT;


And I Inverter (and2x1) (invx1) U0 U1 NAND2



VHDL 2004.2


Architecture DATAFLOW of NAND2 is begin Z<=A nand B; -- concurrent statement end DATAFLOW;


VHDL 2004.2


Architecture RTL of NAND2 is begin process(A,B) begin if (A='1') and (B='1') then -- sequential statement Z<='0'; else Z<='1'; end if; end process; end RTL;
S.W.CHEN VHDL 2004.2 3-15

Configuration cfg_nand2 of NAND2 is for RTL end for; end cfg_nand2;



VHDL 2004.2


Entity a IS END a.W. S. END c.CHEN VHDL 2004.CHEN VHDL 2004.2 3-17 Package Declarations Package Bodies Constant Declarations Subprograms Type Declarations Component Declarations S.W.2 3-18 . CONFIGURATION c OF a IS FOR b END FOR. ARCHITECTURE b Of a IS BEGIN END b.

C: out BYTE.2 3-20 . END [a].W.. end component. S.W. S. constant BYTE_FF: BYTE:=255. END [a].CHEN VHDL 2004. signal ADDEND: NIBBLE. PACKAGE BODY a IS .. function MY_FUNCTION(A: in BYTE) return BYTE.B: in BYTE.CHEN VHDL 2004. OVERFLOW: out BOOLEAN).Package EXAMPLE is type BYTE is range 0 to 255. end [EXAMPLE].. component BYTE_ADDER port(A. subtype NIBBLE is BYTE range 0 to 15.2 3-19 PACKAGE a IS ..

CHEN VHDL 2004.2 3-22 .2 3-21 Working Library writable library (WORK) Resource Library Vendor supply (Synopsys) Standard library (IEEE) Cell library VHDL model (Artisan.W.W.Compass) S.Primary Units Entity Declaration Package Declaration Configuration Declaration Secondary Units Package Body Architecture Body S.CHEN VHDL 2004.

library IEEE. use WORK..std_logic_arith..Library WORK.ALL. architecture.W. . use IEEE.CHEN VHDL 2004.ALL.W.std_logic_signed. Altera MaxPlusII and Xilinx The work library is the folder that put main vhdl program. use IEEE..ALL. use IEEE.ALL..2 3-24 .ALL.std_logic_1164.ALL.std_logic_unsigned. entity.CHEN VHDL 2004.. use IEEE.numeric_std.EXAMPLE.2 3-23 ModelSim Map work library to other real folder. S. S. use IEEE.

library IEEE. ….CHEN VHDL 2004.W.2 3-25 S. signal a: signed(7 downto 0). ….all.CHEN VHDL 2004. signal a: std_logic. S.std_logic_arith.signal a: bit. signal a: bit_vector(3 downto 0). use ieee. library IEEE. use ieee.W.2 3-26 .std_logic_1164. signal a: std_logic_vector(0 to 3). signal a: unsigned(7 downto 0).all.

2 3-28 .CHEN VHDL 2004.ini work=work artisan_lib25=/cad2/lab/VHDL/modelsim/lib25 S../modelsim.W.ini [Library] others=$Model_TECH/.2 3-27 modelsim.CHEN VHDL 2004.S.W.

CHEN VHDL 2004..CHEN VHDL 2004.2 3-29 vsim& Commad space Workspace S.W.VHD Real Library (vlib) Map Library (vmap) Compiler (vcom) ModelSim Simulation (vsim) S.W.2 3-30 .

U1 U0 z: out std_logic). And I Inverter Z use artisan_lib25. NAND2 end nand2.W. begin U0: and2x1 port map (A. I).b: in std_logic. A library artisan_lib25. end STRUCT. architecture STRUCT of NAND2 is signal I : std_logic.CHEN VHDL 2004. U1: invx1 port map (I.all.prim. (and2x1) (invx1) entity nand2 is B port(a. S.2 3-31 Create Library vlib work Library mapping vmap work work VHDL Compilation vcom nand2.all.W.std_logic_1164.CHEN VHDL 2004. use ieee.Library IEEE.2 3-32 .vhd Simulation vsim test S. B. Z).


VHDL 2004.2


add wave a b z


VHDL 2004.2


simulation command
force a 0 force b 0 run 500 force a 0 force b 1 run 500 force a 1 force b 0 run 500 force a 1 force b 1 run 500


VHDL 2004.2


Write all command to nand2.do
do nand2.do


VHDL 2004.2


Simulation without testbench
Behavioral / gate-level VHDL design Simulator Commands (force,run, set trace) stimuli output Unit Under Test (UUT)



VHDL 2004.2


Simulation with testbench
Behavioral / gate-level VHDL design

Behavioral VHDL program Simulator Commands (run) Testbench

Unit Under Test (UUT)

stimuli output


VHDL 2004.2


CHEN VHDL 2004. Constant Holds one specific value of the specified type.W.W.2 3-40 . S. Often used to hold temporary values within a process or subprogram.S. Variable Holds any single value from the values of the specified type.CHEN VHDL 2004.2 3-39 Signal Describe a real wire in the circuit.

Assignment: data <= ‘1’. procedure. Signal Addr : bit_vector(31 downto 0). Constant .(process. Alias Secs : integer 0 to 59 is TimeSeconds. S. Variable TimeSeconds : integer range 0 to 59.to enhance readability Declaration: constant bitwidth : std_logic_vector (7 downto 0) := “01101110”.2 3-41 Declares an alternative name for an existing named object or part of an object. Variable . Alias Msb : bit_vector(15 downto 0) is Addr(31 downto16).Signal Declaration: signal data : std_logic :=‘0’ . function) Declaration: variable data : unsigned (0 to 2) := “000”. Alias Lsb : bit_vector(15 downto 0) is Addr(15 downto 0). S.2 3-42 .W.CHEN VHDL 2004. Assignment: data := “101”.CHEN VHDL 2004.W.

TYPE Bit IS ('0'.2 3-43 Enumeration TYPE std_ulogic IS ('U'.'Z'.'H'.only ‘X’.’1’.W.CHEN VHDL 2004.Leaf is the default data type.'1‘).'1'..'0'.'W'.CHEN VHDL 2004.’Z’ can be synthesized. S.’0’.2 3-44 .W.'L'. -. TYPES Scalar Composite Access File Enumeration Physical Numeric Record Array Bit Character Boolean Time Real Integer Bit Vector String Natural Positive TYPE type_name IS . S.'X'..'-‘ ). TYPE Boolean IS (FALSE. TRUE).

S. ns = 1000 ps.W.2 3-46 .CHEN VHDL 2004.2 3-45 Physical Type . integer range END UNITS. us = 1000 ns.Enumeration-predefined character bit boolean severity_level S.CHEN VHDL 2004.W.only use in simulation TYPE Time IS RANGE 0 to 2000000000 UNITS fs. ps = 1000 fs.

Physical Type
TYPE capacitance IS RANGE 0 to 2000000000 UNITS ff; pf=1000 ff; nf=1000 pf; uf=1000 nf; END UNITS;


VHDL 2004.2




VHDL 2004.2


Numeric Type
TYPE Byte IS RANGE 0 TO 255; TYPE Register IS RANGE 10#54.6# TO 10#67.3# ; <base>#<value>#e<value>


( 2 )10


VHDL 2004.2


Numeric Type-Predefined
integer real


VHDL 2004.2


for Enumeration

use in the FSM’s state

TYPE Colors IS (red, yellow, blue, green, black); SUBTYPE Primary IS Colors RANGE red TO blue ;

for Numeric
TYPE Integer IS RANGE -2147483647 TO +2147483647; SUBTYPE Natural IS Integer RANGE 0 TO Integer'HIGH ;


VHDL 2004.2


Natural Positive


VHDL 2004.2


Fraction: unsigned(23 downto 0).W. a.2 fraction 3-53 Record Type Use work. END RECORD.Record Type Package example Is TYPE FloatPointType IS RECORD Sign: std_logic.fraction<=(others=>‘0’).example.exponent<=“1011010”. S. end arch.2 3-54 . begin a.sign<=‘1’.all. a.CHEN exponenet VHDL 2004. sign S.W. Exponent: unsigned(6 downto 0).CHEN VHDL 2004. Architecture arch of xxx is signal a: FloatPointType. end.

CHEN VHDL 2004. Use array type signal a : Data_Bus. procedure) Constrained Declare array type TYPE Data_Bus is ARRAY ( 0 TO 31 ) OF Bit . 0 TO 3 ) OF Bit.2 3-56 .2 3-55 Array Type (in architecture.W. TYPE Dim_2 is ARRAY (0 TO 7. function.CHEN VHDL 2004. signal b : Dim_2. process.W.Record vs. a(23 downto 0)<=(others=>‘0’). S. begin a(31)<=‘1’. end arch. S. Array Architecture arch of xxx is signal a: std_logic_vector(31 downto 0). a(30 downto 24)<=“1011010”.

W.2 3-57 Model 1 type dim1 is array (7 downto 0) of bit_vector(7 downto 0).1) <= ‘0’. -.W. process. Model 2 type dim2 is array ( 7 downto 0. b(0.2 3-58 . S. Assignment: a(0)(7 downto 0) <= “00000000”.Array Type (in architecture. Use array type signal c : String(3 downto 1). procedure) Unconstrained Declare array type TYPE String is ARRAY (Positive Range <> ) OF Character. Assignment: b(0. S.CHEN VHDL 2004.0) <= ‘0’.7 downto 0) of bit. signal d : Bit_Vector(3 downto 0).7 downto 0) <= “00000000”. function. TYPE Bit_Vector is ARRAY (Natural Range<> ) OF Bit .CHEN VHDL 2004.Error b(0. signal a : dim1. signal b : dim2.

2 3-60 .CHEN VHDL 2004. nxt : data_ptr. S.W. temp. END RECORD. END PROCESS. head := temp. ELSIF (RW_DIR = '1') THEN D_OUT <= head. DEALLOCATE(temp). temp. head := temp.nxt := head.Only simulation Package example Is Type data_rec. S.W. end.data.nxt.delete temp END IF. TYPE data_rec IS RECORD data : std_logic_vector(7 downto 0).2 3-59 PROCESS (CLK) VARIABLE head: data_ptr := NULL. BEGIN IF CLK'EVENT AND CLK = '1' THEN IF (RW_DIR = '0') THEN --Write Mode temp := NEW data_rec. VARIABLE temp: data_ptr := NULL.CHEN VHDL 2004. temp := head. -.data := D_IN.Incomplete type Type data_ptr is Access data_rec. END IF. -.

VARIABLE l1. test).CHEN VHDL 2004. BEGIN lp1: WHILE NOT (ENDFILE(romdef)) LOOP 38 lp2: FOR j IN romdout'RANGE 49 LOOP READLINE(romdef. LINE BIT data S.l2 : LINE. l1). END LOOP lp1.data“. test).all.W. WHILE NOT ( ENDFILE(input_file) ) LOOP TEXT (File) READLINE(input_file.all. USE ieee. 38 49 56 77 romdef S.W. WRITELINE(output_file. VARIABLE test : std_logic_vector(7 downto 0). END rom_init. WRITE(l2.CHEN END LOOP.std_logic_textio.l). l2). romdout’Range END LOOP lp2.2 3-62 . FILE output_file : TEXT IS OUT "/dsk/vhdl/out.2 3-61 TYPE mem_data IS ARRAY (integer RANGE <>) OF integer. READ(l. VHDL 2004.romdout(j)).data“. VARIABLE romdout : OUT mem_data) IS VARIABLE l: line. PROCEDURE rom_init( VARIABLE romdef: IN TEXT. READ(l1.textio.USE std. FILE input_file : TEXT IS IN "/dsk/vhdl/in.

CHEN VHDL 2004.2 3-64 . S.ALL.USE std.data“. FILE output_file : TEXT open Write_Mode IS “out.2 3-63 S.data".W. FILE output_file : TEXT open Append_Mode IS "out.textio.CHEN VHDL 2004. FILE input_file : TEXT open Read_Mode IS "in.data“.W.

W. SAT).2 3-66 . THU.CHEN VHDL 2004.W. S. WED.CHEN VHDL 2004. byte’high=7 T’LOW week’low=SUN. count’high=63. FRI. byte’low=0 TYPE week IS (SUN. TYPE count IS INTEGER RANGE 0 to 63. count’low=0. TYPE byte IS ARRAY (7 downto 0) of STD_LOGIC. TUE.2 3-65 T’HIGH week’high=SAT.S. MON.

-.W. TUE. Signal Y : unsigned (3 downt 0).Y(0)<=A(3) nand B(3). FRI. S. -.2 3-67 Signal A : unsigned ( 3 downto 0). Y(3)<=A(A’low) nor B(B’low). -. THU. byte’left=7 T’RIGHT week’right=SAT. TYPE count IS INTEGER RANGE 0 to 63. WED. count’right=63.Y(0)<=A(0) nor B(0).Y(0)<=A(0) or B(3).W. SAT). Signal B : unsigned ( 0 to 3).CHEN VHDL 2004. byte’right=0 TYPE week IS (SUN. count’left=0.T’LEFT week’left=SUN. Y(0)<=A(A’left) and B(B’left). Y(1)<=A(A’right) or B(B’right).Y(0)<=A(3) and B(0).2 3-68 . S. Y(2)<=A(A’high) nand B(B’high). MON. -.CHEN VHDL 2004. TYPE byte IS ARRAY (7 downto 0) of STD_LOGIC.

S.2 3-70 .CHEN VHDL 2004. 3 dwonto 0) of BIT.A’LENGTH nibble’length=4. data’length(2)=4 TYPE nibble IS ARRAY (3 downto 0) of STD_LOGIC. TYPE address IS ARRAY (17 downto 5) of BIT.W. TYPE data IS ARRAY (1 downto 0 . S.CHEN VHDL 2004.2 3-69 A’RANGE nibble’range= 3 downto 0 A’REVERSE_RANGE address’reverse_range = 5 to 17 TYPE nibble IS ARRAY (3 downto 0) of STD_LOGIC.W. address’length=13 A’LENGTH(i) data’length(1)=2. TYPE address IS ARRAY (17 downto 5) of BIT.

if (A’length = B’length) then -. Signal B : unsigned ( 0 to 3).if ( 4 = 4) then for N in A’range loop -.W.CHEN VHDL 2004.for N in 0 to 3 loop S.for N in 3 downto 0 loop for N in A’reverse_range loop -.CHEN VHDL 2004.2 3-71 S’EVENT S’STABLE S’ACTIVE can’t be synthesized S’TRANSACTION can’t be synthesized S.Signal A : unsigned ( 3 downto 0).W.2 3-72 .

false which identifies if signal S has a new value assigned onto this signal.CHEN VHDL 2004.S’event Function returning a Boolean .W.positive-edge-trigger if (clk’event and clk=‘1’) if ( not clk2’stable and clk2=‘1’) S.2 3-74 .2 3-73 -.W.CHEN VHDL 2004. S’stable Function returning a Boolean . S.true which identifies if signal S has a new value assigned onto this signal.

S S. S’active A B S <= A and B.2 3-75 S’event vs.W.W.CHEN VHDL 2004.True which identifies if signal S had a new assignment made onto it.) S.CHEN VHDL 2004.2 3-76 .S’active Function returning a Boolean . (whether the value of the assignment is the SAME or DIFFERENT.

Attribute Delay_time of Clock1. S.W. S. Specify this attribute to the identifiers.2 3-78 . Attribute Delay_time : time.W. Clock2 : signal is 2. This signal toggles in value (between ‘0’ and ‘1’) when signal S had a new assignment made onto it (whether the value of the assignment is the SAME or DIFFERENT.S’transaction Implicit signal of type bit which is created for signal S when it S’transaction is used in the code.CHEN VHDL 2004.CHEN VHDL 2004.3 ns.2 3-77 Declare an “Attribute”.

Attribute Encoding : string.CHEN VHDL 2004.M + AND_2’place.2 3-80 .W.CHEN VHDL 2004. Yellow. S. Attribute place : Com_loc. Attribute place of AND_2 : Label is (40. Attribute Encoding of Color : type is “00 11 10 01”.2 3-79 Can provide a means of specifying particular enumerated values.. 35). S. Perimeter <= 2*(AND_2’place.W. b.Y). Green).Type Com_loc is Record M. N: integer. End Record. c).. AND_2 : And_comp port map (a. . Type Color is (Red. Orange. signal perimeter : integer.

W.W.S.CHEN VHDL 2004.2 3-82 .2 3-81 Literal Operands Identifier Aggregate Function call operands Qualified Expression Operands Type Conversion Operands Record & Record Element Operands S.CHEN VHDL 2004.

end arch.Hexadecimal O”576” -.2 Numeric Literals 314159 8#57# 16#9FDE# 3-83 Architecture arch of en is Signal k: bit_vector(15 downto 0).W.CHEN VHDL 2004.W. -.2 3-84 . Signal g: std_logic_vector(15 downto 0).String Literals “ABC” B”1010” -.error g<=to_stdlogicvector(X”9FDE”). S. begin k<=X“9FDE”.CHEN VHDL 2004. g<=X“9FDE”.Octal Enumeration Literals TRUE FALSE ‘a’ ‘1’ ‘0’ S.Binary X”9FDE” -.

..d: std_logic. . Y1. Arry <= ( 3=>a . begin .C. c . 1=>c . Arry <= ( a .b. function fun_a (A: unsigned(7 downto 0)) return std_logic is variable Result: std_logic. b .W.2 3-85 Aggregate data to an ARRAY.W..CHEN VHDL 2004. d ).CHEN VHDL 2004. signal Arry: std_logic(3 downto 0).port(A. S.D: in std_logic.Y2: out std_logic). end fun_a. 2=>b .2 3-86 . S.c. Signal a..B. 0=>d ).

W.only the actual. Rec <= ( ‘1’ .1=>c. Rec <= ( sign=>’1’ .2=>b.2 3-88 .CHEN VHDL 2004. formal => actual formal actual Arry<=(3=>a.b. S.Aggregate data to a RECORD type FloatPointType is record Sign: std_logic. Frac: unsigned(23 downto 0). frac=>”1101010” ). end record. Arry<=(a.c. Signal Rec : FloatPointType. “1010” .0=>d).d). Exp: unsigned(6 downto 0). S. “1101010” ). Positional Association .CHEN VHDL 2004.W.both the formal and actual are listed.2 3-87 Named Association . exp=>”1010” .

=>) <= AR . signal b: std_logic_vector(3 downto 0). --Error S.W.W.=>.2 3-90 . signal c: std_logic_vector(4 downto 0).=>.CHEN VHDL 2004. S.2 3-89 wrong method: signal a: std_logic.b). ….correct method: (=>. C<=(a. or AR <= (=>.CHEN VHDL 2004.=>).

F2=>A2).2 3-91 y(2 downto 0) <= a(0 to 2). y(3) <= a(3) and b(3). S.A2.F4=>A4.CHEN VHDL 2004. y(5 downto 4) <= (a(5) and b(5))&(a(4) or b(4)). f3:std_logic.a3.a2.F1=>A1. S.W.F3=>A3) or B2.W. y(11 downto 9) <= c.CHEN VHDL 2004. Y3 <= B1 or Fn1(A1. y(8 downto 6) <= b(2 downto 0). f2:std_logic. f4:std_logic) return std_logic.a4) or B1 or B2.F4=>A4. Y2 <= B1 or B2 or Fn1(F3=>A3. Y1 <= Fn1(a1.Function fn1(f1:std_logic.2 3-92 .

W. type R_2 is range 0 to 20.2 3-93 type_name(expression) integer types similar array types same length convertible or identical element types Enumerated types are not convertible S. FUNC(5). function FUNC(A: R_2) return BIT. -.ambiguous FUNC(R_1'(5)). -. function FUNC(A: R_1) return BIT.2 3-94 .W.unambiguous S.type_name’(expression) type R_1 is range 0 to 10.CHEN VHDL 2004.CHEN VHDL 2004.

. signal S_INT: INT_1.Ok S_INT <= INT_1(T_INT). type INT_2 is range 0 to 20. signal S_BIT_VEC: MY_BIT_VECTOR.2 3-96 ..OK S.CHEN VHDL 2004. BIT_ARRAY_10(S_BIT_VEC). -. signal T_INT: INT_2. type BIT_ARRAY_10 is array(11 to 20) of BIT..CHEN VHDL 2004.2 3-95 subtype MY_BIT_VECTOR is BIT_VECTOR (1 to 10)..Error S.W. -. -.type INT_1 is range 0 to 10. T_INT <= INT_2(S_INT)..W. .

2 3-97 Record & Record Element Operands signal M.l ) then Y.C: R1_Type. type BIT_ARRAY_20 is array(0 to 20) of BIT. wrong conversion: BOOLEAN(S_BIT).I .. signal S_BIT: BIT.CHEN VHDL 2004.l /= M.length not equal ARRAY_1(S_BIT_VEC).type INT_1 is range 0 to 10. -.W. signal Y: R2_Type.. . S.2 3-98 . BIT_ARRAY_20(S_BIT_VEC).enumerated type INT_1(S_BIT). end if.I <= M. else Y. -.I <= 0.element types not convertible S.CHEN VHDL 2004. if ( C.C.I. subtype MY_BIT_VECTOR is BIT_VECTOR (1 to 10). -.W. type ARRAY_1 is array (1 to 10) of INT_1. signal S_BIT_VEC: MY_BIT_VECTOR.

W. Z<= (a nand b) nand c. S.CHEN VHDL 2004.Logical operator(and or nand nor xor xnor not) relational operator(= /= < <= > >=) shift operator (sll srl sla sra rol ror) Only be supported by VHDL’93 adding operator (+ . Z<= a nand b nand c. Z<= a nand (b nand c).2 3-100 .2 3-99 nand vs.W.&) sign (+ -) multiplying operator (* / mod rem) miscellaneous operator (** abs) S.CHEN VHDL 2004. and Z<= a and b and c.

S.CHEN VHDL 2004. c(7 downto 6) <= a & b. = /= else vs.Simple Logic end if. else Q<=‘0’. if((A(7 downto 3)=“00000”) and (A(2 downto 0) /= “111”) and (A(2 downto 0) /= “000”)) then Q<=‘1’.Comparators Q<=‘1’. <= >= > < end process. Process(A) -.CHEN VHDL 2004. Q<=‘0’. signal c: bit_vector (7 downto 0). end if. S. b: bit.2 3-101 concatenation & signal a.W.W. begin end process.Process(A) begin if((A<=“00000110”) and (A>=“00000001”)) then -.2 3-102 .

CHEN VHDL 2004.ERROR when “00” => Q<=C. when “01” => Q<=A. . Case TTT’(a&b) is when “00” => Q<=C.W. S. when others => Q<=‘0’. when others => Q<=‘0’.The result of Concatenate Operator is unconstrained Array Case a&b is -. when “01” => Q<=A. end case.W.2 3-104 . S. end case.CHEN VHDL 2004. end case.. Subtype TTT is bit_vector(1 to 2). when others => Q<=‘0’..2 3-103 Case bit_vector’(a. b) is when “00” => Q<=C. when “01” => Q<=A.

Remainder and Modulus The right-hand operand must be a computable power of 2 and cannot be negative. There are more restrictions of synthesis in the other synthesis tools excepts Synopsys.2 3-105 REM -Sign of rem operation is sign of the “left” operand MOD -Sign of rem operation is sign of the “right” operand J=K*N+(J mod K) J 4 -4 4 -4 S. Division.2 J MOD K 4 1 -1 -4 3-106 .CHEN VHDL 2004.W.CHEN K 5 5 -5 -5 J REM K 4 -4 4 -4 VHDL 2004. S.for synopsys synthesis Supports the multiplying operators for all integer types.W.

W. end arch.ALL. S..W. ARCHITECTURE ARCH of XXX IS signal a: STD_LOGIC.2 3-107 std_logic_1164 Library IEEE. C <= 2 ** D.a). B: INTEGER range -8 to 7. S..CHEN VHDL 2004.CHEN VHDL 2004.a.std_logic_1164. the left operand must be the computable value 2. USE IEEE.for synopsys synthesis Supports the “abs” and “**” operators for all integer types. signal C: INTEGER range 0 to 15. begin b<=(a. When you're using “**”.2 3-108 .a. signal b: STD_LOGIC_VECTOR(3 downto 0). signal D: INTEGER range 0 to 3. . A <= abs(B). signal A.

all.std_logic_arith.std_logic_unsigned.CHEN VHDL 2004.y. signal x.all. z<=x+y. use ieee.W.all.error end arch.z: std_logic_vector(3 downto 0). -.CHEN VHDL 2004.2 3-110 .10 b <= “1010”.. Use ieee. --use ieee.std_logic_1164.2 3-109 Library ieee.W. . Architecture arch of xxx is signal a.all. use ieee. -.-6 end arch. begin a <= “1010”. architecture arch of xxx is signal a:unsigned(3 downto 0). S. S.std_logic_arith Library ieee. begin c<=a+b.c: unsigned (3 downto 0).std_logic_arith.b. signal b: signed(3 downto 0).

“00011101” S. -. z := shl(u.STD_LOGIC_ARITH. -. IEEE.ALL. USE IEEE. s:= “11101011”.“00001101” z := shr(s.count).ALL.. variable z: unsigned(7 downto 0). u:= “01101011”. IEEE. size=>2).std_logic_unsigned. IEEE.math_real.“01011000” z := shl(s.W.std_logic_arith.std_logic_vector unsigned IEEE.ALL.ALL.count). IEEE..count). count := conv_unsigned(arg=>3. -.: unsigned(7 downto 0). 1 1 .CHEN VHDL 2004.1164_ALL. Declaration Function Declaration and Function S. variable u.std_logic. IEEE.“01011000” z := shr(u.math_complex.W.numeric_std. -.ALL. IEEE.ALL.CHEN VHDL 2004.2 “11” 3-112 . variable count: unsigned (1 downto 0).count).std_logic_signed.2 3-111 LIBRARY IEEE.ALL.s.

“00111” -.count).Error y1 := a sla count.y2 : unsigned(4 downto 0).count).“10111” y2 := a sra count. z := slr(a. -.LIBRARY IEEE.Numeric_STD. variable a. variable y1. -.“10000” -. z := rol(a.count).z: unsigned(4 downto 0).“00111” S..“10011” -. a := “11100”.2 3-113 variable a : unsigned(4 downto 0).W.ALL.CHEN VHDL 2004.count).“11101” S. USE IEEE. -. . constant count: integer := 2.count). z := ror(a.. a := “10101”. constant count: integer := 2.. -. ..2 3-114 .CHEN VHDL 2004. z := sll(a.W. y1 := sla(a.

W.CHEN VHDL 2004.W.2 3-115 S.2 3-116 ./synopsys S.pdf Design Compiler HDL Compiler for VHDL Reference Manual Package Reference /usr/mentor/fpgadv50_ss/Modeltech/vhdl_src .CHEN VHDL 2004./ieee .Synthesis Reference %acroread /usr/synopsys/sold/cur/top.

2 3-118 .CHEN VHDL 2004.S.CHEN VHDL 2004.W.2 3-117 a c A B b And I Inverter Z (my_and) (my_inv) U0 U1 NAND2 My_and a My_inv z S.W.

S.CHEN VHDL 2004. end arch.B: in std_logic. z: out std_logic). end arch. configuration cfg_inv of my_inv is for arch end for.2 3-119 a My_inv z entity my_inv is port(a:in std_logic. configuration cfg_and of my_and is for arch end for. C: out std_logic).W.a c b My_and entity my_and is port(A. end cfg_and.2 3-120 . end my_and. architecture arch of my_and is begin c<= a and b. end my_inv.CHEN VHDL 2004. S. architecture arch of my_and is begin z<= not a.W. end cfg_inv.

But will have warning during compiling. VHDL simulator will find the corresponding entity automatically. S.W.2 3-122 . z: out std_logic). (my_and) (my_inv) end component. B U1 component my_inv U0 port(a:in std_logic.z). U1: my_and port map (a.b: in std_logic.architecture arch of my_nand is component my_and A port(A. Entity my_nand is begin port(a.CHEN VHDL 2004.CHEN VHDL 2004. U2: my_inv port map (I. signal I: std_logic. And I Inverter Z C: out std_logic). NAND2 z: out std_logic).b.I). you must designate the corresponding entity oneself. Can ignore. If component and entity have the different name.W. end component. end my_nand.B: in std_logic.2 3-121 If component and entity have the same name. S. end arch.


C: out std_logic).my_nand(arch). BEGIN U1: ND2 port map(X.Y. U3: ND2 port map(r.y: in std_logic. U2: ND2 port map(X.CHEN Configuration conf of yy is for xx for u1: ND2 use entity work. VHDL 2004.B: in std_logic. end yy.s). S.CHEN VHDL 2004. z: out std_logic).s: BIT... end conf.2 3-126 .2 3-125 S. ARCHITECTURE xx OF yy IS component ND2 port(A. . for others: nd2 use entity work. end for.Y. end for... end for.s. .my_nand(arch).r).W. signal r.Z). END xx.Component and Entity are Different name entity yy is port(x.W. end component.

end xx. C: out std_logic). for ALL: ND2 use entity work.CHEN VHDL 2004.Configuration conf2 of yy is for xx for ALL: ND2 use configuration work.. end conf. S.CHEN VHDL 2004.W.my_nand(arch). begin . S.B: in std_logic. end for.2 3-128 .2 3-127 Solving the Warning during Compiling ARCHITECTURE xx OF yy IS component ND2 port(A.. end component. end for.cfg1_nand.W.

signal VDD: std_logic. z=>Z). b=> GND . U0: my_and port map (a=> VDD . VDD<=‘1’.W.W. zn=>I) VHDL’93 only S. c=>I).2 3-130 . begin GND<=‘0’.CHEN VHDL 2004. ‘1’ ’0’ U1: my_inv port map (a=>I.architecture STRUCT of NAND2 is signal I: std_logic. signal GND:std_logic. end STRUCT.2 3-129 S.CHEN VHDL 2004. port map(a1=>’1’. a2=>’0’.

END MY_AND2.CHEN VHDL 2004. PORT (q: OUT std_logic.W.CHEN VHDL 2004.b:IN std_logic). a.2 3-131 Entity ENTITY MY_AND2 IS GENERIC( tp : time :=5 ns ).W.S. timing propagation S.2 3-132 .

.b) VARIABLE newstate: std_logic. PROCESS(a. PORT(q: OUT std_logic.b: IN std_logic)..W. ENTITY and2 IS GENERIC(tp: time:= 5 ns). timing propagation a...2 3-133 in architecture component declaration component instantiations in configuration parents children S. END and2.CHEN VHDL 2004.2 3-134 .. . END PROCESS.W. newstate was assigned to q. BEGIN newstate := a AND b. After waiting 5 ns. q <= newstate after tp. S.CHEN VHDL 2004.

Y).2 3-136 .CHEN VHDL 2004. b=>CIN). PORT (q: OUT std_logic.W.W. timing propagation S.CHEN VHDL 2004. END COMPONENT.Generic (component declaration) Component Declaration COMPONENT my_and GENERIC(tp:time:=3 ns). U5: my_and GENERIC MAP(tp=>7 ns) PORT MAP(a=>IN1. a.2 3-135 Generic (component instantiations) Component Instantiation U4: my_not GENERIC MAP(7 ns) PORT MAP(IN.b:IN std_logic). q=>IN3. S.

W. S. END fulladd_config4. FOR u0: my_and use entity work...my_and(arch) GENERIC MAP (tp=>3 ns). END FOR... END FOR.CHEN VHDL 2004.W.CHEN VHDL 2004. .Full-adder Configuration (tp=5 ns) and2 architecture and2 architecture and2 architecture S.2 3-137 CONFIGURATION fulladd_config OF fulladd IS FOR structure .2 3-138 .

W. END FOR. END c_74LS08_cfg.CHEN VHDL 2004.W. END c_74F08_cfg. S.5 ns).Configuration Full-adder and2 Configuration(tp=5 ns) and2 Configuration (tp=6 ns) and2 Configuration (tp=25 ns) S.2 3-140 . END FOR.CHEN VHDL 2004.2 3-139 Configuration of and2 CONFIGURATION 74F08_cfg OF my_and IS FOR arch GENERIC MAP(tp=> 2. CONFIGURATION 74LS08_cfg OF my_and IS FOR arch GENERIC MAP(tp=> 10 ns).

FOR u5: my_and use configuration work. Q : OUT unsigned( Size .W.74f08_cfg.2 3-141 7bits Shift left logic ENTITY shl7 IS GENERIC ( Size: INTEGER := 8).Configuration of fulladd CONFIGURATION fulladd_config OF fulladd IS FOR structure .. constant count : unsigned(1 downto 0) := “11”... END shl7.2 3-142 .. END FOR.74ls08_cfg.. FOR u4: my_and use configuration work. END FOR.1 downto 0 )).CHEN VHDL 2004.W. . ..count). END fulladd_config4. S. . END FOR.. Q <= shl(D. PORT ( D : IN unsigned( Size .1 downto 0 ). S.CHEN VHDL 2004..

. Signal D. Q :OUT unsigned( Size . PORT (D :IN unsigned( Size .2 3-144 .. END COMPONENT.15bits Shift left logic COMPONENT shl7 GENERIC ( Size: INTEGER := 4).1 DOWNTO 0 ).W. u0 : shl7 GENERIC MAP (16) PORT MAP ( D.1 DOWNTO 0 )).W.Q).Q : unsigned(15 dwonto 0)..CHEN VHDL 2004. S.2 3-143 S.CHEN VHDL 2004.

W.S.CHEN VHDL 2004.2 4-2 .2 4-1 S.W.CHEN VHDL 2004.

W.2 4-3 Architecture arch of en is {Declaration Statement} begin {Concurrent Statement} {Sequential Statement} end arch.CHEN VHDL 2004.2 4-4 .W.CHEN VHDL 2004.S. S.

2 4-5 Sequential Statement can use “variable”.CHEN VHDL 2004. Be placed in the front of “begin”.W.CHEN VHDL 2004. S. Each statement will operate simultaneously.W.2 4-6 .Declares the internal signals that is similar to the statement in the packages. three types: process function procedure c<=a and b. b a c z Concurrent Statement Each statement can be taken as a small circuit. architecture block process procedure function S. z<=a and c.

begin t := a and c.. end process. wait on a. concurrent sequential S.b end Process a.CHEN VHDL 2004.architecture arch of en is begin concurrent c <= a and b.. end Process Process [process declaration] begin .2 4-8 .b) [process declaration] begin . z <= t..b -> sensitivity list S.2 4-7 Process (a.. end arch.c) variable t: bit. process(a.CHEN VHDL 2004.W.W.

W..Assignment IF CASE LOOP EXIT NEXT WAIT NULL ASSERT [label:] process (..variable..CHEN VHDL 2004.2 4-9 Assignment architecture arch of en is signal a: std_logic:=‘0’. -. S.2 4-10 .signal b := ‘0’ -. end.. end process [label]...CHEN VHDL 2004.a small circuit S....) begin .. -.. end arch.... begin a <= ‘1’. begin process variable b: std_logic:=‘1’.W.

(data1. z : out bit_vector(3 downto 0)). architecture arch of en is begin process( a.CHEN VHDL 2004.indexed named -. -.Aggregates S.2 4-12 . b : in bit. databus(3) <=‘0’. z(3 downto 2)<=a(2 downto 1).b ) begin z(1 downto 0)<= (b .Five kinds of Target data <= ‘1’. databus(2 to 4) <=“101”.W. end en.2 4-11 entity en is port (a : in bit_vector(2 downto 0). end arch. a(0) ). A. S.NUM_FIELD := 12.field names -.CHEN VHDL 2004. end process.slices -.simple name -.data2) <=“10”.W.

begin process(clk.CHEN VHDL 2004.d: std_logic:=‘0’. end if.CHEN VHDL 2004. end if. end arch.2 4-14 .b.b.a.b: std_logic:=‘1’.W. C(t) <= A and B D <= C(t-1) S.a. d <= c.W. Side effect error S.2 4-13 process(clk. end process.Architecture arch of yy is signal a.c) begin if(clk’event and clk = ‘1’) then c <= a and b.c) begin if(clk’event and clk = ‘1’) then c <= a and b. end process. signal c. d <= c.

W. end process. end arch. end if.a.Architecture arch of yy is signal a. C(t) := A and B D <= C(t) S. d <= c. d <= c. S. begin if(clk’event and clk = ‘1’) then c := a and b. begin if(clk’event and clk = ‘1’) then c := a and b.2 4-16 . end process.b) variable c : std_logic.b) variable c : std_logic.b: std_logic:=‘1’. begin process(clk.a. end if.CHEN VHDL 2004.CHEN VHDL 2004.W. signal d: std_logic:=‘0’.2 4-15 process (clk.

S.p1.2 4-17 process( a.W. else Z<=C.signal changed delta time Variable updated many events Signal updated Note: A process is not a clock. elsif (P2=‘0’) then Z<=B.CHEN VHDL 2004.c.p2 ) begin if (P1=‘1’) then Z<=A.W.CHEN VHDL 2004. S.b. end if.2 4-18 . end process.

p2 ) begin if (P1=‘1’) then Z<=A. in_val : std_logic. end if. end process. .c..2 4-20 .CHEN VHDL 2004. S.p1. if (cond) then out_val <= in_val.process( a.b. signal cond : boolean. else out_val <= 'Z'. elsif (P2=‘0’) then Z<=B.2 4-19 signal out_val. cond Out_val S..W.CHEN VHDL 2004.W. In_val end if.

d.b. en2.W.CHEN VHDL 2004. else En2=‘0’ end process. en2.2 4-21 process(a. end if. end process. S. in1. out<=in1. when PICK_D => Z <= D. out<=‘Z’. end process. in2) begin begin If (En1=‘1’) then If (En1=‘1’) then out<=in1. in1 else elsif (En2=‘1’) then out<=‘Z’.value) begin case VALUE is when PICK_A => Z <= A . else in2 if(En2=‘1’) then out<=‘Z’.c.error S.W.2 4-22 . when PICK_C => Z <= C. in2) Process(en1. when PICK_B => Z <= B.CHEN VHDL 2004. out<=in2. out end if. -. end case. out<=in2. in1. En1=‘1’ end if.Process(en1.

... when 4 to 7 | 2 => Z <= "0100".. use work. a. S.. Process(value) begin case VALUE is when 0 => Z <= "0001"..d: in bit. when 1|3 => Z <= "0010"..CHEN VHDL 2004. PICK_A=00 PICK_B=01 PICK_C=10 PICK_D=11 S... entity en is port (value: in ENUM. PICK_D).2 4-23 signal VALUE :INTEGER range 0 to 15. end process. PICK_C.all. signal Z :BIT_VECTOR(3 downto 0).CHEN VHDL 2004. .2 4-24 .c. end case. end test.W. z: out bit).. PICK_B.package test is type ENUM is (PICK_A..test..W..b. when others => Z <= "1000". end en.

loop used for synthesis don’t use wait statement fixed range S. for.CHEN VHDL 2004.S..2 4-26 .CHEN VHDL 2004. A loop is not a clock..W.2 4-25 loop can’t be synthesized while…loop can’t be synthesized Note:Loop and clock have no relational.W.

2 4-28 . END PROCESS.CHEN VHDL 2004.PROCESS BEGIN [loop1:] LOOP Because wait exists. don’t write sensitivity list.2 4-27 PROCESS VARIABLE a:integer :=1.W. BEGIN [loop1:] WHILE (a<=10) LOOP WAIT FOR 25 ns. END LOOP [loop1]. WAIT FOR 25 ns. END LOOP [loop1]. S.W. END PROCESS.CHEN VHDL 2004. clk1<= NOT clk1. S. a:=a+1. clk1<= NOT clk1.

2 4-30 .CHEN VHDL 2004. clk1 <= NOT clk1. END LOOP loop2. S. end process. a:=a+1. clk1 <= NOT clk1.permanent existence begin loop1: While(a<=10) LOOP WAIT FOR 25 ns.2 4-29 process VARIABLE a:integer :=1. END LOOP loop1. END LOOP [loop1]. END PROCESS. loop2: FOR a IN 1 TO 10 LOOP WAIT for 26 ns . S.W. -.CHEN VHDL 2004. clk<= NOT clk .W.PROCESS BEGIN [loop1:] FOR a IN 1 TO 10 LOOP WAIT FOR 25 ns.

2 4-32 . A(I)<=B(I).2 A>B A<B 4-31 process(B.CHEN VHDL 2004. S. If(copy_enable(I)=‘0’) then next. . end if. else a(I)<=b(I).W.. else null. end if. exit. S. end loop. exit.CHEN VHDL 2004.signal A.B: BIT_VECTOR(7 downto 0). signal A_LESS_THAN_B: BOOLEAN..copy_enable) begin A<="00000000".W. end process. for I in 1 to 8 loop next when COPY_ENABLE(I)='0'. elsif (A(I)='0' and B(I)='1') then A_LESS_THAN_B<=TRUE. end loop. for I in 7 downto 0 loop if(A(I)='1' and B(I)='0') then A_LESS_THAN_B<=FALSE.

2 4-34 . process begin z<=a and b.CHEN VHDL 2004.CHEN VHDL 2004.wait on sensitivity clause can’t be synthesized wait for timeout clause can’t be synthesized wait until condition clause Note:wait and sensitivity list in the process are not able to coexist. end process.b. end process.W.2 4-33 process (a. only signal S. S.b) begin z<=a and b.W. wait on a.

S. end if. -. -. count<=i.CHEN VHDL 2004.W. pwring <= false.halt until dtack is ‘1’.negative-edge trigger wait until clk='0' and clk’event. process begin wait on dtack until dtack='1' for 150 ms.only wait for 150ms.W. S. end process. if dtack='0' then buserr<='1'.2 4-36 . wait on i.CHEN VHDL 2004. end process. reset<='1'. -.process begin i<=i+1. end process.2 4-35 process begin if pwring then wait for 150 ns. end if.

end if. . wait on i. end process. end process. end process... count<= i.W. wait on clk.. process begin wait until (clk='1' and clk'event). Z<=A. count<= i.2 4-38 . -...clk) begin if (clk='1' and clk'event) then Z<=A.CHEN VHDL 2004. .2 4-37 process(a.W. S.signal I. process begin i<=i+1. begin I:=i+1. process variable I: integer:=0..wait on i..CHEN VHDL 2004.. count: integer:=0. I count I count 1 2 3 4 5 wait on 12345 12345 no wait on 01234 signal count: integer:=0. I 12345 count 1 2 3 4 5 S. end process. wait on clk.

bad for synthesis S. if(a='1') then wait until (clk='1' and clk'event) Z<=A. -.OK end process.clk.process(a. end if.2 4-39 Process variable VAR: bit. end process. begin wait until clk’event and clk=‘1’.reset) begin if(reset ='1') then Z<=‘0’.CHEN VHDL 2004. elsif(clk='1' and clk'event) then Z<=A.W.CHEN VHDL 2004.2 4-40 . -.register S <= Var. -. S.W. VAR := not Var. end if.

combinational S <= Var.S2) variable Var: bit.W. -. S<=Var. -. -. Var := S3.CHEN VHDL 2004.CHEN VHDL 2004. begin if CLK’event and CLK=‘1’ then Var:=not Var.W. end if. begin wait until clk’event and clk=‘1’. S. S.X S2 <= Var.Process variable VAR: bit. -. VAR := S and S1.2 4-41 Process(CLK.O end process.X S <= S3. -.2 4-42 .X S4 <= S. end process.

if S1=‘1’ then Var:= not Var.Comb end if.2 4-43 Process (S1) begin if S1=‘1’ then Var:=not Var.latch S<=Var. -. Process (S1) begin Var:=‘0’.Comb S<=Var. S.CHEN VHDL 2004.W. end process.2 4-44 . The signal or variable is read in any path prior to being assigned a value. -. end process. The VHDL attribute ‘event is not present in the conditional expression.CHEN VHDL 2004.The signal or variable is in an equivalent process where not all the alternatives of a conditional expression are considered. S.W. -.latch end if. S<=‘0’. -.

W.latch S.Flip-flops if statement without else if (clk’event and clk=‘1’) -.W.wait statement wait until (clk’event and clk=‘1’).2 4-46 .Flip-flops if(clk=‘1’) -.CHEN VHDL 2004.2 4-45 ASSERT condition REPORT string SEVERITY serverity_level serverity_level note warning error failure S.CHEN VHDL 2004. -.Flip-flops wait until (clk=‘1’). -.

W. Z: out Bit ). END IF. S.W. END PROCESS.PROCESS BEGIN WAIT UNTIL (nmi='0' OR int0='0') FOR 5 us. it will report message. Function function fun_name ( A. return return.Functions S.2 4-48 .procedure return expression. ASSERT (nmi='0' OR int0='0') REPORT "NO INTERRUPT OCCURRED IN 5 us" SEVERITY ERROR. Note:When the condition of ASSERT is false. -.CHEN VHDL 2004. -.B: in Bit ) return Integer.2 4-47 Procedure procedure pro_name (A: in Bit. IF (nmi='1' AND int0='1') THEN err<='1'.CHEN VHDL 2004.

W. LOWER: out NIBBLE) is begin UPPER:=NIBBLE(B(7 downto 4)). LOWER:=NIBBLE(B(3 downto 0)). end IS_EVEN. UPPER. -.Returns TRUE if NUM is even. LOWER: out NIBBLE). procedure BYTE_TO_NIBBLES(B: in BYTE.package test is type BYTE is array (7 downto 0) of BIT. end test. -.2 4-50 . type NIBBLE is array (3 downto 0) of BIT. procedure BYTE_TO_NIBBLES(B: in BYTE. end BYTE_TO_NIBBLES.W. S. S. function IS_EVEN(NUM: in INTEGER) return BOOLEAN. end test.CHEN VHDL 2004.CHEN VHDL 2004.Splits a BYTE into UPPER and LOWER halves.2 4-49 package body test is function IS_EVEN(NUM: in INTEGER) return BOOLEAN is begin return ((NUM rem 2) =0). UPPER.

type LARGE is range 0 to 10000. . variable EVEN: BOOLEAN.W. function IS_ODD(NUMBER: LARGE) return BOOLEAN.W. B <= IS_ODD(A_NUMBER). signal A_NUMBER : SMALL. end process. BOT). end process.process (…. S. BOT: NIBBLE.) signal INT: INTEGER.2 4-52 .) variable TOP.. function IS_ODD(NUM: SMALL) return BOOLEAN. EVEN := IS_EVEN(INT). begin INT<=7. TOP. signal B: BOOLEAN.CHEN VHDL 2004.2 4-51 type SMALL is range 0 to 100.. begin BYTE_TO_NIBBLES("00101101". S. process(….CHEN VHDL 2004.

I2: in NEW_BIT) return NEW_BIT.. '1'.W.2 4-53 Only Simulation S. 'X')..type NEW_BIT is ('0'. function “and”(I1. .C:NEW_BIT.B.CHEN VHDL 2004.2 4-54 .I2:in NEW_BIT) return NEW_BIT. C<=(A and B) or C. function “or”(I1.CHEN VHDL 2004.W. . S. signal A...

S.2 4-55 wired_and wired_or package RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT. end. function res_f(..CHEN VHDL 2004.Four steps type new_type is . S. Utilizes the prior declarations to declare a subtype.. subtype res_t is res_f new_type. Utilizes the subtype to allocate signals.W.. subtype RESOLVED_BIT is RES_FUNC BIT. Declares a new type.CHEN VHDL 2004.2 4-56 . signal bus : res_t..W.) return new_type is Declares a function returns the new type.

end. end WAND_VHDL. Z<=Y.package body RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT is --pragma resolution_method wired_and begin -.2 4-57 use work.RES_PACK. end WAND_VHDL. return '1'.but parsed for correct VHDL syntax for I in DATA'range loop if DATA(I)='0' then return '0'.CHEN VHDL 2004. end.2 4-58 .CHEN VHDL 2004. S. architecture WAND_VHDL of WAND_VHDL is begin Z<=X.W.Y : in BIT. end loop. S. Z : out RESOLVED_BIT).W. end if.all. entity WAND_VHDL is port(X.The code in this function is ignored by VHDL Compiler -.

W.2 4-59 Signal Assignment Process Block & Guarded Block Concurrent Assert Concurrent Procedure Call S.CHEN VHDL 2004.CHEN VHDL 2004.2 Conditional Signal Assignment Selected Signal Assignment Generate Statement 4-60 .S.W.

end process.ARCHITECTURE BEHAVIOR OF NOR2 IS BEGIN q <= a NOR b. END BEHAVIOR. end if. end EXAMPLE.2 4-61 architecture EXAMPLE of COUNTER is begin process(IN_COUNT. else OUT_COUNT<=IN_COUNT+1. S. S.CHEN VHDL 2004.W.W.2 4-62 .CLEAR) begin if(CLEAR='1' or IN_COUNT=9) then OUT_COUNT<=0.CHEN VHDL 2004.

end block B1. B3: block begin Z<=S.W. S.CHEN Block Statement (2/2) concurrent statements hierarchically VHDL 2004. begin S<=A and B.[label:] Block {Declaration Statement} begin {Concurrent Statement} {Sequential Statement} end block [label]. end block B2. end block B3. begin S<=C and D.W.2 4-64 .2 4-63 B1: block signal S: BIT.CHEN VHDL 2004. S. B2: block signal S:BIT. Y<=S.

W.CHEN VHDL 2004.label: process() begin end process [label].W. S. component and2 end component.CHEN VHDL 2004. package mypack is end [mypack].2 4-65 ALU MEMORY S. label: block begin end block [label]. entity name is end name. architecture arch of name is end arch.2 4-66 . configuration test of name is end test.

W.2 4-68 . END BLOCK B1. S. S.W.CHEN VHDL 2004. END guarded_latch. not be supported by synthesis ARCHITECTURE guarded_latch OF latch IS BEGIN B1: BLOCK (en='1‘) BEGIN q <= guarded d after 5 ns.CHEN VHDL 2004. BUS signal to take on the default value sepcified by the bus resoluation function.Enable and disable drivers contained in the block.2 switch 4-67 SIGNAL KIND REGISTER signal to retain its last value. qbar <= guarded not (d) after 6 ns.

END new_latch. b: OUT std_logic). but port will hold the original value.W.no register here. a<= guarded not d after 200 ns. -. DISCONNECT a: std_logic AFTER 10 ns.CHEN VHDL 2004.d:IN std_logic. S.CHEN VHDL 2004.model the time delay of tri-state signals used for SIGNAL KIND signals ENTITY new_latch IS PORT(c.2 4-69 B1: BLOCK(c='1‘) BEGIN b<= guarded not d after 100 ns. END BLOCK B1.2 4-70 .W. S. a: OUT std_logic BUS.

S. True after 20 ns. B: in BIT. process(A.procedure ADD(signal A.. -. signal SUM: out BIT). end P2.2 4-71 Architecture arch of en is signal S:boolean.Sequential procedure call end process.B.CHEN VHDL 2004.SUM).procedure P2” severity NOTE. S. Begin P(False).SUM). Procedure P(A:boolean) is begin assert S report “S is false -. False after 10 ns.W.CHEN VHDL 2004. … architecture arch of en is begin ADD(A. end arch.. end arch.W. False after 30 ns. Procedure P2(A_s:boolean) is begin assert A_s report “S is false -. P2(S).B) -.The equivalent process begin ADD(A. end P.procedure P” severity NOTE. S<= True. -.Concurrent procedure call .B.2 4-72 .

CHEN VHDL 2004.2 4-73 Conditional Signal Assignment Z <= A when ASSIGN_B = '1' else B when ASSIGN_A = '1' else C.Concurrent Procedure Calls (3/3) [Results] 0 NS Assertion NOTE at 0 NS in design unit CPROC(CPROC_A) from process /CPROC/_P0: "S is False -.00 NSAssertion NOTE at 30.W. elsif ASSIGN_B = '1' then Z<=B. B.Procedure P2"10. end process.CHEN VHDL 2004.Procedure P” Assertion NOTE at 0 NS in design unit CPROC(CPROC_A) from process /CPROC/_P1: "S is False -. ASSIGN_A. end if.Procedure P2" S. process(A.00 NS in design unit CPROC(CPROC_A) from process /CPROC/_P1: "S is False -. S.00 NSAssertion NOTE at 10.Procedure P2"30. ASSIGN_B. C) begin if ASSIGN_A = '1' then Z<=A.00 NS in design unit CPROC(CPROC_A) from process /CPROC/_P1: "S is False -.W. else Z<=C.2 4-74 .

end case. B_OUT<=B when ENABLE_B else 'Z'. S.2 4-76 . when 1=> C when “10“.W. D. C.. D) begin with CONTROL select case CONTROL is when 0=> Z <= A when “00“. when 2=> Z<=C. Z<=B. D when “11“. end process. process(CONTROL. when 3=> Z<=D. B when “01“. end process. B.CHEN VHDL 2004.2 4-75 signal A.. Z<=A. process(A_OUT) begin SIG<=A_OUT. process(B_OUT) begin SIG<=B_OUT. Z: BIT. . S. C.A_OUT<=A when ENABLE_A else 'Z'. B.CHEN VHDL 2004. signal CONTROL: bit_vector(1 downto 0 ). A.W. end process.

end generate [LABEL]. LABEL: for I in 3 downto 0 generate C(2*I+1)<=A(I) nor X.2 .W. C(7) <= A(3) nor X.漢界 楚河 S.W.. B: bit_vector(3 downto 0). C(0) <= B(0) nor X. C(2) <= B(1) nor X. C(1) <= A(0) nor X. 4-78 S. C(3) <= A(1) nor X. C(4) <= B(2) nor X.2 4-77 signal A. signal X: bit. C(5) <= A(2) nor X. . C(6) <= B(3) nor X.CHEN VHDL 2004.CHEN VHDL 2004.. C(2*I)<=B(I) nor X. signal C: bit_vector(7 downto 0).

. S. -.clock. end component.a(i+1)).concurrent outp<=a(4). a(0)<=inp. .CHEN VHDL 2004. signal a: std_logic_vector(0 to 4).CHEN VHDL 2004.2 4-79 component dff port(sig_in. q: out std_logic).W.clock:in std_logic. END GENERATE.S..W. g1: FOR i IN 0 TO 3 GENERATE u0 : dff port map(a(i).2 4-80 .

. end CONVERTER.W. .CHEN VHDL 2004. S. Convert: buffer BIT_VECTOR(N-1 downto 0)). port(CLK. ..CHEN VHDL 2004.DATA: in BIT...W.2 4-81 CONVERTER entity CONVERTER is generic(N: INTEGER:=8).S. signal S : bit_vector(N-2 downto 0).2 4-82 .

W.CONVERTER G: for I in convert'range generate -. end generate G1.2 4-84 .CHEN VHDL 2004. end process.shift middle bits up G2:if(I>CONVERT'right and I<CONVERT'left) generate S(I)<=S(I-1) and CONVERT(I). CONVERT(I)<=S(I-1). end process.CHEN VHDL 2004. S CONVERT S.W. process begin wait until (CLK'event and CLK='1'). end generate G2.shift (N-1) data bit into high-order bit G1: if (I=CONVERT'left) generate process begin wait until (CLK'event and CLK='1'). CONVERT(I)<=S(I-1).2 4-83 data -. S.

2 4-85 S. end generate G3.2 4-86 .CHEN VHDL 2004.-.CHEN VHDL 2004. end generate G.Move DATA into low-order bit G3:if(I=CONVERT'right) generate process begin wait until (CLK'event and CLK='1'). CONVERT(I)<=DATA. end process. S(I)<=CONVERT(I).W. S.W.

W.ARCHITECTURE behv OF ckints IS BEGIN err<='1' WHEN (nmi='1' AND int0 ='1') ELSE '0'. S.W. END behv. ASSERT (nmi='0' OR int0='0') REPORT "NO INTERRUPT OCCURRED" SEVERITY ERROR.2 4-87 S.CHEN VHDL 2004.CHEN VHDL 2004.2 4-88 .

CHEN VHDL 2004.2 5-1 S.W.2 5-2 .W.S.CHEN VHDL 2004.

signal X.S. END a.CHEN VHDL 2004.2 5-4 .C. … signal A.CHEN VHDL 2004. Y <= A or not(B) or (C and D).D : std_logic.Y : std_logic. S. ARCHITECTURE a OF BL_EQ IS BEGIN X <= (A and B and not(C)) or (A and not(D)) or (B and C and D).B.W. y = A + B'+C • D.W.2 5-3 x = A • B • C '+ A • D'+ B • C • D.

end process p2.CHEN VHDL 2004. (a1(2) nor a1(3))). p2:process (a1) variable v: unsigned(1 downto 0).2 5-5 p1:process(a1) variable v: unsigned(1 downto 0).CHEN VHDL 2004. s2<=v(0) nand v(1). begin v:=(a1(4) nor a1(5))&(a1(6) nor a1(7)). S.S. end process p1.W.2 5-6 . begin v:=((a1(0) nor a1(1)). s1<=v(0) nand v(1). y1<=s1 nor s2.W.

d2.CHEN VHDL 2004.b2.CHEN VHDL 2004.W.S.W.2 5-8 .2 5-7 process(a2. end process. S.c2.e2) begin y2<=a2+(b2-c2)+(d2*e2).

a2.b2.c1.process(a1.2 5-9 process if case concurrent conditional assign with.d2) begin y1<=a1+b1+c1+d1.select S. S..CHEN VHDL 2004.. y2<=(a2+b2)+(c2+d2).d1.CHEN VHDL 2004.W. end process.c2.2 5-10 .b1.W.

else y<=a when sel="00" else else y<=d.CHEN VHDL 2004. if(sel3='1') then y3<=a3.W.sel3. else elsif(sel="10") then if(sel(0)='0') then y<=c.y1<=a1 when sel1='1' else b1 . elsif(sel="01") then end if.a.W. b when sel="01" else y<=d. S. d. end process. c when sel="10" else end if. process(sel2. end if. S.CHEN VHDL 2004. end if. y<=b.b. if(sel="00") then else y<=a. end if. end process.a3.d) if(sel(0)='0') then begin y<=a. Y<=b. y<=c.2 5-12 . end if. else y3<=b3.2 5-11 if(sel(1)='0') then process(sel.b3) begin y2<=b2.a2. if(sel2='1') then y2<=a2.c.b2.

b when "01". end process. a when others.process(sel. elsif (a="00001000") then y<="011".CHEN VHDL 2004. elsif (a="00000010") then y<="001". with sel select y<=a when "00". when "10" => y<=c.2 5-13 process(a) begin if (a="00000001“) then y<="000".W.b. end process. elsif (a="10000000") then y<="111". d when "11".CHEN VHDL 2004. else y<="XXX".2 5-14 . S. elsif (a="00100000") then y<="101". elsif (a="01000000") then y<="110". when others => y<=a.W. elsif (a="00010000") then y<="100".c. c when "10". when "11" => y<=d.d) begin case sel is when "00" => y<=a. elsif (a="00000100") then y<="010". S. end case. when "01" => Y<=b. end if.a.

2 5-15 y <= "000" when a="00000001" else "001" when a="00000010" else "010" when a="00000100" else "011" when a="00001000" else "100" when a="00010000" else "101" when a="00100000" else "110" when a="01000000" else "111" when a="10000000" else "XXX". when others => y<="XXX". when "00010000" => y<="100". end process. when "00100000" => y<="101". when "10000000" => y<="111".2 5-16 . S.process(a) begin case a is when "00000001" => y<="000". end case. when "00001000" => y<="011".CHEN VHDL 2004. when "00000100" => y<="010". S.W.CHEN VHDL 2004.W. when "00000010" => y<="001". when "01000000" => y<="110".

end process. end if. "001" when "00000010". S. end loop.2 5-18 ."1").W. exit.with a select y<= "000" when "00000001". y<="XXX". begin test:="00000001". "111" when "10000000". "110" when "01000000". S. "101" when "00100000".2 5-17 process(a) variable n: integer range 0 to 7 . "100" when "00010000". "XXX" when others. "010" when "00000100".CHEN VHDL 2004.W.CHEN VHDL 2004. test:=shl(test.3). variable test: unsigned (7 downto 0). "011" when "00001000". for n in 0 to 7 loop if(A=test) then y<=conv_unsigned(n.

S.b1.compare: process(a1. end if.CHEN VHDL 2004. if(a3=b3) then y3<='1'.CHEN VHDL 2004.W.2 5-19 S.a3.2 5-20 . else y3<='0'. end process.b3) begin y1<='1'. y2<='0'. exit. if(a2=b2) then y2<='1'.b2. for n in 0 to 5 loop if(a1(n) /= b1(n)) then y1<='0'. end loop.W.a2. end if. end if. else null.

S.CHEN VHDL 2004.W. end if. S. end a.W. end process.d) begin if ena = '0' then q <= d.2 5-21 architecture a of latch is begin process(ena.2 5-22 .CHEN VHDL 2004.

architecture a of latch is begin process(ena,d,clear) begin if clear = ‘0’ then q <= ‘0’; elsif ena = ‘1' then q <= d; end if; end process; end a;


VHDL 2004.2


architecture a of d_ff is begin process(clk,d) begin if clk‘event and clk = '1' then q <= d; end if; end process; end a;


VHDL 2004.2


(with Synchronous Reset)
architecture a of dff_sr is begin process(reset,clk,d) begin if clk'event and clk = '1' then if reset = '0' then q <= '0'; else q <= d; end if; end if; end process; end a;
S.W.CHEN VHDL 2004.2 5-25

(with Asynchronous Reset)
architecture a of dff_ar is begin process(reset,clk,d) begin if reset = '0' then q <= '0'; elsif clk'event and clk = '1' then q <= d; end if; end process; end a;


VHDL 2004.2


architecture a of div2 is begin process(clk_in,reset) variable clk_2: std_logic; begin if reset = '0' then clk_2 := ‘0’; -- set initial value elsif clk_in'event and clk_in = '1' then clk_2 := not clk_2; clk_out <= clk_2; end if; end process; end a;


VHDL 2004.2



VHDL 2004.2


W.down) variable updown : unsigned(1 downto 0).CHEN VHDL 2004.2 5-30 . elsif clock'event and clock='1' then case updown is when "00"=> count<=count. end case.reset.W. when "10"=> count<=count+1. begin updown:=up&down. S. end process.2 5-29 up-by-one down-by-two Counter (2/2) S. when "01"=> count<=count-2.CHEN VHDL 2004. when others=> count<=count.up-by-one down-by-two Counter (1/2) process(clock. end if.up. if (reset='1‘) then count<="00000".

W.2 OL 5-32 .CHEN VHDL 2004.S.W.CHEN VHDL 2004.2 5-31 Current state Next state Output logic CLK S1 NS CS S2 S3 S.

end if.CHEN VHDL 2004. OL CS + NS.reset) begin if (reset='1') then currentstate<=st0. S. end process seq. S.three ways CS.2 5-33 seq: process(clock. Maybe the Output side will connect with a latch after being synthesized. OL NS + OL. CS OL and CS don’t put into the same process. NS.2 5-34 .W.CHEN VHDL 2004.W. elsif clock'event and clock='1' then currentstate<=nextstate.

end process comb. S.CHEN VHDL 2004.currentstate) begin case currentstate is when st0=> nextstate<=st1. when st2=> nextstate<=st3.2 5-36 . when st3=> nextstate<=st0. else nextstate<=st3. S. when st1=> if (control='1') then nextstate<=st2.W. 2 when st2. 1 when st1.comb: process (control. end case.CHEN VHDL 2004. end if. 3 when st3.2 5-35 with currentstate select y <= 0 when st0. 0 when others.W. when others=> nextstate<=st0.

W.2 5-37 S.W.CHEN VHDL 2004.CHEN VHDL 2004.2 5-38 .S.

end if. when st2=> state<=st3. y<=0. y<=0. y<=1. else state<=st3. elsif clock'event and clock='1' then case state is when st0=> state<=st1. when st1=> if(control='1') then nextstate<=st2. end if.currentstate) begin case currentstate is when st0=> nextstate<=st1.next_cur: process(clock.CHEN VHDL 2004. end if. S.reset) begin if(reset='1') then state<=st0. y<=3.W.2 5-39 comb: process (control. when st2=> nextstate<=st3. when others=> state<=st0.W.2 5-40 . S. when st1=> if(control='1') then state<=st2. end process comb. end case. when st3=> nextstate<=st0. else nextstate<=st3.CHEN VHDL 2004. end process next_cur. end case. when st3=> state<=st0. y<=2. when others=> nextstate<=st0.

when st2=>y<=2.reset.CHEN VHDL 2004. case currentstate is when st0=>y<=0.seq: process(clock. end case. end process seq.2 5-42 .2 5-41 S.currentstate) begin if(reset='1') then currentstate<=st0. end if. when st1=>y<=1. elsif clock'event and clock='1' then currentstate<=nextstate. when st3=>y<=3.CHEN VHDL 2004.W.W. S.

currentstate) begin if(reset='1') then currentstate<=st0. end if. end process seq. end case.CHEN VHDL 2004. when st2=>y<=2. case currentstate is when st0=>y<=0.S. S. elsif clock'event and clock='1' then currentstate<=nextstate.reset.2 5-43 seq: process(clock.W.CHEN VHDL 2004.2 5-44 . when st1=>y<=1. when st3=>y<=3.W.

CHEN VHDL 2004. Stimulus vectors Unit Under Test (UUT) Reference vectors Output vectors Test Vectors File Waveform Generation Compare Results VHDL Testbench S.2 Results File Pass/fail indication 6-2 .W.W.CHEN VHDL 2004. There is wide variety of ways in which testbench may be coded.S.2 6-1 A testbench is normally written in the same HDL language.

W. S.Instantiate the hardware model under test.CHEN VHDL 2004. Generate stimulus waveforms Generate expected waveforms Provide a pass or fail indication automatically.2 6-4 . Can transportable across different design tools.2 6-3 Advantage of Testbench in VHDL No need to learn other simulation tool or language. Can be exploited to the full in a testbench.CHEN VHDL 2004. S.W.

CHEN VHDL 2004.CHEN VHDL 2004. Use simple assignments for signals with few transitions. S.2 6-5 Vectors Generated “on-the-fly” Use continuous loops for repetitive signals.Generate them “on-the-fly” form within a testbench.W. Use relative or absolute time generated signals.2 6-6 . Read vectors stored in a separate system file. Use loop constructs for repetitive signal patterns S. Read vectors stored as constants in an array. such as clocks.W. such as resets.

u0: f_adder port map (a_i. sum.W. S.all..c_i: std_logic.std_logic_1164.2 6-7 component f_adder port (a.c_i.W.sum_o. USE ieee. .carry: out std_logic).c: in std_logic.all.b. end component. USE std.carry_o: std_logic.b_i.textio. ENTITY testbench IS END testbench.std_logic_textio.CHEN VHDL 2004..2 6-8 .LIBRARY ieee. signal sum_o.carry_o).CHEN VHDL 2004. USE ieee.b_i.all. S. signal a_i.

S. . signal ClockFast : std_logic := '0'.CHEN VHDL 2004. S. -..W.5).constant FastClock : integer := 100.2 6-10 .W.100MHz constant FastClockPeriod : TIME := 1 us/FastClock. .. ClockFast <= not ClockFast after FastClockPeriod / 2 . signal ClockMed : std_logic := '0'. -..2 6-9 Generating Medium Clock Signals constant MedClock : integer := 50.50MHz constant MedClockPeriod : TIME := 1 us/MedClock.CHEN VHDL 2004.5) when ClockMed = '0' else '0' after (MedClockPeriod * 0.. ClockMed <= '1' after (MedClockPeriod * 0.

W.60). signal ClockSlow : std_logic := '0'.2 6-11 Generating Phase Clock Signals constant MedClock : integer := 50.40). wait for (SlowClockPeriod * 0. S. S. process begin wait for (SlowClockPeriod * 0.constant SlowtClock : integer := 40. ClockSlow <= '0'..CHEN VHDL 2004. signal Clock_ph1.CHEN VHDL 2004. ClockSlow <= '1'. Clock_ph2 <= Clock_ph1'delayed(MedClockPeriod/2). .W. -. .50MHz constant MedClockPeriod : TIME := 1 us/MedClock. -... end process. Clock_ph1 <= not Clock_ph1 after MedClockPeriod /2.Clock_ph2 : std_logic := '0'..2 6-12 .40MHz constant SlowClockPeriod : TIME := 1 us/SlowtClock.

2 6-13 Generating Signals with Few Transitions signal reset : std_logic..stop : std_logic := '0'.. '0' after 20 ns.W. wait. signal clk. . '1' after 40 ns.CHEN VHDL 2004. .100MHz constant runtime : TIME := 1 us/RunClock. end process.Generating Clock Signals with Wait constant RunClock : integer := 100. S. exit when stop = '1‘. end loop.. reset <= '1'. process begin loop wait for runtime/2.2 6-14 . -. clk <= not clk.W. S..CHEN VHDL 2004.

process begin A <= '0'. reset <= '0'. B <= '1'. wait for runtime. S.B : std_logic. wait for runtime. wait. End process. .CHEN VHDL 2004. wait for runtime. wait for runtime.2 6-15 Relative Time Generated Signals signal A. B <= '1'.W.. B <= '0'. .. S.CHEN VHDL 2004. process begin wait for (runtime/4).100MHz constant runtime : TIME := 1 us/RunClock.W. constant runtime : TIME := 50 ns.. signal reset : std_logic := '1'. end process.2 6-16 .. A <= '1'. B <= '0'. -.constant RunClock : integer := 100.

3). stop <= ‘1’. '1' after (runtime*3).b. S. wait for 10 ns. B <= '0'.c.CHEN VHDL 2004.W.Absolute Time Generated Signals signal A. '0' after (runtime*2).sum. Testbench of Full_adder wait.stop : std_logic := ‘0’. S.B : std_logic. signal cs : std_logic_vector(1 downto 0). for i in 0 to 7 loop (c.CHEN VHDL 2004.W. b) <= conv_std_logic_vector (i. constant runtime : TIME := 50 ns. end process..2 6-18 . '1' after (runtime*2). process Begin cs <= conv_std_logic_vector((conv_integer(a) + conv_integer (b) + conv_integer (c))..2 6-17 Repetitive Stimulus Using Loops signal a. end loop.2). … A <= '0'. .carry. '1' after (runtime*1). a. assert carry&sum = cs report "error result" severity error.

std_logic_textio. Signal OperateData : bit_vector(7 downto 0). BufLine). 2 => "00000011")..W.string’(“(A. begin wait for 15 ns.b). constant MemArr : MemVecArr :=(0 => "00000000". use ieee. writeline(output_file.CHEN VHDL 2004. . end process. end process.all. write(BufLine. end loop.B)=11 6-19 type MemVecArr is array (0 to 2) of bit_vector(7 downto 0)..2 6-20 .. process begin for N in MemVecArr’range loop OperateData <= MemArr(N)..textio.2 (A. . write(BufLine.use std.B)=”)).. 1 => "00000001". wait for 10 ns..data". process variable BufLine : LINE. S. .B)=10 (A.B)=01 (A.CHEN VHDL 2004.a). S. file output_file : TEXT IS OUT “out.B)=00 (A.all. write(BufLine.W.

report “Error number is :” & integer’IMAGE(error_num).a). read(BufLine. wait for 10 ns. . variable a.. S. read(BufLine.c). report integer’IMAGE(error_num).b. begin while not(ENDFILE(input_file)) loop readline(input_file.2 6-22 . report T’IMAGE(X).. S. wait for 10 ns.b). end process. report “string” & T’IMAGE(X). read(BufLine. process variable BufLine : LINE. process Variable error_num : integer.2 a bc 000 001 010 011 100 101 110 111 6-21 report “string”.data". BufLine).W. end process. report “Error number is :”.Reading Test Vector System Files file input_file : TEXT IS IN “in.W. end loop.c : bit. begin error_num := 10.CHEN VHDL 2004.CHEN VHDL 2004.

'8'. begin for i in 0 to S’length-1 loop for j in i*4 to (i*4)+3 loop temp(j-(i*4)) := S(j).W. report message: Hex Value is : abcd.2 6-23 function to_hex(S : std_logic_vector) return string is constant hex_index : string(1 to 16) := ('0'.'5'.'c'.W.CHEN VHDL 2004.'9'. end loop.'b'. return result. end to_hex. begin hex_value := X”abcd”. S.”.'7'. return result. end process.'6'.'f'). S. end if. end loop.2 6-24 . variable temp : std_logic_vector(3 downto 0).'e'. report “Hex Value is : ” & to_hex(hex_value) & “.'2'.'d'.'1'. else result := (others => 'X'). variable result : string(S’length/4 downto 1).'a'.CHEN VHDL 2004.process Variable hex_value : std_logic_vector(15 downto 0). if temp >= "0000" and temp <= "1111" then result(i+1) := hex_index(to_integer(unsigned(temp))+1). wait for 10 ns.'4'.'3'.

W.W.CHEN VHDL 2004.CHEN VHDL 2004.2 7-2 .2 7-1 VHDL Testbench VHDL & Verilog co-simulator VHDL RTL Logic synthesizer Artisan Cell VHDL model Verilog Gate level Verilog in cadence S.S.

W.Gate-Level Simulation for Verilog Apply for Cell-base Design Kit Prepare VHDL Cell Library Compile VHDL Cell Library Start on gate-level co-simulation S.tw/chip_design/desi gn_petition.25um Cell-Based Design kit V1.html CIC 0.W.CHEN VHDL 2004.edu.2 7-4 .35um Cell-Based Design Kit (TSMC/TSMC) Release S.cic.0 Release CIC 0.2 7-3 http://www.CHEN VHDL 2004.

25um Invoke ModelSim vsim& Create a library – artisan_lib25 vlib artisan_lib25 vmap artisan_lib25 artisan_lib25 S.CHEN VHDL 2004.W.25 um technology CIC_CBDK25_V1/CIC/VHDL/CORE/tsmc25.vhd S.v hd 0.CHEN VHDL 2004.2 7-5 Compile VHDL Cell Library .0.2 7-6 .W.35 um technology CBDK035_TSMC_TSMC/CIC/VHDL/*.

.CHEN VHDL 2004.. open “Compile HDL Source Files window”. Compile tsmc25.W.. Select “artisan_lib25” in the Library form.vhd to vital library Select Compile -> Compile.35um Invoke ModelSim vsim& Create a library – vital vlib vital vmap vital vital Compile Vtable. Select “vital” in the Library form Compile Vtable.2 7-7 Compile VHDL Cell Library .vhd to artisan_lib25 library Select Compile -> Compile.25um Compile tsmc25.vhd S.2 7-8 ..CHEN VHDL 2004.W.Compile VHDL Cell Library .vhd S.

) S.design vsim –L compass_lib work.W. open “Simulate window”. Select “Design” label and load design.Compile VHDL Cell Library . add the path of artisan_lib25 in the Search Libraries[-L].design S.CHEN VHDL 2004.2 7-10 .. Select “tsmc_lib35” in the Library form Compile *.W..35um Create a library – tsmc_lib35 vlib tsmc_lib35 vmap tsmc_lib35 tsmc_lib35 Compile *.. Select “Libraries”label.vhd to tsmc_lib35 library Select Compile -> Compile.2 7-9 Start on Gate-Level co-Simulation Load Design (I) Select Simulate -> Simulate.CHEN VHDL 2004..vhd (can ignore the warnings. Load Design (II) vsim –L artisan_lib25 work.

2 7-12 .CHEN VHDL 2004.synopsys_dc.setup of Synopsys Apply for Cell-base Design Kit Prepare VHDL Cell Library Compile VHDL Cell Library Start on VHDL gate-level simulation S.CHEN VHDL 2004.VHDL Testbench VHDL simulator VHDL RTL Logic synthesizer Artisan Cell VHDL model VHDL Gate level Verilog Verilog in cadence S.2 7-11 Gate-Level Simulation for VHDL Modify .W.W.

all use tsmc_lib35.cic.CHEN VHDL 2004.35 um technology vhdlout_use_packages={"IEEE.W.prim" } 0.std_logic_116 4".vcomponents" } In the VHDL gate-level code.html CIC 0.2 7-13 http://www.setup 0.“tsmc_lib35.tw/chip_design/desi gn_petition.std_logic_116 4".W.vcomponents. "artisan_lib25.35um Cell-Based Design Kit (TSMC/TSMC) Release S.edu.0 Release CIC 0.all S.25 um technology vhdlout_use_packages={"IEEE.CHEN VHDL 2004. you can see the following description: use artisan_lib25.2 7-14 .synopsys_dc.25um Cell-Based Design kit V1.prim..

2 7-15 Compile VHDL Cell Library .CHEN VHDL 2004.CHEN VHDL 2004.W.35 um technology CBDK035_TSMC_TSMC/CIC/VHDL/*.25 um technology CIC_CBDK25_V1/CIC/VHDL/CORE/tsmc25.0.25um Invoke ModelSim vsim& Create a library – artisan_lib25 vlib artisan_lib25 vmap artisan_lib25 artisan_lib25 S.W.2 7-16 .v hd 0.vhd S.

25um Compile tsmc25. open “Compile HDL Source Files window”.vhd S.Compile VHDL Cell Library .vhd S.. Compile tsmc25.vhd to artisan_lib25 library Select Compile -> Compile.2 7-18 .W.vhd to vital library Select Compile -> Compile.CHEN VHDL 2004. Select “vital” in the Library form Compile Vtable..2 7-17 Compile VHDL Cell Library ..35um Invoke ModelSim vsim& Create a library – vital vlib vital vmap vital vital Compile Vtable. Select “artisan_lib25” in the Library form.W..CHEN VHDL 2004.

CHEN VHDL 2004..2 7-19 Start on Gate-Level co-Simulation Load Design (I) Select Simulate -> Simulate.vhd (can ignore the warnings.) S. Select “tsmc_lib35” in the Library form Compile *.design S..Compile VHDL Cell Library .W. Load Design (II) vsim work. open “Simulate window”.CHEN VHDL 2004.2 7-20 ..vhd to tsmc_lib35 library Select Compile -> Compile. Select “Design” label and load design..W.35um Create a library – tsmc_lib35 vlib tsmc_lib35 vmap tsmc_lib35 tsmc_lib35 Compile *.

, Create a library – tsmc_lib35 Modelsim> vlib tsmc_lib35 Modelsim> vmap tsmc_lib35 tsmc_lib35 .all. 開始 compile tsmc25.25 製程 VHDL Library: Invoke modelsim % vsim& Create a library – artisan_lib25 Modelsim> vlib artisan_lib25 Modelsim> vmap artisan_lib25 artisan_lib25 Compile tsmc25.How to do gate-level simulation VHDL 版本 1.開啟 Compile HDL Source Files window.Compile .html 3.Synopsys 合成前: 編輯 .Compile .vhd 4.cic.25 製程,則修改或加入一行如下: vhdlout_use_packages={"IEEE.prim"} 如果是.all.35 製程,則修改或加入一行如下: vhdlout_use_packages={"IEEE.setup .tw/chip_design/design_petition. 2.vhd. 在 Library form 中選擇 vital 開始 compile Vtable..std_logic_1164".vhd .edu. "artisan_lib25.vhd to vital library 選擇 Compile -> Compile.vcomponents.申請 CIC Cell-Base Design Kit。 http://www.35 製程 VHDL Library: Invoke modelsim % vsim& Create a library – vital Modelsim> vlib vital Modelsim> vmap vital vital Compile Vtable.開啟 Compile HDL Source Files window. 5.vhd to artisan_lib25 library 選擇 Compile -> Compile.vcomponents"} 合成出的 vhdl gate-level 電路,可看到以下描述: use artisan_lib25.25 製程 路徑:CIC_CBDK25_V1/CIC/VHDL/CORE/tsmc25.std_logic_1164"..35 製程 路徑:CBDK035_TSMC_TSMC/CIC/VHDL/*."tsmc_lib35.prim. 在 Library form 中選擇 artisan_lib25.. 或 use tsmc_lib35..vhd.得到所需 VHDL 版本的 Cell Library: .如果是.synopsys_dc.

.Compile *.開啟 Compile HDL Source Files window. (有 warning 可以忽略) 6.開始 gate-level simulation for modelsim。 . 開始 compile *..vhd to tsmc_lib35 library 選擇 Compile -> Compile.vhd. 在 Library form 中選擇 tsmc_lib35.

.tw/chip_design/design_petition.Verilog 版本 1. 選擇 Design 標籤,選取欲模擬的電路,再按 Load.v to tsmc_lib35 library 選擇 Compile -> Compile.edu.開啟 Compile HDL Source Files window. 選擇 Libraries 標籤,在 Search Libraries[-L]中加入 artisan_lib25 或 tsmc_lib35 的路徑.v . 在 Library form 中選擇 artisan_lib25.cic.v 5.開始 gate-level simulation for modelsim。 .v.開啟 Compile HDL Source Files window. 開始 compile tcb773p.25 製程 Verilog Library: Invoke modelsim % vism& Create a library – artisan_lib25 Modelsim> vlib artisan_lib25 Modelsim> vmap artisan_lib25 artisan_lib25 Compile tsmc25.v to artisan_lib25 library 選擇 Compile -> Compile..Load Design Simulate -> Simulate…開啟 Simulate window..得到所需 Verilog 版本的 Cell Library: .35 製程 路徑:CBDK035_TSMC_TSMC/CIC/Verilog/tcb773p.. 6. 4.35 製程 Verilog Library: Invoke modelsim % vism& Create a library –tsmc_lib35 Modelsim> vlib tsmc_lib35 Modelsim> vmap tsmc_lib35 tsmc_lib35 Compile tcb773p.html 2.Compile .申請 CIC Cell-Base Design Kit。 http://www.25 製程 路徑:CIC_CBDK25_V1/CIC/Verilog/tsmc25. 開始 compile tsmc25. 在 Library form 中選擇 tsmc_lib35.v 3.Compile .

vcd. Open a VCD file VSIM> vcd file dump. 5. and variable value changes.pdf .Assgin simulate command on command field.wlf 8. 7. %vsim –view ???. It is an ASCII file containing header information.Assign VCD command on command field. variable definitions.View WLF file. Simulate -> End Simulation… 6. 2. Simulate -> Simulate… 3.When simulation is completion. you can get the dump.vcd ???.vcd Add all signal to VCD file VSIM>vcd add –r * 4.When you complete above steps. For example: force¡B run… But add wave is unnecessary. end simulation is necessary. load design you want to simulate.First.Other VCD command reference. /usr/mentor/fpgadv50_ss/Modeltech/docs/pdf/se_cmds.Translate VCD file to WLF file %vcd2wlf ???.The VCD file format is specified in the IEEE 1364 standard.wlf & VSIM>add wave * 9.How to dump VCD file 1.

“entity_name” is the name of top entity. With FSDB files. Simulate -> End Simulation… 9. Open a FSDB file VSIM>fsdbDumpfile dump.Assign FSDB command on command field.novas 6.vhd. 2.Use nWave of Dubussy to view FSDB file. The simulation run time for an FSDB file is faster than that for a VCD file.Prepare data file novas.) 7.fsdb Set the depth of design you want to view signal VSIM>fsdbDumpvars 2 entity_name (“2” is the depth.fsdb.Debussy supports a new and open FSDB file format that has the following advantages over the standard VCD file format¡G An FSDB file is much more compact than the standard VCD file.Start your simulation.so to your library path. %vlib novas %vcom –work novas /usr/debussy/share/PLI/modelsim_fli/SOLARIS2/novas. %setenv LD_LIBRARY_PATH /usr/debussy/share/PLI/modelsim_fli/SOLARIS2/:$LD_LIBRARY_PATH 5.vhd 4.Run your simulation.vhd Load your design to simulate (“userdesign” is the name of top entity or comfiguration) Modelsim>vsim userdesign novas.vhd 3.End simulation to save the dump.Compile novas. Typically. /usr/debussy/share/PLI/modelsim_fli/SOLARIS2/novas. VSIM>run 100000ns 8. Debussy displays waveform and back-annotated signal values faster.Set the path of novas_fli.How to dump FSDB file 1. Invoke ModelSim %vsim& Compile your design Modelsim>vcom userdesign.vhd that provided by Debussy. an FSDB file is about 5 to 50 times smaller than a VCD file. Invoke nWave .

use novas. For example¡G Open a FSDB file fsdbDumpfile("dump.vhd 12. you can get dump.fsdb file from step 2 to step 8. Add the routine in the package pkg to your design.pkg. When your simulation complete and end simulaton. Compile novas.vhd to the novas library.fsdb."entity_name"). Modelsim>vlib novas Modelsim>vmap novas novas Modelsim>vcom –work novas novas. Add the following line to your VHDL design¡G library novas.vhd. 11. you also get dump. Reference the package pkg defined in novas.fsdb"). . “entity_name” is the name of top entity.) 13. (“2” is the depth. *If your design is Verilog code. Other method¡G 10. Set the depth of design you want to view signal fsdbDumpvars(2.all.%nWave& Please refer the Debussy’s training course to get more information.

VHDL LAB –ModelSim Setup your environment 1. c. Set up working directory for modelsim %cp ~/VHDL/modelsim.do 9. Click “Load” to load cfg1_multiplier 6. <File> -> <New> -> <Library…> a.ini . Fill in “work” in Library Name form. Select the “cfg1_multiplier” in work library of middle window. Enable “a new library and a logical mapping to it” in the Create New Library window.vhd” in UP window. Assign command on command field >add wave /multiplier/a /multiplier/b /multiplier/z >force /multiplier/a 1011 >force /multiplier/b 0011 >run 500 >force /multiplier/b 1010 >run 500 8. Using command script include test. End Simulation to save results <Simulate> -> <End Simulation> 10. Select the “Design” slice. Write step 7 to test. Compile VHDL code <Compile> -> <Compile…> a. 3.do >do test. b.do. c. b. %/bin/rm –rf * 3. b.wlf >add wave * -------------------------------------------------------------------- . Execute simulation <Simulate> -> <Simulate…> a. Use mouse to select source file “multi. %cd ~/VHDL/lab1 2.csh -----------------------------------------------------------------------LAB1 1. %cicsetup 4. Creat a work library. Log in WS with username/password shown in the KB 2. Log out and then log in again 5. Review waveform %vsim –view vsim. Click <OK>. Invoke ModelSim %vsim& 4. %source /usr/mentor/cic_setup/modelsim. Click <Done> to close Compile window. 1 7. Copy setup files for VHD simulator (Mentor ModelSim) and logic synthesyzer (Synopsys’s Design compiler): %cp –r /cad2/lab/VHDL/lab-modelsim ~/VHDL 5. Click <Compile> to compile the VHDL code. c. 6.

%cd ~/VHDL/lab4 2.cfg_testfa 9.wlf cfg_testadd4 >add wave * >run -all -----------------------------------------------------------------------LAB4 Co-simulation:Verilog call VHDL 1.cfg_testadd4 2 >add wave * >run -all -----------------------------------------------------------------------LAB3 Co-simulation:VHDL call Verilog 1. 3. End Simulation to save result. Execute simulatioin >vsim -wlf fadder.vhd and run simulation 7. Invoke Modelsim %vsim& 4.ini . Simulate 4bit-adder %vsim& >vlib work >vmap work work >vlog fa. Add all signal to wave form viewer.vhd and fa.v >vcom adder4.vhd 8. Prview adder4.vhd >vsim -wlf add4.LAB2 1.vhd testfixture_add4. Prview adder4. Revise f_adder. Creat a new library >vlib work 5.vhd 4. <Simulate> -> <End Simulation> 12.vhd and run simulation >vcom add4. %cd ~/VHDL/lab3 2. Set up working directory for modelsim %cp ~/VHDL/modelsim. 3.do and study.vhd and run simulation 5.wlf work.ini . Revise adder4. 3. Simulate 4bit-adder %vsim& .ini .vhd >vsim –wlf add4.do 13. %vi f_adder. Revise add4. >add wave * 10.vhd testfixture_add4. Compile full adder >vcom f_adder.v and fa.wlf work.v 4.vhd testfixture_fa. View the f_adder. Set up working directory for modelsim %cp ~/VHDL/modelsim. %cd ~/VHDL/lab2 2. Run simulation >run -all 11. map the new library to the work library >vmap work work 6. Set up working directory for modelsim %cp ~/VHDL/modelsim.

v >vcom testfixture_add4.vhd to concurrent version ---------------------------------------------------------------------3 LAB6 FSM 1. 3.ini .setup . Set up environment for Synopsys Design Compiler %cp ~/VHDL/.vhd >vsim –wlf fsm. %cd ~/VHDL/lab7 2.wlf cfg_testadd4 >add wave * >run -all -----------------------------------------------------------------------LAB5 1. 3.cfg_testFSM >add wave * >run -all ---------------------------------------------------------------------LAB7 Gate-level implementation and simulation for VHDL 1.ini .vhd % vi test_alu. Simulate ALU %vsim& >vlib work >vmap work work >vcom alu. %source /usr/synopsys/CICuser_setup/synthesis.>vlib work >vmap work work >vcom fa. Set up working directory for modelsim %cp ~/VHDL/modelsim. Run Synopsys Design Compiler %da& <Setup>-><command Window> .wlf work. Simulate FSM %vsim& >vlib work >vmap work work >vcom fsm.vhd >vsim –wlf alu. 3.ini . Set up working directory for modelsim %cp ~/VHDL/modelsim.vhd test_alu.vhd >vlog adder4.vhd 4.vhd % vi alu. %cd ~/VHDL/lab6 2.vhd >vsim –wlf add4.vhd and test_alu. %cd ~/VHDL/lab5 2. Revise ALU.wlf work.synopsys_dc. Set up working directory for modelsim %cp ~/VHDL/modelsim.cfg_testALU >add wave * >run -all 5. Revise fsm.vhd 4. Revise alu.csh 4.vhd test_fsm.vhd % vi fsm.

11.wlf work. %source /usr/synopsys/CICuser_setup/synthesis.dc” in the command field.csh 4. Simulate ALU in GATE level %vsim& >vlib work >vmap work work >vcom alu_gate. Re-compile the “test_alu. Create schematic >create_schematic -herarchy 9. Revise “test_alu. 14. Choose Design >current_design alu . Choose Design >current_design alu 7.to run all commands. Then type “include ???.synopsys_dc.sdf !!!You may write step 5-10 to a dc file. Perform logic synthesis >compile 8. Set up environment for Synopsys Design Compiler %cp ~/VHDL/. 3. Add net delay to simulation >vsim –sdftyp /u=alu. Read VHDL RTL to DC >Read –f vhdl alu.5.vhd” and re-run the simulation ALU error? Because we forget to annotate the timing information into the design in “vsim” phase.vhd” 13.vhd” use the RTL architecture in 4 “ALU. Because to “ALU_test.vhd >write_sdf –version 2. Read VHDL RTL to DC >Read –f vhdl alu. Change naming rule vhdl >change_names –rule vhdl 10. 12.cfg_testALU >add wave * >run -all Have Error Message!!!. Run Synopsys Design Compiler %da& <Setup>-><command Window> 5. %cd ~/VHDL/lab8 2.wlf work.1 alu.cfg_testALU >add wave * >run -all ---------------------------------------------------------------------LAB8 Gate-level implementation and simulation for Verilog 1.sdf –wlf alu.vhd” to let it use the gate-level architecture in “alu_gate.ini .vhd 6.setup .vhd 6. Set up working directory for modelsim %cp ~/VHDL/modelsim.vhd”.vhd test_alu. Output vhd gate-level netlist and SDF files >write –f vhdl –h –o alu_gate.vhd >vsim –wlf alu.

Output verilog gate-level netlist and SDF files > write -f verilog -h -o alu_gate.dc” in the command field.sdf !!!You may write step 5-10 to a dc file.v > write_sdf -version 2.1 alu.v >vcom test_alu..wlf \ work. Change naming rule verilog > change_names -rule verilog -hierarchy 9.cfg_testalu >add wave * >run -all 5 .7. Perform logic synthesis >set_fix_multiple_port_nets -all -buffer_constants > compile -map_effort medium 8.to run all commands. Simulate ALU in GATE level %vsim& >vlib work >vmap work work >vlog alu_gate.vhd >vsim –L ./lab7/artisan_lib25 -sdftyp /U=alu. 10..sdf -wlf alu. Then type “include ???.

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