DEPARTMENT OF COMPUTER SCIENCE ENGINEERING SUBJECT CODE: CS34 DIGITAL PRINCIPLES AND SYSTEM DESIGN (FOR THIRD SEMESTER

CSE)

TWO MARK QUESTIONS &ANSWERS

PREPARED BY C.ANNA PALAGAN Lecturer -ECE

CS 34 DIGITAL PRINCIPLES AND SYSTEM DESIGN TWO MARK QUESTIONS AND ANSWERS Uni t – I 1. Define binary logic? Part - A

Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT. 2. What are the basic digital logic gates? The three basic logic gates are AND gate OR gate NOT gate 3. What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 4. Give the classification of logic families

5. Which gates are called as the universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application. 6. Classify the logic family by operation? The Bipolar logic family is classified into

Saturated logic Unsaturated logic. The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family. 7. Define Fan-out? Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation. 8. Define power dissipation? Power dissipation is measure of power consumed by the gate when fully driven by all its inputs. 9. What is propagation delay? Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns. 10. Define noise margin? It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts. 11. Define fan in? Fan in is the number of inputs connected to the gate without any degradation in the voltage level. 12. What is Operating temperature? All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c. 13. What is High Threshold Logic? Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic. 14. Which gate is equal to AND-invert Gate? NAND gate. 15. Which gate is equal to OR-invert Gate? NOR gate. 16. Bubbled OR gate is equal to NAND gate

17. Bubbled AND gate is equal to NOR gate 18. Define the term digital. The term digital refers to any process that is accomplished using discrete units 19. What is meant by bit? A binary digit is called bit 20. What is the best example of digital system? Digital computer is the best example of a digital system. 21. Define byte? A group of 8 bits. 22. List the number systems? i) Decimal Number system ii) Binary Number system iii) Octal Number system iv) Hexadecimal Number system 23. State the sequence of operator precedence in Boolean expression? i) Parenthesis ii) AND iii) OR 24. What is the abbreviation of ASCII and EBCDIC code? ASCII-American Standard Code for Information Interchange. EBCDIC-Extended Binary Coded Decimal Information Code. 25. What are the universal gates? NAND and NOR 26. What are the different types of number complements? i) 1’sComplement ii) 2’s Complement. 27. Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used. 28. How to represent a positive and negative sign in computers? Positive (+) sign by 0 Negative (-) sign by 1. 29. What is meant by Map method? The map method provides a simple straightforward procedure for minimizing Boolean function.

30.What is meant by two variable map? Two variable map have four minterms for two variables, hence the map consists of four squares, one for each minterm 31. What is meant by three variable map? Three variable map have 8 minterms for three variables, hence the map consists of 8 squares, one for each minterm 32. What is the use of Don’t care conditions? Any digital circuit using this code operates under the assumption that these unused combinations will never occur as long as the system 33. Express the function f(x, y, z)=1 in the sum of minterms and a product of maxterms? Minterms=∑ (0,1,2,3,4,5,6,7) Maxterms=Nomaxterms. 34. What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate? F=xy1 + x1y F=xy +x1y1 35. What are the methods adopted to reduce Boolean function? i) Karnaugh map ii) Tabular method or Quine mccluskey method iii)Variable entered map technique. 36. Why we go in for tabulation method? This method can be applied to problems with many variables and has the advantage of being suitable for machine computation. 37. State the limitations of karnaugh map. i) Generally it is limited to six variable map (i.e.) more than six variable involving expressions are not reduced. ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. 38. What is tabulation method? A method involving an exhaustive tabular search method for the minimum expression to solve a Boolean equation is called as a tabulation method. 39. What are prime-implicants? The terms remained unchecked are called prime-implecants. They cannot be reduced further. 40. Explain or list out the advantages and disadvantages of K-map method? The advantages of the K-map method are i. It is a fast method for simplifying expression up to four variables. ii. It gives a visual method of logic simplification.

iii. Prime implicants and essential prime implicants are identified fast. iv. Suitable for both SOP and POS forms of reduction. v. It is more suitable for class room teachings on logic simplification. The disadvantages of the K-map method are i. It is not suitable for computer reduction. ii. K-maps are not suitable when the number of variables involved exceed four. iii. Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don’t care terms. 41. List out the advantages and disadvantages of Quine-Mc Cluskey method? The advantages are, a. This is suitable when the number of variables exceed four. b. Digital computers can be used to obtain the solution fast. c. Essential prime implicants, which are not evident in K-map, can be clearly seen in the final results. The disadvantages are, a. Lengthy procedure than K-map. b. Requires several grouping and steps as compared to K-map. c. It is much slower. d. No visual identification of reduction process. e. The Quine Mc Cluskey method is essentially a computer reduction method. 42. Define Positive Logic. When high voltage or more positive voltage level is associated with binary ‘1’ and while the low or less positive level is associated with binary ‘0’ then the system adhering to this is called positive logic. 43. Define Negative Logic. When high voltage level is associated with binary ‘0’ and whiles the low level is associated with binary ‘1’ then the system adhering to this is called negative logic. 44. List the characteristics of digital Ics i) propagation delay ii) power dissipation iii) Fan-in iv) Fan-out v) Noise margin 45. Why parity checker is needed? Parity checker is required at the receiver side to check whether the expected parity is equal to the calculated parity or not. If they are not equal then it is found that the received data has error.

46. What is meant by parity bit? Parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving and for errors. 47. Why parity generator necessary? Parity generator is essential to generate parity bit in the transmitter. 48. What is IC? An integrated circuit is a small silicon semiconductor crystal called a chip containing electrical components such as transistors, diodes, resistors and capacitors. The various components are interconnected inside the chip to form an electronic circuit. 49. What are the needs for binary codes? a. Code is used to represent letters, numbers and punctuation marks. b. Coding is required for maximum efficiency in single transmission. c. Binary codes are the major components in the synthesis (artificial generation) of speech and video signals. d. By using error detecting codes, errors generated in signal transmission can be detected. e. Codes are used for data compression by which large amounts of data are transmitted in very short duration of time. 50. Mention the different type of binary codes? The various types of binary codes are, a. BCD code (Binary Coded decimal). b. Self-complementing code. h. The excess-3 (X’s-3) code. i. Gray code. c. Binary weighted code. d. Alphanumeric code. e. The ASCII code. f. Extended binary-coded decimal interchange code (EBCDIC). g. Error-detecting and error-correcting code. h. Hamming code. 51. List the advantages and disadvantages of BCD code? The advantages of BCD code are a. Any large decimal number can be easily converted into corresponding binary number b. A person needs to remember only the binary equivalents of decimal number from 0 to 9. c. Conversion from BCD into decimal is also very easy. The disadvantages of BCD code are a. The code is least efficient. It requires several symbols to represent even small numbers. b. Binary addition and subtraction can lead to wrong answer. c. Special codes are required for arithmetic operations. d. This is not a self-complementing code. e. Conversion into other coding schemes requires special methods.

52. What is meant by self-complementing code? A self-complementing code is the one in which the members of the number system complement on themselves. This requires the following two conditions to be satisfied. a. The complement of the number should be obtained from that number by replacing 1s with 0s and 0s with 1s. b. The sum of the number and its complement should be equal to decimal 9. Example of a self-complementing code is i. 2-4-2-1 code. ii. Excess-3 code. 53. Mention the advantages of ASCII code? The following are the advantages of ASCII code a. There are 27 =128 possible combinations. Hence, a large number of symbols, alphabets etc.., can be easily represented. b. There is a definite order in which the alphabets, etc.., are assigned to each code word. c. The parity bits can be added for error-detection and correction. 54. What are the disadvantages of ASCII code? The disadvantages of ASCII code are a. The length of the code is larger and hence more bandwidth is required for transmission. b. With more characters and symbols to represent, this is not completely sufficient. 55. What is the truth table? A truth table lists all possible combinations of inputs and the corresponding outputs. 56. Define figure of merit? Figure of merits is defined as the product of speed and power. The speed is specified in terms of propagation delay time expressed in nano seconds. Figure of merits=Propagation delay time (ns)* Power (mw). It is specified in pico joules (ns*mw=PJ). Unit – II Part - A 1. Define Combinational circuit. A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination of inputs without regard to previous inputs. 2. Explain the design procedure for combinational circuits • The problem definition • Determine the number of available input variables & required O/P variables. • Assigning letter symbols to I/O variables • Obtain simplified Boolean expression for each O/P. • Obtain the logic diagram.

3. What is a half-adder? The combinational circuit that performs the addition of two bits is called a halfadder. 4. What is a full-adder? The combinational circuit that performs the addition of three bits is called a halfadder. 5. What is half-subtractor? The combinational circuit that performs the subtraction of two bits is called a halfsub tractor. 6. What is a full-subtractor? The combinational circuit that performs the subtraction of three bits is called a halfsub tractor. 7. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithemetic sum of two binary numbers in parallel. 8. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. 9. Give the truth table for a half adder. Input X 0 0 1 1 Y 0 1 0 1 Output Sum ( S ) 0 1 1 0 Carry ( C ) 0 0 0 1

10. Give the truth table for a half Subtractor. Input X 0 0 1 1 Y 0 1 0 1 Output Difference (D) 0 1 1 0 Borrow ( B ) 0 1 0 0

11. From the truth table of a half adder derive the logic equation S =X⊕ Y C= X. Y 12. From the truth table of a half subractor derive the logic equation D = X ⊕Y

B =X1.Y 13. From the truth table of a full adder derive the logic equation S =X⊕ Y ⊕ Z C = XY + YZ + XZ 14. What is code conversion? If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit which converts one system of codes to the other. The process of conversion is referred to as code conversion. 15. What is code converter? It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter. 16. What do you mean by analyzing a combinational circuit? The reverse process for implementing a Boolean expression is called as analyzing a combinational circuit. (ie) the available logic diagram is analyzed step by step and finding the Boolean function 17. Give the truth table for a full Subtractor. Input X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 Output Difference (D) 0 1 1 0 1 0 0 1 Borrow ( B ) 0 1 1 1 0 0 0 1

18. Give the truth table for a full adder. Input X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum ( S ) 0 1 1 0 1 0 0 1 Output Carry ( C ) 0 0 0 1 0 1 1 1

19. From the truth table of a full subtractor derive the logic equation S =X⊕ Y ⊕ Z C = X1Y + YZ + X1Z 20. What are the two types of logic circuits for digital systems? Combinational and sequential Unit – III Part - A 1. Give the applications of Demultiplexer. Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 2. What is priority encoder? A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 3. Can a decoder function as a Demultiplexer? i) It finds its application in Data transmission system with error detection. ii) One simple application is binary to Decimal decoder. 4. Mention the uses of Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places. 5. What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit. 6. Can a decoder function as a Demultiplexer? Yes. A decoder with enable can function as a Demultiplexer if the enable line E is taken as a data input line A and B are taken as selection lines. 7. List out the applications of multiplexer? The various applications of multiplexer are a. Data routing. b. Logic function generator. c. Control sequencer. d. Parallel-to-serial converter. 8. List out the applications of decoder? The applications of decoder are a. Decoders are used in counter system. b. They are used in analog to digital converter. c. Decoder outputs can be used to drive a display system.

9. List out the applications of comparators? The following are the applications of comparator a. Comparators are used as a part of the address decoding circuitry in computers to select a specific input/output device for the storage of data. b. They are used to actuate circuitry to drive the physical variable towards the reference value. c. They are used in control applications. 10. What are the applications of seven segment displays? The seven segment displays are used in a. LED displays b. LCD displays 11. List the types of ROM. i) Programmable ROM (PROM) ii) Erasable ROM (EPROM) iii) Electrically Erasable ROM (EEROM) 12. Differentiate ROM & PLD’s ROM (Read Only Memory) PLD’s (Programmable Logic Array) 1.It is a device that includes both the decoder and the OR gates within a single IC package 2. It is a device that includes both AND and OR gates within a single IC package 3.ROM does not full decoding of the variables and does generate all the minterms 4. PLD’s does not provide full decoding of the variable and does not generate all the minterms 13. What are the different types of RAM? The different types of RAM are a. NMOS RAM (Nitride Metal Oxide Semiconductor RAM) b. CMOS RAM (Complementary Metal Oxide Semiconductor RAM) c. Schottky TTL RAM d. ELL RAM. 14. What are the types of arrays in RAM? RAM has two type of array namely, a. Linear array b. Coincident array 15. Explain DRAM? The dynamic RAM (DRAM) is an operating mod, which stores the binary information in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors. DRAM cell Storage capacitor Column (sense line) Row (control line) 16. Explain SRAM? Static RAM (SRAM) consists of internal latches that store the binary information. The stored information remains valid as long as the power is applied to the unit. SRAM is easier to use and has shorter read and write cycle. The memory capacity of a static RAM varies from 64 bit to 1 mega bit.

17. What are the terms that determine the size of a PAL? The size of a PLA is specified by the a. Number of inputs b. Number of products terms c. Number of outputs 18. What are the advantages of RAM? The advantages of RAM are a. Non-destructive read out b. Fast operating speed c. Low power dissipation d. Compatibility e. Economy 19. What is VHDL? VHDL is a hardware description language that can be used to model a digital system at many level of abstraction, ranging from the algorithmic level to the gate level. The VHDL language as a combination of the following language. a. Sequential language b. Concurrent language c. Net-list language d. Timing specification e. Waveform generation language. 20. What are the features of VHDL? The features of VHDL are a. VHDL has powerful constructs. b. VHDL supports design library. c. The language is not case sensitive. 21. Define entity? Entity gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and others peripherals. 22. List out the different elements of entity declaration? The different elements of entity declaration are: 1. entity_name 2. signal_name 3. mode 4. in: 5. out: 6. input 7. buffer 8. signal_type

23. Give the syntax of entity declaration? ENTITY entity_name is PORT (signal_name: mode signal_type; signal_names: mode signal_type; signal_names: mode signal_type; END entity_name; 24. What do you meant by concurrent statement? Architecture contains only concurrent statements. It specifies functionality, interconnections or relationship between inputs and outputs. behavior,

25. What are operates used in VDHL language? There are different types of operators used in VHDL language Logical operators: AND, OR, NOT, XOR, etc., Relational operator : equal to, <less than etc., Shift operators : SLL- Shift Left Logical, ROR- Rotate Right Logical etc., Arithmetic operators: Addition, subtraction etc., Miscellaneous operators: <= assign to etc., 26. Define VHDL package? A VHDL, package is a file containing definitions of objects which can be used in other programs. A package may include objects such as signals, type, constant, function, procedure and component declarations 27. What is meant by memory decoding? The memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it. 28. What is access and cycle time? The access time of the memory is the time to select word and read it. The cycle time of a memory is a time required to complete a write operation. 29. What is Demultiplexer? A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. 30. Mention the uses of Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places. 31. Give other name for Multiplexer and Demultiplexer.  Multiplexer is otherwise called as Data selector.  Demultiplexer is otherwise called as Data distributor. 32. What is Magnitude Comparator? A Magnitude Comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes.

33. What is decoder? A decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2n unique output lines. 34. What is encoder? A decoder is a combinational circuit that converts binary information from 2nInput lines to a maximum of ‘n’ unique output lines. 35. Define Multiplexing? Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 36. What is binary decoder? A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 out puts lines. 37. What do you mean by comparator? A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers. 38. List basic types of programmable logic devices. • • • Read only memory Programmable logic Array Programmable Array Logic
n

39. Explain ROM A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2 . 40. Define address and word: In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.
n

41. State the types of ROM • • • • Masked ROM. Programmable Read only Memory Erasable Programmable Read only memory. Electrically Erasable Programmable Read only Memory.

42. What is programmable logic array? How it differs from ROM? In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. 43. Explain PROM. • PROM (Programmable Read Only Memory) It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20µs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent. 44. Explain EPROM. • EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed. 45. Explain EEPROM. • EEPROM (Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals. 46. What is RAM? Random Access Memory. Read and write operations can be carried out. 47. What is programmable logic array? How it differs from ROM? In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

48. What is mask - programmable? With a mask programmable PLA, the user must submit a PLA program table to the manufacturer. 49. What is field programmable logic array? The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA. 50. List the major differences between PLA and PAL PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL 51. Define PLD. Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve specific logic functions. 52. Give the classification of PLDs. PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL) 53. Define PLA PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array. 54. Define PAL PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic. 55. Why was PAL developed? It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity. 56. Why the input variables to a PAL are buffered? The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected. 57. What does PAL 10L8 specify? PAL - Programmable Logic Array 10 - Ten inputs PAL AND arrays are programmable OR arrays are fixed Cheaper and Simpler

L - Active LOW Output 8 - Eight Outputs 58. Give the comparison between PROM and PLA. PROM 1. And array is fixed and OR Array is programmable. 2. Cheaper and simple to use. Unit – IV Part - A 1. What is sequential circuit? Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path. 2. List the classifications of sequential circuit. i) Synchronous sequential circuit. ii) Asynchronous sequential circuit. 3. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time. 4. What is a clocked sequential circuit? Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don’t cause instability problems. 5. What is called latch? Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. 6. List different types of flip-flops. i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop iv) T flip-flop v) JK flip-flop vi) JK master slave flip-flop PLA Both AND and OR Arrays are Programmable. Costliest and complex than PROMS.

7. What do you mean by triggering of flip-flop. The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flipflop 8. What is an excitation table? During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition. A table which lists the required inputs for a given chance of state is called an excitation table. 9. Give the excitation table of a JK flip-flop Present State Qn 0 0 1 1 Next State Qn+1 0 1 0 1 J 0 1 X X Flip Flop Inputs K X X 1 0

10. Give the excitation table of a SR flip-flop Present State Qn 0 0 1 1 Next State Qn+1 0 1 0 1 R X 0 1 0 Flip Flop Inputs S 0 1 0 X

11. Give the excitation table of a T flip-flop Present State Next State Qn Qn+1 0 0 0 1 1 0 1 1 12. Give the excitation table of a D flip-flop Present State Qn 0 0 1 1 Next State Qn+1 0 1 0 1 Flip Flop Inputs D 0 1 0 1 Flip Flop Inputs T 0 1 1 0

13. What is a characteristic table? A characteristic table defines the logical property of the flip-flop and completely characteristic its operation.

14. Give the characteristic equation of a SR flip-flop. Q(t+1)=S+R1Q 15. Give the characteristic equation of a D flip-flop. Q(t+1)=D 16. Give the characteristic equation of a JK flip-flop. Q(t+1)=JQ1+K1Q 17. Give the characteristic equation of a T flip-flop. Q(t+1)=TQ1+T1Q 18. What is the difference between truth table and excitation table. i) An excitation table is a table that lists the required inputs for a given change of state. ii) A truth table is a table indicating the output of a logic circuit for various input states. 19. What is counter? A counter is used to count pulse and give the output in binary form. 20. What is synchronous counter? In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The output of the flip-flops change state at the same instant. The speed of operation is high compared to an asynchronous counter 21. What is Asynchronous counter? In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less. 22. What is the difference between synchronous and asynchronous counter? Synchronous counter 1. Clock pulse is applied simultaneously Clock pulse is applied to the first flip-flop, the change of output is given as clock to next flip-flop Asynchronous counter 1. Speed of operation is high Speed of operation is low. 23. Name the different types of counter. a) Synchronous counter b) Asynchronous counter i) Up counter ii) Down counter iii) Modulo – N counter iv) Up/Down counter 24. What is up counter? A counter that increments the output by one binary number each time a clock pulse is applied.

25. What is down counter? A counter that decrements the output by one binary number each time a clock pulse is applied. 26. What is up/down counter? A counter, which is capable of operating as an up counter or down counter, depending on a control lead. 27. What is a ripple counter? A ripple counter is nothing but an asynchronous counter, in which the output of the flip-flop changes state like a ripple in water. 28. What are the uses of a counter? i) The digital clock ii) Auto parking control iii) Parallel to serial data conversion. 29. What is meant by modulus of a counter? By the term modulus of a counter we say it is the number of states through which a counter can progress. 30. What is meant by natural count of a counter? By the term natural count of a counter we say that the maximum number of states through which a counter can progress. 31. A ripple counter is a---- ---- --- - sequential counter. Ans: Synchronous 32. What is a modulo counter? A counter that counts from 0 to T is called as modulo counter. 33. A counter that counts from to T is called a modulo counter. True or False. Ans: True 34. The number of flip-flops required for modulo-18 counter is---- --Ans: five. 35. What is a ring counter? A counter formed by circulating a ‘bit’ in a shift register whose serial output has been connected to its serial input. 36. What is BCD counter? A BCD counter counts in binary coded decimal from0000 to 1001 and back to0000. Because of the return to0000 after a count of 1001, a BCD counter does not have a regular pattern as in a straight binary counter. 37. What are the uses of a ring counter? i) Control section of a digital system.

ii) Controlling events, which occur in strict time sequence. 38. What is a register? Memory elements capable of storing one binary word. It consists of a group of flipflops, which store the binary information. 39. What is Johnson counter? It is a ring counter in which the inverted output is fed into the input. It is also know as a twisted ring counter. 40. What is a shift register? In digital circuits, datas are needed to be moved into a register (shift in) or moved out of a register (shift out). A group of flip-flops having either or both of these facilities is called a shift register. 41. What is serial shifting? In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the technique is called serial shifting. 42. Write the uses of a shift register. i) Temporary data storage ii) Bit manipulations. 43. What is a cycle counter? A cycle counter is a counter that outputs a stated number of counts and then stops. 44. Define state of sequential circuit? The binary information stored in the memory elements at any given time defines the “state” of sequential circuits. 45. Define state diagram. A graphical representation of a state table is called a state diagram. 46. What is the use of state diagram? i) Behavior of a state machine can be analyzed rapidly. ii) It can be used to design a machine from a set of specification. 47. What is state table? A table, which consists time sequence of inputs, outputs and flip-flop states, is called state table. Generally it consists of three section present state, next state and output. 48. What is a state equation? A state equation also called, as an application equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation denotes the next state of the flip-flop and the right side; a Boolean function specifies the present state. 49. What is meant by race around condition? In JK flip-flop output is fed back to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are

both high then output toggles continuously. This condition is known as race around condition. 50. How many bits would be required for the product register if the multiplier has 6 bits and the multiplicand has 8 bits? The product register is 14-bit width with extra bit at the left end indicating a temporary storage for any carry, which is generated when the multiplicand is added to the accumulator 51. Define sequential circuits. Their outputs are a function of the inputs and the state of memory elements. The state of memory elements, in turn, is a function of previous inputs. 52. What is the classification of sequential circuits? The sequential circuits are classified on the basis of timing of their signals into two types. They are, 1) Synchronous sequential circuit. 2) Asynchronous sequential circuit. 53. Define Flip flop. The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state. 54. What are the different types of flip-flop? There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop and T flip-flop 55. What is the operation of D flip-flop? In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset. 56. What is the operation of JK flip-flop? When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and J are low the output does not change When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

57. What is the operation of T flip-flop? T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles. 58. Define race around condition. In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’. 59. What is a master-slave flip-flop? A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave. 60. Define rise time. The time required to change the voltage level from 10% to 90% is known as rise time (tr). 61. Define fall time. The time required to change the voltage level from 90% to 10% is known as fall time (tf). 62. Define skew and clock skew. The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew. 63. Define setup time. The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup. 64. Define hold time. The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold. 65. Define propagation delay. A propagation delay is the time required to change the output after the application of the input. 66. Define registers.

A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has storing a group of n flip-flops and is capable of any binary information/number containing n-bits.

67. Define shift registers. The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers. 68. What are the different types of shift type? There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register 69. Explain the flip-flop excitation tables for RS FF. RS flip-flop In RS flip-flop there are four possible transitions from the present state to the next state. They are, 0 0 transition: This can happen either when R=S=0 or when R=1and S=0. 0 1 transition: This can happen only when S=1 and R=0. 1 0 transition: This can happen only when S=0 and R=1. 1 1 transition: This can happen either when S=1 and R=0 or S=0 and R=0. 70. Define sequential circuit? In sequential circuits the output variables dependent not only on the present input Variables but they also depend up on the past history of these input variables. 71. Give the comparison between combinational circuits and sequential circuits. Combinational circuits Memory unit is not required circuit 72. What do you mean by present state? The information stored in the memory elements at any given time defines the Sequential circuits Memory unity is required

Parallel adder is a combinational Serial adder is a sequential circuit

present state of the sequential circuit. 73. What do you mean by next state? The present state and the external inputs determine the outputs and the next state of the sequential circuit. 74. State the types of sequential circuits? 1. Synchronous sequential circuits 2. Asynchronous sequential circuits 75. Define synchronous sequential circuit In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time. 76. The following wave forms are applied to the inputs of SR latch. Determine the Q waveform Assume initially Q = 1

Here the latch input has to be pulsed momentarily to cause a change in the latch output state, and the output will remain in that new state even after the input pulse is over. Uni t – V Part - A 1. What is SM chart? Just as flow charts are useful in software design, flow charts are useful in the hardware design of digital systems. These flow charts are called as State Machine Flow Charts or SM charts. SM charts are also called as ASMC (Algorithmic State machine chart). ASM chart describes the sequential operation in a digital system. 2. What are the three principal components of SM charts? The 3 principal components of SM charts are state box, decision box & Conditional output box. 3. What is decision box? A diamond shaped symbol with true or false branches represents a decision box. The condition placed in the box is a Boolean expression that is evaluated to determine which branch to take in SM chart.

4. What is link path? How many entrance paths & exit paths are there in SM block? A path through an SM block from entrance to exit is referred to as link path. An SM block has one entrance and exit path. 5. Differentiate ASM chart and conventional flow chart? A conventional Flow chart describes the sequence of procedural steps and decision paths for an algorithm without concern for their time relationship. The ASM chart describes the sequence of events as well as the timing relationships between the states of a sequential controller and the events that occur while going from one state to the next. 6. What is flow table? During the design of synchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such table is called Flow table. 7. What is primitive flow table? A flow table is called Primitive flow table because it has only one stable state in each row. 8. Define race condition. A race condition is said to exist in a synchronous sequential circuit when two or more binary state variables change, the race is called non-critical race. 9. Define critical & non-critical race with example. The final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called non-critical race. The final stable state that the circuit reaches depends on the order in which the state variables change, the race is called critical race. 10. How can a race be avoided? Races can be avoided by directing the circuit through intermediate unstable states with a unique state – variable change. 11. Define cycle and merging? When a circuit goes through a unique sequence of unstable states, it is said to have a cycle. The grouping of stable states from separate rows into one common row is called merging. 12. Give state – reduction procedure. The state – reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined in to one if they can be shown to be equivalent. 13. Define hazards. Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. 14. Does Hazard occur in sequential circuit? If so what is the problem caused?

Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may result in a transition to a wrong state. 15. Give the procedural steps for determining the compatibles used for the purpose of merging a flow table. The purpose that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table can be divided into 3 procedural steps. i. Determine all compatible pairs by using the implication table. ii. Find the maximal compatibles using a Merger diagram iii. Find a minimal collection of compatibles that covers all the states and is closed. 16. What are the types of hazards? 1) Static – 0 hazards 2) Static – 1 hazard 3) Dynamic hazards 17. What is mealy and Moore circuit? Mealy circuit is a network where the output is a function of both present state and input. Moore circuit is a network where the output is function of only present state. 18. Differentiate Moore circuit and Mealy circuit? Moore circuit a. It is output is a function of present state only. b. Input changes do not affect the output. c. Moore circuit requires more number of states for implementing same function. Mealy circuit a. It is output is a function of present state as well as the present input. b. Input changes may affect the output of the circuit. c. It requires less numbers of states for implementing same function.

19. How can the hazards in combinational circuit be removed? Hazards in the combinational circuits can be removed by covering any two min terms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit. 20. How does an essential hazard occur? An essential hazard occurs due to unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard. 21. What is Timing diagram? Timing diagrams are frequently used in the analysis of sequential network. These diagrams show various signals in the network as a function of time. 22. What is setup and hold time? The definite time in which the input must be maintained at a constant value prior to the application of the pulse is setup time. The definite time is which the input must not

chance after the application of the positive or negative going transition of the pulse based on the triggering of the pulse. 23. Define bit time and word time. The time interval between clock pulses is called bit time. The time required to shift the entire contents of a shift register is called word time. 24. What is bi-directional shift register and unidirectional shift register? A register capable of shifting both right and left is called bi-directional shift register. A register capable of shifting only one direction is called unidirectional shift register. 25. Define equivalent state. If a state machine is started from either of two states and identical output sequences are generated from every possible set of sequences, then the two states are said to be equivalent. 26. If a shift register can be operated in all possible ways then it is called as----------Ans: Univerasal register: It can be operated in all possible modes with bi- directional shift facility. 27. What is gate delay? If the change in output is delayed by a time ε with respect to the input. We say that the gate has a propagation delay of ε. normally propagation delay for 0 to 1 output (ε1) may be different than the delay for 1 to 0 changes (ε2). 28. Define state reduction algorithm. State reduction algorithm is stated as “Two states are said to be equivalent if, for each member of the set of inputs they give the same output and send the circuit either to the same state or to an equivalent state. When two states are equivalent, one of them can be removed without altering the input-output relation. 29. What is meant by level triggering? In level triggering the output of the flip-flop changes state or responds only when the clock pulse is present. 30. Write the uses of a shift register. i) Temporary data storage. ii) Bit manipulations. 31. What is meant by flow table? During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such a table is called a flow table. 32. What are the problems involved in asynchronous circuits? The asynchronous sequential circuits have three problems namely, a. Cycles

b. Races c. Hazards 33. Define cycles? If an input change includes a feedback transition through more than unstable state then such a situation is called a cycle. 34. Define primitive flow table? A primitive flow table is a flow table with only one stable total state in each row. Remember that a total state consists of the internal state combined with the input. 35. Define merging? The primitive flow table has only one stable state in each row. The table can be reduced to a smaller numbers of rows if two or more stable states are placed in the same row of the flow table. The grouping of stable states from separate rows into one common row is called merging. 36. Define Asynchronous sequential circuit? In asynchronous sequential circuits change in input signals can affect memory element at any instant of time. 37. Give t h e c o m p a r i s o n b e t w e e n s y n c h r o n o u s & A s y n c h r o n o u s s e q u e n t i a l circuits? Synchronous sequential circuits Memory elements are clocked flipflops Easier to design 38. What is race around condition? In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition. 39. Give the comparison between synchronous & Asynchronous counters. Asynchronous counters Synchronous counters In this type of counter flip-flops are In this type there is no connection between connected in such a way that output of 1st output of first flip-flop and clock input of flip-flop drives the clock for the next flip- the next flip - flop flop. Asynchronous sequential circuits. Memory elements are either unlocked flip - flops or time delay elements. More difficult to design

All

the

flip-flops

are

Not

clocked All

the

flip-flops

are

clocked

simultaneously

simultaneously

40. The tPd for each flip-flop is 50 ns. Determine the maximum operating frequency for MOD - 32 ripple counter f max (ripple) = 5 x 50 ns = 4 MHZ 41. What are secondary variables? -present state variables in asynchronous sequential circuits 42. What are excitation variables? -next state variables in asynchronous sequential circuits 43. What is fundamental mode sequential circuit? -input variables changes if the circuit is stable -inputs are levels, not pulses -only one input can change at a given time 44. What is pulse mode circuit? -inputs are pulses -widths of pulses are long for circuit to respond to the input -pulse width must not be so long that it is still present after the new state is reached 45. What is the significance of state assignment? In synchronous circuits-state assignments are made with the objective of circuit reduction. Asynchronous circuits-its objective is to avoid critical races 46. When does race condition occur? -Two or more binary state variables change their value in response to the change in i/p variable 47. What is non critical race? -final stable state does not depend on the order in which the state variable changes -race condition is not harmful 48. What is critical race? -final stable state depends on the order in which the state variable changes -race condition is harmful 49. When does a cycle occur? -asynchronous circuit makes a transition through a series of unstable state 50. What are the different techniques used in state assignment?

-shared row state assignment -One hot state assignment 51. What are the steps for the design of asynchronous sequential circuit? -construction of primitive flow table -reduction of flow table -state assignment is made -realization of primitive flow table 52. What is hazard? -unwanted switching transients 53. What is static 1 hazard? -output goes momentarily 0 when it should remain at 1 54. What is static 0 hazard? -output goes momentarily 1 when it should remain at 0 55. What is dynamic hazard? -output changes 3 or more times when it changes from 1 to 0 or 0 to 1 56. What is the cause for essential hazards? -unequal delays along 2 or more path from same input 57. What is flow table? -state table of an synchronous sequential network 58. What is primitive flow chart? -One stable state per row

59. What is combinational circuit? Output depends on the given input. It has no storage element. 60. Define merger graph. The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn. 61. Define closed covering A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering. 62. Define state table.

For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table. 63. Define total state The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit. 64. What are the steps for the design of asynchronous sequential circuit? 1. Construction of a primitive flow table from the problem statement. 2. Primitive flow table is reduced by eliminating redundant states using the state reduction 3. State assignment is made 4. The primitive flow table is realized using appropriate logic elements. 65. Define primitive flow table: It is defined as a flow table which has exactly one stable state for each row in the table. The design process begins with the construction of primitive flow table. 66. What are the types of asynchronous circuits? 1. Fundamental mode circuits 2. Pulse mode circuits 67. Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous circuit. In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races. 68. What are races? When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner. 69. Define non critical race. If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race. 70. Define critical race? If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.

71. What is a cycle? A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed. 72. Write a short note on fundamental mode asynchronous circuit. Fundamental mode circuit assumes that. The input variables change only when the circuit is stable. Only one input variable can change at a given time and inputs are levels and not pulses. 73. Write a short note on pulse mode circuit. Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the pulses is long enough for the circuit to respond to the input and the pulse width must not be so long that it is still present after the new state is reached. 74. Define secondary variables The delay elements provide a short term memory for the sequential circuit. The present state and next state variables in asynchronous sequential circuits are called secondary variables. 75. Define flow table in asynchronous sequential circuit. In asynchronous sequential circuit state table is known as flow table because of the behavior of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to flow from one to another. 76. A pulse mode asynchronous machine has two inputs. If produces an output whenever two consecutive pulses occur on one input line only. The output remains at 1 until a pulse has occurred on the other input line. Write down the state table for the machine.

77. What is fundamental mode? A transition from one stable state to another occurs only in response to a change in the input state. After a change in one input has occurred, no other change in any input occurs until the circuit enters a stable state. Such a mode of operation is referred to as

a fundamental mode. 78. Write short note on shared row state assignment. Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable. 79. Write short note on one hot state assignment. The one hot state assignment is another method for finding a race free state assignment. In this method, only one variable is active or hot for each row in the original flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions. 80. What is edge-triggered flip-flop? The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock. Part - B UNIT – I 1. Simplify the following Boolean function by using Tabulation method F (w, x, y, z) =Σ(0,1,2,8,10,11,14,15)  Determination of Prime Implicants  Selection of prime Implicants 2. Simplify the following Boolean functions by using K’Map in SOP & POS. F (w, x, y, z) =Σ(1,3,4,6,9,11,12,14)  Find the Number of variable map  Draw the Map  Simplification of SOP & POS 3. Simplify the following Boolean functions by using K’Map in SOP & POS. F (w, x, y, z) =Σ(1,3,7,11,15) + d(0,2,5)  Find the Number of variable map  Don’t care treat as variable X.  Draw the Map  Simplification of SOP & POS

4. Reduce the given expression. [(AB)1+ A1 +AB] using Boolean algebra Laws and theorems 5. Reduce the given function minimum number of literals. (ABC)1+ A1)+AC Reduce the expression using Boolean algebra Laws and theorems UNIT II 1. Design a combinational logic circuit to convert the Gray code into Binary code  Truth table  K’Map Simplification  Draw the Logic Diagram 2. Draw the truth table and logic diagram for full-Adder  Truth table  K’Map Simplification  Draw the Logic Diagram 3. Draw the truth table and logic diagram for full-Subtractor  Truth table  K’Map Simplification  Draw the Logic Diagram 4. Explain Binary parallel adder.  Explanation  Logic diagram 5. Design a combinational logic circuit to convert the BCD to Binary code  Truth table  K’Map Simplification  Draw the Logic Diagram 6. Design a 4-bit binary adder/subtractor circuit.
 Basic equations Comparison of equations  Design using twos complement Circuit diagram

7. Design and explain a comparator to compare two identical words.
 Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0  If two numbers equal P = Ai  Obtain the logic Expression. 

Bi

Obtain the logic diagram.

8. Explain in detail the look ahead carry generator.
 Block diagram

 Explanation Logic diagram

UNIT III 1. Implement the following function using PLA. A (x, y, z) =Σm (1, 2, 4, 6) B (x, y, z) =Σm (0, 1, 6, 7) C (x, y, z) =Σm (2, 6)  K’Map Simplification  PLA table  PLA Logic Diagram 2. Implement the following function using PAL. W (A, B, C, D) =Σm (2, 12, 13) X (A, B, C, D) =Σm (7, 8, 9, 10, 11, 12, 13, 14, 15) Y (A, B, C, D) =Σm (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) Z (A, B, C, D) =Σm (1, 2, 8, 12, 13)  K’Map Simplification  PAL Logic diagram 3. Implement the given function using multiplexer  Implementation table  Multiplexer Implementation 4. Explain about Encoder and Decoder?  Definition  Truth table  Logic Diagram 5. Explain about 4 bit Magnitude comparator?  Explanation  Logic Diagram 6. Design a logic circuit to convert the BCD code to Excess – 3 code.
 Truth Table for BCD to Excess – 3 conversion.  K-map simplification  Logic circuit implementing the Boolean Expression

7. Explain in detail about PLA and PAL.
 Logic difference between Prom & PLA  Logic diagram implementing a function  Logic difference between Prom & PAL  Logic diagram implementing a function

8. Implement F(A,B,C,D)= (1,3,4,11,12,13,14,15) using multiplexer.
 Implementation  Table  Explanation.

9. Implement W(A,B,C,D) = (2,12,13) X(A,B,C,D) = (7,8,9,10,11,12,13,14,15) Y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15) Z (A,B,C,D) = (1,2,8,12,13) using PAL
 Table  PAL implementation

UNIT IV 1. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6. Use JK Flip-flop.  State diagram  Excitation State table  K’Map Simplification  Logic diagram 2. Describe the operation of SR flip-flop  Logic Diagram  Graphical Symbol  Characteristics table  Characteristics equation  Excitation Table 3. The count has a repeated sequence of six states, with flip flops B and C repeating the binary count 00, 01, 10 while flip flop A alternates between 0 and 1 every three counts. Designs with JK flip-flop  State diagram  Excitation State table  K’Map Simplification  Logic diagram 4. Design a 3-bit T flip-flop counter  State diagram

 Excitation State table

 K’Map Simplification  Logic diagram 5. Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram.
 BCD Ripple Counter Count sequence  Truth Table  State diagram representing the Truth Table  Truth Table for the J-K Flip Flop  Logic Diagram

6. Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected.
 Construct state diagram  Obtain the flow table  Obtain the flow table & output table  Transition table Select flip flop Excitation table Logic diagram

7. Explain in detail about serial in serial out shift register.
 Block diagram Theoretical explanation  Logic diagram  Working

UNIT V 1. Design an Asynchronous sequential circuit using SR latch with two inputs A and B and one output y. B is the control input which, when equal to 1, transfers the input A to output y. when B is 0, the output does not change, for any change in input.  State Table
 Primitive Flow Table  Formal Reduction (Implication Method)

 Merging  Reduced Table  K’Map Simplification  Logic Diagram 2. Give hazard free relation for the following Boolean function.

F (A, B, C, D) =Σm (0, 2, 6, 7, 8, 10, 12)  K’Map simplification  Create Hazard free link 3. Explain about Hazards?  Explain Static Hazard  Explain Dynamic Hazard 4. Explain about Races?  Explain Critical Race  Explain Non-Critical Race 5. Design T Flip flop from Asynchronous Sequential circuit?  State Table  Primitive Flow Table  Formal Reduction (Implication Method)  Merging  Reduced Table  K’Map Simplification  Logic Diagram 6. Explain with neat diagram the different hazards and the way to eliminate them.  Classification of hazards  Static hazard & Dynamic hazard definitions  K map for selected functions Method of elimination Essential hazards

7. State with a neat example the method for the minimization of primitive flow table.  Consider a state diagram  Obtain the flow table  Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions  Plot the reduced flow table 8. Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0.  Obtain the state diagram  Obtain the flow table  Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions  Plot the reduced flow table  Obtain transition table  Excitation table

 Logic diagram

9. Explain in detail about Races.  Basics of races  Problem created due to races  Classification of races Remedy for races cycles 10. Explain the different methods of state assignment  Three row state assignment Shared row state assignment  Four row flow table  Multiple row state assignment  Prevention of races. ADDITIONAL QUESTIONS Unit – I Boolean algebra and Logic Gates Part A 1. Find the hexadecimal equivalent of the decimal number 256 2. Find the octal equivalent of the decimal number 64 3. What is meant by weighted and non-weighted coding? 4. Convert A3BH and 2F3H into binary and octal respectively 5. Find the decimal equivalent of (123)9 6. Find the octal equivalent of the hexadecimal number AB.CD 7. Encode the ten decimal digits in the 2 out of 5 code 8. Show that the Excess – 3 code is self –complementing 9. Find the hexadecimal equivalent of the octal number 153.4 10. Find the decimal equivalent of (346)7 11. A hexadecimal counter capable of counting up to at least (10,000)10 is to be constructed.What is the minimum number of hexadecimal digits that the counter must have? 12. Convert the decimal number 214 to hexadecimal 13. Convert 231.3 4 to base 7 14. Give an example of a switching function that contains only cyclic prime implicant 15. Give an example of a switching function that for which the MSP from is not unique. 16. Express x+yz as the sum of minterms 17. What is prime implicant? 18. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D=1 19. What are ‘minterms’ and ‘maxterms’? 20. State and prove Demorgan’s theorem 21. Find the complement of x+yz 22. Define the following: minterm and term 23. State and prove Consensus theorem 24. What theorem is used when two terms in adjacent squares of K map are combined? 25. How will you use a 4 input NAND gate as a 2 input NAND gate? 26. How will you use a 4 input NOR gate as a 2 input NOR gate?

27. Show that the NAND connection is not associative 28. What happens when all the gates is a two level AND-OR gate network are replaced by NOR gates? 29. What is meant by multilevel gates networks? 30. Show that the NAND gate is a universal building block 31. Show that a positive logic NAND gate is the same as a negative logic NOT gate 32. Distinguish between positive logic and negative logic 33. Implement AND gate and OR gate using NAND gate 34. What is the exact number of bytes in a system that contains (a) 32K byte, (b) 64M bytes, and (c) 6.4G byte? 35. List the truth table of the function: F = x y + x y’ + y ’z Part B 1. (a) Explain how you will construct an (n+1) bit Gray code from an n bit Gray code (b) Show that the Excess – 3 code is self -complementing 2. (a) Prove that (x1+x2).(x1’. x3’+x3) (x2’ + x1.x3) =x1’x2 (b) Simplify using K-map to obtain a minimum POS expression: (A’ + B’+C+D) (A+B’+C+D) (A+B+C+D’) (A+B+C’+D’) (A’+B+C’+D’) (A+B+C’+D) 3. Reduce the following equation using Quine McClucky method of minimization F (A,B,C,D) = ∑m(0,1,3,4,5,7,10,13,14,15) 4. (a) State and Prove idempotent laws of Boolean algebra. (b) using a K-Map ,Find the MSP from of F= ∑(0,4,8,12,3,7,11,15) +∑d(5) 5 (a) With the help of a suitable example, explain the meaning of an redundant prime implicant (b) Using a K-Map, Find the MSP form of F= ∑ (0-3, 12-15) + ∑d (7, 11) 6 (a) Simplify the following using the Quine – McClusky minimization technique D = f(a,b,c,d) = ∑ (0,1,2,3,6,7,8,9,14,15).Does Quine –McClusky take care of don’t care conditions? In the above problem, will you consider any don’t care conditions? Justify your answer (b) List also the prime implicants and essential prime implicants for the above case 7 (a) Determine the MSP and MPS focus of F= ∑ (0, 2, 6, 8, 10, 12, 14, 15) (b) State and Prove Demorgan’s theorem 8 Determine the MSP form of the Switching function F = ∑ ( 0,1,4,5,6,11,14,15,16,17,20- 22,30,32,33,36,37,48,49,52,53,56,63) 9. (a) Determine the MSP form of the Switching function F( a,b,c,d) =∑(0,2,4,6,8) + ∑d(10,11,12,13,14,15) (b) Find the Minterm expansion of f(a,b,c,d) = a’(b’+d) + acd’ 10 Simplify the following Boolean function by using the Tabulation Method F= ∑ (0, 1, 2, 8, 10, 11, 14, 15) 11 S t a t e and Prove the postulates of Boolean algebra 12 ( a) Find a Min SOP and Min POS for f = b’c’d + bcd + acd’ + a’b’c + a’bc’d 13 F i n d an expression for the following function usingQuine McCluscky method F= ∑ (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30) 14 S t a t e and Prove the theorems of Boolean algebra with illustration

15 F i n d the MSP representation for F(A,B,C,D,E) = ∑m(1,4,6,10,20,22,24,26) + ∑d (0,11,16,27) using K-Map method. Draw the circuit of the minimal expression using only NAND gates 16 ( a) Show that if all the gates in a two – level AND-OR gate networks are replaced by NAND gates the output function does not change (b) Why does a good logic designer minimize the use of NOT gates? 17 Simplify the Boolean function F(A,B,C,D) = ∑ m (1,3,7,11,15) + ∑d (0,2,5) .if don’t care conditions are not taken care, What is the simplified Boolean function .What are your comments on it? Implement both circuits 18 (a) Show that if all the gate in a two – level OR-AND gate network are replaced by NOR gate, the output function does not change. (b) Implement Y = (A+C) (A+D’) ( A+B+C’) using NOR gates only 19 (a) F3 = f(a,b,c,d) = ∑ (2,4,5,6) F2 = f(a,b,c,d) = ∑ (2,3,,6,7) F1 = f(a,b,c,d) = ∑ (2,5,6,7) .Implement the above Boolean functions (i) When each is treated separately and (ii)When sharing common term (b) Convert a NOR with an equivalent AND gate 20 Implement the Switching function whose octal designation is 274 using NAND gates only 21 Implement the Switching function whose octal designation is 274 using NOR gates only 22 ( a) Show that the NAND operation is not distributive over the AND operation (b) Find a network of AND and OR gate to realize f(a,b,c,d) = ∑ m (1,5,6,10,13,14) 23 What is the advantage of using tabulation method? Determine the prime implicants of the following function using tabulation method F( W,X,Y,Z) = ∑(1,4,6,7,8,9,10,11,15) 23 ( a) Explain about common postulates used to formulates various algebraic structures (b) Given the following Boolean function F= A”C + A’B + AB’C + BC Express it in sum of minterms & Find the minimal SOP expression Unit – II Combinational Logic Part A 1. How will you build a full adder using 2 half adders and an OR gate? 2. Implement the switching function Y= BC’ + A’B + D 3. Draw 4 bit binary parallel adder 4. Write down the truth table of a full adder 5. Write down the truth table of a full sub tractor 6. Write down the truth table of a half sub tractor 7. Find the syntax errors in the following declarations (note that names for primitive gates are optional): Module Exmp1-3(A, B, C, D, F) inputs A,B,C, and g1(A,B,D); not (D,B,A);

OR (F,B,C); endmodule ; 8. Draw the logic diagram of the digital circuit specified by module circt (A,B,C,D,F); input A,B,C,D; output F; wire w,x,y,z,a,d; and (x,B,C,d); and y,a,C); and (w,z,B); or (z,y,A); or (F,x,w); not (a,A); not (d,D); endmodule 9. Define Combinational circuits 10. Define Half and Full adder 11. Give the four elementary operations for addition and subtraction 12. Design the combinational circuit with 3 inputs and 1 output. The output is 1 when the binary value of the inputs is less than 3.The output is 0 otherwise 13. Define HDL 14. What do you mean by carry propagation delay? 15. What is code converter? 16. Give short notes on Logic simulation and Logic synthesis 17. What do you mean by functional and timing simulation? 18. What do you mean by test bench? 19. Give short notes on simulation versus synthesis 20. Define half sub tractor and full sub tractor Part B 1 Design a 4 bit magnitude comparator to compare two 4 bit number 2 Construct a combinational circuit to convert given binary coded decimal number into an Excess 3 code for example when the input to the gate is 0110 then the circuit should generate output as 1001 3 Design a combinational logic circuit whose outputs are F1 = a’bc + ab’c and F2 = a’ + b’c + bc’ 4 (a) Draw the logic diagram of a *-bit 7483 adder (b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor 5 (a) Draw a diode ROM, which translates from BCD 8421 to Excess 3 code (b) Distinguish between Boolean addition and Binary addition 6 Realize a BCD to Excess 3 code conversion circuit starting from its truth table 7 (a) Design a full sub tractor (b) How to it differ from a full sub tractor 8 Design a combinational circuit which accepts 3 bit binary number and

converts its equivalent excess 3 codes 9 Derive the simplest possible expression for driving segment “a” through ‘g’ in an 8421 BCD to seven segment decoder for decimal digits 0 through 9 .Output should be active high (Decimal 6 should be displayed as 6 and decimal 9 as 9) 10 Write the HDL description of the circuit specified by the following Boolean function (i) Y= (A+B+C) (A’+B’+C’) (ii) F= (AB’ + A’B) (CD’+C’D) (iii) Z = ABC + AB’ + A(D+B) (iv) T= [(A+B} {B’+C’+D’)]

11 Design 16 bit adder using 4 7483 ICs Unit – III Design with MSI Devices Part A 1. What is a decoder and obtain the relation between the number of inputs ‘n’ and outputs ‘m’ of a decoder? 2. Distinguish between a decoder and a demultiplexer 3. Using a single IC 7485 ; draw the logic diagram of a 4 bit comparator 4. What is decoder? 5. What do you mean by encoder? 6. Write the short notes on priority encoder 7. What is multiplexer? Draw the logic diagram of8 to 1 line multiplexer 8. What do you mean by comparator? 9. Write the HDL description of the circuit specified by the following Boolean function X=AB+ACD+BC’ 10. How does ROM retain information? 11. Distinguish between PAL and PLA 12. Give the classification of memory 13. What is refreshing? How it is done? 14. What is Hamming code? 15. Write a short note on memory decoding 16. List the basic types of programmable logic devices 17. What is PAL? How it differ from PROM and PLA? 18. Write short notes on – PROM, EPROM, EEPROM 19. How many parity bits are required to form Hamming code if massage bits are 6? 20. How to find the location of parity bits in the Hamming code? 21. Generate the even parity hamming codes for the following binary data 1101, 1001 22. A seven bit Hamming code is received as 11111101. What is the correct code? 23. Compare static RAMs and dynamic RAMs 24. Define Priority encoder 25. Define PLDs Part B

Implement the switching function F= ∑(0,1,3,4,7) using a 4 input MUX and explain Explain how will build a 64 input MUX using nine 8 input MUXs State the advantages of complex MSI devices over SSI gates Implement the switching function F(A,B,C) = ∑ ( ,2,4,5) using the DEMUX 74156 Implement the switching function F= ∑(0,1,3,4,12,14,15) using an 8 input MUX Explain how will build a 16 input MUX using only 4 input MUXs Explain the operation of 4 to 10 line decoder with necessary logic diagram Draw a neat sketch showing implementation of Z1 = ab’d’e + a’b’c’e’ + bc + de , Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 = a’c’e +ce using a 5*8*4 PLA 9. Implement the switching functions: Z1 = ab’d’e + a’b’c’e’ + bc + de , Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 = a’c’e +ce Using a 5*8*4 PLA 10 Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array 11.Design a combinational circuit using a ROM ,that accepts a 3- bit number and generates an output binary number equal to the square of the given input number Unit – IV Synchronous Sequential Logic Part A 1. Derive the characteristic equation of a D flip flop 2. Distinguish between combinational and sequential logic circuits 3. What are the various types of triggering of flip-flops? 4. Derive the characteristic equation of a T flip flop 5. Derive the characteristic equation of a SR flip flop 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. What is race round condition? How it is avoided? List the functions of asynchronous inputs Define Master slave flip flop Draw the state diagram of ‘T’ FF, ‘D’ FF Define Counter What is the primary disadvantage of an asynchronous counter? How synchronous counters differ from asynchronous counters? Write a short note on counter applications Compare Moore and Mealy models When is a counter said to suffer from lock out? What is the minimum number of flip flops needed to build a counter of modulus z 8? State the relative merits of series and parallel counters What are Mealy and Moore machines? When is a counter said to suffer from lockout? What is the difference between a Mealy machine and a Moore Machines? Distinguish between synchronous and asynchronous sequential logic circuits Derive the characteristic equation of a JK flip flop How will you convert a JK flip flop into a D flip flop What is mean by the term ‘edge triggered’?

1. 2. 3. 4. 5. 6. 7. 8.

25. What are the principle differences between synchronous and asynchronous networks? 26. What is lockout? How it is avoided? 27. What is the pulse mode operation of asynchronous sequential logic circuits not very popular? 28. What are the advantages of shift registers? 29. What are the applications of a shift register? 30. How many flip –flops are needed to build an 8 bit shift register? 31. A shift register comprises of JK flip-flops. How will you complement of the counters of the register 32. List the basic types of shift registers in terms of data movement. 33. Write short notes on PRBS generator 34. Give the HDL dataflow description for T flip - flop 35. Give the HDL dataflow description for JK flip – flop Part B 1 Draw the state diagram and characteristics equation of T FF, D FF and JK FF 2 (a) What is race around condition? How is it avoided? (b) Draw the schematic diagram of Master slave JK FF and input and output waveforms.Discuss how it prevents race around condition 3 Explain the operation of JK and clocked JK flip-flops with suitable diagrams 4 Draw the state diagram of a JK flip- flop and D flip – flop 5 Design and explain the working of a synchronous mod – 3 counter 6 Design and explain the working of a synchronous mod – 7 counter 7 Design a synchronous counter with states 0,1, 2,3,0,1 …………. Using JK FF 8 Using SR flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 9 Using JK flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 10 ( a) Discuss a decade counter and its working principle (b) Draw as asynchronous 4 bit up-down counter and explain its working 11 (a) How is the design of combinational and sequential logic circuits possible with PLA? (b) Mention the two models in a sequential circuit and distinguish between them 12 D e s i g n a modulo 5 synchronous counter using JK FF and implement it. Construct its timing diagram 13 A sequential machine has one input line where 0’s and 1’s are being incident. The machine has to produce a output of 1 only when exactly two 0’s are followed by a ‘1’ or exactly two 1’s are followed by a ‘0’.Using any state assignment and JK flipflop,synthesize the machine 14 Using D flip –flop ,design a synchronous counter which counts in the sequence 000, 001, 010, 011, 100, 1001,110,111,000 15 U s i n g JK flip-flops, design a synchronous sequential circuit having one and one output. the output of the circuit is a 1 whenever three consecutive 1’s are observed. Otherwise the output is zero 16 Design a binary counter using T flip – flops to count in the following

sequences: (i) 000,001,010,011,100,101,110,111,000 (ii) 000,100,111,010,011,000 17 (a) Design a synchronous binary counter using T flip – flops (b) Derive the state table of a serial binary adder 18. Design a 3 bit binary Up-Down counter 19. (i) Summarize the design procedure for synchronous sequential circuit (ii) Reduce the following state diagram

Unit – V Asynchronous Sequential Logic Part A 1. Distinguish between fundamental mode and pulse mode operation of asynchronous sequential circuits 2. What is meant by Race? 3. What is meant by critical race? 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. What is meant by race condition in digital circuit? Define the critical rate and non critical rate What are races and cycles? What is the significance of state assignment? What are the steps for the analysis of asynchronous sequential circuit? What are the steps for the design of asynchronous sequential circuit? Write short notes on (a) Shared row state assignment (b) One hot state assignment What are Hazards? What is a static 1 hazard? What is a static 0 hazard? What is dynamic hazard? Define static 1 hazard, static 0 hazards, and dynamic hazard? Describe how to detect and eliminate hazards from an asynchronous network? What is static hazard?

18. List the types of hazards? 19. How to eliminate the hazard? 20. Draw the wave forms showing static 1 hazard? Part B 1. What is the objective of state assignment in asynchronous circuit? Give hazard – free realization for the following Boolean function f(A,B,C,D) = ∑M(0,2,6,7,8,10,12) 2. Summarize the design procedure for asynchronous sequential circuit a. Discuss on Hazards and races b. What do you know on hardware descriptive languages? 3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z Wherever Y is 1, input X is transferred to Z .When Y is 0; the output does not change for any change in X.Use SR latch for implementation of the circuit 4. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock .the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output 5. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X. 6. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and one output Z. An output z =1 is to occur only during the input state xy = 01 and then if the only if the input state xy =01 is preceded by the input sequence. 7. A pulse mode asynchronous machine has two inputs. It produces an output whenever two consecutive pulses occur on one input line only .The output remains at ‘1’ until a pulse has occurred on the other input line. Draw the state table for the machine. 8. (a) How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine (b) State the restrictions on the pulse width in a pulse mode asynchronous sequential machine 9. Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence X1X2 = 00,01,11 causes the output to become 1.The next input change then causes the output to return to 0.No other inputs will produce a 1 output

UNIVERSITY QUESTION

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