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Basic Concepts in VLSI Physical Design Automation
VLSI Design Cycle
• • • • Large number of devices Optimization requirements for high performance Time-to-market competition Cost
VLSI Design Cycle (contd.)
1. 2. 3. 4. 5. 6. 7. 8. System specification Functional design Logic design Circuit design Physical design Design verification Fabrication Packaging, testing, and debugging
• Converts a circuit description into a geometric description.
– This description is used for fabrication of the chip. 1. 2. 3. 4. Partitioning Floorplanning and placement Routing Compaction
Basic steps in the physical design cycle:
n-channel Transistor 7 .
n-channel Transistor Operation 8 .
n-channel Transistor Layout 9 .
p-channel MOS Transistor 10 .
Fabrication Layers 11 .
MOS Transistor Behavior 12 .
Summary of VLSI Layers 13 .
VLSI Fabrication 14 .
Silicon Wafer 15 .
General Design Rules 16 .
Types of Fabrication Errors 17 .
Width/Spacing Rules (MOSIS) 18 .
Poly-Diffusion Interaction 19 .
Contacts 20 .
Contact Spacing 21 .
M2 Contact (Via) 22 .
CMOS Layout Example 23 .
Stick Diagrams 24 .
Static CMOS Inverter 25 .
Static CMOS NAND Gate 26 .
Static CMOS NOR Gate 27 .
Static CMOS Design :: General Rule 28 .
Simple Static CMOS Design Example 29 .
Static CMOS Design Example Layout 30 .
VLSI Design Styles • Programmable Logic Devices – Programmable Logic Device (PLD) – Field Programmable Gate Array (FPGA) – Gate Array • Standard Cell (Semi-Custom Design) • Full-Custom Design 31 .
Field Programmable Gate Array (FPGA) .
Array of logic cells connected via routing channels.Introduction • • • User / Field Programmability. 33 . – Using antifuse elements. Different types of cells: – Special I/O cells. • Mainly lookup tables (LUT) with associated registers. – Logic cells. • Interconnection between cells: – Using SRAM based switches.
Gen.Xilinx XC4000 Architecture CLB CLB Slew Rate Control Passive Pull-Up. H Func. F Func. Gen. Gen. DIN F' G' H' SD D Q 1 G' H' S/R Control EC RD Y F4 F3 F2 F1 DIN F' G' H' SD D Q 1 H' F' EC RD X K Configurable Logic Blocks (CLBs) 34 . Pull-Down Vcc Switch Matrix D Q Output Buffer Pad CLB CLB Q D Delay Input Buffer Programmable Interconnect C1 C2 C3 C4 H1 DIN S/R EC S/R Control I/O Blocks (IOBs) G4 G3 G2 G1 G Func.
Gen. H Func. F Func. Gen. F' G' H' SD D Q YQ EC RD 1 G' H' S/R Control Y F4 F3 F2 F1 DIN F' G' H' SD D Q XQ EC RD 1 H' F' X K 35 . Gen.XC4000E Configurable Logic Blocks C1 C2 C3 C4 H1 DIN S/R EC S/R Control G4 G3 G2 G1 DIN G Func.
• Two Registers – Each can be configured as flip-flop or latch. – Can also implement 16x1 memory.CLB Functionalities • Two 4-input function generators – Implemented using Lookup Tables using 16x1 RAM. – Synchronous and asynchronous Set / Reset. 36 . – Independent clock polarity.
37 . . not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM G Func.Look Up Tables • • Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table Example: 4-bit address Combinatorial Logic A B C D Z A B C D 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Z 0 0 0 1 1 1 0 0 0 1 WE G4 G3 G2 G1 Capacity is limited by number of inputs. Gen. . .
XC4000X I/O Block Diagram 38 .
CLB to CLB 2) General Purpose Interconnect .Xilinx FPGA Routing 1) Fast Direct Interconnect .Uses switch matrix CLB CLB CLB CLB Switch Matrix Switch Matrix CLB CLB CLB CLB 39 .
FPGA Design Flow • Design Entry – In schematic. 40 . etc. • Implementation – Placement & Routing – Bitstream generation – Analyze timing. • Download – Directly to Xilinx hardware devices with unlimited reconfigurations. simulation. or Verilog. view layout. VHDL.
Gate Array .
which is based on generic (standard) masks. results in an array of uncommitted transistors on each GA chip. b) These uncommitted chips can be customized later. • Gate array is done with metal mask design and processing. • Gate array implementation requires a two-step manufacturing process: a) The first phase.Introduction • In view of the fast prototyping capability. which is completed by defining the metal interconnects between the transistors of the array. – Design implementation of • FPGA chip is done with user programming. the gate array (GA) comes after the FPGA. 42 .
Channeled vs. Channel-less (SoG) Approaches 44 .
• The GA chip utilization factor is higher than that of FPGA. 45 . • Current gate array chips can implement as many as hundreds of thousands of logic gates. – More customized design can be achieved with metal mask designs. • Chip speed is also higher. – The used chip area divided by the total chip area.
Standard Cell Based Design .
47 . – Requires developing full custom mask set. NAND gates.Introduction • One of the most prevalent custom design styles. characterized. and flip-flops. • Inverters. • Basic idea: – All of the commonly used logic cells are developed. and stored in a standard cell library. – A typical library may contain a few hundred cells. – Also called semi-custom design style. NOR gates. OAI gates. D-latches. complex AOI.
– A number of cells can be abutted side-by-side to form rows. and – Routing of inter-cell connections. • The input and output pins are located on the upper and lower boundaries of the cell. – Neighboring cells share a common power and ground bus. • The power and ground rails typically run parallel to upper and lower boundaries of cell.Characteristic of the Cells • Each cell is designed with a fixed height. – nMOS transistors are located closer to the ground rail while the pMOS transistors are placed closer to the power rail. – To enable automated placement of the cells. 48 .
Standard Cells 49 .
Standard Cell Layout 50 .
their heights match.Floorplan for Standard Cell Design • Inside the I/O frame which is reserved for I/O cells. – Over-the-cell routing is also possible. – Between cell rows are channels for dedicated inter-cell routing. 51 . – Neighboring cells can be abutted side-by-side. • The physical design and layout of logic cells ensure that – When placed into rows. the chip area contains rows or columns of standard cells. which provides natural connections for power and ground lines in each row.
Full Custom Design .
Introduction • The standard-cells based design is often called semi custom design. – The development cost of such a design style is prohibitively high. • In the full custom design. the entire mask design is done anew without use of any library. – The cells are pre-designed for general use and the same cells are utilized in many different chip designs. – The concept of design reuse is becoming popular to reduce design cycle time and cost. 54 .
– Static or dynamic. – Standard cells.Contd. • The most rigorous full custom design can be the design of a memory cell. 55 . – Since the same layout design is replicated. there would not be any alternative to high density memory chip design. a good compromise can be achieved by using a combination of different design styles on the same chip. • For logic chip design. data-path cells and PLAs.
orientation and placement of every transistor is done individually by the designer. full-custom design is rarely used due to the high labor cost. – Design productivity is usually very low.• In real full-custom layout in which the geometry. • In digital CMOS VLSI. – Exceptions to this include the design of high-volume products such as memory chips. 56 . per designer. high-performance microprocessors and FPGA masters. • Typically 10 to 20 transistors per day.
Comparison Among Various Design Styles Design Style FPGA Gate array Standard cell Fixed height Variable Full custom Variable Cell size Fixed Fixed Cell type Programm able Fixed Fixed Variable Cell placement Fixed In row Variable Interconnect Programm able Very fast Variable Variable Variable Design time Fast Medium Slow 57 .
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