Edition 2011

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Laboratory Manual

VLSI LAB

Prepared by:
ASHISH SHARMA ASSTT. PROFESSOR ECE DEPARTMENT NIET,JAIPUR

DEPT OF E C, NIET. VLSI LAB MANUAL

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EXPERIMENT 1 : STATIC CHARACTERISTICS OF INVERTER IN SCHEMATIC AIM : Design a CMOS inverter in schematic and simulate for Transient Characteristics. PROCEDURE : Run the VLSI software for schematic entry. From the tool bar drag and drop the one pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Out1= NOT(a)

DEPT OF E C NIET, VLSI LAB MANUAL

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Give a Clock as the input and simulate for the output. TWO INPUT OR GATE IN SCHEMATIC AIM : Design a CMOS two input NAND gate.EXPERIMENT 2 : STATIC CHARACTERISTICS OF TWO INPUT NAND GATE. Two Input NOR gate F= NOT(A+B) Two Input NAND gate OUT1=NOT(IN1 AND IN2) DEPT OF E C NIET. Two input AND gate and Two input OR gate in schematic and simulate for Transient Characteristics. Two input NOR gate. VLSI LAB MANUAL 3 . PROCEDURE : Run the VLSI software for schematic entry. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. TWO INPUT NOR GATE. TWO INPUT AND GATE.

Two Input AND gate OUT=A AND B Two Input OR gate OUT= A OR B DEPT OF E C NIET. VLSI LAB MANUAL 4 .

Paint Nwell. DEPT OF E C NIET. Label for input and outputs. Paint Ndiffussion with proper design rules. Draw POLY over the diffusions as shown in the layout diagram. Assign appropriate Clock input and simulate for the output. Put Pdiffusion. Put the appropriate diffusion contacts and do connections for VDD and GND. VLSI LAB MANUAL 5 . Connect the output contacts using the metal. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. PROCEDURE : Run the VLSI software for layout entry.EXPERIMENT 3 : STATIC CHARACTERISTICS OF INVERTER IN LAYOUT AIM : Design the layout of a CMOS Inverter and simulate for DC(Transfer) and Transient characteristics.

TWO INPUT AND GATE AND TWO INPUT AND GATE IN LAYOUT AIM : Design the layout for two input NANDgate. Connect the output contacts using the metal. three input OR gate. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. PROCEDURE : Run the VLSI software for layout entry. Label for input and outputs.EXPERIMENT 4 : TRANSFER AND TRANSIENT CHARACTERISTICS OF TWO INPUT NAND GATE. Paint Ndiffussion with proper design rules. Paint Nwell. TWO INPUT OR GATE. VLSI LAB MANUAL 6 . Draw POLY over the diffusions as shown in the layout diagram.and simulatelate for DC(Transfer) and Transient characteristics. Assign appropriate Clock input and simulate for the output. Put Pdiffusion. Put the appropriate diffusion contacts and do connections for VDD and GND. two input AND gate and two input AND gate. DEPT OF E C NIET.

DEPT OF E C NIET. VLSI LAB MANUAL 7 .

DEPT OF E C NIET. VLSI LAB MANUAL 8 .

Put Pdiffusion. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Label for input and outputs. Connect the output contacts using the metal. VLSI LAB MANUAL 9 . Paint Nwell. Give a Clock as the input and simulate for the output. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Assign appropriate Clock input and simulate for the output. Draw POLY over the diffusions as shown in the layout diagram.EXPERIMENT 5 : REALISE A 2 INPUT EXOR GATE AIM : Realise a two input EXOR gate in schematic and draw its layout and simulate PROCEDURE : Run the VLSI software for schematic entry. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Put the appropriate diffusion contacts and do connections for VDD and GND. OUT = NOT ( A B + AB) DEPT OF E C NIET.

VLSI LAB MANUAL 10 .DEPT OF E C NIET.

Give a Clock as the input and simulate for the output. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. generate layout using tool option and simulate PROCEDURE : Run the VLSI software for schematic entry.EXPERIMENT 6 : REALISE A 1 BIT FULL ADDER IN CMOS SCHEMATIC AND SIMULTATE. GENERATE LAYOUT USING TOOL OPTION AND SIMULATE AIM : TO realise a 1 bit full adder in CMOS schematic and simultate. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. VLSI LAB MANUAL 11 . SUM = A ⊕ B ⊕ C CARRY=AB+BC+CA DEPT OF E C NIET.

Wave forms of one bit Full adder Layout of one Bit Full adder DEPT OF E C NIET. VLSI LAB MANUAL 12 .

EXPERIMENT 7: REALISE A BOOLEAN EXPRESSION Y=NOT((A+B)(C+D)E) IN SCHEMATIC AND DRAW ITS LAYOUT AND SIMULATE AIM : TO realise a Boolean expression Y=Not((A+B)(C+D)E) in schematic and draw its layout and simulate. Connect the output contacts using the metal. Draw POLY over the diffusions as shown in the layout diagram. Label for input and outputs. DEPT OF E C NIET. Paint Nwell. Run the VLSI software for layout entry. VLSI LAB MANUAL 13 . PROCEDURE : Run the VLSI software for schematic entry. Put Pdiffusion. Paint Ndiffussion with proper design rules. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. Put the appropriate diffusion contacts and do connections for VDD and GND. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Assign appropriate Clock input and simulate for the output.

VLSI LAB MANUAL 14 .DEPT OF E C NIET.

When sel=1 then TG acts as closed switch.. Theory : CMOS transmission gate is created by connecting an nFET and pFET in Parallel as shown. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. VLSI LAB MANUAL 15 . From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. It does not have threshold voltage drop problems. If sel=0 nFET is OFF and pFET is OFF and TG acts as Open switch. It can be used as for transmitting any voltage (0. The schematic works as per the truth table given below: S1 S0 OUT 0 0 I0 0 1 I1 1 0 I2 1 1 I3 DEPT OF E C NIET. Give a Clock as the input and simulate for the output. PROCEDURE : Run the VLSI software for schematic entry.Vdd) from left to right and vice versa. A 4X1 Multiplexer can be designed using transmission gates as shown in Fig. below.EXPERIMENT 8 : 4 X 1 MUX USING TRANSMISSION GATES AIM : To Realize a 4 X 1 MUX using transmission gates in schematic and layout and simulate.

VLSI LAB MANUAL 16 .DEPT OF E C NIET.

DEPT OF E C NIET. Paint Nwell. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Label for input and outputs. Run the VLSI software for layout entry. VLSI LAB MANUAL 17 . From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Give a Clock as the input and simulate for the output. JK FLIPFLOP and T FLIPFLOP in CMOS schematic and layout and simulate PROCEDURE : Run the VLSI software for schematic entry. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. Draw POLY over the diffusions as shown in the layout diagram. Assign appropriate Clock input and simulate for the output. JK FLIPFLOP AND T FLIP FLOP IN CMOS SCHEMATIC AND LAYOUT AIM : To Realsie D FLIPFLOP. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal.EXPERIMENT 9: D FLIP FLOP. Paint Ndiffussion with proper design rules. Put Pdiffusion.

VLSI LAB MANUAL 18 . DEPT OF E C NIET.For T flip-flop short J and K.

DEPT OF E C NIET. AIM : To Realsie a four bit asynchronous counter using T flipflop as a cell in schematic PROCEDURE : Run the VLSI software for schematic entry.EXPERIMENT 10: FOUR BIT ASYNCHRONOUS COUNTER USING T FLIPFLOP AS A CELL IN SCHEMATIC. VLSI LAB MANUAL 19 . From the library drag the T flip flop cells and connect them as shown in schematic. Give a Clock and Input and simulate for the output.

DEPT OF E C NIET.EXPERIMENT 11: FOUR BIT SYNCHRONOUS COUNTER USING T FLIPFLOP AS A CELL IN SCHEMATIC. VLSI LAB MANUAL 20 . AIM : To Realsie a four bit synchronous counter using T flipflop as a cell in schematic PROCEDURE : Run the VLSI software for schematic entry. From the library drag the T flip flop cells and connect them as shown in schematic. Give a Clock and Input and simulate for the output.

Give a Clock and Input and simulate for the output. From the library drag the D flip flop cells and connect them as shown in schematic. AIM : To Realsie a four bit shift register using D flipflop as a cell in schematic PROCEDURE : Run the VLSI software for schematic entry.EXPERIMENT 12: FOUR BIT SHIFT REGISTER USING D FLIPFLOP AS A CELL IN SCHEMATIC. DEPT OF E C NIET. VLSI LAB MANUAL 21 .

The UTP is given by UTP = (Vdd + β 1 / β 3 Vt. M1 and M2 are in series and are driven by in1. p |) /(1+ β 4 / β 6 ) β 4 / β 6 = (W / L)4 /(W / L)6 Design example : Let UTP =1.n) /(1+ β 1 / β 3 ) β 1 / β 3 = (W / L)1 /(W / L)3 Similarly M6 is feedback resistor for pFET group. Draw the layout as shown in the layout. Calculate UTP and LTP and verify the values by simulation. Use the tool option to observe the hysterisis curve.2v. Give a sine wave signal as input and simulate. The LTP is given by LTP = ( β 4 / β 6 (Vdd − | Vt . p | − LTP) = 2 β 4 / β 6 = 4 and (W/L)4/(W/L)6 = 4 M4width = 4 x width of M6 DEPT OF E C NIET. PROCEDURE : Calculate the required W and L from the given parameters. Show the hysterisis curve.44 β 1 / β 3 = 6 and (W/L)1/(W/L)3 = 6 M1 width = 6 x width of M3 LTP: β 4 / β 6 = ( LTP /(Vdd − | Vt . Theory : The Schematic of Schmitt Trigger is shown below. n) = 2. VLSI LAB MANUAL 22 . As in1 is increased it keeps M2 off even after M1 is turned on. Vtn=0.45V and LTP= 1. When in1=0 Vout =Vdd and M3 is ON which acts as feedback path.5v.EXPERIMENT 13: DESIGN OF SCHMITT TRIGGER AIM : Design a Schmitt trigger for the ratio (β1/β3)=6) and (β4/β6)=3) in layout.4vand |Vtp|=0. Assume Vdd=1.67 V UTP: β 1 / β 3 = (Vdd − UTP ) /(UTP − Vt .

DEPT OF E C NIET. VLSI LAB MANUAL 23 .

VLSI LAB MANUAL 24 .DEPT OF E C NIET.

Hysterisis Characteristics DEPT OF E C NIET. VLSI LAB MANUAL 25 .

DEPT OF E C NIET. VLSI LAB MANUAL 26 .

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