HUMBOLDT-UNIVERSITÄT ZU BERLIN

INSTITUT FÜR INFORMATIK

COMPUTER ARCHITECTURE
Lecture 4

DATA AND INSTRUCTION FORMATS, ADDRESSING METHODS AND MACHINE PROGRAMMING CONCEPTS
Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca

CA - IV - D&IF - 1

TYPES OF INFORMATION, DATA AND INSTRUCTION FORMATS, ADDRESSING METHODS, AND MACHINE PROGRAMMING CONCEPTS
INFORMATION TYPES FORMATS (PDP-11, PowerPC, MOTOROLA 68000, Pentium examples)

ADDRESSES

ADDRESSING MODES

SIMPLE I/O PROGRAMMING

PUSHDOWN STACK vs. REGISTER ORGANIZATION
CA - IV - D&IF - 2

D&IF .3 .IV .SOME BASIC INFORMATION TYPES Information Data Instructions Nonnumeric Data Numbers Fixed-point Floating-point Binary Decimal Binary Decimal CA .

g. The PRECISION of the NUMBER 4. integers. real numbers.4 . THE COST of HARDWARE required to store and process the numbers ASCII – American Standard Committee on Information Interchange (7 bits) EBCDIC – Extended Binary-Coded Decimal Interchange Code (8 bits) CA .IV .D&IF ..DATA FORMATS In selecting the number representation the following factors should be taken into account. TYPES of NUMBERS to be represented e. 1. The RANGE of VALUES to be encountered 3. complex numbers 2.

D&IF . Type of instruction field (fixed or variable) 5. 1-.IV . OP-CODE ADDRESS(ES) 0-. 3. 4. 1. The cost of hardware required to decode and execute instructions. 2. The number of instructions to be represented. 2. The addressability and addressing modes. The ease of decoding.INSTRUCTION FORMATS In selecting the instruction format(s) the following factors should be considered.or 3-addressable instruction formats CA .5 .

IV .6 8 BITS CHARACTER .INSTRUCTION AND DATA FORMATS FOR PDP .11 INSTRUCTION FORMATS 1-ADDRESS OP-CODE 10 BITS Mode Rn 3 BITS 3 BITS OP-CODE 2-ADDRESS 4 BITS Mode Rn Mode Rn 3 BITS 3 BITS SRC 3 BITS 3 BITS DST OFFSET 8 BITS OP-CODE BRANCH 8 BITS BRANCH ADDRESS = [ UPDATED PC ] + 2 x OFFSET DATA FORMAT 16 BITS 2' s COMPLEMENT 8 BITS CHARACTER CA .D&IF .

BASIC INSTRUCTION FORMAT & PDP-11 ADDRESS FIELD OP CODE ADDRESS 15 6 5 ADDRESS MODE Rn 3 0 0 0 0 1 1 1 R 7 2 0 0 1 0 0 0 0 1 R 0 R 1 0 MODE RN (RN)+ -(RN) X(RN) Register Autoinc.D&IF .7 . Index (0) (2) (4) (6) 5 0 0 1 1 4 0 1 0 1 If "1" Indirect CA . Autodec.IV .

X – offset value. RS – Source Register. ME – Mask End. I16 – Immediate Operand. CR – Condition Register. CDR – Comparing field CA .IV .INSTRUCTION FORMATS for PowerPC 0 Two operand general instruction format Three operand general instruction format Instruction format for comparing I (1) OP code 6 RD/RS 11 RA 16 I16/X 31 0 (2) OP code 6 RD/RS 11 RA 16 RB 21 22 OE Sub OP code 31 Rc 0 (3) OP code 6 9 11 RB 16 I16 31 CRD OPc 0 Instruction format for comparing II (4) OP code 6 9 11 RA 16 RB 21 Sub OP code 31 0 CRD OPc Instruction format for logical operations with (5) the use of crb 0 OP code 0 6 crbD 6 11 crbA 11 16 crbB 16 21 Sub OP code 21 31 0 31 26 Instruction format for (6) OP code RS RA SH Shift/Rotate operations MB ME Rc RD – Destination Register.8 . OE/Rc – setting flags. SH – Shift/Rotate. RA – Additional Register. XER – Exeption Register. crb – Conditional Register Bit.D&IF . RB – third Register. MB – Mask Begin.

9 .DATA FORMAT for PowerPC 0 8 16 24 32 40 48 56 63 Byte 0 Byte 1 Byte 7 Half word 0 Half word 2 Word 0 Word 4 Double word 0 •The big-endian ordering is default mode.D&IF . CA .IV . the little-endian mode is also possible.

EFFECTIVE .ADDRESS INSTRUCTION OPERATION WORD GENERAL FORMAT 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 4 Mode 3 2 Effective Address 1 0 Register CA .10 . One or Two Words) 1 0 SINGLE .IV . One or Two Words) Source Effective Address Extension (If Any.INSTRUCTION FORMAT for MOTOROLA 68000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Operation Word (First Word specifies Operation and Modes) Immediate Operand (If Any.D&IF . One or Two Words) Destination Effective Address Extension (If Any.

.IV .. Near Pointer Offset or Linear Address 7 BCD 4 3 BCD 0 0 0 7 31 Far Pointer or Logical Address Segment Selector Offset 4 3 47 32 31 CA .D&IF .11 0 .. BCD X BCD BCD BCD Packed BCD Integers BCD BCD .PENTIUM INTEGER DATA FORMATS Byte Signed Integer Sign 76 Word Signed Integer 15 14 Doubleword Signed Integer Sign 31 30 Byte Unsigned Integer 7 Word Unsigned Integer 15 Doubleword Unsigned Integer 31 X BCD 0 0 0 0 0 0 Sign BCD Integers X ..

12 . or sign extension. 2 or 4 bytes or none 7 65 Scale Index Immediate Immediate data 1.IV . The encoding of fields in the opcode depends on the class of operation. condition codes. • The base field specifies the register number of the base register. the register encoding.PENTIUM GENERAL INSTRUCTION FORMAT Instruction Prefixes Up to four prefixes of 1 byte each (optional) 7 Mod Opcode 1 or 2 byte ModR/M 1 byte (if required) 32 0 R/M SIB 1 byte (if required) Displacement Address displacement 1. 2. the size of displace-ments. The base-plus-index and scale-plus-index forms of 32-bit addressing require the SIB byte. • The index field specifies the register number of the index register.D&IF . The SIB byte includes the following fields: • The scale field specifies the scale factor. • The reg/opcode field is either a register number or 3 more opcode bits. ModR/M and SIB Bytes • The mod and the r/m form 32 possible values: 8 registers and 24 addressing modes. Certain encodings of the ModR/M byte require a second addressing byte. It’s is specified in the primary opcode. These fields define the direction of the operation. or 4 bytes or none 32 Base 0 65 Reg/ Opcode Opcode Smaller encoding fields can be defined within the primary opcode. the SIB byte. to fully specify the addressing form. • The r/m field can specify a register as an operand or can be combined with the mod field to encode an addressing mode. CA .

X MULTIPLY C.T MOVE C.IV .NUMBER OF ADDRESSES ONE .X Comments T T X X X A TxB C XxC X+T CA . X ADD T. T MULTIPLY B.ADDRESS MACHINES X=AxB+CxC Instruction LOAD A MULTIPLY B STORE T LOAD C MULTIPLY C ADD T STORE X Comments Transfer A to accumulator AC AC AC x B Transfer AC to memory location T Transfer C to accumulator AC AC AC x C AC AC + T Transfer result to memory location X Instruction MOVE A.AND TWO .13 .D&IF .

replace by their sum Transfer result from top of stack to X CA .T MULTIPLY C.IV .X Comments T X X AxB CxC X+T Instruction PUSH A PUSH B MULTIPLY PUSH C PUSH C MULTIPLY ADD POP X Comments Transfer A to top of stack Transfer B to top of stack Remove A. C from stack and replace by C x C Remove CxC. B.14 .THREE .D&IF .AND ZERO-ADDRESS MACHINES X=A xB+CxC Instruction MULTIPLY A. X ADD X. T. AxB from stack. B from stack and replace by A x B Transfer C to top of stack Transfer second copy of C to top of stack Remove C. C.

D&IF . INDEXED ADDRESSING . Also operand could follow immediately after the instruction.g. the address of the second operand is implied as being accumulator) IMMEDIATE ADDRESSING .The address is implied by the instruction (e.in one-address machine. INDIRECT ADDRESSING . No memory access is required. It can have more than one level..The address of operand is given explicity as part of the instruction IMPLIED ADDRESSING .The operand is given explicitly as the instruction.EA = B + DA CA .IV .ADDRESSING METHODS ABSOLUTE (DIRECT) ADRESSING .The effective address of the operand is in the register or main memory location whose address appears in the instruction.The effective address of the operand is generated by adding base register value (B) to the address .EA = X + DA BASE ADDRESSING .The effective address (EA) of the operand is generated by adding an index register value (X) to the direct address (DA) .15 .

16 . or also the last address can be given. or special end-of-block character can be given. Very useful in the secondary storage management.D&IF . EA = DA + PC AUGMENTED ADDRESSING . Length of the block is usually specified in the instruction.IV . CA .Effective address is a concatenation of the contents of the augmented address register (AAR) and direct address.SELF-RELATIVE ADDRESSING .Effective address is a sum of a direct address and a program counter contents (PC).Address of the first word in the block is given. or blocks may have fixed length. EA = AAR || DA (AAR often specifies a page and DA is an address within this particular page) BLOCK ADDRESSING .

Consortium of Apple.PowerPC Family .IV . IBM and Motorola (announced in 1991) CPU 601 603 603e 604 604e G3 750CX 750CXe G4 7410 7450 Speed* 60-120 MHz 75-160 MHz 100-300 MHz 120-180 MHz 150-350 MHz 200-450 MHz 366-466 MHz 400-700 MHz 350-600 MHz 466-533 MHz 667-733 MHz Instructions 3 per cycle 2 per cycle 2 per cycle 4 per cycle 4 per cycle 3 per cycle 3 per cycle 3 per cycle 19 per cycle** 20 per cycle** unknown L1 cache 32 KB 2x8 KB 2x16 KB 2x16 KB 2x32 KB 2x32 KB 8-10x bus multiplier 2x32 KB+ 8x bus multiplier 2x32 KB+ 10x bus multiplier 2x32 KB plus 2 MB L2 cache 2x32 KB plus 1 MB L2 cache 2x32 KB+ 256K L2+2 MB L3 cache * as used in Apple ** AltiVec can do up to 16 simultaneous calculations + integrated 256 KB level 2 cache CA .D&IF .17 .

the value 0 is used instead of the contents of R0. CA . If zero is used in place of Ri. where Rsrc is any of the general purpose registers R1 through R32. X. the operand is specified in the form X(Rsrc). REGISTER INDEX ADDRESSING MODE .GENERAL METHODS OF ADDRESSING OF PowerPC IMMEDIATE INDEX ADDRESSING MODE -The effective address of the operand is the sum of the contents of a register named in the instruction and a signed 16-bit offset.IV .18 . In this case the effective address is [Rj].The effective address of the operand is the sum of the contents of two general purpose registers named in the instruction.D&IF . The effective address is computed as Aeff = [Ri] + [Rj]. In assembly language. and the effective address is computed as Aeff = X + [Rsrc]. that is also given in the instruction.

The distance between the branch instruction and the target address is given in the instruction REGISTER INDIRECT .D&IF .IV .METHODS OF ADDRESSING MODES FOR BRANCH INSTRUCTIONS OF PowerPC ABSOLUTE . CA . Instructions that use this mode are called branch to register.The target address is given in the instruction RELATIVE .19 .The target address is the contents of a register specified by the instruction OP code. for simplicity.

]]. ]]. FETCH X. EA = [[Rn INCREMENT Rn.IV .( Rn ) X( Rn ) @Rn @( R n )+ @-( R n ) @X(R n ) EA = [Rn ]. 001 011 101 111 1 3 5 7 REGISTER INDIRECT AUTOINCREMENT INDIRECT AUTODECREMENT INDIRECT INDEX INDIRECT EA = [ Rn]. [Rn ]) OPERAND = 010 100 110 2 4 6 AUTOINCREMENT AUTODECREMENT INDEX ( Rn )+ .20 .D&IF . INCREMENT PC EA = [X+[Rn]] EA [L] [[L]] = effective address = contents of the location whose address is L (the address L can be that of a main memory location or a register Rn) = L points to a location where the effective address can be found CA .PDP-11 ADDRESSING MODES B5B4B3 000 Decim. FETCH X. INCREMENT Rn DECREMENT EA = [Rn ]. INCREMENT PC EA = X + [Rn]. EA = [[Rn DECREMENT Rn. 0 NAME REGISTER SYNTAX Rn MEANING EA = Rn ( THAT IS.

I NCREMENT PC. Increment PC (That is.PDP-11 ADDRESSING MODES WITH Rn = PC B5B4B3 Decim. operand N follows the intstruction) EA = [[PC]]. IT IS SPECIFIED RELATIVE TO PC BY DISPLACEMENT X IN WORD FOLLOWING INSTRUCTION) FETCH X. EA = X + [PC] ( THAT IS.) F ETCH X. follows the intstr. Increment PC (that is. NAME SYNTAX #N MEANING EA = [PC]. I NCREMENT PC. EA IS A. which is A. ( THAT IS THE ADDRESS A OF LOCATION CONTAINING EA IS SPECIFIED RELATIVE TO [PC] BY DISPLACEMENT X IN WORD FOLLOWING INSTRUCTION) EA [L] [[L]] = effective address = contents of the location whose address is L (the address L can be that of a main memory location or a register Rn or PC) CA .D&IF .21 = L points to a location where the effective address can be found .IV . EA. 010 2 I MMEDIATE ( AUTOINCREMENT) A BSOLUTE (AUTOINCREMENT INDIRECT) RELATIVE ( INDEX ) 011 3 @#A 110 6 A 111 7 RELATIVE INDIRECT (INDEX INDIRECT) @A EA = [X+[PC]].

THE 68000 MICROPROCESSOR ADDRESSING MODES & INSTRUCTIONS 68000. 68040 & 68060 (two architectures) •16-bit external & 32-bit internal . X extended.(16 data.D&IF . 24 address) 64 pins (other models have 32 data and 32 address) •32. Z zero.2 byte 224 . 68020. C carry) byte 0 byte 1 0 long word 0 byte 3 byte 2 2 long word 4 0 2 24 -2 byte 224 . SUPERVISOR STACK POINTER) PROGRAM COUNTER STATUS REGISTER (supervisor or trace mode select. V overflow.IV .1 CA .22 . 68030. interrupt mask. N negative. 16 & 8 bit words (operands) 31 16 15 7 byte word long word 8 DATA REGISTERS. 8 ADDRESS REGISTERS (A USER STACK POINTER.

PENTIUM ADDRESSING MODES 1) Immediate Operands 2) I/O Port Addressing 3) Register Operands 4) Memory Operands Process or Word and Bus Widths of some 16.23 .D&IF .IV . 16/32 and 64/32 Bit CISC Microprocessors CA .

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