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ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025 REGULATIONS - 2009 CURRICULUM I TO IV SEMESTERS (FULL TIME)
M.E. VLSI DESIGN
SEMESTER I SL. COURSE NO CODE THEORY MA9217 1 2 VL 9211 3 AP9212 4 VL9212 5 VL9213 6 E1 PRACTICAL 7 VL9217 COURSE TITLE L T P C
Applied Mathematics for Electronics Engineers DSP Integrated Circuits Advanced Digital System Design VLSI Design Techniques Solid State Device Modeling and Simulation Elective I VLSI Design Lab I TOTAL SEMESTER II
3 3 3 3 3 3 0 18
1 0 0 0 0 0 0 1
0 0 0 0 0 0 4 4
4 3 3 3 3 3 2 21
SL. COURSE NO CODE THEORY 1 AP9221 2 VL9221 AP9222 3 4 AP9224 5 E2 6 E3 PRACTICAL 7 VL9225
Analysis and Design of Analog Integrated Circuits CAD for VLSI Circuits Computer Architecture and Parallel Processing Embedded Systems Elective II Elective III VLSI Design Lab II TOTAL
3 3 3 3 3 3 0 18
0 0 0 0 0 0 0 0
0 0 0 0 0 0 4 4
3 3 3 3 3 3 2 20
SL. COURSE NO CODE THEORY 1 E4 2 E5 3 E6 PRACTICAL 4 VL9234 COURSE TITLE L T P C
Elective IV Elective V Elective VI Project Work (Phase I) TOTAL
3 3 3 0 9
0 0 0 0 0
0 0 0 12 12
3 3 3 6 15
SEMESTER IV 1
SL. COURSE NO CODE PRACTICAL 1 VL9241
Project Work (Phase II) TOTAL
Total no.of credits to be earned for the award of Degree 21+20+15+12 =68
ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025 REGULATIONS - 2009 CURRICULUM I TO VI SEMESTERS (PART TIME)
M.E. VLSI DESIGN
SEMESTER I SL. COURSE NO CODE COURSE TITLE THEORY 1 MA9217 Applied Mathematics for Electronics Engineers 2 AP9212 Advanced Digital System Design 3 VL9212 VLSI Design Techniques VLSI Design Laboratory I PRACTICAL 4 VL9217 L 3 3 3 0 TOTAL 9 T 1 0 0 0 1 P 0 0 0 4 4 C 4 3 3 2 12
SEMESTER II SL. COURSE NO CODE COURSE TITLE THEORY 1 AP9221 Analysis and Design of Analog Integrated Circuits 2 VL9221 CAD for VLSI Circuits 3 AP9224 Embedded Systems VLSI Design Laboratory II TOTAL PRACTICAL 4 VL9225 L 3 3 3 0 9 T 0 0 0 0 0 P 0 0 0 4 4 C 3 3 3 2 11
SL. COURSE NO CODE COURSE TITLE THEORY 1 VL 9211 DSP Integrated Circuits 2 VL9213 Solid State Device Modeling and Simulation 3 E1 Elective I TOTAL L 3 3 3 9 T 0 0 0 0 P 0 0 0 0 C 3 3 3 9
SL. COURSE NO CODE COURSE TITLE THEORY 1 AP9222 Computer Architecture and Parallel Processing 2 E2 Elective II 3 E3 Elective III TOTAL L 3 3 3 9 T 0 0 0 0 P 0 0 0 0 C 3 3 3 9
SL. COURSE NO CODE THEORY 1 E4 Elective IV 2 E5 Elective V 3 E6 Elective VI Project Work (phase I) TOTAL PRACTICAL 4 VL9234 COURSE TITLE L 3 3 3 0 9 T 0 0 0 P 0 0 0 C 3 3 3 6 15
0 12 0 12
SL. COURSE NO CODE COURSE TITLE PRACTICAL 1 VL9241 Project Work (Phase II) TOTAL Total credit 12+11+9+915+12 = 68 L 0 0 T P C 12 12
0 24 0 24
LIST OF ELECTIVES M. VLSI DESIGN SL.E. NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 COURSE CODE VL9251 VL9252 VL9253 VL9254 VL9255 VL9256 VL9257 VL9258 AP9213 AP9252 VL9261 NE9251 AP9256 VL9264 VL9265 VL9266 COURSE TITLE Testing of VLSI Circuits Low Power VLSI Design VLSI Signal Processing Analog VLSI Design Design of Semiconductor Memories VLSI Technology Physical Design of VLSI Circuits Genetic Algorithms and their Applications Advanced Microprocessors and Microcontrollers Neural Networks and Its Applications ASIC Design Reliability Engineering Electromagnetic Interference and Compatibility in System Design Digital Speech Signal Processing DSP Processor Architecture and programming Introduction to MEMS System Design Special Elective L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 .
. Pearson Education. Fundamentals of Queueing theory. Klir and Yuan. New Delhi. 4. Prentice Hall of India Pvt.. Uniform.Probability function – moments – moment generating functions and their properties – Binomial. Donald Gross and Carl M. An introduction. UNIT V QUEUEING MODELS 9 Poisson Process – Markovian queues – Single and Multi-server Models – Little’s formula . Asia. Sterling. George J. UNIT III ONE DIMENSIONAL RANDOM VARIABLES 9 Random variables ..A. W. T. Theory and applications. B. 2nd edition.Toeplitz matrices and some applications.K. Operations Research. John Wiley and Sons. 3. New York (1985). Moon. Geometric. 5 .. 2. Private Ltd.APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS LT P C 3104 UNIT I FUZZY LOGIC 9 Classical logic – Multivalued logics – Fuzzy propositions – Fuzzy quantifiers. Total: 45 Hours REFERENCES: 1. Taha. Poisson. H. MA9217 L = 45: T=15. New Delhi (2007).C. Prentice – Hall of India. Gamma and Normal distributions – Function of a Random Variable. 1997. 2000.. UNIT II MATRIX THEORY 9 Some important matrix factorizations – The Cholesky decomposition – QR factorization – Least squares method – Singular value decomposition . Exponential. 7th edition. Pearson education editions. 5. Fuzzy sets and fuzzy logic. Miller & Freund’s Probability and Statistics for Engineers. Ltd. Richard Johnson.Machine Interference Model – Steady State analysis – Self Service queue. 7th Edition. Mathematical methods and algorithms for signal processing. UNIT IV DYNAMIC PROGRAMMING 9 Dynamic programming – Principle of optimality – Forward and backward recursion – Applications of dynamic programming – Problem of dimensionality. 2002.. Harris.
Oppenheim et.processing systems. Discrete cosine transforms.al. Finite word length effects -Parasitic oscillations. UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9 FIR filters. DFT-The Discrete Fourier Transform. Round-off noise. Trends in CMOS technologies. Asia. Image coding. Lars Wanhammer. “VLSI Digital Signal Processing Systems design and Implementation”. Shared memory architecture with Bit – serial PEs. 3. DSP system design. Signal. DCT processor and Interpolator as case studies. Implementation based on complex PEs. Bit-parallel and Bit-Serial arithmetic. UNIT II DIGITAL SIGNAL PROCESSING 9 Digital signal processing. Adaptive DSP algorithms. Sampling of analog signals. Complex multipliers. Reducing the memory size. Ideal DSP architectures. Mapping of analog transfer functions. A. 2000. VLSI process technologies. Residue Number System. UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9 Conventional number system. MOS transistors. Mapping of DSP algorithms onto hardware. “ Digital signal processing – A practical approach”. Barrie W. Transfer functions. Filter structures. Mapping of analog filter structures. Jervis. Selection of sample frequency. Coefficient sensitivity. MOS logic. Signal flow graphs. Layout of VLSI circuits. Redundant Number system. Multirate systems. Multirate filters.VL 9211 DSP INTEGRATED CIRCUITS LTPC 3003 UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 9 Standard digital signal processors. FFT-The Fast Fourier Transform Algorithm. Measuring round-off noise. Emmanuel C. Application specific IC’s for DSP. 6 . 4. 1999 Academic press. Systolic and Wave front arrays. Integrated circuit design. Standard DSP architecture. Frequency response. Pearson Education. Cordic algorithm. Multiprocessors and multicomputers. “Discrete-time Signal Processing”. Improved shift-accumulator. FFT processor. “DSP Integrated Circuits”. Keshab K. Scaling of signal levels.Parhi. Total: 45 Hours REFERENCES: 1. Pearson Education. Second Edition.V. John Wiley & Sons. Shared memory architectures. DSP systems. Specifications of IIR filters. Ifeachor. Basic shift accumulator. FIR chips. IIR filters. Sampling rate change with a ratio L/M. New York 2. Sensitivity and noise. UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES 9 DSP system architectures. Interpolation with an integer factor L. 1999. FIR filter structures.
2004 Douglas L.State diagram.Lala “Fault Tolerant and Fault Testable Hardware Design” B S Publications.Hill .design of asynchronous sequential circuit-Static.2006 7 . state table assignment and reduction-Design of synchronous sequential circuits-design of iterative circuits-ASM chart and realization using ASM UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9 Analysis of asynchronous sequential circuit – flow table reduction-races-state assignment-transition table and problems in transition table.”Digital System Design using VHDL” Thomson learning.Divider – Design of simple microprocessor Total = 45 HRS REFERENCES: 1 2 3 4 5 6 Charles H.2001 Parag K.2002 Parag K.Perry “VHDL programming by Example” Tata McGraw. state table. dynamic and essential hazards – data synchronizers – mixed operating mode asynchronous circuits – designing vending machine controller UNIT III FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9 Fault table method-path sensitization method – Boolean difference method-D algorithm -Tolerance techniques – The compact algorithm – Fault in PLA – Test generation-DFT schemes – Built in self test UNIT IV SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES 9 Programming logic device families – Designing a synchronous sequential circuit using PLA/PAL – Realization of finite state machine using PLD – FPGA – Xilinx FPGA-Xilinx 4000 UNIT V SYSTEM DESIGN USING VHDL 9 VHDL operators – Arrays – concurrent and sequential statements – packages.Data flow – Behavioral – structural modeling – compilation and simulation of VHDL code –Test bench .AP9212 ADVANCED DIGITAL SYSTEM DESIGN LTPC 3003 UNIT I SEQUENTIAL CIRCUIT DESIGN 9 Analysis of clocked synchronous sequential circuits and modeling.Realization of combinational and sequential circuits using HDL – Registers – counters – sequential machine – serial adder – Multiplier.Lala “Digital system Design using PLD” B S Publications.Roth Jr “Fundamentals of Logic Design” Thomson Learning 2004 Nripendra N Biswas “Logic Design Theory” Prentice Hall of India.2003 Charles H Roth Jr.
Pucknell. comparators. Inverter ratio. Inductance. Pearson Education. Transmission gates. UNIT IV VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICAL DESIGN 9 Multiplexers. Introduction to VLSI Design McGraw Hill International Editions. Super buffers.Body effect. 2. behavioral modelling. J. Basics of CMOS testing. power distribution. John P. switching times. B. 1995. Principles of CMOS VLSI Design. data flow modelling. Driving large capacitance loads. gate level modelling. 2000. 8 . Pearson Education ASIA.VL9212 VLSI DESIGN TECHNIQUES LTPC 3003 UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY 9 NMOS and PMOS transistors. DC and transient characteristics . 2nd Edition.2002. 1990. Stick diagram. Pearson Education. switching characteristics. 2004. “Verilog HDL”.Scaling. 6.Design equationsSecond order effects. Wayne Wolf “Modern VLSI Design System on chip. John Wiley & Sons.Fabricius. task & functions. 7.Uyemura “Introduction to VLSI Circuits and Systems”. Capacitance estimation. Carry look ahead adders. Arithmetic circuits – Ripple carry adders. UNIT III CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION 9 Resistance estimation. Prentice Hall of India Publication. Threshold voltage. Physical design – Delay modelling . CMOS logic structures .Bhasker. Test Bench. UNIT V VERILOG HARDWARE DESCRIPTION LANGUAGE 9 Overview of digital design with Verilog HDL. “A Verilog HDL Primer”. modules and port definitions. power dissipation and design margining. 3. Charge sharing . Multipliers. 5.cross talk.. MOS models and small signal AC characteristics. High-speed adders. Neil H. Inc. UNIT II INVERTERS AND LOGIC GATES 9 NMOS and CMOS Inverters. Total: 45 REFERENCES: 1.E. hierarchical modelling concepts. Basic CMOS technology. floor planning. priority encoders. Shift registers.S. dynamic CMOS design. transistor sizing. 2001. “Basic VLSI Design”. 2nd Edition. Decoders. Samir Palnitkar. Weste and Kamran Eshraghian. 4. Static CMOS design. 2nd edition.Publications. 2002. Eugene D. Clock distribution.
long channel drain current model. Channel charge model. gate tunneling current model. noise model. modeling second order effects of the drain current. Layout-dependent parasitics model. modeling of device mismatch for Analog/RF Applications. Threshold voltage model. “Device Modeling for Analog and RF CMOS Circuit Design”. modeling of charge storage effects. High speed model. Capacitance models. Nonquasi-static modeling. noise model temperature effects. Trond Ytterdal. UNIT IV OTHER MOSFET MODELS 9 The EKV model. Yuhua Cheng and Tor A. Enhanced model for effective DC and AC channel length and width. Basic modeling. calculation of distortion in analog CMOS circuits UNIT III BSIM4 MOSFET MODELING 9 Gate dielectric model. Automation of the tests TOTAL: 45 REFERENCES: 1. substrate current models. Capacitors. modeling parasitic BJT. UNIT V 9 . RF model. Inductors.C small signal modeling. model features. junction diode models. mobility model.VL9213 SOLID STATE DEVICE MODELING AND SIMULATION LTPC 3003 UNIT I MOSFET DEVICE PHYSICS 9 MOSFET capacitor. model parameter extraction. RF modeling of MOS transistors. model for accurate distortion analysis. Equivalent circuit representation of MOS transistor. Source/drain resistance model. UNIT II NOISE MODELING 9 Noise sources in MOSFET. John Wiley & Sons Ltd. I-V model. FjeldlyWayne Wolf. Basic operation. nonlinearities in CMOS devices and modeling. MOS model 9. MOSAI model) MODELLING OF PROCESS VARIATION AND QUALITY ASSURANCE 9 Influence of process variation. Flicker noise modeling. High frequency behavior of MOS transistor and A. Resistors. Benchmark circuits for quality assurance.Advanced MOSFET modeling. Thermal noise modeling.
Modeling of Sequential Digital system using VHDL. 4. 2. Simulation of NMOS and CMOS circuits using SPICE. Modeling of Sequential Digital system using Verilog. 7. 8.VL9217 VLSI DESIGN LAB I LTPC 0042 1. Implementation of MAC Unit using FPGA. Digital Filters in DSP Processor. 5. Design and Implementation of ALU using FPGA. Implementation of FFT. AP9221 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS 10 . 3. Implementation of DSP algorithms using software package. 6. Modeling of MOSFET using C.
S. Behzad Razavi. “CMOS Analog Circuit Design”. slew rate model and high frequency analysis.Allen Douglas R. 2004.2003. 4.short channel effects in MOS transistors – weak inversion in MOS transistors. ltd. Bipolar and MOS Analog Integrated circuit design”. “Analysis and design of Analog IC’s”. Meyer.”Semiconductor Devices. Analysis of difference amplifiers with active load using BJT and FET.Inc. supply and temperature independent biasing techniques. Cascode. voltage controlled oscillator.Chand and company ltd. Nandita Dasgupata. Fourth Edition. Phillip E. Monolithic PLL design in integrated circuits: Sources of noise. source follower and Push pull output stages. closed loop analysis of PLL. UNIT II CIRCUIT CONFIGURATION FOR LINEAR IC 9 Current sources. UNIT III OPERATIONAL AMPLIFIERS 9 Analysis of operational amplifiers circuit.substrate current flow in MOS transistor. 2000 3. Gray. “Principles of data conversion system design”. Wilson and Widlar current source – CMOS Class AB output stages – Two stage MOS Operational Amplifiers. 2. 2002. Output stages: Emitter follower. Lewis. 5. Grebene.LTPC 3003 UNIT I MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES 9 Depletion region of a PN junction – large signal behavior of bipolar transistorssmall signal model of bipolar transistor. Willey International..small signal model of the MOS transistors. Prentice Hall of India pvt. Holberg. Frequency response of integrated circuits: Single stage and multistage amplifiers. voltage references.large signal behavior of MOSFET. Operational amplifier noise UNIT IV ANALOG MULTIPLIER AND PLL 9 Analysis of four quadrant and variable trans conductance multiplier. with Cascode. Amitava Dasgupta. John Wiley & sons. Hurst. MOS Telescopic-Cascode Operational Amplifier – MOS Folded Cascode and MOS Active Cascode Operational Amplifiers TOTAL: 45 REFERENCES: 1. Second Edition-Oxford University Press-2003 VL9221 CAD FOR VLSI CIRCUITS LTPC 11 .Noise models of Integrated-circuit Components – Circuit Noise Calculations – Equivalent Input Noise Generators – Noise Bandwidth – Noise Figure and Noise Temperature UNIT V ANALOG DESIGN WITH MOS TECHNOLOGY 9 MOS Current Mirrors – Simple. Modelling and Technology”.
placement and partitioning .Tractable and Intractable problems . Kluwer Academic Publishers.Simple scheduling algorithm .Two Level Logic Synthesis.Design rules .partitioning UNIT III FLOOR PLANNING 9 Floor planning concepts .Area routing . 12 .algorithms for constraint graph compaction .Hardware models . 2002.channel routing . "Algorithms for VLSI Physical Design Automation". TOTAL: 45 REFERENCES: 1.Gate-level modeling and simulation .Types of local routing problems . "Algorithms for VLSI Design Automation".Assignment problem .Review of VLSI Design automation tools .Allocation assignment and scheduling . UNIT IV SIMULATION 9 Simulation .H.algorithms for global routing.Circuit representation . N. UNIT V MODELLING AND SYNTHESIS 9 High level Synthesis .shape functions and floorplan sizing .Internal representation .Combinational Logic Synthesis .general purpose methods for combinatorial optimization.Switch-level modeling and simulation . Sherwani.problem formulation .Placement algorithms . 2. S.High level transformations.Algorithmic Graph Theory and Computational Complexity .Binary Decision Diagrams .3003 UNIT I VLSI DESIGN METHODOLOGIES 9 Introduction to VLSI Design methodologies .Review of Data structures and algorithms .A.global routing . Gerez. John Wiley & Sons. UNIT II DESIGN RULES 9 Layout Compaction .2002.
5. UNIT III HARDWARE TECHNOLOGIES 9 Processor and memory hierarchy advanced processor technology. sequential and weak consistency models. scalability analysis and approaches. Multiprocessors and Multicomputers and Multivectors and SIMD computers. UNIX. 1990. memory hierarchy technology. “ Computer Organization and Architecture”. Multithreaded and data flow architectures. 3. ”Advanced Computer architecture – A design Space Approach” . Multiprocessor and Multicomputers. Tata McGraw Hill 1998. UNIT II PARTITIONING AND SCHEDULING 9 Program partitioning and scheduling. " Advanced Computer Architecture ". UNIT V SOFTWARE AND PARALLEL PROGRAMMING Parallel models. Jordan Gita Alaghband. Michael. Parallel processing applications. “Scalable parallel computing”. speedup performance laws. Architectural development tracks. 4.Conditions of parallelism. 7. Harry F.backplane bus systems. Macmillan Publishing Company. Principles of scalable performance . Quinn. Pearson Education . 6. Wilkinson. Program and network properties. Program flow mechanisms. 9 TOTAL: 45 REFERENCES: 1. Languages and compilers. 2003 9. 2001. Terence Fountain. Kai Hwang. Kai Hwang. Dezso Sima. virtual memory technology. John P. “Modern processor design . Pearson Education . 2002 8. shared memory organisations. 13 . M. 2003. Pearson Education Asia . Multivector and SIMD computers. Fundamentals of super scalar processors”. MACH and OSF/1 for parallel computers. PHI.Kain. System interconnect architectures. Parallel program development and environments.AP9222 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING LTPC 3003 UNIT I THEORY OF PARALLELISM 9 Parallel computer models . cache memory organisations. 2003.Shen. 2. McGraw Hill International. Barry.J. PRAM and VLSI models.performance matrices and measures. William Stallings. Scalable.the state of computing. 1994. Richard Y. Allen “Parallel Programming”. “ Advanced computer architecture –A systems Design Approach”. “ Fundamentals of parallel Processing”. UNIT IV PIPELINING AND SUPERSCALAR TECHNOLOGIES 9 Parallel and scalable architectures. superscalar and vector processors. bus cache and shared memory . Peter Kacsuk. “ Designing Efficient Algorithms for Parallel Computers”. McGraw Hill International. Tata McGraw Hill 2003.
System Analysis and Architecture Design. Morgan Kaufman Publishers. Dynamic Versus Static systems.W.I2C. CAN Bus.AP9224 EMBEDDED SYSTEMS LTPC 3003 UNIT I EMBEDDED PROCESSORS 9 Embedded Computers. Wayne Wolf. ARM Bus. UNIT V SYSTEM DESIGN TECHNIQUES 9 Design Methodologies. Pearson Education Asia. Specification. Input/output devices. weighted round robin Approach. challenges in validating timing constraints in priority driven systems. Optimality of the Earliest deadline first (EDF) algorithm. McGraw-Hill. Design Example: Telephone PBX. Frank Vahid and Tony Givargis. Personal Digital Assistants. Component interfacing.S. Internet.Hardware and Software Architectures. SHARC processor. 3. effective release times and deadlines. Characteristics of Embedded Computing Applications. Formalism for System DesignStructural Description. Design Example: Model Train Controller. “Real-Time Systems” . TOTAL: 45 REFERENCES: 1. Off-line Versus On-line scheduling. 2. SHARC Bus. UNIT II EMBEDDED PROCESSOR AND COMPUTING PLATFORM 9 Data operations. Krishna and K. Designing Hardware and Software Components. Networks for embedded systems. “Real-Time systems”. 14 . M. Requirement Analysis. Myrinet. Set-top Boxes. Priority driven Approach. Liu. CPU Bus configuration. Memory devices. Hardware platform design. designing with microprocessor development and debugging. Architectural Design. Flow of Control. SHARC link supports. Shin. John Wiley & Sons. Flow of Control. Specification. Allocation and scheduling.Hardware Design and Software Design. Jane.Requirements. Network-Based design. C. Design Example : Alarm Clock. parallelism with instructions.Communication Analysis.System Architecture. Ink jet printer. Data operations.Memory organization. System Integration. ARM processor. UNIT IV REAL-TIME CHARACTERISTICS 9 Clock driven Approach. Design Example: Elevator Controller. Challenges in Embedded Computing system design. 1997 4. Quality Assurance. “Embedded System Design: A Unified Hardware/Software Introduction” . G. Behavioural Description. “Computers as Components: Principles of Embedded Computing System Design”.processor and memory organization. system performance Analysis. Hybrid Architecture UNIT III NETWORKS 9 Distributed Embedded Architecture. Embedded system design process. Ethernet.
3.) System design using PLL. 4.) Implementation of Alarm clock controller using embedded microcontroller. 2.) Implementation of Elevator controller using embedded microcontroller. 6.) Implementation of 4 Bit Sliced processor in FPGA / CPLD.VL9225 VLSI DESIGN LAB II LTPC 0042 1. 15 . 5.) Implementation of model train controller using embedded microcontroller.) Implementation of 8 Bit ALU in FPGA / CPLD.
L.D. 2. Lala. Prentice Hall International. Jaico Publishing House. UNIT IV SELF – TEST AND TEST ALGORITHMS 9 Built-In self Test – test pattern generation for BIST – Circular BIST – BIST Architectures – Testable Memory Design – Test Algorithms – Test generation for Embedded RAMs. 3. UNIT V FAULT DIAGNOSIS 9 Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design – System Level Diagnosis.2002. UNIT III DESIGN FOR TESTABILITY 9 Design for Testability – Ad-hoc design – generic scan based design – classical scan based design – system level DFT approaches.D.A. “Design Test for Digital IC’s and Embedded Core Systems”. 16 . 2002. M.Bushnell and V. Kluwer Academic Publishers. UNIT II TEST GENERATION FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS 9 Test generation for combinational logic circuits – Testable combinational logic circuit design – Test generation for sequential circuits – design of testable sequential circuits.Abramovici.Breuer and A. P. Academic Press. A. 2002.K. “Essentials of Electronic Testing for Digital. “Digital Circuit Testing and Testability”. Total: 45 REFERENCES: 1. “Digital systems and Testable Design”.Agrawal.VL9251 TESTING OF VLSI CIRCUITS LTPC 3003 UNIT I BASICS OF TESTING AND FAULT MODELLING 9 Introduction to testing – Faults in Digital Circuits – Modelling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – driven simulation. 2002. Memory and Mixed-Signal VLSI Circuits”. M.L.Crouch. 4. Friedman. M.
Abdelatif Belaouar.1995. “Low voltage CMOS VLSI Circuits”.Chandrasekaran and R. inc. “Practical low power digital VLSI design”. Gary Yeap. “Low power digital CMOS design”. Chirstian Pignet. Kluwer. “Low power digital VLSI design”. “Low power CMOS VLSI circuit design”. 6. John Wiley and sons. “Low voltage SOI CMOS VLSI devices and Circuits”. James B. Kluwer.VL9252 LOW POWER VLSI DESIGN LTPC 3003 UNIT I POWER DISSIPATION IN CMOS 9 Hierarchy of limits of power – Sources of power consumption – Physics of power dissipation in CMOS FET devices – Basic principle of low power design. Wiley. Costas Goutis. Inter connect and layout design – Advanced techniques – Special techniques. 1995.Broadersen.B. UNIT III DESIGN OF LOW POWER CMOS CIRCUITS 9 Computer arithmetic techniques for low power system – reducing power consumption in memories – low power clock. 5. Kluwer. 2000. Shih-Chia Lin.I. Wiley 1999. TOTAL: 45 REFERENCES: 1. 2001.Prasad. 1998. Mohamed.Kulo.H Lou. 2. 7. Kluwer. UNIT II POWER OPTIMIZATION 9 Logic level power optimization – Circuit level low power design – circuit techniques for reducing power consumption in adders and multipliers.Elmasry.Kulo and J.P. J. 4. Kaushik Roy and S. UNIT V SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER 9 Synthesis for low power – Behavioral level transform – software design for low power. Dimitrios Soudris. “Designing CMOS Circuits for Low Power”.W. 3. A. 2002.C. UNIT IV POWER ESTIMATION 9 Power Estimation technique – logic power estimation – Simulation power analysis – Probabilistic power analysis. VL9253 VLSI SIGNAL PROCESSING 17 .
“ Digital Signal Processing with Field Programmable Gate Arrays”. Longest path matrix algorithm. Odd-Even merge-sort architecture. UNIT IV SCALING. 2-parallel fast FIR filter. Unfolding – an algorithm for unfolding. Loop bound. ROUND-OFF NOISE. bit-serial FIR filter. synchronous pipelining and clocking styles. Asynchronous pipelining bundled data versus dual rail protocol. ALGORITHMIC STRENGTH REDUCTION 9 Retiming – definitions and properties. properties of unfolding. Distributed Arithmetic fundamentals and FIR filters UNIT V NUMERICAL STRENGTH REDUCTION. Interscience. 2007. sample period reduction and parallel processing application. Meyer – Baese. PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS 9 Fast convolution – Cook-Toom algorithm. Look-Ahead pipelining with power-of-2 decomposition. 2. round-off noise in pipelined IIR filters. WAVE AND ASYNCHRONOUS PIPELINING 9 Numerical strength reduction – subexpression elimination. UNIT III FAST CONVOLUTION. Pipelining and Parallel processing of FIR filters. CSD representation. Design and implementation “. parallel carry-ripple and carry-save multipliers. Bit-level arithmetic architectures – parallel multipliers with sign extension. round-off noise. Keshab K. iteration bound. Second Edition.LTPC 3003 UNIT I INTRODUCTION TO DSP SYSTEMS. Clustered look-ahead pipelining. Design of Lyon’s bit-serial multipliers using Horner’s rule. wave pipelining. CSD multiplication using Horner’s rule for precision improvement. combined pipelining and parallel processing of IIR filters. UNIT II RETIMING. Parhi. scaling and round-off noise computation. Pipelined and parallel recursive filters – Look-Ahead pipelining in first-order IIR filters. modified Cook-Toom algorithm. parallel rankorder filters. PIPELINING AND PARALLEL PROCESSING OF FIR FILTERS 9 Introduction to DSP systems – Typical DSP algorithms. state variable description of digital filters. Data flow and Dependence graphs . SYNCHRONOUS. multiple constant multiplication. CONTINUOUS TIME AND LOW. BIT-LEVEL ARITHMETIC ARCHITECTURES 9 Scaling and round-off noise – scaling operation. two-phase clocking. iterative matching.critical path. “ VLSI Digital Signal Processing Systems. rank-order filters. Parallel processing of IIR filters. clock skew in edge-triggered single phase clocking. 2004 VL9254 ANALOG VLSI DESIGN LTPC 3003 UNIT I BASIC CMOS CIRCUIT TECHNIQUES.VOLTAGESIGNAL PROCESSING 9 18 . Springer. DCT architecture. L: 45 REFERENCES: 1. U. Pipelining and Parallel processing for low power. Wiley. Algorithmic strength reduction in filters and transforms – 2-parallel FIR filter.
1990.NMOS and CMOS ". Thermal. UNIT IV DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS 9 Fault modelling and Simulation . Allen. 2.Cascade Design-SwitchedCapacitor Ladder Filter-Synthesis of Switched-Current Filter. McGraw-Hill International Editons.Gate. 1994.Floating . Terri Fiez. 3. Malcom R.Strader. OVER SAMPLED A/D CONVERTERS AND ANALOG INTEGRATED SENSORS 9 First-order and Second SC Circuits-Bilinear Transformation . Randall L Geiger.Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOSTransistor. Yannis Tsividis. “Design of Analog-Digital VLSI Circuits for Telecommunication and signal Processing ".France.Bipolar and Low-Voltage BiCMOS OpAmp Design-Instrumentation Amplifier Design-Low Voltage Filters. TOTAL : 45 REFERENCES: 1. “Analog VLSI Design . Prentice Hall.Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test BusesDesign for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits. VLSI Design Techniques for Analog and Digital Circuits ".Haskard. 4. UNIT II BASIC BICMOS CIRCUIT TECHNIQUES. ANALOG COMPUTERAIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT 9 Review of Statistical Concepts . CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING 9 Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks . Prentice Hall. UNIT III SAMPLED-DATA ANALOG FILTERS. " Noel K.Statistical Circuit SimulationAutomation Analog Circuit Design-automatic Analog Layout-CMOS Transistor LayoutResistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout. “Analog VLSI signal and Information Processing ". Lan C.Statistical Device Modeling. 1998.Nyquist rate A/D ConvertersModulators for Over sampled A/D Conversion-First and Second Order and Multibit SigmaDelta Modulators-Interpolative Modulators –Cascaded Architecture-Decimation Filtersmechanical. 1994 VL9255 DESIGN OF SEMICONDUCTOR MEMORIES LTPC 3003 UNIT I RANDOM ACCESS MEMORY TECHNOLOGIES 9 Static Random Access Memories (SRAMs): SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-Bipolar SRAM 19 .Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS. Phillip E. Mohammed Ismail. Humidity and Magnetic Sensors-Sensor Interfaces. Jose E. Mc Graw Hill International Company.May. Low-Power Neural Networks-CMOS Technology and ModelsDesign Methodology-Networks-Contrast Sensitive Silicon Retina. UNIT V STATISTICAL MODELING AND SIMULATION.
TESTING. Ashok K. Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magnetoresistive. AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE 9 RAM Fault Modeling. DRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions. 2001. 2. Electrical Testing. 20 . Psuedo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing.Haraszti. “CMOS Memory Circuits”. UNIT V PACKAGING TECHNOLOGIES 9 Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening TechniquesRadiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing .Prentice-Hall of India Private Limited. Tegze P. " Semiconductor Memories Technology. Random Access Memories (MRAMs)-Experimental Memory Devices. Kluwer Academic publishers.Radiation Dosimetry-Water Level Radiation Testing and Test Structures. TOTAL: 45 REFERENCES: 1. UNIT III MEMORY FAULT MODELING. Pseudo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and TestingApplication Specific Memory Testing UNIT IV RELIABILITY AND RADIATION EFFECTS 9 General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for ReliabilityReliability Test Structures-Reliability Screening and Qualification. Specific DRAMs. New Delhi. Electrical Testing. 1997. Dynamic Random Access Memories (DRAMs): DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Strucutures-BiCMOS.Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) EPROMs-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-Advanced Flash Memory Architecture. RAM Fault Modeling. Testing and Reliability ".Sharma.Technologies-Silicon On Insulator (SOI) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs. UNIT II NONVOLATILE MEMORIES 9 Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) .
“ Emerging Memories: Technologies and Trends”.3. Kluwer Academic publishers. 21 . Betty Prince. 2002.
“Introduction to NMOS and CMOS VLSI System design Prentice Hall India. Wayne Wolf .1998. Models of Diffusion in Solids. Growth Mechanism and kinetics. DIFFUSION. relative Plasma Etching techniques and Equipments. Electron Lithography. Silicon Shaping.NMOS IC Technology – CMOS IC Technology – MOS Memory IC technology . Feature Size control and Anisotropic Etch mechanism. Oxidation Techniques and Systems. Molecular Beam Epitaxy. “VLSI Technology”. Douglas A. S. Ion Lithography. Oxide properties. UNIT IV PROCESS SIMULATION AND VLSI PROCESS INTEGRATION 9 Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching and Deposition. Pucknell and Kamran Eshraghian. 2. UNIT III DEPOSITION. 3. EPITAXY AND OXIDATION 9 Electronic Grade Silicon. Czochralski crystal growing.”Modern VLSI Design”.2000. UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING 9 Optical Lithography. Mc. plasma assisted Deposition.Hill Second Edition. 2002. Oxidation of Poly Silicon. Vapor phase Epitaxy.VL9256 VLSI TECHNOLOGY LTPC 3003 UNIT I CRYSTAL GROWTH. Redistribution of Dopants at interface. Flick’s one dimensional Diffusion Equation – Atomic Diffusion Mechanism – Measurement techniques . X-Ray Lithography. UNIT V ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES 9 Analytical Beams – Beams Specimen interactions . 2003. Thin Oxides. Prentice Hall India. processing consideration. Oxidation induced Defects. ION IMPLEMENTATION AND METALISATION 9 Deposition process. Amar Mukherjee.Graw. Silicon on Insulators. “ Basic VLSI Design”. 4.Range theory.Chemical methods – Package types – banking design consideration – VLSI assembly technology – Package fabrication technology.Bipolar IC Technology – IC Fabrication. Polysilicon.Sze. WAFER PREPARATION.M. TOTAL: 45 REFERENCES: 1. 22 . Annealing Shallow junction – High energy implantation – Physical vapour deposition – Patterning. Prentice Hall India. Plasma properties.Implant equipment. Epitaxial Evaluation.
Buffered Clock Trees. TOTAL: 45 REFERENCES: 1.Floor plan sizingPlacement: Cost function.K.partition with capacity and i/o constrants.Wein Burger Arrays.Randomised Routing.Gate matrix layout. Timing – Driven Placement: Zero Stack Algorithm.hierarchial approach.Delay in RC trees. Routing in FPGA: Array based FPGA.force directed method. Floor planning: Rectangular dual floor planning.Other issues in minimization UNIT V SINGLE LAYER ROUTING.multicommodity flow based techniques.field programmable gate array(FPGA)-layout methodologiesPackaging-Computational Complexity-Algorithmic Paradigms UNIT II PLACEMENT USING TOP-DOWN APPROACH 9 Partitioning: Approximation of Hyper Graphs with Graphs. Wong. Lorenzatti. 1998. UNIT III ROUTING USING TOP DOWN APPROACH 9 Fundamentals: Maze Running. Preas M. Kernighan-Lin HeuristicRatiocut. VL9258 GENETIC ALGORITHMS AND THEIR APPLICATIONS 23 .1D compaction.Steiner trees Global Routing: Sequential Approaches.2D compaction.Programmable Logic Arrays.Transistor chaining.Integer Linear Programming Detailed Routing: Channel Routing.Linear Programming Approach Timing Driving Routing: Delay Minimization.placement by simulated annealingpartitioning placement.One Step approach.Click Skew Problem.Single Layer detailed Routing.Row based FPGAs UNIT IV PERFORMANCE ISSUES IN CIRCUIT LAYOUT 9 Delay Models: Gate Delay Models. The Benjamin Cummins Publishers. C. “ Physical Design and Automation of VLSI systems”.simulated annealing. CELL GENERATION AND COMPACTION 9 Planar subset problem(PSP). “An Introduction to VLSI Physical Design”.Switch box routing.Single Layer Global Routing. Mc Graw Hill International Edition 1995 2.line searching.Weight based placement. Minimization: constrained via Minimizationunconstrained via Minimization.VL9257 PHYSICAL DESIGN OF VLSI CIRCUITS LTPC 3003 UNIT I INTRODUCTION TO VLSI TECHNOLOGY 9 Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining.module placement on a resistive network – regular placementlinear placement.hierarchial approaches.Models for interconnected Delay.Wire length and bend minimization technique – Over The Cell (OTC) RoutingMultiple chip modules(MCM). Sarafzadeh. Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates.
Marley Maria Bernard Vellasco “Evolution Electronics: Automatic Design of electronic Circuits and Systems Genetic Algorithms”.Koza. Vellasco. “Practical Genetic Algorithms” Wiley – Interscience.”Genetic Algorithm for VLSI Design. CRC press.1977. 2.R.UNIT I Introduction. Morgan Kufmann. 1st Edition Dec 2001. Sue Ellen Haupt.partitioning-automatic placement.Bennett III. 24 .fitness function-GA vs Conventional algorithm.E.Mapping for FPGA. John R. Pinaki Mazumder.GA Technology-Steady State Algorithm-Fitness Scaling-Inversion LTPC 3003 9 UNIT II 9 GA for VLSI Design. David Andre . Forrest H. 4.Automatic test generationPartitioning algorithm Taxonomy-Multiway Partitioning UNIT III 9 Hybrid genetic – genetic encoding-local improvement-WDFR-Comparison of CasStandard cell placement-GASP algorithm-unified algorithm.Layout and test Automation”. 1st Edition .MRudnick. Layout and Test automation. Haupt.routing technology. Total = 45 REFERENCES: 1. Ricardo Sal Zebulum. Marley Maria B. UNIT IV 9 Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame work-test generation procedures. Randy L. Prentice Hall. May 1999. 3.1998. UNIT V 9 Power estimation-application of GA-Standard cell placement-GA for ATG-problem encoding. Macro Aurelio Pacheco. “Genetic Programming Automatic programming and Automatic Circuit Synthesis”.
6.Inc. 25 . “ The Pentium Microprocessor ‘’ Pearson Education .Peatman .” An Introduction to the Intel family of Microprocessors ‘’ Pearson Education 1999. John .” The Intel Microprocessors Architecture . UNIT II HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM 9 CPU Architecture. 5..Breg. James L.B. PHI.” Micro Computer Engineering .” Pearson Education . 3.Miller . Gene . Programming and Interfacing “ . Antonakos . Prentice hall. UNIT V PIC MICROCONTROLLER 9 CPU Architecture – Instruction set – interrupts.pipelining –the instruction pipeline – pipeline hazards – instruction level parallelism – reduced instruction set –Computer principles – RISC versus CISC.H. 8. ‘’ Advanced Microprocessors” McGraw Hill. Daniel Tabak . Barry.ARM instruction set. 7. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint 2001. REFERENCES: 1. 4. UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS 9 Instruction set addressing modes – operating modes. 2000. 1997.Thumb Instruction set. ‘’ ARM System –On –Chip architecture “Addision Wesley . 1997.Antonakos .AP9213 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS LTPC 3003 UNIT I MICROPROCESSOR ARCHITECTURE 9 Instruction Set – Data formats –Addressing modes – Memory hierarchy –register file – Cache – Virtual memory and paging – Segmentation.Interrupsystem.B.2002. 1995 2.Timers.Bus Operations – Pipelining – Brach predication – floating point unitOperating Modes –Paging – Multitasking – Exception and Interrupts – Instruction set – addressing modes – Programming the Pentium processor. 2003. James L. Steve Furber .I2C Interfacing –UART. “ Design with PIC Microcontroller . UNIT III HIGH PERFORMANCE RISC ARCHITECTURE – ARM 9 Organization of CPU – Bus architecture –Memory management unit .RTC-Serial Communication Interface – A/D Converter PWM and UART.addressing modes – Programming the ARM processor.A/D Converter –PWM and introduction to C-Compilers.
Applications of Hopfield Networks – Simulated Annealing – Boltzmann Machine – Bidirectional Associative Memory – BAM Stability Analysis – Error Correction in BAMs .Learning in Radial Basis Function Networks .Applications: XOR Problem – Image Classification.Memory Annihilation of Structured Maps in BAMS – Continuous BAMs – Adaptive BAMs – Applications ADAPTIVE RESONANCE THEORY: 26 .Exact Interpolator – Regularization Theory – Generalized Radial Basis Function Networks . UNIT II 9 RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR MACHINES: RADIAL BASIS FUNCTION NETWORKS: Cover’s Theorem on the Separability of Patterns .AP9252 NEURAL NETWORKS AND ITS APPLICATIONS LTPC 3003 9 UNIT I BASIC LEARNING ALGORITHMS Biological Neuron – Artificial Neural Model . Support Vector Machines: Optimal Hyperplane for Linearly Separable Patterns and Nonseparable Patterns – Support Vector Machine for Pattern Recognition – XOR Problem .Error Performance of Hopfield Networks .Boosting – Associative Gaussian Mixture Model – Hierarchical Mixture of Experts Model(HME) – Model Selection using a Standard Decision Tree – A Priori and Postpriori Probabilities – Maximum Likelihood Estimation – Learning Strategies for the HME Model .Statistical Learning Theory – Single Layer Perceptron – Perceptron Learning Algorithm – Perceptron Convergence Theorem – Least Mean Square Learning Algorithm – Multilayer Perceptron – Back Propagation Algorithm – XOR problem – Limitations of Back Propagation Algorithm.Boltzman Learning – Supervised and Unsupervised Learning – Learning Tasks: Pattern Space – Weight Space – Pattern Association – Pattern Recognition – Function Approximation – Control – Filtering .Beamforming – Memory – Adaptation .-insensitive Loss Function – Support Vector Machines for Nonlinear Regression UNIT III 9 COMMITTEE MACHINES: Ensemble Averaging . UNIT IV 9 ATTRACTOR NEURAL NETWORKS: Associative Learning – Attractor Neural Network Associative Memory – Linear Associative Memory – Hopfield Network – Content Addressable Memory – Strange Attractors and Chaos .EM Algorithm – Applications of EM Algorithm to HME Model NEURODYNAMICS SYSTEMS: Dynamical Systems – Attractors and Stability – Non-linear Dynamical SystemsLyapunov Stability – Neurodynamical Systems – The Cohen-Grossberg Theorem.Types of activation functions – Architecture: Feedforward and Feedback – Learning Process: Error Correction Learning –Memory Based Learning – Hebbian Learning – Competitive Learning .
Demuth. Martin T. Skapura. “Neural Networks: A Comprehensive Foundation”. 2003. Howard B. 2001. 4.Solving Noise-Saturation Dilemma – Recurrent On-center – Off-surround Networks – Building Blocks of Adaptive Resonance – Substrate of Resonance Structural Details of Resonance Model – Adaptive Resonance Theory – Applications UNIT V 9 SELF ORGANISING MAPS: Self-organizing Map – Maximal Eigenvector Filtering – Sanger’s Rule – Generalized Learning Law – Competitive Learning .. “Neural Networks: A Classroom Approach”. 2. Total: 45 REFERENCES: 1. and Mark Beale.Hagan. 3. Addison Wesley Longman (Singapore) Private Limited. Satish Kumar. Simon Haykin. Thomson Learning. “Neural Network Design”. Freeman and David M. 27 . Delhi. 2003.Vector Quantization – Mexican Hat Networks Self-organizing Feature Maps – Applications PULSED NEURON MODELS: Spiking Neuron Model – Integrate-and-Fire Neurons – Conductance Based Models – Computing with Spiking Neurons. Applications. Pearson Education (Singapore) Private Limited. Delhi. 2ed. and Programming Techniques. James A. New Delhi.Noise-Saturation Dilemma . Tata McGraw-Hill Publishing Company Limited. “Neural Networks Algorithms. 2004. New Delhi.
Prentice Hall PTR.VL9261 ASIC DESIGN LTPC 3003 UNIT I INTRODUCTION TO ASICS. UNIT III PROGRAMMABLE ASIC INTERCONNECT.fault simulation . "Application Specific Integrated Circuits.Xilinx I/O blocks. Farzad Nekoogar and Faranak Nekoogar.Transistor Parasitic Capacitance. 2000. 1999.Actel ACT . Rajsuman. PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY 9 Actel ACT -Xilinx LCA .Xilinx EPLD . Santa Clara.Altera MAX 5000 and 7000 .S .Altera MAX 9000 .Clock & Power inputs .Logical effort –Library cell design . UNIT II PROGRAMMABLE ASICS. 3. UNIT IV LOGIC SYNTHESIS.Half gate ASIC -Schematic entry .FPGA partitioning . R.Design flow . PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS 9 Anti fuse .partitioning methods . 1997.placement physical design flow –global routing .Low level design language . System-on-a-Chip Design and Test. 2003. 2.Library architecture .Data path logic cell . Timing Verification of Application-Specific Integrated Circuits (ASICs).Altera MAX DC & AC inputs and outputs .types of simulation -boundary scan test . 2004.floor planning . CMOS LOGIC AND ASIC LIBRARY DESIGN 9 Types of ASICs .. FLOOR PLANNING. From ASICs to SOCs: A Practical Approach.J. PLACEMENT AND ROUTING 9 System partition .Altera FLEX –Design systems . SIMULATION AND TESTING 9 Verilog and logic synthesis -VHDL and logic synthesis .CMOS transistors CMOS Design rules .circuit extraction DRC. 4.Xilinx LCA –Altera FLEX .CFI design representation.detailed routing . Prentice Hall PTR. Nekoogar. FPGA-Based System Design. UNIT V ASIC CONSTRUCTION. 5. 28 . Addison -Wesley Longman Inc. CA: Artech House Publishers. M.special routing . TOTAL: 45 REFERENCES: 1. Prentice Hall PTR. F.Transistors as Resistors . Wayne Wolf.PREP benchmarks .EPROM and EEPROM technology .Smith.PLA tools -EDIF.Logic Synthesis .automatic test pattern generation.static RAM .Combinational Logic Cell – Sequential logic cell .
Safety margin and loading roughness on reliability. Reliability in electronic system design. extreme value . reliability and costs. Reliability modeling. 4. Patrick D. 2000. prediction and measurement. reliability growth monitoring. TOTAL: 45 REFERENCES: 1. John Wiley & Sons.HALT and HASS". New York. standard for reliability. Hobbs. John Wiley & Sons. Integrated reliability programmes . Accelerated test data analysis. failure reporting. David Newton and Richard Bromley.probability plotting techniques – Weibull. 2nd Edition. Von Nostrand Reinhold. organization for reliability. hardware/software interfaces. Block diagram and Fault tree Analysis . MODELLING AND DESIGN 9 Statistical design of experiments and analysis of variance Taguchi method. 2002 David J. Fourth edition. "Introduction to Reliability Engineering". New York. testing for reliability and durability. 1996. Reliability prediction. Pareto analysis. software structure and modularity. Wiley International. Analysis of load – strength interference . preventive maintenance strategy. Klinger. Practical Reliability Engineering. failure modes. 1998. binomial data. component types and failure mechanisms. UNIT III ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY 9 Reliablity of electronic components. Design for maintainability. UNIT V MANUFACTURE AND RELIABILITY MAQNAGEMENT 9 Control of production variability.petric Nets.hazard. fault tolerance. Lewis. reliability demonstration. State space Analysis. Gregg K. Monte carlo simulation. Menendez. 5th Edition. software reliability. statistical confidence and hypothesis testing . UNIT IV RELIABILITY TESTING AND ANALYSIS 9 Test environments. Quality control and stress screening. quality and safety. Yoshinao Nakada and Maria A. effects and criticality analysis. 2. load strength analysis. Maintenance schedules. "AT & T Reliability Manual". O’Connor. AP9256 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN LTPC 29 . Electronic system reliability prediction. 3. specifying reliability.T. Design analysis methods – quality function deployment. software errors. Acceptance sampling.NE9251 RELIABILITY ENGINEERING LTPC 3003 UNIT I PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE 9 Statistical distribution . Production failure reporting. UNIT II RELIABILITY PREDICTION. "Accelerated Reliability Engineering . CUSUM charts. Exploratory data analysis and proportional hazards modeling.
Terminations. UNIT V EMI MEASUREMENTS AND STANDARDS 9 Open area test site. EN.”Introduction to Electromagnetic Compatibility” . Near field cable to cable coupling.”Noise Reduction Techniques in Electronic Systems”. Power distribution decoupling. 1988. VIAs connection. Measurements and Technologies”. Field to cable coupling . “Handbook of EMI/EMC” . 5. “Engineering EMC Principles. Cross talk control. Vol I-V. radiated and transient coupling.. Filtering. Sensors.R.P. ESD. V. 1996. Grounding. 4.Ott. TOTAL: 45 REFERENCES: 1. Bonding. Common mode and ground loop coupling . Civilian standards-CISPR.J. Military standards-MIL461E/462.White Consultant Incorporate. and coupling factors. Tx /Rx Antennas. Differential mode coupling . 1986. Bemhard Keiser. Norwood.Kodali. TEM cell. IEC. cross talk . EMI test shielded chamber and shielded ferrite lined anechoic chamber. Cable routing. UNIT IV EMC DESIGN OF PCBS 9 Component selection and mounting. Newyork. Routing. 1988. C. UNIT II EMI COUPLING PRINCIPLES 9 Conducted. John Wiley and Sons. Sources and victim of EMI. Newyork. A Wiley Inter Science Publications. Power mains and Power supply coupling. Common ground impedance coupling . Henry W. Inc. 3.Paul. Injectors / Couplers. Transient EMI. John Wiley and Sons. Grounding. EMI Rx and spectrum analyzer. Radiation Hazards. Isolation transformer. “Principles of Electromagnetic Compatibility”. Zoning. Transient suppressors. PCB trace impedance. 3rd Ed. 2. Artech house. UNIT III EMI CONTROL TECHNIQUES 9 Shielding. Signal control. Conducted and Radiated EMI Emission and Susceptibility. 1992. VL9264 DIGITAL SPEECH SIGNAL PROCESSING LTPC 3003 8 UNIT I MECHANICS OF SPEECH 30 . FCC.3003 UNIT I EMI/EMC CONCEPTS 9 EMI-EMC definitions and Units of parameters. IEEE Press. Don R.
Ben Gold and Nelson Morgan. HOMOMORPHIC SPEECH ANALYSIS: Cepstral analysis of Speech – Formant and Pitch Estimation – Homomorphic Vocoders. hidden Markov model – Music analysis – Pitch Detection – Feature analysis for recognition –Automatic Speech Recognition – Feature Extraction for ASR – Deterministic sequence recognition – Statistical Sequence recognition – ASR systems – Speaker identification and verification – Voice response system – Speech Synthesis: Text to speech.Witten – – Principles of Computer Speech – Academic Press – 1982 VL9265 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING LTPC 3003 31 . 2004 2.Rabiner and R. voice over IP. dynamic time warping.Speech production mechanism – Nature of Speech signal – Discrete time modelling of Speech production – Representation of Speech signals – Classification of Speech sounds – Phones – Phonemes – Phonetic and Phonemic alphabets – Articulatory features. L.H.Phase vocoder— Channel Vocoder.Analysis synthesis systems. John Wiley and Sons Inc. UNIT V APPLICATION OF SPEECH SIGNAL PROCESSING 10 Algorithms: Spectral Estimation. Speech and Audio Signal Processing.Schaffer – Digital Processing of Speech signals – Prentice Hall -1978 3. Quatieri – Discrete-time Speech Signal Processing – Prentice Hall – 2001. Music production – Auditory perception – Anatomical pathways from the ear to the perception of sound – Peripheral auditory system – Psycho acoustics UNIT II TIME DOMAIN METHODS FOR SPEECH PROCESSING 8 Time domain parameters of Speech signal – Methods for extracting the parameters Energy. J. 4. .R. I.W.Flanagan – Speech analysis: Synthesis and Perception – 2nd edition – Berlin – 1972 5.L. Average Magnitude – Zero crossing Rate – Silence Discrimination using ZCR and energy – Short Time Auto Correlation Function – Pitch period estimation using Auto Correlation Function UNIT III FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING 9 Short Time Fourier analysis – Filter bank analysis – Formant extraction – Pitch Extraction – Analysis by Synthesis. UNIT IV LINEAR PREDICTIVE ANALYSIS OF SPEECH 10 Formulation of Linear Prediction problem in Time Domain – Basic Principle – Auto correlation method – Covariance method – Solution of LPC equations – Cholesky method – Durbin’s Recursive algorithm – lattice formation and solutions – Comparison of different methods – Application of LPC parameters – Pitch detection using LPC parameters – Formant analysis – VELP – CELP. REFERENCES: 1. Singapore.
Venkataramani and M. 32 .Addressing modes and assembly language instructions – Application programs –Filter design. UNIT V ADVANCED PROCESSORS 9 Architecture of TMS320C54X: Pipe line operation. Convolution of two sequences. “Digital Signal Processors – Architecture.Bhaskar. Programming and Applications” – Tata McGraw – Hill Publishing Company Limited. 2.Architecture of Motorola DSP563XX – Comparison of the features of DSP family processors. Analog Devices. TOTAL: 45 REFERENCES: 1. FFT calculation. 2003.Pipelining – Special Addressing modes in P-DSPs – On chip Peripherals.UNIT I FUNDAMENTALS OF PROGRAMMABLE DSPs 9 Multiplier and Multiplier accumulator – Modified Bus Structures and Memory access in PDSPs – Multiple access memory – Multi-port memory – VLIW architecture. B. Operation – Block Diagram of DSP starter kit – Application Programs for processing real time signals. UNIT III TMS320C3X PROCESSOR 9 Architecture – Data formats . UNIT II TMS320C5X PROCESSOR 9 Architecture – Assembly language syntax .Addressing modes – Assembly language Instructions .Pipeline structure.Instruction sets . Motorola.Addressing modes – Groups of addressing modes. Filter design UNIT IV ADSP PROCESSORS 9 Architecture of ADSP-21XX and ADSP-210XX series of DSP processors. Code Composer studio . User guides Texas Instrumentation.Operation – Block Diagram of DSP starter kit – Application Programs for processing real time signals – Generating and finding the sum of series. New Delhi.Architecture of TMS320C6X .
MEMS materials. 2000. Bending of thin plates. Case studies – Capacitive accelerometer. MEMS scanners and retinal scanning display. torsional deflection. Peizo electric pressure sensor. Miniaturization.” MEMS & Micro systems Design and Manufacture” Tata McGraw Hill. 33 . Kluwer publishers. Fracture and thin film mechanics.” Microsystems Design”. editor. Electromagnetic actuators. UNIT V INTRODUCTION TO OPTICAL AND RF MEMS 9 Optical MEMS.System design basics – Gaussian optics. Feed back systems. Comb generators. resolution.VL9266 INTRODUCTION TO MEMS SYSTEM DESIGN LTPC 3003 UNIT I INTRODUCTION TO MEMS 9 MEMS and Microsystems. 2000 3. Microaccelorometers and Micro fluidics. case study – Capacitive RF MEMS switch. Micro actuation. performance issues. electro static instability. Stephen Santuria. Mohamed Gad-el-Hak. Tai Ran Hsu.” The MEMS Handbook”. RF Memes – design basics. Digital Micro mirror devices. MEMS with micro actuators. Resonance. matrix operations. strain and material properties. Typical products. Micro fabrication UNIT II MECHANICS FOR MEMS DESIGN 9 Elasticity. Mechanical vibration. New Delhi. bistable actuators. Surface tension. Modelling of MEMS systems. 2. UNIT IV CIRCUIT AND SYSTEM ISSUES 9 Electronic Interfaces. Thermo mechanics – actuators. rotary motors. Stress.” An introduction to Micro electro mechanical system design”. Case studies. gap and finger pull up. Noise . Circuit and system issues. Spring configurations. inch worms. CRC press Baco Raton. 2002. CAD for MEMS. Nadim Maluf.2000. Micro sensors. Electro static actuators. force and response time. UNIT III ELECTRO STATIC DESIGN 9 Electrostatics: basic theory. TOTAL: 45 REFERENCES: 1. 4. gap closers. . Artech House.
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