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NOVAS nTX Tutorial

NOVAS nTX Tutorial

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Sections

  • About This Book
  • Purpose
  • Audience
  • Book Organization
  • Conventions Used in This Book
  • Related Publications
  • How to Reach Novas Software, Inc
  • Introduction
  • Overview - Why nTX?
  • Technology
  • Transaction Analysis
  • Transaction Generation/Extraction
  • Debug with Transactions
  • Overview
  • What is a Transaction?
  • Generating Transaction Data
  • Use Model
  • Detailed Transaction View
  • Selecting Transactions
  • Transaction Properties
  • Transaction Attributes
  • Analyzing Transactions
  • Transaction Extraction
  • Use SystemVerilog Assertions (SVA)
  • SVA Code
  • Use nTE
  • Pre-requisites
  • Installing nTE from the Internet
  • Set Up the Environment
  • Bus Configuration File (BCF) Format
  • nTE Results
  • Transaction Tutorials
  • Before You Begin
  • View Transactions in nWave
  • Import FSDB File
  • Add Transaction Waveforms
  • View Transactions in Transaction Analyzer Window
  • Add/Remove Transaction Streams
  • Merge Transaction Streams
  • Manipulate the Stream View
  • Generate Statistics
  • Analyze Transactions Using TCL
  • Execute the TCL File
  • Manipulate Transactions and View Statistics with TCL
  • Example TCL Script
  • Generate an FSDB File with Transaction Information
  • PLI Background
  • Procedures for Writing a PLI Routine
  • Steps for Writing FSDB
  • Steps to Dump Transactions to FSDB
  • C Files for FSDB Writer API
  • Use Provided C Files for PCI Transaction Dumping
  • Appendix A: AMBA AHB Transactor
  • BCF Format
  • Name
  • Mapping Root
  • Signal Map
  • Parameters
  • Transactor Configurations
  • Transaction Hierarchy
  • Protocol Tree
  • Transaction Description
  • Additional Information
  • Data Types
  • Transactor Constants
  • Appendix B: AMBA AHB Lite Transactor
  • Appendix C: AMBA APB Transactor
  • Appendix D: AMBA AXI Transactor
  • Appendix E: MPEG2_TS Transactor
  • Appendix F: OCP-IP Transactor
  • Limitations
  • Appendix G: PCI-Express (PCIe) Transactor
  • Appendix H: UART Transactor
  • Protocol Tree - TX
  • Protocol Tree - RX
  • Appendix I: USB Transactor
  • Index

nTX

User’s Guide and Tutorial

NOVAS Software, Inc.
NOVAS Software, Inc. 2025 Gateway Place, Suite 400, San Jose, CA 95110 Phone: 1-888-NOVAS-38 (1-888-668-2738) Fax: 408-467-7889 www.novas.com

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Printing
Printed on June 30, 2006.

Version
This manual supports Verdi and nTX 2006.04 and higher versions.

Copyright
All rights reserved. No part of this manual may be reproduced in any form or by any means without written permission of: NOVAS Software, Inc. 2025 Gateway Place, Suite 400, San Jose, CA 95110 www.novas.com Copyright (c) 1996-2006 NOVAS Software, Inc.

Trademarks
Debussy is a registered trademark and Verdi is a trademark of Novas Software, Inc. Verdi, nTrace, nSchema, nState, nWave, Temporal Flow View, nBench, nCompare, nLint, nECO, nESL, nTX, nAnalyzer, Active Annotation, and Knowledge-Based Debugging are trademarks of Novas Software, Inc. The product names used in this manual are the trademarks or registered trademarks of their respective owners.

Restricted Rights
The information contained in this document is subject to change without notice.

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Contents

Contents
About This Book 7
Purpose......................................................................................................... 7 Audience ...................................................................................................... 7 Book Organization ....................................................................................... 8 Conventions Used in This Book .................................................................. 9 Related Publications................................................................................... 10 How to Reach Novas Software, Inc........................................................... 11

Introduction

13

Overview - Why nTX?............................................................................... 13 Technology ................................................................................................ 14 Transaction Analysis ............................................................................ 14 Transaction Generation/Extraction....................................................... 14

Debug with Transactions

15

Overview.................................................................................................... 15 What is a Transaction?.......................................................................... 15 Generating Transaction Data ................................................................ 15 Use Model.................................................................................................. 16 Detailed Transaction View ................................................................... 16 Selecting Transactions .......................................................................... 17 Transaction Properties .......................................................................... 18 Transaction Attributes .......................................................................... 19 Analyzing Transactions ........................................................................ 19 Generating Transaction Data ................................................................ 20

Transaction Extraction

23

Use SystemVerilog Assertions (SVA)....................................................... 23 Use Model............................................................................................. 23 SVA Code............................................................................................. 24 Use nTE ..................................................................................................... 29 Pre-requisites ........................................................................................ 29 Installing nTE from the Internet ........................................................... 30 Set Up the Environment........................................................................ 31 Use Model............................................................................................. 31

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nTX User’s Guide and Tutorial

Bus Configuration File (BCF) Format.................................................. 32 nTE Results........................................................................................... 35

Transaction Tutorials

37

Before You Begin ...................................................................................... 37 View Transactions in nWave ..................................................................... 38 Import FSDB File ................................................................................. 38 Add Transaction Waveforms................................................................ 38 View Transactions in Transaction Analyzer Window ............................... 41 Import FSDB File ................................................................................. 41 Add/Remove Transaction Streams ....................................................... 41 Merge Transaction Streams .................................................................. 43 Manipulate the Stream View ................................................................ 45 Generate Statistics ................................................................................ 50 Analyze Transactions Using TCL.............................................................. 54 Execute the TCL File............................................................................ 54 Manipulate Transactions and View Statistics with TCL ...................... 55 Example TCL Script ............................................................................. 58 Generate an FSDB File with Transaction Information .............................. 64 PLI Background.................................................................................... 64 Procedures for Writing a PLI Routine .................................................. 65 Steps for Writing FSDB........................................................................ 69 Steps to Dump Transactions to FSDB .................................................. 70 C Files for FSDB Writer API ............................................................... 72 Use Provided C Files for PCI Transaction Dumping ........................... 73

Appendix A: AMBA AHB Transactor

75

Overview.................................................................................................... 75 BCF Format ............................................................................................... 75 Name..................................................................................................... 75 Mapping Root ....................................................................................... 75 Signal Map............................................................................................ 76 Parameters............................................................................................. 76 Transactor Configurations .................................................................... 78 Transaction Hierarchy................................................................................ 78 Protocol Tree ........................................................................................ 79 Transaction Description........................................................................ 80 Additional Information .............................................................................. 86 Data Types ............................................................................................ 86 Transactor Constants ............................................................................ 88

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............................................. 98 Transactor Constants ................................................................................... 98 Data Types ............... 89 Signal Map....................................................................... 116 www.................................... 89 Mapping Root ................................... 109 Data Types ........ 113 Transactor Configurations ................................................................................................................................................. 115 Protocol Tree ............................................................................................................................... 92 Protocol Tree ...........................................................we will delete ........................................................................................................................ 89 Name...................... 100 Appendix C: AMBA APB Transactor 101 Overview..............................................if tort to your rights..................................................................................................Appendix B: AMBA AHB Lite Transactor 89 Overview..................... 90 Transactor Configurations .............................................................................................................. 90 Parameters.................................................................................... 101 Signal Map.............................................................................................................................................................. 89 BCF Format .................................. 102 Transactor Configurations .................................................... 111 Signal Map........................................................ 114 Transaction Hierarchy..................................... 106 Additional Information ........................................ 112 Parameters................................................................................................................................................. 111 Mapping Root ............................ 111 BCF Format ................................................................... 105 Transaction Description......................................................com EMail:cadserv21@hotmail............................. 91 Transaction Hierarchy.........................................................................com 3 The document is for study only........................................................... 102 Parameters............................................................................ 103 Transaction Hierarchy................................................................................................ 111 Name.. 101 Mapping Root ............... 109 Transactor Constants .............................. 109 Appendix D: AMBA AXI Transactor 111 Overview...................................................................................................................................please inform us..... 94 Additional Information .....cadfamily................................................................................................................................................................................................... 101 Name....................................................................................................................................................................... 105 Protocol Tree ................................................................................................................................................................................................................... 101 BCF Format ..................... 93 Transaction Description..................................................................................................

.......................................... 156 Appendix G: PCI-Express (PCIe) Transactor 157 Overview............................. 131 Signal Map.....nTX User’s Guide and Tutorial Transaction Description.............................................................................................................................. 131 Mapping Root ............................................................................................... 132 Transactor Configurations ...................................................................................................................... 132 Parameters......................................................... 139 Name................. 134 Transaction Description.................................... 127 Transactor Constants ...................................................................................cadfamily................................ 157 BCF Format .................................................................................................................................................. 145 Transaction Hierarchy.............................................................................................................................. 127 Data Types .................................................................. 157 Mapping Root .................................................................................................................. 135 Additional Information ......... 139 Mapping Root ..................... 131 Name....................................................................................................................................................................................................................................................................................................................... 157 www...................................................................................... 147 Transaction Description...com EMail:cadserv21@hotmail.............................. 129 Appendix E: MPEG2_TS Transactor 131 Overview.................................... 140 Parameters..........................com 4 The document is for study only. 157 Name...................................................................................................................... 148 Additional Information ..................... 155 Data Types ........................ 138 Appendix F: OCP-IP Transactor 139 Overview........................................................... 131 BCF Format ................................................................................. 146 Protocol Tree ........................................................we will delete ................................ 141 Transactor Configurations ............................................................................................... 133 Transaction Hierarchy........................................................................................................................................................................................................................................................................................................................ 139 BCF Format ............................................................................................................................... 133 Protocol Tree ................................................... 155 Transactor Constants ............................................................ 138 Data Types ........................................................ 140 Signal Map.......................................................................... 117 Additional Information ................................................................................... 139 Limitations.....please inform us................if tort to your rights...............

............................................................ 161 Transaction Description....................................................................................................... 179 Protocol Tree ........... 181 Additional Information .......... 169 Data Types ........................... 175 Mapping Root .................................................................Signal Map.................. 188 Parameters.................................................................................. 187 Mapping Root . 192 Additional Information ............................................................................................................................................................................ 190 Protocol Tree ............................................................................................................................................................................................................................. 162 Additional Information ............................ 176 Parameters............................................................. 176 Signal Map....................................................... 169 Appendix H: UART Transactor 175 Overview...... 160 Transaction Hierarchy.. 175 BCF Format .......................................... 161 Protocol Tree ....................... 187 Signal Map........................... 187 BCF Format ............................ 178 Transaction Hierarchy............................................................................................................... 185 Appendix I: USB Transactor 187 Overview............................................................................................... 176 Transactor Configurations ............................................................................................................... 159 Transactor Configurations ....................................... 178 Protocol Tree ........................................................................................................................................if tort to your rights............................................................................com 5 The document is for study only.................................................................please inform us...........................................................we will delete ............................... 188 Transactor Configurations ..................................................... 180 Transaction Description...... 187 Name................................................................................................. 175 Name.......................................................................................................................................................................................................................................................................................................................................................................................TX..........................................com EMail:cadserv21@hotmail............................ 158 Parameters........ 198 Data Types .................RX.......................................................................................... 198 Index 201 www............................................................................... 191 Transaction Description......................................................................................................... 190 Transaction Hierarchy.......................................... 185 Data Types ....................................cadfamily..........................

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Field Programmable Gate Arrays (FPGAs).please inform us. This document assumes that you have a basic knowledge of the platform on which your version of Verdi runs: UNIX or Linux and that you are knowledgeable in Verilog or VHDL. both scalable and efficient. please refer to the appropriate chapter of the Novas Command Reference Manual. C++. www. an add-on to Novas’s Verdi debugging system.cadfamily. Audience The audience for this manual includes engineers who are familiar with modeling techniques and languages used in high level design such as the use of transactions. and digital logic design. SystemC. If you do not feel comfortable with basic Verdi operations.About This Book About This Book Purpose This book is designed to allow you to quickly become proficient in the nTX module. For detailed descriptions of individual commands. This book focuses on the most commonly used commands without going into detail on everything. You should already be familiar with Verdi before beginning this book.com EMail:cadserv21@hotmail. automated debugging tools. Modeling at this abstract level requires more capable. The application domain of these modeling approaches and languages can be for System-on-Chip (SoC). boardlevel.com 7 The document is for study only. and numerous other programmable or custom design blocks and components. simulation software. although you may skip any sections with which you are already familiar. or platform designs implemented with Application Specific Integrated Circuits (ASICs).if tort to your rights. and developing hardware and/or software designs using C.we will delete . please review the Verdi User’s Guide and Tutorial document first. The manual should be read from beginning to end.

Appendix A-I provides detailed information for extracting the AHB. as well as debug with. as well as debug with. PCI.com EMail:cadserv21@hotmail. MPEG2-TS.nTX User’s Guide and Tutorial Book Organization This nTX User’s Guide and Tutorial is organized as follows: • • • • • • About This Book provides an introduction to this book and explains how to use it.cadfamily. AHB-lite.we will delete . Transaction Extraction provides details on different methods for extracting transactions. • www.com 8 The document is for study only. Debug with Transactions provides details regarding the recording and creation of. UART and USB protocols respectively with nTE. transactions in Verdi with nTX. capabilities. APB. AXI. and utilities. transactions in Verdi with nTX.if tort to your rights. Introduction provides an overview of nTX and introduces its broadly applicable use methodology and unique environment. Index is a detailed index to this book. Transaction Tutorials provides examples regarding the recording and creation of. OCP-IP.please inform us.

Click-left or Click means click the left mouse button on the indicated item. book titles. www. and file names within paragraphs.com 9 The document is for study only.com EMail:cadserv21@hotmail.please inform us. Click-right means click the right mouse button on the indicated item.cadfamily.we will delete . menu items. Menu->Command identifies the path used to select a menu command. then move the pointer to the destination and release the button. Note describes important information. section names. Bold is used to emphasize text. It is also used for test messages that nTX displays on the screen. Shift-click-left means press and hold the <Shift> key then click the left mouse button on the indicated item. Double-click means click twice consecutively with the left mouse button.About This Book Conventions Used in This Book The following conventions are used in this book: • • • • • • • • • • • • Italics font is used for emphasizes. warnings. Drag-left means press and hold the left mouse button.if tort to your rights. and other nTX terms. Courier type is used for program listings. Drag means press and hold the middle mouse button on the indicated item then move and drop the item to the other window. or unique commands. Click-middle means click the middle mouse button on the indicated item. file path. design names. highlight titles.

gives detailed information on linking Novas object files with supported simulators for FSDB dumping.org) or vendor (www.com) websites. etc.gives detailed information on the Verdi and Debussy command set including nTX. Library Developer’s Guide .detailed information on using nCompare.) language reference materials are not included in this manual. www. please refer to the appropriate language standards board (www.accellera.detailed information on using Verdi. For language related documents. VHDL.nTX User’s Guide and Tutorial Related Publications • • • • Novas Installation and System Administration Guide .detailed information on using nECO. Linking Novas Files with Simulators to Enable FSDB Dumping .ieee. etc. nESL User’s Guide and Tutorial . nLint User’s Guide and Tutorial .if tort to your rights. Language Documentation Hardware description (Verilog. Verdi User’s Guide and Tutorial . www.please inform us.detailed information on using nLint.we will delete .synopsys.com.com.detailed information on using nESL. nAnalyzer User’s Guide and Tutorial .detailed information on using nAnalyzer.for current information about the latest software version.com 10 The document is for study only. Verdi Release Notes .org.cadfamily.cadence. Vera. nECO User’s Guide and Tutorial .provides information on creating. • • • • • • • • • www. see the Verdi Release Notes shipped with the product and the installation files in the distribution directories.explains how to install Novas products including Verdi. nCompare User’s Manual . Verdi and Debussy Quick Reference Guide .com EMail:cadserv21@hotmail. Verdi and Debussy Command Reference Manual . verifying and using symbol libraries. www.gives a brief summary of the different modules and related mouse commands and bind keys. SystemVerilog.) and verification (e.verisity.

support@novas.com 11 The document is for study only.please inform us.O. Corporate Headquarters: 2025 Gateway Place. Suite 400 San Jose.com for technical support.we will delete . No. Phone: 1-888-NOVAS-38 (1-888-668-2738) or 408-467-7888 FAX: 408-467-7889 E-Mail: sales@novas.C.com for license request and sales information. 25. Inc.S. Industry East Road IV Science-Based Industrial Park Hsinchu.novas.if tort to your rights.cadfamily.com EMail:cadserv21@hotmail.com Asia Headquarters: 5F. Taiwan R. URL: http://www.A.About This Book How to Reach Novas Software. Phone: 886-3-567-9656 FAX: 886-3-567-0066 www. CA 95110 U.

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adding advanced system and platform debugging technologies with unified support for the diverse methodologies involved in such designs. particularly with complex protocols.com EMail:cadserv21@hotmail. The nTX technology addresses multiple key requirements: • • Comprehensive transaction analysis environment that provides easy understanding of complex device communication. Transaction-level abstractions ease the understanding of on-chip communication and bus complexity. They are an extremely powerful datalevel abstraction that help users think about high-level design and functionarchitecture trade-offs.com 13 The document is for study only. understand and debug the information. nTX. www. builds on top of the comprehensive Verdi debug system.cadfamily. Leverage powerful automated RTL debug system and significant debug experience from a wealth of application areas.we will delete . Automation tools must enable analysis functions including bus loading and utilization. engineers still need a way to visualize. resource usage. synchronization and the like. system performance evaluation such as throughput and latency.Why nTX? Transactions have been used for years to model system-level behavior.Introduction Introduction Overview .please inform us. correlation across bus bridges.if tort to your rights. mainly with in-house simulation environments. however.

Transaction Generation/Extraction The transaction data can be obtained from one or more of the following diverse sources: • Native FSDB dumper function calls embedded in the system model. Extraction from SystemVerilog Assertions.) Transaction IP-provider partners such as Denali and Spiratech. Spreadsheet view that supports data management and presentation functions such as sorting/filtering of transactions and statistical analysis.com 14 The document is for study only.if tort to your rights. and also from the HVLs (such as ‘e’. available soon.cadfamily. • • • www.please inform us.nTX User’s Guide and Tutorial Technology nTX provides support in the following areas. SystemC SCV methods. Transaction Analysis The current support for transaction level verification and debug in nTX is as follows: • • Transaction waveform visualization in nWave.we will delete .com EMail:cadserv21@hotmail. End user coding using the FSDB writer API.

Create attributes. For testbench verification. a powerful viewing mechanism for transactions is mandatory to system designers.cadfamily. there is no such concept as "transaction type". even if the sets of attributes that constitute two transactions are the same.com EMail:cadserv21@hotmail.Debug with Transactions Debug with Transactions Overview Transactions are an important piece of abstraction in system design and debug. therefore. Create a transaction. When an error is found in the transaction level. When you create a transaction.we will delete . Create a stream. transaction IP partners. Transaction streams can be dumped into FSDB format using dumping libraries provided by Novas and its partners or using the Open Transaction Interface (OTI) extension of the Novas FSDB Writer API. Each transaction consists of a set of attributes and is independent of one another. you must follow the steps below: 1.com 15 The document is for study only. What is a Transaction? Transactions are higher level abstractions of signal-level detailed activity. 4. the signal level is then investigated. or the FSDB writer API and Open Transaction Interface (OTI).please inform us. 2. System design is in a very early stage of the whole design process. Streams hold transactions. Generating Transaction Data The transaction data can be obtained from Novas provided native FSDB dumpers. if the entire system is to be verified. That is. www. Transaction data can also be extracted from your code using SystemVerilog Assertions.if tort to your rights. transaction level checking is efficient and easy to focus comparisons of system behavior against system specification. Transactions are organized into streams. Create relationships between existing transaction. 3. as in SCV.

nTX User’s Guide and Tutorial

Use Model
The transaction FSDB file is loaded into nWave the same way as a general FSDB file. A stream name will be shown in the signal pane; begin time, end time, and attributes are shown in the value pane; and the transaction will be shown in the waveform pane as rectangles enclosing all the attributes. This section includes the following topics: • • • • • • Detailed Transaction View Selecting Transactions Transaction Properties Transaction Attributes Analyzing Transactions Generating Transaction Data

Detailed Transaction View
The following figure summarizes the different aspects of transaction viewing in nWave.

Figure: Detailed Transaction View

Although there is a begin time and end time in a transaction, when you click on a transaction, the cursor will be located at the begin time. When you select a stream, you can click the Search Backward/Search Forward icons (blue left/ right arrows) on the nWave toolbar to step through the transactions. A dashed line

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Debug with Transactions

under the transaction box indicates there are more attributes than are currently displayed. You can increase (decrease) the height of the stream in the signal pane to show more (less) attributes. Alternatively, you can move the cursor on top of the transaction attributes in the value pane (middle column) to activate a tip showing all attributes as displayed in the following figure.

Figure: Transaction Tip

Selecting Transactions
Individual transactions can be selected by clicking on the label in the waveform pane; the background color of the selected transaction will change to light blue. Pressing the Search Backward/Search Forward toolbar icons will not change the selected transaction but will change waveform cursor time. The selection is important for viewing the covered or obscured transactions when there is a time overlap for multiple transactions. The top triangle is used to select the underlying transaction and bring it to the front.

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nTX User’s Guide and Tutorial

If there are transactions related to the selected one, the related transaction will be highlighted with a pink background color, similar to the following example.

Figure: Transaction Relationships

Transaction Properties
Transactions contain a lot of data. You can view the attributes and relationships of a selected transaction in a tabular format. To open the Transaction Property form, select a transaction, click-right to open the context menu, and chose the Properties… command. The Attributes tab summarizes the transaction attributes, as shown in the following example:

Figure: Transaction Property Dialog Window - Attributes

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Debug with Transactions

You can view the selected transaction relationships by selection the Relationship tab in the Transaction Property form.

Transaction Attributes
You can use string matching to search attributes. In nWave, choose Waveform -> Set Search Attributes… to open the Search Attribute Value form. Alternatively, you can click-left on the Search By: icon on the toolbar and select the Transaction Attribute Values option.

Figure: Search Attribute Value Form

You can specify the attribute name and value. Once you’ve entered the search criteria and clicked OK, you can use the Search Forward/Search Backward icons on the nWave toolbar to step through the transactions of the selected streams.

Analyzing Transactions
In addition to the waveform viewing capability for transactions, you can open the Transaction Analyzer window by invoking Tools -> Transaction Analyzer -> Open Transaction Analyzer Window from nWave. Once the window is open, you can load one or more streams individually or merge multiple streams together.

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you can use View -> Find to locate a string or pattern. Generating Transaction Data The transaction data can be obtained from the following sources.nTX User’s Guide and Tutorial The window will be similar to the following: Figure: Transaction Analyzer Window For the current selected stream (or merged streams). and HVL simulators.supported OSCI and NCSC simulators.cadfamily.if tort to your rights.please inform us. ModelSim) • Vera Click here to access the SystemC Linking chapter in the Linking Novas Files with Simulators to Enable FSDB Waveform Dumping manual for details on linking native FSDB dumpers. you can choose View -> Show All to restore all the transaction data. or View -> Filter to filter and display transactions whose attributes match user-specified conditions.we will delete . SystemC SCV.com EMail:cadserv21@hotmail. Provided FSDB Dumpers Dump transaction data from languages directly with native FSDB dumpers. After filtering a stream.com 20 The document is for study only. These commands allow you to more quickly navigate the streams and focus on the transactions of interest. SystemC/SCV -. Specman/e SystemVerilog test bench in conjunction with simulator support (VCS. • • • www.

com 21 The document is for study only.we will delete . Click here for an example. The transactions can then be extracted from a signal level FSDB.if tort to your rights. you can use the Open Transaction Interface (OTI) extension of the FSDB writer API to dump transaction data.cadfamily.com EMail:cadserv21@hotmail. Click here for more details. FSDB Writer API and the Open Transaction Interface (OTI) If you are unable to generate transaction data in FSDB format from any of the previously mentioned methods.please inform us. www.Debug with Transactions Transaction IP Partners Please contact Denali (PCI-Express) or Spiratech (AMBA AXI. AHB) directly for details on dumping FSDB format from their available intellectual property (IP). SVA Extraction You can add SystemVerilog Assertions (SVA) constructs to your design code to represent transactions.

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Add SVA code to your design either inlined or as a separate file. www. This opens the Transaction Evaluator form where all SVA assert signals are listed. Use Model Before you can to extract transactions from SVA. 2. Once the design and FSDB file are loaded into Verdi.if tort to your rights.com 23 The document is for study only. Generate an FSDB file containing design data with your preferred simulator. Load the design and FSDB file into Verdi. 3. Use SystemVerilog Assertions (SVA) SVA can be added to your design and then extracted to display as transactions.please inform us.com EMail:cadserv21@hotmail.cadfamily.Transaction Extraction Transaction Extraction There are two primary methods of extracting transaction information from a signal level FSDB: • • Use SystemVerilog Assertions (SVA) Use nTE The SVA method can be used with proprietary protocols and the nTE method supports a variety of industry standard protocols.we will delete . you must do the following: 1. you can extract the transactions by invoking Tools -> Transaction -> Transaction Evaluator.

com 24 The document is for study only. After you click Run.if tort to your rights. You can also drag any of the assertions to the nTrace source code pane to see the related code. Recommended Coding Style The following coding styles are recommended for optimum transaction extraction results: • Only “assert” directive is supported.nTX User’s Guide and Tutorial Figure: Transaction Evaluator Form In the Transaction Evaluator form. the following sections contain a summary of recommended and unsupported coding styles.com EMail:cadserv21@hotmail.cadfamily.please inform us. This FSDB file will automatically be loaded into Verdi and you can start using all transaction viewing and analysis commands for debug in addition to the standard Verdi capability. you can select the assertions to be extracted and you can specify the results file name. the transactions will be extracted from the assertion code and saved to the specified file. Transaction signals have an _nTX suffix appended to the assertion name. SVA Code When it comes to adding SVA code to your design that will ultimately be used to extract transactions. you can display the assertions using a Table or Tree view. www.we will delete . NOTE: You will need to add the transaction waveforms using nWave’s Get Signals command.

cadfamily.please inform us. Example 2: sequence s1. logic [31:0] addr. do not declare local variables with the same name across different sequences/properties. @(posedge hclk) (`true. will be recorded as attributes of transactions. . .Transaction Extraction • • • Most SVA constructs are supported... endsequence should be modified as: sequence s1. Using constructs below the sequence layer is recommended for modeling the transaction. logic [31-1:0] data. Example 1: sequence single_read. endsequence SINGLE_READ: assert property(single_read). including those declared in the sub-sequence of a specific assertion. “data”. . addr = haddr) ##1 ((!hready && hsel). int localvar.if tort to your rights.ws = 0) ## 0 (hready) ##1 (!hready && hsel) [*0:$] ##1 ((hready && hsel && `SR_CTRL)..com 25 The document is for study only. int localvar1.com EMail:cadserv21@hotmail. data = hrdata).. SVA local variables... The local variables “addr”. www. endsequence sequence s2. int ws. therefore.we will delete . and “ws” variables of sequence “single_read” will be recognized as the attributes of assertion statement “SINGLE_READ”. ws = ws + 1) [*0:$] ##1 (hready. endsequence sequence s2. Refer to unsupported coding style for details. int localvar.

string label_nTX.. Then the sub-sequence/property’s “label_nTX” variable (if one exists) would be used as its transaction label..nTX User’s Guide and Tutorial int localvar2. label_nTX = “my_single_read”..... if you specify the following for a sequence/ property: sequence single_read.. and assigning a label name to it.. endsequence a_s1 : assert property((@posedge clk) s1 ##1 s2). www.. label_nTX = “my_s1”.. Unsupported Coding Style The following coding styles are not supported for transaction extraction: • • • • Multiple clocking is not supported Immediate assertion coding style is not supported.. If you specify the following for an assertion statement: sequence s1. label_nTX = “my_s2”. (. Only the “assert” directive is supported.. (. endsequence • You can specify the transaction label name of a specific sequence by declaring a string type local variable named “label_nTX”.please inform us. For example.cadfamily..... endsequence sequence s2.) . (... In this case.. the label would be either “my_s1” or “my_s2”....com EMail:cadserv21@hotmail.if tort to your rights.com 26 The document is for study only..... string label_nTX. SVA “cover” and “assume” directives are not supported. .. Three types of assertion successes will not be recognized as a transaction: • The vacuous SUCCESS of the implication will not be recognized as a transaction. string label_nTX..) .we will delete .. endsequence Then the transaction label name would be “my_single_read”.) .

ram_2kx32. Empty matches.DO (test. logic [10:0] Addr.EN (test.we will delete .ADDR).uSMI. .uFL_AMBA_SRAM. input RST. .com EMail:cadserv21@hotmail. .ram_2kx32. logic [31:0] Data. Addr = ADDR. input RDInvalid ).uFL_AMBA_SRAM. logic [31:0] Data.EN). input [31:0] DI.WE (test. Data = DI) ##1 (!(EN == 1'b1 && WE == 1'b1)).please inform us.ram_2kx32.DI (test. Code Example The following SVA code example: bind test assert_checker bind_transaction_evaluator( .mem. module assert_checker ( input EN. input WE. . output [31:0] DO.mem.” will not be recognized as a transaction.CLK (test. sequence core_memory_write.mem.ram_2kx32.ram_2kx32. Data = DO).uFL_AMBA_SRAM.uFL_AMBA_SRAM.WE).iXOEN_d) ).RST (test. . endsequence sequence core_memory_read.g.ram_2kx32.CLK).mem.uFL_AMBA_SRAM.DO). (1) ## 0 (EN == 1'b1 && WE == 1'b1.uFL_AMBA_SRAM.uFL_AMBA_SRAM. Addr = ADDR) ##1 (RDInvalid == 1'b0) ##1 (1.RDInvalid (test. .if tort to your rights.mem.ADDR (test.uFL_AMBA_SRAM. “seq1[*0].com 27 The document is for study only.Transaction Extraction • • The abort SUCCESS of 'disable iff' will not be recognized as a transaction.DI). input CLK. logic [10:0] Addr.cadfamily. (1) ## 0 (WE==1'b0 && RST==1'b0 && RDInvalid==1'b0. e.mem. input [10:0] ADDR.ram_2kx32.RST).mem. endsequence www. .

cadfamily. endmodule will be extracted and displayed as transaction waveforms similar to the following: Figure: Extracted Transaction Waveform www.nTX User’s Guide and Tutorial CORE_MEM_WRITE : assert property(@(posedge CLK) core_memory_write).please inform us. CORE_MEM_READ : assert property(@(posedge CLK) core_memory_read).we will delete .if tort to your rights.com 28 The document is for study only.com EMail:cadserv21@hotmail.

Transaction Extraction

Use nTE
nTE uses various transactors from SpiraTech to extract transactions from signal level simulation results. A source FSDB file containing signal activity, together with a bus configuration file (BCF), is loaded into the transactor using nTE. An FSDB file is produced containing a transaction hierarchy, together with the original signals. This may be viewed using nWave and the Transaction Analyzer window.

Pre-requisites
Pre-requisites include: • • The concept of models at different levels of abstraction, e.g. transactionlevel modeling. Familiarity with one of the supported bus protocols (see the relevant protocol specification), as listed below: • AMBA AHB • AMBA AHB-Lite • AMBA APB • AMBA AXI • MPEG2 Transport Stream • OCP-IP • PCI Express • UART • USB Refer to the appendices for more information on configuring nTE and interpreting the transaction hierarchy for each of the protocols. Installation of the nTE package.

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nTX User’s Guide and Tutorial

Installing nTE from the Internet
Complete the following steps to install nTE from the internet: 1. Create a directory for the software.
> mkdir <NTE_INST_DIR>

2. Change to the installation directory.
> cd <NTE_INST_DIR>

3. Connect to web http://www.novas.com. 4. Select Support-> Downloads and follow the instructions. In addition to the standard Verdi installation files, the following compressed file is available:
Novas-2006??-nte.tar.gz # nTE Package

where 2006 corresponds to the year, e.g. 2006 and ?? corresponds to the month, e.g. 04. When there is a patch release between quarterly releases, a p# will be appended to the version, e.g. 200604p1. 5. Decompress and extract the software:
> gzip -cd Novas-2006??-nte.tar.gz | tar xvf -

The following directories are created:
nte_examples adaptor_lib i686-linux-gcc-2.96 sparc-sol-gcc-2.95 Examples Transactor library files Linux binaries Solaris 2 binaries

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Transaction Extraction

Set Up the Environment
1. Specify the following environment variables:
> setenv CY_HOME "<path_to_nte_installation>" > setenv CY_PLATFORM "<platform>"

where platform is: • i686-linux for Linux (RedHat7, RedHat 9 and compatible) • sparc-sol for Solaris (Solaris 7, 8, and 9) 2. Add the nTE installation to the search path in your login script: For C (csh) shell: set path = ($CY_HOME/$CY_PLATFORM/bin $path) For Bourne (sh) and Korn (ksh) shells: PATH=$CY_HOME/$CY_PLATFORM/bin:$PATH 3. Add the Novas installation to the search path (which includes fsdbmerge) in your login script: For the C (csh) shell: set path = (<NOVAS_INST_DIR>/bin $path) For Bourne (sh) and Korn (ksh) shells: PATH=<NOVAS_INST_DIR>/bin:$PATH 4. Add the following to your LD_LIBRARY_PATH: > setenv LD_LIBRARY_PATH "$CY_HOME/$CY_PLATFORM/lib"

Use Model
To run nte, a command of the following format should be issued:
nte –input wires.fsdb –output transactions.fsdb \ –config config.bcf

Where: wires.fsdb is the output of the wire level simulation. transactions.fsdb is the desired output name (any existing file of the same name will be overwritten). • config.bcf contains a configuration to suit the transactor being used. Once the output FSDB has been generated by nte from the input FSDB and BCF configuration, the results can be viewed in nWave, which will display the original wire data and the recognized transactions. Refer to the Transaction chapter for more details. • •

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nTX User’s Guide and Tutorial

Bus Configuration File (BCF) Format
nTE makes use of the BCF (Bus Configuration File) Format for configuration. The BCF format supports C style single line (//), and multiple line (/* ... */) comments. The BCF features currently supported by nTE are defined in the following sections.

Bus Definition Block
The BCF file should contain one or more ‘bus definition blocks’, as follows.
<nte_transactor_library_name> <user_name> { }

‘nte_transactor_library_name’ selects which transactor to use, e.g. nte_UART_v2p1_ns. ‘user_name’ is a name for this bus definition block, which can consist of upper and lower case letters, numbers, and underscores (_). This name must be unique for each bus definition block within a single BCF file. Within the bus definition block nTE supports a number of statements and subblocks. For example:
nte_UART_v2p1_ns UARTtest { SIGMAP { // signal mappings... } PARAMETER { // bus parameters... } }

Multiple bus definition blocks can be used to extract transactions for multiple interfaces within the input FSDB file and combine the results into a single output FSDB file.
NOTE: nTE 1.3 or later is required to support multiple bus definition blocks.

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cadfamily. this can result in nTE not being able to fully interpret the protocol. For this reason a warning is written to the log file for each unmapped signal. For example: nte_UART_v2p1_ns UARTtest { MAPPING_ROOT = "/tbuart/tb". Clock Mapping A clock can either be user-defined by setting the clk_* parameters within the PARAMETER block of the BCF file.please inform us. . as follows: SIGMAP { <nte_transactor_signal_name> = "<user_signal_name>". <nte_transactor_signal_name> = "<user_signal_name>". See the appendix for the protocol you are interested in for a full listing of the signals in each of the nTE transactors. ‘user_signal_name’ is the name of a signal within the FSDB file that will be used as input to nTE.com EMail:cadserv21@hotmail. . SIGMAP { /UART/TX = "/tx". There can be any number of signal mappings within the signal mapping block. If you choose to map the clock. Mapping Root Statement The mapping root statement is defined within the bus definition block.Transaction Extraction Signal Mapping Block The signal mapping block is defined within the bus definition block. www. as follows: MAPPING_ROOT = "<root_user_signal_path>".com 33 The document is for study only. . ‘root_user_signal_path’ is prefixed to each of the ‘user_signal_names’ in the signal mapping block. Not every signal within the nTE transactor library has to be mapped. or a clock can be mapped so that the extraction process 'learns' the characteristics of the clock on a continuous basis.we will delete . However. } ‘nte_transactor_signal_name’ is the name of a signal defined within the nTE transactor library that has been selected for this bus definition block. unmapped signals will simply be left with a default value.if tort to your rights. then clk_* parameters do not need to be set within the PARAMETER block.

so it is included at the start of each of the user's signal names. /UART/RX = "/tbuart/tb/rx". For example: PARAMETER { UART_word_length = 8. www. } } NOTE: In this example. <value>.we will delete . . as this will result in a complete signal name like /tbuart/tb//tx which is incorrect. is equivalent to nte_UART_v2p1_ns UARTtest { SIGMAP { /UART/TX = "/tbuart/tb/tx". } = = <value>.if tort to your rights.cadfamily.nTX User’s Guide and Tutorial /UART/RX } } = "/rx". See the appendix for the protocol you are interested in for a full listing of what these are.please inform us. the root mapping does not have a separator (/) at the end of it. ‘value’ is the value to be assigned to that parameter. } There can be any number of parameter assignments within the bus parameter block.com 34 The document is for study only. UART_stop_bit_length = 1.com EMail:cadserv21@hotmail. Any parameters that are not assigned a value will take on a default value. ‘nte_transactor_parameter_name’ is the name of a parameter defined within the nTE transactor library that has been selected for this bus definition block. as follows: PARAMETER { <nte_transactor_parameter_name> <nte_transactor_parameter_name> .0. Bus Parameter Block The bus parameter block is defined within the bus definition block. . The separator should not be included in both places.

the following messages should be displayed once nTE is invoked: nTE complete for instance (INSTANCE_NAME) of protocol (PROTOCAL_NAME) nTE moving output file nTE complete If any settings are incorrect. Failed to connect to /RAM_bus/addr The following message indicates a wire is in BCF file but not in the adaptor.rd_data The following message indicates a parameter has been set outside the legal range: NTE_HALT: Fatal: Configured Addr bus width greater than maximum allowed. www.if tort to your rights.com EMail:cadserv21@hotmail.cadfamily.we will delete .Transaction Extraction nTE Results If all the settings are correct. Failed to relate /RAM_bus/rd_data with /RAM_bus_example/st/ iRAM_I/iRAM_I/rd_data The following messages indicate the configured bus width in the adaptor does not match the bus width in the input FSDB file: NTE_ERROR: Error: Aggregate value is the wrong length '"0000000000000000"' to an 8 bit field NTE_ERROR: Invalid aggregate passed to wire RAM_bus.please inform us.com 35 The document is for study only. This does not cause nTE to fail as you may not want to connect a signal. The following message indicates a wire is in adaptor but has not been connected to FSDB wire. the following warning or error messages may be displayed: nTE adaptor failed This would be followed by any of the next messages.

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Make a copy of these demo files in your working directory: % cp -r <NOVAS_INST_DIR>/demo <working_dir> www. 2. Create a working directory: % mkdir <working_dir> 4. You must also complete the following actions in order to set up the Novas environment and the files required for this tutorial: 1.Transaction Tutorials Transaction Tutorials The following topics are included: • • • • • Before You Begin View Transactions in nWave View Transactions in Transaction Analyzer Window Analyze Transactions Using TCL Generate an FSDB File with Transaction Information Before You Begin Before you begin the tutorials. Specify the search path to the license file: % setenv NOVAS_LICENSE_FILE <license_file> NOTE: Your license file must include an nTX feature line for this tutorial.please inform us. you (or your system manager) must have installed Verdi (which automatically installs nTX) as described in the accompanying Novas Installation and System Administration Guide. 3.com 37 The document is for study only.if tort to your rights.com EMail:cadserv21@hotmail. Add the Verdi application (binary) to the search path: % set path=(<NOVAS_INST_DIR>/bin $path) NOTE: The percent ('%') character on the left-hand side of the command represents the system prompt. All of the tutorial data resides in the <NOVAS_INST_DIR>/demo directory.we will delete .cadfamily.

cadfamily. cursor.fsdb & The nTrace and nWave windows open and the FSDB file is loaded. www. Execute Verdi to import the FSDB file: > verdi -ssf ahb32.bus. Change the directory to <working_dir>/demo/nTX. etc.if tort to your rights.) are available with FSDB files containing transactions. % cd <working_dir>/demo/nTX 2. Click on MyAHB_1 to show the streams under this hierarchy. NOTE: This tutorial only has an FSDB file that contains transactions and there isn’t a related design. nWave section in the Verdi User’s Guide and Tutorial document. for a complete introduction to nWave. Import FSDB File 1.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial View Transactions in nWave This tutorial will familiarize you with transaction viewing and search operations. Refer to the Tutorials chapter. The transaction FSDB is loaded displaying BusTop as the top hierarchy and MyAHB_1(_AHB_) as the first hierarchical level which is for different protocols. Add Transaction Waveforms 1.please inform us.com 38 The document is for study only.we will delete . All nWave manipulation functions (zoom. re-size. 2. In nWave. choose Signal -> Get Signals… to open the Get Signals form. marker.

www.cadfamily.com 39 The document is for study only.please inform us. Click Search Forward icon (blue right arrow) in toolbar to step through the transactions. re-size the signal and value panes to more readily display the text and zoom in on the waveform pane to see the transaction details. Click on the AhbTransaction stream in the signal pane to select it. Note. 10. Move the mouse cursor over the attributes in the value pane to show the details in a tip. 6. In nWave. Click on the Search By: in the nWave toolbar and choose the last option. 7. you can adjust the height by dragging the small grey line in the lower left corner of the stream name in the signal pane. 9. Since there are more attributes than the default signal height can display. In the Search Attribute Value form. Select AhbTransfer and AhbTransaction. the cursor moves to the begin time of each transaction. enter “BurstType” for Attribute and “incr 4” for Value.Displaying Streams 3.if tort to your rights. 8. 5. Transaction Attribute Values. 4.com EMail:cadserv21@hotmail.Transaction Tutorials The results will be similar to the following example: Figure: Get Signals . then click OK.we will delete .

The child transactions are highlighted in pink. Click OK.we will delete .if tort to your rights. 12.com EMail:cadserv21@hotmail.com 40 The document is for study only. www. Click on the transaction in the waveform pane at time 4810000ps. There will be 4 AhbTransfer burst read command transactions and 3 busy ones as the children of the selected transaction. 13. With the same transaction selected.nTX User’s Guide and Tutorial The form should look similar to the following: Figure: Search Attributes 11. Figure: Search Results with Related Transactions 14. click-right to open the right mouse button context menu and choose Properties to open the Transaction Property form which shows all the attributes and relationships for the selected transaction.please inform us. Click the Search Forward/Search Backward icons on the toolbar to locate a matching transaction at 4810000ps.cadfamily. which is burst read of “incr 4” type. The cursor in the waveform will automatically move to the nearest transaction with BurstType = incr 4.

choose Tools -> Transaction Analyzer -> Open Transaction Analyzer Window to open the Transaction Analyzer window.cadfamily. 2. Execute Verdi to import the FSDB file: > verdi -ssf ahb32. Import FSDB File 1.Transaction Tutorials View Transactions in Transaction Analyzer Window This tutorial will familiarize you with transaction viewing and search operations in a spreadsheet-like view.if tort to your rights.com 41 The document is for study only. Change the directory to <working_dir>/demo/nTX. NOTE: This tutorial only has an FSDB file that contains transactions and there isn’t a related design.please inform us. 1. % cd <working_dir>/demo/nTX 2. www.bus.we will delete .fsdb & The nTrace and nWave windows open and the FSDB file is loaded. you can view and manipulate the results in the Transaction Analyzer window. Add/Remove Transaction Streams After loading a FSDB file with transaction data. The FSDB file currently loaded in nWave will be the default in the Transaction Analyzer window. In nWave. In the Transaction Analyzer window. choose Stream -> Get Stream to open the Select Stream form.com EMail:cadserv21@hotmail.

com EMail:cadserv21@hotmail.we will delete . 3.nTX User’s Guide and Tutorial The form should look similar to the following: Figure: Select Stream Form All of the transaction streams available in the FSDB file will be listed in a tree-like format. 4. Double-click on AhbTransfer to automatically add the stream to the Transaction Analyzer window.com 42 The document is for study only.if tort to your rights. www.please inform us. Left-click to select AhbTransaction and click OK to add the stream and close the form. The stream name changes to gray and is appended with a red dot.cadfamily.

5.if tort to your rights. When streams are merged you can search and filter all the transaction attributes simultaneously.cadfamily. Note the stream has been removed from the Transaction Analyzer window.we will delete . Left-click to select the AhbTransaction. it does not effect the FSDB file. In the Transaction Analyzer window.com EMail:cadserv21@hotmail. Merge Transaction Streams You can also merge two or more streams in the Transaction Analyzer window. 6. Each stream has a tab of its own. AhbTransfer and AhbTransaction. The currently selected stream name is blue. in the Transaction Analyzer window. You can change the width of the columns by selecting the vertical line in the column header and dragging-left. www. 1. NOTE: The Merge Stream command only merges the transaction streams for viewing purposes. choose Stream -> Merge Stream to open the Merge Stream form. Choose Stream -> Close Stream. You can select the stream name to see the details of the stream.Transaction Tutorials The Transaction Analyzer window should look similar to the following: Figure: Transaction Analyzer Window with Streams Loaded There are two streams.com 43 The document is for study only.please inform us.

Click the Default button to automatically generated the merged stream name which will consist of each stream name linked with an underscore. Click the button to move all streams to the Merged Stream column. 5.we will delete . Click the button to move the selection back to the Stream Name column. 3. Click the UP button to move AhbTransaction above AhbTransfer. 6.cadfamily. www. Left-click to select the AhbTransaction stream in the Merged Stream column.please inform us. The stream name is changed to black and is selectable again.nTX User’s Guide and Tutorial The form will be similar to the following: Figure: Merge Stream Form All of the transaction streams available in the FSDB file will be listed in a tree-like format in the Stream Name column. 4. 7.com 44 The document is for study only.if tort to your rights. 2.com EMail:cadserv21@hotmail. Click OK. Left-click to select the Error stream in the Merged Stream column. After the stream is added. its name becomes gray with a red dot in the Stream Name column and can not be selected again. 8.

the cursor time would change in nTrace and nSchema as well. Choose View -> Sync Cursor Time to synchronize the cursor globally. Click-left anywhere on the row for Index 18 to set the cursor time. 2. The selected row is highlighted in yellow. 4. www. you’ll set the cursor/marker position in the Transaction Analyzer window and learn how to synchronize it with the other Verdi windows. If you had a design loaded and active annotation enabled.Transaction Tutorials The form will be similar to the following: Figure: Merged Stream in the Transaction Analyzer Window If the different streams have transactions at the same time. 5. Click-left anywhere on the row for Index 13 to set the cursor time. 3.if tort to your rights. both will be displayed.please inform us. Manipulate the Stream View There are several ways to manipulate the streams in the Transaction Analyzer window. 1. Click-middle anywhere on the row for Index 25 to set the marker time. Set the Cursor/Marker In this example.we will delete . Note the cursor time changes in nWave as well even without waveforms being displayed. Scroll until you can see Index 25.com 45 The document is for study only. The selected row is highlighted in red.com EMail:cadserv21@hotmail. select the AhbTransfer stream. In the Transaction Analyzer window. You can also filter the transactions based on one or two attribute conditions. 6.cadfamily. You can change which columns (attributes) are displayed and in what order.

Slave. In the Transaction Analyzer window.we will delete . select BurstType.if tort to your rights.please inform us. select Index. 1.com EMail:cadserv21@hotmail. www.nTX User’s Guide and Tutorial Change the Column (Attribute) Display In this example. select the AhbTransfer stream. Click the button to move it to the Hide Column section. 5. Only one attribute can be selected at a time. 4. all the columns (attributes) will be listed in the Show Column section.cadfamily. Click the DOWN button multiple times until Index is at the bottom of the list. 7. and EndTime individually. Choose View -> Column Configuration to open the Config Bus Table form. Select Label in the Show Column section. you’ll select some columns (attributes) to remove from the display and re-order the remaining columns. Repeat the previous steps for Response. 2. 6. 8. In the Show Column section. The form will be similar to the following: Figure: Config Bus Table Form By default. In the Show Column section. 3.com 46 The document is for study only.

select the AhbTransfer stream. The Transaction Analyzer window should be updated as follows: Figure: Modified Attribute Display for AhbTransfer Stream Note four columns have been removed from the display and the remaining columns have been re-ordered.if tort to your rights. you will search for a text string. Search the Transactions In this example. 10. Click the UP button multiple times until BurstType is located below Command. In the Pattern text field. 3. enter aa9. Click OK. The Index column is now the right-most column and BurstType is next to Command. The Find String form should be similar to the following: www.cadfamily. Choose View -> Find to open the Find String form. In the Transaction Analyzer window. 11.please inform us. 12.we will delete . 1. Choose View -> Show All and all columns (attributes) are added back to the view in the original order. Left-click on the Command column to sort by the command attribute types.com EMail:cadserv21@hotmail. 2.com 47 The document is for study only.Transaction Tutorials 9.

you will filter the transactions based on certain attributes. 3. The first occurrence of ‘aa9’ will be highlighted in blue in the Data column of the Transaction Analyzer window. In the first Criteria row.please inform us. 4. click Close on the Find String form. The form will be similar to the following: Figure: Filter Form . select the AhbTransfer stream. 5. There are multiple. Toggle the Column field and select Command.if tort to your rights. Filter the Transactions In this example.nTX User’s Guide and Tutorial Figure: Find String Form 4. 1. In the Transaction Analyzer window. click Next. 6. In the Find String form. Choose View -> Filter to open the Filter form. toggle the criteria to = and enter single write in the related text field.com EMail:cadserv21@hotmail. 2.we will delete .Command = single write www.com 48 The document is for study only.cadfamily. When you are done searching for different patterns. Continue to click the Next/Previous buttons to locate more occurrences of ‘aa9’.

7.we will delete . You can sort the current results by clicking another column header or you can further reduce the display by specifying another filter or you can restore the stream and start over.cadfamily.com EMail:cadserv21@hotmail.please inform us. In the Filter form (which should still be open unless you closed it). similar to the following: Figure: Filter Results for Command single write At this point you have several options. Click Apply. The form will be similar to the following: Figure: Filter Form . Let’s specify another filter.Transaction Tutorials 5.if tort to your rights.com 49 The document is for study only. toggle the Column field and select SizePerBeat. The Transaction Analyzer window will be updated to display transactions whose command attribute is of type single write. toggle the criteria to >= and enter 2 byte in the related text field. In the first Criteria row. 6.SizePerBeat >= 2byte www.

Generate Statistics In addition to viewing and manipulating the transactions in a spreadsheet-like view. www. In the Transaction Analyzer window.com 50 The document is for study only. Click Apply. you can filter the stream first and then generate statistics based on the reduced display.we will delete .cadfamily. Let’s restore the stream and start over. Choose View -> Show All and transaction rows are added back to the view in the original order.if tort to your rights. The Transaction Analyzer window will be updated to display transactions whose command attribute is of type single write and whose SizePerBeat attribute value is greater than or equal to 2 bytes. similar to the following: Figure: Filter Results for Command single write with SizePerBeat >= 2 bytes At this point you have several options. you can generate a variety of statistics for the stream. select the AhbTransaction_AhbTransfer merged stream. 9. Choose Tools -> Statistic Window to open the Perform Statistical Calculation form.please inform us. NOTE: Although this example will use the entire merged stream. 1.nTX User’s Guide and Tutorial 8. You can sort the current results by clicking another column header or you can further reduce the display by specifying another filter or you can restore the stream and start over. 2.com EMail:cadserv21@hotmail.

In this example you want to view the frequency of BurstType for the entire simulation range.com 51 The document is for study only.please inform us.if tort to your rights. 4. Click OK. 3. 5. www.cadfamily. Click the Full Range button to automatically enter the from and to times.we will delete .Transaction Tutorials The form will be similar to the following: Figure: Perform Statistical Calculation Form You have several options for setting up the form.com EMail:cadserv21@hotmail. Toggle the Category Column field and select BurstType.

we will delete . Figure: Bar Chart for BurstType For the stream combination. you can capture the results in PNG format.please inform us. At this point.com EMail:cadserv21@hotmail.if tort to your rights. In the Statistics Window. www. you can easily see the frequency of the burst types.com 52 The document is for study only.cadfamily. choose View -> Pie Chart. or duplicate the window.nTX User’s Guide and Tutorial A Statistics Window similar to the following will open. 6. You can also change the view to a pie chart or table.

com 53 The document is for study only.please inform us. Choose File -> Exit in nTrace to close the Verdi session. Choose File -> Close to close the Statistics Window. 8.cadfamily. www.com EMail:cadserv21@hotmail. Figure: Bar Chart for BurstType 7.if tort to your rights.Transaction Tutorials The window will be updated similar to the following.we will delete . You can generate more statistics for different attribute types.

Change the directory to <working_dir>/demo/nTX. query.tcl operates on a transactional FSDB. and statistic TCL commands in a TK program that can be launched from Verdi.cadfamily.tcl & The nTrace window opens with a new menu item.if tort to your rights. choose Tools -> Launch TA Example in nTrace. Execute Verdi to play the TCL file and load the FSDB file: > verdi -play ta_ex.. To launch the TA Example window as shown below." -tclCmd createMainWin -shortKey Y AddEventCallback [tk appname] cursorTimeChangedCB taCursorTimeChange 0 AddEventCallback [tk appname] markerTimeChangedCB taMarkerTimeChange 0 AddEventCallback [tk appname] tableRowSelectedCB stsTableRowSelected 0 www. Figure: TA Example Window This menu item was added as a result of the following code in the TCL file: # Append a Verdi menu item eMenuAppendItem -win $_nTrace1 -menuName Tools -itemName "Launch TA Example.. The FSDB used contains transactions of the AMBA AHB interface.please inform us.nTX User’s Guide and Tutorial Analyze Transactions Using TCL This tutorial demonstrates the usage of transaction manipulation. % cd <working_dir>/demo/nTX 2.com 54 The document is for study only. 3. Execute the TCL File The TCL script ta_ex. Both files can be found in the <working_dir>/demo/nTX directory.com EMail:cadserv21@hotmail. 1.we will delete .

This opens the ahbStat window. The AhbTransaction stream is added to the Transaction Analyzer window. In the TA Example window. Manipulate Transactions and View Statistics with TCL The transaction manipulation commands can be executed from the CommandTest menu of the TA Example window.com EMail:cadserv21@hotmail.if tort to your rights.we will delete .fsdb file loaded. In the TA Example window. Load File and Load a Stream should be executed before executing other commands. An information window is displayed when these commands are executed. 1.Transaction Tutorials AddEventCallback [tk appname] tableRowUnselectedCB stsTableRowUnselected 0 The Command 1-3 buttons are reserved for user-defined commands. the values will automatically be updated in the ahbStat window.please inform us.cadfamily. similar to the following example: Figure: ahbStat Window Note if you change the cursor or marker position in the Transaction Analyzer window. 4. Choose CommandTest -> Load a Stream. choose Statistics -> AHB Statistics. choose CommandTest -> Load File. 2. click-left on 7 in the Index column to set the cursor and click-middle on 23 to set the marker. The Transaction Analyzer window opens with the ahb32.bus.com 55 The document is for study only. In the Transaction Analyzer window. 3. www.

www. In the ahbStat window.nTX User’s Guide and Tutorial 5. In the ahbStat window. read bytes and write bytes.if tort to your rights. The results will be similar to the following: Figure: AHB Transaction Statistics 6.com EMail:cadserv21@hotmail.we will delete . Change the cursor or marker positions in the Transaction Analyzer window to select the first and last transaction and then click Update in the ahbStat window.please inform us. 7.cadfamily. click the Update button to update the number of transactions. click the Command Frequency (Bar Graph) or Burst Type Frequency (Pie Chart) buttons to display the frequency of AHB commands or burst type for the transactions within the current cursor/ marker time.com 56 The document is for study only.

For example. similar to the following: Figure: Highlighted Transactions www.please inform us. 8. you can click on bars to see their related transactions in the Transaction Analyzer window.we will delete .com 57 The document is for study only.Transaction Tutorials The results will be similar to the following: Figure: Bar Graph and Pie Chart The TCL script includes sample code for highlighting the related transactions for certain statistic items.if tort to your rights.cadfamily. In the Statistics Window for the Command Frequency. Note the statistic results are calculated based on the transactions within the cursor and marker time. The corresponding transactions will be highlighted in the Transaction Analyzer window.com EMail:cadserv21@hotmail. click the orange bar for SingleWrite. in the Command Frequency bar graph window.

file add command -label "Quit" -command "debExit" underline 0 $w configure -menu $w.fsdb" -underline 0 $w.staTest -label "Statistics" -underline 0 # File menu menu $w..menuBar.please inform us...menuBar.menuBar.menuBar add cascade -menu $w." command "createTA" -underline 0 $w.menuBar.menuBar.if tort to your rights.nTX User’s Guide and Tutorial Example TCL Script #!/bin/sh # the next line restarts using wish \ exec wish "$0" "$@" # Global variables set cursorTime 0 set markerTime 0 set cursorIdx 0 set markerIdx 0 set numTrans 0 set numRByte 0 set numWByte 0 # Statistics table set cmdTbl 0 # Related transaction list (command frequency) set trListSR {} set trListSW {} set trListBR {} set trListBW {} proc createMainWin {} { global cursorTime set w .menuBar add cascade -menu $w.menuBar.menuBar.cmdTest -label "CommmandTest" -underline 0 $w.com EMail:cadserv21@hotmail.we will delete .file -label "File" underline 0 $w.menuBar.menuBar # Command Test menu menu $w.menuBar.file -tearoff 0 $w.menuBar." -command "createWV" -underline 0 $w.menuBar -tearoff 0 $w.bus.cmdTest add command -label "Load a Stream" -command "taAddStream -stream MyAHB_1/AhbTransaction" -underline 0 $w.cmdTest -tearoff 0 $w.com 58 The document is for study only..menuBar.file add command -label "nWave.cmdTest add command -label "Config Columns" -command "taConfigureColumn {Idx BeginTime EndTime Command StartAddress Master Slave}" -underline 0 www.template catch {destroy $w} toplevel $w wm title $w "TA Example" # TA example menu bar menu $w.menuBar add cascade -menu $w.file add command -label "TransactionAnalyzer.cadfamily.cmdTest add command -label "Load File" -command "loadFile ahb32.

menuBar.menuBar.cmdTest add command -label "Close File" -command "taCloseFile" -underline 0 # Statistics menu menu $w.cmd2 -text "Command 2" -command {onCommand Command2} button $w.cmdTest add command -label "Set 100th Transaction as Active" -command "taSetActiveTransaction -trans 100" -underline 0 $w.if tort to your rights.debFrame.menuBar.cmd2 -fill $w.cmdTest add command -label "Sort by address" -command "taSort -orderBy StartAddress" -underline 0 $w.cmd3 -text "Command 3" -command {onCommand Command3} pack pack pack pack pack } $w.cursorTime.cmdTest add command -label "Set Marker to 14110000" command "taSetMarker -time 14110000" -underline 0 $w.we will delete .debFrame.cmdTest add command -label "Set Radix of \"StartAddress\" to Decimal" -command "taSetRadix -column StartAddress -format Dec" -underline 0 $w.cmdTest add command -label "Filter to Single Read" command "taFilter {Command = single read}" -underline 0 $w.cmdTest add command -label "Show All Transactions" command "taShowAll -stream MyAHB_1/AhbTransaction" -underline 0 $w.debFrame -fill both -fill x x -pady x -pady x -pady -pady 2 2 2 2 # Create transaction analyzer window proc createTA {} { set ta_win [taCreateWindow] } www.menuBar.cursorName -side left pack $w.menuBar.cmdTest add command -label "Delete Stream" -command "taDeleteStream -stream MyAHB_1/AhbTransaction" -underline 0 $w.please inform us.debFrame.menuBar.cursorTime $w.debFrame.menuBar.debFrame.menuBar.com 59 The document is for study only.debFrame.menuBar.debFrame.cursorTime.menuBar.cmd1 -fill $w.debFrame.cursorTime.cmdTest add command -label "Set Cursor to 760000" command "taSetCursor -time 760000" -underline 0 $w.cursorName -text "Cursor Time: " label $w.cursorTime.cmd1 -text "Command 1" -command {onCommand Command1} button $w.debFrame.cursorVal -width 20 -relief sunken -anchor w -textvar cursorTime pack $w.cursorVal button $w.menuBar.debFrame.menuBar.cmdTest add command -label "Jump To Marker" -command "taJumpToMarker" -underline 0 $w.cmd3 -fill $w.debFrame.debFrame.cmdTest add command -label "Jump To Cursor" -command "taJumpToCursor" -underline 0 $w.cadfamily.Transaction Tutorials $w.menuBar.debFrame -borderwidth 10 frame $w.cmdTest add command -label "Find Text (incr)" command "taFind incr" -underline 0 $w.menuBar.com EMail:cadserv21@hotmail.cursorTime label $w.staTest -tearoff 0 $w.staTest add command -label "AHB Statistics" -command "showAhbStat" -underline 0 # Frame for Verdi commands frame $w.

we will delete .ahbStat] { toplevel .com EMail:cadserv21@hotmail.ahbStat -border 5 frame .update -text "Update" \ -default active -command "updateAHBStat" www.ahbStat.buttons pack .please inform us.ahbStat.buttons.com 60 The document is for study only.if tort to your rights.buttons -side bottom -fill x button .nTX User’s Guide and Tutorial # Create waveform window proc createWV {} { set wv_win [wvCreateWindow] } proc onCommand btn { tk_dialog .cadfamily." info 0 OK } # Cursor Time change callback proc cursorTimeChangedCB args { global cursorTime set cursorTime [lindex $args [expr [lsearch $args "-time"]+ 1]] } # Marker Time change callback proc markerTimeChangedCB args { global markerTime set markerTime [lindex $args [expr [lsearch $args "-time"]+ 1]] } # Table row selected callback proc tableRowSelectedCB args { global cmdTbl global trListSR trListSW trListBR trListBW set tbl [lindex $args [expr [lsearch $args "-table"] + 1]] if {$tbl == $cmdTbl} { switch [lindex $args [expr [lsearch $args "-rowIdx"] + 1]] { 0 {taHighlightTransactions -transList $trListSR -color cyan} 1 {taHighlightTransactions -transList $trListSW -color cyan} 2 {taHighlightTransactions -transList $trListBR -color cyan} 3 {taHighlightTransactions -transList $trListBW -color cyan} } } } # Marker Time change callback proc tableRowUnselectedCB args { taClearAllHighlightTransactions } # Load a file proc loadFile args { if {[taGetCurrentWindow] == "0"} { taCreateWindow } taOpenFile -file $args } # AHB statistic dialog proc showAhbStat {} { global cursorTime markerTime if ![winfo exists .ahbStat.dialog1 "Info" "Button $btn pressed.

f2.info.ahbStat.info.info.value .name -side left pack .f5.info.ahbStat.$i -side top -fill x -pady 2 label .name config -text "Number of read bytes:" .value -relief sunken -width 40 pack .ahbStat.ahbStat.$i -bd 2 pack .info.info pack .name config -text "Number of transactions:" .value .info.name config -text "Cursor time:" .ahbStat.$i.info.if tort to your rights.cmdChart -text "Command Frequency (Bar Graph)" -command "showCmdChart" pack .$i.info.cmdChart -side bottom -fill x -pady 2 } } # Display bar chart of AHB command distribution proc showCmdChart {} { global cursorTime markerTime cmdTbl global trListSR trListSW trListBR trListBW set set set set set set set set trListSR trListSW trListBR trListBW cntSR cntSW cntBR cntBW {} {} {} {} 0 0 0 0 if {[checkAhbStream] == 0} { return 0.btChart -side bottom -fill x button .info.ahbStat.update -side left -expand 1 -pady 2 button .f5.we will delete .buttons.ahbStat.info.info.value -side right } .value .ahbStat.info -expand yes -fill both -padx 1 -pady 2 foreach i {f1 f2 f3 f4 f5} { frame .close -side left -expand 1 -pady 2 frame .info.com EMail:cadserv21@hotmail.cadfamily.ahbStat.btChart -text "Burst Type Frequency (Pie Chart)" -command "showBurstChart" pack .$i.close -text Close \ -default active -command "destroy .info.com 61 The document is for study only.ahbStat.name config -text "Number of write bytes:" .info.please inform us.ahbStat.value .ahbStat.f1.info. } www.ahbStat.info.f4. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0.value config config config config config -anchor -anchor -anchor -anchor -anchor w w w w w -textvar -textvar -textvar -textvar -textvar cursorTime markerTime numTrans numRByte numWByte # Charts button .f3.ahbStat.f3.ahbStat.ahbStat.ahbStat" pack .$i.name label .ahbStat.name config -text "Marker time:" .f2.ahbStat.buttons.info.ahbStat.ahbStat.ahbStat.ahbStat.f1.ahbStat.buttons.info.f4.ahbStat.info.info.ahbStat.Transaction Tutorials pack .

lappend trListSR $idx.please inform us. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0.} "burst write" {incr cntBW.} "burst read" {incr cntBR. } foreach idx $transList { set bt [lindex [taGetAttributeValue -trans $idx -attr "BurstType"] 1] switch $bt { "single" {incr cntSingle} "incr" {incr cntIncr} "wrap 4" {incr cntWrap4} "incr 4" {incr cntIncr4} "wrap 8" {incr cntWrap8} "incr 8" {incr cntIncr8} "wrap 16" {incr cntWrap16} "incr 16" {incr cntIncr4} } } set btTbl [taCreateTable -name "Burst Type Fequency" -cols {Command Count}] taAddRow -table $btTbl -valueList "SINGLE $cntSingle" taAddRow -table $btTbl -valueList "INCR $cntIncr" taAddRow -table $btTbl -valueList "WRAP4 $cntWrap4" taAddRow -table $btTbl -valueList "INCR4 $cntIncr4" taAddRow -table $btTbl -valueList "WRAP8 $cntWrap8" www.cadfamily. lappend trListBR $idx. lappend trListBW $idx.} } } set cmdTbl [taCreateTable -name "Command Frequency" -cols {Command Count}] taAddRow -table $cmdTbl -valueList "SingleRead $cntSR" taAddRow -table $cmdTbl -valueList "SingleWrite $cntSW" taAddRow -table $cmdTbl -valueList "BurstRead $cntBR" taAddRow -table $cmdTbl -valueList "BurstWrite $cntBW" taCreateView -view BarGraph -table $cmdTbl } # Display pie chart of AHB burst type distribution proc showBurstChart {} { global cursorTime markerTime set cntSingle 0 set cntIncr 0 set cntWrap4 0 set cntIncr4 0 set cntWrap8 0 set cntIncr8 0 set cntWrap16 0 set cntIncr16 0 if {[checkAhbStream] == 0} { return 0.com 62 The document is for study only. lappend trListSW $idx.we will delete .} "single write" {incr cntSW.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial foreach idx $transList { set cmd [lindex [taGetAttributeValue -trans $idx -attr "Command"] 1] switch $cmd { "single read" {incr cntSR.if tort to your rights.

please inform us.. } # Update numTrans set numTrans [llength $transList] # Update numRByte and numWByte set numRByte 0 set numWByte 0 foreach idx $transList { set cmd [lindex [taGetAttributeValue -trans $idx -attr "Command"] 1] set beatCnt [lindex [taGetAttributeValue -trans $idx -attr "BeatCount"] 1] set sizePerBeat [lindex [taGetAttributeValue -trans $idx attr "SizePerBeat"] 1] set byteCnt [expr [lindex $sizePerBeat 0] * [lindex $beatCnt 1]] if {[string match *read $cmd]} { set numRByte [expr $numRByte + $byteCnt].dialog1 "Warning" "AHB stream not loaded!" info 0 OK return 0.Transaction Tutorials taAddRow -table $btTbl -valueList "INCR8 $cntIncr8" taAddRow -table $btTbl -valueList "WRAP16 $cntWrap16" taAddRow -table $btTbl -valueList "INCR16 $cntIncr16" taCreateView -view PieChart -table $btTbl } # Update AHB statistics proc updateAHBStat {} { global cursorTime markerTime numTrans numRByte numWByte if {[checkAhbStream] == 0} { return 0. } elseif {[string match *write $cmd]} { set numWByte [expr $numWByte + $byteCnt].we will delete .cadfamily.com EMail:cadserv21@hotmail. } return 1.com 63 The document is for study only. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0. proc checkAhbStream {} { if {[taSelectStream -stream MyAHB_1/AhbTransaction] == 0} { tk_dialog .if tort to your rights.." -tclCmd createMainWin -shortKey Y AddEventCallback [tk appname] cursorTimeChangedCB taCursorTimeChange 0 AddEventCallback [tk appname] markerTimeChangedCB taMarkerTimeChange 0 AddEventCallback [tk appname] tableRowSelectedCB stsTableRowSelected 0 AddEventCallback [tk appname] tableRowUnselectedCB stsTableRowUnselected 0 www. } # Append a Verdi menu item eMenuAppendItem -win $_nTrace1 -menuName Tools -itemName "Launch TA Example. } } } # Check if AHB transaction is loaded.

1. 2. If you are already familiar with this procedure. If you are already familiar with this type of information. The following new tasks are provided to dump transactions along with normal HDL signals to a single FSDB file during simulation: $fsdb_tr_file $fsdb_tr_stream $fsdb_tr_attribute $fsdb_tr_begin $fsdb_tr_data $fsdb_tr_abort $fsdb_tr_end $fsdb_tr_close This section includes the following topics: • PLI Background • Procedures for Writing a PLI Routine • Steps for Writing FSDB • Steps to Dump Transactions to FSDB • C Files for FSDB Writer API • Use Provided C Files for PCI Transaction Dumping The first several sections provide background detail for creating PLI routines and using the FSDB writer API. you can skip to the next section.com 64 The document is for study only.opencores. PLI Background The following summarizes the typical process for adding new PLI functions to your simulator environment. Use the veriuser. Write C functions that have PLI routines (see following section for details).cadfamily.please inform us.if tort to your rights. www.org.nTX User’s Guide and Tutorial Generate an FSDB File with Transaction Information A "simple" simulation-time transaction recognizer for the PCI bus protocol has been created using an open source code design called “PCI Bridge IP Core” from www. you can skip to the last section for the example.c to associate the C function with the simulator system task.we will delete .com EMail:cadserv21@hotmail.

www. extern int plicompile_tr_stream(). 4. extern int plicompile_tr_scope(). you can skip to the next section. You should refer to the simulator user guide to understand how this is done.we will delete .if tort to your rights.cadfamily.Transaction Tutorials 3. Procedures for Writing a PLI Routine The following summarizes the typical process for writing a new PLI routine (corresponds to #1 above). extern int plitask_tr_file(). extern int plimisc_tr_file(). int my_calltf().h> #include <vxl_veriuser. Specify the function prototype and variable declaration.c containing the main PLI/C program must have the following lines: #include <veriuser.h> 2. pass the C/C++ function details to the simulator during the compile process of Verilog code. extern int plicompile_tr_file(). Some simulators.com 65 The document is for study only. If you are already familiar with this procedure. 1. Once linked.com EMail:cadserv21@hotmail. The file veriuser. In the present case. when the simulator encounters the user defined system tasks (those starting with $).so in UNIX). it will be as shown below. Compile veriuser. extern int plitask_tr_stream().DLL in Windows and *.c and C functions dynamically to generate shared lib (*. extern int plimisc_tr_scope(). if the functions are in separate files. my_checktf(). 6. Include the header files. they should be declared as external functions. (This is called linking. This part of the program contains all the local variables and the functions that it invokes as part of the system call. such as. Based on the simulator. NCSIM also allows dynamic linking.) 5. extern int plitask_tr_scope(). However. During execution of the Verilog code by the simulator. run the simulator like any normal Verilog simulation. as explained in the next step.please inform us. the execution control is passed to the PLI routine (C/C++ function).

These are the variables through which the simulator communicates with the C code. 3. static s_tfcell deb_veriusertfs[] = #else s_tfcell veriusertfs[] = #endif { { usertask. extern int plicompile_tr_data().nTX User’s Guide and Tutorial extern int plimisc_tr_stream(). /* calltf routine */ plimisc_tr_file. extern int plitask_tr_abort(). extern int plicompile_tr_abort().com 66 The document is for study only.please inform us.we will delete . /* user_data value */ plicompile_tr_file.com EMail:cadserv21@hotmail. extern int plimisc_tr_data(). extern int plimisc_tr_end(). /* sizetf routine */ plitask_tr_file. There are a number of data structures that must be defined in a PLI program.cadfamily.if tort to your rights. Create the essential data structure. extern int plitask_tr_attribute(). extern int plicompile_tr_end(). extern int plitask_tr_close(). The simulator looks at this table and figures out which properties the system call corresponding to this PLI routine would be associated with. extern int plicompile_tr_close(). extern int plitask_tr_begin(). extern int plimisc_tr_close(). /* checktf routine */ 0. extern int plicompile_tr_begin(). extern int plimisc_tr_begin(). /* misctf routine */ www. extern int plicompile_tr_attribute(). /* type of PLI routine */ 0. extern int plitask_tr_end(). extern int plitask_tr_data(). Veriusertfs[]: the main interaction between the C code that one writes and the Verilog simulator is done through a table. extern int plimisc_tr_abort(). extern int plimisc_tr_attribute().

0. "$fsdb_tr_attribute". 0. { usertask. { usertask. plitask_tr_begin. { usertask. { usertask. plicompile_tr_stream. plimisc_tr_attribute. plicompile_tr_data. /* system task/function name www.if tort to your rights. { usertask. */ 1/* forward reference = true */ }.please inform us. 0. "$fsdb_tr_scope". 1 }. plitask_tr_scope.com EMail:cadserv21@hotmail.com 67 The document is for study only. plicompile_tr_begin. 0.we will delete . plicompile_tr_attribute. plitask_tr_stream. 0. 0.Transaction Tutorials "$fsdb_tr_file". "$fsdb_tr_stream". 1 }. plitask_tr_attribute. plicompile_tr_scope. 0. "$fsdb_tr_begin". 1 }. plimisc_tr_begin. 1 }. 0. plimisc_tr_scope.cadfamily. plimisc_tr_stream. 0. 0.

nTX User’s Guide and Tutorial plitask_tr_data, plimisc_tr_data, "$fsdb_tr_data", 1 }, { usertask, 0, plicompile_tr_abort, 0, plitask_tr_abort, plimisc_tr_abort, "$fsdb_tr_abort", 1 }, { usertask, 0, plicompile_tr_end, 0, plitask_tr_end, plimisc_tr_end, "$fsdb_tr_end", 1 }, { usertask, 0, plicompile_tr_close, 0, plitask_tr_close, plimisc_tr_close, "$fsdb_tr_close", 1 }, {0} /*** final entry must be 0 ***/ };

4. Include the appropriate tf routines. a. checktf routine • Optional. • Simulator checks the routine once right before simulation. b. calltf routine • Perform the task or function. c. sizetf • Returns the size.

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Transaction Tutorials

• Has to be a userfunction or userRealfunction routine. • Default returns 32-bit values. d. misctf • Routine called depending upon reasons e.g. reason_endofcompile, reason_paramvc, etc.

Steps for Writing FSDB
The following summarizes the typical process for writing an FSDB file. If you are already familiar with this procedure, you can skip to the next section. 1. Open an FSDB. An FSDB is opened by the ffw_Open API, which asks the application to give the file name and file type. The file type tells the source of the information, and is defined as fsdbFileType in fsdbShr.h header file. Once the file is opened successfully, the application can get a pointer to the FSDB writer object, which is a must parameter for most FSDB Writer APIs. 2. Set scale unit and other information. If the simulation does have a scale unit, then the application must set it. If it does not, then the default value is 1ns. Other information such as simulation date and simulator version are optional and for reference only. 3. Choose the tree creation scheme. The tree creation scheme is chosen by calling the ffw_CreateTreeByIdcodeScheme or ffw_CreateTreeByHandleScheme APIs. The default is idcode scheme if nothing is called. 4. Initialize data type creation (if necessary). If there is user defined data type, then the application must call the data type creation API to notify the FSDB writer, so that it can initialize the necessary data structures to store the data type definition. This can be done by calling the ffw_GetDataTypeCreationReady API. For most cases, there aren’t user defined data types; therefore, by default, the FSDB writer assumes there are no user defined data types. 5. Create the design hierarchy. The design hierarchy is composed by calling tree creation APIs. The ffw_BeginTree API creates a top scope, which has no name. The ffw_CreateScope API creates a scope, which is a child of “the current scope,” and then moves “the current scope” down to the newly created one. The ffw_CreateUpscope moves “the current scope” up to its parent scope.

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nTX User’s Guide and Tutorial

The ffw_CreateVarByIdcode or ffw_CreateVarByHandle APIs create a variable, which belongs to “the current scope.” The ffw_EndTree API completes the design hierarchy. Note that an FSDB file may contain none, one, or multiple design hierarchies. 6. Create the value changes. Conceptually, a value change is composed of a pair: a time and a value. The time is created by calling ffw_CreateXCoorByHnL, while the value is created by calling the ffw_CreateVarValueByIdcode or ffw_CreateVarValueByHandle APIs. 7. Close the FSDB. An FSDB is closed by calling the ffw_Close API, which flushes the necessary in-core data and temporary files to the FSDB file. Then it performs some clean up tasks and completes the FSDB file.

Steps to Dump Transactions to FSDB
The following summarizes the typical process for dumping transactions to an FSDB file. If you are already familiar with this procedure, you can skip to the next section. 1. Create transaction file name in the FSDB file using $fsdb_tr_file. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_file} {"FILE_ID"} (in Verilog code) $fsdb_tr_file("FILE_ID"); Example:
ncsim> call {$fsdb_tr_file} {"pci_tr.fsdb"}

2. Create a transaction stream name in the FSDB file using $fsdb_tr_stream. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_stream} {"STREAM_ID"} (in Verilog code) $fsdb_tr_stream("STREAM_ID"); Examples:
ncsim> ncsim> ncsim> ncsim> call call call call {$fsdb_tr_stream} {$fsdb_tr_stream} {$fsdb_tr_stream} {$fsdb_tr_stream} {"CON_RD"} {"CON_WR"} {"IO_RD"} {"IO_WR"}

3. Create a transaction attribute name in the FSDB file using $fsdb_tr_attribute.

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Transaction Tutorials

Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_attribute} {"ATTRIBUTE_ID"} (in Verilog code) $fsdb_tr_attribute("ATTRIBUTE_ID"); Examples:
ncsim> call {$fsdb_tr_attribute} {"addr"} ncsim> call {$fsdb_tr_attribute} {"data"}

4. Create a transaction hierarchical scope name in the FSDB file using $fsdb_tr_scope. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_scope} {"Top.level1.leve2.level3...."} (in Verilog) code $fsdb_tr_scope("Top.level1.level2.level3....."); Example:
ncsim> call {$fsdb_tr_scope} {"SYSTEM.monitor32"}

5. Begin a transaction in the FSDB file (for this PCI transaction address phase) using $fsdb_tr_begin. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_begin} {"TRANS_ID",address_attribute} (in Verilog code) $fsdb_tr_begin("TRANS_ID", address_attribute); Example:
$fsdb_tr_begin("IO_READ",ad_prev[PCI_BUS_DATA_RANGE:0]);

6. Begin a data transaction in the FSDB file (for this PCI transaction data phase) using $fsdb_tr_data. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_data} {data_attribute} (in Verilog code) $fsdb_tr_data(data_attribute); Example:
$fsdb_tr_data("PCI_DATA",pci_ext_ad[PCI_BUS_DATA_RANGE:0]);

7. Abort any previous transaction in the FSDB file (for this PCI transaction abort phase) using $fsdb_tr_abort. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_abort}

www.cadfamily.com EMail:cadserv21@hotmail.com 71 The document is for study only,if tort to your rights,please inform us,we will delete

we will delete .c fsdb_tr_data. fsdb_tr_attribute. 8.nTX User’s Guide and Tutorial (in Verilog code) $fsdb_tr_abort. Syntax: (in ncsim. Close a transaction in the FSDB file using $fsdb_tr_close.c Abort transaction. End any transaction in the FSDB file (for this PCI transaction end phase) using $fsdb_tr_end.c Begin address transaction and create value change. Begin data transaction and create value change.c fsdb_tr_file. Example: $fsdb_tr_abort. C File Name Function fsdb_tr_abort. Example: $fsdb_tr_close. Create transaction file name www.if tort to your rights. Syntax: (in ncsim. End transaction.com 72 The document is for study only.rc) ncsim> call {$fsdb_tr_end} (in Verilog code) $fsdb_tr_end. C Files for FSDB Writer API The following table summarizes the C files that were created for the corresponding FSDB writer API. Close the FSDB file.c fsdb_tr_end.com EMail:cadserv21@hotmail. fsdb_tr_begin.please inform us. These are provided in the <NOVAS_INST_DIR>/share/PLI/nTX_ex directory. 9.rc) ncsim> call {$fsdb_tr_close} (in Verilog code) $fsdb_tr_close.c fsdb_tr_close. Example: $fsdb_tr_end.c Create transaction attribute name.cadfamily.

c fsdb_tr_stream.cadfamily.if tort to your rights.com EMail:cadserv21@hotmail.c Get transaction hierarchical scope name from user to create the FSDB signal tree. ncelab and ncsim on the PCI design with FSDB dumping.v file). % cd <working_dir>/pci/bench/verilog % mv pci_bus_monitor. 3.Transaction Tutorials fsdb_tr_scope.orig % cp <NOVAS_INST_DIR>/share/PLI/nTX_ex/bench/verilog/ pci_bus_monitor. 4.v. pci should be the main directory with several sub-directories. The following steps are based on the NCSIM simulator. Download the design and related documentation from the following link: http://www. Create transaction stream name in FSDB. 5.com 73 The document is for study only. Use Provided C Files for PCI Transaction Dumping The following steps summarize how to use the provided C files to dump the open source “PCI Bridge IP Core” transactions to the FSDB file. Unzip and untar the downloaded file and install in your working directory. 1. Generate the libpli.so and pli. 1. The file included in the download package need to be replaced with this new version.org/pdownloads. The C files that are provided by Novas can be found in the <NOVAS_INST_DIR>/share/PLI/nTX_ex/link directory. Run ncvlog.a for PLI linking. please modify the make file appropriately. % mkdir <working_dir> 2. Copy these files locally. Now everything should be set up to run the example and generate an FSDB file with transaction information. % cd <working_dir>/pci/nTX_ex/link % make 2.we will delete .v . The new system tasks have been inserted into a new version of the module pci_bus_monitor (<install>/bench/verilog/pci_bus_monitor. www.opencores.v pci_bus_monitor.cgi/list/pci?no_loop=yes You should select All. % cd <working_dir>/pci % cp <NOVAS_INST_DIR>/share/PLI/nTX_ex/link . Create a working directory.please inform us. If you use a different simulator.

please inform us. view and manipulate the transactions.cadfamily.com EMail:cadserv21@hotmail. www.com 74 The document is for study only.we will delete .nTX User’s Guide and Tutorial % cd <working_dir>/pci/sim/rtl_sim/run % make Once the FSDB file is created.if tort to your rights. you can use the steps in the previous tutorial to load.

This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.com 75 The document is for study only. Sequential and non-sequential single transfers.please inform us.we will delete . Name The bus declaration (nte_AMBA_AHB_v2p8_2x16_32_ns) must be one of the supported transactors. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. nte_AMBA_AHB_v2p8_2x16_32_ns MyAHB_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.if tort to your rights.Appendix A: AMBA AHB Transactor Appendix A: AMBA AHB Transactor Overview The AMBA-AHB Transactor supports the following features: • • • • Data bus width from 8-bits to 1024-bits.cadfamily. www. Split transactions.com EMail:cadserv21@hotmail. MAPPING_ROOT = "/AHB_2x2_system/test_AHB". IDLE and BUSY transfer types.

however.com 76 The document is for study only. The transactor signals are pre-defined as shown in the file below and must not be changed. // signals from each slave /ahb_core/HSPLIT_0[0] ="/V_AHB_or_gate_S[0]/HSPLIT[0]". // signals from each master /ahb_core/HBUSREQ[0] ="/V_AHB_core/HBUSREQ[0]". /ahb_core/HSIZE ="/V_AHB_core/HSIZE". The SIGMAP code example is for an unmapped clock. // signals from arbiter /ahb_core/HGRANT[0] ="/V_AHB_core/HGRANT[0]". /ahb_core/HSPLIT_1[0] ="/V_AHB_or_gate_S[1]/HSPLIT[0]". } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file: www.please inform us. /ahb_core/HWDATA ="/V_AHB_core/HWDATA". /ahb_core/HPROT ="/V_AHB_core/HPROT". NOTE: Clock can be mapped to /ahb_core/HCLK. /ahb_core/HBUSREQ[1] ="/V_AHB_core/HBUSREQ[1]".if tort to your rights.we will delete . // signals from slave MUX (read data and response) // all of these are inputs to each master /ahb_core/HREADY ="/V_AHB_core/HREADY".com EMail:cadserv21@hotmail. /ahb_core/HRDATA ="/V_AHB_core/HRDATA". For example you can leave the HSPLIT signal unconnected for slaves that do not support the split feature. /ahb_core/HGRANT[1] ="/V_AHB_core/HGRANT[1]". If this is done they will be assigned a default value (normally 0). /ahb_core/HWRITE ="/V_AHB_core/HWRITE". /ahb_core/HMASTLOCK ="/V_AHB_core/HMASTLOCK". /ahb_core/HSPLIT_1[1] ="/V_AHB_or_gate_S[1]/HSPLIT[1]". /ahb_core/HSPLIT_0[1] ="/V_AHB_or_gate_S[0]/HSPLIT[1]". /ahb_core/HADDR ="/V_AHB_core/HADDR". /ahb_core/HRESP ="/V_AHB_core/HRESP". /ahb_core/HBURST ="/V_AHB_core/HBURST". control and // write data MUX) // all of these are inputs to each slave /ahb_core/HTRANS ="/V_AHB_core/HTRANS". SIGMAP { // signals from master MUX (address. /ahb_core/HMASTER ="/V_AHB_core/HMASTER". it is possible to leave signals unconnected by removing them from the sigmap section. /ahb_core/HLOCK[1] ="/V_AHB_core/HLOCK[1]".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. /ahb_core/HLOCK[0] ="/V_AHB_core/HLOCK[0]".cadfamily.

• warn_after_n_ready_low_cycles: A warning will be issued when the ready signal from selected slave has remained low for ‘n’ clock cycles after it was selected. An example is shown below: • • • Figure: Clock Setup // parameters PARAMETER { clk_init_value = 0. www. //ns clk_2nd_time = 5 ns. The clock set up is important for the correct operation of the transactor. • hold_time: The hold time for all AHB signals. //ns warn_after_n_ready_low_cycles = 100. • setup_time: The setup time for all AHB signals. //ns setup_time = 2 ns.we will delete .please inform us. where ‘n’ is equal to the number set for the parameter. //initial value of clock clk_phase_shift = 0 ns. • clk_2nd_time: The relative time of second clock change after the previous change.com 77 The document is for study only. allow_no_bus_transfers = true. clk_phase_shift: The time of the first transition from the initial value. //ns clk_1st_time = 5 ns.cadfamily. //ns hold_time = 1 ns.Appendix A: AMBA AHB Transactor clk_init_value: The initial value of the clock (0 or 1).if tort to your rights. • allow_no_bus_transfers: Recognize AHB_no_bus_transfer transactions when set to the default state of true. If the clock is mapped then clk_* parameters do not need to be set. } NOTE: PARAMETER code example is for an unmapped clock.com EMail:cadserv21@hotmail. clk_1st_time: The relative time of the first clock change after the initial phase shift change.

‘ns’. This does not have to match the time scale of the input FSDB file. types and attributes of these transactions are described in detail. ‘128’. e.cadfamily. ‘256’) ‘tu’ – time unit (‘ps’. represents the output of the SPLIT signals from AHB slaves. however. ‘64’.we will delete .nTX User’s Guide and Tutorial Transactor Configurations A number of transactor configurations are available. ‘32’. the width of the read and write data busses (‘16’. any signal changes below this time resolution will not be seen by nTE. The naming convention used is nte_AMBA_AHB_‘ver’_‘ms’_‘dw’_‘tu’. The AHB Transactor recognizes transactions from the AHB active signals. These transactions are then made up of one or more of the appropriate phases. where ‘ver’. In this section the function. The protocol tree shows how the transactions are inter-related. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. orthogonal to the core transaction hierarchy. e. indicates the maximum number of masters and split-capable slaves (‘2x16’. An additional transaction.if tort to your rights. ‘8x16’. www. AHB_no_bus_transfer contains AHB_request_grant_phase. ‘fs’).g.g. These are in turn made up of one or more of the appropriate cycles. At the highest level are transactions representing complete transfers. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. ‘4x16’. ‘ms’.com 78 The document is for study only.com EMail:cadserv21@hotmail. ‘dw’ and ‘tu’ have the following meanings and valid values: • • • • ‘ver’ – version (‘v2p8’) ‘ms’ – master/slave configuration. ‘16x16’) ‘dw’ – data width. AHB_request and AHB_grant.please inform us.

if tort to your rights.please inform us.com EMail:cadserv21@hotmail.cadfamily.we will delete .Appendix A: AMBA AHB Transactor Protocol Tree www.com 79 The document is for study only.

T_slave_response Response MUX_S >=> master & arbiter. to the unit (or units) to the right of the symbol. T_transfer_size TransferSize MUX_M >=> slave. Attributes: T_request Request master >=> arbiter. or is to continue with a transfer later. Attributes: T_request Request master >=> arbiter. T_PROT ProtectionCtrl MUX_M >=> slave. www. T_slave_response Response MUX_S >=> master & arbiter. or idle transfer. It will connect a split transfer with its respective completion. from the unit to the left of the symbol.com 80 The document is for study only. T_lock Lock master >=> arbiter. busy. T_PROT ProtectionCtrl MUX_M >=> slave. T_transfer_size TransferSize MUX_M >=> slave.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.if tort to your rights.we will delete . T_lock Lock master >=> arbiter. word Data MUX_S >=> master AHB_transfer_attempt AHB_transfer_attempt is a multi-directional transaction used for a complete data. NOTE: The size of a number of the attributes is dependant on the transactor AHB_single_transfer AHB_single_transfer is a multi-directional transaction used for single bus transfers. T_WriteNread WriteNread MUX_M >=> slave.please inform us. configuration in use. split.cadfamily.com EMail:cadserv21@hotmail. T_burst_type BurstType MUX_M >=> slave & arbiter. word Address MUX_M >=> slave & decoder & arbiter. word Data MUX_S >=> master AHB_idle_busy_transfer AHB_idle_bust_transfer is a multi-directional transaction used when a bus master is granted access to the bus but does not immediately perform a data transfer. word Address MUX_M >=> slave & decoder & arbiter T_burst_type BurstType MUX_M >=> slave & arbiter. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). T_WriteNread WriteNread MUX_M >=> slave.

if tort to your rights. T_PROT ProtectionCtrl MUX_M >=> slave www. Attributes: T_WriteNread WriteNread MUX_M word Address MUX_M T_transfer_type TransferType T_burst_type BurstType MUX_M T_transfer_size TransferSize T_PROT ProtectionCtrl MUX_M T_slave_response Response word Data MUX_S >=> slave. T_transfer_type TransferTypeMUX_M >=> slave & arbiter.cadfamily. master >=> arbiter AHB_transfer_data AHB_transfer_data item is a multi-directional transaction used to perform a data transfer. Attributes: T_WriteNread WriteNread MUX_M >=> slave. T_burst_type BurstType MUX_M >=> slave & arbiter. T_burst_type BurstType MUX_M >=> slave & arbiter. T_slave_response Response MUX_S >=> master & arbiter.com 81 The document is for study only. T_lock Lock master >=> arbiter. word Address MUX_M >=> slave & decoder & arbiter. >=> slave. T_PROT ProtectionCtrl MUX_M >=> slave. T_WriteNread WriteNread MUX_M >=> slave. T_transfer_type TransferType MUX_M >=> slave & arbiter. T_transfer_size TransferSizeMUX_M >=> slave.we will delete . MUX_M >=> slave & arbiter. >=> slave & decoder & arbiter.Appendix A: AMBA AHB Transactor Attributes: T_request Request master >=> arbiter. >=> slave & arbiter. MUX_M >=> slave.com EMail:cadserv21@hotmail. >=> master AHB_control_phase AHB_control_phase is a multi-directional transaction used to perform the control phase of a data transfer. Attributes: T_request Request T_lock Lock master >=> arbiter. word Address MUX_M >=> slave & decoder & arbiter. T_transfer_size TransferSize MUX_M >=> slave. MUX_S >=> master & arbiter. word Data MUX_S >=> master AHB_no_bus_transfer AHB_no_bus_transfer is a multi-directional transaction used as a result of a master not being granted access to the bus by the arbiter.please inform us.

or not granting. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit ready MUX_S >=> master & arbiter & slave T_slave_response Response MUX_S >=> master & arbiter AHB_request_grant_phase AHB_request_grant_phase is a bi-directional transaction used to perform request and granting.we will delete . MUX_S >=> master AHB_data_write_phase AHB_data_write_phase is a multi-directional transaction used to perform the write phase of a data transfer. Attributes: T_slave_response Response word Data MUX_S >=> master & arbiter. Attributes: bit split_info_core[C_max_num_masters] www. arbiter >=> master AHB_split_info_core AHB_split_info_core is a uni-directional transaction used to unlock a master from a split transaction.nTX User’s Guide and Tutorial AHB_data_read_phase AHB_data_read_phase is a multi-directional transaction used to perform the read phase of a data transfer. Attributes: T_request Request T_lock Lock T_grant Grant master >=> arbiter. of access to the bus.com EMail:cadserv21@hotmail. master >=> arbiter.please inform us.cadfamily. MUX_M >=> slave AHB_response_cycle AHB_response_cycle is a multi-directional transaction used to perform the response to the data transfer.com 82 The document is for study only.if tort to your rights. Attributes: T_slave_response Response word Data MUX_S >=> master & arbiter.

Attributes: bit active_master[4] AHB_write_data AHB_write_data is a uni-directional transaction used to pass data from a master to a slave.Appendix A: AMBA AHB Transactor AHB_active_master AHB_active_master is a uni-directional transaction used to indicate the ID of the master currently active on the bus. Attributes: bit WriteNread. T_transfer_size TransferSize. bit ProtectionCtrl[4] www. Attributes: bit Data[C_datawidth] AHB_read_data AHB_read_data is a uni-directional transaction used to pass data from a slave to a master.com EMail:cadserv21@hotmail. synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period.please inform us. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit Data[C_datawidth] AHB_address AHB_address is a uni-directional transaction used to pass the address from a master to a slave. Attributes: bit Address[C_addresswidth] AHB_slave_control AHB_slave_control is a uni-directional transaction used to instruct the slave to control its response.cadfamily.we will delete . synchronized to the rising edge of the system clock of duration one clock period.if tort to your rights.com 83 The document is for study only.

if tort to your rights.com 84 The document is for study only. synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit master_Locked AHB_slave_ready AHB_slave_ready is a uni-directional transaction used to indicate that a transfer has completed on the bus.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial AHB_trans_control AHB_trans_control is a uni-directional transaction used to control the transfer on the bus. synchronized to the rising edge of the system clock of duration one clock period. Attributes: T_transfer_type TransferType.we will delete .cadfamily. synchronized to the rising edge of the system clock of duration one clock period.please inform us. Attributes: bit Request. Attributes: bit ready www. Attributes: bit grant AHB_master_Locked AHB_master_Locked is a uni-directional transaction used to lock a master access to the bus. synchronized to the rising edge of the system clock of duration one clock period. bit Lock AHB_grant AHB_grant is a uni-directional transaction used to grant access to the bus. T_burst_type BurstType AHB_request AHB_request is a uni-directional transaction used to request access to the bus.

size 3 bit array. size 4 Direction MUX_M >=> slave & arbiter MUX_M >=> slave & decoder & arbiter MUX_M >=> slave MUX_M >=> slave MUX_M >=> slave & arbiter MUX_M >=> slave MUX_S >=> master & arbiter & slave MUX_S >=> master & arbiter bit array. size number_of_masters array of bits. representing the output of the SPLIT signals from AHB slaves.com EMail:cadserv21@hotmail.if tort to your rights. size data_width MUX_S >=> master Master >=> arbiter Master >=> arbiter Arbiter >=> master arbiter >=> MUX_M & slave arbiter >=> master & slave HMASTLOCK bit www. size 3 bit array.please inform us. size 2 bit array. size address_width bit bit array. Attributes: T_slave_response Response stp_split_info stp_split_info is a uni-directional transaction.cadfamily. size data_width MUX_M >=> slave bit array.com 85 The document is for study only. size number_of_masters array of bits. Wires Name HTRANS HADDR HWRITE HSIZE HBURST HPROT HWDATA HREADY HRESP HRDATA HBUSREQ HLOCK HGRANT HMASTER Type bit array. and synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period. size 2 array of bits.Appendix A: AMBA AHB Transactor AHB_slave_response AHB_slave_response is a uni-directional transaction used to provide additional information on the status of the transfer. size 4 bit array bit array. It has no attributes. It is orthogonal to the core transaction hierarchy and is not included in the protocol tree.we will delete . size number_of_masters bit array.

ERROR = 1. WRAP16 = 6.com EMail:cadserv21@hotmail. NONSEQ = 2. such as ‘int’. SEQ = 3 }. INCR16 = 7 www.com 86 The document is for study only. size or_gate_S >=> arbiter max_number_of_masters bit bit clock_source >=> arbiter & master & slave reset_source >=> arbiter & master & slave Additional Information Data Types In addition to the standard transactor types. type enum T_burst_type:3 { SINGLE = 0. INCR4 = 3. WRAP8 = 4. INCR8 = 5.we will delete . RETRY = 2. BUSY = 1. INCR = 1.please inform us. the AHB transactor makes use of the following types: type enum T_slave_response:2 { OKAY = 0. and ‘bit’.cadfamily. type enum T_transfer_type:2 { IDLE = 0.if tort to your rights. SPLIT = 3 }. WRAP4 = 2.nTX User’s Guide and Tutorial Name HSPLIT_core HCLK HRESETn Type Direction bit array.

bits_64 = 3. bits_128 = 4. bits_32 = 2. PRIVILEGED = 1 }.if tort to your rights. CACHEABLE = 1 }. type enum T_WriteNread:1 { READ = 0.Appendix A: AMBA AHB Transactor }. bits_16 = 1.we will delete . DATA = 1 }. bits_1024 = 7 }. type enum T_transfer_size:3 { bits_8 = 0. type struct T_PROT { T_data_nOpcode data_opcode. BUFFERABLE = 1 }.please inform us.com EMail:cadserv21@hotmail. bits_256 = 5.com 87 The document is for study only. T_bufferable bufferable. type enum T_data_nOpcode:1 { OPCODE= 0.cadfamily. WRITE = 1 }. T_privileged privileged. bits_512 = 6. www. type enum T_privileged:1 { USER = 0. type enum T_cacheable:1 { NOT_CACHEABLE = 0. type enum T_bufferable:1 { NOT_BUFFERABLE= 0.

cadfamily. type enum T_grant:1 { NO_GRANT = 0. LOCK = 1 }.please inform us. 32. REQUEST = 1 }. GRANT = 1 }. 4. type enum T_lock:1 { NO_LOCK = 0.we will delete . Transactor Constants • • • C_max_num_masters – the number of masters in use (valid values are 2.com EMail:cadserv21@hotmail. type enum T_request:1 { NO_REQUEST= 0.if tort to your rights. }.nTX User’s Guide and Tutorial T_cacheable cacheable. 64. 128 and 256) C_addresswidth – the width of the address bus (valid value is 32) www.com 88 The document is for study only. 8 and 16) C_datawidth – the width of the data bus (valid values are 16.

Sequential and non-sequential single transfers.com EMail:cadserv21@hotmail.please inform us. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. Name The bus declaration (nte_AMBA_AHB_lite_v2p8_32_ns) must be one of the supported transactors.com 89 The document is for study only. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.if tort to your rights.Appendix B: AMBA AHB Lite Transactor Appendix B: AMBA AHB Lite Transactor Overview The AMBA-AHB Transactor supports the following features: • • • Data bus width from 8-bits to 1024-bits. IDLE and BUSY transfer types. MAPPING_ROOT = "/AHB_lite_system/test_AHB". www. nte_AMBA_AHB_lite_v2p8_32_ns MyAHB_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.we will delete .cadfamily.

we will delete . SIGMAP { // signals from master MUX (address. however. /ahb_core/HSIZE ="/V_AHB_core/HSIZE". clk_2nd_time: The relative time of the second clock change after the previous change. NOTE: Clock can be mapped to /ahb_core/HCLK. warn_after_n_ready_low_cycles: A warning will be issued when the ready signal from selected slave has remained low for ‘n’ clock cycles www. clk_phase_shift: The time of the first transition from the initial value. it is possible to leave signals unconnected by removing them from the sigmap section. clk_1st_time: The relative time of the first clock change after the initial phase shift change. } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file: • • • • • • • clk_init_value: The initial value of the clock (0 or 1). /ahb_core/HRESP ="/V_AHB_core/HRESP". /ahb_core/HRDATA ="/V_AHB_core/HRDATA". The SIGMAP code example is for an unmapped clock. // signals from slave MUX (read data and response) // all of these are inputs to each master /ahb_core/HREADY ="/V_AHB_core/HREADY". setup_time: The setup time for all AHB signals. hold_time: The hold time for all AHB signals.if tort to your rights.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. /ahb_core/HMASTLOCK ="/V_AHB_core/HMASTLOCK". /ahb_core/HBURST ="/V_AHB_core/HBURST".com EMail:cadserv21@hotmail. /ahb_core/HWDATA ="/V_AHB_core/HWDATA".com 90 The document is for study only. If this is done they will be assigned a default value (normally 0). control and // write data MUX) // all of these are inputs to each slave /ahb_core/HTRANS ="/V_AHB_core/HTRANS". /ahb_core/HPROT ="/V_AHB_core/HPROT". /ahb_core/HWRITE ="/V_AHB_core/HWRITE".please inform us. The transactor signals are pre-defined as shown in the file below and must not be changed. /ahb_core/HADDR ="/V_AHB_core/HADDR".cadfamily.

‘fs’).we will delete . //ns setup_time = 2 ns. The clock set up is important for the correct operation of the transactor. //ns clk_1st_time = 5 ns.if tort to your rights. //ns hold_time = 1 ns. //ns clk_2nd_time = 5 ns. where ‘ver’.com EMail:cadserv21@hotmail. Transactor Configurations A number of transactor configurations are available.cadfamily. however. An example is shown below: Figure: Clock Setup // parameters PARAMETER { clk_init_value = 0. //ns warn_after_n_ready_low_cycles = 100.Appendix B: AMBA AHB Lite Transactor after it was selected. www. ‘256’) ‘tu’ – time unit (‘ps’. The naming convention used is nte_AMBA_AHB_lite_‘ver’_‘dw’_‘tu’. If the clock is mapped then clk_* parameters do not need to be set. ‘64’. } NOTE: PARAMETER code example is for an unmapped clock.com 91 The document is for study only. ‘128’.please inform us. This does not have to match the time scale of the input FSDB file. ‘dw’ and ‘tu’ have the following meanings and valid values: • • • ‘ver’ – version (‘v2p8’) ‘dw’ – width of data bus (‘16’. ‘32’. where ‘n’ is equal to the number set for the parameter. //initial value of clock clk_phase_shift = 0 ns. ‘ns’. any signal changes below this time resolution will not be seen by nTE.

AHB_slave_control and AHB_trans_control transactions. e. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. The protocol tree shows how the transactions are inter-related. These transactions are then made up of one or more of the appropriate phases. or AHB_data_read_phase. AHB_control_phase is made up of AHB_address.com 92 The document is for study only. which is made up of AHB_control_phase and AHB_data_write_phase.cadfamily.com EMail:cadserv21@hotmail.please inform us. AHB_single_transfer contains AHB_transfer_data.we will delete . www.g. These are in turn made up of one or more of the appropriate cycles. The highest level includes transactions representing complete transfers. e.nTX User’s Guide and Tutorial Transaction Hierarchy The AHB-Lite transactor consists of a number of transactions that enable communication at different levels of abstraction.g.if tort to your rights. types and attributes of these transactions are described in detail. In this section the function.

Appendix B: AMBA AHB Lite Transactor Protocol Tree www.if tort to your rights.com 93 The document is for study only.we will delete .please inform us.cadfamily.com EMail:cadserv21@hotmail.

word Address master >=> slave & decoder T_burst_type BurstType master >=> slave T_transfer_size TransferSize master >=> slave. T_burst_type BurstType master >=> slave. T_slave_response Response MUX_S >=> master.com EMail:cadserv21@hotmail.we will delete . T_slave_response Response MUX_S >=> master. master >=> slave & decoder. to the unit (or units) to the right of the symbol.please inform us. T_transfer_size TransferSize master >=> slave. configuration in use.if tort to your rights.com 94 The document is for study only. master >=> slave. Attributes: T_WriteNread WriteNread master >=> slave. www. NOTE: The size of a number of the attributes is dependant on the transactor AHB_single_transfer AHB_single_transfer is a multi-directional transaction used for single bus transfers. Attributes: T_WriteNread WriteNread word Address T_transfer_type TransferType master >=> slave.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. T_PROT ProtectionCtrl master >=> slave.cadfamily. from the unit to the left of the symbol. word Address master >=> slave & decoder. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). word Data MUX_S >=> master AHB_idle_busy_transfer AHB_idle_busy_transfer is a multi-directional transaction used when the master does not perform a read or write transfer. Attributes: T_WriteNread WriteNread master >=> slave. T_PROT ProtectionCtrl master >=> slave. word Data MUX_S >=> master AHB_transfer_data AHB_transfer_data item is a multi-directional transaction used to perform a data transfer.

Appendix B: AMBA AHB Lite Transactor T_burst_type BurstType T_transfer_size TransferSize T_PROT ProtectionCtrl T_slave_response Response word Data master >=> slave &, master >=> slave, master >=> slave, MUX_S >=> master, MUX_S >=> master

AHB_control_phase
AHB_control_phase is a multi-directional transaction used to perform the control phase of a data transfer. Attributes:
T_WriteNread WriteNread word Address T_transfer_type TransferType T_burst_type BurstType T_transfer_size TransferSize T_PROT ProtectionCtrl master master master master master master >=> >=> >=> >=> >=> >=> slave, slave & decoder, slave, slave, slave, slave

AHB_data_read_phase
AHB_data_read_phase is a multi-directional transaction used to perform the read phase of a data transfer. Attributes:
T_slave_response Response word Data MUX_S >=> master, MUX_S >=> master

AHB_data_write_phase
AHB_data_write_phase is a multi-directional transaction used to perform the write phase of a data transfer. Attributes:
T_slave_response Response word Data MUX_S >=> master, master >=> slave

AHB_response_cycle
AHB_response_cycle is a multi-directional transaction used to perform the response to the data transfer. Attributes:
bit ready T_slave_response Response MUX_S >=> master & slave MUX_S >=> master

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nTX User’s Guide and Tutorial

AHB_write_data
AHB_write_data is a uni-directional transaction used to pass data from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Data[C_datawidth]

AHB_read_data
AHB_read_data is a uni-directional transaction used to pass data from a slave to the master, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Data[C_datawidth]

AHB_address
AHB_address is a uni-directional transaction used to pass the address from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Address[C_addresswidth]

AHB_slave_control
AHB_slave_control is a uni-directional transaction used to pass control information from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit WriteNread, T_transfer_size TransferSize, bit ProtectionCtrl[4]

AHB_trans_control
AHB_trans_control is a uni-directional transaction used to pass additional control information from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
T_transfer_type TransferType, T_burst_type BurstType

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Appendix B: AMBA AHB Lite Transactor

AHB_master_Locked
AHB_master_Locked is a uni-directional transaction used to indicate the master wishes locked access to the slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit master_Locked

AHB_slave_ready
AHB_slave_ready is a uni-directional transaction used to indicate that a transfer has completed on the bus, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit ready

AHB_slave_response
AHB_slave_response is a uni-directional transaction used to indicate the transfer completion response of the slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
T_slave_response Response

Wires
Name HTRANS HADDR HWRITE HSIZE HBURST HPROT HWDATA HREADY HRESP HRDATA Type bit array, size 2 bit array, size address_width bit bit array, size 3 bit array, size 3 bit array, size 4 bit array, size data_width bit array bit array, size 2 bit array, size data_width Direction master >=> slave master >=> slave & decoder master >=> slave master >=> slave master >=> slave master >=> slave master >=> slave MUX_S >=> master & slave MUX_S >=> master MUX_S >=> master master >=> slave

HMASTLOCK bit

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nTX User’s Guide and Tutorial

Name HCLK HRESETn

Type bit bit

Direction clock_source >=> master & slave reset_source >=> master & slave

Additional Information
Data Types
In addition to the standard transactor types, such as ‘int’, and ‘bit’, the AHB-Lite transactor makes use of the following types: type enum T_slave_response:2
{ OKAY = 0, ERROR = 1, RETRY = 2, SPLIT = 3 }; type enum T_transfer_type:2 { IDLE = 0, BUSY = 1, NONSEQ = 2, SEQ = 3 }; type enum T_burst_type:3 { SINGLE = 0, INCR = 1, WRAP4 = 2, INCR4 = 3, WRAP8 = 4, INCR8 = 5, WRAP16 = 6, INCR16 = 7 };

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Appendix B: AMBA AHB Lite Transactor type enum T_transfer_size:3 { bits_8 = 0. T_cacheable cacheable. type enum T_privileged:1 { USER = 0.please inform us. CACHEABLE = 1 }. PRIVILEGED = 1 }. BUFFERABLE = 1 }. WRITE = 1 }. bits_64 = 3.if tort to your rights. type enum T_bufferable:1 { NOT_BUFFERABLE= 0.we will delete . bits_128 = 4. bits_16 = 1. T_privileged privileged. type struct T_PROT { T_data_nOpcode data_opcode. }. www.com 99 The document is for study only. bits_256 = 5. bits_1024 = 7 }. bits_512 = 6. bits_32 = 2. type enum T_cacheable:1 { NOT_CACHEABLE = 0. type enum T_WriteNread:1 { READ = 0. T_bufferable bufferable.cadfamily. type enum T_data_nOpcode:1 { OPCODE= 0.com EMail:cadserv21@hotmail. DATA = 1 }.

we will delete .com 100 The document is for study only. LOCK = 1 }.nTX User’s Guide and Tutorial type enum T_request:1 { NO_REQUEST= 0.please inform us.cadfamily.com EMail:cadserv21@hotmail.if tort to your rights. Transactor Constants • • C_datawidth – the width of the data bus (valid values are 16. 128 and 256) C_addresswidth – the width of the address bus (valid value is 32) www. REQUEST = 1 }. GRANT = 1 }. type enum T_lock:1 { NO_LOCK = 0. 32. type enum T_grant:1 { NO_GRANT = 0. 64.

if tort to your rights.we will delete .0 APB Support for single slave systems with no select bus.com EMail:cadserv21@hotmail. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. MAPPING_ROOT = "/APB_test/st_APB/APB_bus".please inform us. Name The bus declaration (nte_AMBA_APB_v1p0_32x16_ns) must be one of the supported transactors.com 101 The document is for study only. www. nte_AMBA_APB_v1p0_32x16_ns my_APB { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.Appendix C: AMBA APB Transactor Appendix C: AMBA APB Transactor Overview The AMBA-AXI Transactor supports the following features: • • AMBA 2.cadfamily. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.

clk_1st_time: The relative time of the first clock change after the initial phase shift change. clk_phase_shift: The time of the first transition from the initial value. "/PSEL_2". "/PSEL_6". "/PSEL_13". "/PSEL_9". The SIGMAP code example is for an unmapped clock. "/PWDATA". "/PSEL_5".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.please inform us. "/PSEL_11".com 102 The document is for study only. then some of these can be left unconnected (remove the mapping from the SIGMAP block).if tort to your rights. www. "/PSEL_10".cadfamily. "/PSEL_7". "/PWRITE". "/PRDATA". "/PSEL_12".com EMail:cadserv21@hotmail. "/PSEL_3". If there are less slaves in the system. SIGMAP { /APB_bus/PADDR /APB_bus/PSEL[0] /APB_bus/PSEL[1] /APB_bus/PSEL[2] /APB_bus/PSEL[3] /APB_bus/PSEL[4] /APB_bus/PSEL[5] /APB_bus/PSEL[6] /APB_bus/PSEL[7] /APB_bus/PSEL[8] /APB_bus/PSEL[9] /APB_bus/PSEL[10] /APB_bus/PSEL[11] /APB_bus/PSEL[12] /APB_bus/PSEL[13] /APB_bus/PSEL[14] /APB_bus/PSEL[15] /APB_bus/PENABLE /APB_bus/PWRITE /APB_bus/PRDATA /APB_bus/PWDATA } = = = = = = = = = = = = = = = = = = = = = "/PADDR". "/PSEL_1". "/PSEL_0".we will delete . "/PSEL_8". This example is for a transactor with 16 APB slaves connected. "/PSEL_15". Configuration of the transactor is made via the PARAMETER section of the bcf file. "/PENABLE". "/PSEL_14". Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. The transactor signals are pre-defined as shown in the file below and must not be changed. "/PSEL_4". The available parameters are: • • • clk_init_value: The initial value of the clock (0 or 1). NOTE: Clock can be mapped to /APB_bus/PCLK.

1 ns. Set this to ‘false’ if the system has a single slave. Setting this to false will also disable recognition of idle transactions. use_select: Use the slave select bus (‘true’ or ‘false’). true.com EMail:cadserv21@hotmail.Appendix C: AMBA APB Transactor • • • • clk_2nd_time: The relative time of the second clock change after the previous change. Transactor Configurations A number of transactor configurations are available.we will delete . • allow_idle: Recognize idle transactions (‘true’ or ‘false’). setup_time: The setup time for all APB signals. 1 ns.16. Defaults to ‘true’. ‘dw’.com 103 The document is for study only. 50 ns. hold_time: The hold time for all APB signals. Defaults to ‘true’.if tort to your rights. NOTE: PARAMETER code example is for an unmapped clock.please inform us. then PSEL should not be mapped in the SIGMAP block. If the clock is mapped then clk_* parameters do not need to be set.cadfamily. ‘max_slaves’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘dw’ – width of data bus (8. and no PSEL bus. An example is shown below: Figure: Clock Setup // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time use_select allow_idle } = = = = = = = = 0b0. 32) www. 50 ns. 50 ns. The naming convention used is nte_AMBA_APB_‘ver’_‘dw’x‘max_slaves’_‘tu’ where ‘ver’. true. The clock set up is important to the correct operation of the transactor. Setting to ‘false’ will result in smaller output FSDB. Note that if this is set to false.

com 104 The document is for study only. sets width of PSEL (16.please inform us.nTX User’s Guide and Tutorial • • ‘tu’ – time unit (‘ps’. any signal changes below this time resolution will not be seen by nTE. 64) www.com EMail:cadserv21@hotmail.we will delete . ‘ns’. however. ‘fs’). This does not have to match the time scale of the input FSDB file.if tort to your rights. ‘max_slaves’ – maximum number of connected slaves.cadfamily.

types and attributes of these transactions are described in detail.please inform us.we will delete .Appendix C: AMBA APB Transactor Transaction Hierarchy The APB transactor consists of a number of transactions that enable communication at different levels of abstraction. In this section the function.com 105 The document is for study only. Protocol Tree www.if tort to your rights.com EMail:cadserv21@hotmail. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.cadfamily.

PENABLE = 0).please inform us.com EMail:cadserv21@hotmail. RnW. Attributes: word bit bit slave_id addr[C_APB_addresswidth] data[C_APB_wdatawidth] master >=> slave.cadfamily. PENABLE = 1). PENABLE = 0).if tort to your rights. Attributes: word bit bit slave_id. Attributes: word T_WriteNread bit bit slave_id. wdata[C_APB_wdatawidth] //only used/written to //when RnW == write enable A single cycle transaction representing the ENABLE state of the APB bus (PSELx = 1. from the unit to the left of the symbol.com 106 The document is for study only. data[C_APB_wdatawidth] idle A single cycle transaction representing the IDLE state of the APB bus (PSELx = 0. master >=> slave. along with values of address. addr[C_APB_addresswidth]. RnW and wdata if it is valid. Attributes indicate the currently selected slave. www. Attributes: None setup A single cycle transaction representing the SETUP state of the APB bus (PSELx = 1. Attributes indicate the currently selected slave. addr[C_APB_addresswidth]. to the unit (or units) to the right of the symbol. slave >=> master write write is an APB write from a master (typically an APB bridge) to a slave.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.we will delete . read read is an APB read from a master (typically an APB bridge) to a slave.

and if so. T_WriteNread RnW master >=> slave.please inform us. Attributes: bit en control_cycle control_cycle is a single cycle transaction that holds the values of the RnW and address signals.we will delete . Attributes: word slave_id master >=> slave.Appendix C: AMBA APB Transactor along with values of address. // data holds either read or write data depending on RnW bit data[] master >=> slave || slave >=> master selected_slave selected slave is a single cycle transaction used to indicate whether or not a slave is selected. Attributes: T_WriteNread bit RnW.com 107 The document is for study only. slave_id enable_cycle enable_cycle is a single cycle transaction that holds the value of the enable signal. bit addr[C_APB_addresswidth] master >=> slave. Attributes: bit wdata[C_APB_wdatawidth] rdata_cycle rdata_cycle is a single cycle transaction that holds the value of the read data bus. addr[C_APB_addresswidth] wdata_cycle wdata_cycle is a single cycle transaction that holds the value of the write data bus. the id of that slave. RnW and data (either read or write data depending on the current value of RnW). Attributes: bool word selected.com EMail:cadserv21@hotmail.cadfamily. Attributes: www.if tort to your rights.

Name PCLK PADDR PSEL PENABLE PWRITE PRDATA PWDATA Type bit bit [C_APB_addresswidth] [C_num_slaves] bit bit bit bit [C_APB_rdatawidth] bit [C_APB_wdatawidth] Direction clock_source >=> master & slave master to slave master to slave master to slave master to slave slave to master master to slave www.com EMail:cadserv21@hotmail. see the section on Signal Descriptions in the AMBA AXI Protocol Specification.com 108 The document is for study only.nTX User’s Guide and Tutorial bit rdata[C_APB_rdatawidth] Wires For a description of each of these wires (signals).please inform us.cadfamily.we will delete .if tort to your rights.

and ‘bit’.please inform us.cadfamily. the APB transactor makes use of the following types: type enum T_WriteNread:1 { READ = 0.we will delete .com EMail:cadserv21@hotmail.com 109 The document is for study only. such as ‘int’.if tort to your rights.Appendix C: AMBA APB Transactor Additional Information Data Types In addition to the standard transactor types. WRITE = 1 }. Transactor Constants • • • • C_APB_rdatawidth – the width of the read data bus C_APB_wdatawidth – the width of the write data bus C_APB_addresswidth – the width of the address bus C_num_slaves – the width of the slave select bus (determines the maximum number of slaves) www.

nTX User’s Guide and Tutorial www.we will delete .com 110 The document is for study only.cadfamily.please inform us.com EMail:cadserv21@hotmail.if tort to your rights.

com EMail:cadserv21@hotmail. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.Appendix D: AMBA AXI Transactor Appendix D: AMBA AXI Transactor Overview The AMBA-AXI Transactor supports the following features: • • • • Configurable bus widths (address. MAPPING_ROOT = "/verilog_conc_model/AXI_structure/iAXI".if tort to your rights.please inform us.com 111 The document is for study only.we will delete . transaction ID) Recognition of complete bursts as a single transaction Out-of-order transaction completion Full support for narrow transfers and unaligned transfers (encoding/ decoding of data onto the data bus) BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. Name The bus declaration (nte_AMBA_AXI_v1p6_32_32_32_4_ns) must be one of the supported transactors. www. read data. write data. nte_AMBA_AXI_v1p6_32_32_32_4_ns my_AXI { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.cadfamily.

The transactor signals are pre-defined as shown in the file below and must not be changed.please inform us.com EMail:cadserv21@hotmail.cadfamily. /AXI/ARBURST = "/ARBURST". "/RRESP". /AXI/ARREADY = "/ARREADY". The SIGMAP code example is for an unmapped clock. /AXI/AWPROT = "/AWPROT".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. SIGMAP { // From reset source /AXI/ARESETn = "/ARESETn".com 112 The document is for study only. /AXI/AWBURST = "/AWBURST". /AXI/ARLEN = "/ARLEN". If this is done they will be assigned a default value (normally 0). /AXI/AWSIZE = "/AWSIZE". /AXI/AWADDR = "/AWADDR". "/RREADY". /AXI/AWLEN = "/AWLEN". /AXI/ARID = "/ARID". it is possible to leave signals unconnected by removing them from the sigmap section. // Read channel /AXI/RVALID /AXI/RLAST /AXI/RDATA /AXI/RRESP /AXI/RID /AXI/RREADY // Write channel = = = = = = "/RVALID". /AXI/AWREADY = "/AWREADY". /AXI/AWID = "/AWID". "/RDATA".if tort to your rights. "/RID". /AXI/AWCACHE = "/AWCACHE". /AXI/ARCACHE = "/ARCACHE". /AXI/AWLOCK = "/AWLOCK".we will delete . NOTE: Clock can be mapped to /AXI/ACLK. // Write address channel /AXI/AWVALID = "/AWVALID". /AXI/ARPROT = "/ARPROT". www. /AXI/ARADDR = "/ARADDR". /AXI/ARSIZE = "/ARSIZE". "/RLAST". /AXI/ARLOCK = "/ARLOCK". // Read address channel /AXI/ARVALID = "/ARVALID". however.

clk_1st_time: The relative time of the first clock change after the initial phase shift change. "/WREADY". "/WSTRB". Configuration of the transactor is made via the PARAMETER section of the bcf file.Appendix D: AMBA AXI Transactor /AXI/WVALID /AXI/WLAST /AXI/WDATA /AXI/WSTRB /AXI/WID /AXI/WREADY = = = = = = "/WVALID". /AXI/BREADY = "/BREADY".please inform us. • byte_level_transactions: Boolean value (true/false) to determine whether the top level AXI transactions are AXI_read/write (true) or AXI_buswidth_read/write (false). "/WID". • hold_time: The hold time for all AXI signals. • setup_time: The setup time for all AXI signals.cadfamily. /AXI/BID = "/BID". "/WDATA". /AXI/BRESP = "/BRESP". The available parameters are: clk_init_value: The initial value of the clock (0 or 1).com 113 The document is for study only.we will delete . must be less than or equal to the maximum width for the transactor. } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. // Write response channel /AXI/BVALID = "/BVALID". • wdata_width: The width of the write data bus (in bits). An example is shown below: • • • www. The clock set up is important to the correct operation of the transactor. clk_phase_shift: The time of the first transition from the initial value. • clk_2nd_time: The relative time of second clock change after the previous change.com EMail:cadserv21@hotmail.if tort to your rights. must be less than or equal to the maximum width for the transactor. • rdata_width: Tthe width of the read data bus (in bits). "/WLAST".

5 ns. ‘iw’ and ‘tu’ have the following meanings and valid values: • • • • • ‘ver’ – version (‘v2p8’) ‘rw’/’ww’ – read/write width (16. www. ‘ns’.nTX User’s Guide and Tutorial Figure: Clock Setup // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time byte_level_transactions rdata_width wdata_width } = = = = = = = 0. // // // = 32. ‘aw’. 5 ns. ‘fs’). 64. 0 ns. 2 ns. true.cadfamily.if tort to your rights. Transactor Configurations A number of transactor configurations are available. // // = 32. ‘rw’. any signal changes below this time resolution will not be seen by nTE. 128.please inform us. ‘ww’.com 114 The document is for study only. 1 ns. The naming convention used is nte_AMBA_AXI_‘ver’_‘rw’_‘ww’_‘aw’_‘iw’_‘tu’ where ‘ver’. however. 32. 256 –equal values) ‘aw’ – address width (‘32’) ‘iw’ – ID width (‘4’) ‘tu’ – time unit (‘ps’. // // top level transaction selection (byte level or buswidth variants) width of read data in bits width of write data in bits NOTE: PARAMETER code example is for an unmapped clock.com EMail:cadserv21@hotmail.we will delete . This does not have to match the time scale of the input FSDB file. If the clock is mapped then clk_* parameters do not need to be set.

please inform us. types and attributes of these transactions are described in detail.com EMail:cadserv21@hotmail.if tort to your rights. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.we will delete .Appendix D: AMBA AXI Transactor Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. www.cadfamily.com 115 The document is for study only. In this section the function.

com 116 The document is for study only.com EMail:cadserv21@hotmail.please inform us.nTX User’s Guide and Tutorial Protocol Tree www.we will delete .if tort to your rights.cadfamily.

This is followed by a read_data_burst transaction returning the requested data and response status from slave to master. master. There can be multiple outstanding (concurrent) reads. A read_control transaction passes address and control information from the master to the slave.cadfamily. configuration in use. Note that AXI_read is mutually exclusive to AXI_buswidth_read.we will delete .com EMail:cadserv21@hotmail. This is followed by a read_data_burst transaction returning the requested data and response status from slave to master. slave. These can overlap due to pipe-lining and the use of the ID signal. These can overlap due to pipe-lining and the use of the ID signal.if tort to your rights. from the unit to the left of the symbol.please inform us. slave. slave. slave. with read data (and length) expressed in words of size equal to the bus width. There can be multiple outstanding (concurrent) reads. AXI_buswidth_read AXI_buswidth_read is a bidirectional read transaction between the master and slave. to the unit (or units) to the right of the symbol. slave. slave.com 117 The document is for study only. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). NOTE: The size of a number of the attributes is dependant on the transactor AXI_read AXI_read is a bidirectional read transaction between the master and slave. with read data (and length) expressed in bytes. master data_length is the number of bytes in the transaction. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] T_AXI_SIZE size T_AXI_BURST burst T_AXI_LOCK lock T_AXI_CACHE cache T_AXI_PROT prot bit id[AXI_MAX_ID_WIDTH] int data_length bit data_bytes[AXI_MAX_RDATA_LENGTH][8] T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH] master master master master master master master master slave slave >=> >=> >=> >=> >=> >=> >=> >=> >=> >=> slave. Note that AXI_buswidth_read is mutually exclusive to AXI_read. slave. Attributes: www. A read_control transaction passes address and control information from the master to the slave.Appendix D: AMBA AXI Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.

slave.if tort to your rights. AXI_buswidth_write AXI_buswidth_write is a bidirectional write transaction between the master and slave. T_AXI_SIZE size master >=> slave. A write_data_burst transaction passes data and strobe information from master to slave.nTX User’s Guide and Tutorial bit addr[AXI_MAX_ADDRESS_WIDTH] master >=> slave. slave. A write_control transaction passes address and control information from the master to the slave.please inform us.com EMail:cadserv21@hotmail. slave. with write data (and length) expressed in words of size equal to the bus width. T_AXI_CACHE cache master >=> slave. master data_length is the number of bytes in the transaction. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] T_AXI_SIZE size T_AXI_BURST burst T_AXI_LOCK lock T_AXI_CACHE cache T_AXI_PROT prot bit id[AXI_MAX_ID_WIDTH] int data_length bit data_bytes[AXI_MAX_WDATA_LENGTH][8] T_AXI_RESPONSE resp master master master master master master master master master slave >=> >=> >=> >=> >=> >=> >=> >=> >=> >=> slave. slave. Note that AXI_write is mutually exclusive to AXI_buswidth_write. T_AXI_LOCK lock master >=> slave. These can overlap due to pipe-lining and the use of the ID signal. There can be multiple outstanding (concurrent) writes. with the two transactions being linked together by a common id. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_RDATA_WIDTH] slave >=> master.com 118 The document is for study only. be in parallel with or follow the write_control. slave. The AXI_write transaction is finished by a write_response transaction passing status information from the slave to the master. int ntransfers master >=> slave.cadfamily. A write_data_burst transaction passes data and strobe www. slave. The write_data_burst may precede. AXI_write AXI_write is a bidirectional write transaction between the master and slave. T_AXI_BURST burst master >=> slave. T_AXI_PROT prot master >=> slave. A write_control transaction passes address and control information from the master to the slave. with write data (and length) expressed in bytes. slave. T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH] slave >=> master ntransfers is the number of words of size equal to the bus width in the transaction. bit id[AXI_MAX_ID_WIDTH] master >=> slave. slave.we will delete .

int ntransfers master >=> slave. The AXI_write transaction is finished by a write_response transaction passing status information from the slave to the master.com 119 The document is for study only. with the two transactions being linked together by a common id.Appendix D: AMBA AXI Transactor information from master to slave. burst. T_AXI_CACHE cache master >=> slave.com EMail:cadserv21@hotmail. T_AXI_RESPONSE resp slave >=> master ntransfers is the number of words of size equal to the bus width in the transaction. ntransfers. There can be multiple outstanding (concurrent) writes. These can overlap due to pipelining and the use of the ID signal.if tort to your rights. cache. A read_control transaction may take multiple clock cycles to complete. read_control read_control is a unidirectional transaction passing address and control information from master to slave as part of a read transaction. T_AXI_BURST burst master >=> slave. bit write_strobes[AXI_MAX_BURST_LENGTH][AXI_MAX_WSTRB_WIDTH] master >=> slave. T_AXI_LOCK lock master >=> slave. but only one may be active at any time.cadfamily. bit id[AXI_MAX_ID_WIDTH] master >=> slave. lock. T_AXI_SIZE size master >=> slave. size.we will delete . Attributes: bit int T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH]. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] master >=> slave. T_AXI_PROT prot master >=> slave. The write_data_burst may precede. www. It consists of a single read_addr_channel_phase. id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) to be transferred. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_WDATA_WIDTH] master >=> slave. Note that AXI_buswidth_write is mutually exclusive to AXI_write. prot. be in parallel with or follow the write_control.please inform us.

burst.nTX User’s Guide and Tutorial read_data_burst read_data_burst is a unidirectional transaction passing data and status information from slave to master as part of a read transaction. There can be multiple outstanding (concurrent) write data bursts.if tort to your rights. ntransfers. prot.please inform us. Attributes: bit int T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH].com EMail:cadserv21@hotmail.we will delete . id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) to be transferred. write_control write_control is a unidirectional transaction passing address and control information from master to slave as part of a write transaction.com 120 The document is for study only. These can overlap due to pipelining and the use of the ID signal. These can overlap due to pipelining and the use of the ID signal. It consists of a single write_addr_channel_phase. It consists of one or more write_channel_phase transactions. Attributes: int ntransfers. but only one may be active at any time. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_RDATA_WIDTH]. cache. size. It consists of one or more read_channel_phase transactions. lock. bit id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) being transferred. There can be multiple outstanding (concurrent) read data bursts. www. write_data_burst write_data_burst is a unidirectional transaction passing data and strobe information from master to slave as part of a write transaction.cadfamily. A write_control transaction may take multiple clock cycles to complete. T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH]. Attributes: int ntransfers.

A read_addr_channel_phase transaction may take multiple clock cycles to complete. id[AXI_MAX_ID_WIDTH] read_addr_channel_phase read_addr_channel_phase is a unidirectional transaction passing address and control information from master to slave as part of a read transaction. id[AXI_MAX_ID_WIDTH] The number of transfers is defined as length+1 read_channel_phase read_channel_phase is a unidirectional transaction passing a single word of data and status information from slave to master as part of a read transaction. It consists of one or more read_channel_cycle transactions. but only one may be active at any time. Attributes: T_AXI_RESPONSE bit resp. bit strb[AXI_MAX_BURST_LENGTH][AXI_MAX_WSTRB_WIDTH]. It consists of a single write_resp_channel_phase. write_response write_response is a unidirectional transaction passing status information from slave to master as part of a write transaction. prot.cadfamily. Attributes: bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH].we will delete . A read_channel_phase transaction may take multiple clock cycles to complete. determined by the RREADY signal. lock. A write_response transaction may take multiple clock cycles to complete.please inform us. cache. bit id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) being transferred. www. burst. length[4]. It consists of one or more read_addr_channel_cycle transactions. but only one may be active at any time. determined by the ARREADY signal.if tort to your rights. but only one may be active at any time.com 121 The document is for study only.com EMail:cadserv21@hotmail. size.Appendix D: AMBA AXI Transactor bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_WDATA_WIDTH].

A write_resp_channel_phase www. prot. cache.com EMail:cadserv21@hotmail. Attributes: T_AXI_LAST bit bit bit last.nTX User’s Guide and Tutorial Attributes: T_AXI_LAST bit T_AXI_RESPONSE bit last. It consists of one or more write_addr_channel_cycle transactions. It consists of one or more write_resp_channel_cycle transactions. data[AXI_MAX_WDATA_WIDTH]. id[AXI_MAX_ID_WIDTH] write_addr_channel_phase write_addr_channel_phase is a unidirectional transaction passing address and control information from master to slave as part of a write transaction. determined by the AWREADY signal. burst. determined by the WREADY signal.we will delete . A write_addr_channel_phase transaction may take multiple clock cycles to complete. write_channel_phase write_channel_phase is a unidirectional transaction passing a single word of data and strobe information from master to slave as part of a write transaction. data[AXI_MAX_RDATA_WIDTH]. resp. but only one may be active at any time. id[AXI_MAX_ID_WIDTH] The number of transfers is defined as length+1. length[4].cadfamily. size. but only one may be active at any time. strb[AXI_MAX_WSTRB_WIDTH]. Attributes: bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH].if tort to your rights.please inform us. lock. It consists of one or more write_channel_cycle transactions. A write_channel_phase transaction may take multiple clock cycles to complete. id[AXI_MAX_ID_WIDTH] write_resp_channel_phase write_resp_channel_phase is a unidirectional transaction passing a status information from slave to master as part of a write transaction.com 122 The document is for study only.

burst.please inform us.com EMail:cadserv21@hotmail.com 123 The document is for study only. Each read_addr_channel_cycle groups the set of read address channel signals and synchronizes them to a clock.Appendix D: AMBA AXI Transactor transaction may take multiple clock cycles to complete. determined by the BREADY signal. prot. id[AXI_MAX_ID_WIDTH] write_addr_channel_cycle write_addr_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. Attributes: T_AXI_VALID T_AXI_LAST bit T_AXI_RESPONSE bit valid. with only one active at a time. size. id[AXI_MAX_ID_WIDTH] read_addr_channel_cycle read_addr_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. data[AXI_MAX_RDATA_WIDTH]. One or more read_addr_channel_cycles make up a read_addr_channel_phase. with only one active at a time. the number of which is determined by RREADY. Attributes: T_AXI_VALID bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit valid. length[4]. with only one active at a time. www. addr[AXI_MAX_ADDRESS_WIDTH].if tort to your rights. but only one may be active at any time.we will delete .cadfamily. One or more read_channel_cycles make up a read_channel_phase. resp. Attributes: T_AXI_RESPONSE bit resp. lock. Each write_addr_channel_cycle groups the set of write address channel signals and synchronizes them to a clock. cache. Each read_channel_cycle groups the set of read channel signals (for data/response) and synchronizes them to a clock. last. id[AXI_MAX_ID_WIDTH] read_channel_cycle read_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. the number of which is determined by ARREADY.

resp. Attributes: www. One or more write_resp_channel_cycles make up a write_resp_channel_phase. addr[AXI_MAX_ADDRESS_WIDTH].com EMail:cadserv21@hotmail.if tort to your rights.cadfamily. id[AXI_MAX_ID_WIDTH] write_channel_cycle write_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. and only one can be active at a time. id[AXI_MAX_ID_WIDTH] write_resp_channel_cycle write_resp_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. Each write_channel_cycle groups the set of write channel signals (for data/strobe) and synchronizes them to a clock. burst. Attributes: T_AXI_VALID T_AXI_LAST bit bit bit valid.please inform us. size. length[4]. cache. the number of which is determined by BREADY. Attributes: T_AXI_VALID bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit valid. This item synchronizes the ARREADY signal to the clock. lock. One or more write_channel_cycles make up a write_channel_phase. Attributes: T_AXI_VALID T_AXI_RESPONSE bit valid. id[AXI_MAX_ID_WIDTH] read_addr_channel_ready This item lasts a single clock cycle on the bus. Each write_resp_channel_cycle groups the set of write response channel signals and synchronizes them to a clock. strb[AXI_MAX_WSTRB_WIDTH].we will delete . the number of which is determined by WREADY. last. with only one active at a time.com 124 The document is for study only.nTX User’s Guide and Tutorial One or more write_addr_channel_cycles make up a write_addr_channel_phase. prot. with only one active at a time. the number of which is determined by AWREADY. data[AXI_MAX_WDATA_WIDTH].

see the section on Signal Descriptions in the AMBA AXI Protocol Specification. Name ACLK ARESETn ARVALID ARADDR Type bit bit bit Direction clock_source to master.cadfamily. size AXI_ADDRESS_WIDTH master to slave www. and only one can be active at a time.we will delete . slave and reset_source reset_source to master and slave master to slave bit array.if tort to your rights. This item synchronizes the WREADY signal to the clock. Attributes: T_AXI_READY ready write_channel_ready This item lasts a single clock cycle on the bus.Appendix D: AMBA AXI Transactor T_AXI_READY ready read_channel_ready This item lasts a single clock cycle on the bus.please inform us. This item synchronizes the RREADY signal to the clock. Attributes: T_AXI_READY ready Wires For a description of each of these wires (signals). This item synchronizes the BREADY signal to the clock. Attributes: T_AXI_READY ready write_addr_channel_ready This item lasts a single clock cycle on the bus. This item synchronizes the AWREADY signal to the clock.com 125 The document is for study only. and only one can be active at a time.com EMail:cadserv21@hotmail. and only one can be active at a time. Attributes: T_AXI_READY ready write_resp_channel_ready This item lasts a single clock cycle on the bus. and only one can be active at a time.

size 2 bit array. size AXI_ADDRESS_WIDTH master to slave AWCACHE bit array.we will delete .cadfamily. size AXI_RDATA_WIDTH bit array.nTX User’s Guide and Tutorial Name ARLEN ARSIZE ARBURST ARLOCK ARCACHE ARPROT ARID ARREADY AWVALID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWPROT AWID RVALID RLAST RDATA RRESP RID RREADY WVALID WLAST WDATA WSTRB WID WREADY BVALID BRESP Type bit array. size 2 bit array. size 3 bit array. size AXI_ID_WIDTH bit bit bit array. size AXI_WDATA_WIDTH bit array. size 2 bit array. size 4 bit array. size AXI_WSTRB_WIDTH bit array. size 4 bit array. size 2 bit array. size 3 bit array.please inform us.if tort to your rights. size AXI_ID_WIDTH bit bit bit array. size 4 bit array. size 2 bit array. size 3 bit array. size AXI_ID_WIDTH bit bit bit bit array. size 4 AWREADY bit www. size 3 bit array.com 126 The document is for study only.com EMail:cadserv21@hotmail. size 2 Direction master to slave master to slave master to slave master to slave master to slave master to slave master to slave slave to master master to slave master to slave master to slave master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master slave to master slave to master slave to master master to slave master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master bit array. size AXI_ID_WIDTH bit bit bit array.

com 127 The document is for study only. write_addr_channel_cycle_invalid. read_channel_cycle.Appendix D: AMBA AXI Transactor Name BID BREADY Type bit array.please inform us. with the exception that they represent cycles where the valid signal is low. read_channel_cycle_invalid. // Word size encoding type enum T_AXI_SIZE:3 { BYTES_1 = 0. the AXI transactor makes use of the following types: // Validity of a channels signals type enum T_AXI_VALID:1 { INVALID = 0. such as ‘int’. write_channel_cycle and write_resp_channel_cycle. BYTES_2 = 1.we will delete . write_addr_channel_cycle.if tort to your rights. VALID = 1 }. size AXI_ID_WIDTH bit Direction slave to master master to slave Additional Communication Items Additional items read_addr_channel_cycle_invalid. write_channel_cycle_invalid and write_resp_channel_cycle_invalid are also available. LAST = 1 }.cadfamily. and ‘bit’. Additional Information Data Types In addition to the standard transactor types. // Last phase in burst transfer type enum T_AXI_LAST:1 { MORE_TO_COME = 0.com EMail:cadserv21@hotmail. These are identical to the read_addr_channel_cycle. www. BYTES_4 = 2.

WRAP = 2. PRIV_SEC_INST = 5. PRIV_SEC_DATA = 1. BYTES_32 = 5.cadfamily. CACHE_WBACK_ALLOC_W_ONLY = 11.please inform us. NORM_NONSEC_INST = PRIV_NONSEC_INST = }. // Protection type type enum T_AXI_PROT:3 { NORM_SEC_DATA = 0. RESERVED = 3 }.nTX User’s Guide and Tutorial BYTES_8 = 3. CACHE_WBACK_ALLOC_RW = 15 }. BYTES_16 = 4. NORM_NONSEC_DATA = PRIV_NONSEC_DATA = NORM_SEC_INST = 4. CACHE_WTHROUGH_ALLOC_RW = 14. // Burst type . RESERVED_1100 = 12. CACHE_NOALLOC = 2. 3. www. CACHE_WTHROUGH_ALLOC_R_ONLY = 6. CACHE_WTHROUGH_ALLOC_W_ONLY = 10. RESERVED_1001 = 9.we will delete .if tort to your rights. RESERVED_0101 = 5. RESERVED_1000 = 8. 2.determines address calculation type enum T_AXI_BURST:2 { FIXED = 0. BYTES_64 = 6. 7 // Cache type type enum T_AXI_CACHE:4 { NONCACHE_NONBUF = 0. CACHE_WBACK_ALLOC_R_ONLY = 7. BUF_ONLY = 1.com EMail:cadserv21@hotmail.com 128 The document is for study only. RESERVED_0100 = 4. 6. BYTES_128 = 7 }. INCR = 1. CACHE_BUF_NOALLOC = 3. RESERVED_1101 = 13.

// Lock type for atomic accesses type enum T_AXI_LOCK:2 { NORMAL = 0.please inform us. RESERVED = 3 }. DECERR = 3 }.cadfamily. Transactor Constants • • • • • • • • AXI_MAX_ADDRESS_WIDTH – the maximum width of the address bus (read and write) AXI_MAX_ID_WIDTH – the maximum width of the id bus (read and write) AXI_MAX_RDATA_WIDTH – the maximum width of the read data bus AXI_MAX_WDATA_WIDTH – the maximum width of the write data bus AXI_MAX_WSTRB_WIDTH – the maximum width of the write strobe bus AXI_MAX_RDATA_LENGTH – the maximum number of bytes in an AXI_read transfer AXI_MAX_WDATA_LENGTH – the maximum number of bytes in an AXI_write transfer AXI_MAX_BURST_LENGTH – the maximum number of words in a burst www.com 129 The document is for study only. LOCKED = 2.we will delete . // Ready signal values type enum T_AXI_READY:1 { WAIT = 0.if tort to your rights. EXOKAY = 1.com EMail:cadserv21@hotmail. EXCLUSIVE = 1. SLVERR = 2. READY = 1 }.Appendix D: AMBA AXI Transactor // Response type type enum T_AXI_RESPONSE:2 { OKAY = 0.

com 130 The document is for study only.if tort to your rights.com EMail:cadserv21@hotmail.cadfamily.please inform us.nTX User’s Guide and Tutorial www.we will delete .

Optional Adaptation Field. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. Name The bus declaration (nte_MPEG_TS_v1p0_ns) must be one of the supported transactors. MAPPING_ROOT = "/MPEG_TS_top_level/MPEG_structure/the_transport_stream".com EMail:cadserv21@hotmail.com 131 The document is for study only.if tort to your rights. www.Appendix E: MPEG2_TS Transactor Appendix E: MPEG2_TS Transactor Overview The MPEG_TS Transactor supports the following features: • • • • ISO/IEC 13818-1:2000 Audio/Video qualifier. nte_MPEG2_TS_v1p0_ns MyMPEG2_TS_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.we will delete . Byte-wide data bus. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.please inform us.cadfamily.

"/MPEG2_TS_data". = "/MPEG2_TS_audio_video". The available parameters are: clk_init_value: The initial value of the clock (0 or 1). The clock set up is important to the correct operation of the transactor. however. If this is done they will be assigned a default value (normally 0).please inform us. "/MPEG2_TS_valid". • setup_time: The setup time for all MPEG2 TS signals.com 132 The document is for study only. The transactor signals are pre-defined as shown in the file below and must not be changed. sync_byte: Defaults to 0x47. The SIGMAP code example is for an unmapped clock. clk_1st_time: The relative time of the first clock change after the initial phase shift change. An example is shown below: • • • • Figure: Clock Setup www.com EMail:cadserv21@hotmail. it is possible to leave signals unconnected by removing them from the sigmap section. Configuration of the transactor is made via the PARAMETER section of the bcf file. • clk_2nd_time: The relative time of second clock change after the previous change.cadfamily. clk_phase_shift: The time of the first transition from the initial value. • hold_time: The hold time for all MPEG2 TS signals.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. SIGMAP { /MPEG2_TS/MPEG2_TS_sync = /MPEG2_TS/MPEG2_TS_audio_video /MPEG2_TS/MPEG2_TS_valid = /MPEG2_TS/MPEG2_TS_data = } "/MPEG2_TS_sync".we will delete . NOTE: Clock can be mapped to /MPEG2_TS/MPEG2_TS_clock.if tort to your rights. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file.

50 ns. optional_fields_phase and payload_phase. This does not have to match the time scale of the input FSDB file. 1 ns. ‘ns’. e. where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘tu’ – time unit (‘ps’. 0x47. www. The naming convention used is nte_MPEG2_TS_‘ver’_‘tu’. 50 ns. The MPEG2_TS Transactor recognizes transactions from the transport stream active signals. types and attributes of these transactions are described in detail.we will delete . adaptation_header_phase. At the highest level is a transaction (stream_packet_phase) representing a complete MPEG2 packet. 50 ns. any signal changes below this time resolution will not be seen by nTE.g. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction.com EMail:cadserv21@hotmail.please inform us. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. ‘fs’). This transaction is then made up of phases.cadfamily. In this section the function.Appendix E: MPEG2_TS Transactor // parameters PARAMETER { clk_init_value sync_byte clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time } = = = = = = = 0b0. sync_phase.if tort to your rights. If the clock is mapped then clk_* parameters do not need to be set. 1 ns. The protocol tree shows how the transactions are inter-related.com 133 The document is for study only. header_phase. NOTE: PARAMETER code example is for an unmapped clock. however. Transactor Configurations A number of transactor configurations are available.

please inform us.we will delete .com 134 The document is for study only.com EMail:cadserv21@hotmail.cadfamily.if tort to your rights.nTX User’s Guide and Tutorial Protocol Tree www.

Attributes: bit bit ts_adaptation_header_length[8].we will delete . ts_adaptation_field.com 135 The document is for study only. ts_identifier[13]. ts_payload_flag.if tort to your rights. byte transport_packet_payload[] sync_phase sync_phase is a uni-directional transaction used to indicate the start of a packet and to transfer the sync byte 0x47. ts_continuity[4] adaptation_header_phase adaptation_header_phase is a uni-directional transaction used to transfer the adaptation field. www.Appendix E: MPEG2_TS Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. header_phase header_phase is a uni-directional transaction used to transfer the 4-byte header. ts_adaptation_header_flags[8]. Attributes: bit bit bit bit bit bit bit bit ts_error_indicator. to the unit (or units) to the right of the symbol.please inform us.cadfamily. ts_start_indicator. ts_priority. Attributes: T_MPEG_TS_transport_packet_header transport_packet_header. T_MPEG_TS_transport_adaptation_header transport_adaptation_header. stream_packet_phase stream_packet_phase is a uni-directional transaction used for complete transport packet transfers. Attributes: none.com EMail:cadserv21@hotmail. from the unit to the left of the symbol. ts_scrambling[2]. byte transport_optional_fields[].

Attributes: bit av www.com EMail:cadserv21@hotmail. Attributes: bit av MUX_S >=> master stream_valid_byte stream_valid_byte is a uni-directional transaction used to transfer a valid byte.if tort to your rights. Attributes: bit bit bit sync.nTX User’s Guide and Tutorial optional_fields_phase optional_fields_phase is a uni-directional transaction used a to transfer optional fields.we will delete . Attributes: byte data[] stream_av_phase stream_av_phase is a uni-directional transaction used to transfer the phase. Attributes: byte data[] payload_phase payload_phase is a uni-directional transaction used to transfer the packet payload. data[8] stream_packet_stripe stream_packet_stripe is a uni-directional transaction used to transfer a packet.cadfamily.please inform us. Attributes: bit bit sync. data[8] stream_packet_av_stripe stream_packet_av_stripe is a uni-directional transaction used to indicate an audio or video packet. valid.com 136 The document is for study only.

if tort to your rights. Name MPEG_TS_clock MPEG_TS_sync MPEG_TS_audio_video MPEG_TS_valid MPEG_TS_data[8] Type bit bit bit bit bit array. size 8 Direction source >=> destination source >=> destination source >=> destination source >=> destination source >=> destination www.com EMail:cadserv21@hotmail.please inform us. see the section on Signal Descriptions in the MPEG2_TS Protocol Specification.com 137 The document is for study only.cadfamily.Appendix E: MPEG2_TS Transactor Wires For a description of each of these wires (signals).we will delete .

such as ‘int’.com EMail:cadserv21@hotmail.cadfamily. the MPEG2 TS transactor makes use of the following types: type struct T_MPEG_TS_transport_packet_header { bit transport_error_indicator. }. bit }. bit adaptation_flags[8].nTX User’s Guide and Tutorial Additional Information Data Types In addition to the standard transactor types. type struct T_MPEG_TS_transport_adaptation_header { bit adaptation_field_length[8].we will delete . and ‘bit’.com 138 The document is for study only. packet_identifier[13]. bit adaptation_field_flag.please inform us. www. //PUSI start of PES //in the packet transport_priority.if tort to your rights. //EI indicates error //from previous stages bit payload_unit_start_indicator. //Presence of adaptation //field in packet //Presence of payload //data in the packet //Between truncated PES //portions bit payload_flag. //Priority indicator //Identifies the content //of the packet //Transport //scrambling type bit bit bit transport_scrambling_flags[2]. continuity_counter[4].

please inform us.if tort to your rights.0 (see Limitations below) Configurable bus widths (address.cadfamily.com 139 The document is for study only. Name The bus declaration (nte_OCP_IP_v1p0_32_32_16_8_ns) must be one of the supported transactors. However the following limitations exist with the current version: • • • OCP ordering model currently unsupported for transactions on same thread. BurstPrecise = 0 not supported. etc.) Recognition of complete bursts as a single transaction Out-of-order transaction completion Limitations Over 90% of the OCP-IP 2.we will delete .Appendix F: OCP-IP Transactor Appendix F: OCP-IP Transactor Overview The OCP-IP Transactor supports the following features: • • • • OCP-IP Release 2.0 specification is covered by the OCP transactor. data.com EMail:cadserv21@hotmail. thread ID. nte_OCP_IP_v1p0_32_32_16_8_ns myOCP { www. Incomplete support for sideband/test signals BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.

www. "/MCmd". however. "/SRespInfo". it is possible to leave signals unconnected by removing them from the sigmap section. The SIGMAP code example is for an unmapped clock. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. "/MBurstPrecise". "/MByteEn". "/MReqInfo". "/SResp". "/SDataAccept". "/SData".please inform us. "/MBurstSeq".if tort to your rights.nTX User’s Guide and Tutorial Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.we will delete . MAPPING_ROOT = "/default_config_recognition/str/iOCP". "/SCmdAccept". "/MDataInfo". "/MDataValid".com EMail:cadserv21@hotmail. = = = = = = = "/MAtomicLength". "/MReqLast". "/MData". "/SDataInfo". "/MBurstSingleReq". "/MDataLast". SIGMAP { // basic OCP signals /OCP/MAddr /OCP/MCmd /OCP/MData /OCP/MDataValid /OCP/MRespAccept /OCP/SCmdAccept /OCP/SData /OCP/SDataAccept /OCP/SResp = = = = = = = = = "/MAddr". // simple OCP extensions /OCP/MAddrSpace = /OCP/MByteEn = /OCP/MDataByteEn = /OCP/MDataInfo = /OCP/MReqInfo = /OCP/SDataInfo = /OCP/SRespInfo = // OCP burst extensions /OCP/MAtomicLength /OCP/MBurstLength /OCP/MBurstPrecise /OCP/MBurstSeq /OCP/MBurstSingleReq /OCP/MDataLast /OCP/MReqLast "/MAddrSpace".com 140 The document is for study only. Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. "/MRespAccept".cadfamily. NOTE: Clock can be mapped to /OCP/Clk. If this is done they will be assigned a default value (normally 0). "/MDataByteEn". "/MBurstLength". The transactor signals are pre-defined as shown in the file below and must not be changed.

"/Scanout".cadfamily.Appendix F: OCP-IP Transactor /OCP/SRespLast = "/SRespLast". "/MDataThreadID". // sideband OCP signals /OCP/MError = "/MError". Configuration of the transactor is made via the PARAMETER section of the bcf file. "/SThreadID". "/TDI". "/StatusBusy".com EMail:cadserv21@hotmail. = = = = = = = = = = "/Scanctrl". "/ControlWr". "/StatusRd". These can be seen in the example below using values as allowed by the OCP specification. The available parameters are: www. "/TDO". "/Status". "/TRST_N". "/SThreadBusy". /OCP/MReset_n = "/MReset_n". "/TCK". This is where the OCP configuration and the default values of the OCP wires must be set. "/SDataThreadBusy".we will delete . "/MThreadID".if tort to your rights. "/Scanin". "/ClkByp". Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. "/ControlBusy". /OCP/MFlag = "/MFlag".please inform us. // OCP thread extensions /OCP/MConnID = /OCP/MDataThreadID = /OCP/MThreadBusy = /OCP/MThreadID = /OCP/SDataThreadBusy = /OCP/SThreadBusy = /OCP/SThreadID = "/MConnID". /OCP/SError = "/SError". /OCP/SFlag = "/SFlag". "/TestClk". "/MThreadBusy". /OCP/SReset_n = "/SReset_n". /OCP/SInterrupt = "/SInterrupt". "/TMS".com 141 The document is for study only. /OCP/Control /OCP/ControlBusy /OCP/ControlWr /OCP/Status /OCP/StatusBusy /OCP/StatusRd // test OCP signals /OCP/Scanctrl /OCP/Scanin /OCP/Scanout /OCP/ClkByp /OCP/TestClk /OCP/TCK /OCP/TDI /OCP/TDO /OCP/TMS /OCP/TRST_N } = = = = = = "/Control".

cadfamily. 1. 1. 0. 0. 0. = 0. 0. An example is shown below: • • • Figure: Clock Setup // parameters PARAMETER { //Protocol broadcast_enable burst_aligned burstseq_dflt1_enable burstseq_dflt2_enable burstseq_incr_enable burstseq_strm_enable burstseq_unkn_enable burstseq_wrap_enable burstseq_xor_enable endian force_aligned mthreadbusy_exact rdlwrc_enable read_enable readex_enable sdatathreadbusy_exact sthreadbusy_exact write_enable writenonpost_enable //Phase datahandshake reqdata_together writeresp_enable //Signal (Dataflow) addr addr_wdth addrspace = = = = = = = = = = = = = = = = = = = 0. 0. 0. = 32. 1.if tort to your rights. 0. • clk_2nd_time: The relative time of second clock change after the previous change. 0. 0. = 0. 0. www. 0. = 1.we will delete . clk_1st_time: The relative time of the first clock change after the initial phase shift change. = 0. 0. • setup_time: The setup time for all OCP signals • hold_time: The hold time for all OCP signals The clock set up is important to the correct operation of the transactor.nTX User’s Guide and Tutorial clk_init_value: The initial value of the clock (0 or 1). 0. LITTLE. = 0. 0.com 142 The document is for study only.com EMail:cadserv21@hotmail.please inform us. clk_phase_shift: The time of the first transition from the initial value.

0. 2.if tort to your rights. 1.com EMail:cadserv21@hotmail. 0. 2.com 143 The document is for study only. 0. 0. 0. www. 2. 0.please inform us.cadfamily. 0. 0. 0. 32. 0. 1. 2. 0. = 0. 0. 4. 0. 0. 2. = 0. 1. 0. 0. 0. 1. 0. 0. 1. 0. 8. 0. 2. 0. 0. 2. 0. 0. 0. 1. 2. 8. 0. = 0. 0. 0.Appendix F: OCP-IP Transactor addrspace_wdth atomiclength atomiclength_wdth burstlength burstlength_wdth burstprecise burstseq burstsinglereq byteen cmdaccept connid connid_wdth dataaccept datalast data_wdth mdata mdatabyteen mdatainfo mdatainfo_wdth mdatainfobyte_wdth mthreadbusy reqinfo reqinfo_wdth reqlast resp respaccept respinfo respinfo_wdth resplast sdata sdatainfo sdatainfo_wdth sdatainfobyte_wdth sdatathreadbusy sthreadbusy threads //Signal (Sideband) control controlbusy control_wdth controlwr interrupt merror mflag mflag_wdth mreset serror sflag sflag_wdth sreset status statusbusy statusrd status_wdth //Signal (Test) clkctrl_enable jtag_enable jtagtrst_enable = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 2. 0. 1. 0. 0. 0.we will delete .

0. 0. 0. = 2. 0. 0.com EMail:cadserv21@hotmail. 1.nTX User’s Guide and Tutorial scanctrl_wdth scanport scanport_wdth // basic OCP signals default_Clk default_MAddr default_MCmd default_Mdata default_MdataValid default_MrespAccept default_ScmdAccept default_Sdata default_SdataAccept default_Sresp = 2. // simple OCP extensions default_MaddrSpace = default_MbyteEn = default_MdataByteEn = default_MdataInfo = default_MreqInfo = default_SdataInfo = default_SrespInfo = // OCP burst extensions default_MatomicLength default_MburstLength default_MburstPrecise default_MburstSeq default_MburstSingleReq default_MdataLast default_MreqLast default_SrespLast = = = = = = = = // OCP thread extensions default_MconnID = default_MdataThreadID = default_MthreadBusy = default_MthreadID = default_SdataThreadBusy = default_SthreadBusy = default_SthreadID = // sideband OCP signals default_Merror default_Mflag default_MReset_n default_Serror default_Sflag default_Sinterrupt default_SReset_n default_Control default_ControlBusy default_ControlWr default_Status default_StatusBusy default_StatusRd = = = = = = = = = = = = = www. 0. 0. 0. 0. 0. 1. 0. 0. 1. 0. 0. 0. 1. 0. 0. 0. 0xF.we will delete . 0. 0. 0. 0. 0. 0.if tort to your rights. 0xF. 1. 0. 0.please inform us.cadfamily. 1.com 144 The document is for study only. = 0. 0. = = = = = = = = = = 0. 0. 0. 0. 0. 1. 0. 1. 0. 0.

0. ‘aw’. } NOTE: PARAMETER code example is for an unmapped clock. 0. Transactor Configurations A number of transactor configurations are available. 128. 0. This does not have to match the time scale of the input FSDB file. When the required configuration is not available. 1 ns. The naming convention used is nte_OCP_IP_‘ver’_‘aw’_‘dw’_‘threads’_‘blw’_‘tu’ where ‘ver’. 0. 256) ‘threads’ – number of threads (16) ‘blw’ – burst length width (8) ‘tu’ – time unit (‘ps’.we will delete .if tort to your rights. If the clock is mapped then clk_* parameters do not need to be set. 5 ns. an transactor with bus widths greater than those required should be used. ‘ns’. 64. These and other run-time parameters must be configured using the PARAMETER section of the bcf file. 5 ns. 1. ‘blw’ and ‘tu’ have the following meanings and valid values: ‘ver’ – version (‘v1p0’) ‘aw’ – address width (32) ‘dw’ – data width (16. 0.com EMail:cadserv21@hotmail.com 145 The document is for study only. ‘dw’. 0 ns.please inform us. ‘fs’). 0. however. any signal changes below this time resolution will not be seen by nTE. 0. • • • • • • www. 0. 32.Appendix F: OCP-IP Transactor // test OCP signals default_Scanctrl default_Scanin default_Scanout default_ClkByp default_TestClk default_TCK default_TDI default_TDO default_TMS default_TRST_N // clock frequency clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time = = = = = = = = = = = = = = = = 0. ‘threads’.cadfamily. 1 ns. 0.

com EMail:cadserv21@hotmail. www. In this section the function.if tort to your rights.we will delete .nTX User’s Guide and Tutorial Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction.com 146 The document is for study only. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. types and attributes of these transactions are described in detail.cadfamily.please inform us.

we will delete .com EMail:cadserv21@hotmail.please inform us.cadfamily.com 147 The document is for study only.if tort to your rights.Appendix F: OCP-IP Transactor Protocol Tree www.

please inform us. NOTE: The size of a number of the attributes is dependant on the transactor Readburst Readburst is a bidirectional read transaction between the master and slave. There can be multiple outstanding (concurrent) reads.com 148 The document is for study only. One or more Mrequest_phase transactions pass address and control information from the master to the slave.we will delete .if tort to your rights. If datahandshake is enabled then a Writeburst is made up of one or more www. configuration in use. Attributes: MCmd_encoding Rcmd master >=> slave bit Addr[(1<<OCP_burstlength_wdth)-1][OCP_addr_wdth] master >=> slave bit AddrSpace[OCP_addrspace_wdth] master >=> slave bit ReqInfo[OCP_reqinfo_wdth] master >=> slave bit BurstLength[OCP_burstlength_wdth] master >=> slave bit BurstPrecise master >=> slave MBurstSeq_encoding BurstSeq master >=> slave bit BurstSingleReq master >=> slave bit AtomicLength[OCP_atomiclength_wdth] master >=> slave bit ConnID[OCP_connid_wdth] master >=> slave bit ThreadID[OCP_log2_threads] master >=> slave bit ByteEnable[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth/8] master >=> slave bit Data[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth] slave >=> master bit DataInfo[(1<<OCP_burstlength_wdth)-1][OCP_sdatainfo_wdth] slave >=> master SResp_encoding Resp[(1<<OCP_burstlength_wdth)-1] slave >=> master bit RespInfo[OCP_respinfo_wdth] slave >=> master Writeburst Writeburst is a (possibly) bidrectional write transaction between the master and slave. from the unit to the left of the symbol.com EMail:cadserv21@hotmail. to the unit (or units) to the right of the symbol. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants).nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. One or more Sresponse_phase transactions return the requested data and response status from slave to master. These can overlap due to pipe-lining and the use of the ThreadID signal.cadfamily. with write data (and length) expressed in words of size equal to the bus width.

www. Addr[OCP_addr_wdth]. It consists of one or more Mrequest transactions. if writeresp_enable is set.Appendix F: OCP-IP Transactor Mrequest_phase transactions. one or more Sresponse_phase transactions. Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit Cmd. There can be multiple outstanding (concurrent) writes. but only one may be active at any time. If datahandshake is not enabled then a Writeburst is made up of one or more MrequestData_phase transactions and. BurstSingleReq. These can overlap due to pipe-lining and the use of the ThreadID signal.com 149 The document is for study only.if tort to your rights.com EMail:cadserv21@hotmail. AddrSpace[OCP_addrspace_wdth]. Attributes: MCmd_encoding Wcmd master >=> slave bit Addr[(1<<OCP_burstlength_wdth)-1][OCP_addr_wdth] master >=> slave bit AddrSpace[OCP_addrspace_wdth] master >=> slave bit ReqInfo[OCP_reqinfo_wdth] master >=> slave bit BurstLength[OCP_burstlength_wdth] master >=> slave bit BurstPrecise master >=> slave MBurstSeq_encoding BurstSeq master >=> slave bit BurstSingleReq master >=> slave bit AtomicLength[OCP_atomiclength_wdth] master >=> slave bit ConnID[OCP_connid_wdth] master >=> slave bit ThreadID[OCP_log2_threads] master >=> slave bit ByteEnable[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth/8] master >=> slave bit Data[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth] master >=> slave bit DataInfo[(1<<OCP_burstlength_wdth)-1][OCP_sdatainfo_wdth] master >=> slave SResp_encoding Resp[(1<<OCP_burstlength_wdth)-1] slave >=> master bit RespInfo[OCP_respinfo_wdth] slave >=> master Mrequest_phase Mrequest_phase is a unidirectional transaction passing address and control information from master to slave as part of a Readburst or Writeburst transaction. A Mrequest_phase transaction may take multiple clock cycles to complete. if writeresp_enable is set. BurstPrecise. one or more MwriteData_phase transactions and.we will delete .please inform us. ReqInfo[OCP_reqinfo_wdth]. BurstLength[OCP_burstlength_wdth]. BurstSeq.cadfamily. one or more Sresponse_phase transactions.

BurstSingleReq.com 150 The document is for study only. Data[OCP_data_wdth]. DataByteEn[OCP_data_wdth/8]. but only one may be active at any time. A MrequestData_phase transaction may take multiple clock cycles to complete. It consists of one or more MrequestData transactions.com EMail:cadserv21@hotmail. A MwriteData_phase transaction may take multiple clock cycles to complete. AtomicLength[OCP_atomiclength_wdth]. Data[OCP_data_wdth]. Attributes: bit bit bit bit bit ThreadID[OCP_log2_threads]. ConnID[OCP_connid_wdth]. ReqLast MrequestData_phase MrequestData_phase is a unidirectional transaction passing control and data information from master to slave as part of a Writeburst transaction.nTX User’s Guide and Tutorial bit bit bit bit bit AtomicLength[OCP_atomiclength_wdth]. ThreadID[OCP_log2_threads]. ByteEnable[OCP_data_wdth/8]. Addr[OCP_addr_wdth]. AddrSpace[OCP_addrspace_wdth]. Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit bit bit bit bit bit bit bit Cmd.please inform us. It consists of one or more MwriteData transactions. DataInfo[OCP_sdatainfo_wdth] MwriteData_phase MwriteData_phase is a unidirectional transaction passing data from master to slave as part of a Writeburst transaction. but only one may be active at any time. BurstLength[OCP_burstlength_wdth]. DataLast www. ConnID[OCP_connid_wdth]. BurstSeq. ReqLast.we will delete . BurstPrecise. ThreadID[OCP_log2_threads]. DataInfo[OCP_mdatainfo_wdth].cadfamily. ReqInfo[OCP_reqinfo_wdth]. ByteEnable[OCP_data_wdth/8].if tort to your rights.

Attributes: MCmd_encoding bit bit Cmd. It takes a single clock cycle to complete and only one may be active at any time.com EMail:cadserv21@hotmail. RespInfo[OCP_respinfo_wdth]. RespLast Mrequest Mrequest is a unidirectional transaction passing address and control information from master to slave as part of a Mrequest_phase transaction. BurstLength[OCP_burstlength_wdth]. Resp. BurstPrecise. ReqInfo[OCP_reqinfo_wdth]. ConnID[OCP_connid_wdth].if tort to your rights. BurstSeq. It takes a single clock cycle to complete and only one may be active at any time. AddrSpace[OCP_addrspace_wdth]. Data[OCP_data_wdth]. but only one may be active at any time.please inform us. It consists of one or more Sresponse transactions. Addr[OCP_addr_wdth]. Attributes: bit bit bit SResp_encoding bit bit ThreadID[OCP_log2_threads].we will delete . AtomicLength[OCP_atomiclength_wdth].com 151 The document is for study only. Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit bit bit bit bit bit Cmd. ByteEnable[OCP_data_wdth/8]. Addr[OCP_addr_wdth]. ReqLast MrequestData MrequestData is a unidirectional transaction passing address and control and write data information from master to slave as part of a MrequestData_phase transaction. ThreadID[OCP_log2_threads].Appendix F: OCP-IP Transactor Sresponse_phase Sresponse_phase is a unidirectional transaction passing read data and read/write status information from slave to master as part of a Readburst or Writeburst transaction. AddrSpace[OCP_addrspace_wdth].cadfamily. www. DataInfo[OCP_sdatainfo_wdth]. BurstSingleReq. A Sresponse_phase transaction may take multiple clock cycles to complete.

Attributes: bit bit bit bit bit ThreadID[OCP_log2_threads]. Name Clk Type bit Direction clock_source to master and slave www. BurstSeq. Data[OCP_data_wdth]. BurstLength[OCP_burstlength_wdth]. Data[OCP_data_wdth]. DataByteEn[OCP_data_wdth/8]. ConnID[OCP_connid_wdth].com EMail:cadserv21@hotmail. DataInfo[OCP_mdatainfo_wdth]. DataInfo[OCP_sdatainfo_wdth] MwriteData MwriteData is a unidirectional transaction passing write data information from master to slave as part of a MwriteData_phase transaction. RespInfo[OCP_respinfo_wdth]. AtomicLength[OCP_atomiclength_wdth].cadfamily. DataLast Sresponse Sresponse is a unidirectional transaction passing address and control and write data information from master to slave as part of a Sresponse_phase transaction.com 152 The document is for study only.we will delete . see the section on Signal Descriptions in the OCP-IP Protocol Specification.nTX User’s Guide and Tutorial bit bit bit MBurstSeq_encoding bit bit bit bit bit bit bit bit ReqInfo[OCP_reqinfo_wdth]. BurstPrecise.please inform us. DataInfo[OCP_sdatainfo_wdth]. It takes a single clock cycle to complete and only one may be active at any time. Attributes: bit bit bit SResp_encoding bit bit ThreadID[OCP_log2_threads]. BurstSingleReq. ReqLast. ThreadID[OCP_log2_threads]. RespLast Wires For a description of each of these wires (signals). It takes a single clock cycle to complete and only one may be active at any time.if tort to your rights. Resp. Data[OCP_data_wdth]. ByteEnable[OCP_data_wdth/8].

size OCP_threads bit array.Appendix F: OCP-IP Transactor Name MAddr MCmd MData MDataValid MRespAccept SCmdAccept SData SDataAccept SResp MAddrSpace MByteEn MDataByteEn MDataInfo MReqInfo SDataInfo SRespInfo MAtomicLength MBurstLength MBurstPrecise MBurstSeq MBurstSingleReq MDataLast MReqLast SRespLast MConnID MDataThreadID MThreadBusy MThreadID SDataThreadBusy SThreadBusy SThreadID MError Type bit array.com 153 The document is for study only. size OCP_connid_wdth bit array. size OCP_threads bit array. size OCP_addrspace_wdth bit array. size OCP_threads bit array.if tort to your rights. size OCP_burstlength_wdth master to slave master to slave master to slave master to slave master to slave master to slave slave to master master to slave master to slave master to slave master to slave slave to master slave to master slave to master master to slave www. size OCP_addr_wdth bit array. size OCP_log2_threads bit Direction master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master slave to master master to slave master to slave master to slave master to slave master to slave slave to master slave to master master to slave bit array. size OCP_data_wdth/8 bit array. size OCP_log2_threads bit array. size OCP_addr_wdth bit bit bit bit array. size OCP_log2_threads bit array. size 3 bit bit bit bit bit array. size 2 bit bit array. size OCP_atomiclength_wdth bit bit array. size 2 bit array. size OCP_data_wdth/8 bit array.cadfamily. size 3 bit array. size OCP_datainfo_wdth bit array.com EMail:cadserv21@hotmail.please inform us. size OCP_respinfo_wdth bit array. size OCP_reqinfo_wdth bit array. size OCP_sdatainfo_wdth bit array.we will delete .

size OCP_status_wdth bit bit bit array. size OCP_control_wdth bit bit bit array.we will delete .com EMail:cadserv21@hotmail. size OCP_sflag_wdth bit bit bit array.if tort to your rights.nTX User’s Guide and Tutorial Name MFlag MReset_n SError SFlag SInterrupt SReset_n Control ControlBusy ControlWr Status StatusBusy StatusRd Scanctrl Scanin Scanout ClkByp TestClk TCK TDI TDO TMS TRST_N Type bit array. size OCP_mflag_wdth bit bit bit array. size OCP_scanport_wdth bit bit bit bit bit bit bit Direction master to slave master to slave slave to master slave to master slave to master slave to master system to core core to system system to core core to system core to system system to core system to core system to core core to system system to core system to core system to core system to core core to system system to core system to core www.please inform us.cadfamily.com 154 The document is for study only. size OCP_scanport_wdth bit array. size OCP_scanport_wdth bit array.

// WriteConditional BCST = 0b111 // Broadcast }. // Read RDEX = 0b011.com 155 The document is for study only. // Unknown RSVD = 0b111 // Reserved }. // Write RD = 0b010. // WriteNonPost WRC = 0b110. // Data valid / accept FAIL = 0b10.com EMail:cadserv21@hotmail. such as ‘int’. // ReadEx RDL = 0b100. // No response DVA = 0b01. // Idle WR = 0b001.cadfamily. // Response encoding type enum SResp_encoding:2 { NULL = 0b00. // Exclusive OR STRM = 0b101. // Custom (packed) WRAP = 0b010. // core is little-endian BIG. // Burst sequence encoding type enum MBurstSeq_encoding:3 { INCR = 0b000. // ReadLinked WRNP = 0b101.we will delete .please inform us. // Request failed ERR = 0b11 // Response error }. the AXI transactor makes use of the following types: // Command encoding type enum MCmd_encoding:3 { IDLE = 0b000. // Streaming UNKN = 0b110. // core is big-endian www. type enum endian_mode // no specific coding for this in the spec { LITTLE. // Incrementing DFLT1 = 0b001.if tort to your rights.Appendix F: OCP-IP Transactor Additional Information Data Types In addition to the standard transactor types. and ‘bit’. // Wrapping DFLT2 = 0b011. // Custom (not packed) XOR = 0b100.

if tort to your rights. memories.com 156 The document is for study only. depending on its static or dynamic configuration (e. CPUs) core has no inherent endianness (e. // // // // // core can be either big or little endian.g.nTX User’s Guide and Tutorial BOTH.we will delete .please inform us.g. SThreadID and SDataThreadID www. cores that deal only in OCP words) NEUTRAL }.com EMail:cadserv21@hotmail. Transactor Constants • • • • • • • • • • • • • • • • • • • • OCP_addr_wdth – the width of the MAddr bus OCP_data_wdth – the width of the MData and SData buses OCP_addrspace_wdth – the width of the MAddrSpace bus OCP_mdatainfo_wdth – the width of the MDataInfo bus OCP_mdatainfobyte_wdth – the size of the mdatainfo byte OCP_reqinfo_wdth – the width of MReqInfo OCP_sdatainfo_wdth – the width of SDataInfo OCP_sdatainfobyte_wdth – the size of the sdatainfo byte OCP_respinfo_wdth – the width of SRespInfo OCP_atomiclength_wdth – the width of MAtomicLength OCP_burstlength_wdth – the width of MBurstLength OCP_connid_wdth – the width of MConnID OCP_mflag_wdth – the width of MFlag OCP_sflag_wdth – the width of SFlag OCP_control_wdth – the width of Control OCP_status_wdth – the width of Status OCP_scanctrl_wdth – the width of Scanctrl OCP_scanport_wdth – the width of Scanin and Scanout OCP_threads – the number of threads (width of the *ThreadBusy buses) OCP_log2_threads – the width of MThreadID.cadfamily.

com EMail:cadserv21@hotmail. www.cadfamily. Name The bus declaration (nte_PCIe_v2p0_8_ns) must be one of the supported transactors. Configurable number of lanes. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.com 157 The document is for study only. NTLP packet recognition. nte_PCIe_v2p0_8_ns my_PCIe { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.if tort to your rights.we will delete . DLLP packet recognition.Appendix G: PCI-Express (PCIe) Transactor Appendix G: PCI-Express (PCIe) Transactor Overview The PCIe Transactor supports the following features: • • • • • • PCIe specification 1. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.0a TLP packet recognition with matching completion. MAPPING_ROOT = "/tlp_dllp_idle_test2/PCI_express_structure/ PCI_Express_adaptor_I".please inform us. 'pad-or-idle' recognition.

// NB using 'D' so Differential_Wires /PCI_EXPRESS/D[0][1] = "/D[0][1]". /PCI_EXPRESS/D[1][5] = "/D[1][5]". it is possible to leave signals unconnected by removing them from the sigmap section.com EMail:cadserv21@hotmail. /PCI_EXPRESS/D[0][4] = "/D[0][4]". /PCI_EXPRESS/D[1][0] = "/D[1][0]". however. /PCI_EXPRESS/D[1][2] = "/D[1][2]".com 158 The document is for study only. or single ended signals. Example using differential pairs: SIGMAP { /PCI_EXPRESS/D[0][0] = "/D[0][0]".cadfamily. /PCI_EXPRESS/D[1][3] = "/D[1][3]". and must be set correctly. of which only one should be used. /PCI_EXPRESS/D[0][6] = "/D[0][6]". The parameter 'Differential_Wires' is used to indicate which set of signals transactions should be extracted from. // must be set 'true' /PCI_EXPRESS/D[0][2] = "/D[0][2]". www. depending on whether you are mapping to differential pairs. /PCI_EXPRESS/D[1][7] = "/D[1][7]". The transactor signals are pre-defined as shown in the file below and must not be changed. /PCI_EXPRESS/D[1][1] = "/D[1][1]".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. /PCI_EXPRESS/D[0][5] = "/D[0][5]". /PCI_EXPRESS/D[1][4] = "/D[1][4]". The following examples are for an 8 lane transactor. // must be set 'false' /PCI_EXPRESS/SingleD[0][2] = "/SingleD[0][2]".if tort to your rights.we will delete . If this is done they will be assigned a default value (normally 0). PCI Express has two sets of signals. NOTE: Clock can be mapped to /PCI_EXPRESS/PCLK0 and /PCI_EXPRESS/ PCLK1. // NB using 'SingleD' so Differential_Wires /PCI_EXPRESS/SingleD[0][1] = "/SingleD[0][1]". The SIGMAP code examples are for an unmapped clocks. /PCI_EXPRESS/D[1][6] = "/D[1][6]". /PCI_EXPRESS/D[0][3] = "/D[0][3]". /PCI_EXPRESS/D[0][7] = "/D[0][7]". } Example using single ended signals: SIGMAP { /PCI_EXPRESS/SingleD[0][0] = "/SingleD[0][0]".please inform us. signals must be removed or added for transactors with a fewer or greater number of lanes.

"/SingleD[1][3]".please inform us.cadfamily. "/SingleD[1][4]". clk_1st_time_1: The relative time of the first clock change after the initial phase shift change for end 1. "/SingleD[1][6]". Use_request_complete: Use the TLP_request_complete transaction to link TLP requests with their completions (true or false). clk_init_value_1: The initial value of the clock for end 1 (0 or 1). "/SingleD[1][5]". the 'SingleD' signals should be mapped. clk_init_value_0: The initial value of the clock for end 0 (0 or 1). The available parameters are: • • • • • • • • • • PCI_Exp_Lanes: The number of lanes.com EMail:cadserv21@hotmail. then each of the 'D' signals should be mapped. If this is set to true.if tort to your rights. "/SingleD[1][2]". "/SingleD[0][7]". or single ended signals for each lane (true or false). Configuration of the transactor is made via the PARAMETER section of the bcf file. "/SingleD[1][1]". "/SingleD[0][4]". clk_phase_shift_1: The time of the first transition from the initial value for end 1. "/SingleD[1][7]". "/SingleD[1][0]". clk_phase_shift_0: The time of the first transition from the initial value for end 0. Must be less than or equal to the maximum allowed by the specific transactor specified.com 159 The document is for study only. clk_2nd_time_1: The relative time of second clock change after the previous change for end 1. "/SingleD[0][5]". Differential_Wires: Use differential pairs. clk_1st_time_0: The relative time of the first clock change after the initial phase shift change for end 0.we will delete . "/SingleD[0][6]". otherwise. It may be • www. clk_2nd_time_0: The relative time of second clock change after the previous change for end 0. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file.Appendix G: PCI-Express (PCIe) Transactor /PCI_EXPRESS/SingleD[0][3] /PCI_EXPRESS/SingleD[0][4] /PCI_EXPRESS/SingleD[0][5] /PCI_EXPRESS/SingleD[0][6] /PCI_EXPRESS/SingleD[0][7] /PCI_EXPRESS/SingleD[1][0] /PCI_EXPRESS/SingleD[1][1] /PCI_EXPRESS/SingleD[1][2] /PCI_EXPRESS/SingleD[1][3] /PCI_EXPRESS/SingleD[1][4] /PCI_EXPRESS/SingleD[1][5] /PCI_EXPRESS/SingleD[1][6] /PCI_EXPRESS/SingleD[1][7] } = = = = = = = = = = = = = "/SingleD[0][3]".

Use_request_complete = true.cadfamily. or if the nTE is consuming too much memory during the extraction.please inform us. ‘ns’. An example is shown below: Figure: Clock Setup // parameters PARAMETER { PCI_Exp_Lanes = clk_init_value_0 = clk_init_value_1 = clk_phase_shift_0 = clk_phase_shift_1 = clk_1st_time_0 = clk_1st_time_1 = clk_2nd_time_0 = clk_2nd_time_1 = Differential_Wires } 8. This does not have to match the time scale of the input FSDB file.com 160 The document is for study only. //Use the 'D' (differential //pair) signals (true). //initial value of clock[0] 0 ns.8. //First time period of clock[1] 1 ns.32) ‘tu’ – time unit (‘ps’. //Second time period of clock[0] 1 ns. //initial value of clock[1] 1 ns. any signal changes below this time resolution will not be seen by nTE. The clock set up is important to the correct operation of the transactor.we will delete . //number of lanes 0 ns. ‘lanes’ and ‘tu’ have the following meanings and valid values: • • • ‘ver’ – version (‘v2p0’) ‘lanes’ – the maximum number of lanes. Transactor Configurations A number of transactor configurations are available.2.4. The naming convention used is nte_PCIe_‘ver’_‘lanes’_‘tu’ where ‘ver’. ‘fs’). or //'SingleD' (single bit) //signals (false).12. If the clock is mapped then clk_* parameters do not need to be set. however. //Enable (true) or disable //(false) TLP_request_complete //transactions NOTE: PARAMETER code example is for an unmapped clock. www. //Second time period of clock[1] = true.16. the PCI_Exp_Lanes parameter cannot be set greater than this value (1.com EMail:cadserv21@hotmail. //phase shift of clock[0] 1 ns. //phase shift of clock[1] 1 ns.if tort to your rights. //First time period of clock[0] 1 ns.nTX User’s Guide and Tutorial useful to turn this off if only one direction is active.

com EMail:cadserv21@hotmail.we will delete . In this section the function.please inform us.cadfamily.if tort to your rights.com 161 The document is for study only. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. Protocol Tree www.Appendix G: PCI-Express (PCIe) Transactor Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. types and attributes of these transactions are described in detail.

com EMail:cadserv21@hotmail. from the unit to the left of the symbol. TLP_request_complete TLP_request_complete is a bi-directional transaction between PCIe endpoints.if tort to your rights.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. It is defined as an array of size 2. to the unit (or units) to the right of the symbol. www.cadfamily.please inform us. Attributes: e_TLP_Basic_Types request_type End_Unit[A] >=> End_Unit[B]. one for each direction of the link.com 162 The document is for study only.we will delete .

Appendix G: PCI-Express (PCIe) Transactor e_TLP_Basic_Types complete_type End_Unit[B] >=> End_Unit[A] TLP_Packet TLP_Packet is a unidirectional transaction used for the transfer of a TLP between End Units.com 163 The document is for study only. It is defined as an array of size 2. Attributes: e_AckNak bit bool AckNak_type Sequence_Number[12] CRC_16_Error DLLP_FC_Packet DLLP_FC_Packet is a uni-directional transaction used for the transfer of a DLL flow-control packet between End Units. one for each direction of the link. Attributes: bit Sequence_Number[12] bool LCRC_Error e_TLP_detailed_Types Fmt_Type bit TC[3] bit Attr[2] bit TD bit EP bit Length[10] byte rest_of_header[12] byte data[] byte digest[4] NTLP_Packet NTLP_Packet is a uni-directional transaction used for the transfer of a Null TLP between End Units. Attributes: www.we will delete .cadfamily. It is defined as an array of size 2. It is defined as an array of size 2.com EMail:cadserv21@hotmail. one for each direction of the link. one for each direction of the link. Note that the payload is an unsized array of bytes and will be set as appropriate to the transaction. one for each direction of the link. Attributes: byte payload[] DLLP_AckNak_Packet DLLP_AckNak_Packet is a uni-directional transaction used for the transfer of a DLL ack/nack packet between End Units.if tort to your rights. It is defined as an array of size 2.please inform us.

5. It is defined as an array of size 2.nTX User’s Guide and Tutorial e_DLLP_Types e_DLLP_Msg_Subtype bit bit bit bool DLLP_Msg_Type DLLP_Msg_Subtype VC_ID[3] HdrFC[8] DataFC[12] CRC_16_Error DLLP_PM_Packet DLLP_PM_Packet is a uni-directional transaction used for the transfer of a DLL power management packet between End Units. one for each direction of the link.com EMail:cadserv21@hotmail. It is defined as an array of size 2.please inform us. one for each direction of the link. It is defined as an array of size 2.5. D21. Attributes: e_DLLP_Classes byte bool DLLP_class DLLP_payload[4] CRC_16_Error Compliance_OS Compliance_OS is a uni-directional transaction used to transfer the compliance pattern based on the sequence of 8b/10b Symbols K28. K28.5 & D10.if tort to your rights.we will delete . Attributes: Bit bool Vendor_Data[3][8] CRC_16_Error DLLP_Packet DLLP_Packet is a unidirectional transaction used for the transfer of a DLL packet between End Units.com 164 The document is for study only.cadfamily. Attributes: e_Pm bool Pm_type CRC_16_Error DLLP_Vendor_Specific_Packet DLLP_Vendor_Specific_Packet is a uni-directional transaction used for the transfer of a DLL vendor specific packet between End Units. Attributes: bool delayed www. one for each direction of the link. It is defined as an array of size 2.2 between End Units. one for each direction of the link.

link_number[8]. one for each direction of the link. Attributes: none Skp_OS Skp_OS is a uni-directional transaction used to compensate for different bit rates for two communicating Ports between End Units. Attributes: bool bit bool bit bit bit bit bit bit bit bit link_number_valid. loopback.we will delete . The attribute ‘n’ refers to the number of SKP symbols in the ordered set (1. data_rate_identifier[8].5).. lane_number_valid.if tort to your rights. one for each direction of the link. It is defined as an array of size 2. It is defined as an array of size 2. n_fts[8]. It is defined as an array of size 2.please inform us. lane_number[8]. Attributes: none Ts1_OS Ts1_OS is a uni-directional transaction used to indicate a Ts1 training sequence for initializing bit alignment. Symbol alignment and to exchange Physical Layer parameters between End Units. hot_reset. one for each direction of the link.com 165 The document is for study only. disable_link. one for each direction of the link. disable_scrambling. It is defined as an array of size 2. ts1_identifier[8] www. Attributes: word n FTS_OS FTS_OS is a uni-directional transaction used to indicate a Fast Training Sequence when moving from a L0s power-saving state to L0 normal state between End Units.Appendix G: PCI-Express (PCIe) Transactor Electrical_Idle_OS Electrical_Idle_OS is a uni-directional transaction used to indicate the state of the output drivers in which both lines of a link are driven to the DC common mode voltage.com EMail:cadserv21@hotmail.cadfamily.

It is defined as a two-dimensional array of size 2. Attributes: none www. disable_scrambling. by the number_of_lanes. lane_number[8]. Symbol alignment and to exchange Physical Layer parameters between End Units. Attributes: bool bit bool bit bit bit bit bit bit bit bit link_number_valid. loopback. disable_link. lane_number_valid.cadfamily. It is defined as an array of size 2. data_rate_identifier[8]. one for each direction of the link.com EMail:cadserv21@hotmail. one for each direction of the link.we will delete .nTX User’s Guide and Tutorial Ts2_OS Ts2_OS is a uni-directional transaction used to indicate a Ts2 training sequence for initializing bit alignment. Attributes: e_PLLP_Types byte PLLP_Type payload[] Logical_Idle_Slice Logical_Idle_Slice is a uni-directional transaction to indicate when no information (TLPs. It is defined as an array of size 2. or special Symbol) is being transmitted or received between End Units. hot_reset.please inform us. DLLPs. n_fts[8]. Attributes: none PLLP_Packet PLLP_Packet is a uni-directional transaction used to transfer a PLL packet between End Units. one for each direction of the link. ts2_identifier[8] pad_or_idle pad_or_idle is a uni-directional transaction used to transfer PAD or IDLE between End Units. one for each direction of the link. It is defined as an array of size 2. link_number[8].com 166 The document is for study only.if tort to your rights.

Attributes: bit bit Z HGFEDCBA[8] Pre_Encoded_Symbol Pre_Encoded_Symbol is a uni-directional transaction used for the transfer of preencoded symbols between End Units.please inform us. by the number_of_lanes. one for each direction of the link. Attributes: bit data_byte[8] Z_Byte Z_Byte is a uni-directional transaction used for the transfer of Special Symbols and Data Bytes.com EMail:cadserv21@hotmail. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes of duration 10*data_rate. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes.com 167 The document is for study only. Attributes: Z_HGFEDCBA e_Validity z_byte Symbol_Validity Symbol Symbol is a uni-directional transaction used for the transfer of Symbols between End Units. by the number_of_lanes.we will delete .Appendix G: PCI-Express (PCIe) Transactor Special_Symbols Special_Symbols is a uni-directional transaction used to transfer a Special Symbol between End Units. It is defined as a two-dimensional array of size 2.cadfamily. Attributes: e_Special_Symbols Special_Symbol Data_Byte Data_Byte is a uni-directional transaction used to transfer data bytes between End Units.if tort to your rights. Attributes: bit abcdeifghj[10] www. one for each direction of the link. It is defined as a two-dimensional array of size 2.

cadfamily.nTX User’s Guide and Tutorial Symbol_Bit Symbol_Bit is a uni-directional transaction used for the transfer of Symbols bits between End Units.com EMail:cadserv21@hotmail.please inform us. Name RST D Type bit [2][number_of_lanes] bit [2] Direction Support >=> End_Unit [0] and End_Unit [1] End_Unit[0] >=> End_Unit[1] and End_Unit[1] >=> End_Unit[0] End_Unit[0] >=> End_Unit[1] and End_Unit[1] >=> End_Unit[0] SingleD [2][number_of_lanes] hdl_bit www. Attributes: hdl_bit Data Wires For a complete description of the link wires refer to section 4 of the PCIeTM Base Specification. The data wires (D) are differential (implemented by the bit array bit[2]) and there are two End Units each having a number_of_lanes (implemented by [2][number_of_lanes]). It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number of lanes.The data wires SingleD are non-differential.com 168 The document is for study only.if tort to your rights. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes. Attributes: bit Differential_Data[2] Symbol_Single_Bit Symbol_Single_Bit is a uni-directional transaction used for the transfer of nondifferential Symbol bits between End Units. of duration equal to the data rate.we will delete . of duration equal to the data_rate.

MsgD = 10.com 169 The document is for study only. www. 0b00_0_1000.we will delete . CplLk = 13. Msg = 9. Reserved = 15 }. such as ‘int’. //Reserved //Reserved //Reserved //Reserved //Completion without data //Completion for Locked //Memory Read without Data //Reserved //Reserved //Reserved = 0b00_0_1100. //Configuration Read Type 1 Reserved2 Reserved3 Reserved4 Reserved5 Cpl CplLk Reserved6 Reserved7 Reserved8 = = = = = = 0b00_0_0110. 0b00_0_1001. CfgRd0 = 5. type enum e_TLP_detailed_Types:7 { MRd_32bit = 0b00_0_0000. IORd = 3.Appendix G: PCI-Express (PCIe) Transactor Additional Information Data Types In addition to the standard transactor types. and ‘bit’. CplD = 12. CfgWr1 = 8. //Configuration Read Type 0 CfgRd1 = 0b00_0_0101. Cpl = 11. CfgWr0 = 6. IOWr = 4. 0b00_0_1010. = 0b00_0_1110. the PCIe transactor makes use of the following types: type enum e_TLP_Basic_Types:4 { MRd = 0. = 0b00_0_1101. //Memory Read Request-Locked //32-bit IORd = 0b00_0_0010. //Memory Read Request 32-bit MRdLk_32bit = 0b00_0_0001.cadfamily.please inform us. MRdLk = 1. 0b00_0_0111.com EMail:cadserv21@hotmail. CplDLk = 14. MWr = 2. //IO Read Request Reserved1 = 0b00_0_0011.if tort to your rights. //Reserved CfgRd0 = 0b00_0_0100. CfgRd1 = 7. 0b00_0_1011.

//Reserved = 0b01_0_1110. MsgReserved2 = 0b01_1_0111. //Reserved = 0b01_0_1011. //Reserved = 0b01_0_1001. //Message routed to route //complex //Message routed by address //Message routed by ID //Message broadcast from //root complex //Message local . //Reserved = 0b01_0_0011. //Reserved = 0b01_0_1101. //Reserved = 0b00_1_0011. //Reserved = 0b00_1_1100. //Reserved = 0b01_0_0101. //Reserved = 0b01_0_1000. //Reserved = 0b00_1_1011. //Reserved = 0b01_0_0000. //Reserved = 0b00_1_1010. MsgBroadComp = 0b01_1_0011. //Reserved = 0b00_1_0001.cadfamily. //Reserved = 0b01_1_0000. //Reserved = 0b01_0_0110. www. //Memory Read Request 64-bit = 0b01_0_0001. //Memory Read Request-Locked //64-bit = 0b01_0_0010. //Reserved = 0b00_1_0100.if tort to your rights. //Reserved = 0b00_1_0101. = 0b01_1_0101.we will delete . //Reserved = 0b01_0_0111. MsgLocal MsgGather = 0b01_1_0100. //Reserved = 0b01_0_1111. //Reserved = 0b00_1_1000. //Reserved = 0b00_1_1101. //Reserved = 0b00_1_0010. //Reserved = 0b01_0_1010. //Reserved = 0b00_1_1001. //Reserved = 0b00_1_1111.com EMail:cadserv21@hotmail.com 170 The document is for study only. MsgReserved1 = 0b01_1_0110.nTX User’s Guide and Tutorial Reserved9 Reserved10 Reserved11 Reserved12 Reserved13 Reserved14 Reserved15 Reserved16 Reserved17 Reserved18 Reserved19 Reserved20 Reserved21 Reserved22 Reserved23 Reserved24 Reserved25 MRd_64bit MRdLk_64bit Reserved26 Reserved27 Reserved28 Reserved29 Reserved30 Reserved31 Reserved32 Reserved33 Reserved34 Reserved35 Reserved36 Reserved37 Reserved38 Reserved39 MsgRoutComp = 0b00_0_1111. MsgRoutID = 0b01_1_0010. //Reserved = 0b01_0_1100. //Reserved = 0b00_1_1110. //Reserved = 0b00_1_0000. //Reserved = 0b00_1_0110. //Reserved = 0b01_0_0100. //Reserved = 0b00_1_0111.please inform us.terminate //at receiver //Message gathered and //routed to route complex //Message Reserved //Terminate at Receiver //Message Reserved //Terminate at Receiver MsgRoutAdd = 0b01_1_0001.

com 171 The document is for study only. = 0b10_0_0100. 0b10_1_1110. Reserved54 Reserved55 Reserved56 Reserved57 Reserved58 Reserved59 Reserved60 Reserved61 Reserved62 Reserved63 Reserved64 Reserved65 Reserved66 Reserved67 Reserved68 Reserved69 Reserved70 Reserved71 Reserved72 = = = = = = = = = = = = = = = = = = = 0b10_0_1100.com EMail:cadserv21@hotmail.we will delete . = 0b10_0_0010. 0b10_0_1101. = = = = 0b10_0_0110. 0b10_1_0011. = 0b10_0_1011. = 0b10_0_0001. 0b01_1_1110. 0b01_1_1011. 0b10_1_0010. 0b10_0_1000. 0b10_1_0110. 0b10_1_1001. 0b10_0_0111. www. 0b10_1_1011. = 0b10_0_0011. 0b10_1_0000. 0b10_1_0111. 0b10_0_1001. 0b01_1_1111. 0b01_1_1101. 0b01_1_1100. = 0b10_0_1010. 0b10_1_1010. //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Memory write request 32-bit //Reserved //IO write request //Reserved //Configuration write type 0 //Configuration write type 1 //Reserved //Reserved //Reserved //Reserved //Completion with data //Completion for locked //memory read //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved = 0b10_0_0000. = 0b10_0_0101.Appendix G: PCI-Express (PCIe) Transactor Reserved40 Reserved41 Reserved42 Reserved43 Reserved44 Reserved45 Reserved46 Reserved47 MWr_32bit Reserved48 IOWr Reserved49 CfgWr0 CfgWr1 Reserved50 Reserved51 Reserved52 Reserved53 CplD CplDLk = = = = = = = = 0b01_1_1000. 0b01_1_1010. 0b01_1_1001. 0b10_0_1110. 0b10_1_1101.please inform us.if tort to your rights. 0b10_1_1000. 0b10_0_1111. 0b10_1_1100. 0b10_1_0001. 0b10_1_0101. 0b10_1_0100.cadfamily.

//Reserved //Memory write request 64-bit //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Message routed to route //complex with data MsgDRoutAdd = 0b11_1_0001. //Message routed by ID with //data MsgDBroadComp = 0b11_1_0011.terminate //at receiver with data MsgDGather = 0b11_1_0101. 0b11_0_1100. 0b11_0_1011. 0b11_0_1110. //Message broadcast from //root complex with data MsgDLocal = 0b11_1_0100.cadfamily. 0b11_0_1001. 0b11_1_1111.if tort to your rights. 0b11_0_0011. www.we will delete . 0b11_0_0101. //Message local . //Message gathered and //routed to route complex with data MsgDReserved1 = 0b11_1_0110.com 172 The document is for study only. 0b11_0_1101. 0b11_1_1100. 0b11_0_1000. 0b11_1_1101. 0b11_0_0010.nTX User’s Guide and Tutorial Reserved73 MWr_64bit Reserved74 Reserved75 Reserved76 Reserved77 Reserved78 Reserved79 Reserved80 Reserved81 Reserved82 Reserved83 Reserved84 Reserved85 Reserved86 Reserved87 Reserved88 MsgDRoutComp = 0b10_1_1111. 0b11_0_0100. = 0b11_0_0000. 0b11_1_1010. 0b11_0_0111.please inform us. 0b11_1_1011.com EMail:cadserv21@hotmail. 0b11_0_0110. = = = = = = = = = = = = = = = 0b11_0_0001. //Message routed by address //with data MsgDRoutID = 0b11_1_0010. type enum e_AckNak : 1 = = = = = = = = 0b11_1_1000. //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved = 0b11_1_0000. 0b11_1_1001. 0b11_0_1010. //Message Reserved //Terminate at Receiver Reserved89 Reserved90 Reserved91 Reserved92 Reserved93 Reserved94 Reserved95 Reserved96 }. 0b11_0_1111. //Message Reserved //Terminate at Receiver MsgDReserved2 = 0b11_1_0111. 0b11_1_1110.

Fc_Class. Pm_Enter_L23. type enum e_Special_Symbols www. DLLP}. // Posted // NonPosted // Completed type enum e_DLLP_Types : 3 {AckNak. UpdateFC }. InitFC2.com EMail:cadserv21@hotmail. TLP. type enum e_DLLP_Msg_Subtype : 2 {P. }. type enum e_Pm : 2 {Pm_Enter_L1. Unknown_Class }. Pm. type enum e_DLLP_Classes : 3 {AckNak_Class.cadfamily. type struct Z_HGFEDCBA {bit Z.Appendix G: PCI-Express (PCIe) Transactor {Ack. type enum e_PLLP_Types : 2 {NULLIFIED_TLP. Pm_Act_State_Req. InitFC1. Cpl }. Vendor_Specific. bit HGFEDCBA[8].com 173 The document is for study only.we will delete . Pm_Class. Nak}.please inform us. Vendor_Specific_Class. Pm_Req_Ack }. NP.if tort to your rights.

com 174 The document is for study only. www.if tort to your rights. 11. // // // // // // // // // // // // Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity SKP FTS SDP IDL RES1 COM RES2 RES3 PAD STP END EDB Character Character Character Character Character Character Character Character Character Character Character Character type enum e_Validity {InValid. 02. 07. 04.please inform us.nTX User’s Guide and Tutorial {PD_SKP PD_FTS PD_SDP PD_IDL PD_RES1 PD_COM PD_RES2 PD_RES3 PD_PAD PD_STP PD_END PD_EDB }. 10. = = = = = = = = = = = = 00. 09. 08.cadfamily. Valid}. 03. 06.we will delete .com EMail:cadserv21@hotmail. 05. 01.

Name The bus declaration (nte_UART_v2p1_ns) must be one of the supported transactors. 7 or 8 bit words • Parity Selection: No Parity. Programmable character format: • Word Length of 5.if tort to your rights. serial communication link.we will delete . 1½.com EMail:cadserv21@hotmail. • Stop Bit Length: 1. The UART Transactor supports the majority of features present in 16C550 compatible devices. 6. 2. full duplex. Software Flow Control via XON/XOFF character generation/recognition.com 175 The document is for study only.please inform us. Independent receiver and transmitter operating frequency to enable dual speed channel applications. Even or Odd.Appendix H: UART Transactor Appendix H: UART Transactor Overview The UART transactor fits between two industry standard UART devices to perform a point-to-point. nte_UART_v2p1_ns UARTtest { www. Features supported include: • • • Selectable serial data rates. It enables the recognition of transactions from a wire level FSDB file.cadfamily. • BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.

Tx_sample_clk_1st_time: The relative time period of the first Tx_sample_clk change. Configuration of the transactor is made via the PARAMETER section of the bcf file. Tx_bit_clk_2nd_time: The relative time period of the second Tx_bit_clk change after the previous change. "/DCDn". NOTE: UART transactor does not have a clock that can be mapped. MAPPING_ROOT = "/UART_loopback/UART_structure/UART_I". "/RIn".com EMail:cadserv21@hotmail. "/DSRn". "/RTSn". however. SIGMAP { /UART/TX /UART/RX /UART/DTRn /UART/RTSn /UART/CTSn /UART/RIn /UART/DCDn /UART/DSRn } = = = = = = = = "/TX". Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.please inform us. www.nTX User’s Guide and Tutorial Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed. "/DTRn". If this is done they will be assigned a default value (normally 0).we will delete . "/CTSn".if tort to your rights. Rx_bit_clk_1st_time: The relative time period of the first Rx_bit_clk change.cadfamily. Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.com 176 The document is for study only. The transactor signals are pre-defined as shown in the file below and must not be changed. it is possible to leave signals unconnected by removing them from the sigmap section. The available parameters are: • • • • • Tx_bit_clk_1st_time: The relative time period of the first Tx_bit_clk change. "/RX". Tx_sample_clk_2nd_time: The relative time period of the second Tx_sample_clk change after the previous change.

• UART_number_xon_xoff_chars: Number of XON/XOFF characters. • UART_word_length: The number of bits per word. • UART_xoff1: Value used as XOFF1. Rx_sample_clk_2nd_time = 50 ns. • UART_software_flow_control: Specify whether XON/XOFF characters are enabled. • UART_parity_type: Even or odd parity. The clock set up is important for the correct operation of the transactor. Rx_bit_clk_1st_time = 800 ns.com 177 The document is for study only. • UART_xon1: Value used as XON1. Tx_sample_clk_2nd_time = 50 ns. Rx_bit_clk_2nd_time = 800 ns. An example is shown below: • Figure: Clock Setup // parameters PARAMETER { Tx_bit_clk_1st_time = 800 ns. • UART_stop_bit_length: Number of stop bits. • UART_xon2: Value used as XON2.Appendix H: UART Transactor Rx_bit_clk_2nd_time: The relative time period of the second Rx_bit_clk change after the previous change. • Rx_sample_clk_2nd_time: The relative time period of the second Rx_sample_clk change after the previous change.cadfamily. • UART_parity_mode: Parity on or off.if tort to your rights.we will delete . Tx_sample_clk_1st_time = 50 ns.please inform us. Tx_bit_clk_2nd_time = 800 ns. UART_word_length = 8. • UART_xoff2: Value used as XOFF2. • Rx_sample_clk_1st_time: The relative time period of the first Rx_sample_clk change. www.com EMail:cadserv21@hotmail. Rx_sample_clk_1st_time = 50 ns.

UART_xon1 = 0b11100010. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. UART_xoff2 = 0b01010011.please inform us. } Transactor Configurations A number of transactor configurations are available. ‘ns’.com EMail:cadserv21@hotmail. www. The naming convention used is nte_UART_'ver'_’tu’ where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v2p1’) ‘tu’ – time unit (‘ps’. //evn | odd UART_stop_bit_length = 1. In this section the function.cadfamily.nTX User’s Guide and Tutorial UART_parity_mode = parity_ena. any signal changes below this time resolution will not be seen by nTE.com 178 The document is for study only. UART_xon2 = 0b00011101. //parity_ena | parity_dis UART_parity_type = evn.if tort to your rights. types and attributes of these transactions are described in detail. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. UART_xoff1 = 0b11111011.we will delete . //sfc_dis | sfc_ena UART_number_xon_xoff_chars = 1. UART_software_flow_control = sfc_dis. ‘fs’). This does not have to match the time scale of the input FSDB file.0. however.

cadfamily.TX www.if tort to your rights.Appendix H: UART Transactor Protocol Tree .please inform us.com 179 The document is for study only.com EMail:cadserv21@hotmail.we will delete .

RX www.we will delete .if tort to your rights.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial Protocol Tree .cadfamily.com 180 The document is for study only.please inform us.

please inform us. Tx_XON_char Tx_XON_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an XON character sequence.we will delete . Tx_XOFF_char Tx_XOFF_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an XOFF character sequence. to the unit (or units) to the right of the symbol. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. www.Appendix H: UART Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.if tort to your rights. Attributes: mbit data[8] Rx_BRK_char Rx_BRK_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating the Break condition.com 181 The document is for study only. Tx_char Tx_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character with correct parity.cadfamily. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. from the unit to the left of the symbol.com EMail:cadserv21@hotmail. Tx_BRK_char Tx_BRK_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating the Break condition. Attributes: bit data[8] Tx_char_parity_error Tx_char_parity_error is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character with incorrect parity.

if tort to your rights. or 8-bit data character word.nTX User’s Guide and Tutorial Rx_XOFF_char Rx_XOFF_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an XOFF character sequence.we will delete . Rx_char Rx_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character with correct parity. 6. This transaction is only enabled when the Parity Mode feature has been enabled. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. Tx_word Tx_word is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a 5.please inform us. Attributes: bit data[8] Rx_char_parity_error Rx_char_parity_error is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character with incorrect parity.cadfamily. Attributes: bit data[8] Tx_start Tx_start is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an active low Start bit. Rx_XON_char Rx_XON_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an XON character sequence.com EMail:cadserv21@hotmail. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. www.com 182 The document is for study only. 7. Attributes: bit data[8] Tx_parity Tx_parity is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character parity bit.

The UART Transactor may be configured to recognize 1. or 2 Stop Bits. Attributes: bit data[8] Rx_parity Rx_parity is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character parity bit. This transaction is only enabled when the Parity Mode feature has been enabled. Rx_word Rx_word is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a 5. Attributes: bit data Rx_start Tx_start is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an active low Start bit.if tort to your rights. 1½. 1½. 6.Appendix H: UART Transactor Attributes: bit p Tx_stop Tx_stop is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a character’s Stop Bit sequence.cadfamily. Attributes: bit data Tx_start_sample Tx_start_sample is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_sample_clk_period indicating a Start Bit synchronized to the rising edge of Tx_sample_clk. or 2 Stop Bits.please inform us. The UART Transactor may be configured to recognize 1. or 8-bit data character word. 7. Attributes: bit p Rx_stop Rx_stop is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a character’s Stop Bit sequence. www.we will delete .com EMail:cadserv21@hotmail.com 183 The document is for study only.

cadfamily. Attributes: bit data Tx_stop_halfbit Tx_stop_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_half_bit_clk_period indicating a single Half Stop Bit synchronized to the rising edge of Tx_half_bit_clk. Rx_bit Rx_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_bit_clk_period indicating a single Data Bit synchronized to the rising edge of Rx_bit_clk.nTX User’s Guide and Tutorial Tx_bit Tx_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_bit_clk_period indicating a single Data Bit synchronized to the rising edge of Tx_bit_clk.we will delete . Attributes: bit data Rx_stop_bit Rx_stop_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_bit_clk_period indicating a single Stop Bit synchronized to the rising edge of Rx_bit_clk.please inform us. Attributes: bit data Tx_stop_bit Tx_stop_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_bit_clk_period indicating a single Stop Bit synchronized to the rising edge of Tx_bit_clk.com EMail:cadserv21@hotmail.com 184 The document is for study only. www. Attributes: bit data Rx_start_sample Rx_start_sample is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_sample_clk_period indicating a Start Bit synchronized to the rising edge of Rx_sample_clk.if tort to your rights.

cadfamily. see the section on Signal Descriptions in the AMBA AXI Protocol Specification.if tort to your rights. Attributes: bit data Wires For a description of each of these wires (signals).Appendix H: UART Transactor Attributes: bit data Rx_stop_halfbit Rx_stop_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_half_bit_clk_period indicating a single Half Stop Bit synchronized to the rising edge of Rx_half_bit_clk.com 185 The document is for study only.com EMail:cadserv21@hotmail.please inform us. the UART transactor makes use of the following types: type enum e_ParitySelection { www.we will delete . such as ‘int’. Name TX RX DTRn RTSn CTSn RIn DCDn DSRn RCLK Type bit bit bit bit bit bit bit bit bit Direction UART_unit_A >=> UART_unit_B UART_unit_B >=> UART_unit_A UART_unit_A >=> UART_unit_B UART_unit_A >=> UART_unit_B UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A Support to UART_unit_A Additional Information Data Types In addition to the standard transactor types. and ‘bit’.

nTX User’s Guide and Tutorial no_parity. xon1_character. sfc_ena }.com EMail:cadserv21@hotmail. type enum e_StopBitLength { one. type enum e_parity_type { evn.please inform us. xon2_character }. xoff2_character. parity_ena }. type enum special_characters { data_character. EVEN_parity.if tort to your rights. xoff1_character. ODD_parity. odd }.com 186 The document is for study only. type enum e_sfc { sfc_dis.we will delete . type enum e_parity_mode { parity_dis.cadfamily. two }. force_parity_1. one_half. www. force_parity_0 }.

Start-of-Frame packets. Complete Split and Ping transactions. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.Appendix I: USB Transactor Appendix I: USB Transactor Overview The USB 2.please inform us. Full-speed (12Mb/s) & Low-speed (1.0 Transactor supports the following features: • • • • • USB Revision 2. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.if tort to your rights. MAPPING_ROOT = "/USB2_top_level/USB2_structure/the_usb_bus". nte_USB2_v1p0_fs) must be one of the included transactor libraries. The following limitations apply to the current version of the USB 2. Interrupt. nte_USB2_v1p0_fs myUSB { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.0 (see Limitations below).we will delete .com EMail:cadserv21@hotmail. Isochronous. www.5Mb/s). Control.0 Transactor: • Suspend and Resume is not supported.cadfamily. Name The bus declaration (e. Power-on Reset to determine speed (parameterized and selectable).g.com 187 The document is for study only. Bulk. High-speed (480Mb/s). Start Split.

= "/DM".we will delete . hold_time: The hold time for all USB signals.com EMail:cadserv21@hotmail. The transactor signals are pre-defined as shown in the file below and must not be changed. setup_time: The setup time for all USB signals. clk_2nd_time: The relative time of second clock change after the previous change. This parameter is ignored if enable_speed_detection is set to ‘true’. tDRST: Length of complete reset speed detection.if tort to your rights. enable_speed_detection: If set to ‘false’ the speed is set manually via the usb_speed_selector parameter. ‘full’ or ‘high’. The available parameters are: • • • • • • • • clk_init_value: The initial value of the clock (0 or 1). usb_speed_selector: Manually selects the speed of the USB bus. • • • www.cadfamily. NOTE: Clock can be mapped to /USB2/UCLK. packet2packet_delay: The maximum delay permitted between a token packet and subsequent data packet (including zero-length data packets). SIGMAP { // USB signals /USB2/DP /USB2/DM } = "/DP".please inform us. clk_1st_time: The relative time of the first clock change after the initial phase shift change. clk_phase_shift: The time of the first transition from the initial value.com 188 The document is for study only.0 specification. In this case the remaining parameters (below) must be set. tUCH: Minimum duration of a Chirp K from a high-speed capable device within the reset protocol. The SIGMAP code example is for an unmapped clock. Configuration of the transactor is made via the PARAMETER section of the BCF file. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. If set to ‘true’ then the transactor will detect the speed from the signals according to the USB 2. Can be set to ‘low’.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.

An example is shown below: • Figure: Clock Setup The USB interface speed can be detected by the transactor or set manually via the usb_speed_selector parameter. • tWTDCH: Time after end of device Chirp K by which hub must start driving first Chirp K in the hub’s chirp sequence. The clock set up is important for the correct operation of the transactor. If this is too short then reset SE0’s may be incorrectly detected during extraction. www. Figure: High Speed Detection Parameters Note that tWTREV + tWTRSTHS is the minimum time required for a valid SE0 to be recognized. • tDCHSE0: Time before end of reset by which a hub must end its downstream chirp sequence.cadfamily.if tort to your rights. resulting in the transactor resetting the speed mid-simulation.Appendix I: USB Transactor tWTREV: Duration a high-speed capable device operating in high-speed must wait after start of SE0 before reverting to full-speed.we will delete .com 189 The document is for study only. The diagram below demonstrates the parameters that need to be set if speed is detection is required (enable_speed_detection = true). • tWTRSTHS: Time a device must wait after reverting to full-speed before sampling the bus state for SE0 and beginning the high-speed detection handshake.com EMail:cadserv21@hotmail.please inform us.

nTX User’s Guide and Tutorial // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time packet2packet_delay usb_speed_selector enable_speed_detection tDRST tUCH tWTREV tWTRSTHS tWTDCH tDCHSE0 } = = = = = = = = = = = = = = = 0b0.0 transactor consists of a number of transactions that enable communication at different levels of abstraction.cadfamily. types and attributes of these transactions are described in detail.please inform us. 1041600 fs. Transactor Configurations A number of transactor configurations are available. 10 ms.com EMail:cadserv21@hotmail. 500 us. 100 us. 100 fs.we will delete . 100 fs. If the clock is mapped then clk_* parameters do not need to be set. 100 us. high. In this section the function.if tort to your rights. ‘fs’) Transaction Hierarchy The USB 2. www. 1041600 fs.com 190 The document is for study only. false. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. 500 ns. The naming convention used is nte_USB2_‘ver’_‘tu’ where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘tu’ – time unit (‘ps’. 0 fs. 3 ms. NOTE: PARAMETER code example is for an unmapped clock. 1 ms.

Appendix I: USB Transactor Protocol Tree www.please inform us.if tort to your rights.com 191 The document is for study only.com EMail:cadserv21@hotmail.cadfamily.we will delete .

Attributes: int int int data_packet_length address endpoint www. It includes the token packet and any subsequent data packet during read transfers.com 192 The document is for study only.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.cadfamily.we will delete .please inform us. It includes the token packet and any subsequent data packet during write transfers. from the unit to the left of the symbol. Attributes: int int T_USB2_bmRequestType_transfer_direction T_USB2_bmRequestType_type T_USB_bmRequestType_recipient bit bit bit int T_USB2_packet_identifier_field address endpoint transfer_direction transfer_type transfer_recipient bRequest[8] wValue[16] wIndex[16] wLength data_type_pid IN_data_stage IN_data_stage is a bi-directional read transaction between the host/hub and device.if tort to your rights. Attributes: int int int T_USB2_packet_identifier_field bit data_packet_length address endpoint data_type_pid data_in[][8] OUT_data_stage OUT_data_stage is a unidirectional transaction between the host/hub and device. Setup_stage Setup_stage is a unidirectional write transaction between the host/hub and device.com EMail:cadserv21@hotmail. to the unit (or units) to the right of the symbol. It includes the control token packet and any subsequent data packet used during control transfers.

Appendix I: USB Transactor T_USB2_packet_identifier_field bit data_type_pid data_out[][8] OUT_ssplit_stage OUT_ssplit_stage is a unidirectional write transaction between the host and hub.please inform us.com EMail:cadserv21@hotmail.cadfamily.we will delete .com 193 The document is for study only. FS/LS token and any subsequent data packet during split-write transfers. Attributes: int int bit bit T_USB2_endpoint_type int int hub_address port_number speed_start end endpoint_type address endpoint www. It includes the Start_Split token. It includes the Complete-Split token and FS/LS token during split-write transfers.if tort to your rights. It includes the Start-Split token and FS/LS token during split-read transfers. Attributes: int int bit bit T_USB2_endpoint_type int int int T_USB2_packet_identifier_field bit hub_address port_number speed_start end endpoint_type address endpoint data_packet_length data_type_pid data_out[][8] OUT_csplit_stage OUT_csplit_stage is a unidirectional write transaction between the host and hub. Attributes: int int bit T_USB2_endpoint_type int int hub_address port_number speed_start endpoint_type address endpoint IN_ssplit_stage IN_ssplit_stage is a unidirectional read transaction between the host and hub.

Attributes: int address www. It contains the packet hub address. FS/LS token and any subsequent data packet during split-read transfers.com EMail:cadserv21@hotmail. It includes the Complete-Split token. port number. Attributes: int int bit T_USB2_endpoint_type int int int T_USB2_packet_identifier_field bit hub_address port_number speed_start endpoint_type address endpoint data_packet_length data_type_pid data_in[][8] token_packet token_packet is a unidirectional transaction between a host/hub and device.if tort to your rights. address.nTX User’s Guide and Tutorial IN_csplit_stage IN_csplit_stage is a bi-directional read transaction between the host and hub. endpoint and CRC5 values.cadfamily. It contains the packet identifier.com 194 The document is for study only. Attributes: bit bit bit bit bit T_USB2_endpoint_type bool address[7] start_complete port[7] speed_start end end_type crc5_error ping_special_token ping_special_token is a unidirectional transaction between a host/hub and device. It contains the address and endpoint values. Attributes: T_USB2_packet_identifier_field bit bit bool packet_id address[7] endpoint[4] crc5_error split_token_packet split_token_packet is a unidirectional transaction between a host and hub.we will delete . endpoint and CRC5 values.please inform us. speed.

speed indication and endpoint type for split transfers. It signifies the start of a packet. It contains the start/complete identifier. Attributes: none. Attributes: T_USB2_packet_identifier_field packet_id sync_phase sync_phase is a unidirectional transaction between a host/hub and device. Attributes: int bool frame_number crc5_error data_packet data_packet is a unidirectional transaction between a host/hub and device.com EMail:cadserv21@hotmail. data bytes and CRC16.we will delete . port address.com 195 The document is for study only.please inform us.Appendix I: USB Transactor int endpoint start_of_frame_packet start_of_frame_packet is a unidirectional transaction between a host/hub and device. packet identifier. Attributes: bit bit bit bit start_complete port[7] speed_start end www.if tort to your rights. It is generated every 125?s signifying the start of a micro-frame and contains the frame number. split_phase split_phase is a unidirectional transaction between a host and hub. It contains the payload length. It contains the handshake response from host or device.cadfamily. Attributes: int T_USB2_packet_identifier_field bit bool payload_length packet_id data[][8] crc16_error handshake_packet handshake_packet is a unidirectional transaction between a host/hub and device.

cadfamily. Attributes: bit address[7] endpoint_phase endpoint_phase is a unidirectional transaction between a host/hub and device.nTX User’s Guide and Tutorial bit end_type[2] identifier_phase identifier_phase is a unidirectional transaction between a host/hub and device.we will delete . Attributes: bit bool data_bit data_valid address_phase address_phase is a unidirectional transaction between a host/hub and device. It contains the endpoint of the device. It contains the packet identifier. It controls when bit-stuffing is required.if tort to your rights. Attributes: T_USB2_packet_identifier_field packet_id bit_stuff_phase bit_stuff_phase is a unidirectional transaction between a host/hub and device.com EMail:cadserv21@hotmail. Attributes: bit endpoint[4] frame_number_phase frame_number_phase is a unidirectional transaction between a host/hub and device. Attributes: www.com 196 The document is for study only.please inform us. It contains the address of the device. Attributes: bit frame_number[11] data_phase data_phase is a unidirectional transaction between a host/hub and device. It contains the data byte stream. It contains the frame number.

Attributes: bit crc5_data[5] end_of_sof_phase end_of_sof_phase is a unidirectional transaction between a host/hub and device. It signifies EOP for packets other than Start-of-Frame or Data. crc5_phase crc5_phase is a unidirectional transaction between a host/hub and device. It signifies the EOP for a Start-of-Frame packet. Name DP DM Type bit bit Direction source to destination or destination to source source to destination or destination to source www. It contains the un-coded bit values. Attributes: None.please inform us.we will delete .cadfamily. It contains the CRC5 value.com EMail:cadserv21@hotmail. Attributes: bit bit plus minus Wires For a description of each of these wires (signals). end_of_packet_phase end_of_packet_phase is a unidirectional transaction between a host/hub and device. Attributes: None.if tort to your rights.Appendix I: USB Transactor int payload_length bit data[][8] NOTE: The CRC16 value and 8-bit EOP are absorbed into the data byte stream as the last 3-bytes in the stream. usb2_stripe usb2_stripe is a bi-directional transaction between a host/hub and device. see the section on Signal Descriptions in the AMBA AXI Protocol Specification.com 197 The document is for study only.

please inform us.com EMail:cadserv21@hotmail. pid_ack = 0b0010. pid_in = 0b1001. pid_mdata = 0b1111 }.if tort to your rights. pid_stall = 0b1110.cadfamily. pid_data1 = 0b1011. pid_pre_or_err = 0b1100. such as ‘int’. pid_data2 = 0b0111.nTX User’s Guide and Tutorial Additional Information Data Types In addition to the standard transactor types. type enum T_USB2_bmRequestType_type:2 { t_standard = 0b00. and ‘bit’. pid_nyet = 0b0110. the USB 2. pid_ping = 0b0100. t_reserved = 0b11 www. type enum T_USB2_bmRequestType_transfer_direction:1 { host2device = 0b0. t_class = 0b01. pid_nak = 0b1010. endp_isochronous = 0b01. t_vendor = 0b10.we will delete . pid_sof = 0b0101. endp_interrupt = 0b11 }. pid_split = 0b1000. pid_setup = 0b1101. pid_out = 0b0001.com 198 The document is for study only. pid_data0 = 0b0011.0 transactor makes use of the following types: type enum T_USB2_packet_identifier_field:4 { pid_reserved = 0b0000. endp_bulk = 0b10. device2host = 0b1 }. type enum T_USB2_endpoint_type:2 { endp_control = 0b00.

}. high = 0b10. type enum T_USB_bmRequestType_recipient:5 { recip_device = 0b0_0000.com EMail:cadserv21@hotmail. www.please inform us. recip_reserved = 0b0_0100 }. recip_interface = 0b0_0001.cadfamily. recip_other = 0b0_0011. recip_endpoint = 0b0_0010.if tort to your rights.Appendix I: USB Transactor }. type enum T_USB2_speed:2 { low = 0b00.com 199 The document is for study only.we will delete . full = 0b01.

if tort to your rights.we will delete .com EMail:cadserv21@hotmail.please inform us.com 200 The document is for study only.nTX User’s Guide and Tutorial www.cadfamily.

19. 19. 40 Search Forward 16. 70 streams 15. 44.please inform us. 18. 19. 21. 65. 40 S Search Backward 16. 47. 21 OTI 15. 70. 71. 73 R related transaction 18 relationships 18. 19 Sync Cursor Time 45 system tasks 73 G Get Signals 38 Get Stream 41 H HDL 64 header file 65. 17. 50 stream 17. 72 attributes 15. 45.we will delete . 21. 69. 47 M marker 45 Merge Stream 43 C C code 66 C files 73 C functions 64 C program 65 child transactions 40 Column Configuration 46 cursor 45 cursor time 17 N nWave 16. 39. 38. 71 PLI 64. 19. 39. 64.if tort to your rights. 43. 21 overlap 17 P PCI 64.cadfamily. 66 D dynamic link 65 F filter 45 FSDB 15. 38. 39 O Open Transaction Interface 15. 69 www. 72 attribute 70. 46.com 201 The document is for study only.Index Index A API 15. 40. 17. 16. 72.com EMail:cadserv21@hotmail. 69. 17. 39. 40 Set Search Attributes 19 Show All 20.

49. 17. 38. 18. 48. 70. 64. 45.if tort to your rights. 41.com EMail:cadserv21@hotmail.please inform us. 40. 50 Transaction Attribute Values 19. 44 transactions 49.we will delete .cadfamily. 50 V Verdi 37 Verilog 65. 16. 71. 43. 66 W waveform 17 www. 39 transaction relationships 19 transaction streams 42.com 202 The document is for study only. 47. 72. 73 Transaction Analyzer 19. 41.nTX User’s Guide and Tutorial T transaction 15.

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