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Topics

Basics of sequential machines. s Sequential machine specification. s Sequential machine design processes.
s

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Sequential machines
Use registers to make primary output values depend on state + primary inputs. s Varieties:
s

Mealyoutputs function of present state, inputs; Mooreoutputs depend only on state.

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FSM structure

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Constraints on structure
No combinational cycles. s All components must have bounded delay.
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Synchronous design
s

Controlled by clock(s).
State changes at time determined by the clock. Inputs to registers settle in time for state change. Primary inputs settle in time for combinational delay through logic.

Machine state is determined solely by registers.


Dont have to worry about timing constraints, events outside the registers.

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Non-functional requirements and optimization


s

Performance:
Clock period is determined by combinational logic delay.

Area:
Combinational logic size usually dominates area.

Energy/power:
Often dominated by combinational logic. May be improved by latching values.

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Models of state machines


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Register-transfer:
Combinational equations for inputs to registers.

State transition graph/table:


Next-state, output functions described piecewise.

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State transition graph


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Each transition describes part of the nextstate, output functions:


0/010 S1 1/1-0 S3 S2

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Register-transfer structure
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Registers fed by combinational logic:


D Q D Q

Combinational logic

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Block diagram
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Purely structural description:

B1

B2
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Symbolic values
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A sequential machine description may use symbolic, not binary values.


Symbolic values must be encoded during implementation.

Encoding may optimize implementation characteristics:


Area. Performance. Energy.

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STG vs. register-transfer


Each representation is easier for some types of machines. s Example: counter.
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Counter state transition graph


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Cyclic structure:
1/1 0 1 1/2 6 1/7 7

1/0

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Counter register-transfer function


s

Specify using addition:


Next_count = count + 1.

Regular structure of logic.

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Example: 01 string recognizer


s

Recognize 01 sequence in input string:


recognizer 0 0 1 1 0 1 0 0 1 0 0 1
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Recognizer state transition graph


1/0 0/0 0/0

Bit 1

Bit 2

1/1

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Mealy vs. Moore machine


s

Moore machine:
Output a function of state.

Mealy machine:
Output a function of primary inputs + state.

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Sequential machine definition


Machine computes next state N, primary outputs O from current state S, primary inputs I. s Next-state function:
s

N = (I,S).
s

Output function (Mealy):


O = (I,S).

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Reachability
State is reachable if there is a path from given state. s May be created by state encoding:
s s0 s1

s2
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s3
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Homing sequence
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Sequence of inputs that drives the machine to a given state.


s0 s1

s2

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Equivalent states
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States are equivalent if they cannot be distinguished by any input sequence:


s1 1/0 s3 -/0 0/0 s2 -/0 s4 -/1

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Networks of FSMs
s

Functions can be built up from interconnected FSMs:


I1 O1 M1 x y M2 I2 O2

Internal connections External connections


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Illegal composition of Mealy machines

Combinational logic

Combinational logic

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Communicating FSM states


0/0 s1 -/1 1/0 s2 M1
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s3 1/1 -/0 s4 M2
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0/0

Product machine
s

Two connected machines:

i1

o1

i2

o2

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Component STGs

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Behavior of connected machines


i1 R o1 i2 S o2

0 0 0 0
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R1 R2 R3 R3

0 1 0 0

S1 S2 S1 S1

1 0 0 0
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Forming product machine


s s

Form Cartestian product of states:


R1S1, R1S2, R2S1, R2S2, R3S1, R3S2.

For each product state, determine the combined behavior of each product transition:
Required inputs. Produced output. Next product state.

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State assignment
s

Find a binary code for symbolic values in machine.


Optimize area, performance. May be done on inputs, outputs as well.

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Optimizing state assignments


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Codes affect the next-state, output logic.


Compute conditions based on state.

Best code depends on the input, output logic and its interaction with state computations.

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Encoding a shift register


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Symbolic state transition table for shift register:

0 1 0 1 0 1 0 1

S00 S00 S01 S01 S10 S10 S11 S11

S00 S10 S00 S10 S01 S11 S01 S11

0 0 1 1 0 0 1 1

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Bad encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 10. s Logic:
s

Output = S1 S0 + S1 S0 N1 = I N0 = I S1 + I S1

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Good encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 11. s Logic:
s

Output = S0 N1 = I N0 = S1

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One-hot code
N-state machine has n-bit encoding. s Ith bit is 1 if machine is in state i. s Comparison:
s

Easy to tell what state the machine is in. Easy to get the machine into an illegal state (0000, 1111, etc.). Uses a lot of registers.
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Common factors in state coding


s

Consider this set of transitions:


0, s1 OR s2 -> s3, 1

Want to choose a code that easily produces s1 OR s2.


S1 = 00, S2 = 01.

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State codes in n-space


1

s2 code = 110 s1 code = 111

0 1
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State codes and delay

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