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Basics of sequential machines. s Sequential machine specification. s Sequential machine design processes.
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Sequential machines
Use registers to make primary output values depend on state + primary inputs. s Varieties:
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FSM structure
Constraints on structure
No combinational cycles. s All components must have bounded delay.
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Synchronous design
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Controlled by clock(s).
State changes at time determined by the clock. Inputs to registers settle in time for state change. Primary inputs settle in time for combinational delay through logic.
Performance:
Clock period is determined by combinational logic delay.
Area:
Combinational logic size usually dominates area.
Energy/power:
Often dominated by combinational logic. May be improved by latching values.
Register-transfer:
Combinational equations for inputs to registers.
Register-transfer structure
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Combinational logic
Block diagram
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B1
B2
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Symbolic values
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Cyclic structure:
1/1 0 1 1/2 6 1/7 7
1/0
Bit 1
Bit 2
1/1
Moore machine:
Output a function of state.
Mealy machine:
Output a function of primary inputs + state.
N = (I,S).
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Reachability
State is reachable if there is a path from given state. s May be created by state encoding:
s s0 s1
s2
FPGA-Based System Design: Chapter 5
s3
Copyright 2004 Prentice Hall PTR
Homing sequence
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s2
Equivalent states
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Networks of FSMs
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Combinational logic
Combinational logic
s3 1/1 -/0 s4 M2
Copyright 2004 Prentice Hall PTR
0/0
Product machine
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i1
o1
i2
o2
Component STGs
0 0 0 0
FPGA-Based System Design: Chapter 5
R1 R2 R3 R3
0 1 0 0
S1 S2 S1 S1
1 0 0 0
Copyright 2004 Prentice Hall PTR
For each product state, determine the combined behavior of each product transition:
Required inputs. Produced output. Next product state.
State assignment
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Best code depends on the input, output logic and its interaction with state computations.
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
Bad encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 10. s Logic:
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Output = S1 S0 + S1 S0 N1 = I N0 = I S1 + I S1
Good encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 11. s Logic:
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Output = S0 N1 = I N0 = S1
One-hot code
N-state machine has n-bit encoding. s Ith bit is 1 if machine is in state i. s Comparison:
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Easy to tell what state the machine is in. Easy to get the machine into an illegal state (0000, 1111, etc.). Uses a lot of registers.
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
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FPGA-Based System Design: Chapter 5