Figure 1-1 Basic Gates

A C B AND: C = A B

A C B OR: C = A + B A B

A NOT: C = A'

C

C

EXCLUSIVE OR: C = A + B

Figure 1-2 Full Adder
X 0 0 0 0 1 1 1 1 Y Cin CoutSum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 1

X Y Cin

Cout FULL ADDER Sum (a) Full adder module

(b) Truth Table Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin

Figure 1-3 Four-Variable Karnaugh Maps
AB CD 00 01 11 10 00 01 11 10
0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10

AB CD 00 C 01 11 10 00 01 11 10
1 0 1 1 0 1 1 1 0 0 X X 1 0 1 1

four corner terms combine to give B' D' A'BD

F =∑m(0,2,3,5,6,7,8,10,11) + ∑d(14,15) = C + B' D' + A' BD = (B' + C + D) (B + C + D') (A'+B')

Figure 1-4 Selection of Prime Implicants AB CD 00 A'C' 01 11 3 00 1 0 01 X 4 11 10 8 12 1 1 1 5 13 9 1 7 1 15 1 11 ACD 10 1 2 6 X 14 10 A'B'D' F = A'C' + A'B'D' + ACD + A'BD or F = A'C' + A'B'D' + ACD + BCD .

Figure 1-5 Simplification Using Map-Entered Variables AB AB AB 00 01 11 10 00 01 11 10 1 X 1 1 X 1 1 X AB CD 00 01 11 10 00 1 01 11 10 X 1 1 E E X 1 F 1 X CD CD 00 01 11 10 00 X 01 11 10 X X X 1 1 X X X X CD 00 01 11 10 00 01 11 10 X X X X X X 1 X X G E=F=0 MS 0 = A'B' + ACD E = 1. F = 1 MS 2 = AD G = MS0 + EMS 1 + FMS 2 = A'B' + ACD + EA'D + FAD . F = 0 MS 1 = A'D E = 0.

Figure 1-6 NAND and NOR Gates NAND: A B NOR: A B C A B C C = (A+B)' = A'B' C A B C C = (AB)' = A' + B' .

Figure 1-7 Conversion to NOR Gates A B' G D E F C Z (a) AND-OR network Double inversion cancels A B' C' D G' Z Complemented input E cancels inversion F (b) Equivalent NOR-gate network .

Figure 1-8 Conversion of AND-OR Network to NAND Gates A B C D E F (a) AND_OR network Bubbles cancel A B C D E F (b) First step in NAND conversion Added inverter A B' Added inverter C D' E' F (c) Completed conversion .

Hazard (b) Timing Chart A B C A F BC 00 01 F = AB' + BC + AC 11 10 A 0 0 0 1 0 1 1 1 1 0 (c) Network with hazard removed .Figure 1-9 Elimination of 1-Hazard A B E C F = AB' + BC D F BC 00 01 11 B' B D E F 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns 10 A 0 0 0 1 0 1 1 1 1 0 (a) Network with 1-hazard 1 .

Figure 1-10 Clocked D Flip-flop with Rising-edge Trigger Q' Q D Q DFF 0 0 1 1 D Q+ = D 0 1 0 1 Q+ 0 0 1 1 CLK .

Figure 1-11 Clocked J-K Flip-flop J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 1 0 Q' K FF CK Q J Q + = JQ' + K'Q .

Figure 1-12 Clocked T Flip-flop Q' Q T Q FF 0 0 1 1 T Q+ = QT' + Q'T = Q + T 0 1 0 1 Q+ 0 1 1 0 CLK .

Figure 1-13 S-R Latch S S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 – – P R Q Q += S + R'Q .

Figure 1-14 Transparent D Latch G 0 0 0 0 1 1 1 1 D 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 1 0 0 1 1 Q Latch G D .

Figure 1-15 Implementation of D Latch D G Q Q+ = DG + G'Q + (DQ) D .

Figure 1-16 General Model of Mealy Sequential Machine Inputs (X) Combinational Network Next state Outputs (Z) State State Reg clock .

Figure 1-17 State Graph and Table for Code Converter t0 t1 0/0.1/1 t3 NC S5 (b) State Table (a) Mealy state graph .1/1 t2 NC NC S1 0/1 S3 0/1 0/1 1/0 S0 1/0 S2 C 0/0.1/1 S4 C 1/0 S6 C 0/1 PS S0 S1 S2 S3 S4 S5 S6 X=0 S1 S3 S4 S5 S5 S0 S0 NS X=1 S2 S4 S4 S5 S6 S0 – X=0 1 1 0 0 1 0 1 Z X=1 0 0 1 1 0 1 – 0/0.

6) (in the X=1 column. and S5 & S6 are NS of S4) Figure 1-18(a) State Assignment Map 01 11 10 .3. (1.6) III.2) (3. in the X=0 column. S3 & S4 are NS of S1.4.6) (2.2) (3. II. and S5 & S6 have NS S0) II.4) (5.1. III. S1 and S2 both have NS S4.4) (5. States which have the same next state (NS) for a given input should be given adjacent assignments (look at the columns of the state table). States which have the same output for a given input should be given adjacent assignments.5) Q1 Q2 Q3 00 0 S0 1 S1 S2 S5 S6 S3 S4 (S1 & S2 are NS of S0. I. S3 & S4 have NS S5. (1.From Page 20 I. States which are the next states of the same state should be given adjacent assignments (look at the rows). (0.

S4 = 110. S5 = 011. S6 = 010 . S1 = 100. S3 = 111.Figure 1-17(b) State Table Figure 1-18(b) Transition Table PS S0 S1 S2 S3 S4 S5 S6 NS Z X=0 X=1 X=0 X=1 S1 S3 S4 S5 S5 S0 S0 S2 S4 S4 S5 S6 S0 – 1 1 0 0 1 0 1 0 0 1 1 0 1 – Q1Q2Q3 000 100 101 111 110 011 010 001 Q1:Q2:Q3: X=0 X=1 100 111 110 011 011 000 000 xxx 101 110 110 011 010 000 xxx xxx Z X=0 X=1 1 1 0 0 1 0 1 x 0 0 1 1 0 1 x x S0 = 000. S2 = 101.

Figure 1-19 Karnaugh Maps for Figure 1-17 XQ 1 Q 2Q 3 00 01 11 10 1 00 1 1 1 01 11 10 X 0 0 1 0 0 1 0 0 X 0 X XQ1 Q 2 Q 3 00 01 11 10 0 00 0 1 1 01 11 10 X 0 0 1 1 1 1 1 1 X 0 X D 1 = Q1+ = Q2' XQ1 Q 2Q 3 00 01 11 10 00 0 1 0 1 01 11 10 X 0 0 0 1 1 0 1 0 X 0 X D 2 = Q2+= Q1 XQ1 Q 2Q 3 00 01 11 10 00 1 1 0 0 01 11 10 X 0 1 0 0 1 1 1 0 X 1 X D 3 = Q3+ = Q1Q 2Q 3 + X'Q1Q 3' + XQ1'Q 2' Z = X'Q3' + XQ3 .

Figure 1-20 Realization of Code Converter Q2' G1 A1 D Q FF1 Q' Q1 D Q FF2 Q' G4 D3 D Q1 Q1' Q2 Q2' X G5 A5 A6 G6 G7 Z Q1 Q2 Q3 Q1 Q3' I1 X' G2 A2 X Q1' Q2' G3 A3 CLK Q3 Q X' FF3 Q3' Q' .

Figure 1-21 Derivation of J-K Input Equations Q1+ XQ1 Q 2 Q 3 00 01 11 10 1 00 1 1 1 01 11 10 X 0 0 1 0 0 1 0 0 X 0 X J1= Q 2' XQ1 Q 2 Q 3 00 01 11 10 00 1 X X 1 01 11 10 X 0 0 X X X X X X X 0 X XQ1 K1 = Q 2 Q 2 Q 3 00 01 11 10 X 00 X 0 0 01 11 10 X X X 0 1 1 0 1 1 X X X (a) Derivation using separate J-K map XQ1 Q 2 Q 3 00 01 11 10 1 00 1 1 1 01 11 10 X 0 0 1 0 0 1 0 0 X 0 X Q1+ XQ1 Q 2 Q 3 00 01 11 10 0 00 0 1 1 01 11 10 X 0 0 1 1 1 1 1 1 X 0 X Q2+ XQ 1 Q 2 Q 3 00 01 11 10 00 0 1 0 1 J3 J2 X 01 X 0 0 K3' 0 11 0 1 1 K2' X J3 10 0 1 0 J3 = X'Q 1 + XQ1' K3 = Q 1' + Q2' Q3+ J1 K1' J1 J1 = Q2' K1 = Q2 J2 = Q1 K2 = Q 1' (b) Derivation using the shortcut method .

Figure 1-22 Coding Schemes for Serial Data Transmission bit sequence NRZ NRZI RZ Manchester 1 bit time 0 1 1 1 0 0 1 0 .

Figure 1-23 Moore network for NRZ-to-Manchester Conversion NRZ data CLK2 X Conversion Network Z Manchester data (a) Conversion network S0 0 1 1 S3 1 1 0 S1 0 0 0 S2 1 Present Next State State X = 0 X=1 S0 S1 S3 S1 S2 – S2 S1 S3 S3 – S0 (c) State table Present Output (Z) 0 0 1 1 (b) State Graph .

Figure 1-24 Timing for Moore Network 1 bit time X (NRZ) CLOCK2 State S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1 Z (Manchester) 0 0 1 1 bit time 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 .

X ) N2 Z2 = 2( sj .Figure 1-25 Determination of Equivalent States si X sj N1 Z1 = 1( s i. X ) si s j iff Z1 = Z 2 for every input sequence X .

b a.b c-e b-g a b c d e e-f a.Figure 1-26(i) State Table Reduction Present State a b c d e f g h Next State X=0 1 c f d e ha g / b g e b f a c g c f Present Output X=0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 b c d e f g c-d e-f f -g b-c f -g a ≡ b iff c ≡ d and e ≡ f a.g a.g f .d e.g e.

b d e a.g a-b a.b c-e b-g a b c d e e-f a-g f a b c d e a ≡ b.d e. c ≡ d.b c-e b-g e-f a.g f f g a.Figure 1-26(ii) State Table Reduction b c d e f g c-d e-f f -g b-c f -g a.g e.g e. e ≡ f .g a ≡ b iff c ≡ d and e ≡ f b c c-d e-f f -g b-c f -g a.d e.

e ≡ f Present State a c e g X=0 c a e c 1 e g a g X=0 0 0 0 0 1 0 0 1 1 Final Reduced Table .Figure 1-26(iii) State Table Reduction Present State a b c d e f g h Next State X=0 1 c f d e ha g / b g e b f a c g c f Present Output X=0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 a ≡ b. c ≡ d.

Figure 1-27 Timing Diagram for Code Converter Clock X State Next State Z S0 S1 1 0 S1 S3 0 S3 S5 1 1 S5 S0 1 0 S0 * 0 ta t b tc S2 1 S2 S4 0 0 S4 S5 0 S5 S0 1 S0 S2 0 1 *=S1 1 .

Figure 1-28 Timing Diagram for Figure 1-20 Clock X Q3 Q2 Q1 Z 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 .

Figure 1-29 Setup and Hold Times for D Flip-flop t su t h D Clock Q t plh t phl .

Figure 1-30 Setup and Hold Timing for Changes in X CLK X tx tcxmax tsu ty tcxmin th D .

Figure 1-31 Synchronous Digital System Clock Control Signals Condition Signals Data In Control Inputs CONTROL SECTION DATA SECTION Data Out .

Figure 1-32 Timing Chart for System with Falling-Edge Devicves State Change Initiated Here Clock Uncertain Switching Transients Control Signal Clock·CS Figure 1-33 Gated Control Signal Clock CS CLK CK Clock CS CK (a) Faling-edge device (b) Rising-edge device .

Figure 1-34 Timing Chart with Rising-Edge Devices State Change Initiated Here Clock Switching Transients Control Signal (CS) CLK1 = Clock · CS CS CLK2 = Clock + CS (a) (b) Figure 1-35 Incorrect Design Clock CS Figure 1-36 Correct Design (a) with gated clock (b) With enble CS CK CLK2 Clock CK Enable CLK1 CK Clock CS "Rising Edge" Device .

All state changes occur immediately following the active edge of the clock signal. switching noise.Synchronous Design Principals (from page 34) Method: All clock inputs to flip-flops. etc. occur between clock pulses and have no effect on system performance. are driven directly from the system clock or from the clock ANDed with a control signal. etc. Result: Advantage: All switching transients. . registers. counters.

Figure 1-37 Four Kinds of Tristate Buffers B A B 0 0 1 1 A 0 1 0 1 C C Hi-Z Hi-Z 0 1 A B 0 0 1 1 A 0 1 0 1 B C C Hi-Z Hi-Z 1 0 A B 0 0 1 1 A 0 1 0 1 B C C 0 1 Hi-Z Hi-Z A B 0 0 1 1 A 0 1 0 1 B C C 1 0 Hi-Z Hi-Z (a) (b) (c) (d) .

A Reg. B Reg. C Clock .Figure 1-38 Data Transfer Using Tristate Bus Eni Input Data 8 Ena Lda 8 Ldb TRI-STATE BUS Enb Enc Ldc Reg.