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• It is a 16 bit µp. • 8086 has a 20 bit address bus can access upto 220 memory locations ( 1 MB) . • It can support upto 64K I/O ports. • It provides 14, 16-bit registers. • It has multiplexed address and data bus AD0- AD15 and A16 – A19.
M. Krishna Kumar
8086 Microprocessor (cont..)
• It requires single phase clock with 33% duty cycle to provide internal timing. • 8086 is designed to operate in two modes, Minimum and Maximum. • It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. • It requires +5V power supply. • A 40 pin dual in line package.
M. Krishna Kumar
8086 Microprocessor (cont..)
Minimum and Maximum Modes: • The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. • The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.
M. Krishna Kumar
8086 Microprocessor (cont..)
AH BH CH GENERAL REGISTERS DH SP BP SI DI ES CS SS DS ALU DATA BUS 16 BITS BUS TEMPORARY REGISTERS IP 8 0 8 6 CONTROL LOGIC B U S EU CONTROL Q BUS SYSTEM 8 BIT FLAGS EXECUTION UNIT ( EU ) BUS INTERFACE UNIT ( BIU) AL BL CL DL ADDRESS BUS ∑ ( 20 ) BITS DATA BUS ( 16 ) BITS
INSTRUCTION QUEUE 1 2 3 4 5 6
M. Krishna Kumar MM/M1/LU3/V1/2004 4
Krishna Kumar MM/M1/LU3/V1/2004 5 .Pin Diagram of 8086 GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 A19/S6 ____ VCC AD15 A16 / S3 A17 / S4 A18 / S5 _____ 8086 CPU 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ___ BHE / S7 _____ _____ MN/MX RD ___ RQ _____ / GT0 ( HOLD) ____ RQ / GT1 ( HLDA) ___ _______ LOCK (WR) ___ ____ ___ S1 ___ S0 ______ (DT / R) _____ (DEN) ________ S2 (M / IO ) QS1 (INTA) TEST READY RESET QS0 (ALE) M.
D15 8086 MPU ALE ___ BHE / S7 __ TEST NMI RESET INTERFACE HOLD HLDA VCC ____ DMA INTERFACE MEMORY I/O CONTROLS M / IO ____ __ DT / R RD _____ _____ WR MN / MX MODE SELECT DEN READY CLK M. Krishna Kumar MM/M1/LU3/V1/2004 6 .VCC GND A0 . A16 / S3 – A19/S6 INTR _____ INTA INTERRUPT ______ ADDRESS / DATA BUS D0 .A15.
reading and writing operands for memory and calculating the addresses of the memory operands. • EU executes instructions from the instruction system byte queue.Internal Architecture of 8086 • 8086 has two blocks BIU and EU. • The instruction bytes are transferred to the instruction queue. • The BIU performs all bus operations such as instruction fetching. M. Krishna Kumar MM/M1/LU3/V1/2004 7 .
Krishna Kumar MM/M1/LU3/V1/2004 8 . • EU contains Control circuitry. Address adder. M. Instruction pointer. Flag register. ALU. • BIU contains Instruction queue. Pointer and Index register. Segment registers.. Instruction decoder. This results in efficient use of the system bus and system performance.) • Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining.Internal Architecture of 8086 (cont.
Krishna Kumar MM/M1/LU3/V1/2004 9 . Instruction queuing. M.) • Bus Interfacr Unit: • It provides a full 16 bit bidirectional data bus and 20 bit address bus. Address relocation and Bus control..Internal Architecture of 8086 (cont. • The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: • Instruction fetch. Operand fetch and storage. • The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
Internal Architecture of 8086 (cont. • These prefetching instructions are held in its FIFO queue. When ever the queue of the BIU is not full. it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory. the BIU is free to look ahead in the program by prefetching the next sequential instruction. the BIU fetches two instruction bytes in a single memory cycle. it automatically shifts up through the FIFO to the empty location nearest the output.) • This queue permits prefetch of up to six bytes of instruction code. • After a byte is loaded at the input end of the queue. Krishna Kumar MM/M1/LU3/V1/2004 10 .. With its 16 bit data bus. M.
Krishna Kumar MM/M1/LU3/V1/2004 11 . • These intervals of no bus activity. It reads one instruction byte after the other from the output of the queue.. If the queue is full and the EU is not requesting access to operand in memory. • If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O. the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.Internal Architecture of 8086 (cont. which may occur between bus cycles are known as Idle state.) • The EU accesses the queue from the output end. M.
Internal Architecture of 8086 (cont. M. the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.) • The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus.. Krishna Kumar MM/M1/LU3/V1/2004 12 . • For example. • The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.
• The EU extracts instructions from the top of the queue in the BIU. passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. generates operands if necessary.. the EU tests the status and control flags and updates them based on the results of executing the instruction. Krishna Kumar MM/M1/LU3/V1/2004 13 .Internal Architecture of 8086 (cont. decodes them.) • EXECUTION UNIT : The Execution unit is responsible for decoding and executing all instructions. • During the execution of the instruction. M.
. it transfers control to a location corresponding to another set of sequential instructions. the EU waits for the next instruction byte to be fetched and shifted to top of the queue. Krishna Kumar MM/M1/LU3/V1/2004 14 . the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.) • If the queue is empty.Internal Architecture of 8086 (cont. • Whenever this happens. • When the EU executes a branch or jump instruction. M.
) COMMON SIGNALS Name AD 15 – AD 0 A19 / S 6 – A 16 / S 3 BHE /S7 Function Address/ Data Bus Address / Status Bus High Enable / Status Minimum / Maximum Mode Control Read Control Wait On Test Control Wait State Controls System Reset Non .State Output 3.State Input Input Input Input Input Input Input 15 MN / MX RD TEST READY RESET NMI INTR CLK Vcc GND M.Internal Architecture of 8086 (cont.. Krishna Kumar .State Input Output 3.state Output 3 .Maskable Interrupt Request Interrupt Request System Clock + 5V Ground MM/M1/LU3/V1/2004 Type Bidirectional 3 .
state .Internal Architecture of 8086 (cont. Output 3. 3. Krishna Kumar MM/M1/LU3/V1/2004 16 .. 3-State Output Output Function Hold Request Hold Acknowledge Write Control Memory or IO Control Data Transmit / Receiver Date Enable Address Latch Enable Interrupt Acknowledge M.State Output .) Minimum Mode Signals Name HOLD HLDA WR M/IO DT/R DEN ALE INTA ( MN/ MX = Vcc ) Type Input Output Output . Output 3-State .
Krishna Kumar MM/M1/LU3/V1/2004 17 .State Output M.) Maximum mode signals ( MN / MX = GND ) Name RQ / GT1.Internal Architecture of 8086 (cont. 0 LOCK S2 – S0 QS1.. QS0 Function Request / Grant Bus Access Control Bus Priority Lock Control Bus Cycle Status Instruction Queue Status Type Bidirectional Output. 3. 3.State Output.
the 8086 provides all control signals needed to implement the memory and I/O interface. • Address/Data Bus : these lines serve two functions.Minimum Mode Interface • When the Minimum mode operation is selected. interrupt and DMA. A 20bit address gives the 8086 a 1Mbyte memory address space. A19 represents the MSB and A0 LSB. Krishna Kumar MM/M1/LU3/V1/2004 18 . • The minimum mode signal can be divided into the following basic groups : address/data bus. control. As an address bus is 20 bits long and consists of signal lines A0 through A19. More over it has an independent I/O address space which is 64K bytes in length. status. M.
• When acting as a data bus. they carry read/write data for memory. D15 is the MSB and D0 LSB. input/output data for I/O devices.Minimum Mode Interface ( cont. and interrupt type codes from an interrupt controller. M. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles..) • The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. Krishna Kumar MM/M1/LU3/V1/2004 19 .
.) Vcc GND INTR Interrupt interface INTA Address / data bus TEST NMI 8086 RESET MPU D0 – D15 ALE BHE / S7 M / IO DMA interface HOLD HLDA DT / R RD WR Vcc Mode select MN / MX CLK clock DEN READY Memory I/O controls A0-A15.Minimum Mode Interface ( cont. Krishna Kumar Block Diagram of the Minimum Mode 8086 MPU MM/M1/LU3/V1/2004 20 .A16/S3 – A19/S6 M.
Krishna Kumar MM/M1/LU3/V1/2004 21 . M. • Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle.. These status bits are output on the bus at the same time that data are transferred over the other bus lines. • Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.Minimum Mode Interface ( cont.) • Status signal : The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3.
M. Krishna Kumar MM/M1/LU3/V1/2004 22 .Minimum Mode Interface ( cont.) S4 0 0 1 1 S3 0 1 0 1 Segment Register Extra Stack Code / none Data Memory segment status codes..
Krishna Kumar MM/M1/LU3/V1/2004 23 . They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus.. • Control Signals : The control signals are provided to support the 8086 memory I/O interfaces. The last status bit S6 is always at the logic 0 level.Minimum Mode Interface ( cont.) • Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. M. when valid write data are on the bus and when to put read data on the system bus.
Minimum Mode Interface ( cont. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. • Using the M/IO and DT/R lines. the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. • Another control signal that is produced during the bus cycle is BHE bank high enable. which is as the S7 status line. These lines also serves a second function.) • ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. Krishna Kumar MM/M1/LU3/V1/2004 24 .. M.
This corresponds to reading data from memory or input of data from an input port. • On the other hand. Therefore. data are either written into memory or output to an I/O device.Minimum Mode Interface ( cont. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. When this line is logic 1 during the data transfer part of a bus cycle..) • The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. • The direction of data transfer over the bus is signaled by the logic level output at DT/R. M. logic 0 at DT/R signals that the bus is in the receive mode. the bus is in the transmit mode. Krishna Kumar MM/M1/LU3/V1/2004 25 .
M. Krishna Kumar MM/M1/LU3/V1/2004 26 . • On the other hand.) • The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. • There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. This is DEN ( data enable) and it signals external devices when they should put data on the bus.. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. one other control signal is also supplied. During read operations.Minimum Mode Interface ( cont. RD indicates that the 8086 is performing a read of data of the bus.
Krishna Kumar MM/M1/LU3/V1/2004 27 . This signal is provided by an external clock generator device and can be supplied by the memory or I/O subsystem to signal the 8086 when they are ready to permit the data transfer to be completed. • INTR is an input to the 8086 that can be used by an external device to signal that it need to be serviced..Minimum Mode Interface ( cont. • Interrupt signals : The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge ( INTA). M.) • READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods.
Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input.. M. it indicates this fact to external circuit with pulse to logic 0 at the INTA output. • If the logic 1 is found. When an interrupt request has been recognized by the 8086. instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. • The TEST input is also related to the external interrupt interface.) • Logic 1 at INTR represents an active interrupt request.Minimum Mode Interface ( cont. Krishna Kumar MM/M1/LU3/V1/2004 28 . The 8086 no longer executes instructions. the MPU suspend operation and goes into the idle state.
• There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the reset interrupt RESET. execution resume with the next instruction in the program.) • As TEST switches to 0. M. The RESET input is used to provide a hardware reset for the 8086. This feature can be used to synchronize the operation of the 8086 to an event in external hardware.Minimum Mode Interface ( cont. • On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. Krishna Kumar MM/M1/LU3/V1/2004 29 .. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine.
Minimum Mode Interface. DT/R. M. RD. it signals to the 8086 by switching HOLD to the logic 1 level. Krishna Kumar MM/M1/LU3/V1/2004 30 . • When an external device wants to take control of the system bus. the 8086 enters the hold state. At the completion of the current bus cycle. • DMA Interface signals :The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. signal lines AD0 through AD15. DEN and INTR are all in the high Z state. M/IO. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level. A16/S3 through A19/S6. In the hold state. WR. BHE.
M. it provides signals for implementing a multiprocessor / coprocessor system environment.Maximum Mode Interface • When the 8086 is set for the maximum-mode configuration. there are some system resources that are common to all processors. • They are called as global resources. These are known as local or private resources. • By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Krishna Kumar MM/M1/LU3/V1/2004 31 . There are also other resources that are assigned to specific processors. • Usually in this type of system environment.
Maximum Mode Interface (cont. M. Krishna Kumar MM/M1/LU3/V1/2004 32 .) • Coprocessor also means that there is a second processor in the system.. facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor. In this two processor does not access the bus at the same time. • One passes the control of the system bus to the other and then may suspend its operation. • In the maximum-mode 8086 system.
QS0 Local bus control RQ / GT1 RQ / GT0 MWTC IORC BCLK Multi Bus Vcc GND LOCK CLK S0 S1 S2 INTR TEST NMI RESET 8086 MPU MN/MX 8086 Maximum mode Block Diagram MM/M1/LU3/V1/2004 33 M. A16/S3-A19/S6 D0 – D15 BHE RD READY QS1.INIT S0 S1 S2 LOCK CLK CRQLCK RESB SYSB/RESB ANYREQ AEN 8289 Bus arbiter BUSY CBRQ BPRO BPRN BREQ CLK AEN IOB IOB CLK AEN IOB S0 S1 8288 Bus S2 controller DEN DT/ R ALE MRDC AMWC IOWC AIOWC INTA MCE / PDEN DEN DT / R ALE A0-A15. Krishna Kumar .
Maximum Mode Interface (cont. S2 prior to the initiation of each bus cycle. • Specially the WR. M/IO. signals are no longer produced by the 8086. I/O and interrupt interfaces.. This 3. DEN. Instead it outputs three status signals S0. M.bit bus status code identifies which type of bus cycle is to follow. ALE and INTA. the bus controller generates the appropriately timed command and control signals.) • 8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory. S1. Krishna Kumar MM/M1/LU3/V1/2004 34 . DT/R. • S2S1S0 are input to the external bus controller device.
AMWC None M. Krishna Kumar MM/M1/LU3/V1/2004 35 .Maximum Mode Interface (cont.. AIOWC None MRDC MRDC MWTC.) Status Inputs S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CPU Cycles Interrupt Acknowledge Read I/O Port Write I/O Port Halt Instruction Fetch Read Memory Write Memory Passive Bus Status Codes 8288 Command INTA IORC IOWC.
it indicates that an I/O read cycle is to be performed. These 3 signals provide the same functions as those described for the minimum system mode. • The control outputs produced by the 8288 are DEN.) • The 8288 produces one or two of these eight command signals for each bus cycles. • In the code 111 is output by the 8086. it is signaling that no bus activity is to take place. Krishna Kumar MM/M1/LU3/V1/2004 36 . DT/R and ALE. M. For instance.Maximum Mode Interface (cont.. when the 8086 outputs the code S2S1S0 equals 001. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems.
Maximum Mode Interface (cont..)
• 8289 Bus Arbiter – Bus Arbitration and Lock Signals : This device permits processors to reside on the system bus. It does this by implementing the Multibus arbitration protocol in an 8086-based system. • Addition of the 8288 bus controller and 8289 bus arbiter frees a number of the 8086 pins for use to produce control signals that are needed to support multiple processors. • Bus priority lock ( LOCK) is one of these signals. It is input to the bus arbiter together with status signals S0 through S2.
M. Krishna Kumar
Maximum Mode Interface (cont..)
• The output of 8289 are bus arbitration signals: bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock (BCLK). • They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086. • In this way the processor can be assured of uninterrupted access to common system resources such as global memory.
M. Krishna Kumar
Maximum Mode Interface (cont..)
• Queue Status Signals : Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0. • Following table shows the four different queue status.
M. Krishna Kumar
Maximum Mode Interface (cont..)
QS1 0 (low) 0 1 (high) 1 QS0 0 1 0 1 Queue Status No Operation. During the last clock cycle, nothing was taken from the queue. First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.
Queue status codes
M. Krishna Kumar
the minimum mode HOLD.) • Local Bus Control Signal – Request / Grant Signals: In a maximum mode configuration..Maximum Mode Interface (cont. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1. M. HLDA interface is also changed. Krishna Kumar MM/M1/LU3/V1/2004 41 . respectively. They provide a prioritized bus access mechanism for accessing the local bus.
all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. M. Krishna Kumar MM/M1/LU3/V1/2004 42 . clock generator. depending upon the address map of the system.Minimum Mode 8086 System • In a minimum mode 8086 system. memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices. • In this mode. transreceivers. • The remaining components in the system are latches.
M.) • Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are required to separate the valid data from the time multiplexed address/data signals. DEN and DT/R. • Transreceivers are the bidirectional buffers and some times they are called as data amplifiers.Minimum Mode 8086 System (cont. Krishna Kumar MM/M1/LU3/V1/2004 43 . • They are controlled by two signals namely. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086..
• Usually.. EPROM are used for monitor storage.e.) • The DEN signal indicates the direction of data. A system may contain I/O devices. while RAM for users program storage.Minimum Mode 8086 System (cont. M. i. The system contains memory for the monitor and users program storage. from or to the processor. Krishna Kumar MM/M1/LU3/V1/2004 44 .
) • The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. Krishna Kumar MM/M1/LU3/V1/2004 45 . • The clock generator also synchronizes some external signal with the system clock. the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation.Minimum Mode 8086 System (cont. M. • It has 20 address lines and 16 data lines. The general system organisation is as shown in below fig..
. • The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts.) • The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. Krishna Kumar MM/M1/LU3/V1/2004 46 .Minimum Mode 8086 System (cont. During the negative going edge of this signal. the valid address is latched on the local bus. the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. • The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. M.
From T1 to T4 . the address is removed from the local bus and is sent to the output. The bus is then tristated.Minimum Mode 8086 System (cont. • The addressed device will drive the READY line high.) • The BHE and A0 signals address low. high or both bytes. the valid data is available on the data bus. • At T2. When the processor returns the read signal to high level. the addressed device will again tristate its bus drivers. • The read (RD) signal causes the address device to enable its data bus drivers.. Krishna Kumar MM/M1/LU3/V1/2004 47 . the M/IO signal indicates a memory or I/O operation. M. After RD goes low. The read (RD) control signal is also activated in T2.
• The M/IO. • The data remains on the bus until middle of T4 state. after sending the address in T1. Krishna Kumar MM/M1/LU3/V1/2004 48 . RD and WR signals indicate the type of data transfer as specified in table below. the processor sends the data to be written to the addressed location.) • A write cycle also begins with the assertion of ALE and the emission of the address.Minimum Mode 8086 System (cont. M.. • The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. In T2. The M/IO signal is again asserted to indicate a memory or I/O operation. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
. Krishna Kumar MM/M1/LU3/V1/2004 49 .Minimum Mode 8086 System (cont.) M / IO 0 0 1 1 RD 0 1 0 1 WR 1 0 1 0 Transfer Type I / O read I/O write Memory read Memory write Data Transfer table M.
Minimum Mode 8086 System (cont. Krishna Kumar MM/M1/LU3/V1/2004 50 .) Clk T1 ALE T2 T3 TW T4 ADD / STATUS ADD / DATA RD DEN DT / R BHE A19 – A16 A15 – A0 S7 – S3 Bus reserved for data in D15 – D0 Read Cycle Timing Diagram for Minimum Mode M..
.Minimum Mode 8086 System (cont. Krishna Kumar MM/M1/LU3/V1/2004 51 .) T1 Clk ALE ADD / STATUS ADD / DATA WR DEN BHE A19 – A16 A15 – A0 S7 – S3 Valid data D15 – D0 T2 T3 TW T4 T1 DT / R Write Cycle Timing Diagram for Minimum Mode M.
Krishna Kumar MM/M1/LU3/V1/2004 52 . M. the HLDA is dropped by the processor at the trailing edge of the next clock. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle. When the request is dropped by the requesting master.) • Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. the bus will be given to another requesting master. the CPU activates HLDA in the next clock cycle and for succeeding bus cycles.Minimum Mode 8086 System (cont.. • The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low.
Krishna Kumar MM/M1/LU3/V1/2004 53 ..Minimum Mode 8086 System (cont.) Clk HOLD HLDA Bus Request and Bus Grant Timings in Minimum Mode System M.
• In this mode.Maximum Mode 8086 System • In the maximum mode. Krishna Kumar MM/M1/LU3/V1/2004 54 . there may be more than one microprocessor in the system configuration. • In the maximum mode. Another chip called bus controller derives the control signal using this status information . the processor derives the status signal S2. M. • The components in the system are same as in the minimum mode system. S1. the 8086 is operated by strapping the MN/MX pin to ground. S0.
MWTC. M. is to derive control signals like RD and WR ( for memory and I/O devices). • It derives the outputs ALE. IOWC and AIOWC. S1. DEN.) • The basic function of the bus controller chip IC8288. DT/R. ALE etc. DT/R. IORC. IOB and CEN pins are specially useful for multiprocessor systems.Maximum Mode 8086 System (cont. S0 and CLK. The AEN.. These inputs to 8288 are driven by CPU. DEN. • The bus controller chip has input lines S2. using the information by the processor on the status lines. AMWC. MRDC. Krishna Kumar MM/M1/LU3/V1/2004 55 .
. CEN pin is usually tied to +5V. • INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.Maximum Mode 8086 System ( cont.) • AEN and IOB are generally grounded. Krishna Kumar MM/M1/LU3/V1/2004 56 . • If IOB is grounded. it acts as master cascade enable to control cascade 8259A. The significance of the MCE/PDEN output depends upon the status of the IOB pin. else it acts as peripheral data enable used in the multiple bus configurations. M.
• For both of these write command signals. M. MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals.) • IORC. IOWC are I/O read command and I/O write command signals respectively .Maximum Mode 8086 System ( cont.. These signals enable an IO interface to read or write the data from or to the address port. Krishna Kumar MM/M1/LU3/V1/2004 57 . • All these command signals instructs the memory to accept or send data from or to the bus. the advanced signals namely AIOWC and AMWTC are available. • The MRDC.
Krishna Kumar MM/M1/LU3/V1/2004 58 .Maximum Mode 8086 System ( cont. but are activated one clock cycle earlier than the IOWC and MWTC signals respectively. • The address/data and address/status timings are similar to the minimum mode.) • They also serve the same purpose. just like minimum mode. • ALE is asserted in T1.. The only difference lies in the status signal used and the available control and advanced command signals. • The maximum mode system timing diagrams are divided in two portions as read (input) and write (output) timing diagrams. M.
.Maximum Mode 8086 System ( cont. Krishna Kumar MM/M1/LU3/V1/2004 59 .) DEN DT/ R S1 IORC 8288 IOWTC S2 MWTC AEN IOB CEN ALE MRDC + 5V CLK A/D Latches Address bus Add bus Clk S0 Control bus Reset Clk Generator RDY 8284 Reset Clk Ready 8086 S0 S1 S2 AD6-AD15 A16-A19 DT/R DIR Data buffer BHE A0 DEN G CS0H CS0L RD WR Memory Data bus CS WR RD Peripherals Maximum Mode 8086 System. M.
M.) • Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.Maximum Mode 8086 System ( cont. Krishna Kumar MM/M1/LU3/V1/2004 60 . S1.. S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1. • R0.
• The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. • If reader input is not activated before T3. 8288 will set DEN=1 thus enabling transceivers.Maximum Mode 8086 System ( cont. For an output.) • In T2.. wait state will be inserted between T3 and T4. the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. M. These signals are activated until T4. and for an input it will activate MRDC or IORC. Krishna Kumar MM/M1/LU3/V1/2004 61 .
) • Timings for RQ/ GT Signals :The request/grant response sequence contains a series of three pulses.. The request/grant pins are checked at each rising pulse of clock input. the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state. M.Maximum Mode 8086 System ( cont. • When a request is detected and if the condition for HOLD request are satisfied. Krishna Kumar MM/M1/LU3/V1/2004 62 . it sends a release pulse to the processor using RQ/GT pin. it accepts the control of the bus. • When the requesting master receives this pulse.
Krishna Kumar MM/M1/LU3/V1/2004 63 ..) T1 Clk AL E S2 – S0 Add/Status Add/Data MRDC DT / R T2 One bus cycle T3 T4 T1 Active BHE.Maximum Mode 8086 System ( cont. A19 – A16 A15 – A0 Inactive S7 – S3 D15 – D0 Active DEN Memory Read Timing in Maximum Mode M.
Maximum Mode 8086 System ( cont.. Krishna Kumar MM/M1/LU3/V1/2004 64 . M.) T1 Clk ALE S2 – S0 ADD/STATUS ADD/DATA AMWC or AIOWC MWTC or IOWC DT / R DEN high Active BHE A15-A0 Inactive S7 – S3 Data out D15 – D0 Active T2 One bus cycle T3 T4 T1 Memory Write Timing in Maximum mode.
Krishna Kumar MM/M1/LU3/V1/2004 65 .) Clk RQ / GT Another master request bus access CPU grant bus Master releases bus RQ/GT Timings in Maximum Mode. M..Maximum Mode 8086 System ( cont.
They are the instruction pointer. with 9 of bits implemented for status and control flags.. four data registers. M.Internal Registers of 8086 (cont.) • The 8086 has four groups of the user accessible internal registers. • The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register. four pointer and index register. four segment registers. Krishna Kumar MM/M1/LU3/V1/2004 66 .
The CS register is automatically updated during far jump.. Krishna Kumar MM/M1/LU3/V1/2004 67 . The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. M.Internal Registers of 8086 (cont. far call and far return instructions. CS register cannot be changed directly. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: • Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. data and extra data. There are four different 64 KB segments for instructions. stack.) • Most of the registers contain data/instruction offsets within 64 KB memory segment.
SS register can be changed directly using POP instruction. M. DS register can be changed directly using POP and LDS instructions. the processor assumes that all data referenced by general registers (AX. BX.) • Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. DX) and index register (SI. CX. Krishna Kumar MM/M1/LU3/V1/2004 68 . the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. By default. By default. DI) is located in the data segment..Internal Registers of 8086 (cont. • Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
usually with program data. • It is possible to change default segments used by general and index registers by prefixing instructions with a CS. the processor assumes that the DI register references the ES segment in string manipulation instructions..Internal Registers of 8086 (cont. DS or ES prefix. ES register can be changed directly using POP and LES instructions.) • Extra segment (ES) is a 16-bit register containing address of 64KB segment. Krishna Kumar MM/M1/LU3/V1/2004 69 . • All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. By default. SS. The general registers are: M.
BL in this case contains the low-order byte of the word. and BH contains the high-order byte. BX register usually contains a data pointer used for based.) • Accumulator register consists of two 8-bit registers AL and AH. which can be combined together and used as a 16bit register AX. which can be combined together and used as a 16-bit register BX.Internal Registers of 8086 (cont.. based indexed or register indirect addressing. M. Krishna Kumar MM/M1/LU3/V1/2004 70 . AL in this case contains the low-order byte of the word. and AH contains the high-order byte. • Base register consists of two 8-bit registers BL and BH. Accumulator can be used for I/O operations and string manipulation.
Count register can be used in Loop. which can be combined together and used as a 16-bit register CX. DL register contains the low-order byte of the word.. shift/rotate instructions and as a counter in string manipulation. • Data register consists of two 8-bit registers DL and DH. Krishna Kumar MM/M1/LU3/V1/2004 71 . In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. M. Data register can be used as a port number in I/O operations. CL register contains the low-order byte of the word. and DH contains the highorder byte.Internal Registers of 8086 (cont.. and CH contains the highorder byte.) • Count register consists of two 8-bit registers CL and CH. which can be combined together and used as a 16-bit register DX. When combined. When combined.
. as well as a source data address in string manipulation instructions. • Base Pointer (BP) is a 16-bit register pointing to data in stack segment. SI is used for indexed.Internal Registers of 8086 (cont. M. BP register is usually used for based. • Source Index (SI) is a 16-bit register.) • The following registers are both general and index registers: • Stack Pointer (SP) is a 16-bit register pointing to program stack. Krishna Kumar MM/M1/LU3/V1/2004 72 . based indexed and register indirect addressing. based indexed or register indirect addressing.
set if the result is too large positive number.) • Destination Index (DI) is a 16-bit register. Krishna Kumar MM/M1/LU3/V1/2004 73 . DI is used for indexed. M. or is too small negative number to fit into destination operand. based indexed and register indirect addressing.. • Overflow Flag (OF) . • Flags is a 16-bit register containing 9 one bit flags. Other registers: • Instruction Pointer (IP) is a 16-bit register. as well as a destination data address in string manipulation instructions.Internal Registers of 8086 (cont.
• Single-step Flag (TF) .set if the result is zero. M. • Interrupt-enable Flag (IF) . • Zero Flag (ZF) . Krishna Kumar MM/M1/LU3/V1/2004 74 .setting this bit enables maskable interrupts.Internal Registers of 8086 (cont.) • Direction Flag (DF) .if set then single-step interrupt will occur after the next instruction.if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. • Sign Flag (SF) .set if the most significant bit of the result is set..
set if there was a carry from or borrow to bits 0-3 in the AL register. • Carry Flag (CF) .set if there was a carry from or borrow to the most significant bit during last result calculation.Internal Registers of 8086 • Auxiliary carry Flag (AF) . Krishna Kumar MM/M1/LU3/V1/2004 75 .set if parity (the number of "1" bits) in the low-order byte of the result is even. • Parity Flag (PF) . M.
references the data in a register or in a register pair.Addressing Modes (cont. Krishna Kumar MM/M1/LU3/V1/2004 76 .. • Based :.the data value/data address is implicitly associated with the instruction. where data is located.instruction specifies a register containing an address. M.the data is provided in the instruction. • Register . • Direct . • Immediate . the resulting value is a pointer to location where data resides. This addressing mode works with SI.8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP).) • Implied .the instruction operand specifies the memory address where data is located. • Register indirect . DI. BX and BP registers.
M. the resulting value is a pointer to location where data resides. • Based Indexed with displacement :.the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI). • Based Indexed :.Addressing Modes • Indexed :. the resulting value is a pointer to location where data resides. the resulting value is a pointer to location where data resides.8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI). Krishna Kumar MM/M1/LU3/V1/2004 77 .8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI).
Memory (cont. • To access memory outside of 64 KB the CPU uses special segment registers to specify where the code. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below).. data and stack memories occupy the same memory space. • 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte M. Krishna Kumar MM/M1/LU3/V1/2004 78 .) • Program.
.) • 32-bit addresses are stored in "segment: offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset • Physical memory address pointed by segment: offset pair is calculated as: • address = (<segment> * 16) + <offset> M.Memory (cont. Krishna Kumar MM/M1/LU3/V1/2004 79 .
.the processor can access data in any one out of 4 available segments. • Data memory .) • Program memory .Memory (cont. which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). • All conditional jump instructions can be used to jump within approximately +127 to -127 bytes from current instruction. as well as for far jumps anywhere within 1 MB of memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment. Krishna Kumar MM/M1/LU3/V1/2004 80 .program can be located anywhere in memory. M.
CS:. Stack or Extra segments can be usually done by prefixing instructions with the DS:.) • Accessing data from the Data. Krishna Kumar MM/M1/LU3/V1/2004 81 . M.Memory (cont.. SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). • Word data can be located at odd or even byte boundaries. Reading word data from even byte boundaries requires only one memory access. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Code.
The stack can be located at odd memory addresses.03FFh are reserved for interrupt vectors. M.FFFFFh . Reserved locations: • 0000h .after RESET the processor always starts program execution at the FFFF0h address.Memory • Stack memory can be placed anywhere in memory. Each interrupt vector is a 32-bit pointer in format segment: offset. Krishna Kumar MM/M1/LU3/V1/2004 82 . but it is not recommended for performance reasons (see "Data Memory" above). • FFFF0h .
) The processor has the following interrupts: • INTR is a maskable hardware interrupt. Interrupt processing routine should return with the IRET instruction.. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>.Interrupts (cont. • When an interrupt occurs. M. Krishna Kumar MM/M1/LU3/V1/2004 83 . fetches from the bus one byte representing interrupt type. disables further interrupts. the processor stores FLAGS register into stack.
) • NMI is a non-maskable interrupt..any one interrupt from available 256 interrupts. Krishna Kumar MM/M1/LU3/V1/2004 84 .interrupt on overflow M. Interrupt type of the NMI is 2. i. • INT <interrupt number> instruction .Interrupts (cont. Interrupt is processed in the same way as the INTR interrupt. This is a type 3 interrupt. • Software interrupts can be caused by: • INT instruction . the address of the NMI processing routine is stored in location 0008h.breakpoint interrupt. • INTO instruction . This interrupt has higher priority then the maskable interrupt.e.
When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. Krishna Kumar MM/M1/LU3/V1/2004 85 . This is a type 1 interrupt. • Software interrupt processing is the same as for the hardware interrupts.generated if the TF flag is set. Unused Opcode (type 6) and Escape opcode (type 7). • Processor exceptions: Divide Error (Type 0).Interrupts • Single-step interrupt . M.
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