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Assembly6x9

Assembly6x9

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Sections

  • 1 Preface
  • 2 Basic Numbering Systems
  • 2.1 Binary
  • 2.2 Hexadecimal
  • 3 Assembly Language Overview
  • 3.1 Instruction Set Architecture
  • 3.2 Assembler
  • 3.2.1 Assembly Language Statements
  • 3.3 Line Format and Naming
  • 3.4 Program Structure
  • 4 Z390 Emulator and Hello World
  • 4.1 The z390 Portable Mainframe Project
  • 4.2 Running the Emulator
  • 4.3 Hello World
  • 4.4 Running Hello World
  • 4.5 Examining Hello.prn
  • 4.6 More Basic Assembly Language Examples
  • 5 Basic Instruction Formats
  • 5.1 Operands
  • 5.2 Operand Notation
  • 5.3 Operand Semantics
  • 5.4 Operand Formats
  • 5.4.1 RR Format
  • 5.4.2 RX Format
  • 5.4.3 RS Format
  • 5.4.4 SI Format
  • 5.4.5 SS Format
  • 5.4.5.1 One 8 Bit Length Field
  • 5.4.5.2 Two 4 Bit Length Fields
  • 6 Basic Addressing
  • 6.1 Explicit Addressing
  • 6.2 Symbolic Addressing
  • 6.3 Machine Language Formats
  • 6.3.1 RR Machine Language Format
  • 6.3.2 RX Machine Language Format
  • 6.3.3 RS Machine Language Format
  • 6.3.4 SI Machine Language Format
  • 6.3.5 SS Machine Language Format
  • 7 Program Status Word (PSW)
  • 7.1 Layout
  • 7.2 Addressing modes
  • 7.3 Condition Code
  • 7.4 Program Mask
  • 7.5 Problem / Supervisor State Bit
  • 7.6 Instruction Addressing
  • 8 Flow of Control & Branch Instructions
  • 8.1 Conditional Branching (BC, BCR)
  • 8.2 Branch and Link Instructions
  • 8.2.1 BAL and BALR - Branch and Link
  • 8.2.2 Branch and Save - BAS and BASR
  • 8.2.3 Branch Relative and Save - BRAS, BRASL
  • 8.3 Looping Branch Instructions
  • 8.3.1 Branch Index Low, Equal, High - BXLE, BXH
  • 8.3.2 Branch on Count - BCT (RX) and BCTR (RR)
  • 9 Data Types
  • 9.1 Arithmetic Data
  • 9.1.1 Packed Decimal and Zoned Decimal Format Data
  • 9.1.2 Binary Integers and 2s Complement
  • 9.1.3 Nomenclature
  • 9.1.4 Threshold Binary Values
  • 10 Data Declarations
  • 10.1 Declare Constant and Declare Storage (DC and DS)
  • 10.2 Literals
  • 11 Linkage
  • 11.1 Linkage Registers
  • 11.2 Save Area
  • 12 Assist Macro Input/Output
  • 12.1 Input / Output using XREAD and XPRNT
  • 12.2 XDUMP
  • 12.3 XDECO/XDECI
  • 12.4 XHEXO/XHEXI
  • 13 Integer Arithmetic
  • 13.1 Program to Add Numbers
  • 13.2 Analyzing the PRN File
  • 13.3 Debugging (XDUMP)
  • 13.4 Data Addressing Alternatives
  • 13.5 More Addressing Alternatives
  • 13.6 Using Extended Mnemonics
  • 14 Other Binary Arithmetic Instructions
  • 14.1 Subtraction
  • 14.2 Halfword Instructions
  • 14.3 Condition Codes After Binary Operations
  • 14.4 Overflows
  • 14.5 Unsigned Arithmetic (AL, ALR, SL, SLR)
  • 14.6 Multiply (M, MR)
  • 14.7 Divide (D, DR)
  • 15 Character Instructions
  • 15.1 Basic Character Instructions
  • 15.1.1 Moving Characters (MVC)
  • 15.1.2 Move Immediate (MVI)
  • 15.1.3 Compare Logical Characters (CLC)
  • 15.1.3.1 Compare Logical Immediate (CLI)
  • 15.2 Character Long Instructions
  • 15.2.1 Compare Logical Character Long (CLCL)
  • 15.2.2 Move Character Long (MVCL)
  • 15.3 Translate (TR) and Translate and Test (TRT)
  • 16 Miscellaneous Register Operations
  • 16.1 Load (L)
  • 16.2 Load (LR)
  • 16.3 Store (ST)
  • 16.4 Load Multiple (LM)
  • 16.5 Store Multiple (STM)
  • 16.6 Load and Test (LTR)
  • 16.7 Load Positive (LPR)
  • 16.8 Load Negative (LNR)
  • 17 Bit Operations
  • 17.1 Boolean Instructions
  • 17.1.1 AND (N, NR, NI, NC)
  • 17.1.2 OR (O, OR, OI, OC)
  • 17.1.3 Exclusive OR (X, XR, XI, XC)
  • 17.2 Complement LCR
  • 17.3 Shift
  • 17.3.1 Logical (SRL, SRDL, SLL, SLDL)
  • 17.3.2 Arithmetic (SRA, SRDA, SLA, SLDA)
  • 17.4 Test Under Mask (TM)
  • 17.5 Test and Set (TS)
  • 18 Decimal Arithmetic
  • 18.1 PACK
  • 18.3 Multiply Packed (MP)
  • 18.4 Divide Packed (DP)
  • 18.5 EDIT (ED)
  • 18.6 Miscellaneous Decimal Related Instructions
  • 18.6.1 UNPACK (UNPK)
  • 18.6.2 Move Numerics (MVN)
  • 18.6.3 Move Zones (MVZ)
  • 19 Multiple Base Registers
  • 19.1 Base Register Addressing
  • 20 System Macro Input/Output
  • 21 Converting Between Zoned, Packed and Binary
  • 22 Programming Examples
  • 22.1 Console Input/Output
  • 22.2 Random Numbers
  • 22.3 Convert Infix to Suffix
  • 22.4 Bubble Sort a Table of Numbers
  • 22.5 Search for Prime Numbers
  • 22.6 Print a String in Hexadecimal
  • 22.7 Word Count Program
  • 23 General Instruction Set

Basic IBM Mainframe Assembly Language Programming

by

Kevin C. Ó Kane

1

Copyright © 2011 by Kevin C. Ó Kane. All rights reserved. The author may be contacted at: kc.okane@gmail.com Department of Computer Science The University of Northern Iowa Cedar Falls, Iowa 50614-0507 http://www.omahadave.com

Graphics and production design by the Threadsafe Publishing & Railway Maintenance Co. Hyannis, Nebraska

Revision: 1.01 June 20, 2011 Text formatted using Open Office 3.3.0

2

Table of Contents
1 Preface ................................................................................................................9 2 Basic Numbering Systems................................................................................11 2.1 Binary..............................................................................................................11 2.2 Hexadecimal....................................................................................................11 3 Assembly Language Overview........................................................................15 3.1 Instruction Set Architecture.............................................................................15 3.2 Assembler........................................................................................................16
3.2.1 Assembly Language Statements...........................................................................17

3.3 Line Format and Naming.................................................................................18 3.4 Program Structure............................................................................................18 4 Z390 Emulator and Hello World....................................................................21 4.1 The z390 Portable Mainframe Project.............................................................21 4.2 Running the Emulator......................................................................................21 4.3 Hello World.....................................................................................................22 4.4 Running Hello World......................................................................................23 4.5 Examining Hello.prn.......................................................................................24 4.6 More Basic Assembly Language Examples ...................................................25 5 Basic Instruction Formats...............................................................................27 5.1 Operands..........................................................................................................27 5.2 Operand Notation............................................................................................27 5.3 Operand Semantics..........................................................................................28 5.4 Operand Formats.............................................................................................28
5.4.1 RR Format............................................................................................................28 5.4.2 RX Format............................................................................................................28 5.4.3 RS Format............................................................................................................29 5.4.4 SI Format..............................................................................................................29 5.4.5 SS Format.............................................................................................................29 5.4.5.1 One 8 Bit Length Field..................................................................................29 5.4.5.2 Two 4 Bit Length Fields................................................................................30

6 Basic Addressing...............................................................................................31 6.1 Explicit Addressing.........................................................................................31 6.2 Symbolic Addressing.......................................................................................33 6.3 Machine Language Formats............................................................................35
6.3.1 RR Machine Language Format.............................................................................35 6.3.2 RX Machine Language Format.............................................................................36 6.3.3 RS Machine Language Format.............................................................................37 6.3.4 SI Machine Language Format...............................................................................38 6.3.5 SS Machine Language Format..............................................................................39

7 Program Status Word (PSW)..........................................................................41 7.1 Layout..............................................................................................................41 7.2 Addressing modes...........................................................................................41
3

..........65 12.......51 9.....................................................................................................................................................................................................................................46 8............................................................................................83 14.............................61 12 Assist Macro Input/Output...........75 13...............6 Using Extended Mnemonics............................................................................5 More Addressing Alternatives.........................7..................2 Halfword Instructions.......................55 10 Data Declarations..................2 Literals ..................................................49 9 Data Types......84 14....................................6 Instruction Addressing.............................83 14.................................................57 10...................................2 Branch and Link Instructions..............59 11 Linkage.......................................61 11...57 10................................. SL........................................................55 9.......79 13...............................................................................................................................................1..........5 Unsigned Arithmetic (AL........66 12........1................................46 8...........................................................1 BAL and BALR ....................83 14..................................................................1 Branch Index Low...............1 Arithmetic Data..........................2 Binary Integers and 2s Complement....3 Looping Branch Instructions.........4 Threshold Binary Values......... BRASL...............1 Subtraction..............79 13........................................2 Analyzing the PRN File......BAS and BASR...............................................................................47 8.....................................47 8...........................Branch and Link ............................................................. BCR).....................2 XDUMP..................61 11........................2 Branch on Count ....1................................................1 Program to Add Numbers..........................................42 8 Flow of Control & Branch Instructions.......................................................................................................................................................3 Branch Relative and Save ............83 14.....................42 7............................................................1 Linkage Registers...................................................1 Declare Constant and Declare Storage (DC and DS)................BCT (RX) and BCTR (RR).........5 Problem / Supervisor State Bit.........47 8...............69 13................................................................................................2......................83 14........3 Condition Code....................69 13........................4 Overflows.......................................................................................................43 8...3 Debugging (XDUMP)...4 Data Addressing Alternatives......................1 Packed Decimal and Zoned Decimal Format Data..................................................................................6 Multiply (M..................2..........................80 14 Other Binary Arithmetic Instructions....................................................3.....................72 13.........2 Save Area................................1.........1 Input / Output using XREAD and XPRNT......................................2.3................................4 XHEXO/XHEXI....................................................BRAS......................................41 7..........................................................................................................84 4 ..........3 XDECO/XDECI....................... ALR............... Equal...... BXH...................BXLE.41 7.................................4 Program Mask.................................. High .................................51 9............... MR)........................65 12..........................................3 Nomenclature..............67 13 Integer Arithmetic .............................47 8...............51 9..66 12................................ SLR)..43 8..........................................................................3 Condition Codes After Binary Operations.2 Branch and Save .....................................1 Conditional Branching (BC......................52 9............................................................................................................................

..................................4 Load Multiple (LM)..............1 Base Register Addressing ...............95 16................................................5 Test and Set (TS) ............................................................. Zero and Add Positive (AP.................................................................................................................................97 17......................................87 15.................................... SLA........................................95 16......................8 Load Negative (LNR).................................2........................................................................................................................1 Logical (SRL.6.......6.....97 17.....................7 Divide (D.....................................................................87 15.......... SLDA) .........................97 17....................................1 Load (L)..............3 Compare Logical Characters (CLC).................1................... NI.....................................................................................................................101 18................95 16.................88 15.......................103 18... SRDL......................... SRDA...............100 17.....87 15............98 17...............................85 15 Character Instructions...................3 Translate (TR) and Translate and Test (TRT)............................................................. SLDL) ........99 17...........................................................................................................89 15....2 Move Numerics (MVN).............................................96 16.....................3 Multiply Packed (MP).................................................6 Miscellaneous Decimal Related Instructions. SLL............ DR)...1 PACK..101 18..2 Move Immediate (MVI)..102 18..............................................1 AND (N............1.....2 Complement LCR ....................................1.. SP...................2 Add...................................................................................................................................................................................2 OR (O........................................................... OI.........3 Store (ST)..................1.....................5 EDIT (ED)..2 Load (LR)......................105 19....................................................................2 Arithmetic (SRA.....90 15.................................1 Boolean Instructions.....................................................................................103 18...................7 Load Positive (LPR)......................5 Store Multiple (STM)..................................................109 21 Converting Between Zoned................................... XI...........................3 Move Zones (MVZ)..........96 17 Bit Operations.4 Divide Packed (DP).........................................................................................1 Moving Characters (MVC)......................................................................................................................................................................... Packed and Binary ....................1..........................111 5 ........................................14.........100 17.......................1 Basic Character Instructions.........90 16 Miscellaneous Register Operations.............89 15.....................97 17............................................................2 Character Long Instructions..1 Compare Logical Immediate (CLI)...................2 Move Character Long (MVCL).......................................95 16....1........................................................................102 18.................................................................................................................95 16..........3 Exclusive OR (X................................102 18...............6 Load and Test (LTR)......3 Shift................103 18............................................................ XC)............................................101 18 Decimal Arithmetic.96 16.........................................3..........................95 16............... XR.....6........3.................................... NR.......................98 17....................3...................................................4 Test Under Mask (TM) .......105 20 System Macro Input/Output ........103 19 Multiple Base Registers.99 17...... Subtract............ NC)....................101 18.........87 15........ ZAP)............................................ OC)...........89 15.......................................1 UNPACK (UNPK)....... OR...............1.......................2..............................1 Compare Logical Character Long (CLCL).....................................................................................

.............................3 Convert Infix to Suffix ....117 22.........126 22.....................................22 Programming Examples.....120 22............................2 Random Numbers...135 6 .......................................1 Console Input/Output...................................................................................................................5 Search for Prime Numbers.......................................................6 Print a String in Hexadecimal......................................................................................................................................................................................................122 22.....................7 Word Count Program...................................................................................4 Bubble Sort a Table of Numbers..............................117 22...............125 22.........................118 22..128 23 General Instruction Set........

.........................52 Table 12 Powers of two.......................77 Figure 33 ADD1................................50 Figure 19 Example DS/DC statements.........A Hollerith/IBM Punched Card...58 Figure 20 Literals........................92 Figure 41 TRT Verifying Input.........12 Table 3 Conversion from Hex to Decimal...............11 Table 2 Hex to Decimal Conversion................RR Examples............38 Figure 15 SS Machine Language Format......PRN...................................................34 Figure 10 ................32 Figure 9 ..............81 Figure 35 Loop example........45 Table 9 Extended mnemonics................................................93 Figure 42 Multiple Base Registers.........88 Figure 39 TRT Table with ORG......................................................................................................45 Table 8 Decimal mask equivalents.....................................35 Figure 11 RR Machine Language Format.............................13 Table 5 Condition Code after signed Add.....124 Figure 52 Search for Prime Numbers.118 Figure 48 Random Numbers in C...Alternative 2...........69 Figure 24 ADD................................MLC Step 2...119 Figure 50 Convert Infix to Suffix.....81 Figure 36 MVC Examples.....................................Alternative 1................................................................80 Figure 34 ADD2.................88 Figure 38 CLC Examples ..91 Figure 40 TRT Example............................................MLC Step 1......................126 Figure 53 Print Hex Equivalent...............36 Figure 12 RX Machine Language Format...............129 Figure 54 Dictionary Program..61 Table 17 Save area.......23 Figure 3 Assemble and run Hello World........................................................................................................................65 Figure 23 ADD...............................36 Figure 13 RS Machine Language Format...71 Figure 27 ADD................................................................................53 Table 14 Binary nomenclature.........122 Figure 51 Bubble Sort....137 Index of Tables Table 1 Numbering Systems......................................73 Figure 31 Add program exposed...............................MLC Step 4..........................................................................................................................................49 Figure 18 BCT loop example.........................................62 Figure 22 XREAD example.37 Figure 14 SI Machine Language Format....................................................................................................................................115 Figure 46 Example Execution...................................70 Figure 25 ADD................MLC Step 3.......32 Figure 8 .71 Figure 28 ADD.............................51 Table 11 Example packed decimal numbers.............................70 Figure 26 ADD.........132 Figure 55 Over-Extended Instructions (humor)...........87 Figure 37 MVI Examples..........................................................113 Figure 45 Negative Decimal Arithmetic...106 Figure 43 QSAM Input/Output............111 Figure 44 Decimal Arithmetic.........................................................44 Table 6 Mask settings after a signed add.......................76 Figure 32 ...............25 Figure 5 Example program..................119 Figure 49 Random Number Generator................26 Figure 6 .....39 Figure 16 BC example.....Dump format.................................Example symbolic addressing....................................................................MLC Step 5..................................44 Table 7 Decimal mask settings...............44 Figure 17 BXLE loop example...........Explicit addressing.............................MLC Step 5......62 Table 18 Conditions Codes..Example memory addressing...........................................................13 Table 4 Decimal to Hex Conversion...............................................24 Figure 4 Macro expansion.............................53 Table 13 Decimal value of a binary number...............................59 Figure 21 SUBENTRY code........................................................................................................72 Figure 30 ADD..116 Figure 47 Console I/O using WTO/WTOR.............................Index of Figures Figure 1 ............................84 Table 20 General Instructions..........................72 Figure 29 ADD.................................135 7 ........................................MLC Step 5..............MLC ........31 Figure 7 Memory operand.........83 Table 19 CC after logical add/subtract...19 Figure 2 Hello World.............56 Table 15 DS/DC Data Types....................46 Table 10 Numeric data types............MLC ...............58 Table 16 Linkage registers........

8 .

This was a family of computers designed to meet a wide range of applications both scientific and commercial. While most computer users are familiar with the ubiquitous Intel microprocessor line. and ARCHLVL3 (System z10 machines). ARCHLVL2 (zSeries and System z9 machines). 2. are fully backward compatible with the earliest of the 360 series. even the most recent. Many computer architectures have come and gone in the past 50 years and only a few designs remain to this day. At present. However. with each new generation. however. along with the portable. Java based z390 emulator. as the x86 architecture has become an increasingly more complex collection of exceptions and special cases. the question of which assembly language architecture to teach in an introductory course in computer organization has arisen. however. there are three architecture levels named: ARCHLVL1 (ESA 390 systems). the IBM mainframe. additional facilities and instructions were added. This text seeks to address this need by giving the reader a basic understanding of the underlying mainframe architecture from the level of the instruction set. seeks to provide a real world alternative. Simultaneously. Linux and virtual hosting applications. to give the reader a basic understanding of the IBM mainframe architecture from the perspective of the instruction set architecture and to serve as an assembly language text for introductory college courses in computer organization. for the most part. as mainframe sales have grown rapidly and it is being increasingly deployed in large. mission critical applications.1 Preface The purposes of this book are: 1. In its latest models. These are referred to as architecture levels. the demand for programmers to maintain and develop new code is growing. as the programmers who wrote the billions of lines of mainframe assembly code since the introduction of the 360 in 1964 begin to retire. The current series of IBM mainframes (System z10) had its origins in the 1964 with the introduction of the IBM 360 Series of machines. few are aware of the other widely used architecture. These reflect the additions to the original design which are. The system was conceived as a series of compatible machines ranging from small basic machines to large. 9 . consistent with the original intent. All models of the IBM mainframe. enterprise level configurations. This text. In many cases this is solved by the use of simulators for non-existent. both 64 bit addressing and 64 bit data are supported. In recent years. This book will deal mainly with the basic architecture for simplicity concentrating mainly on the original instruction formats. Similarly. The original architecture was based on a 24 bit address (16 MB address space) and 32 bit data. abstract RISC based architectures. cloud computing. open sourced.

The z/Architecture was introduced in 2000 and is represented by machines in the z9 and z10 families. It is a 64 bit CISC (complex instruction set computer) architecture with sixteen 64/32 bit general purpose registers. Document Number: SA22-7832-03 (05/04/04) presently to be found at: http://publibz.z390.ibm.com/cgi-bin/ bookmgr_OS390/BOOKS/DZ9ZR003/CCONTENTS 10 . In this book will deal mainly with 31 bit addressing and the z390 framework in order to be compatible with the free z390 emulator and assembler: http://www. sixteen bit access registers. Memory addressing is implemented as either 24.boulder. 31 or 64 bits although much legacy programming is in 24 bit mode. sixteen 64 bit floating point registers. and sixteen 64/32 bit control registers.org/ Which corresponds to the definition as found in the IBM z/Architecture Principles of Operation.

Any decimal integer can be represented exactly by a corresponding binary number. the binary series which is equivalent to the decimal number 10 is: 1*23 (810) + 0*22 (410) + 1*21 (210) + 0*20 (110) or. instructions. pointers and so forth. Binary numbering consist of only two digits: 0 and 1.2 Hexadecimal Internally. This table shows the equivalence between the first 16 binary.1 Binary The IBM mainframe.see below) numbers and the corresponding sum of the powers of 2. as is the case with all other modern digital computers. When writing a number. stated as a single number. decimal. each position. hexadecimal (base 16 .2 Basic Numbering Systems 2. For example. most modern computer memories are organized as a collection of 8 bit bytes. uses an internal binary representation for numbers. Each binary number is a sum of a series of values of powers of two. characters. reading from right to left. Representing the contents of bytes as binary numbers yields 11 . 10102 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F 3 3 2 Power of 2 20 21 21+20 22 22+20 22+21 2 +21+20 23 2 +20 23+21 23+21+20 23+22 23+22+20 23+22+21 2 +22+21+20 Table 1 Numbering Systems 2. represents a higher power of two as shown in Table 1.

the contribution of that digit as expressed in decimal. we can represent the content of a byte in base 16. Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal Equivalent by Digit Position 0 268435456 536870912 805306368 1073741824 1342177280 1610612736 1879048192 2147483648 2415919104 2684354560 2952790016 3221225472 3489660928 3758096384 4026531840 8 0 16777216 33554432 50331648 67108864 83886080 100663296 117440512 134217728 150994944 167772160 184549376 201326592 218103808 234881024 251658240 7 0 1048576 2097152 3145728 4194304 5242880 6291456 7340032 8388608 9437184 10485760 11534336 12582912 13631488 14680064 15728640 6 0 65536 131072 196608 262144 327680 393216 458752 524288 589824 655360 720896 786432 851968 917504 983040 5 0 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 4 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 Position Table 2 Hex to Decimal Conversion Each four bit binary number can be immediately converted to its hexadecimal equivalent by simple substitution. noting that a byte consists of two 4 bit fields. conversion between base 16 and base 2 and vice versa is trivial. however. you need to add the contribution of each hex digit. E. B. When you want the decimal equivalent of a hex number. Since 16 is itself a power of two. D. if you have a binary number such as: 000 0001 1010 1011 0010 0011 0111 1000 Using the values from Table 1. In base 16 we need 16 symbols to represent the digits of the numbering system (the equivalent of 010 through 1510). it can be converted to decimal by adding the decimal equivalent contributions of each of the hex digits as shown in Table 3. a table such as that in Table 2 is useful. representing the values 1010 through 1510. it can be represented in hex as: 000 0001 1010 1011 0010 0011 0111 1000 0 1 A B 2 3 7 8 Conversion from a hexadecimal (hex) number to its equivalent decimal notation. C. we use the same symbols as the decimal numbering system (0 through 9). requires more work because there is a fundamental change in base. for each hex digit position (up to an eight digit hex number). So. However.inconveniently long sequences of 1s and 0s. For the first 10 digits. To do this. if you have the hexadecimal number such as: 01 AB 23 78. Thus. and F. It gives. For digits above nine. 12 . we use the upper (or lower) case letters A.

Conversion from decimal to hex can be done in several ways. For example. another method to convert between binary. if you have Table 2. insert a zero in the skipped position. this can be rendered in hex as shown in Table 4. is to successively find the largest decimal value in the table and subtract it from your decimal number. 0 1 A B 2 3 7 8 0 16777216 10485760 720896 8192 768 112 8 27992184 Position 8 Position 7 Position 6 Position 5 Position 4 Position 3 Position 2 Position 1 Decimal equivalent of 01AB2378 Table 3 Conversion from Hex to Decimal Of course. If you skip a hex position in the process. 123456789 6016277 773397 52501 3349 21 5 Subtract 117440512 hex digit 7 position 7 Subtract 5242880 hex digit 5 position 6 Subtract 720896 hex digit B position 5 Subtract 49152 hex digit C position 4 Subtract 3328 Hex digit D position 3 Subtract 16 hex digit 1 position 2 Subtract 5 hex digit 5 position 1 Result: 07 5B CD 15 Table 4 Decimal to Hex Conversion 13 . The corresponding hex digit is retained as part of the answer. if you have the decimal number: 123456789. decimal and hexadecimal is to use the programming mode of a calculator such as that which comes with Ubuntu. The easiest.

14 .

They can range from 010 (0000 0000 00002 or 00016) to 409510 (1111 1111 11112 or FFF16). For the most part. The 12 bit displacements are always treated as positive numbers. a register operand is always specified in field of 4 bits. If an operand is in memory. 4 or 6 bytes long. Following the opcode is one or more (usually two) operand specifications.1 Instruction Set Architecture In the original IBM S/360 architecture. the maximum number of unique opcodes is 256 (2 raised to the eighth power). These are the binary codes between 00002 (010) and 11112 (1510). Each instruction consists of an opcode (operation code) which tells the CPU which instruction to execute followed by one or more operands which tell the CPU what data the instruction works upon. A program in memory consists of a series of instructions coded in binary. In all instructions. Originally. since there are 8 bits in a byte. displacements were always 12 bit unsigned numbers (in newer systems. Registers are very high speed memory locations located in the CPU. In base/displacement addressing. in newer implementations. Some instructions work only on the lower 32 of these bits while others work on all 64. they were 32 bits in length but on more recent machines they are 64 bits long. There are 16 general purpose registers. Each operand specification indicates if the operand is in memory. the basic architecture uses an addressing scheme known as base/displacement addressing. in a register or a constant.3 Assembly Language Overview 3. each instruction is either 2. there were six basic instruction formats and these are still the basis of many of the instructions in use today as well as the model for many of the newer formats. Originally. two bytes are used for some opcodes and the total number of permissible opcodes is now very much larger than the original 256. In the basic architecture. not all possible codes were originally used. the address of the operand in memory is calculated by adding the contents of a register with a constant called a displacement. 20 bit signed displacements are possible). These are used mainly for integer calculations and for addressing. we will work only with 32 bits. There are two classes of registers: general purpose registers and floating point registers. However. In actual practice. The floating point registers are used to perform floating point calculations and are not discussed in this book. The general purpose registers are addressed by a number between 0 and 15. The first byte is always the opcode. 15 . As a result. The opcode is a numeric value that indicates which instruction is to be executed.

Instead of coding a base and displacement. it means there is no index register. Instead of coding an Add instruction as 5A16 we use the mnemonic symbol A. The assembler calculates and inserts the correct base and displacement. we say that assembly language is a low level language and C/C++ is a high level language. the base register is loaded with an absolute memory address usually near the starting point of the program. When we write in assembly language.2 Assembler It is technically possible (although very tedious) to write programs in binary or hexadecimal. Thus. In the very earliest days of computing. The end result is a binary coding of our program but with a lot less effort on our part. in many cases. some instructions have what is called an index register. however. when a program is loaded into memory. each line usually consists of a single instruction to be executed. it would always need to be loaded at the same place in memory. The contents of the index register are added along with the contents of the base register and the displacement to calculate an address. we use labels attached to data areas in our program. To improve productivity. this was normally the case. Index registers are useful for array manipulation where the base/displacement points to the start of an array and the index register is used to give an offset from this point into the array. the ability to place a program anywhere in memory. That is. However. This would make it very difficult for a computer to run multiple programs at the same time because programs might compete for the same memory locations. if register zero is specified as an index register. The assembler translates our symbolic representation into binary. Compare this to a line of code written in a language such as C or C++ where a single line of code may require many instructions to be executed. In addition to base/displacement. a different value will be loaded into the base register and the operands will be likewise relocated. Since operand addresses are calculated relative to the base register. Any register can be used as a base register except register zero. If a program used actual memory address constants to specify operand addresses.The purpose of base/displacement addressing is to achieve program relocatability. we use symbols for the instructions. However. they will be correct if the base register is correct. Base/displacement addressing makes it possible to load a program anywhere in memory. people soon developed a class of programs known as assemblers whose purpose it was to allow programmers to write in a symbolic language and leave the job of translating the symbolic code into binary to the assembler. Register zero never participates in address arithmetic. Memory addresses are all calculated relative to the contents of the base register. For this reason. when we write a program in assembly language. When we write in a high level language the compiler selects the instructions to execute. If the program is placed somewhere else in memory. Thus. 3. we might be able to specify a more efficient 16 .

1 Assembly Language Statements There are basically four classes of statements in an assembly language program: 1. disk resident code modules that contain segments of frequently used code.) 3. in rare cases. These are statements. 2. Instruction statements. that a DS or DC statement may. While these statements affect the way in which your machine language program is generated. Macros statements. high level languages increase programmer productivity but low level languages can increase program efficiency.designate a base register. in fact. end of the source module. .placement of literal pool.start or continue control section. This module is nearly executable lacking only library routines and internal address linkages (for example. Thus. B. .declare constant). generally speaking. Macros are small. adjust location counter. a programmer working in a high level language will probably accomplish more per day than someone working in a low level language. These are statements that inform or direct the assembler. These are statements that tell the assembler to reserve memory in the run time module for data. the number of lines of code a programmer does per day is invariant with regard to language used. usually designating data in memory or registers upon which the instruction operates (for example. Assembler directives.sequence of instructions. 3. On the other hand. This is not common. we insert the macros containing the code into our programs. resolution of subroutine call addresses). The main assembler directive we will use are: A. The data may be uninitialized (DS statement . . All instructions have one or more operands. So. each data allocation statement results in data areas being incorporated into the run time module Note: it is possible. 17 . they do not normally result the generation of code or data. F. 4. G. D.2. C.declare storage) or initialized (DC statement . one per line. not generate any data as we will see in Figure 54 on page 132. (Note: an executable module on disk usually still requires some final adjustments as it is loaded into memory for execution. The output of the assembler (or a compiler. add the contents of one register to another). Rather than write the code new each time.assembler print options. define one symbol to be the equivalent of another. For the most part. for that matter) is a binary object module consisting of instructions and data. however. USING END EQU LTORG CSECT ORG PRINT . E. To build a final executable module we employ a program known as the link editor or loader which resolves these and either creates an executable on disk or loads the executable into memory. Each instruction statement results in machine code being generated in the run time module. which will be translated into machine language for execution at run time. Data Allocation statements (DS/DC).

9.3 Line Format and Naming Historically. If an operand is so long that it would extend beyond column 71. Comments may not extend beyond column 71. the remainder of the line is a comment. begin in column sixteen and may not include embedded blanks except within quoted strings. 4. 3. There may be at most two continuation cards. place a character (usually an X) in column 72 and continue the operand on column sixteen of the next line. most assembly programmers follow the original format to this day: 1.4 Program Structure The basic structure of a program will be: 1. 8. Labels begin in column one and are from one to eight characters in length The first character of a label is either a letter in the range A through Z. $.From the program level. data allocation statements and assembler directives but they may also contain statements in the macro language itself. 5. 6. 3. Although there may have been some relaxation in the format in recent years. it is first read by the macro preprocessor. Blank lines are ignored but are part of the overall line count. If column 1 one is an asterisk. Internally. Characters after the first character may be any of the above as well as digits in the range 0 through 9. The mnemonic (short abbreviation) for the operation code or assembly directive begins in column ten. macros may be a combination of instructions. # or @. Before your program is processed by the assembler. After the operands and one blank. The macro preprocessor inserts the macros into your program and executes and macro commands written in the macro preprocessor language. Introductory assembler directives and register renaming macros such as: PRINT NOGEN EQUREGS The assembler directive (PRINT) determines what information the 18 . if any. 10. macros look very much like instructions. comments may be written. 2. assembly language programs were punched on 80 column cards and followed a format consistent with that media. Operands. 3. 7.

Figure 1 . Your program may have more than one instance of SUBEXIT. An entry linkage macro: SUBENTRY This macro establishes your base register and linkage to the calling program and performs a number of tedious housekeeping functions. 3. The EQUREGS is the name of a macro on disk whose contents will be inserted at this point. These can include binary variable. R1. The data area. when specifying registers.A Hollerith/IBM Punched Card 19 . .. Unless you specifically tell the assembler that R1 means 1.. 3.. pointers. You may also specify initial values for data areas as well. Macros are small. R2. Usually the data area consists of multiple labeled statements declaring what would be called variables in a high level languages. This macro tells the assembler that if you use symbols such as R0. etc. 1. R3. you can't do this. 2.assembler will show in its printout of your program. 2. In an assembly language program you tell the assembler how much data to reserve for program use. and others.. Each of these statements causes the assembler to reserve a specific number of bytes in the run-time module. frequently used segments of code stored on disk for re-use. 4. Most programmers prefer to use R1. character strings. . that you mean 0. The program code appears at this point followed by the exit macro SUBEXIT which returns to the calling program.

20 .

2 Running the Emulator There are several ways to run the emulator. The results are the same but the examples used in this book were done in command prompt mode.org/ where the Java code for the project can be found. and other platforms supporting the J2SE runtime. you need to add some information to your systems program search path." (from the web site): http://www. it may be all highlighted and this means that if you type something.Enable z390 and zcobol users to compile. assemble. The emulator can be run either in a graphical user window or from a command prompt.. The purpose of this is so you can execute the emulator from any directory. This assumes that you have installed the z390 emulator in the directory noted. the emulator may have been installed in "Program Files (x86)" 21 . Be careful. GPL project to ". You will see the current contents of the Path environment variable.zip. Click OK and close the windows. download the most recent setup. you will be replacing the entire contents . then click the Edit button. In the lower window.4 Z390 Emulator and Hello World 4.. At the end of the values for the Path variable. click it.z390. Note: if you have a 64 bit version of Windows. First. If you do. and execute mainframe COBOL and assembler problem state programs with minimum source code changes using Windows. add the following: .do not do this.. The examples in this text were developed using this package. You should consult the documentation for details. quickly hit cancel and start again.exe file contained therein. In this section we show how to run the emulator in a command prompt window. 4. link.1 The z390 Portable Mainframe Project The z390 portable mainframe macro assembler and emulator project is a Java based. Linux. not just the one containing the actual code. Go to: Start | Settings | System | Advanced Settings and click on the Environment Variables button.C:\"Program Files"\"Automated Software Tools"\z390.. To install the software. unzip and execute the setup.. scroll down to the Path line.

When finished. including blanks. the first few lines of an assembly program deal with assembler directives and linkage: connecting your program with the program that called it.3 Hello World Now it's time to write the usual Hello World program as shown in Figure 2. type cmd into the run box.mlc A window will open in which you can type your program and save it when done. Be careful that you type it exactly. A command window should appear. Close does not count. In Properties. click OK. A typical macro can be from 3 to hundreds of lines long. type: mkdir asmdir where asmdir is the name you chose. You probably want this to be at least double the screen height. width and position. Macros are code segments stored on a system library designed to perform common. You will probably want to tailor this window so it is larger than its default size. repetitive tasks and to simplify program development. As the macro is inserted into your program. establishing a base register for your program and creating a save area. You may also want to adjust the colors if you prefer something other than white text on a black background. This can usually be found in Start | Programs | Accessories | Command Prompt Alternatively. To create a directory. Normally this is done with macros. click Layout and adjust the window size. The prompt in the command window should identify the directory path to your default user directory. Next. In the command window. The buffer width should be the same as the screen width. locate your system's command prompt icon. Enter the directory with the command: cd asmdir 4. This involves saving the calling program's registers so they can be restored at exit. Macros look like machine instructions but are directives to the assembler to insert and process code elements into you program. start notepad with the command: notepad hello. Right click the top bar and the click Properties. 22 . You will probably want to create a directory in which you will place your assembly language programs.and you will need to add (x86) to the "Program Files" in the above. You may want to leave this window open in the event you need to make corrections. The Screen Buffer Size Height is the number of lines to remember at any given time. Structurally.

The directive PRINT NOGEN is a note to the assembler. the assembler will show the contents of the of the macro expansion (usually not very interesting).L'MSG SUBEXIT DC C'Hello World!' END Figure 2 Hello World Another macro.it may be tailored or altered by the macro preprocessor. L'MSG is assembler short hand that evaluates to the value of the length attribute of the label after the L' figure which. The z390 emulator provides a macro called SUBENTRY that establishes your program's linkage. the address of the field to be printed is given as MSG and the length as L'MSG. The purpose of EQUREGS is to make codes such as R1 and so forth the equivalent of their number part. The program in Figure 2 writes the phrase Hello World returns to the operating system. R3 and so forth as the equivalent of 1. EQUREGS. causes the assembler to accept notation such as R1. 2. Most programmers prefer to refer to the general purpose registers as a number preceded by the letter R however this notation is not accepted by the assembler. In Figure 2. 3 and so forth. Return is accomplished by the macro SUBEXIT. usually the length of the memory reserved in the case of DS and DC statements). 1 2 HELLO 3 4 5 6 MSG 7 PRINT NOGEN SUBENTRY EQUREGS XPRNT MSG. in this case. assemble and execute it by typing the command: assist hello. save area and sets register 13 to be your initial base register. R2. It takes two arguments: the address of the data field to be printed and its length. The resulting code is referred to as the macro expansion. part of the Assist package of macros originally developed by Dr.4 Running Hello World Once you have typed and saved the program. They provide simplified access to common tasks and are useful for novice programmers. John R. We will use several of these in the examples in this text.mlc 23 . If omitted. XPRNT prints data to the default output device (the screen for most users). 4. is 12 (note: all labels have a length attribute. It tells the assembler to display the names of the macros but not show the macro expansion itself. The assembler calculates the base and displacement necessary to address the label MSG. Mashey at the Computer Science Department of The Pennsylvania State University. The program's output is done by the macro XPRNT.

C:\user>rem assemble. This will cause the macro expansions to appear. It shows many things but for now.0_18 18:13:22 hello LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=32 18:13:22 hello EZ390 START USING z390 V1.0_18 Hello World! 18:13:22 hello EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=21 INS=12 Figure 3 Assemble and run Hello World 4. you see it's invocation followed by it's expansion.prn Look in the file hello. In this figure. The file hello. the result is referred to as the macro expansion). The assist command is the name of a Windows batch file in the emulator directory which runs the emulator with the Assist macro support feature enabled and then executes the result if the assembly was successful. The result should be several messages and the line Hello World! as shown in Figure 3 (note: some extraneous material at the end of longer lines has been cut).01b ON J2SE 1. link.01b ON J2SE 1. Further details on the meaning of this code will be covered below. and exec ASSIST prgram hello. examine the area in the center of the display which will look something like Figure 4.5. The number is the line number as determined by the assembler. The code in the macro expansion sections is preceded by plus signs.6.6.5.MLC C:\user>echo off 18:13:22 hello MZ390 START USING z390 V1. contains the translation of the program into binary and other information about the 24 .5 Examining Hello. You will see the same messages in the command prompt window but there are other files.prn This is one of the output files from the assembler.6.in the command prompt window.mlc. It contains error messages and a description of the machine language program created.prn file (usually referred to as the listing). lines 15 through 30 are due to the EQUREGS macro and lines 34 through 38 are the result of the SUBEXIT macro.5. extraneous text to the left has been removed. The left hand portion of the . For each macro. Now modify the program and remove the PRINT NOGEN line and repeat the assist command. Lines 2 through 12 are the expansion of the SUBENTRY macro (when a macro is inserted into our program. What remains is the assembler's listing of your code and the expansion of the macros.prn with the command: more hello.prn (examined below) is the main assembler listing of your program.0_18 18:13:22 hello MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 42 IO=681 18:13:22 hello LZ390 START USING z390 V1. The assembler will create several files in your directory all with the file name hello but with different extensions.01b ON J2SE 1.

12. we suppress macro expansion with the PRINT NOGEN directive as the contents of the expansion are not ordinarily very interesting. 1 HELLO SUBENTRY 2+HELLO CSECT 3+ STM 14.104(15) 5+ DC 18F'0' 6+ DC CL8'HELLO' 7+ DC CL8'09/06/10' 8+ DC CL8'19. On line 1 we tell the assembler not to show macro expansion. It doesn't actually do any calculations and mainly relies on system macros rather than actual instructions. In Figure 5 we see a program to add two numbers. we aren't interested in this code as it is always the same. Normally.executable module.02' 9+ ST 15. The merely tell the assembler that when it sees a symbol such as R5 it really means 5. etc. The left hand side is entirely in hexadecimal.12(13) 4+ BAL 15.12. It has all the basic components of any assembly language program: 1. On line 2 we include the macro which allows us to use R1. The commands in EQUREGS are assembly directives and generate no code. The right hand side is normally in decimal notation with some exceptions.12(.13) 37+ LM 2.8(13) 10+ ST 13. 2.0 35+ L 13.4(.4(15) 11+ LR 13.28(13) 38+ BR 14 40 MSG DC C'Hello World!' 41 END Figure 4 Macro expansion 4.13) 36+ L 14. Normally. R2. 25 .13 14 EQUREGS 15+R0 EQU 0 16+R1 EQU 1 17+R2 EQU 2 18+R3 EQU 3 19+R4 EQU 4 20+R5 EQU 5 21+R6 EQU 6 22+R7 EQU 7 23+R8 EQU 8 24+R9 EQU 9 25+R10 EQU 10 26+R11 EQU 11 27+R12 EQU 12 28+R13 EQU 13 29+R14 EQU 14 30+R15 EQU 15 33 SUBEXIT 34+ LA 15.6 More Basic Assembly Language Examples The hello world program isn't very interesting.15 12+ USING HELLO+8.

9. The XDECO converts the binary into printable decimal characters. On line 8 we print the contents of OUT.it merely marks the end of our assembly language program.OUT XPRNT OUT. The SUBEXIT macro restores the registers that were saved by the SUBENTRY macro. The contents of R2 are in pure binary and cannot be printed directly.L'OUT SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DS CL12 END Figure 5 Example program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADD MSG ONE TWO OUT 26 . a character string of length 12. it does not initialize it. Linkage involves saving the contents of the calling programs registers so they can be restored on exit. A base register needs to be setup and the assembler informed of this if program labels are to be used. On line 4 we load the 4 byte binary value from label ONE into register 2. 8. we use a symbolic label and the assembler calculates the base and displacement address.ONE A R2.L'MSG XDECO R2. The result of the addition remains in register 2. Line 13 reserves but does not initialize. 10. This is not a return statement . Normally. 12. A DS differs from a DC in that a DS only reserves memory. 5. One line 6 we write a title.3. The XPRNT macro needs to know where the beginning of the message is and its length. On line 9 we exit and return to the operating system. Lines 11 and 12 reserve storage for two full word (4 byte) binary values and initialize them to 1 and 2 respectively.TWO XPRNT MSG. We use the symbolic label ONE and the assembler calculates the base and displacement for us and inserts the correct values into the instruction. Again. On line 5 we add the 4 byte binary value at label TWO to the contents of register 2. On line 7 we convert the binary value in R2 to printable characters stored in the 12 byte character string at label OUT. PRINT NOGEN EQUREGS SUBENTRY L R2. 6. On line 3 we establish linkage and a base register. 4. 11. 7. we will use 32 bit binary numbers although there are instructions to use 64 bit binary as well. Line 14 tells the assembler there is no more code. Return is made by the SUBEXIT macro.

They are selected from the set of 16 general purpose registers. Most have two. That is. When an operand is in memory. The resulting number is the address of the operand in memory. however. R1. I. the operand is specified by giving the register number (0 through 15).B2) 27 . if specified. In most cases.5 Basic Instruction Formats 5. The terms base register and index register do not refer to another class of registers. The only oddity concerning registers selected to be base or index registers is that if you specify register zero as either the base or index register.1 Operands In the basic IBM architecture. we will assume that SUBENTRY has been used and that the default base register is thus set to R13. be used for other purposes. L and D are used to indicate the nature of the operand. the displacement and. the memory address is specified as a combination of a base register and a displacement and. the contents of register zero will not be used in the address calculation. Instructions may have from one to three operands. an optional index register. in some instructions. The index register is not often used but when it is. The address of a memory resident operand is calculated by adding the contents of the base register. Often. For most of this text. It may. operands can be in registers or memory. however. When an operand is in a register. the 32 bit binary Add instruction is shown in its explicit definition as: A R1. unless we tell the assembler to the contrary.D2(X2. This is permitted so long as you include the EQUREGS macro (or equivalent) at the beginning of your program. the contents of the index register. Operands can be registers. code letters are used to indicate what operands of instruction are. B. it is used in array-like operations where the base and displacement identify the start of an array and the index register gives an offset into it. M. R2 and so forth. the displacement and base register will be automatically filled in by the assembler as is the case when we specify an operand as a symbolic label attached to a data declaration statement as we saw in Figure 5. X. it means no register. the assembler will set the index register to 0 meaning no register. 5. For example. General purpose register 0 is not used for addressing. immediate data or memory addresses. When specifying operands the letters R. In most cases. you will see the registers designated as R0.2 Operand Notation In the documentation for each instruction.

R I B D X M L means means means means means means means a general purpose register an immediate byte a base register a displacement an index register a mask a length Thus. third). 5. When the operand is a mask.4. M1 tells us that the first operand is a 4 bit mask. if any. RR instructions are specified as: OpCode R1.R2 OpCode M1. 5. 5. When the operand is in memory.3 Operand Semantics When the contents of a register are the operand. RX (registerindexed storage).The letters tell us what the operand or operand component is and the numbers tell us which operand we are looking at (first.1 RR Format In RR format instructions there are normally two operands both of which reside in the general purpose registers (GPR). The opcode is always the first byte. RS (register-storage). each in 4 bits. The first operand is a register (shown as R1) or a mask 28 . The instruction. I is used. The address of the operand in memory is computed by taking the sum of the displacement and the contents of the base register and the index register. second. M is used. When the operand is a byte contained as part of the instruction. base and displacement.2 RX Format In RX format instructions there are normally two operands. is 16 bits long. original instruction formats are RR (register-register). An RR instruction consists of an 8 bit opcode and two register designations. X. L is used in instructions where the operands are of varying length. base and index register. RR format instructions are also called register/register instructions.4. R is used. SI (storage-immediate) and SS (storagestorage): 5. the operand will be composed of a base and displacement or an index.4 Operand Formats The basic. the Add instruction shown above has a first operand that is a register and a second operand that is composed of a displacement.R2 The R1 tells us that the first operand is a register and the R2 tells us that the second operand is a register. therefore. and B. the first operand consists of only an R while the second operand is composed of D. In the above.

RX instructions are specified as: OpCode R1.D2(X2.B2) OpCode M1. The first and third operands are registers and the second operand is base/displacement.4. RS instructions are specified as: OpCode R1. Registers are always specified with 4 bit numbers. RX instructions are always four bytes long. displacement and index register. The byte is a positive integer in the range 0 to 255.4 SI Format SI Format. In actual execution. The result is an absolute memory address.B2) ) is the address of the operand in memory. there is a one byte field that gives the length of the target operand.5. two are registers and one is a base/displacement. In SI format instructions the first operand is a base/displacement value and the second operand is a one byte constant called the immediate operand. it means there is no index register. RS instructions are four bytes long.D2(X2.4. If the index register is specified as register zero (normally the case).R3. In addition. The displacement is a 12 bit field containing a constant between 0 and 4095.D2(B2) 5. the value of the displacement and the contents of the index (unless it is 0). SI instructions are 4 bytes long and are also called storage/immediate instructions. The second operand is a base register.5 SS Format 5.1 One 8 Bit Length Field In SS instructions. the value is interpreted as one greater that what is stored so a 0 is interpreted as meaning 1 and 255 is interpreted as 256 and so forth. There is no index register.D2(B2) 29 . The address of the operand in memory is calculated by adding the contents of the base.I2 OpCode D1(B1) 5. RS instructions are also called register/storage instructions.B1). SI instructions are specified as: OpCode D1(B1).(shown as M1). The second operand (shown as D2(X2. SS-8 instructions are specified as: OpCode D1(L. SS instructions are six bytes in length and also called storage/storage instructions. The R1 is specified in a 4 bit field.3 RS Format In RS format instructions there are three operands.4. both operands are in memory and specified with base/displacement addresses.B2) 5.4.

This the instruction has two lengths. the maximum length is 16. The first length field applies to the first operand and the second to the second. 30 . this is a 6 byte instruction.2 Two 4 Bit Length Fields This is really the same format as above except the length byte is viewed as two four bit fields. As before. As before. Because of the 4 bit length fields.5. 5.4.B1).D2(L2. SS-4 instructions are designated as: OpCode D1(L1. the value is interpreted as one greater than what is actually in the instruction so a 0 means 1 and 15 means 16.where L is the 8 bit length code.B2) where L1 and L2 are 4 bit length codes.

When using base. A mnemonic is a short code to make information easier to memorize. consider the examples in Figure 6. Here you see three examples of RR instructions RR instruction mnemonics always end in the letter R. result in R3 LR R4. the assemblers require you to use numbers only to the example should not have the letter R. possibly (in RX instructions only). if an operand is in a register. a system macro is invoked at the beginning of each program which makes the more easily read R form possible. As with the AR instruction.R5 *Contents of R5 copied to R4 Figure 6 .1 Explicit Addressing This simplest form of addressing is register addressing. In an instruction. an index register. So. you can see that register 2 is the first operand and register 3 is the second operand so the value (contents) of register 3 will be added to the value (contents) in register 2 and the answer (result) will be left in register 2. AR R2. this means you fill in 31 .6 Basic Addressing Operands in memory are addressed either by a single register which contains the absolute address of the operand or by means of a combination of base register. result remains in R2 SR R3. you simply specify the register number. AR. More on this later. for an operand with base and displacement only. the SR instruction subtracts the contents of register 4 from the contents of register 3 and the result is placed in register 3. In the second example we see the subtract register instruction.R4 *Contents of R4 subtracted from R3. In the final example we see the LR or load register instruction. or (2) explicitly where you specify the base. index addressing. The instruction adds the contents of the register specified as the second operand tho the contents of the register specified as the first operand and leaves the result in the first operand. displacement and index or (3) as a mixture of symbolic and explicit. in RX instructions. on the other hand. 6. you must specify it's location by means of a base. an optional index register.RR Examples If. you fill-in each of the fields. The first example involves the add register instruction. displacement. In the most fully explicit way to express a memory operand. In the example. in most cases. you may specify the memory resident operand either (1) symbolically such that the assembler calculates the base and displacement. In the case of instructions the mnemonics are usually one to 4 character abbreviations of the name of the instruction. an operand is in memory. However. Note: technically. displacement and. For example. displacement and.R3 *Contents of R3 added to R2. This instruction copies the contents of the second operand to the first.

In each. the operand is actually part of the instruction itself and not in a register or memory. In the basic instruction set. D2(B2) D2(X2. In all but one case. 0 is often seen in this position and the operand. the displacement is added to contents of the register specified as the base register and the result is the amount of the shift. the format as it appears on the so-called green card looks like those in the examples in Figure 7. If 0 is used in an addressing context it means no register. respectively.Example memory addressing Another way to specify an operand is called immediate addressing. displacement Figure 8 . immediate operands are always one byte in length. immediate operands are the second operand and thus designated as I2 in the instruction format tables. the shift instructions.B2) base and displacement base.the value of the displacement and the register number. the value of the displacement is 1234. in effect. The number following each indicates if this is the first. That is. however. most programs shift by a constant amount. If R5 has 1000 in it and R6 has 100 in it. Note: register 0 can be used for arithmetic and other things but it has this special meaning when used for addressing. 1234(R5) 1234(R6. the second operand is used to calculate the number of bits by which to shift the register(s). third operands are never of the base displacement variety. index and displacement base. There are several ways to code an immediate operand but it is often specified either as a character constant such as C'A' (The letter A) or as a hexadecimal constant such as X'FF' (a byte all of whose bits are ones). Since the index register is seldom used. the base is R5 and the index is either R6 or R0.R5) base and displacement base.R5) 1234(R0. index and displacement Figure 7 Memory operand Index registers are only used in RX instructions. B2 is the place where you put the base register and X2 is the place where you put the index register. Often they are specified as 0. In the example. Note that although the shift instructions are RS instructions by the R3 operand is not used. In general. In practice. They will not be used. no index. In this case. D2 is the place where you put the displacement. 1334 and 2234. In the basic instruction set. the effective addresses (the result of the address arithmetic calculations) are 2234. second or third operand. Thus. In the case of the shift instructions. Figure 8 gives a few examples. No actual address is calculated. displacement only. no register will be used for that position. In some instructions. if you put 0 into a B or X position. in particular. it is common to see code such as 32 . 2 is used as most memory operands are second operands. is base. In Figure 7. The contents for R0 are unimportant.

It is the job of the assembler when you use a label in. R12 is a base register and is pointing (has as its contents) the address of the first byte of your program. assembly programmers seldom use the explicit base and displacement format when writing programs. You use an assembler command called USING to tell the assembler which register(s) can be used as base registers and what their address contents are. for example. Instead. it needs to know where in your program these possible base register candidates are pointing so it can calculate the displacement from that point. no register contribution.) What this all means is that instead of you calculating a lot of base and displacement values. 3. 6.2 Symbolic Addressing In reality.SRA R5. The labels refer to other parts or your program. displacements will be calculated as distances from that point. an instruction. for example. In order to do this. Additionally. they use labels. The question is. In practice this is not difficult in simple programs. how does the number 10 become represented in the base/displacement operand specification? When you specify a number alone as a base/displacement/index operand. the base register will be setup by a system macro named SUBENTRY. These labels usually appear on data elements or instructions.0) which is to say. 2. the assembler needs to know which register or registers it can use for base registers. The assembler keeps track of the size of everything you write and knows how many bytes each label is from the start of your program. (For the examples in this book. For example. the assembler will do it for you. Thus if. load a value from memory at label I into register 7 add to register 7 the value in memory of J store the result back into memory at label K 33 . shift the bits in register 5 right by 10. it is as though you specified: 10(0. When you write a program you need to tell the assembler not only which register or registers it can use as base registers but also where they are pointing. suppose you have a program in which you want to: 1. to calculate the correct base and displacement for you and replace the label in the assembled code with these values. Labels can appear on either instructions or data.10 which means. displacement 10.

it is only 392 bytes from the value in the base register. it is easier to have the assembler calculate the displacements than to do the calculation yourself. it scans and parses its operands. While your label is 400 bytes from the start of the program. However. Thus. Since the load instruction is an RX instruction. It loads the 32 bit value from the address specified by the second operand (I) into the register specified as the first operand. the second operand. the four byte value from memory at I is now in register 7. The z390 emulator uses an entry macro named SUBENTRY which.I The first instruction is the RX load instruction.R13) The displacement is calculated relative to the base register. Assume that your program is using R13 as its base register. Note: R13 does not point at the beginning or your program but 8 bytes into it! So. Hence. Then it calculates how many bytes from the beginning of the the program the label is located. Obviously. be default. the displacement is 392. 34 .I R7. L A ST … I J K DC DC DS F'10' F'20' F Figure 9 . R7. it has an index register position but.Example symbolic addressing R7. is simple. not the start of the program. the other instructions from Figure 9 will be translated to machine language as if they had been written as shown in Figure 10.J R7. I is more complex. given R13 as the base register pointing at byte 8 and the label I is located at location 400 from the actual start of your program. Next the assembler calculates the relative offset of label I from your base register. Assume that label I is 400 bytes from the start of the program. label J is 404 bytes from the start. Figure 9 gives a code fragment that shows the code fragment (other parts of the program have been omitted). established R13 as you base register and causes it to point to byte 8 of your program. we are not using it so R0 is placed there. The assembler first finds label I. let us say that I is at offset 400 from the beginning of the program. as is typical. the assembler will generate the explicit code: L R7. For this example. Similarly. and label K is 408 bytes from the beginning.Assume all values are 32 bit (4 byte) binary values.392(R0. When the assembler sees the load instruction. The first operand.

Length specifications are always one byte. the assembler translates from your symbolic assembly code to the actual binary code. Instructions are either two. programmers wrote in binary.R2 35 .3. SS.3 Machine Language Formats The end result of submitting your program to the assembler is a translation of your program into binary machine language.400(R0.Explicit addressing 6. This is true for all basic instruction types but not true for some recent additions. depending on the instruction. In the basic instruction set.1 RR Machine Language Format The machine language format is shown in Figure 11 and an example explicit format is: AR R1. All immediate operands are one byte.) has a specific machine language binary format. Displacements are always twelve bits. this is not true but it is true for all the basic instruction types. those days are long gone. In the earliest days of computing.392(R0. F).R13) F'10' F'20' F Figure 10 . The entire 8 bits might be the length or the byte may be subdivided into two four bit length fields. 4. etc. RS. four or six bytes long.R13) R7. 6. This is not true with several of the newer instruction types added in recent years but is true for all the basic types.R13) R7. Registers. the machine language code has the following similarities regardless of the instruction type: 1. While these formats are similar to a certain point. 5.L A ST … I J K DC DC DS R7. both base and index. RX. they are not identical.396(R0. Instead. SI. Each instruction begins with an 8 bit opcode (operation code) that identifies the instruction to be executed. 6. In some recently added instruction types. Each instruction type (RR. are always represented as four bit fields (that's because there are sixteen registers numbered 1 through F and you need four bits to represent the largest of these. 3. 2. happily.

The opcode for the AR instruction. the are two bytes in length.D2(X2. in hexadecimal.3.Figure 11 RR Machine Language Format RR format instructions (see Figure 11) are the simplest. Address calculation always results in a positive (unsigned) number. if you have an instruction of the form: A R5. and the displacement. consider the instruction: AR R5.R6 which means to add the signed binary contents for register 6 to the signed binary contents of register 5 and leave the answer in register 5. The address of the memory resident operand is calculated by adding the contents of the base register. So. The displacement is treated as an unsigned twelve bit binary number (that is. you will see this on the left hand side of the printable output of the assembler. Consequently. the opcode is in the first byte and the second byte is divided into two four bit fields for each of the registers. it can never be negative). In this format.LABEL 36 . When you run the assembler. 6. They consist of an opcode and two register specifications.B2) Figure 12 RX Machine Language Format RX instructions have two operands. This is the translation of your symbolic code to actual executable code. The first is normally a register and the second is the address of an operand in memory. the index register (if it is not zero). For example.2 RX Machine Language Format The machine language format is shown in Figure 12 and an example explicit format is: A R1. as discussed above. is 1A so the machine language translation of the above is the two bytes: 1A56 Where each hex digit represents four bits.

The base and displacement designate what is called the second operand even though it appears third in the actual machine language format.3 RS Machine Language Format The machine language format is shown in Figure 13 and an example explicit format is: LM R1.R12) where 24010 is the value calculated by the assembler as the displacement from the presumed contents of R12 to LABEL.3. followed by 4 bits to designate the register being used as the first operand. Since the second operand is specified as a symbol (rather than a specific displacement and register).this means to add the contents of the signed 32 bit operand in memory at label LABEL to the signed binary contents of register 5 and leave the result in register 5. after the assembler determines the base register and displacement. 6. The label LABEL refers to a line in your program where a full word binary valye is stored. Your symbolic instruction from above. followed by 4 bits to designate the base register then 12 bits for the displacement. followed by the base register specification (R12 .R3. followed by the four bits of the index register specification (R0). two of which are designated as registers and the third a memory location in base/displacement format. The machine language format consists of an 8 bit opcode.12 is C in hex) followed by the twelve bit displacement 24010 which is 0F016. The meaning of the two register operands varies depending upon the instruction being executed but the format of the machine language representation is always the same. followed by 4 bits designating the register being used as the third operand. it will be converted by the assembler to the explicit format. might look like: A R5. There is no index register. The opcode for the Add (RX) instruction is 5A and thus the final result is: 5A50C0F0 In this representation (see Figure 12) the 8 bit op code is followed by the four bits specifying the first operand (R5). The assembler will supply the base and displacement that together can calculate the address of LABEL. At this point all the information needed to build the machine language instruction is known.D2(B2) Figure 13 RS Machine Language Format RS instructions have three operands.240(R0. 37 .

If you want to test is a byte in memory has the value A.MEM In this example. A more fully explicit version of the above.R5. For example. 6. Altogether.R5. It compares a byte in memory with the immediate byte and sets some bits indicating if the byte in memory is equal. one of the RS format instructions is Load Multiple.4 SI Machine Language Format The machine language format is shown in Figure 14 and an example explicit format is: CLI D1(B1).C'A' 38 .For example. After MEMB is translated to an appropriate base and displacement pair. the symbolic instruction might be: CLI MEMB. The other operand is the address of a byte in memory. the base C16 and the displacement (0C816). the first operand (1). 20 bytes of memory are accessed (5 words of 4 bytes each). It loads multiple registers from consecutive words in memory. registers R1. R4 and R5 are loaded with the consecutive 32 bit full words in memory beginning at the label MEM. might be: LM R1. For example. less than or greater than the immediate operand. R2.200(R12) The opcode for LM is 9816 so the machine language instruction would look like: 9815C0C8 By now you should be able to see the opcode (9816). after the assembler has conveniently translated MEM into base displacement format.3. the symbolic instruction might look like: CLI 64(R12). An example of such an instruction is: LM R1. Both the memory operand and the immediate operands are always one byte long.I2 Figure 14 SI Machine Language Format The SI instructions all have one of their two operands actually in the instruction.C'A' This instruction compares the byte in memory at the label MEMB with the immediate byte whose value is the letter A. there is an instruction known as CLI . the third operand (5).Compare Logical Immediate. R3.

both operands are in memory and addressed in base and displacement format.D2(L2. Note that in the instruction. This instruction copies up to 256 characters beginning at the address specified by the second operand to the target beginning at the address specified by the first operand.FROM In fact.The opcode for CLI is 9516 and the machine language instruction for the above would look like: 95C1C040 where C116 is the letter A in hex.B1). An example of the first format might be the Move Character (MVC) instruction.R12).5 SS Machine Language Format Example explicit formats are: MVC D1(L. In the other variation. the length byte is taken as an unsigned 8 bit number. C16 (12) is the base register and 04016 is the displacement. The machine language formats are shown in Figure 15. the length byte is interpreted as two unsigned 4 bit numbers. Figure 15 SS Machine Language Format However. In SS instructions. 6. All SS instructions are 6 bytes in length. If the explicit form of the above might look like: MVC 100(8.B2) SS has two formats that differ slightly from one another with regard to the length field. you would express it symbolically as: MVC TO(8). For example.200(R12) The opcode of MVC is D216 so the machine instruction would look like: D207C064C0C8 39 . in one format. if you want to copy the 8 bytes beginning at the label FROM to the eight bytes beginning at the label TO. The length byte is treated as an unsigned 8 bit number (a negative move length would be meaningless). the I2 operand actually appears first and the first operand D1(B1) appears second. the length designation (8) may be unneeded if the label TO has a length attribute of 8 (see below).D2(B2) AP D1(L1. In this case. the assembler would use the length attribute of the target. Both also have a length byte.3.B1).

4 is the first 4 bit length code (one less than 5 as above). the length is 8 not 7? Correct but when represented in machine language. a typical AP instruction might look like: AP VAL1(5). 02016 is the first displacement. It is normal for both base registers to be the same.VAL2(3) This means to add the three byte field from the second operand (VAL2) to the contents of the 5 byte field specified as the first operand (VAL1) and leave the result in the first operand. So.64(3. 40 .R12). first base (C16). This was done because a length of zero had no use and it allowed the maximum length be be one longer (256 as opposed to 255). Translated to explicit format the above might look like: AP 32(5. 2 is the second length. the first displacement (06416). respectively.R12) which would. Some SS instructions divide the length byte into two 4 bit fields in order to get 2 lengths. C16 is the second base and 04016 is the second displacement. more commonly) with the mnemonic AP.You can see the opcode (D2) the length (07). 1 means 2 and so forth. the second base (C16) and the second displacement (0C816). there is an SS instruction known as Add Decimal (or Add Packed. For example. This is mainly used with a class of arithmetic instructions known as decimal or packed. given the opcode of FA16 yield the machine instruction: FA42C020C040 where FA16 is the opcode. But wait. Thus 0 means 1. The length subfields give the length of the first and second operand. C is the first base. the length is always one less.

The basic addressing mode is determined by bit 31 (ESA/390 mode) and 32 (Z architecture only). positive or an overflow (the answer was too large). In ESA/390 mode. 1. is bit 31 is 1. there are also instructions that do not alter the Condition Code.2 Addressing modes In 24 bit addressing compatibility mode. the condition code tells you if the result was zero. 24-bit addressing is in effect. For example. But. 2 and 3 at any given instant. Many instructions set the Condition Code in order to indicate the result of their execution. however. The Program Mask determines which program exceptions will be recognized. negative. the Condition Code will indicate if the operands were greater than. The meaning of the Condition Code value is connected with how it was set. The Condition Code is two bits in the PSW which reflect the result of a prior operation.3 Condition Code The Condition Code is located at bits 18 and 19. the address portion is bits 33 through 63. it was a 64 bit (8 byte) register in the CPU which contained several important values relating to the status of the system at any given instant. the PSW is 64 bits in length and the address is 31 bits in length. In the Z390 emulator. the address portion of the PSW is bits 40 through 63. when both are zero.4 Program Mask The Program Mask is located in bits 20 through 23. knowing which instruction that Condition Code is important to understanding it's meaning. In 31 bit addressing mode. less than or equal to one another. 7. Thus. 24 bit mode otherwise. In the ESA/390 mode. the PSW is 128 bits and the address is contained in the last 64 bits. In the Z architecture. it is a 128 bit (16 byte) register that has the same purpose and many of the same fields. 7. Originally. After signed binary addition. Currently. Some of the important fields in the PSW in the ESA/390 level architecture are addressed in the following sections. 64 bit addressing is operational. 31 bit mode is in effect and when they are both 1. if you execute a compare instruction. in the other hand. The longer format is mainly due to an extension of the addressing from 24 to 64 bits over the years. the address in contained in the low order 31 bits of the second word of the PSW. The are: 41 . in the latest models.7 Program Status Word (PSW) 7.1 Layout The PSW (Program Status Word) has been part of the IBM mainframe architecture since the beginning. In 64 bit addressing mode the address is found in bits 65 through 127. It can have the values 0. When bit 31 is 0 and bit 32 is 1. addressing is in 31 bit mode. In the Z architecture. 7.

Enable floating point significance exception When the bit is 1. prior to its execution. Any of the branch instructions can alter the address portion of the PSW. When 1. When an instruction is fetched.5 Problem / Supervisor State Bit The Problem State bit is located at bit 15.Enable decimal overflow exception Bit 22 . the address portion of the PSW is updated (incremented) to point to the address of the byte immediately following the instruction about to be executed. a branch means changing the address portion of the PSW. In effect. not all instructions may be executed.Enable floating point underflow exception Bit 23 . the address portion of the PSW presumably points to the next instruction to be executed. the system is in supervisor state and all instructions may be executed.6 Instruction Addressing The PSW contains the address of the next instruction to be executed. In problem state. 7.Enable fixed point overflow exception Bit 21 . the next instruction to be executed will be fetched from this location. When you alter this value. the exception is enabled. This is often referred to as the updated address portion of the PSW. Thus. 42 .Bit 20 . When 0. 7. the machine is in (unprivileged) problem state.

index. In the basic architecture there are several branch instructions to handle these situations. Some times we want to skip blocks of code if some condition is true or false or we may want to loop through a block of code a number of times or we want to branch to a subroutine and return when the subroutine has finished.B2) BCR M1. If a mask bit is off and the condition Code has the corresponding value.D2(X2. Normally. the first operand is called a mask. if you want to skip a section of code if.8 Flow of Control & Branch Instructions Every program needs a way to control the order in which instructions will be executed. in the BCR. These include instructions that branch if a condition is true. for example. displacement. 43 . BCR) The conditional branch instructions branch or transfer control based upon the contents of the Condition Code. The mask is 4 bits and these correspond to the 4 possible settings for the Condition Code.R2 In the BC instruction. It resides in the 4 bits where there would normally be a register specification in the RX and RR format. the instruction to make the transfer is a conditional branch. a computer will consecutively fetch and execute instructions one after another from ascending memory locations. execution resumes with the instruction next following the branch instruction. If a mask bit is 1. The two basic conditional branch instructions are the BC (an RX instruction) and BCR (the RR version of the BC). If the Condition Code does not have one of these values. If the Condition Code has one of these values. The mask tells the computer which setting or settings of the Condition Code should cause the instruction to branch. On the other hand. the destination address is calculated form the base. the result of some arithmetic operation were negative. The explicit formats are: BC M1. the destination address is contained in a register specified as the second operand. that means the branch will take place if the Condition Code has the corresponding value. The most common form of the branch instruction is the conditional branch. In both instructions.1 Conditional Branching (BC. The instruction will branch is any tested value succeeds. the branch takes place. However this is not always desirable. instructions that iterate and instructions that are used to call subroutines. For example. In both instructions the destination (where to branch to) is specified by the second operand. no branch takes place. The conditional branch instructions branch or not depending on the Condition Code/ 8.

specifies a 4 bit constant. after a signed Add instruction the Condition Code will have the values shown in Table 5.LAB1 Now the instruction will branch is the Condition Code is either 0 or 1.LAB1 which will work because the BC instruction does not alter the Condition Code.LAB1 Figure 16 BC example What if you wanted to branch if the result in R3 was zero or less than zero (negative)? you could place a second BC instruction after the first such as: BC B'1000'. the third to 2 and the fourth to 3. However. the BC to branch if zero or negative becomes the single instruction: BC B'1100'. the branch to label LAB1 will occur if the result in R3 is zero. the second to 1. 0 1 2 3 Answer Answer Answer Answer was zero was less than zero was greater than zero caused an overflow Table 5 Condition Code after signed Add Let us say you want your program to branch to some label in your program if the result of the Add was zero. B'1000'. B'0000' B'0001' B'0010' B'0011' B'0100' B'0101' B'0110' B'0111' B'1000' B'1001' B'1010' B'1011' B'1100' B'1101' B'1110' B'1111' Never branch Branch if overflow Branch if > zero Branch if > zero or overflow Branch if < zero Branch if < zero or overflow Branch if not zero or overflow Branch if not zero Branch if zero Branch if zero or overflow Branch if zero or > zero Branch if not < zero Branch if zero or < zero Branch if not > zero Branch if not overflow Branch always Table 6 Mask settings after a signed add 44 . All possible other combinations are shown in Table 6.R4 BC B'1000'. you may combine all the conditions for which you want to branch into one mask on one BC instruction.For example. You need mask of 10002 as shown in Figure 16.LAB1 BC B'0100'. this is wasteful. In this case. The first operand. The first position in the mask corresponds to a Condition Code of 0. Instead. Thus. AR R3.

LAB B'1010'.LAB B'1111'. So. if the second operand is specified as R0. Some mask settings (such as 8) have more than one extended representation: BE after a Compare instruction and BZ after an arithmetic instruction.LAB 14. its corresponding binary value determines the branch conditions.LAB B'1001'.LAB B'1101'. The first operand is the four bit mask with the same meanings as in the BC instruction.LAB B'1011'.LAB 8. Table 7 gives examples. The second operand is a register which contains the branch address.LAB 11.LAB 6.LAB B'0110'. BC BC BC BC BC BC BC BC BC BC BC BC BC BC B'0001'.LAB 3.LAB B'0100'. you use a mnemonic which is indicative of the purpose. When a decimal number is given.LAB B'1110'. there are builtin extended mnemonic branch instructions. Note that this corresponds the the mask values in Table 7 as well. These are instructions where the assembler will fill in the mask for you.LAB B'0101'. They are interchangeable. a final decimal mask can be created.LAB 12. By adding the decimal equivalents of the bit positions.LAB B'1100'. The purpose of these is to make your program more readable.LAB Table 7 Decimal mask settings A simple way to construct a decimal mask is to remember that the bit positions in the mask each have a decimal equivalent. However. Condition Code 0 1 2 3 Decimal Mask Value 8 4 2 1 Table 8 Decimal mask equivalents The BCR instruction is similar to the BC.LAB or or or or or or or or or or or or or or BC BC BC BC BC BC BC BC BC BC BC BC BC BC 1. Additionally.LAB B'1000'. the decimal mask would be 9 (8+1). The assembler uses a BC or BCR with a predetermined mask. 45 .LAB 10.LAB 4. no branch takes place since R0 is not used in addressing contexts. The equivalents are shown in Table 8.LAB B'0011'. Instead of using the mask codes.LAB B'0010'.LAB 13.The mask can be specified in any manner.LAB 2.LAB 9. if you want to branch if the Condition Code is either 0 or 3.LAB 5. These are shown in Table 9. The most popular methods are either as a decimal number or as a bit string.LAB 15.

(X2.D2(X2.B2) Branch Branch Branch Branch if if if if ones mixed zeros not ones BC BC BC BC BC BC 1.B2) 7.B2) BCR 15.D2(X2.B2) BNL D2(X2.D2. in which case no branch takes place. in the high order 8 bits.D2(X2.B2) 4.B2) BM D2(X2.Branch and Link The BAL and BALR instructions unconditionally. they always branch.B2) 7.(X2. In both cases.2 Branch and Link Instructions 8.B2) Branch Branch Branch Branch Branch Branch A high A low A equals B A not high A not low not equal After Arithmetic Instructions BO D2(X2.B2) NOPR R2 Basic BC 15. they do not depend on the condition code. they also place.D2(X2.B2) 8.D2(X2.B2) 8.D2(X2.B2) Branch Branch Branch Branch Branch Branch on overflow plus minus zero not plus not zero Table 9 Extended mnemonics 8.R2 Meaning Branch always Branch always No operation No operation After Compare Instructions (A:B) BH D2.B2) BCR 0.B2) BE D2(X2.B2) 8. 3. 2.B2) BZ D2(X2.B2) 13.B2) BC BC BC BC 1.2.B2) BP D2(X2.R2 BC 0.B2) BM D2(X2.D2(X2.D2(X2.Extended B D2(X2.B2) 14.B2) BC BC BC BC BC BC 2. the absolute memory address of the instruction following the BAL or BALR is placed into the register specified as the first operand.B2) BNO D2(X2.B2) 4.1 BAL and BALR .B2) BNH D2(X2.B2) 11.B2) BNP D2(X2.B2) BR R2 NOP D2(X2. The branch is made to the address specified by the second operand: a base. In addition to placing the 24 bit in the rightmost bits of the register specified as the first operand.B2) After Test Under Mask B0 D2(X2.D2(X2.D2(X2.B2) BZ D2(X2.D2(X2.D2(X2. Normally.B2) 2.B2) 13.B2) BNE D2(X2.D2(X2.D2(X2.B2) 4. This is the linking operation. displacement address in the case of the BAL and the address contained in the register designated as the second operand in the case of the BALR except if the register specified is R0.B2) BNE D2(X2. These instructions were on the earliest implementations of the 360 architecture and assume a 24 bit addressing mode.B2) BL D2(X2. the following fields from the PSW: 1. index.D2(X2. The Instruction Length Code (bits 0 and 1) The Condition Code (bits 2 and 3) The Program Mask (Bits 4 through 7) 46 .D2(X2.D2(X2.

2. The BAS and BASR instructions differ from the BAL and BALR instructions mainly in that they do not place additional information in the high order bits of the address stored in the register specified as the first operand. the branch address is computed by adding the twice the value of the immediate field to the current instruction address.An important use for these instructions is to branch to a subroutine and load into a register the address of the return point. In 31 bit addressing mode. to load a register with the absolute memory address of the byte following the instruction.R15 * branch to subroutine Because the BAL/BALR place additional information in the high order 8 bits of the address saved in the first operand and the BAS and BASR do not.3 Branch Relative and Save . the immediate field is treated as the number of half words to jump from the current address. In 24 bit addressing mode. 8. In the BRASL. BXH In the examples above. it is sometimes used. in combination with R0 as the second operand.3. 8.=V(SUB1) * load the address of a subroutine BALR R14. High .BAS and BASR These are similar to the BAL and BALR instructions and are intended to replace them.BRAS. Equal.1 Branch Index Low.2 Branch and Save . In the BRAS instruction there is a 16 bit immediate field which is treated as a signed binary number. 8. They both load the updated address portion of the PSW into the first operand and branch to the address specified by the second operand except. If in 24 bit addressing mode.BXLE. In both instructions.2. They load the updated instruction address portion of the PSW in the register specified as the first operand. the 24 bit address loaded into the first operand is padded to the left with 8 bits all of which are 1. a compare and a conditional branch. the BAS and BASR are now the preferred linkage instructions for 31 bit addressing. BRASL These instructions are similar to the BAS instruction. 8 zeros are appended to the left. the loop mechanism involved an arithmetic operation. That is. a single one bit is appended to the left. in 31 bit addressing mode. Example: L R15. In the case of the BALR. there is a 32 bit immediate field which is also treated as a signed number.3 Looping Branch Instructions 8. in the BASR if the second operand is specified are R0 in which case no branch takes place. Since this is such a common sequence of 47 . the 31 bit address is padded to the left with 1 bit whose contents are 1.

comparison and conditional branch into one instruction thus. the branch does not take place. The valid pairs are R0/R1. in many circumstances. it is the even register of an even odd pair where the even register of the pair contains the increment and the odd register contains the limit value.events. the architecture provides several instructions that perform all three operations. Closely related to the BXLE is the BXH. The first of these is the BXLE instruction. its contents are used as both the limit and increment and the limit values. The BXH operands are the same in scope and function as the BXLE except that the branch takes place when the contents of the register specified as the first operand are greater than the limit value. The third operand. R4/R5. set to 100. On line 5. The advantage of the BXLE instruction is that it combines the increment.R3. is used to determine the increment amount and the limit value. R8/R9. 48 . R2 is set to zero by subtracting it from itself. The XPRNT prints the result to the screen. The instruction is an RS instruction which has the explicit format: BXLE R1. execution continues with the XDECO which converts the binary value in R2 to printable characters in the 12 byte string OUT. If not. the R3 in the above. also set to 1 and R5 is the limit register. respectively. R6/R7. R4 will be the increment register. We add R3 to R2 in line 9. There are several instructions that use even/odd register pairs. Branch on Index Low or Equal. The BXLE branches to LOOP so long as the value in R3 is less than or equal to 100. The declaration on line 12 reserves storage for a character string of length 12 but does not initialize it (DC statements initialize. R14/R15. If the register designated as R3 is even. The BXLE then increments R3 by 1 (R4) and compares the result with 100 (R5). in a large loop. an increment is added to the contents of the register specified as the first operand. If the register designated as R3 is odd. The second operand of the XPRNT is the length of the string OUT. If the result of the comparison indicates that the contents of the first operand are less than or equal to the limit value. R10/R11. R2/R3. But. R12/R13. In this program we add the first 100 numbers into R2 and then print the result. DS statements only reserve the memory). the D2(B2). On lines 5 through 8 we initialize the registers. The value in the first operand is then compared with a limit value and a branch takes place to the address specified by the second operand.D2(B2) The instruction operates as follows: First. resulting in considerably faster execution. R3 will be our counting register which we set to 1. it is justified. The program in Figure 17 gives an example of the BXLE in use. The data declarations on line 15 and 16 create two full word binary values in memory initialized with the values 1 and 100. When R3 becomes 100. The disadvantage is that it ties up several registers in the process.

ONE L R4. execution advances to the next instruction. the second operand is a register whose contents are the branch address except when the second operand is specified as register zero. In both of these. one is subtracted from the contents of the register specified as the first operand.2 Branch on Count . 49 . the program from Figure 17 becomes the program in Figure 18.L'OUT SUBRETURN LTORG DC F'1' DC F'100' DS CL12 END Figure 17 BXLE loop example LOOP ONE HUNDRED OUT 8. Using a BCT instruction.OUT XPRNT OUT. The BCT instruction then decrements R5 and branches to LOOP is R5 is not zero. In the case of the second operand being R0.BCT (RX) and BCTR (RR) A similar set of looping instructions are the BCT and BCTR or Branch on Count instructions. the BCTR becomes a decrement instruction on the register specified as the first operand. the count register.3. On line 7 we add the counting register into the total (R2).R2 L R3.HUNDRED AR R2. In the case of the BCTR. As before. If the result is not zero. in which case no branch ever takes place (R0 being used in an addressing context).R4.LOOP XDECO R2.R3 BXLE R3.ONE L R5. we zero the contents of R2 (line 5) and load 100 into R5. a branch is made to the address specified by the second operand. When the result is zero.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SUM100 PRINT NOGEN EQUREGS SUBENTRY SR R2.

L'DBL SUBRETURN LTORG DC F'100' DS CL12 END Figure 18 BCT loop example LOOP HUNDRED DBL 50 .LOOP XDECO R2.DBL XPRNT DBL.HUNDRED AR R2.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUM100 PRINT NOGEN EQUREGS SUBENTRY SR R2.R2 L R5.R5 BCT R5.

The final byte has a digit in the high order 4 bits and the sign of the number in the low order 4 bits. numbers up to 31 digits in length. F. likewise. respectively. can be represented. often referred to just simply as packed or BCD (binary coded decimal). half a byte. Signed binary integers of either 2. 1111 and 1110 (hex digits C. 3.1 Arithmetic Data The IBM hardware architecture supports three basic arithmetic data types: binary integer. 1. Each digit is stored in 4 bits. 4. The codes 1100. Printable numbers are in what is called zoned format. Any code is equally valid but C and D are the defaults for positive and negative. Each byte contains two decimal digits except for the final byte which has one 4 bit digit and a 4 bit sign. Normally. In this format. plus a sign. 2.9 Data Types 9. they do not have the range of magnitude often required for scientific calculations. Floating point numbers of either 4. hexadecimal or decimal radixes. Table 10 gives an overview. Further. packed decimal can be converted to printable numeric text very quickly as well. 1010. floating point and packed decimal. The the decimal numbers 0 through 9 are represented by their binary equivalents 000 through 1001 (hex codes 0 through 9). a close cousin of packed decimal format.1. decimal numbers are represented in a string of from 1 to 16 bytes. often referred to simple as zoned. Thus. A. the high order 4 bits of each byte are always ones (hex F) and the low order 4 bits are the digit 51 . or 8 byte length Unsigned binary integers of either 4 or 8 bytes length Varying length signed packed decimals up to 16 bytes long. Table 11 gives several examples of packed decimal numbers. 4. In zoned format. Table 10 Numeric data types 9. Their main disadvantage is that arithmetic operations are relatively slow and thus they are not suitable for procedures which require multiple arithmetic steps. They are merely encodings of a decimal number with a sign appended to the end. One advantage of packed decimal is that numbers in this format they can be used to perform accurate decimal arithmetic on values with many digits. we only see the hex codes so it is easy to remember that the positive codes are CAFE and the negative are DB (as in debit).1 Packed Decimal and Zoned Decimal Format Data The IBM mainframe has a data type called packed decimal. 8 or 16 bytes length with either binary. Another advantage is that character versions of numbers (such a user might type on a terminal) can be converted to packed decimal very quickly and. and E) in the sign position indicate the number is positive while the codes 1101 and 1011 (hex digits D and B) indicate a negative number.

the number is positive and if it is one. the first one usually. the input machinery codes each digit in zoned format. The ED (edit) and UNPK (unpack) instructions convert from packed decimal to zoned decimal and the PACK instruction converts from zoned decimal to packed decimal. Where there are 0s (not shown). the high order 4 bits of a byte are called the zone and the low order 4 bits are called the digit. This. If it is zero. Thus. the positive number 107 is: 0110 1101 and. Decimal +12345 -12345 +1 +12 Packed Decimal (in Hex) 12 34 5C 12 34 5D 1C 01 2C 3 3 1 2 bytes bytes byte bytes Table 11 Example packed decimal numbers When text numbers are read from a terminal or other user input device. the corresponding value of the power of two is added to the total. in an 8 bit computer. The question becomes. how can you represent negative numbers? There are several possibilities. where there are 1s. the number is negative. However. 9. In this table. The positions are powers of two beginning with zero. if you type 1234 into an EBCDIC terminal. in sign and magnitude notation -107 would be: 52 . An actual binary number is the sum of the values for its bit positions. The CVD instruction converts a binary quantity in a register to packed decimal. The CVD is unusual in that the target is addressed by the second operand. one of the bits. Additional details are described in Chapter 21.portion. For example.2 Binary Integers and 2s Complement Positive binary integers are represented as a string of bits of zeros and ones. not all numbers are positive. the binary number (expressed to 32 bits): 0001 0000 1001 0000 1000 0000 1011 1001 is interpreted as shown in Table 13. The value of a binary number is the sum of the values of the bit positions times the value at the position (0 or 1). nothing is added to the final total from that position. Table 12 gives the powers of two from 0 to 31 (32 altogether) and the corresponding bit pattern in a 32 bit field. Likewise. the instruction CVB converts a packed decimal to binary. however).1. The last row is the largest value you can store in an unsigned binary integer: 2311. The first is what is referred to as sign and magnitude. is a sign bit. internally this will be coded as the four bytes: F1 F2 F3 F4. Here. For this reason. the larges number you can store in an 8 bit field is 28-1 or 255 (0 through 255 are 256 values.

The first of these is there are two ways of expressing zero: 0000 0000 1000 0000 1 x 228 268 435 456 1 x 223 8 388 608 1 x 220 1 048 576 1 x 215 32 768 1 x 27 128 1 x 25 32 1 x 24 16 1 x 23 8 1 x 20 1 ------------------277 905 593 Table 13 Decimal value of a binary number 53 .1110 1101 1 2 4 8 16 32 64 128 256 512 024 048 096 192 384 768 536 072 144 288 576 152 304 608 216 432 864 728 456 912 824 648 295 20 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232-1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1 2 4 8 16 33 67 134 268 536 1 073 2 147 4 294 1 2 4 8 16 32 65 131 262 524 048 097 194 388 777 554 108 217 435 870 741 483 967 Table 12 Powers of two Sign and magnitude notation. has several problems. however.

The first is a positive zero and the second is a negative zero. you need more specialized hardware to take into account all the possible outcomes. Thus 107 becomes negative the following way: 0110 1101 1001 0010 1001 0011 107 1s complement 2s complement How does this solve the two zeros problem: 0000 0000 1111 1111 0000 0000 54 zero 1s complement 2s complement (overflow ignored) . This sort of thing confuses the hardware. Another solution is called 1s complement. Another problem is that you can't do arithmetic directly on number in sign and magnitude notation. 107 and -107 appear as: 0110 1101 1001 0010 107 -107 As it turns out. all negative numbers have a leading one bit so that position is still called the sign but the remainder of the number is quite different. The answer is not zero. 1s complement has two zeros too: 0000 0000 1111 1111 positive zero negative zero So. are zero. Both. Yes. This adds complexity and reduces speed. we still have the problem of comparing two values but there is a solution: 2s complement. If I add the value of 107 and -107 I should get zero but I don't: 0110 1101 + 1110 1101 ----------1 0101 1010 The extra bit on the left is an overflow. however. To solve it. This is a problem. 2s complement is formed by adding one to the 1s complement. both negative or mixed. This. If you compare two values you need to take into account that they could both be positive. 1111 1111 is zero. Does this work? It solves the arithmetic problem: 0110 1101 + 1001 0010 ----------1111 1111 And the answer is zero. In 1s complement we form the negative of a number by flipping (complementing) the bits.

it is currently fashionable among disk drive manufacturers to call 1.000 Hz. the largest binary number in 4 bits is 1111 which corresponds to 15 decimal. Thus.294. however. in the case of a 32 bit number. 9. Memory manufacturers. however.000. the instruction formats all allow 4 bits whenever a register is designated. the maximum number of binary codes in an 8 bit byte is 256. 2. a total of 256 values. The minimum number.1.147. are stuck with the higher binary values due to manufacturing issues. 4 bits are needed to specify any of registers in an IBM mainframe. 9.note the small print on the package.294. Can we do arithmetic? Yes: 0110 1101 + 1001 0011 ------------0000 0000 107 -107 There are special rules for handling overflows which won't be covered here. Thus. the range is not 0 to 4. In fact. Unsigned 32 bit numbers.4 Threshold Binary Values In many cases. This. you need 4 bits to be able to specify any register. Terms such as kilobytes. Note: there is one more negative number that positive numbers (that extra zero had to go some place).073. 1 gigabyte of memory actually has 230 or 1.000. However. 55 . megabytes and gigabytes derive from these thresholds.483. the range 0 to 15 has 16 values." Clock rates are normally expressed in base 10 so 1 gHz is 1. Thus. they are shorting you more than 71 million bytes per "gigabyte. A consequence of this is that one bit is lost to sign representation so.295 as shown above but. rather. This lets them claim what appears to be a higher capacity for their offerings. you get the original zero again. it is important to know the maximum number that can be stored in an unsigned binary number with a particular number of bits. however. At 8 bits you can have numbers between 0 and 255. do range from 0 to 4.000.967.1.648 to + 2.741.3 Nomenclature Table 14 gives the decimal values of several powers of two and along with the terms with which we refer to them. expressed in decimal. is 0000 or zero. Hence. That is. of course.147.000. however. For example.483. if you try to create a negative zero.000 bytes a gigabyte .295.967.In other words. is how signed binary integers are represented in a modern computer.824 bytes.647.

Many legacy assembly language programs have coding conventions that take this number into account. if your unsigned binary number has 12 bits. you can have 4096 values between 0 and 4095.1 024 2 048 4 096 8 192 16 384 32 768 65 536 131 072 262 144 524 288 1 048 576 2 097 152 4 194 304 8 388 608 16 777 216 33 554 432 67 108 864 134 217 728 268 435 456 536 870 912 1 073 741 824 2 147 483 648 4 294 967 296 210 2 11 1 K 2 K 4 K 8 K 16 K 32 K 64 K 128 K 256 K 512 K 1024 K or 1 M (meg) 2 M 4 M 8 M 16 M 32 M 64 M 128 M 256 M 512 M 1024 M or 1 G (gig) 2 G 4 G 212 2 2 13 14 215 2 2 16 17 218 2 2 19 20 221 2 2 22 23 224 225 2 26 227 228 2 29 230 231 232 Table 14 Binary nomenclature Similarly.535. one byte (the high order or leftmost) was not used for addressing. 56 . At 24 bits your numeric range is 0 to 16.777. Thus.215. 32 bit and 64 bit addressing modes. the size of a displacement. If they were executed in 32 bit mode. the maximum displacement from a base register is 4095. It takes 3 bytes to hold a 24 bit number. Many programs and operating system conventions used that byte to communicate information. Consequently.215 (~16 meg) number is significant as it was the upper limit of memory size on the basic 360 Series. since addresses were almost always stored in 4 byte full words. Modern mainframes can execute programs in 24 bit. In 16 bits you can count from 0 to 65. the high order byte would be considered part of the address and lead to erroneous results.777. 16. many older legacy programs still run in 24 bit addressing mode to this day. So.

there is an implied length. Java. In IBM Assembler. Alignment refers to where the memory associated with the label can be put.1 Declare Constant and Declare Storage (DC and DS) In a high level language such as C. C++. For example. In your program. the DS/DC code tells the assembler the type of data you are reserving. For example. type F.10 Data Declarations 10. The assembler will remember the attributes with which you labeled the memory for future use. length and so forth of the memory being reserved. In assembly language. followed by one or more spaces followed by a series of codes that indicate the data type. There are several codes that may be used but the most common are given in Table 15. After the label. you normally place a label on an area of memory. a long is 32 bits or 4 bytes in C/C++ while a char is 1 byte. Depending upon the data type and dimensionality. an amount of memory is allocated for each variable. and so forth. This label is then used to refer to the memory in program instructions in a manner analogous to variables in a high level program. 57 . its dimensionality (if any). 8 (doubleword alignment) or 2 (half word alignment). a length and the alignment of the memory that will hold the value. Assembly language has a similar but different approach. This is for performance reasons as some operations execute quicker if the data is on aligned boundaries. A DC (declare constant) statement reserves and initializes memory in your program whereas a DS (declare storage) statement only reserves memory without initialization. Some data types require that the address of the memory holding the value be evenly divisible by 4 (word alignment). is normally 32 bits or 4 bytes because this is the size of a general purpose register in which data of this type is normally manipulated (note: on newer 64 bit architectures 64 bit or 8 byte values are possible). you include one or more spaces followed by either DC or DS. FORTRAN. The first is a DC statement and the second is a DS statement. When reserving memory. In other data specifications. In these. In Table 15. the assembler will allocate an amount of memory at that location in your program. These will be discussed separately. storage class and so forth. a fixed point binary integer. dimensionality. there are two main methods of reserving memory. you manipulate named variables. you access and manipulate this memory by referring to the names of the variables. Note: in some cases the label can be omitted if there are other ways to address the data area. several data specification types have no implied length. data type. Based on your combination of codes. however. These are defined with declaration statements that give the name of the variable. the minimum length is 1 byte and the maximum is effectively unlimited. In both forms you ordinarily (but not always) place a unique label complying with assembler naming rules (see page 18) beginning in column 1. Each code implies a data type.

2. If you use DC. the contents of each is undefined. DAT1 DAT2 DAT3 LAB1 LAB2 LAB3 LAB4 LAB5 DS DS DS DC DC DC DC DC DC F H D F'123' C'HELLO WORLD' B'1011101010001001' X'2F3C' P'1234' F'789' *fullword uninitialized *halfword uninitialized *doubleword uninitialized *binary full word *character string *bit string *hexadecimal string *packed decimal string *binary full word Figure 19 Example DS/DC statements 58 . 2.Type C X B F H D P Z A V Implied Length 4 2 8 4 4 Alignment byte byte byte word halfword doubleword byte byte word word Format characters hexadecimal digits binary digits fixed point binary fixed point binary long floating point packed decimal zoned decimal address value external address value Table 15 DS/DC Data Types In your program. Initialization is normally a single-quoted string beginning immediately after the data type and any qualifications to the data type. the assembler will automatically skip one or more bytes in order that your value will be correctly aligned. If you use the DS statement. None of the data items at these labels are initialized and. if the next available byte is not aligned properly for the data type your are creating. Fore example. The first three labeled DS statements reserve 4. 2 and 8 bytes respectively. you give an initial value that will be loaded into the memory location when the program begins. The value in the string must be appropriate for the data type. The unlabeled memory following LAB5 can be addressed as LAB5+3 (the length of the data at LAB5 is 3 bytes). and 3 bytes respectively and initialize each as shown. The memory reserved by labels LAB1 through LAB5 reserve 4. In some cases. if the next address available is divisible by 2 but not 4 and you are allocating a full word fixed point value (type F). Figure 19 gives some examples. Normally you won't notice this but if you look carefully. consequently. especially where you need to know the exact amount of memory used by variables in contiguous memory. 11. these extra padding bytes may be important. you will see the location counter increment by 6 and not 4 for your variable. you do not provide initialization. the assembler will skip two bytes before allocating your data item.

A literal looks like a DC operand but is always preceded by an "=" sign. As long as the first byte of the data area in within range of a base and displacement.=C'Hello World' MVC RESULT. You may use literal notation in an instruction in place of a label. Note: there is another form of notation for what are called immediate operands. Your label (lets say LOC) will be the address of the first fullword and the remaining 17 will be at successive 4 byte offsets from this location (LOC+4. If you use the same literal more than once. constants are not separately declared in DC statements but contextually with what are called literals. and so forth). one which will extend beyond the range of any base and displacement combination. it can be used without problem (you load the address of the area into a register and address it directly with this register).no = sign Figure 20 Literals One reason for the LTORG directive has to do with base register addressing.C'X' *loads R1 with 123 *moves the string to MESSAGE *moves an edit pattern to RESULT *immediate . This is referred to as the literal pool. however. you may also specify a count. If.2 Literals Often for the sake of clarity or convenience. LOC+8. they would be beyond the large data area and out of range of any base and displacement. In the first example from Figure 20. you permitted the literals to be placed at the end of the program. These are not preceded by the equals signs and the two should not be confused. See the example in Figure 54 in Section Error: Reference source not found on page 132. Table 20 gives several examples. So. 10.=X'40202120' CLI LAB. Thus. if you say 18F you are asking for 18 fullwords. LOC+12. The effect of this is to load register 1 with a full word binary with the equivalent of the decimal number 123.In addition to the label and the data type. it will only be declared once. the literal is in the position of the memory operand of the load (L) instruction. L R1.=F'123' MVC MESSAGE. The declarations for these constants will. This is the number of items of the type you want to allocate. Sometimes a program will need to use a very large data area. be placed at the end of your program or at point immediately after the LTORG directive. 59 . the LTORG can be used to dump the literal pool prior to the start of a large data area. by default. The assembler keeps track of all the literal values and types your program has used. This is a shorthand notation which causes the assembler to make the declaration for you at another place in your program.

60 .

11 Linkage
Linkage refers to the set of conventions used by the operating system whereby programs call one another, pass arguments, and return values. The IBM mainframe still uses the original linkage conventions established when the machine was introduced in 1964 although there have been some additional modes added since then. For purposes of this text, we will deal with the legacy linkage as embodied in the SUBENTRY and SUBEXIT macros. Basically, linkage saves the contents of the calling program's registers in the calling program's save area, creates a local save area to be used by any programs our program calls, and sets up a base register. 11.1 Linkage Registers On entry into a subroutine, several registers have predefined contents as shown in Table 16.
R1 R13 R14 R15 Address Address Address Address of of of of a parameter list save area in calling program return point in calling program entry point in called program

Table 16 Linkage registers

The two main linkage registers are R14 and R15. R14 indicates where the called program is to branch to in the calling program in order to make a return. That is, when the subroutine is finished, it should branch to the address contained in R14. The calling program provides this. Secondly, R15 always contains the address of the entry point in the called program. Normally this is the address of the first instruction in the called program however some subroutines can have multiple entry points. In any event, R15 is the address of the first instruction to be executed. 11.2 Save Area Every program has a save area. A save area, as shown in Table 17, is an 18 full word (72 byte) area in which we place information that will be restored when the program completes as well as information helpful to debugging. When a subroutine starts, it immediately saves the contents of the general purposes registers (except R13) into the calling program's save area then it creates a save area of its own. The address of the calling program's save area will be in R13 upon entry. The code to save the calling program's registers and set up our local save area is in the SUBENTRY macro as shown in Figure 21 as copied from the assembler output file. The line numbers are from the assembler and the plus sign after each indicates that the code is from a macro expansion (non-macro code does not have a plus sign on the line number).
61

Offset Word 0 4 8 12 16 20 24 28 32 36 40 44 50 54 58 62 66 70 Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Contents Address of calling program save area Address of called program save area Register 14 Register 15 Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Table 17 Save area

On line 3 we tell the assembler that this is the start of a control section and that it's name is ADD (from the label on the SUBENTRY). A CSECT is an assembler directive and does not generate code. On line 4 the STM (Store Multiple) causes registers R14, R15, R0, R1, … R11, R12 to be saved in successive 4 byte full words beginning at the fourth full word in the calling program's save area. Word 4 begins at offset 12 (see Table 17) from the start of the calling program's save area whose address is in R13 and thus the displacement of 12 past R13.
3+ADD 4+ 5+ 6+ 7+ 8+ 9+ 10+ 11+ 12+ 13+ CSECT STM BAL DC DC DC DC ST ST LR USING 14,12,12(13) 15,104(15) 18F'0' CL8'ADD' CL8'09/14/10' CL8'20.33' 15,8(13) 13,4(15) 13,15 ADD+8,13

Figure 21 SUBENTRY code

The next instruction, the BAL (Branch and Link), does two things: it causes a branch to the ST (Store) instruction on line 10 and it resets the contents of R15 to point to the first byte of the 18 full word save area immediately following it. The branch address is calculated by adding the contents of R15 and 104, the displacement. At the time it does this, R15 has the address of the STM in it (the first instruction of the program). The ST instruction at line 10 is 104 bytes from the beginning of the STM.

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But after the BAL calculates the branch address but before the actual branch, the BAL loads into the first operand, R15, the update address portion of the PSW, that is, the address of the byte immediately following the BAL. When an instruction executes, the address portion of the PSW always has the address of the byte immediately following the instruction. Normally, this is the address of the next instruction. In this case, however, it is the address of our (called) program's save area. At line 10, the ST instruction stores the address of our save area into the third word of the calling programs save area then stores the address of the calling program's save area in the second word of our save area. Thus, the calling program's save area points to ours and ours points to the calling program's save area. The contents of R15 (address of our save area) are copied to R13 and the assembler is told to use R13 as a base register and to assume that it is pointing at the 9th byte of the program (the 1st byte of the save area) which it is. You will note that after the 18 word save area are character fields containing the name of the CSECT and the date and time when it was assembled. Happily all this is done by the SUBENTRY macro. Like wise, the SUBEXIT macro reloads the calling program's registers and returns to the address contained in R14.

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64 .

Output will have the .20 BC B'1111'. and built the destin'd town. and the man I sing. Long labors. both by sea and land.5. and the man I And haughty Juno's u Expell'd and exil'd. left the Trojan shore. For purposes of this discussion.5.01b ON J2SE 1. And haughty Juno's unrelenting hate.1 Input / Output using XREAD and XPRNT By default. the XREAD pseudo instruction will read from a file with the same name as the file your are assembling but with the . the simplified Assist pseudo instructions XREAD and XPRNT will be used. Long labors.LOOP SUBEXIT DS CL20 END DONE IN README.5. 12. And in the doubtful war.DONE XPRNT IN. both by And in the doubtful The Latian realm. forc'd by fate.6. he bore. Expell'd and exil'd. Screen Output: C:\Documents and Settings\user>assist readme C:\Documents and Settings\user>echo off 12:11:36 readme MZ390 START USING z390 V1.0_18 Arms.XRD extension.01b ON J2SE 1.XPR extension and also appear in the console window.0_18 12:11:36 readme MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 42 IO=578 12:11:36 readme LZ390 START USING z390 V1.01b ON J2SE 1.0_18 12:11:36 readme LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=32 12:11:36 readme EZ390 START USING z390 V1.6. And settled sure succession in his line.12 Assist Macro Input/Output The overall issue of input/output on the s390 architecture also involves the underlying operating system and many other factors. And the long glories of majestic Rome.XRD Arms. From whence the race of Alban fathers come.20 BC B'0100'. before he won The Latian realm.6. 1 2 3 4 5 6 7 8 9 README LOOP PRINT NOGEN SUBENTRY XREAD IN. who. an His banish'd gods re And settled sure suc From whence the race And the long glories 12:11:36 readme EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=30 INS=53 Figure 22 XREAD example 65 . His banish'd gods restor'd to rites divine.

The XDECI has the format: LABEL XDECI R1. This is an aid for debugging and discussed in greater detail in section 13. those that exceed the length stated in the XREAD) will be truncated. The length is specified as either a constant or as a register enclosed in parentheses. XDECO has the format: LABEL XDECO R1.3 below. the program aborts with an abend code of S013. the contents of the register at runtime will be the length. If specified as a register.D2(X2. The number will be right justified with a leading minus sign if negative and padded to the left with blanks. In the event of an error. the floating point registers and the program memory segment to the standard output.The general format of the XREAD is: XREAD INFIELD. On input.XPR 12. carriagereturn/line-feeds will be removed and short records will be padded with blanks (4016 in EBCDIC).B2) In this case. Note that the input line are truncated when printed. Input lines are in ASCII but will be converted to EBCDIC. The first operand is normal not machine register R1 as this register may be altered by the instruction. the first operand designates the register to receive the number converted to signed binary and the second operand designates the address of a filed in memory containing the decimal character representation of the number. 12. The LABEL is optional. the Condition Code is set to 1. At end-of-file. Figure 13 gives an example. 66 . Long input records (that is.3 XDECO/XDECI These pseudo instructions are used to convert from internal binary numbers to character decimal representations and the reverse. The address is specified in the same manner as a second operand in an RX instruction.B2) Where first operand designates the register containing the signed 32 bit binary number to be converted to printable decimal and the second operand gives the address of a 12 character field which will receive the converted number.LENGTH Where INFIELD is the area into which data will be read.2 XDUMP The XDUMP pseudo instruction will dump the contents of the general purpose registers. is also placed in the file README.D2(X2. besides appearing on the screen. Also note that the output.

the Condition Code is set to 3 and the first operand is unchanged. a blank). The instruction scans the number until a non-decimal character is encountered (for example. not the first operand. R1 is set to the first character which is not a digit. Note: R1 in this case means the actual register 1. R1 is set to the address of that character and the Condition Code is set to 3. The converted number is placed in the first operand and the Condition Code is set to 0 if the converted number was zero. If the first character is not numeric or a plus or minus sign. however. 1 if the number was less than zero and 2 if the number was greater than zero.4 XHEXO/XHEXI These operations are similar to XDECO/XDECI except hexadecimal numbers are converted and there is no usage of either the plus or minus signs.XDECI scans the field. 12. the instruction halts. If there are more than 9 digits. 67 .

68 .

one or both of the operands must be a register. In this case we will select R2. not read in at run time) table of numbers between 1 and 5 decimal. Internally. Initially we create the table of numbers as shown in Figure 23. Each of the storage declarations creates a full word (4 bytes) whose contents are the binary equivalent of the decimal numbers in the quoted fields. First. A register is required because the integer arithmetic instructions are all of the RR or RX variety and. We select a register in the range R2 through R12. Among these are binary integer.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 23 ADD. R2 is a good choice but be careful. Since we are working with binary integers (the most common form of integer arithmetic programming).. floating point. the message (to Adding Numbers) and added five additional lines of storage declarations. we normally prefer to see numbers printed as decimal characters. it can sometimes be altered by system calls and some instructions. we will start with an initialized (i.mlc. add them and print the result. it can't compare with the thrill of actually doing arithmetic or some other ostensibly useful computational activity.1 Program to Add Numbers As impressive as Hello World! was. and packed decimal. Next we need to calculate the result.mlc to change the name (to ADD). consequently.mlc as a starting point.e. 69 . however.13 Integer Arithmetic 13. Externally. Any activity involving numbers must convert between these formats when doing input or output operations. Initially. The total storage allocated is 20 bytes. R1 and R13 through R15 have significance with regard to linkage. This is because registers R0. 1 2 3 4 5 6 7 8 9 10 11 12 ADD PRINT NOGEN SUBENTRY EQUREGS XPRNT MSG.MLC Step 1 MSG ONE TWO THREE FOUR FIVE In Figure 23 you can see we modified hello. however. computers represent numbers in several different formats. we will need a register in which to do the calculations. Our program will be called add. we must examine the question of the internal representation of a number versus its external representation. The program will borrow from hello.

we will add each of the values into it until it has the final total and then we will print the total. Obviously we first need to put zero into the register.R2 will be out accumulator.MLC Step 2 MSG ZERO ONE TWO THREE FOUR FIVE Alternatively. One way is to load a full word constant zero into the register. 70 . That is. The SR instruction subtracts the contents of the register specified as the second operand from the contents of the register specified as the first operand and leaves the result in the first operand. This would use a 4 byte Load instruction and require a 4 byte constant in memory as shown in Figure 24.=F'0' *Zero R2 XPRNT MSG. we could use a literal as shown in Figure 25 but this is really the same thing as the assembler merely makes the storage declaration for us (it will appear in the . The L instruction loads the full word (4 bytes.ZERO *Zero R2 XPRNT MSG. we use five Add (A) instructions as shown in Figure 27. It is an RX instruction and the memory address is calculated using the Base. Displacement and Index method. This is the quickest and uses the least memory (2 bytes). Next we need to add each of the values into R2.MLC Step 3 MSG ONE TWO THREE FOUR FIVE The preferred alternative is to simply subtract the register from itself as shown in Figure 26.L'MSG SUBEXIT DC C'Adding Numbers' DC F'0' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 24 ADD.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 25 ADD. fullword aligned) from the memory address specified by the second operand into the register specified as the first operand. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADD PRINT NOGEN SUBENTRY EQUREGS L R2. 1 2 3 4 5 6 7 8 9 10 11 12 13 ADD PRINT NOGEN SUBENTRY EQUREGS L R2.prn file). To do this. This can be done in two ways.

Another way of allocating it would be an operand of 12C which means 12 character strings of length one (implied default length of a character). this later notation 71 .1 2 3 4 5 6 7 8 9 10 11 12 13 ADD MSG ONE TWO THREE FOUR FIVE PRINT NOGEN SUBENTRY EQUREGS SR R2.THREE A R2.MLC Step 4 The A instruction is an RX instruction that adds the full word aligned binary value from memory at the address specified as the second operand to the value in the register specified as the first operand and leaves the result in the first operand.FIVE XPRNT MSG. Note the operand on the DS statement labeled DBL. To print it we need to convert it from binary to decimal characters.R2 *Zero R2 XPRNT MSG. The Assist package has a convenient instruction that does this for us named XDECO as shown in Figure 28.MLC Step 5 MSG ONE TWO THREE FOUR FIVE At the end of the Add instructions the answer is in R2 in binary format.R2 *Zero R2 A R2. We need to print it. XDECO takes the place of several actual instructions (CVD and EDIT) which will be discussed below. However.TWO A R2. In the z390 emulator the address of the 12 byte field need not be aligned.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 26 ADD. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2. XDECO is a pseudo RX instruction in the Assist package that converts the signed binary integer in the register specified as the first operand to a 12 byte signed right justified decimal character (zoned decimal) representation padded to the left with blanks and placed in the 12 bytes of memory beginning at the address specified as the second operand. This format means character length 12 or. one character string with a length attribute of 12.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 27 ADD.FOUR A R2.ONE A R2.

C:\Documents and Settings\user>echo off 13:13:21 add MZ390 START USING z390 V1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2. Column labels have been added at the top which do appear in the actual PRN file.0_18 13:13:21 add MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 43 IO=733 13:13:22 add LZ390 START USING z390 V1.THREE A R2.prn now contains some interesting information as shown in Figure 30 (some parts now shown). the starting byte of each line of code in the machine language image being created.01b ON J2SE 1.2 Analyzing the PRN File The file add.MLC Step 5 13. Column 3 is the effective address.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Figure 28 ADD. 2.0_18 13:13:22 add LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=35 13:13:22 add EZ390 START USING z390 V1. Column 1 is what is known as the location counter.R2 *Zero R2 A R2.6. relative to zero.5. not the length.01b ON J2SE 1.L'MSG XDECO R2. 72 . It is in hexadecimal and gives.6.01b ON J2SE 1.FOUR A R2. There are several things to take note of.DBL XPRNT DBL.6.TWO A R2.would not work with the L'DBL figure in the XDECO. 12 would be the repetition count. not 12. relative to zero. 1. The value of L'DBL would be 1.5.0_18 Adding Numbers 15 13:13:22 add EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=22 INS=20 Figure 29 ADD.FIVE XPRNT MSG. of the first operand if the first operand is a memory address. 3.5.ONE A R2.MLC Step 5 MSG ONE TWO THREE FOUR FIVE DBL Running the code from Figure 28 results in the output shown in Figure 29 (long lines truncated). Column 2 is also in hexadecimal and is the translation of the assembly language statement up to the first 8 bytes.

Since a hex digit corresponds to four bits. 6. The first byte (5A) is the opcode as shown in Figure 30.PRN Column 2 for a line containing an instruction is the translation of that instruction to machine language.DBL XPRNT DBL.L'MSG XDECO R2. the format consists of one byte (2 hex digits) containing the opcode and one byte containing the operands (see section 6. Column 5 indicates the macro level. As an RR instruction. Col 1 000000 000000 000072 000072 000074 000078 00007C 000080 000084 000088 00008E 000092 000098 0000AA 0000B8 0000BC 0000C0 0000C4 0000C8 0000CC 0000D8 Column 4 is the effective address.3. leaving the result in R2.3.ONE A R2. relative to zero. of the second operand if the second operand is a memory address. With regard to the second byte. The Add instruction is an RX instruction and.TWO A R2. Hence. the location counter advanced by 2 from 72 to 74. Note that the location counter jumped from zero at the beginning of the program to 72 following the SUBENTRY. As all RR instructions are two bytes in length. the first hex digit (2) is the first operand and the second hex digit (2) is the second operand. as is the case with nearly all RX instructions except the BC. The next instruction is A R2. Look at the line with the location counter value of 72 (leading zeros omitted). the code 1B2216 is the result of SR R2. The opcode is 1B as determined from Table 20 on page 135. the first operand is designated by the first four bits and the second operand by the second four bits.R2 *Zero R2 A R2.4.FIVE XPRNT MSG. Column 6 contains your original card images. has the format shown in section 6. Col 3 Col 4 Col 5 (1/1)1 (1/2)2 (1/3)15 (1/4)33 (1/5)34 (1/6)35 (1/7)36 (1/8)37 (1/9)38 (1/10)39 (1/11)40 (1/12)41 (1/13)42 (1/14)49 (1/15)50 (1/16)51 (1/17)52 (1/18)53 (1/19)54 (1/20)55 (1/21)56 Col 6 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2.ONE which says to fetch the 4 bytes beginning at the label ONE and add them to the 4 bytes in register R2.THREE A R2. The next byte contains the first operand 73 . This is because the SUBENTRY macro used 72 bytes. 5.FOUR A R2. and actual line number taking into account macro statements. The code 1B22 is represents the SR instruction. Thus we get the hexadecimal machine language 5A20D0B0 16. original line number.2 above.R2.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Col 2 1B22 5A20D0B0 5A20D0B4 5A20D0B8 5A20D0BC 5A20D0C0 E020D0A2000E 5220D0C4 E020D0C4000C C1848489958740D5 00000001 00000002 00000003 00000004 00000005 0000B8 0000BC 0000C0 0000C4 0000C8 0000AA 0000CC 0000CC MSG ONE TWO THREE FOUR FIVE DBL Figure 30 ADD.1 above).

the index register in an address will be R0 unless you explicitly use it (see below for an example). 74 . It is specified as R0. USING is a directive that does not generate code but tells the assembler something it needs to know. So the question becomes. Thus. In this case the USING is telling the assembler that R13 is the base register and that it is pointing to the 8th byte of the program which is HELLO+8 or. In fully explicit notation. will our program will be loaded into the computer memory at location zero every time? No. The SUBENTRY macro expands the same each time except for the program name which it gets form the label on the invocation and the time and date which it gets from the assembler. R13 must have 8 in it? Look at Figure 4 on page 25. So how does the assembler know to use R13 as the base register? Line 12 in Figure 4 tells the assembler that R13 is the base register. The program can be loaded anywhere in memory because all the addresses are relative to R13.(2) and the index register (0). This is how R13 gets the value 8.R13) In response to our second operand label of ONE. Next question. Then on line 11 the LR instruction copies this value to R13 (note: the systems macros use ordinary numbers for the registers. Hence we see a displacement of 0B016 and a base register of R13 in the machine code. not numbers preceded by the letter R). Several things happen here. that the label is B0 or 176 bytes from the 8th byte of the program. When R0 is used in an addressing context it means no register. what's in R13? If you look at the location counter you will see that ONE is at location B816 from the start of the program but the displacement relative to the contents of R13 is B016. There is an R0 and you can use it for arithmetic but if you use it in an address it means no value is contributed regardless of the actual value in R0. Thus the assembler knows that R13 can be used as a base register and that it is pointing 8 bytes into the program. when the assembler see the label ONE in the Add instruction. First. it calculates. in the case of our program. if the program is loaded beginning at location 1 000 00016 everything will work so long as R13 has 1 000 00816 in it. Thus. It shows the expansion of the SUBENTRY macro. The full displacement is 0B0 16 or 17610. correctly. R15 is effectively loaded with the location counter value of 8. The index register remains. in the BAL on line 4. this would correspond to: A R2. Normally.176(R0. The third byte has the base register (D or R13) and the first 4 bits of the displacement (0). the address of ONE will be the sum contents of R13 plus B016 (or 17610). This means that when the program is run. the assembler has calculated the address of ONE is at a displacement of B016 (leading zero omitted) relative to the contents of register 13. Consequently. ADD+8. Then the memory at label ONE will be at 1 000 0B816 or R13+B016.

75 . In most cases. As none of the floating point registers were used. how does R13 get 1 000 00816 in it? When the BAL instruction on line 4 of Figure 4 executes. A similar pattern is shown for the floating point registers (F0 through FF). The contents of memory beginning at location 0000000016 through location 000FFFFF16. For example. The low order bits are F4 unless the register was used in the course of the program.3 Debugging (XDUMP) A dump is ordinarily produced when a program encounters a run time exception or interrupt. RD (R13). The contents of the general purpose and floating point registers are each displayed as 16 hexadecimal digits (corresponding to 8 bytes). R2 and R3 while the last line displays the contents of registers RC (R12). Where the byte code has a printable equivalent. For example. the first line for the general purpose registers displays R0.PRN file with macro expansion printing enabled). The contents of the 16 64-bit general purpose registers R0 through RF (R15). it loads the address of the byte immediately following the BAL into R15 and R15 is eventually copied to R13. On the right hand side is an attempted conversion of each byte in the row to a printable character. all of their bytes are shown as F4. The contents of the memory are shown in rows of 32 hexadecimal digits grouped into four fields of 8 digits each. Alternatively. the printable equivalents are not meaningful. 2. displays 16 bytes of memory. a programmer can explicitly request a dump with the XDUMP macro during program execution in order to analyze program execution. if the program from Figure 28 were modified to include the XDUMP as shown in Figure 31 (shown as the . The contents of the 16 64-bit floating point register F0 through FF (F15). 13. At the beginning of each row is the address of the first byte in the row. There are four registers displayed per line. a period is printed.So. Where there is no printable character for a byte code. Each group or 8 digits corresponds to one word (4 bytes) of memory and they are separated from one another to improve readability. The contents of the dump are as follows: 1. As the program only used 32 bit instructions and since the emulator preinitializes each byte of each register to F4. So. the high order 32 bits of all the general purpose registers are F4. RE (R14) and RF (R15). the result would be the text shown in Figure 32 (long lines truncated). therefore. it is shown. Each line. 3. R1. if the program is loaded into memory beginning at 1 000 00016 the byte immediately following the BAL will be at address 1 000 00816.

12.13) (4/51)46+ L 14.L'DBL (1/13)42 XDUMP (1/14)43 SUBEXIT (4/33)44+ LA 15.12. It tells us that the first eight bytes of the line's content correspond to the characters: 09/14/10 which appears to be a date. Because each line has 1016 (1610) bytes of data..13 (1/3)15 EQUREGS (3/41)16+R0 EQU 0 (3/41)17+R1 EQU 1 (3/41)18+R2 EQU 2 (3/41)19+R3 EQU 3 (3/41)20+R4 EQU 4 (3/41)21+R5 EQU 5 (3/41)22+R6 EQU 6 (3/41)23+R7 EQU 7 (3/41)24+R8 EQU 8 (3/41)25+R9 EQU 9 (3/41)26+R10 EQU 10 (3/41)27+R11 EQU 11 (3/41)28+R12 EQU 12 (3/41)29+R13 EQU 13 (3/41)30+R14 EQU 14 (3/41)31+R15 EQU 15 (1/4)33 SR R2.33' (2/173)10+ ST 15.DBL (1/12)41 XPRNT DBL.TWO (1/7)36 A R2.L'MSG (1/11)40 XDECO R2. On the far right column is the attempted character interpretation of the bytes.12(13) (2/168)5+ BAL 15.ONE (1/6)35 A R2.* means that it is the dump of the 16 memory locations beginning at 260016 through 260F16 inclusive (16 bytes of data).15 (2/188)13+ USING ADD+8..R2 *Zero R2 (1/5)34 A R2... the address will increment by 1016.8(13) (2/174)11+ ST 13. The remaining 8 bytes did not have printable equivalents as indicated by the periods.THREE (1/8)37 A R2.4(15) (2/175)12+ LR 13.28(13) (4/53)48+ BR 14 (1/15)50 MSG DC C'Adding Numbers' (1/16)51 ONE DC F'1' (1/17)52 TWO DC F'2' (1/18)53 THREE DC F'3' (1/19)54 FOUR DC F'4' (1/20)55 FIVE DC F'5' (1/21)56 DBL DS CL12 (1/22)57 END Figure 31 Add program exposed Thus.104(15) (2/169)6+ DC 18F'0' (2/170)7+ DC CL8'ADD' (2/171)8+ DC CL8'09/14/10' (2/172)9+ DC CL8'20.FIVE (1/10)39 XPRNT MSG..4(.13) (4/52)47+ LM 2. 76 .0 (4/50)45+ L 13.. the following line: 00002600 *F0F961F1 F461F1F0 00000000 00000000* *09/14/10.12(.FOUR (1/9)38 A R2..000000 000000 000000 000000 000004 000008 000050 000058 000060 000068 00006C 000070 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000074 000078 00007C 000080 000084 000088 00008E 000092 000098 00009E 00009E 0000A2 0000A6 0000AA 0000AE 0000B0 0000C0 0000C4 0000C8 0000CC 0000D0 0000D4 0000E0 90ECD00C 45FF0068 0000000000000000 C1C4C44040404040 F0F961F1F461F1F0 F2F04BF3F3404040 50FD0008 50DF0004 18DF 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 00000A 00000B 00000C 00000D 00000E 00000F 1B22 5A20D0B8 5A20D0BC 5A20D0C0 5A20D0C4 5A20D0C8 E020D0A8000E 5220D0CC E020D0CC000C E06000000000 41F00000 58D0D004 58E0D00C 982CD01C 07FE C1848489958740D5 00000001 00000002 00000003 00000004 00000005 0000C0 0000C4 0000C8 0000CC 0000D0 0000B0 0000D4 0000D4 (1/1)1 PRINT GEN (1/2)2 ADD SUBENTRY (2/77)3+ADD CSECT (2/167)4+ STM 14.

.........\.* 00008010 *00000000 00000000 00000000 00000000* *....║...... link.........01b ON J2SE 1....C:\Documents and Settings\user\asm>assist err1 C:\Documents and Settings\user\asm>rem assemble. 00002000 *859999F1 40404040 40404040 40404040* *err1 * 00002010 *00008108 00000000 0A030000 00000000* *.Dump format 77 .....6...........á0* 000080A0 *000058D0 D00458E0 D00C982C D01C07FE* *....* .ß?......* 00002080 *00000000 00000000 00000000 00000000* *..?* 000080D0 *00000005 40404040 40404040 4040F1F5* *.......0_18 17:52:04 err1 MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 43 IO=737 17:52:04 err1 LZ390 START USING z390 V1...* 00002020 *00000000 00000000 00000000 00000000* *..err1 * 00002620 *00000000 00000000 00000000 00000000* *...........* .?............................\-. and exec ASSIST C:\Documents and Settings\user\asm>echo off 17:52:04 err1 MZ390 START USING z390 V1..... 000020D0 *000080E0 00000000 00000000 00000000* *...... 00000040 *00000000 00000000 00000000 00002000* *.............* ........ 00008050 *C1C4C440 40404040 F0F961F1 F461F1F0* *ADD 09/14/10* 00008060 *F1F74BF5 F2404040 50FD0008 50DF0004* *17..Ω?* 00008090 *D0CCE020 D0CC000C E0600000 000041F0* *}÷\?}÷......5555555* 00008100 *80008000 000000E0 00000000 000F7EF8* *╪..?..........5........??..........* 00000050 *00000000 00000000 00000000 00000000* *...╪..6... 00002140 *F4F4F4F4 F4F4F4F4 00000000 00000000* *44444444.....* 00002610 *00000000 00000000 859999F1 40404040* *..........390* 000080F0 *80008000 F5F5F5F5 01F5F5F5 F5F5F5F5* *╪."?err1..............0_18 17:52:04 err1 LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 14 IO=36 17:52:04 err1 EZ390 START USING z390 V1..q?}..╪.0_18 Adding Numbers 15 R0-R3 F4F4F4F480008000 F4F4F4F400002300 F4F4F4F40000000F F4F4F4F4F4F4F4F4 R4-R7 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 R8-RB F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 RC-RF F4F4F4F4F4F4F4F4 F4F4F4F480008008 F4F4F4F400002018 F4F4F4F480008008 F0-F3 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4-F7 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F8-FB F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 FC-FF F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 00000000 *00000000 00000000 00000000 00000000* *......* 00002150 *00000000 00000000 00000000 00000000* *...╪\.......╪?............╪........ 00002070 *00000000 9B000000 00000000 00000000* *............... 00008000 *90ECD00C 45FF0068 00000000 00002100* *░╓}..................... 00002600 *F0F961F1 F461F1F0 00000000 00000000* *09/14/10....01b ON J2SE 1........⌂┌* 000080B0 *C1848489 958740D5 A4948285 99A2F6F6* *Adding Numbers66* 000080C0 *00000001 00000002 00000003 00000004* *.52 &┘....╪..5.......* .......01b ON J2SE 1....* 00002310 *00000000 00000000 00000000 00000000* *......* 00000010 *00002000 00000000 00000000 00000000* *... 000FFFF0 *F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5* *5555555555555555* 17:52:05 err1 EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 21 IO=79 INS=21 Figure 32 .....╟.?..6....a?.?..... 00002100 *00000000 00000000 80008008 00002018* *.......=8* 00008110 *F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5* *5555555555555555* . 00002300 *00002304 00000000 00000000 00000000* *....* 00002110 *80008000 80008000 00002300 F4F4F4F4* *╪........╪.╪..5...?* 00008070 *18DF1B22 5A20D0B8 5A20D0BC 5A20D0C0* *...............* .* . ??!?}╜!?}»!?}{* 00008080 *5A20D0C4 5A20D0C8 E020D0A8 000E5220* *!?}D!?}H\?}y....* . 15* 000080E0 *00000000 000F7F20 859999F1 4BF3F9F0* *.* 00000020 *00000000 00000000 00000000 00000000* *.....* ....?.....?..5555......?& ....* 000020E0 *00000000 00000000 00000000 00000000* *.4444* 00002120 *F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4* *4444444444444444* ...........* ...∞}}?∞\}..

because of the emulator. R14 has the return address. therefore. Note that R2 has 15 (F16) in it which is the answer from the calculations. F (R15) is the B2 field (base register).. the presence of "…. as expected. D (R13) is in the B2 field and 00C16 is in the D2 field. 201816 and register 15 has the same contents as R13.From Figure 31 we can see that the first executable instruction is: STM 14. The 12 bytes beginning at label DBL can be seen to start at byte 80D416.12(13) which corresponds to the machine code: 90ECD00C An STM instruction is a Store Multiple and it is of type RS: STM R1. If you look in the dump at address 800016 you will see the code for the STM instruction.. In the memory dump area. 78 .D2(B2) The opcode is 9016.R3. E (R14) is in the R1 field. Since the program is loaded at location 800016. Moving on. 800016 is. the first byte of the program. R13. Looking at the general purpose registers you can see the contents of the base register.. In the instruction in the program. This can be deduced from the location counter address from the assembler for DBL which is D416. This corresponds to the address of the start of the save area as described in section 11. at 80D416. the label DBL is . are 8000800816 (High order bit is 1 but only the lower 31 bits are used for addressing). Details on subroutine linkage are given in section 11 above.104(15) which is the Branch and Link RX instruction and translates into the machine language: 45FF0068 Where 45 is the opcode. 0 (R0) is the X2 (index register) field and 06816 is the D2 field (displacement in hex). all programs will appear to begin at location 800016. therefore. C (R12) is in the R3 field. F (R15) is the R1 field..2 above. the next instruction following the STM is: BAL 15." in the address column means the missing lines are the same as the line above.12. In fact.

Using the dump and the assembler listing. Thus. the next at ONE+8 and so one. The body of the program begins with the SR at 807216 followed by the Add instructions. that is.5 More Addressing Alternatives In reality. Instead. THREE. we will use a Branch Conditional (BC) instruction. we can select any register not otherwise in use except R0. The purpose of the Compare instruction is to set the Condition Code. 13. To loop.The full words for labels ONE. the actual problem is normally at the instruction preceding the address in the PSW. There are several ways to do this but the obvious one is to used the index register in the Add instruction (presently R0 meaning no register). If your program fails. few programmers would code as shown in either Figure 28 or 33 . In Figure 33 the offsets from the label ONE become added to the displacement. Thus. 13. using literal notation). to increment it and we need a loop mechanism.4 Data Addressing Alternatives The program in Figure 28 used several labels. the actual machine code is identical to that in Figure 28. pointing at the next instruction. TWO. we also need a way to test if we are done and loop if we are not. can be seen in Figure 33. which generates identical machine language. For the loop mechanism. In the Add instruction following LOOP we increment the index register (R3) by 4 (using literal notation) then we compare the contents of R3 with the value 16 (again. 79 . An alternative. To do the test. In Figure 34 we've selected R3 for our loop index register which we initially set to zero. Each DC statement generates exactly 4 bytes of data and these are arranged at consecutive memory locations. Here only one label (ONE) is used for each of the second operands but with an increment that takes into account the number of bytes from the label ONE to the desired operand. the 4 bytes following label ONE are at ONE+4. 80C816. As the PSW is always updated. For a register. need to initialize it. To do this we need an additional register. we will use the Compare instruction. 80C416. a loop would be used with a register that incremented by 4 for each iteration and its values added to a base address. FOUR and FIVE can be seen at 80C016. you will normally be given the address contents of the PSW at the time of the failure. 80CC16 and 80D016. it should be easy to locate where the error took place and determine how it was caused. We've added a new label: LOOP which is where we'll branch to until we've added all the numbers.at least not for any significant number items to be added.

ONE+16 XPRNT MSG.6 Using Extended Mnemonics Figure 35 is a related example. If the contents of R3 are equal to 16. The initializes R2 to 0 and R3 to 1 (lines 4 & 5). When the contents of R3 exceed 16. They are. the Condition Code is set to 0. in effect.DBL XPRNT DBL. It is a program to sum the integers from 1 to 100.ONE A R2.ONE+12 A R2. Then it tests R3 against the value 100 (line 8) and branches (line 9) back to LOOP if the contents of R2 are less than 101 or falls through to the next instruction (XDECO) when the contents of R3 become equal to 101. the branch will not take place the the instruction following the BC instruction.ONE+8 A R2.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Figure 33 ADD1. The BC instruction will branch if the Condition Code is 0 or 1 as indicated in Chapter 8. Note: if you do not include a LTORG. These will include the =F'4' and =F'16' used above. will execute.ONE+4 A R2. the Condition Code is set to 1. 13. the assembler will place any literals it has accumulated at the end of your program anyway.Alternative 1 In the BC instruction (line 9) we tell the computer to branch to label LOOP if the Condition Code indicates that the Compare instruction (line 8) found that the value in R3 was less than or equal to 16. the XPRNT (line 10). 80 . The LTORG directive at the end tells the assembler to place any undeclared literals at this place in your program. If contents of R3 are less than 16.R2 *Zero R2 A R2. assembler generated DC statements.L'MSG XDECO R2. It adds R3 to R2 then increments R3 (lines 6 & 7).1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ADD MSG ONE DBL PRINT NOGEN SUBENTRY EQUREGS SR R2.MLC .

Alternative 2 In Figure 35 we see another form of the BC instruction is used: the extended mnemonic form.L'MSG XDECO R2.R2 *Zero R2 SR R3.=F'1' * increment R3 C R3.LOOP XPRNT MSG.L'DBL SUBRETURN LTORG DS CL12 END Figure 35 Loop example 81 .R2 * zero R2 L R3. They help make your program more readable but are. BL on line 9 is really a BC with a mask of B'0100'.ONE(R3) A R3.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ADD LOOP MSG ONE DBL PRINT NOGEN SUBENTRY EQUREGS SR R2.MLC .DBL XPRNT DBL. in reality.DBL XPRNT DBL.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 LTORG END Figure 34 ADD2. 1 2 SUM100 3 4 5 6 LOOP 7 8 9 10 11 12 13 14 DBL 15 PRINT NOGEN SUBENTRY REGS SR R2.R3 A R3.=F'1' * init R3 AR R2.R3 *Zero R3 A R2.=F'101' BL LOOP XDECO R2.=F'16' BC B'1100'. no different than the BC instruction with the appropriate mask. There are several of these forms accepted by the assembler as shown in Table 9 on page 46.=F'4' C R3.

82 .

This happens in 32-bit addition when the result exceeds the maximum allowed for a 83 . when a SH or AH is executed. AH. S. The first operand is treated as a 32 bit signed binary integer. Both operate on 32 bit signed (2s complement) binary integers. 14. the 2 bytes from memory are expanded to 32 bits by extending the sign before the operation with the register takes place.14 Other Binary Arithmetic Instructions 14. Similarly.1 Subtraction Similar to the A and AR instructions are the Subtract S and SR instructions. AR. 14. SH and SR can encounter situations where the result of the operation would overflow the register. Result zero < zero > zero overflow Condition Code 0 1 2 3 Table 18 Conditions Codes 14.2 Halfword Instructions In addition to full word Add and Subtract. The value in memory is unchanged. The S instruction is of type RX and the SR is of type RR. In the case of a STH. the low order 16 bits of the register are stored in memory at the address specified by the second operand. there are also halfword RX versions of these: AH and SH along with the utility instructions Load Halfword (LH) and Store Halfword (STH). When a LH is executed. The first operand of each of the halfword instructions is a register. Both subtract the contents of the second operand from the register specified as the first operand leaving the result in the first operand.3 Condition Codes After Binary Operations All signed arithmetic add and subtract instructions set the Condition Code to indicate the result of the operation as shown in Table 18. the 2 bytes from memory are loaded into the low order two bytes of the register and then the sign bit of the value from memory is extended to the high order 16 bits of the register.4 Overflows The signed arithmetic instructions A. The second operand is a 2 byte location in memory.

signed positive 32 bit number (+2,147,483,647) or the minimum allowed for a signed negative 32 bit number (-2,147,483,648). Overflows can also occur with the Shift Left Arithmetic (SLA) and Shift Left Double Arithmetic (SLDA) instructions when a bit unlike the sign bit is shifted into the sign bit position (the high order bit). As this would result in a sign change, it is considered to be an overflow. When an overflow occurs, the Condition Code is set to 3 and a fixed-pointoverflow exception interrupt is raised. This normally results in program termination unless bit 20 of the PSW is on in which case the interrupt is disallowed. 14.5 Unsigned Arithmetic (AL, ALR, SL, SLR) The architecture provides for unsigned arithmetic in the form of the Add Logical (AL and ALR) and Subtract Logical (SL and SLR) instructions. All four instructions treat both operands as unsigned 32 bit binary integers. The AL and SL instructions are of the RX type with the first operand the contents of a register and the second the contents of a specified memory address. In the ALR and SLR instructions, both operands are memory resident. As with the other Add and Subtract instructions, the result is placed in the first operand. An overflow cannot occur as a result of these instructions. Instead, the Condition Code indicates if a carry took place as shown in Table 19.
Condition code zero, no carry 0 not zero, no carry 1 zero, carry 2 not zero, carry 3 Table 19 CC after logical add/subtract Result

This information can be used to construct extended precision binary integer arithmetic. 14.6 Multiply (M, MR) The basic binary integer multiply instructions are the M and MR. In both, the first operand specifies the even register of an even/odd pair of registers. The multiplicand is a 32 bit signed integer which resides in the odd register of the pair. The multiplier is a 32 bit signed integer which resides either in the register designated as the second operand (MR) or at the memory address specified (M). The contents of the even register are ignored. The result is a 64 bit signed binary number which is placed in the even/odd register pair with the high order 32 bits or the result in the even register and the low order 32 bits in the odd register. The sign of the result is determined by rules of algebra except a zero result is always positive. No overflow can take place and the Condition Code remains unchanged.
84

There is also a MH instruction where a 16 bit signed number from memory is multiplied by the 32 bit signed contents of the register specified as the first operand. The low order 32 bits of the result replace the contents of the first operand. No overflow can occur and the Condition Code remains unchanged. For example, If R5 contains 2010 and R6 contains 310, we can multiply them with the instruction:
MR R4,R6

The result will be in R4 and R5. As the answer is 6010, the result is effectively in R5. R6 will contain results only in the case when answers exceed 32 bits. 14.7 Divide (D, DR) The basic binary integer divide instructions are D and DR. In both, the register specified as the first operand, the dividend, is the even register of an even odd pair. Both registers are treated as one 64 bit signed binary integer with the high order part of the number in the even register. The divisor is a 32 bit signed number located in the register specified as the second operand (DR) or at the memory location specified by the second operand address. The result consists of a remainder located in the even register of the first operand and the quotient located in the odd register. The sign of the of the quotient is determined by the rules of algebra and the remainder has the same sign as the divided except that zero is always positive. A divide by zero will raise a fixedpoint divide exception. The condition code is unchanged. For example, if location VAR1 contains the 32 bit number 10, and location VAR2 contains the 32 bit number 3, you can divide the value at VAR1 by the value at VAR2 with the following:
L R2,VAR1 SRDA R2,32 D R2,VAR2

The result will be 1 in R2 (the remainder) and 3 in R3 (the quotient). Because all 64 bits of the even/odd pair R2/R3 participate, we load the dividend into the even register and then do a shift double arithmetic to the right by 32. In the SRDA instruction, both registers of the even odd pair participate. Effectively, we are loading the dividend into the odd register but insuring that the even register will contain bits like the sign bit of the dividend. See section 17.3.2 Arithmetic (SRA, SRDA, SLA, SLDA) on page 100 for full details on the arithmetic shift instructions.

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86

the implied length attribute of the first operand is used.1.L2 MVC MVC * MVC MVC * L1 L2 DS DC 0(20.see Figure 15 on page 39).L2 *20 bytes from L2 are copied to L1 *10 bytes from L2 are copied to L1 LA R2. In SI (storage immediate) instructions (see Figure 14 on page 38).L2 L1(10). the actual length is coded (one will be subtracted from this value in constructing the machine language representation).2 Move Immediate (MVI) The MVI (Move Immediate) instruction copies the immediate byte from the instruction to an address in memory. in the machine language format. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MVC MVC L1. the length is expressed as an 8 bit field whose value is one less than the actual length to be moved.1 Basic Character Instructions The basic architecture has several instructions to compare and move strings of character data.0(R3) * 10 bytes from L2 are copied to L1 * beginning at position 10 in L1 L1(1).R2). In the case where no length is supplied. In the machine language coding of an MVC (as is also the case with other SS character instructions . Some examples are given in Figure 36.15 Character Instructions 15. The addresses may overlap. and so on. These were extended in later versions of the architecture but we begin with the most basic. Thus.0(R3) * 20 bytes from L2 are copied to L1 10(10. It is an SS instruction and copies up to 256 bytes form the operand specified as the second to the operand specified as the first address. a length value of 0 means move 1 byte and a length value of 255 means move 256 bytes.1 Moving Characters (MVC) The basic character move instruction is the MVC instruction.L1 * blank is copied to the 1st byte of L1 * overlapped move . the second operand is a single byte contained in the 87 .1.=C' ' L1+1(19).R2).L1 LA R3. In the assembly language representation.L1 is made * all blanks CL20 C'ABCDEFGHIJKLMNOPQRST' Figure 36 MVC Examples 15. 15.

The instruction compares successively each corresponding byte of each operand (first with first. If all bytes are found to be equal.X'C1' L1. The first operand greater than the second. the second operand appears second. As with the MVC.L3 * CC will be 2 CLC L1(3). The byte with the larger absolute value is considered the greater of the two. the instruction halts and the condition code is set to reflect the inequality.3 Compare Logical Characters (CLC) The basic instruction for comparing strings of bytes is the CLC (compare logical character)instruction. The instruction continues so long as the bytes compared are equal. the second operand actually appears in the machine format before the first operand as shown in Figure 14 on page 38. When characters are compared.1.instruction. Because of the EX instruction. However. the length encoded in the machine language format is one less than the actual length. 15. the condition code is set to 0 and the instruction halts. If the byte from the first operand 88 .only 3 bytes compared L1 L2 L3 DC C'ABCDEF' DC C'ABCDEX' DC C'ABCDEA' Figure 38 CLC Examples If the instruction encounters an unequal pair of bytes.C'A' L1. MVI MVI MVI MVI L1.L2 * CC will be 0 . It is never a literal (for example.B'11000001' L1. This is called the immediate operand and is designated as I2 in the instruction set description. The condition code is set to indicate the result: CC=0 CC=1 CC=2 CC=3 All bytes in both operands are equal. Figure 37 has some example.L2 * CC will be 1 CLC L1. The first operand less than the second. CLC L1. when writing in assembly language. second with second. If the length is not specified. is not possible. and so forth).193 * * * * sets sets sets sets byte byte byte byte at at at at L1 L1 L1 L1 to to to to be the letter A A (C1 is hex for A) A (binary code for A) A (decimal equivalent) Figure 37 MVI Examples Note that the scond operand of the CLI is always a constant. C'A' and never =C'A'). the assembler will use the length attribute of the first operand. they are compared one by one as unsigned 8 bit bytes. It is an SS format instruction using a single 8 bit length field as shown in the format in Figure 15 on page 39.

The shorter operand is considered to be extended to the right by the padding byte. Up to 16M bytes can be compared. the byte in memory at label XXX is compared with the immediate byte containing the EBCDIC code for the letter A.1 Compare Logical Character Long (CLCL) The CLCL instruction is an RR instruction. The odd register of the first operand contains the first operand's length expressed in the low order 24 bits of the odd register. The condition code is set to reflect the relationship. For example: CLI XXX. the CLC and MVC instructions were limited to character strings no longer than 256 bytes. In the original architecture. This is no longer an issue. should more than one interrupt take place while they are executing.2 Character Long Instructions Two instructions were added to the architecture when the IBM 360 evolved into the IBM 370.2. The odd register of the second operand contains an 8 bit padding byte followed by a 24 bit length. if needed.3. The IBM 370 architecture introduced the CLCL and MVCL instructions with a string length limit of 224-1 (16 MB).1 Compare Logical Immediate (CLI) The first one.X'C1' where the hexadecimal code C116 is the equivalent of the letter A. 15. 15.1. The instruction compares the bytes beginning at the address specified by the even register of the first operand (R1) with the bytes at the address specified by the even register of the second operand (R2). 15. otherwise. 2. These are the CLCL (compare logical character long) and MVCL (move character long). Comparison is byte by byte.is less than the byte from the second operand. the first interrupt might be overwritten by the second. the following has the same effect: CLI XXX. compares one byte in memory with the instruction's immediate byte and sets the condition code accordingly. Alternatively. The string length was said to be based on the maximum amount of time an instruction could execute on a low end version of the IBM 360 without the possibility of missing an interrupt. Both operands must designate the even register of an even-odd pair. the condition code is set to 1. CLI.C'A' In this case. Both the MVC and CLC are uninteruptable and. Figure 38 gives examples. 89 .

The table is 256 bytes long. are bytes from the first operand used as source bytes after bytes have been moved into same. The Condition Code is 3 and no copying is performed if a destructive overlap is detected. The instruction copies the bytes beginning at the address specified by the even register of the first operand (R1) with the bytes at the address specified by the even register of the second operand (R2). and 2 if the first operand is greater than the second. the operation terminates and the byte from the table is placed in the low order byte of register 2 and the address of the byte from the source string causing the halt is placed in register 1. If all tested bytes are zero. and 2 if the first operand is longer than the second. The instruction is interruptible. 90 . If the byte in the table is zero. If the byte in the table is non-zero. Up to 16M bytes can be copied. the condition code becomes zero. If there was no destructive overlap the Condition Code is 0 if both length are equal. the operation continues. 1 if the fistr operand is shorter than the second. 3. the even registers of both operands contain the addresses of the unequal bytes. The length fields in the odd registers of both operands give the number of bytes remaining to be compared when the operation ended. The odd register of the first operand contains the first operand's length expressed in the low order 24 bits of the odd register.The comparison terminates when an inequality is found or at the end of the longer operand. If the first operand is longer than the second. The Condition Code will be set to 0 if both operands are equal. 2.2. Both operands must designate the even register of an even-odd pair. The odd register of the second operand contains an 8 bit padding byte followed by a 24 bit length. the first is padded to the right by the padding byte. If the operation ends with an inequality. The instruction is interruptible.3 Translate (TR) and Translate and Test (TRT) Scanning input fields is important so the 360 architecture provided a single instruction to do this known as the TRT (Translate and Test) instruction. The instruction checks for destructive overlap. That is. The byte found in the table at the offset determined by the source byte decides what should happen: 1.2 Move Character Long (MVCL) The MVCL instruction is an RR instruction. 15. Source bytes from the string are successively (left to right) used to index into the table. The TRT uses a table (given as the second operand) and a string (the first operand). 1 if the first operand is less than the second. 15.

This is shown in Figure 39. Then. To use a TRT to do the scanning you need a table that causes the TRT to continue to scan if blanks are encountered and to halt if a non-blank character is found. The Condition Code is set to 2 if the source string byte was the final byte of the source string. Next. An ORG with no argument resets the location counter to the highest value it has ever held. 91 . will cause the TRT to halt). Go into the table at offset 64 and change the value to X'00'. The source string is not altered. the assembly language provides short cuts: 1. Build a table all of whose bytes are non-zero (X'01'. TAB DC ORG DC ORG 256X'01' TAB+C' ' X'00' Figure 39 TRT Table with ORG In Figure 39. Now the location counter is in the table at the offset corresponding to a blank. you back into the table and replace the byte corresponding to the offset of blank (4016 . it is also clear that typing 256 bytes is not pleasant. While this may sound complicated it isn't. The example in Figure 45 scans each input record for the first word delimited by blanks. for example). we reset the location counter to the start for TAB plus C' ' (which is the equivalent of saying 4016 or 6410 but is easier to understand). Here you place the X'00' and this replaces the X'01' that was here. 2. first you build a table of 256 bytes all initialized to X01 (these bytes. If a tested byte is non-zero. you need a table were all the values are non-zero except the value corresponding to the offset of the blank character (hex 40 or decimal 64). since they are not zero. While the concept of the table is simple. Hence the naked ORG (no argument) The effect of all this is to create a table mainly of X01 codes except in the offset position for blank. and prints the word. However. Take for example the case where you want to scan a source string for the first non-blank character. 6410) with X'00'. a not uncommon thing to do.4. The ORG directive resets the assembler's location counter to the value specified. In this case. the Condition Code becomes 1 if the byte from the source string was not the final byte of the source string. you need to cause the location counter to spring back to where it was when you initially built the table (or subsequent code will overwrite the remainder of the table). Putting it simply.

0(R3) L1 * addr of non-blank * target * copy 1st byte * * * * * * * * * increment increment end addr at end? yes blank? yes .ATEND XPRNT REC.WORD 0(1.1(R0.0(R3) R3.R1 R5.L'WORD * print word WORD.R3) R5.WORD * ripple move LOOP * again * * * ATEND EXIT * * * REC WORD MSG TAB EOJ processing XPRNT MSG.C' ' PRNT 0(1.R3).R5).1(R0.REC+30 R3.L'REC LA TRT BE LR LA MVC L1 LA LA LA CR BNL CLI BE MVC B XPRNT MVI MVC B R3.L'MSG SUBEXIT Literals LTORG DS DC DC DC ORG DC ORG END CL32 actual input record CL30' ' C'***** DONE *****' 256X'01' TAB+C' ' X'00' BEGIN Figure 40 TRT Example (continued on next page) 92 .C' ' * blank to 1st position WORD+1(L'WORD-1).1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 PRINT NOGEN START 0 REGS * PROGRAM TO SCAN AN INPUT IMAGE FOR THE FIRST * WORD DELIMITED BY A BLANK BEGIN LOOP SUBENTRY XREAD REC.REC 0(L'REC.TAB EXIT * only blanks found R3.R4 PRNT 0(R3).R5).L'REC BC B'0100'.end move next loop source addr target addr * read a record * EOF? * write the record of word character PRNT WORD.R5) R4.

verifies their content.C' ' B'1111'.PCK 0(R1).TAB B'1000'.The input images are: TEST1 TEST3 TEST2 * * * Figure 40 TRT Example (continued) The example in Figure 45 reads records with numbers.NBR B'1111'.C'1' B'0111'. sums and prints the result.C' ' B'1111'.C'-' B'0111'.X'FB' SUM.negative loop EOF processing XPRNT MVC ED XPRNT MSG.=X'4020202020202120' RSLT.RET PACK CLI BC NI AP BC NBR.L'REC B'0100'.ATEND REC. 1 2 3 4 SUB 5 6 LOOP 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLUS 21 22 23 24 25 ERR 26 27 28 PCK 29 30 31 32 33 34 ADD 35 36 37 * 38 * 39 * 40 41 ATEND 42 43 44 PRINT NOGEN START 0 REGS SUBENTRY XREAD BC XPRNT MVI TRT BC CLI BC MVI MVI BC CLI BNE MVI BC REC.L'ERRMSG BC B'1111'.a blank plus sign found make + a blank must be bad data XPRNT ERRMSG.L'REC NEGFLG.C'0' REC.BPLUS NEGFLG.ADD NBR+7.PCK read a record EOF? write the record set flag to 0 only blanks and numbers minus sign found? set flag to 1 make .REC NEGFLG.C'1' 0(R1).PCK 0(R1).L'RSLT Figure 41 TRT Verifying Input (continued on next page) 93 .SUM RSLT.C'+' ERR 0(R1).l'MSG RSLT.LOOP is this number neg no yes: make its sign D .

BAD DATA' 256X'01' TAB+C'0' 10X'00' TAB+C' ' X'00' SUM Figure 41 TRT Verifying Input (continued) 94 .45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 RET REC NBR NEGFLG SUM RSLT MSG ERRMSG TAB SUBEXIT LTORG DS DC DC DC DC DC DC DC ORG DC ORG DC ORG END CL10 actual input record PL4'0' C'0' PL4'0' X'4020202020202120' C'DONE***************' C'ERROR .

R4.R4. The registers to be loaded begin with the register specified as the first operand through and including the register specified as the third operand. only 4 bytes are stored.R3. If the first and third operands both specify the same register. LR R5. … R0. The Condition Code is unchanged.R2. STM R1. The word in memory should be on a word boundary (a memory address evenly divisible by 4). only 4 bytes are loaded.R4 and R5 are loaded * R6. … R4 are stored 95 . If the register specified as the first operand is greater than the register specified as the third operand.5 Store Multiple (STM) One or more general purpose registers are stored to consecutive words beginning at the memory address specified as the second operand. It is an RX instruction.L2 * R1. LM R1.R2. 16. The Condition Code is unchanged.L2 * R1.4 Load Multiple (LM) One or more general purpose registers are loaded from consecutive words beginning at the memory address specified as the second operand. The Condition Code is unchanged.3 Store (ST) The store instruction stores the 32 bit contents of a register to a word in memory.1 Load (L) The load instruction load a 32 bit word from memory into a general purpose register.R7. … R0.L1 STM R6. … R4 are loaded.2 Load (LR) The contents of the register specified as the second operand are copied to the register specified as the first operand.R3. wrap around occurs. The memory address should be a word boundary. The Condition Code is unchanged. The Condition Code is unchanged.R6 16. If the register specified as the first operand is greater than the register specified as the third operand. wrap around occurs. If the first and third operands both specify the same register. ST R5.R5. The registers to be stored begin with the register specified as the first operand through and including the register specified as the third operand.L1 16.R5.R4 and R5 are stored * R6.L1 16.16 Miscellaneous Register Operations 16.R7.R1. L R5.L1 LM R6.R1.

8 Load Negative (LNR) The 2s complement of the absolute value of the signed binary integer contained in the register specified as the second operand is loaded into the register specified as the first operand.6 Load and Test (LTR) The contents of the register specified as the second operand are loaded into the register specified as the first operand and the Condition Code is set to reflect the value of the binary integer word copied. no overflow Not possible Greater than zero. CC=0 CC=1 CC=2 CC=3 Zero. CC=0 Zero CC=1 Negative CC=2 Positive 16.16. The Condition Code is set.7 Load Positive (LPR) The absolute value of the signed binary value in the register specified as the second operand is loaded into the register specified as the first operand. The Condition Code is set. Often both operands are specified as the same register in which case the only effect is to set the Condition Code. Both operands may be the same register. CC=0 CC=1 CC=2 CC=3 Zero Negative Not possible Not possible 96 . no overflow Overflow 16.

3. 17. If either or both bits are 0. 2. the resulting bit is 1. the resulting bit is 0.2 OR (O. the resulting bit is 0. 17. 4. NC) In the bitwise AND instructions.1.the bits from the word in memory addressed by the second operand are and'ed with the bits in the register designated as the first operand and the result is placed in the first operand. The bitwise OR instructions are: 1. The basic Boolean operations. RX. If either or both bits are 1.the bits of the operand in the register designated as the second operand are and'ed with the bits of the register designated as the first operand and the result is placed in the first operand. NI .17 Bit Operations Bit operations involve modification or manipulation of individual bit in an operand.1 AND (N. OR. SI or SS instructions. OC) In the bitwise OR instructions.SS format . OR . the corresponding bits from both operands are or'ed. NI.RR format .the bits of the operand in the register designated as the second operand are or'ed with the bits of the register designated as the first 97 . NC . NR . OR. The bitwise AND instructions are: 1.from 1 to 256 bytes beginning at the address specified by the second operand are and'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand. 17. N . If both bits are 1.1. NR. the resulting bit is 1. the designated operation takes place between the corresponding bits of each operand and the result replaces the first operand. AND. The COMPLEMENT and SHIFT instructions work only on operands in registers. corresponding bits from each operand are and'ed together. OR. If both bits are 0.RX format .the bits in the immediate operand are and'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory.SI format .RR format . The number of bytes is determined by an 8 bit length field.1 Boolean Instructions In the Boolean instructions (AND. and EXCLUSIVE OR). EXCLUSIVE and OR can be RR. OI.

the bits from the word in memory addressed by the second operand are exclusive or'ed with the bits in the register designated as the first operand and the result is placed in the first operand. XR. XC . XR . OC .RX format . XI.2 Complement LCR There is only one complement instruction: LCR.SI format . 4. If both bits are 0 or if both bits are 1. 7. The bitwise EXCLUSIVE OR instructions are: 1.the bits of the operand in the register designated as the second operand are exclusive or'ed with the bits of the register designated as the first operand and the result is placed in the first operand.the bits in the immediate operand are or'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory.the bits in the immediate operand are exclusive or'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory.SI format .from 1 to 256 bytes beginning at the address specified by the second operand are or'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand.SS format . If one bit is 0 and the other is 1. 6. OI .3 Exclusive OR (X. O . 3. Both register designations may be the same in which case the contents of the designated register are complemented. XI . 5.1.operand and the result is placed in the first operand. The LCR loads into the register designated as the first operand the 2s complement of the contents of the register designated as the second operand. The condition code is set: 98 . X . 2.the bits from the word in memory addressed by the second operand are or'ed with the bits in the register designated as the first operand and the result is placed in the first operand. XC) In the bitwise Exclusive OR instructions corresponding bits from both operands are exclusive or'ed with one another. 17.from 1 to 256 bytes beginning at the address specified by the second operand are exclusive or'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand. 17. The number of bytes is determined by an 8 bit length field. The number of bytes is determined by an 8 bit length field.RX format . the resulting bit is 1. A value of zero in is unchanged (the 2s complement of 0 is 0).SS format . the resulting bit is 0.RR format .

Logical shifts treat all bits the same.3. For all the shift instructions the first operand designates the register to be shifted and the second operand indicates the number of bit positions to be shifted. SRDL.10 In this case the second operand is shorthand for: 0(R0) and thus the instruction means to shift the contents of R5 left 10 binary positions. the register specified as the operand must be the even register of an even-odd pair. In many cases only the displacement is specified such as: SLL R5. There is no special treatment of the sign bit position. When shifting to the left. 17. No overflow can occur.4. shifting it 2 positions to the left multiplies by 4.1 Logical (SRL. etc. SLL. They are classed as either logical or arithmetic.8. On a right shift. Shifting a binary number to the left has the effect of multiplying it by 2. If the base is specified as zero. an overflow occurs. the amount of shift is the displacement. If the base is specified as any other register. 3 positions by 8 and so forth. On both left and right shifts a zero bit replaces the shifted bit. bits like the sign bit replace the shifted bits. shifts may be either single (only one register participates) or double (two registers participate). Additionally. The number of bits to shift is calculated from the base and displacement of the second operand. SLDL) The logical shift instructions are: 99 . shifting a binary number to the right has the effect of dividing by 2.3 Shift The shift operators move bits either left or right in one or more registers. Similarly.CC=0 CC=1 CC=2 CC=3 Result 0 Result negative Result positive Overflow 17. In the case of a double shift. the contents of the register plus the value of the displacement are the number of bits to shift. if a bit unlike the sign bit is shifted into the sign bit position. Arithmetic shifts are cognizant of the sign bit.

shift right logical (single) SRDL . if a byte in memory at label L1 has the value: 0011 0101 The instruction: TM L1. 17.B'00110101' will set the Condition Code to 3 (all tested bits were 1s).shift left double logical The Condition Code remains unchanged. bits like the sign bit are provided to replace the shifted bits.B'00001111' 100 . The instruction: TM L1. The instruction: TM L1. SLDA) The arithmetic shift instructions are: SRA . SLA.shift right double logical SLL . The bits of the byte in memory addressed by the first operand corresponding to those bits with a value or 1 in the the immediate operand are tested and the Condition Code is set. If the tested bits are mixed 1s and 0s.B'11001010' will set the Condition Code to 0 (all tested bits were 0s).shift left double arithmetic The Condition Code is set: CC=0 CC=1 CC=2 CC=3 Result is 0 Result is negative Result is positive Overflow An overflow can occur only in left shifts when a bit unlike the sign bit is shifted into the sign bit position.shift left arithmetic (single) SLDA . During right shifts.4 Test Under Mask (TM) The TM instruction is an SI instruction. the Condition Code is set to 3. Zeros are provided to replaced the shifted bits.shift right arithmetic (single) SRDA . the Condition Code is set to 0. 3. During left shifts.2 Arithmetic (SRA. 1. the Condition Code is set to 1. For example. 2. If all the tested bits are 1s. 17.shift left logical (single) SLDL .3. zeros are supplied to replace the shifted bits.shift right double arithmetic SLA . If all the tested bits are 0.SRL . SRDA.

On the other hand. Regardless of the result. Subtract. SP. the Condition code is set to 1.will set the Condition Code to 1 (tested bits were mixed). Zero and Add Positive (AP. What this instruction avoids is the situation where a program tests a byte. the byte in memory is set to 1111 1111.5 Test and Set (TS) The TS (Test and Set) instruction is an SI instruction but the immediate operand is omitted. The TS instruction is uninterruptible . The result occupies the first operand. If the second operand is short. The Condition Code is unchanged. The instruction tests the leftmost (high order) bit of the byte in memory designated by as the first operand. Subsequent bytes (to the left) of the source are read.the testing and setting take place in one operation. When the first program regains control it believes that the byte is 0s. likewise marks it as 1s and now two programs believe they own the block of memory. If the byte is all zeros a TS on the byte will reflect this in the Condition Code and mark the byte as all 1s. an interrupt occurs and another program gains control. The original purpose of this instruction was to provide an uninterruptible way in which to see if a resource is available and mark it as in use. If the bit is 0. the first operand is padded to the left with zeros. The zone and digit of first byte of the source are reversed and placed in the right most byte of the target. 18. the Condition Code is set to 0. Example.2 Add. Further examples are given in Chapter 21.1 PACK Both operands are in memory. the zone removed and the digit portion stored in the next available half byte going right in the target. 18 Decimal Arithmetic 18. If the bit is 1. see 0s. Likewise this program tests the same byte. sees 0s and sets the byte to 1s. 17. but before it can set the byte. a TS will indicate this and have no real effect (the byte is still all 1s). consider the case where a byte is used to indicate that some block of memory is available with all 0s indicating it is available for allocation and 1s indicating it is in use. if the block is allocated and the byte is all 1s. The second operand is treated as a zoned decimal number. The operands are processed from right to left. ZAP) 101 .

When the instruction begins the significance indicator is off. 1 if the result is less than zero. The first byte of the first operand is the Fill byte. Following the fill byte are a collection of pattern bytes and message bytes. The Condition Code is unchanged. In order to prevent an overflow from occurring. It stays off until a significant digit (i. non-zero) is encountered or turned on by a pattern byte. 18. a data exception occurs. A Decimal Divide exception occurs in the case of divide by zero or a quotient too large to fit in the digits available. The Condition Code is unchanged. they remain in the result. When the significance indicator is off.3 Multiply Packed (MP) The multiplier (the second operand) is multiplied by the multiplicand (first operand) and the result is placed in the first operand. In the case of the ZAP. The results are a quotient and a remainder which wil replace the dividend. The multiplier may not be longer than 15 digits and must be shorter in length than the multiplicand.4 Divide Packed (DP) The first operand is the dividend and the second operand is the divisor. 18. message bytes are replaced by the fill byte. The remainder occupies the remaining bytes of the first operand. the multiplicand must include at least as many leading bytes of zeros as the number of bytes in the multiplier. 18. The first operand must be large enough to contain the result or a Decimal Overflow occurs.. The first operand is a set of pattern codes that control the formatting process and the second operand is the packed number to be converted. Its length is equal to the difference between the length of the dividend (L1) and the divisor (L2). The result replaces the first operand. The Condition Code will be zero if the result is zero. The divisor may not be longer than 15 digits. 2 if the result is greater than zero and 3 in the case of overflow.5 EDIT (ED) The ED instruction is used to convert packed decimal number to zoned decimal (printable) values. If the significance indicator is on. zeros in the source are replaced by the fill byte. the result is the equivalent of an addition to zero. The quotient occupies the leftmost bytes of the result. It will be placed in the leading bytes of the result in place of non-significant leading zeros. If the significance indicator is off.In these instructions the first operand is the target and the second is the source. 102 . If this is not the case.e.

The first is called the digit selector.6 Miscellaneous Decimal Related Instructions 18. The right-most 4 bits of each source byte (second operand) are moved to the right-most 4 bits of the target operand (first operand). In the case of the last digit.6. the fill byte replaces the digit selector. The Condition Code is unchanged.3 Move Zones (MVZ) This instruction uses only one length field. The pattern code X'21' is called the significance starter. When the last digit of a number is selected. the next digit in the source field is selected. the digit is converted to zoned decimal and replaces the digit selector. If a non-zero digit is selected.2 Move Numerics (MVN) This instruction uses only one length field. the sign is examined. each digit in the source becomes a byte in the result with a leading X'F' zone. the significance indicator is turned off. Further examples are given in Chapter 21. The left-most 4 bits of each source byte (second operand) are moved to the left-most 4 bits of the target operand (first operand).6. 18. it becomes the digit in the final result byte but the zone becomes the sign. Further examples are given in Chapter 21. it remains on or is turned on. It acts like the X'20' above except it always turns the significance indicator on if not already on.6. the significance indicator is turn on if not already on. Except for the digit. The (DB) will be replaced by the fill byte if the number is positive but remain in the result if the number is negative. If the digit is zero and the significance indicator is off.1 UNPACK (UNPK) The UNPK instruction converts its packed decimal second operand to zoned format. 103 . If the digit is non-zero or the significance indicator is on. not the current digit. If encountered in the format. the final characters in the format could be (DB) indicating a debit or negative balance.There are two main pattern bytes: X'20' and X'21'. 18. (Note: you often see this in bank statements where a negative value is indicated at the end of the number). The effect of this is to leave or replace trailing characters in the format. If the sign is negative. 18. If the sign is positive (CAFE). For example. The Condition Code is unchanged. Turning the significance indicator on affects the next digit.

104 .

That is. there are usually not enough spare registers so other techniques are employed. In the case of RX instructions. for large programs. At the beginning of an assembly language program we load the base register with the absolute address of a location near the beginning of the program and then tell the assembler which register we have selected to be the base register and where it is pointing. The address of a memory resident operand is calculated as a forward displacement from the location in memory contained in the base register. the base register (any register between R1 and R15 but usually R13 or lower) contains the absolute address of a location in memory in our program. or displacement and base (in all others). the assembler selects which to use. When a label is within this window of addressability we say that the label is within using of the base register. However. SI. When there is more than one base register available. The base register addressability problem is solved by having multiple base registers with the second pointing 4096 bytes beyond the first and so forth. blocks of code establish their own base register on entry so the same register or registers are re-used. the assembler will calculate the addresses of labels as displacements from the point in the program whose address is contained in the base register.1 Base Register Addressing As we have seen. no branch takes place because the second operand is R0. the assembler cannot address a label which is more than 4095 bytes from the address contained in the base registers. memory resident operands in RX. base register and displacement (in RX format). 105 . Loading a base register with the an absolute address can be accomplished by a BALR instruction in which the second operand is specified as R0. In this case. Programs. One problem with the base-displacement addressing scheme used in the IBM mainframe is that the maximum displacement from a base register is 4095 bytes. However the first operand receives the absolute address of the byte immediately following the BALR. the index register is seldom used and addressing of the memory operand is usually accomplished by only the base register and the displacement. SS and RS instructions are addressed by a combination of index register. In the case were the scope of two base registers overlaps (the 4096 byte window beginning with the byte pointed to be a base register). In these larger programs. however. the assembler selects the register that would yield the smaller displacement. When addressing a memory operand with base and displacement. are obviously longer than 4095 bytes in the real world. Displacements in the basic architecture are positive 12 bit numbers and thus can range from 0 to 4095 (more recent instructions may use longer displacements). From this point on.19 Multiple Base Registers 19.

Outside that area. In this case the programmer needs to be sure to load each register correctly.2048(R0.2048(R0.R12 The above loads the absolute address of the byte following the BALR into R12 then tells the assembler to use R12 as a base register. As there are only fifteen register that can be used as base registers. 1 2 3 4 5 6 BALR R12. 8192. This discontinues use of a base register. This could be accomplished with the following: BALR R12. The assembler assumes that these registers are set to 4096 and 8192 bytes apart.R12. as the asterisk refers to the current address. The use of USING and DROP are assemble-time directives .2048(R0. Note that the USING follows the BALR. the LA instruction is used to set 106 . they are said to be in using. it is not unusual to have more than one base register available for addressing.R10 LA R11. In this case the address expression is asterisk meaning here. for example.R11) LA R10. You will also note there is a DROP directive. respectively.they cover areas of code and are not run time states. The format of the assembler directive USING is an address expression followed by one of more register designations. we would first want to load it with the absolute address of where we are in the program then inform the assembler that R12 is a base register and tell the assembler where the contents of R12 are pointing. most large programs frequently re-use base registers rather than using many registers at once. 11 and 10 maybe used as base registers. The first register is assumed to contain the address of the address expression and subsequent registers. from the point or line in a program where a register is designated as a base register by USING until the point or line where it is dropped by a DROP. and so forth.R12) LA R11.So. if we want to establish R12 as a base register. the operand is said to be out of using. Then it tells the assembler that registers 12. Had it been the other way around.R10 Figure 42 Multiple Base Registers The code in Figure 42 first loads R12 with the absolute address of the byte immediately beyond the BALR. the register is not a base register.R11) LA R10. However. That is. the USING needs to be after the BALR. An example can be seen in Figure 42.R11.R0 USING *. the register may be selected by the assembler to construct a base/displacement address. hence. Then. if any. This is because the address in R12 is the address of the byte immediately following the BALR and. if an operand is beyond the maximum 4095 byte displacement of any base register. are assumed to contain the address expression plus 4096. When operands can be addressed with a valid base and displacement combination. the assembler would assume that the address in R12 was the address of the BALR.R0 USING *.2048(R0.

two LAs are required to add 4096. Note that since the maximum displacement is 4095.R11 and R10 from the value in R12. 107 .

108

20 System Macro Input/Output
Input/output operations on a mainframe traditionally have been record oriented. In most cases these involved fixed length records. Access to files is by means of input/output macros that are specific to the type of data being accessed. In the examples up to this point, the ASSIST pseudo-macros have been used as they simplify the process for novice users. In this section we introduce several basic QSAM (Queued Sequential Access Method) macros and show their usage. In order to perform either input or output it is first necessary to define a DCB (Data Control Block). The DCB is a table built partly by the user and partly by the system which defines the file being operated upon. The DCB has many options, only a few are shown here. A DCB is constructed with the DCB macro. Once a DCB has been constructed, a file is opened with the OPEN macro. The OPEN macro connects your program's DCB with the file being accessed. The OPEN and the DCB specify if the file is being opened for input, output or both. Once a file is open, you may access the file with several macros. Among these are GET and PUT. Others are also possible. When file processing is finished, you should issue a CLOSE macro to finalize any output, free buffers and disconnect from the file. In the example in Figure 43, 34 byte input records are read from one file and written to another. The input DCB is named INDCB and the output DCB is named OUTDCB. The DCB parameters used are as follows:
LRECL=34 RECFM=FT MACRF=GM MACRF=PM EODAD=ATEND DDNAME=IN DDNAME=OUT logical record length of 34 bytes fixed length records - ASCII/EBCDIC conversion the GET file access macro will be used the PUT file access macro will be used branch to label ATEND on end of input data DDNAME name to be opened and read DDNAME name to be opened and written

The LRECL determines the size of the input or output records. In the actual input file, the text records are actually 32 bytes long. The extra two bytes in the LRECL (and the associated input data area REC) allow for the carriage-return/line-feed (CR/LF) characters that are at the end of each line in a Microsoft text file. Note: Linux and Unix based systems have only one character at the end of a line, a linefeed (LF). The input records must each consist of 32 bytes of text. The RECFM parameter tells the system that the input and output files will consist of fixed length records. The MACRF parameter tells the system that the GET or PUT macros will be used for actual input and output. For input operations, the EODAD parameter tells the system the label to be branched to upon encountering the end of file. This parameter is not used for output DCBs.

109

Finally, the DDNAME is used to link the program's DCB to an actual file. In the z390 emulator running of a Windows based PC, this will be the name of an environment variable set by the user which will have the actual file name to be used. Before running the program, the user needs to create environment variables IN and OUT and set them to values that are valid file names. For example, to the Command Prompt, type:
set IN=IN.DAT set OUT=OUT.DAT

When the assembly language program runs, it will attempt to read from the file IN.DAT and write to the file OUT.DAT. You can see the complete list of environment variables by typing the command set by itself. You can delete an environment variable by entering a set command equating variable with nothing such as:
set IN=

The selection of the DDNAMEs IN and OUT was arbitrary. You may use any names that the system accepts. In the program in Figure 43, after the usual initialization, the DCBs are opened by the OPEN macro for OUTPUT and INPUT, respectively. They could have also been opened individually with code such as:
OPEN OUTDCB,OUTPUT OPEN INDCB,INPUT

The WTO macro writes to the console that the OPENs succeeded. Next the program enters a three line infinite loop consisting of the GET and PUT macros and the unconditional branch. The GET macro reads from the file associated with INDCB into the data area REC and the PUT macro writes from the data area to the output file associated with OUTDCB. When the GET encounters the end of file, the GET macro causes a branch to the label ATEND as determined by the EODAD=ATEND parameter in the INDCB. The CLOSE macro at ATEND flushes the buffers and disconnects from the output file. Failure to CLOSE an output file will usually result in the loss of about 2 lines of data. The file OUT.DAT will be an identical copy of the input file.

110

RECFM=FT.DDNAME=OUT LRECL=34.MACRF=GM. The last half byte contains the sign of the number.INDCB. 1 2 3 COPY 4 5 6 7 8 9 LOOP 10 11 12 * 13 * 14 * 15 ATEND 16 17 * 18 * 19 * 20 OUTDCB 21 22 INDCB 23 * 24 * 25 * 26 REC 27 PRINT NOGEN EQUREGS SUBENTRY OPEN (OUTDCB.EODAD=ATEND. in packed format would be: X'01234F' 111 . they must be converted to one of the numeric types. such as Packed Decimal or Integer (binary).(INPUT)) WTO '*** FILES OPEN ***' GET PUT B INDCB.REC LOOP read a record write the record loop EOJ processing CLOSE INDCB SUBEXIT File DCB's DCB DCB LRECL=34. In this section we show how to convert between printable character.DDNAME=IN INPUT RECORD DS END CL34 COPY Figure 43 QSAM Input/Output Arithmetic may not be performed on these character representations of numbers. Packed and Binary Arithmetic on an IBM mainframe can be carried out in binary integer.A. packed decimal and binary.REC OUTDCB. The hex codes C. they must be converted to one of the numeric types. Instead. the printable number 1234 in EBCDIC appears as: X'F1F2F3F4' Arithmetic may not be performed on these character representations of numbers. For example. packed decimal and floating point modes.21 Converting Between Zoned. A Packed Decimal is a string of bytes containing in each half byte a value (in bits) from 0 to 9 except for the last half byte. the above Zoned Decimal number. Instead.RECFM=FT. such as Packed Decimal or Integer (binary).MACRF=PM. When numbers are read from character (EBCDIC) input. and E mean the number is positive and the codes D and B mean its negative.F. Thus. they are in Zoned Decimal format.(OUTPUT). Floating point is not covered here.

all packed numbers appear to be positive (sign of F). To change the sign. The CVB is nontrivial.DAT is the name of the input file. 112 . you first must pack the number (PACK is very fast). On the other hand. packing them and adding them into a sum then prints the total and the average.DAT where INPUT1. however). it can handle more digits of accuracy and it does not need any further conversion. The CVB instruction converts a packed number to binary leaving the result in a register. Each operand may be up to 16 bytes in length. The PACK instruction removes the zones and packs the numerics except for the last byte of the zoned number where the zone and numeric are swapped. it can be seen that the zones have been eliminated and a sign appended. With both 32 and 64 bit binary numbers additional conversion is required from/to packed format. Packed decimal operations do not create round-off errors that are common with floating point numbers. We use the PACK instruction to convert a positive zoned decimal number to packed decimal. The PACK instruction packs into the first operand from the second. we must modify the numeric portion of the last byte. This is done with the Windows command: set IN=INPUT1.In this format. packed decimal is especially useful for business applications where many digits of accuracy are required. To read in a number in and convert it to binary. Packed decimal numbers can occupy up to 16 bytes and thus can represent numbers up to 31 digits in length. then perform a CVB (convert to binary). Since the zone of a text number is always F. While packed or decimal arithmetic is slower than binary arithmetic.2 billion (the range of values is much greater for 64 bit binary numbers. using a 32 bit binary value limits the results to about +/. The basic set of packed arithmetic instructions are: AP SP MP DP CP ZAP Add Packed Subtract Packed Multiply Packed Divide Packed Compare Packed Zero and Add Packed The example in Figure Error: Reference source not found illustrates some basic packed arithmetic operations. For many commercial transactions where a record is read and updated (by adding or subtracting) then quickly written back to disk. When using the z390 emulator for the program in Figure Error: Reference source not found you need first to establish the connection between the DDNAME=IN and the actual input file. Once a number is in packed format. you may do arithmetic on it. packed arithmetic is faster and more flexible. It reads in a table of positive numbers. Note: either upper or lower case in the above is acceptable.

2. This pattern will convert up to seven packed digits to characters with a padding byte of blank. The program in Figure Error: Reference source not found operates as follows (see also Chapter 18): 1.NBR LOOP * * * * * READ A RECORD WRITE THE VALUE TO CONSOLE PACK THE NUMBER ADD TO TOTAL READ ANOTHER RECORD * * * ATEND EOF . 3.DDNAME=IN Figure 44 Decimal Arithmetic (continued on next page) * DONE WITH INPUT * UNPACK AND FORMAT RESULT * * * INDCB 113 . The input file is opened on line 4 and connected with the DCB INDCB.REC(8) SUM.(INPUT)) GET WTO PACK AP B INDCB. The program in Figure Error: Reference source not found is fine as far as it goes but it only handles positive number.RECX) NBR.SUM WTO MF=(E. The program in Figure 45 operates as follows: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PRINT ADD LOOP NOGEN EQUREGS SUBENTRY OPEN (INDCB.REC MF=(E.BRANCH HERE WHEN OUT OF RECORDS CLOSE INDCB ED RSLT. The loop ends when there is no more input due to the EODAD=ATEND option in the DCB on line 22. Note: leading blanks are also permitted as a blank (X'40') and a zero (X'F0') both PACK to zeros. AT line 15 the input file (DCB) is closed. Line 6 through 10 are a loop in which lines of data are read (line 6). This triggers a branch from the GET on line 6 to the label ATEND when the GET encounters the end of file.EODAD=ATEND.RSLTX) SUBEXIT File DCB's DCB LRECL=10. 5. echoed back to the console (line 7).RECFM=FT. A sample execution can be seen in Figure 46 (note input echoed to the console). Initially RSLT has an edit pattern in it as can be seen in line 38. PACKed (line 8) and summed into SUM (line 9). 4. Line 17 writes the output. The program in Figure 45 solves this problem by taking minus signs into account. The branch instruction on line 10 causes the loop to iterate. On line 16 the edit (ED) instruction is used to convert the packed value in SUM to printable characters in RSLT. Zero suppression will not apply to the last digit.MACRF=GM.The input file for the program in Figure Error: Reference source not found is shown at the end.

After the number is PACKed. The input loop is basically the same as in Figure 44. 114 . 2. a plus or a minus. the program sets NEGFLAG as appropriate and replaces the sign by a blank (we do not want the sign present when we pack the number). 4.a minus sign in packed format. If it detects a minus sign. If a sign is detected.23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 * * * RECX REC RECEND NBR SUM RSLTX RSLT RSLTEND input record DC DC DS EQU DS DC DC DC DC EQU END AL2(RECEND-*-2. 9.0) * SUB 2 TO AVOID CR/LF C'INPUT=' CL10 * INPUT RECORD + 2 BYTES FOR CR/LF * PL8 PL4'0' AL2(RSLTEND-*. we add the result. The input number was positive. 5. The high order F16 in the mask byte will preserve the contents of the high order digit of the last byte. The number is PACKed (line 41).0) C'ANSWER=' X'4020202020202120' * EDIT PATTERN * ADD Sample input data: 00000010 00000020 00000030 00000040 Figure 44 Decimal Arithmetic (continued) 1. 8. it loads the address of the input record into R3 and sets a flag (NEGFLAG) to character zero. On line 10. If it finds a minus sign. 6. ANDing this with D16 results in it becoming D16 as well . At end of input the results are printed. 7. if NEGFLAG is 0. NEGFLAG is set to character 1. we And Immediate the last byte of the packed number with the mask byteX'FD' on line 44. Each input record is treated as an 8 byte number and is assumed to be correct (that is. 3. the program does minimal error checking). Now we add the negative number to the sum. The loop scans the input until it finds a leading digit. If NEGFLAG is 1. this flag will reset to character one. It continues scanning the input is it sees a blank. A loop beginning on line 12 and extending through line 40 examines each character in the input. The low order digit of the last digit of the packed number must be F16 because it is the zone of the last digit of the input.

REC MF=(E.C'1' ADD NBR+7.RSLTX) SUBEXIT Figure 45 Negative Decimal Arithmetic (continued on next page) 115 .C'1' 0(R3).C'-' MINUS 0(R3).NBR LOOP * SET FLAG TO 1 * MAKE MINUS A BLANK * MAKE PLUS A BLANK * 9 OR LESS? * MUST BE BAD DATA * * * * INCREMENT POINTER GET ADDRESS OF END COMPARE ADDRESSES LOOP IF NOT DONE PLUS NUM BLANK * IS THIS NUMBER NEGATIVE? * NO * YES .INPUT)) GET WTO LA MVI INDCB.R4 L1 NBR.REC NEGFLG.SUM WTO MF=(E.C'0' 0(R3).1(R0.C'0' NUM * READ A RECORD * WRITE RECORD TO CONSOLE * MAKE FLAG 0 * MINUS SIGN FOUND? * PLUS SIGN FOUND? * BLANK FOUND? * 0 OR GREATER NUMERIC FOUND? L1 CLI BE CLI BE CLI BE CLI BNL ERR MINUS WTO 'BAD DATA .C' ' BLANK 0(R3).C'+' PLUS 0(R3).MAKE SIGN X'D' * LOOP ADD * * * ATEND EOJ processing CLOSE INDCB WTO 'DONE*******' ED RSLT.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 ADD LOOP PRINT NOGEN EQUREGS SUBENTRY OPEN (INDCB.C' ' PCK 0(R3).EXITING' SUBEXIT MVI MVI B MVI B CLI BH LA LA CR BL PACK CLI BNE NI AP B NEGFLG.REC+8 R3.RECX) R3.REC(8) NEGFLG.R3) R4.X'FD' SUM.C'9' ERR R3.C' ' PCK 0(R3).

0_18 05/16/11 Figure 46 Example Execution 116 .03 ON J2SE 1.5.EODAD=ATEND.DDNAME=IN input record DC DC DS EQU DS DC DC DC DC DC EQU DC END AL2(RECEND-*-2.MACRF=GM.03 ON J2SE 0 SEC= 0 MEM(MB)= 15 z390 V1.03 ON J2SE 0 SEC= 0 MEM(MB)= 46 z390 V1.0_18 05/16/11 IO=70 1.56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 * * * INDCB * * * RECX REC RECEND NBR NEGFLG SUM RSLTX RSLT RSLTEND MSG File DCB's DCB LRECL=10. and go from mlc to 390 execution C:\DOCUME~1\user\ASMLAN~1>echo 12:42:32 addloop1 MZ390 START 12:42:32 addloop1 MZ390 ENDED 12:42:32 addloop1 LZ390 START 12:42:32 addloop1 LZ390 ENDED 12:42:32 addloop1 EZ390 START INPUT=00000001 INPUT=-0000002 INPUT=00000003 DONE******* ANSWER= 2 off USING RC= USING RC= USING z390 V1.mlc C:\DOCUME~1\user\ASMLAN~1>rem asmlg assemble.0) * SUBTRACT 2 TO AVOID CR/LF C'INPUT=' CL10 * INPUT RECORD + 2 BYTES FOR CR/LF * PL8 C'0' PL4'0' AL2(RSLTEND-*.5.6.6.5. link.RECFM=FT.6.0_18 05/16/11 IO=2414 1.0) C'ANSWER=' X'4020202020202120' * EDIT PATTERN * C'DONE***************' BEGIN Figure 45 Negative Decimal Arithmetic (continued) C:\DOCUME~1\user\ASMLAN~1>asmlg addloop1.

22 Programming Examples 22. and an event control block (ECB) (A full word binary initially set to zero). Alternatively. The simplest form is: WTO 'STRING TO BE WRITTEN' The above will write the contents within the quote marks (up to 119 characters) to the console window.0) MSG1 DS CL20 MSGEND EQU * The first line. MSG. In Figure 43 on page 111 we saw an example of QSAM based file input/output using the GET and PUT macros. You may read and write directly to the console using the WTO and WTOR macros. This value is used in the line with label MSG. The WTO macro can be used to write a constant string to the console (your command prompt window) or it can be used to write a string stored in memory. The label MSGEND has as its value the location counter value of this point in your program.MSG) where MSG refers to a data area such as the following: MSG DC AL2(MSGEND-*. you may read and write files using the GET and PUT macros or the ASSIST XPRNT and XREAD macros. consists of 2 half words. The first will contain the length of the string to be written (including the half words). in this case a string of length 20 whose contents are filled-in somewhere else in the program. If the length is omitted. This is then followed by the data area which will contain the string to be written. it will be determined from the implied length of label.1 Console Input/Output In Figure 22 on page 65 we saw an example of reading and writing files using the XREAD and XPRNT macros. The WTOR macro is similar. Here we demonstrate the WTO and WTOR macros which are normally available in the IBM assembler. 117 . The value of the first half word it the difference between the location counter at MSG (*) and the value of the location counter after the string and half words. The second half word contains a zero. you can write a string stored in memory to the console with: WTO MF=(E. Alternatively. Here we examine console based input output using the WTO and WTOR macros. an optional length or the input field. its parameters are a message to be written. an area in memory to receive a reply. This pauses the program until the reply has been entered. The macro is followed by a line with the WAIT macro with the ECB from the WTOR.

EV WAIT ECB=EV WTO MF=(E. the low order 15 bits of the original number. The reply is then printed using the extended form of the WTO. then the modulo operation can be performed as a shift rather than as a real division operation.The example in Figure 47 gives an example where a message is written by the simple form of the WTO macro. a and b are constants and N is usually a power of 2.20. The values of a and b determine the overall performance of the program. Each iteration of the formula produces a new random number until the sequence repeats.MSG) SUBEXIT MSG DC AL2(STREND-*. in a 32 bit word. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PRINT NOGEN EQUREGS WTO SUBENTRY WTO 'CONSOLE READ/WRITE' WTOR 'ENTER A STRING'. another message is written by the WTOR macro and the program which waits for a reply.C'YOU TYPED ' STRING DS CL20 STREND EQU * EV DC F'0' END WTO Figure 47 Console I/O using WTO/WTOR 22. that is. we would And the word with the mask: X'00007FFF' whose lower 15 bits are: B'0111111111111111' Figure 48 contains a short C program to generate 1000 random numbers with this technique. The remainder. If N is a power of 2. we can obtain modulo 32768 on a binary number by zeroing out all bits but the lower 15. will be the bits shifted out of the register. For example. Thus.STRING. Next.2 Random Numbers Many random number generators operate on a formula of the form: x = ( a * x + b) % N where x is initially the seed. were taken from: 118 . Thus can be accomplished by and And instruction. if N is 32768 or 215 a divide by 32768 can be accomplished by a right shift of 15 bits. respectively. For example. however.0). The result will be the quotient. The values for a and b are 214013 and 2531011.

http://rosettacode. BRANCH IF > 0 END RAND Figure 49 Random Number Generator 119 . } } Figure 48 Random Numbers in C The assembly language equivalent of the program in Figure 48 can be see in Figure 49. N. printf("%d\n".OUT XPRNT OUT. x. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PRINT NOGEN EQUREGS SUBENTRY WTO 'RANDOM NUMBERS' LA R2.org/wiki/Random_number_generator_(included) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 #include <stdio.h> int main() { unsigned int i. i<1000. The Multiply instruction. b=2531011. a=214013. on the other hand.X M R4. a.8(0. has a 64 bit result only the lower 32 bits of which we use and thus the matter of overflow is not an issue.12 BCT R2. i++) { x = ( a * x + b ) % N.MASK ST R5. Also note the Add Logical instruction on line 13. x=79. b.x).A AL R5.X XDECO R5. N=32768. This causes the number to be treated as an unsigned quantity for purposes of addition.LOOP SUBEXIT A B X MASK OUT DC DC DC DC DS F'214013' F'2531011' F'79' X'00007FFF' CL12 * LOAD R2 WITH 8 * LOAD SEED OR LAST VALUE * MULT BY A * * * * ADD (LOGICAL) B MODULO 32768 STORE RESULT PRINT RESULT RAND * DECR R2. Note that the Multiply instruction on line 11 addresses the even register of the even/odd pair.B N R5.0) LOOP L R5. // seed for (i=1.

and R4 will point to the next available byte in the stack. When items are removed from the 2. there are no embedded blanks in the input string and that the input string has a dollar sign at the end as a terminator character. In a stack. The address in R4 will always point at the next available position. When done. 6. the remaining items pop-up. not 20. R3 will point to the next available byte in the output string. Examine the next character in the input. 3. the operands appear after the operands. The stack will start empty (R4 points to the start of STACK) and grow to higher addresses in STACK when items are added. the existing items are pushed down. On line 3 we print in the infix expression to be converted. If it is a dollar sign. 5. If it is a close parenthesis. Fore example: ((A+B)*(C-D))$ yields AB+CD-* The program works as follows: 1. In infix notation. The MVC on line 5 moves is offset by one from its source to its target and the length is 19. copy it to the output string. push it on the stack. the output should contain the translation to suffix and the stack should be empty. first out data structure. When we remove an item.3 Convert Infix to Suffix In the example in Figure 50 we use a simplified algorithm to convert fully parenthesized infix notation the suffix notation. In lines 4 and 5 we copy blanks into the output field OUT. 120 . The easy way to do this is to place a blank in the first position (line 4) and then propagate it across the remaining 19 positions (line 5). In suffix notation. the operators appear between the operands. If it is a open parenthesis. The algorithm uses a stack. 4. 3. if it is an operand. If it is an operator. We load our main registers in lines 6 through 8. Check results. The (simplified) infix-to-suffix procedure is as follows: 1.22. done. Thus. pop the top element on the stack to the output string. when we place a new item on the stack. The figure L'IN in the XPRNT tells the assembler to calculate the implied length of the data declared at label IN and place the number here. ignore it and go to step 1. Stacks are very useful in many algorithms and the are an example of a last in. 2. R2 will point to the current byte in the input string. In our example we assume that all operands are a single character. byte 0 (the blank) is copied to byte 1 then byte 1 is copied to byte 2 and so forth.

Note that we needed to decrement the stack pointer first because it always points to the next available position. on line 29. If not. At OPR we move the operator character onto the stack. If it is not. the address in R4 will be decremented. we branch to label L3. The MVC on line 31 copies the operator byte from the input string to the stack. the displacements are zero because the registers contain the entire address. 5. On lines 32 through 34 we increment the input and stack pointers then branch to the top of the loop for the next input character. we increment R2 (line 15) and branch back to the top of the loop (effectively. 8. the base position is taken by R2. It means zero displacement past the address in R2. 7. the current position in the stack is no longer in use so the stack pointer (R4) is correct. Finally. 9. we branch to the label OPR. Lines 21 through 28 test if the input character is one of the operators. we test if the byte of input pointed to be R2 is a open parenthesis. Remember. On line 36 we test if the input is a close parenthesis. The 1 in the first operand is the length. Line 15 tests for the terminating dollar sign and branches out of the loop to print the results. we branch to label L1. The main input character processing loop begins at line 13. If it is. Then we increment both the input and output pointers. At line 49 we write out the output string and exit. beginning at line 44. 6. It needs to be decremented to point to the last used position. R2 has the address of the operand. In this example. R2 points to the operator and R4 points to the next available position in the stack. Note the first operand on the CLI instruction on line 13. we ignore the open parenthesis). In an SI instruction the first operand is addressed by a combination of displacement and base: D1(B1). Again. If it is not. we decrement the stack pointer and copy the byte from the stack to the next available byte in the output string (pointed to by R3). 4. 10. After the byte from the stack has been copied to the output. we branch around the operator handling section to label L2. This line and several following it examine each character of input in order to determine how to handle same. If it is. We must provide the length as the assembler can not calculate an implied length (it needs a label to do this).stack. On line 13 itself. 121 . the only alternative is that the character is an operand which we copy to the output string. increment the input and output pointers and branch to the top of the loop. That is. If it is.

C'*' BE OPR CLI 0(R2).C' ' * PUT BLANK IN 1ST POSITION MVC OUT+1(19).C')' BNE L3 S R4.0(R2) A R3.C'+' BE OPR CLI 0(R2).L'OUT SUBEXIT DC C'((A+B)*(C/D))$' DS CL20 DS CL20 END Figure 50 Convert Infix to Suffix * IS INPUT CHAR ( ? * NO * INCREMENT INPUT POINTER * PROCESS NEXT CHARACTER * IS INPUT CHAR $ ? * YES . The program consists of two loops: an outer loop beginning at OUTER and and inner loop beginning at LOOP. * OR / ? * YES L1 * PUSH OPERATOR ONTO STACK * INCRMENT INPUT POINTER * PROCESS NEXT CHARACTER L2 L3 FIN IN OUT STACK 22.OUT * ADDRESS OF OUTPUT STRING LA R4.C'/' BE OPR B L2 OPR MVC 0(1.=F'1' B LOOP MVC 0(1.=F'1' MVC 0(1.STACK * ADDRESS OF STACK * * LOOP TO EXAMINE AND PROCESS INPUT * LOOP CLI 0(R2).R3).=F'1' B LOOP CLI 0(R2).R2) B LOOP CLI 0(R2).OUT * PROPOGATE BLANK ACROSS FIELD LA R2.=F'1' A R2.1(R0.4 Bubble Sort a Table of Numbers The program in Figure 51 performs a bubble sort on the ten full word binary numbers in the table beginning at label TAB. -.END OF INPUT * IS INPUT +.=F'1' B LOOP XPRNT OUT.0(R2) A R4.R3).C'$' BE FIN CLI 0(R2).=F'1' A R2.0(R4) A R3.C'-' BE OPR CLI 0(R2).C'(' BNE L1 LA R2. 122 .=F'1' A R2.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SUFFIX SUBENTRY EQUREGS XPRNT IN.L'IN MVI OUT.IN * ADDRESS OF INPUT STRING LA R3.R4).

the fort is finished and the results are printed. If we do not swap we advance to line 14 and increment R2 by one using the LA trick. we branch to the section of code where we swap the contents (SWAP). the value we load is at TAB+R4. element 1 is compared with element 2 and so forth until element 9 is compared with element 10. That is. R2 is the counter from 0 to 9 and R8 is the swap flag. it means that all nine iterations of the inner loop resulted in no swap. On line 11 we compare the contents of R3 with the value in the table at offset R5... Note that the format of the statement in line 9 causes R4 to be used as the index register. In the program.. A shift left by 2 is the equivalent of multiplying by 4 and thus the value becomes our offset. If not. . their contents are swapped with one another. Now R5 is the offset into the table of the element just above the element whose value is in R3. This. If the value in R2 is less than 9 we continue and execute another loop cycle (note: the value in R2 will range between 0 and 8 which is nine values . 2. If the contents of R3 are greater than the value of this element. If the flag indicates that a pair of elements were swapped. 4. 123 . a flag is set to indicate that a swap has taken place. If the contents of R8 are not zero. This is a common trick for incrementing positive numbers by small amounts and is faster that an RX Add instruction. we have completed a full 9 iterations of the inner loop. . element 0 is compared with element 1. When a pair of elements are swapped. Inside the loop we convert the counter in R2 to an offset in R4. Next we load into R5 the value of R4 incremented by 4 (Line 10). If the value in R8 is zero. If the flag indicates that no swap took place. The table is now sorted so we branch to the location where we print the results. If the value of an element is greater than the value of the element above it. To convert the count into an offset we load the count into R4 and then shift the value left by two bits (lines 7 and 8). we branch to the top of the outer loop and reset R2 and R8. 8. At the beginning of the outer loop these are both set to zero (lines 4 and 5). Next we check the contents of R8. We compare the contents of R2 with 9. That is. We load the value from the table into R3 on line 9. We use the LA instruction which sums the value of R4 and the displacement (4) and places the result in R5.The inner loop examines each element of the table from element 0 to element 9 and compares it with the element in the position above it.we want our first offset to be zero). while the counter may be 0. we need the actual offset into the table in order to address the elements. 1. the process is repeated. 12. These are of the form 0. After all elements have been examined the flag is examined...

We increment R1 by 1. we load the values of the two elements that need to be swapped into R6 and R7 and then store the upper element's value (R7) into the lower element slot (R4 offset) then store the lower element's value in the upper element's slot (R5 offset).R4) C R3.R2 SLA R4.R2 * LOOP AND PRINT RESULTS LR R4.2 L R3.R2) Figure 51 Bubble Sort (continued on next page) DONE PLOOP 124 . We place a 1 in R8 indicating a swap has taken place then branch to label INC to increment the counter and test as described above.TAB(R4) * LOWER L R7. R4 becomes the offset as before by shifting it left by two.TAB(R4) * HIGHER TO LOWER ST R6. AT DONE we do a very similar loop based on offsets and print the results. We load the value from the table into R3 then convert it to printable characters and print it (lines 31 through 33).R8 SR R2.R2 SLA R4.1(0.=F'0' BE DONE B OUTER * FLAG * COUNTER * * * * MULT by 4 GET VALUE OFFSET OF NEXT VALUE COMP VALUES INC * INCR COUNTER * INNER LOOP DONE? * CHECK FLAG * DONE? * DO INNER LOOP AGIAN SWAP L R6. R2 is a counter but this time it will range between 0 and 9 rather than 0 to 8.TAB(R4) XDECO R3.R2) C R2. compare it with 10 and iterate if the value is less than 10.R2 LR R4.1(R0.2 L R3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 BUBBLE SUBENTRY EQUREGS OUTER LOOP SR R8.0) * SET FLAG B INC SR R2.TAB(R5) BH SWAP LA R2.TAB(R5) * LOWER TO HIGHER LA R8.TAB(R4) LA R5.TAB(R5) * HIGHER ST R7.4(R0.OUT XPRNT OUT. As before.In the swap section (lines 21 through 26).1(0.=F'9' BL LOOP C R8.L'OUT LA R2.

The outer loop begins on line 6 where the counter is incremented by one (thus. We have tried all the alternatives. if equal.35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 * * TABLE OF NUMBERS TO SORT * TAB DC F'9' DC F'7' DC F'3' DC F'10' DC F'4' DC F'1' DC F'2' DC F'11' DC F'5' DC F'0' OUT DS CL12 END Figure 51 Bubble Sort (continued) C R2. On Line 13 we initialize the inner loop counter to 1. If the value in R2 is greater than or equal to the value in R4. If we find a case where some counter value from the inner loop divides evenly (remainder of zero). we make it through the entire inner loop finding no value that divides evenly into our candidate value. we branch to label PRIME and print the number. we exit. this divides the value in R4 by 2 and this gives us the upper limit for the inner loop counter. The program operates as on outer loop whose counter is the number to be tested and an inner loop whose counter iterates between 2 and one-half the outer loop counter. On lines 10 and 11 we set up the limit for the inner loop. our inner loop counter. 125 . we test the values between 4 and 999. the value must be prime so we print it and continue to the next. we begin with the counter having a value of 4). At line 16 we compare the value in R2. We compare the counter with 1000 and. The loop will iterate testing all the values between 2 and one-half the value being tested to see if they divide evenly. Consequently. not 1).=F'10' BL PLOOP SUBEXIT 22. In effect. If on the other hand. we begin our testing with 2. First we increment the counter (hence. The program is a loop that tests each number between 4 and 999 to see if it is divisible by any number between 2 and one-half the number being tested. The outer loop counter is R3 and it is initialized to the value 3 on line 4. We load the counter (R3) into R4 then shift the value in R4 right by one.5 Search for Prime Numbers The program in Figure 52 searches for prime numbers in the range of 4 through 999. The inner loop begins on line 12 and extends to line 24. we exit the inner loop and try the next outer loop value. with the limit value in R4.

=F'3' A R3.6 Print a String in Hexadecimal The program in Figure 54 prints a string of characters in their equivalent hexadecimal notation. For example.R3 SRDA R6. Note: when doing a right arithmetic shift.R3 SRA R4. we load the candidate outer loop counter into R6 and double shift it 32 bits to the right into R7.=F'0' BE LOOP B INNER * CANDIDATE NUMBER TO TEST * DONE? * CALCULATE INNER LOOP LIMIT * DIVIDE BY 2 * INNER LOOP COUNTER * INNER LOOP LIMIT TEST * PREPARE EVEN/ODD REGISTER PAIR * CHECK THE REMAINDER * NOT PRIME XDECO R3. This places the candidate into R7 and (since we are only using positive numbers) zeros out R6. Next we divide the candidate by the inner loop counter on line 21. 1 PRIME 2 3 4 5 6 LOOP 7 8 9 10 11 12 13 14 15 INNER 16 17 18 19 20 21 22 23 24 25 26 PRIME 27 28 29 30 DONE 31 32 OUT 33 OUT1 34 35 SUBENTRY EQUREGS L R3.1 L R2. the sign bit is always zero.=F'1000' BE DONE LR R4. The quotient will be in R7 and the remainder in R6. we print it at line 26 then branch back to the outer loop for the next candidate to test.OUT XPRNT OUT.Otherwise. If the remainder is not zero.R2 C R6. we test the next inner loop counter value.32 DR R6.R4 BNL PRIME LR R6. if the string is ABC123. If the remainder is zero (line 22). If a number is prime. bits like the sign bit are supplied at the high end.=F'1' CR R2. the number is not prime and we branch back to the outer loop. the equivalent hexadecimal is: 126 .=F'1' C R3.L'OUT+L'OUT1 B LOOP SUBEXIT DS CL12 DC C' IS PRIME' END Figure 52 Search for Prime Numbers 22. Since our numbers are all positive.=F'1' A R2.

This value is declared as an A-type address constant whose value is the location counter value of the label STRX. We need to extract the high order four bits. R5 will be a register into which we load the input characters and R6 will be an offset into the output string. if the four bit field has 1010 (10 in base 10). STRX gets it's location counter value from the EQU directive which calculates the difference between the current location counter and the location counter at the beginning of STRING. STRX could not be loaded directly because it does not exist at run time . As the loop progresses. The assembler will construct the base and displacement for STRING and also place R4. Hence. While STRX is not really an address. index. We now have an input character in the low order 8 bits of R5. our offset into the string. Each time the BCT is executed. R4 will be an offset into the input string. however. 4. The loop control is the BCT instruction on line 25. and 10). When R2 is still greater than zero. This removes the low order 4 bits and causes what were the high order four bits of the low byte to now be in the 127 2. it will index to the eleventh position in the table where there will be a character A. into the index register position. do a lookup and copy a result to the output then do the same for the low order four bits. and base format. For each byte. 5. The address of the byte to be loaded is computer with the displacement. no branch is made and the loop ends. The program proceeds as follows: 1. it decrements the value in R2 (the string length) by one. 3. STRLEN.this instruction only modifies the low order 8 bits so the high bits remain zero).it is only and equate symbol. When R2 is zero. branch is made to LOOP. it will first extract the high order four bits and use these as a number (between 0 and 15) to index into a table of equivalent printable characters which correspond to the value of the four bit field. Note: the table begins at zero. For example. Registers R4 through R6 are set to zero (lines 8. On line 12 we use the Insert Character instruction to load a byte from the string into the low order 8 bits of R5 (we zeroed all the bits of R5 . offset 10 into the table is to the eleventh element. does exist at run time and will be initialized with the value of STRX. .C1C2C3F1F2F3 The program will advance through the input string byte by byte. The length of the input string is loaded into R2 (line 7). The length is derived from the value stored at label STRLEN on line 33. Beginning on line 12 we loop through the input until done. The SRA on line 13 shifts the contents of R5 to the right by four. the value in R4 will increment by one for each passage through the loop (line 23). Atype address constants are often used for this purpose since they permit initialization of their run time content by computer values as is the case here.9.

In the program in Figure 54. This is done on line 19. Line 25 determines if we should process any more characters as noted above. Lines 20 through 22 do the lookup and store the result. the data structure for each word will be eight characters of text followed by four bytes of of binary giving the number of time the word has occurred in the input text. Information storage and retrieval systems often index documents based only on a maximum number of characters in a word. the word data structure is contained in a table whose declaration is on line 120. we only need to eliminate the high four bits. we will load A into the low byte of R5 and likewise for any value in R5 between 0 and 15. Word counts are useful to identify common and infrequent words which may make poor indexing terms. The previous contents of R5 are lost in this operation. To process the low bits. only the low order four bits will remain. 7. The stem of a word is mainly in the first part of the word. In this example. When this mask is and'ed with another 32 bit value. 9. As we have now processed all 8 bits of the input character. It stores up to 1000 words of length up to 8 characters and maintains a count of the number of times each occurs.the size of the computer word on early mainframes. if the value in R5 is 10 (decimal). On line 15 we store the low order byte from R5 into the output string and increment the offset into the output string on line 16. line 23 increments the offset into the input. Lines 18 through 22 process the low order four bits from the original character. R5 will consist of 28 bits of zeros (high order bits) followed by the four bits that were in the high end of the input character.low order position. Note that the table begins on a full word boundary. We do this by and And instruction with a mask. This is insured by the declaration on line 116. On line 14 we use the Insert Character instruction indexed by the value in R5 to load a character from TABLE.7 Word Count Program The following program builds a dictionary of words. The notation 0F in a DS statement causes the assembler to allocate zero instances of a full word binary but it has the effect of forcing the assembler to advance to the next full word boundary (an address value evenly 128 . Note that the length of the output is twice the length of the input (there are two character of hexadecimal for each input character). 6. It is a 12000 byte table thus allowing for 1000 12 byte entries. R5 is now a number between 0 and 15 and the offset into our lookup table. The mask is a 32 bit value in memory with binary zeros in all but the last four bits. Line 27 writes to output. These are ones. The Salton SMART System was originally based on six character words . TABLE is a string containing the characters 0 through A used to represent hexadecimal numbers. Thus. 8. 22.

The structure of the table at TAB is not visible in the declaration.OUT(R6) LA R6.OUT(R6) LA R6. Rather. Thus. Note that the table TAB is declared last.divisible by 4).STRING(R4) N R5.STRLEN SR R4. the largest displacement allowed.R6) LA R4.R4 SR R5.STRX*2 SUBEXIT STRING STRX STRLEN OUT MASK TABLE * * * * * * * * * * * * * * * LENGTH OF STRING OFFSET INTO INPUT STRING REGISTER TO RCV STRING CHARS OFFSET INTO OUTPUT STRING LOAD NEXT INPUT CHAR MAKE 4 HIGH BITS the 4 LOW BITS LOAD CHAR FROM HEX TABLE STORE CHAR in OUTPUT STRING INCREMENT OUTPUT OFFSET LOAD INPUT CHAR AGAIN ZERO HIGH 4 bits LOAD FROM HEX TABLE STORE TO OUTPUT INCREMENT OUTPUT OFFSET INCREMENT INPUT OFFSET HEX * DECR R2.R5 SR R6.R6 LOOP IC R5.STRING(R4) SRA R5. What is the problem with TAB? Since the extent of TAB is much larger than 4095.R4) BCT R2.LOOP XPRNT OUT. Note that the LTORG appears before the TAB definition. the next declaration. The LTORG causes any literals. Thus. We could have more than one base register but it 129 . anything placed after TAB would be out of using for our single base register. any literals will appear prior to our definition of TAB.R6) IC R5. elements looking like =F'100'. BRANCH IF > 0 * PRINT RESULTS DC C'THIS IS A TEST STRING 0123456789' EQU *-STRING DC A(STRX) DS CL(STRX*2) DC X'0000000F' DC C'0123456789ABCDEF' END HEX Figure 53 Print Hex Equivalent This is important because each full word binary word count in the table must itself be on a full word boundary in order to be accessible by the Load and Store (and other) instructions.1(R0.MASK IC R5. the table TAB begins on a full word boundary.4 IC R5.1(R0.TABLE(R5) STC R5.TABLE(R5) STC R5. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PRINT NOGEN EQUREGS SUBENTRY WTO 'HEXADECIMAL' L R2. the structure is imposed on it by the code which maps this area of memory to be a table of 1000 elements. to be placed in memory beginning at the point where the LTORG appears.1(R0.

Next. it will return (and substitute) a capital A. 2. The TR table: We declare an area of memory 256 bytes long (as normally the case with a TR table) and we initialize each byte to blank .is unnecessary. after the TR instruction on line 9. 3. The ORG directive resets the assembler's location counter back into the address space of the table. Next. If we have reached the end of the input. The net effect: input containing upper or lower case letters will be converted to upper case letters. If it is not. The TR uses the table declared on lines 91 through 112. Retention of hyphens and single quote marks was based on the input used (Dryden's translation of the Aeneid) to test this application in which these characters were important. the DC statement replace the blanks. hyphens and single quote marks. Once repositioned. not counting the CR/LF. upper case alphabetics. The input consists of lines of text up to 80 characters long.the default (line 91). The TR converts all alphabetics to upper case (a common case for indexing terms is normally used in retrieval applications). we branch to label L2. In these lines. the input image consists only of blanks. Next we modify the TR table offsets for the hyphen and single quote which will likewise be retained in the resulting input image. If it is. in this case. On Line 11 we load the address of the input image into R3 and the address of the end of the input image into R4. is the address just beyond the TR table. at the offset into the table associated with the letter a we replace the blank with a capital A. 4. Input is processed in a loop of code beginning at line 7 and extending through line 62. when the TR looks up a lower case a. Each input line is processed by a Translate (TR) instruction to remove punctuation (except the hyphen character) and numerics. 130 . On line 14 we test if the byte being pointed to by the contents of R3 is a blank. The program works as follows: 1. every character looked up will return a blank. Thus. At this point. The first set of changes are lines 92 through 105. We do this for all the alphas. Thus. we branch to 5. We only need that the first byte of TAB be within using as we can address it directly from that point as will be seen. That is. we fall through to line 17 where we increment the pointer in R3. compare it with the limit value in R4. we backup into the table by means of the ORG directive and change some of the blanks. we replace the blanks in the table at the offsets associated with the upper and lower case character with the upper case equivalent. The final ORG with no operand causes the location counter to spring back to the highest value it has had so far which. Input is read into the field IN on line 7 and a branch is made to EOF when there is no more data (line 8). we scan each input image and extract each word.

. we advance to line 30. When the contents of R5 become zero. we branch to L1 to process the next character. this effectively substitutes the low byte of R6 into the length portion of the MVC instruction and exactly R6 bytes are moved to OUT. the length of OUT).LOOP and read a new line of input. Thus. 10. The EX uses the data area MVC at the label MVC. we branch to label L4. testing it against the limit. Initially. we truncate long words. Each table word is followed by a four byte binary integer giving the number of times the work as appeared. The words in the table are no longer than 8 bytes. On line 36 we load the count of the number existing entries in the table into R5. Each time we examine an entry. we decrement the count in R5. we ignore blanks in the input. Even though most of TAB is beyond the reach of using (base register + 4095). The remaining bytes of OUT remain blanks. The loop to search the table to see if our word in OUT is already in the table extends from lines 38 through 46. 6. Once we have its absolute memory address in a register. R5 has the address of the starting point of the word and R3 has the address of the byte just beyond the end of the word. Lines 24 through 28 locate the end of the word by incrementing the input pointer (R3). we have examined all entries and we branch to L6 where we add our word from OUT as a new entry. We then (line 27) test if the character pointed to by the contents of R3 are a blank. COUNT is 0. Thus. If we reach the end of the input image. The CLC (Compare Logical Character) on line 41 131 8. we can load its address. Lines 41 and 42 compare the first 8 bytes of the word in OUT with the word in the table. If not. On line 37 we load the address of the table of words TAB into R6. we loop and look at the next character When we get to line 30. Reaching line 22 we know we are at the start of a word whose address we copy into R5 to preserve the origin of the word. In line 34 we use the EX (Execute) command to move R6 bytes from the input beginning at the address contained in R5 to OUT. we can address its contents without need for displacements as will be seen. Now we need to do a lookup on the table to see if we have this word. If yes. We copy R3 to R6 and subtract R5 from R6 leaving in R6 the length of the word that begins on at the address contained in R5. 9. Lines 32 and 33 ripple move a blank across the field OUT (this program assumes no word will be longer that 30 characters. Since the second byte of the MVC at label MVC is a zero. Lines 38 and 39 test if we have examined the entire table. If we do not find the word in the table. we add it with a count of one. 11. This is the image of the MVC that the EX will execute after ORing the low byte of R6 (contains the length) with the second byte of the MVC at MVC. Thus. If not. 7. the start of the table is within using.

C' ' BNE L2 LA R3.1(R0. we increment the contents of R6 by 12 (line 44). the 4 byte binary count entry. we arrive at label L6. Then we branch to the top to process the next word (label L1A). we branch to L7 to increment the count for this word.EOF TR IN. if any. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 WORDS LOOP XREAD IN. test it against the table limit. load a 1 into R7 (line 54) and store the 4 byte binary 1 in the last 4 bytes of the 12 byte entry (line 55). If they do not. The first operand begins at label OUT and the second operand begins at the address contained in R6. If we find the word. that is. 14.R3) * CVT UPPER CASE & REMOVE NON-ALPHAS * ADDRESS OF END OF INPUT * BLANK? * BRANCH IF NOT BLANK TO PROCESS WORD * * * * INCR PTR INTO INPUT AT END? YES . lines 48 through 51 increment its count. If we looked at every entry in the table and did not find the word.specifies an 8 byte length.PROCESS NEXT CHARACTER L1 L1A CLI 0(R3). Note there is no displacement.80(R0. R6 has the address.R4 BNL LOOP B L1 Figure 54 Dictionary Program (continued on next page) 132 . We load the original value of COUNT.IN LA R4. If the words match. To this we add 1 and then store the result back in the table. 12. We load into R5 the 4 bytes offset 8 bytes from the word in the table. We simply copy the first 8 bytes from OUT to the 1st 8 bytes of the new entry we are creating (line 53). and store it (lines 56 through 60). The we return to the top to process the next word.80 BC B'0100'. Lines 64 through 77 print the table of words and counts using a similar loop to that used to search the table above.R3) CR R3. increment it. PRINT NOGEN EQUREGS SUBENTRY WTO 'WORDS' 13.TRTAB LA R3.END OF INPUT STRING NO . At label L6 we know that R6 will be pointing at the 1st byte of the next available 12 byte slot in the table. decrement the count in R5 and branch to look at the next entry.

R5 MVC OUT(1).R6) A R5.8(R0.TAB C R5.=F'1' B L5 * COPY WORD START ADDR TO R5 * * * * * * * * * * * * * * INCR INPUT POINTER END? YES BLANK? NO .R6).12(R0.R6) S R5.12(R0.22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 L2 L3 LR R5.=F'0' BE L6 CLC OUT(8).=F'1' ST R5.1(R0.R6) L R5.CONTINUE COPY WORD END ADDR TO R6 LENGTH OF WORD IN R6 COPY BLANK TO POSITION 1 PROPOGATE BLANK COPY WORD TO OUT NUMBER OF ENTRIES IN TABLE START OF ARRAY OF ENTRIES NO MORE ENTRIES IN TABLE TO LOOK AT? YES L4 L5 * COMPARE NEW WORD WITH TABLE ENTRY * FOUND WORD IN TABLE * INCREMENT PTR TO NEXT ENTRY * DECREMENT LOOP COUNTER * CONTINUE * * * * * * * * * * * * WORD FOUND .=F'1000' BNL ERROR ST R5.OUT LA R7.LOAD COUNT INCR COUNT STORE COUNT LOOK FOR NEXT WORD IN INPUT COPY WORD TO TABLE LOAD 1 INTO R7 STORE IN COUNT FIELD MAIN COUNT OF ENTRIES INCR TEST LIMIT OVER LIMIT STORE UPDATED COUNT L7 L R5.R3 SR R6.=F'0' BE BYE MVC OUT(8).1(R0.C' ' BNE L3 LR R6.R5) BCT R6.8(R0.COUNT B L1A L6 * PROCESS NEXT INPUT WORD * * * * * * * * * * TABLE ADDRESS COUNT OF ENTRIES EMPTY? DONE COPY WORD TO OUTPUT STRING LOAD WORD COUNT CVT WORD COUNT TO CHARS WRITE WORD AND COUNT INCR TO NEXT ENTRY DECR R6 AND REPEAT IF > 0 EOF L8 LA R5.R0) ST R7.R6) B L1A MVC 0(8.COUNT C R6.8(R0.R5) C R5.COUNT LA R6.R4 BNL L4 CLI 0(R3).OUT+8 XPRNT OUT.20 LA R5.BLANK MVC OUT+1(29).R3 LA R3.0(R6) BE L7 LA R6.MVC L R5.1(R0.OUT EX R6.L8 Figure 54 Dictionary Program (continued) (continued on next page) 133 .0(R5) L R7.R3) CR R3.8(R0.COUNT LA R5.R5) XDECO R7.TAB L R6.

120 * 121 TAB DS 12000C 122 123 END HEX Figure 54 Dictionary Program (continued) 134 .12 * PRINT TOTAL 78 SUBEXIT 79 80 ERROR WTO 'ERROR .0(R5) * FOR EX INSTRUCTION 86 IN DS CL80 * INPUT STRING 87 COUNT DC F'0' * NBR ENTRIES COUNT 88 * 89 * TRT TABLE TO CONVERT TO UPPER CASE AND REMOVE NON-ALPHAS 90 * 91 TRTAB DC 256C' ' 92 ORG TRTAB+C'a' 93 DC C'ABCDEFGHI' 94 ORG TRTAB+C'A' 95 DC C'ABCDEFGHI' 96 97 ORG TRTAB+C'j' 98 DC C'JKLMNOPQR' 99 ORG TRTAB+C'J' 100 DC C'JKLMNOPQR' 101 102 ORG TRTAB+C's' 103 DC C'STUVWXYZ' 104 ORG TRTAB+C'S' 105 DC C'STUVWXYZ' 106 107 ORG TRTAB+C'-' * RETAIN HYPHENS 108 DC C'-' 109 110 ORG TRTAB+C'''' * RETAIN SINGLE QUOTES 111 DC C'''' 112 ORG 113 114 LTORG * LTERALS NEED TO BE AHEAD OF TABLE 115 116 DS 0F * FULL WORD ALIGN 117 * 118 * TABLE IS 1000 ENTRIES.TABLE OVERFLOW' 81 SUBEXIT 82 83 BLANK DC C' ' 84 OUT DS CL30 * OUTPUT STRING & TEMP STORE 85 MVC MVC OUT(0).COUNT * TOTAL NUMBER OF ENTRIES 76 XDECO R5.OUT * CVT TO PRINTABLE 77 XPRNT OUT. EACH ENTRY IS 8 CHARS FOR WORD 119 * AND 4 BYTES COUNT.75 BYE L R5.

23 General Instruction Set Name Mnemonic Type CC OpCode RR RX RX RI RR RX RR RX SS SI RR RX RR RX RR RR RR RX RR RX RS RS RI RI RI RSI RSI RRE RR RX S RS RS RX RI RR RX SS SI RS RR RS RRE RRE RX RX RRE RR RX RR RX SS SI RX RRE RX C C C C C C C C C C 1A 5A 4A A7A 1E 5E 14 54 D4 94 05 45 0D 4D 0C 0B 07 47 06 46 86 87 A75 A74 A76 84 85 B241 19 59 B21A BA BB 49 A7E 15 55 D5 95 BD 0F A9 B25D B257 B2|4F 4E B24D 1D B2|5D 17 57 D7 97 44 B24F 43 ADD AR ADD A ADD HALFWORD AH ADD HALFWORD IMMEDIATE AHI ADD LOGICAL ALR ADD LOGICAL AL AND NR AND N AND (character) NC AND (immediate) NI BRANCH AND LINK BALR BRANCH AND LINK BAL BRANCH AND SAVE BASR BRANCH AND SAVE BAS BRANCH AND SAVE AND SET MODE BASSM BRANCH AND SET MODE BSM BRANCH ON CONDITION BCR BRANCH ON CONDITION BC BRANCH ON COUNT BCTR BRANCH ON COUNT BCT BRANCH ON INDEX HIGH BXH BRANCH ON INDEX LOW OR EQUAL BXLE BRANCH RELATIVE AND SAVE BRAS BRANCH RELATIVE ON CONDITION BRC BRANCH RELATIVE ON COUNT BRCT BRANCH RELATIVE ON INDEX HIGH BRXH BRANCH RELATIVE ON INDEX LOW OR EQ. UNDER MASK CLM COMPARE LOGICAL LONG CLCL COMPARE LOGICAL LONG EXTENDED CLCLE COMPARE LOGICAL STRING CLST COMPARE UNTIL SUBSTRING EQUAL CUSE CONVERT TO BINARY CVB CONVERT TO DECIMAL CVD COPY ACCESS CPYA DIVIDE DR DIVIDE D EXCLUSIVE OR XR EXCLUSIVE OR X EXCLUSIVE OR (character) XC EXCLUSIVE OR (immediate) XI EXECUTE EX EXTRACT ACCESS EAR INSERT CHARACTER IC C C C C C C C C C C C C C C C C C C C C Table 20 General Instructions (continued on next page) 135 . BRXLE CHECKSUM CKSM COMPARE CR COMPARE C COMPARE AND FORM CODEWORD CFC COMPARE AND SWAP CS COMPARE DOUBLE AND SWAP CDS COMPARE HALFWORD CH COMPARE HALFWORD IMMEDIATE CHI COMPARE LOGICAL CLR COMPARE LOGICAL CL COMPARE LOGICAL (character) CLC COMPARE LOGICAL (immediate) CLI COMPARE LOGICAL C.

INSERT CHARACTERS UNDER MASK INSERT PROGRAM MASK LOAD LOAD LOAD ACCESS MULTIPLE LOAD ADDRESS LOAD ADDRESS EXTENDED LOAD AND TEST LOAD COMPLEMENT LOAD HALFWORD LOAD HALFWORD IMMEDIATE LOAD MULTIPLE LOAD NEGATIVE LOAD POSITIVE MONITOR CALL MOVE (character) MOVE (immediate) MOVE INVERSE MOVE LONG MOVE LONG EXTENDED MOVE NUMERICS MOVE PAGE (facility 1) MOVE STRING MOVE WITH OFFSET MOVE ZONES MULTIPLY MULTIPLY MULTIPLY HALFWORD MULTIPLY HALFWORD IMMEDIATE MULTIPLY SINGLE MULTIPLY SINGLE OR OR OR (character) OR (immediate) PACK PERFORM LOCKED OPERATION SEARCH STRING SET ACCESS SET PROGRAM MASK SHIFT LEFT DOUBLE SHIFT LEFT DOUBLE LOGICAL SHIFT LEFT SINGLE SHIFT LEFT SINGLE LOGICAL SHIFT RIGHT DOUBLE SHIFT RIGHT DOUBLE LOGICAL SHIFT RIGHT SINGLE SHIFT RIGHT SINGLE LOGICAL STORE STORE ACCESS MULTIPLE STORE CHARACTER STORE CHARACTERS UNDER MASK STORE CLOCK STORE HALFWORD STORE MULTIPLE SUBTRACT SUBTRACT SUBTRACT HALFWORD SUBTRACT LOGICAL SUBTRACT LOGICAL ICM IPM LR L LAM LA LAE LTR LCR LH LHI LM LNR LPR MC MVC MVI MVCIN MVCL MVCLE MVN MVPG MVST MVO MVZ MR M MH MHI MSR MS OR O OC OI PACK PLO SRST SAR SPM SLDA SLDL SLA SLL SRDA SRDL SRA SRL ST STAM STC STCM STCK STH STM SR S SH SLR SL RS RRE RR RX RS RX RX RR RR RX RI RS RR RR SI SS SI SS RR RS SS RRE RRE SS SS RR RX RX RI RRE RX RR RX SS SI SS SS RRE RRE RR RS RS RS RS RS RS RS RS RX RS RX RS S RX RS RR RX RX RR RX C C C C C C C C C C C C C C C L C C C C C C C C C C BF B222 18 58 9A 41 51 12 13 48 A78 98 11 10 AF D2 92 E8 0E A8 D1 B254 B255 F1 D3 1C 5C 4C A7C B252 71 16 56 D6 96 F2 EE B25E B24E 04 8F 8D 8B 89 8E 8C 8A 88 50 9B 42 BE B205 40 90 1B 5B 4B 1F 5F Table 20 General Instructions (continued) (continued on next page) 136 .

SUPERVISOR CALL TEST AND SET TEST UNDER MASK TEST UNDER MASK HIGH TEST UNDER MASK LOW TRANSLATE TRANSLATE AND TEST UNPACK UPDATE TREE SVC TS TM TMH TML TR TRT UNPK UPT RR S SI RI RI SS SS SS E C C C C C C 0A 93 91 A70 A71 DC DD F3 0102 Table 20 General Instructions (continued) Over the years people have suggested a number of interesting if less practical extensions (humorously. that is): ARG BDM CMN DDS EMR ETO FSE GSI GQS HEM IDD IKI IMU JPF JUM KFP LNM MAW NNI OBU PNG QWF QVC RWD SCE SDJ TTC UBC VDP VMB WAF XID YII ZAM PI POPI RASC RPM RSSC RTAB RWDSK SPSW SRSD WBT : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Agree to Run Garbage Branch and Destroy Memory Convert to Mayan Numerals Damage Disk and Stop Emit Microwave Radiation Emulate Toaster Oven Fake Serious Error Garble Subsequent Instructions Go Quarter Speed Hide Evidence of Malfunction Inhale Dust and Die Ignore Keyboard Input Irradiate and Mutate User Jam Paper Feed Jeer at Users Mistake Kindle Fire in Printer Launch Nuclear Missiles Make Aggravating Whine Neglect Next Instruction Overheat and Burn if Unattended Pass Noxious Gas Quit Working Forever Question Valid Command Read Wrong Device Simulate Correct Execution Send Data to Japan Tangle Tape and Crash Use Bad Chip Violate Design Parameters Verify and Make Bad Warn After Fact eXchange Instruction with Data Yield to Irresistible Impulse Zero All Memory Punch Invalid Punch Operator Immediately Read And Shred Card Read Programmers Mind Reduce Speed. Step Carefully (for improved accuracy) Rewind Tape and Break ReWind DiSK Scramble Program Status Word Seek Record and Scar Disk Water Binary Tree Figure 55 Over-Extended Instructions (humor) 137 .

138 .

............................................................................................................................................................. 102 EDIT...................................................................................................................................................................95 Load Negative.................102 DP.................................................................................................................. 62 Base/displacement....... 49 BCTR...................................................................... 97 Numeric data types................................................................................ 83 Line Format...........87 Move Numerics.................................................................................................................................................................................................................................................................................................................................. 97 ARCHLVL1................................... 18 LCR.... 106 DS........ 89 CLOSE...................................................................................... 84 Multiply..................................................................................................................................................................................................................................................................... 109 LTR....... 9 ARCHLVL3.........................................110 EQUREGS.......................................................................... 90 MVI..................................................................................................35 Machine Language Format...................................................................................................98 Explicit Addressing...9 Immediate operand............................... 102 DR........................................................................................................57 Digit selector......61 Literal...................................................................... 88 Literals....... 97 NC...................................................... 9 2s Complement............... 95 LNR.......................43 Conditional branch.................18.....................................................................................................................................87 BC.......................... 97 NR........................................................ 9 Arithmetic shift instructions.................................. 96 M........................................................................................................................................................109 Mask... 32 Index register............................. 69 Floating point registers.......................................................................................................................... 109 CSECT............100 BAL...................................32 L.. 84 Machine language......................................................................................................................................16 Index registers.. 52 ED.........87 MP............................84 Multiply Packed............................................................102 MVC..................................... 84 Alignment..............................57 Declare storage................................................................................................................................................... 87 MVI)..........................................45 Extended Mnemonics.............. 85 DB....................................................................................................................................... BCR)..................................110 Halfword Instructions...................................................................... 102 MR......................................................... 61 EODAD................................................98 Condition Code/...... 83 AL.................................................................................................... 110 Compare logical character...............................................................................................................88 Complement...............43 Conditional Branching (BC........18 Linkage..................... 43 Mask settings................................................................................................................. 87 MVCL.................................88 Compare Logical Character Long......................................................................................................................................................................................................................52 Bit Operations...................................................................... 57 ALR....................15 General purpose registers....... 85 DROP.............. 110 Decimal Arithmetic..................................................................................................................................................................90 Move Immediate. 57 DCB........... 96 LRECL...........70............................................................................................................. 51 Character Long Instructions..................................................... 10 CLC................................................................................................................................................................................................................................................................................................................................................................... 23 Even/odd register pairs...............................................................................89 CISC.........................................51.......... 9 ARCHLVL2...................................................................................................................15 GET.....................................................................................................................................................................16 Base/displacement addressing.............................................................. 89 CLI............59 LM.........................................................................96 Load Multiple.................................................103 Move Zones........ 75 EBCDIC....................52 A................................................................................... 51 DC...........................................................................................................................72 Logical shift instructions......................................................................................................... 48 CAFE........................ 52....................31 Extended mnemonic............................................................................................................ 11 Binary integer....................................................................................................................................................................................................................................... 84 AND....................................................101 Declare constant..........48 EX....................................103 Divide.............................................................................................................83 Hexadecimal.........................................80 Floating point............................................................................................. 61 Linkage Registers............................................................................................96 Load Positive...... 88 CLCL..................................................................................................... 88 Exclusive OR.........................................................................................................................................................................................Alphabetical Index 1s complement....................... 51 BCT......................................97 Boolean instructions......... 103 N.................................................................96 Location counter................103 Moving Characters...................................................99 LPR.....51............... 81 BCD........ 85 Move Character Long............................................................................................................................................................................................... 52................................................................................... 112 CVD.........................................95 Load and Test................................................................................................................................................................................................................ 95 Labels........ 103 MVZ.............................29.......................... 57 Dump......................................................................................................................................... 97 NI.................. 11 IBM 360........... 96 Load................. 110 DDNAME...................... 62 CVB.......... 69 Binary Integers..................51 139 .....................44 MH.............................. 71 AH......................... 52 D............................................................. 49 Binary........................................ 85 Divide Packed.........................54 24 bit address................................................................................................... 102 End-of-file........................................................................... 66 Entry point...........................................35 MACRF.............................................................43 CR/LF...... 87 MVN..........................................................................................................................................................................................................................................................................................................................................................................................................................................89 Compare Logical Characters...........................................................................................................................................................................................97 BXLE.................................... 98 LH........................................................................15 Basic Character Instructions...

....................................................................................................................................................... 111 Zoned format..... 65 XR.... 83 PACK.. 67.......................................101 Test Under Mask.................................................................103 UNPK........................................... 84 SR................................ 98 XC..................................33 Test and Set............................................................................................................................... 91 Overflow...............................................................67 XI.................................................................. 34 SUBEXIT.................................................................... 19 Subtraction.......................................................................................... 84 SLDA........................................................................................................................ 90 TS................................35 RS Machine Language Format........................................................................................................ 109 Relocatability...................................................... 109 RECFM........................................................................................................37 RX Machine Language Format.......................................................66 XDECI ....................................................................................................................................................... 103 Unsigned arithmetic....................................................................................................................................... 110 QSAM..............................................................................................................................................................................................................................................................................58 Powers of two.......... 83 Save Area............................... 71 XDUMP......................................................................... 111 Padding bytes.................................................................................................. 106 X.......................36 S................................................................................................................................................................................................................................................................................................................................................. 70........................................ 84 SLR.....51 140 ...............................52 Significance starter..................................................................................... 99 SI Format.................................................. 83 Overflows............................................................................ 90 Translate and Test..................... 63 PUT.................................... 29 SI Machine Language Format.........65 Zoned Decimal.95 SUBENTRY.....................18.....................................................66.................................................................................................................................................................................33............................................................................................................................................ 95 Store.................................103 SL.......... 83 Shift.....16 RR Machine Language Format............................................................................................ 83 STM....................................................................................................................................................101. 23 PRN File............100 TM.. 98 XPRNT...................................................... 61 SH.........................41 PSW.............................................................. 98 OR.............................................................................................. 72 Program Status Word.......84 USING......................................62...........................................................................................53 PRINT NOGEN.............................................................................................95 Store Multiple... 98 XREAD................................................................................................ 98 XDECI...... 100 TR....................................90 TRT................................................................................................................................................................... 98 OI............................67 XHEXO......................................... 98 OC........................................................39 ST............................................................................... 67 XDECO................................................ 69.. 101 UNPACK...................38 Sign and magnitude........51.......... 84 SLA........................................................ 95 STH......... 83 Symbolic Addressing..........................66 XHEXI................. 97 ORG......................................................... 41..............................51........... 83 SS Machine Language Format... 112 Packed Decimal........................................................................................................................................................................................................19......O........................

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