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Revision History
The following table shows the revision history for this document. Version 08/02/04 09/03/04 10/05/04 11/05/04 11/30/04 1.0 1.1 1.2 1.3 2.0 Revision Initial Xilinx release. (Printed Handbook version.) Added Chapters 2 and 3. Removed FF1152 package information from Chapters 2 and 3. Added FF1152 pinout information, and revised TDN, TDP, ADC, and SM pin references. • • • • 12/21/04 2.1 • • • Revised four pins affecting only XC4VFX100 devices in the FF1152 package. Added FF676 pinout information. Corrected symbol used for pin AN28 in the FF1513 pinout diagram. Added MGT pin definitions to Table 1-3. Changed four VCCO pins to No Connects in Banks 9 and 10, affecting only XC4VFX20 devices in the FF672 package. Added a colorized SelectIO and bank information diagram for each package. Made minor changes to pin definitions in Table 1-3.

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Version 01/19/05 2.2 • • 02/10/05 09/30/05 2.3 2.4 • • • •

Revision Corrected pin A9 in the FF1152 package (Table 2-6), affecting only XC4VFX100 devices. Corrected the FF1152 pinout diagrams. Removed FF676 package information from the guide. Made minor changes to pin definitions in Table 1-3. Added information on the FF676 package to all the chapters in this guide. Revised Table 1-3, page 14. Added LVDSEXT and updated all INIT_# to INIT_B_0. All dedicated configuration pins are in bank 0. Updated INIT_B and PROG_B references for consistency. Corrected package pinout diagram pins: AE16 in Figure 3-15 and AC34 in Figure 3-17. Revised mechanical drawings for the FF672 (Figure 4-3) and FF1760 (Figure 4-9) packages. Added FF676 package (Figure 4-4). Removed A-A cross sections from all the mechanical drawings in Chapter 4, “Mechanical Drawings”. Revised and updated Chapter 5, “Thermal Specifications”.

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Virtex-4 Packaging and Pinout Specification

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Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide
Organization of This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Packaging Overview
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 2: Pinout Tables
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SF363 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FF668 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF672 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FF676 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 FF1148 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 FF1152 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 FF1513 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 FF1517 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 FF1760 Flip-Chip Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Chapter 3: Pinout Diagrams
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 SF363 Package Pinout Diagram (LX15 and FX12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SF363 Package Pinout Diagram (LX25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 SF363 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . . 293 FF668 Package Pinout Diagram (LX15, SX25, and FX12). . . . . . . . . . . . . . . . . . . . . . 294

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FF668 Package Pinout Diagram (LX25, LX40, LX60, and SX35) . . . . . . . . . . . . . . . 295 FF668 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . . 296 FF672 Package Pinout Diagram (FX20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 FF672 Package Pinout Diagram (FX40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 FF672 Package Pinout Diagram (FX60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 FF672 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . . 300 FF676 Package Pinout Diagram (LX15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 FF676 Package Pinout Diagram (LX25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 FF676 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . . 303 FF1148 Package Pinout Diagram (LX40, LX60, and SX55) . . . . . . . . . . . . . . . . . . . . 304 FF1148 Package Pinout Diagram (LX80, LX100, and LX160) . . . . . . . . . . . . . . . . . . 305 FF1148 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . 306 FF1152 Package Pinout Diagram (FX40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 FF1152 Package Pinout Diagram (FX60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 FF1152 Package Pinout Diagram (FX100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 FF1152 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . 310 FF1513 Package Pinout Diagram (LX100, LX160, and LX200) . . . . . . . . . . . . . . . . . 311 FF1513 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . 312 FF1517 Package Pinout Diagram (FX100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 FF1517 Package Pinout Diagram (FX140) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 FF1517 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . 315 FF1760 Package Pinout Diagram (FX140) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 FF1760 Color-Coded SelectIO and Bank Information . . . . . . . . . . . . . . . . . . . . . . . . 317

Chapter 4: Mechanical Drawings
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
SF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.80mm pitch) . . . . . . . . . 320 FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . . 321 FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . . 322 FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . . 323 FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . 324 FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . 325 FF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . 326 FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . 327 FF1760 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) . . . . . . . . 328

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. 329 Introduction . . . . . . . . . . 332 Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 References . . . .com 7 . . . . . . . . .xilinx. . . . . . . 329 Virtex-4 Power Management Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Some Thermal Management Options . . . . . . . . . . . . . . . 2005 www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4) September 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Virtex-4 Packaging and Pinout Specification UG075 (v2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R Chapter 5: Thermal Specifications Summary . . . . . . . . .

2005 .R 8 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx.

“Pinout Diagrams” Provides pinout diagrams for all Virtex-4 package/device combinations.xilinx. “Pinout Tables” Provides pinout information for all Virtex-4 devices and packages. 2005 www. “Thermal Specifications” Provides thermal data associated with Virtex-4 packages.xilinx. Organization of This Guide This document is comprised of the following chapters: • Chapter 1.4) September 30. “Packaging Overview” Provides an introduction to the Virtex-4 family with a summary of maximum I/Os available in each device/package combination. Chapter 3. Chapter 5. Discusses Virtex-4 power management strategy and thermal management options. Related Documentation The following documents are also available for download at http://www. “Mechanical Drawings” Provides mechanical drawings of all Virtex-4 packages.com/virtex4. • Virtex-4 User Guide Chapters in this guide cover the following topics: Clocking Resources Digital Clock Manager (DCM) Virtex-4 Packaging and Pinout Specification UG075 (v2.com 9 . Virtex-4 Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-4 family.R Preface About This Guide This guide describes Virtex™-4 device pinouts and package specifications. Chapter 4. Also includes table of pin definitions. • • • • Chapter 2. • • Virtex-4 Family Overview The features and product selection of the Virtex-4 family are outlined in this overview. it also includes pinout diagrams and thermal data.

com/virtex4 10 www. and readback through the SelectMAP and JTAG interfaces. • Virtex-4 PCB Designers Guide This designer’s guide provides information on the design of PCBs for Virtex-4 devices.com Virtex-4 Packaging and Pinout Specification UG075 (v2. or to create a technical support case in WebCase. It considers all aspects of the PCB from the system level down to the minute details. • Virtex-4 Tri-Mode Ethernet Media Access Controller This guide describes the Tri-Mode Ethernet Media Access Controller available in the Virtex-4 FX family. boundary-scan and JTAG configuration.R Preface: About This Guide • Phase-Matched Clock Dividers (PMCD) Block RAM and FIFO memory Configurable Logic Blocks (CLBs) SelectIO Resources SelectIO Logic Resources Advanced SelectIO Logic Resources XtremeDSP™ Design Considerations This guide describes the XtremeDSP slice and includes reference designs for using DSP48 math functions and various FIR filters.xilinx. • Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide This guide describes the RocketIO Multi-Gigabit Transceivers available in the Virtex-4-FX family. The address (F) is asserted after clock event 2. Additional Resources To search the database of silicon and software questions and answers. 2005 . reconfiguration techniques. Example See the Virtex-4 Configuration Guide for more information.xilinx. bitstream encryption.4) September 30.xilinx.com/support Typographical Conventions The following typographical conventions are used in this document: Convention Meaning or Use References to other documents Italic font Emphasis in text Underlined Text Indicates a link to a web page. visit the following Xilinx website: http://www. http://www. • PowerPC™ 405 Processor Block Reference Guide This guide is updated to include the PowerPC 405 processor block available in the Virtex-4 FX family. • Virtex-4 Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP). This guide focuses on strategies for making design decisions at the PCB and interface level.

Global pins. Virtex-4 Packaging and Pinout Specification UG075 (v2.80 mm and 1.com and check for any updates to this document. Table 1-3 provides definitions for all pin types. are listed at the end of each table.xilinx. 2005 www. Virtex-4 devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter.R Chapter 1 Packaging Overview Summary This chapter covers the following topics: • • • Introduction Device/Package Combinations and Maximum I/Os Pin Definitions Introduction This section describes the pinouts for Virtex-4 devices in the 0. including JTAG.xilinx. and power/ground pins.com 11 . visit www. of Power and GND pins. To be assured of having the very latest Virtex-4 pinout information. Pins that are not available for the smaller devices are listed in the "No Connects" column of each table. as well as an increased number. configuration.00 mm pitch flip-chip fine-pitch BGA packages. Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O standards (see the Virtex-4 User Guide).4) September 30. All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Package inductance is minimized as a result of optimal placement and even distribution.

and XC4VFX device/package combination. AVCCAUXRX. DXN. 2005 .00 mm 27 x 27 352 FF676 1. PWRDWN_B. AVCCAUXMGT. The number of I/Os per package includes all user I/Os except the fifteen control pins (CCLK. XC4VSX. TCK.5 896 Table 1-2 shows the number of available I/Os. M2.00 mm 40 x 40 768 FF1760 1. HSWAP_EN. TXP. RTERM. PROG_B. MGTVREF.00 mm 27 x 27 448 FF672 1.5 x 42. M1. DXP.80 mm 17 x 17 240 FF668 1. the number of RocketIO™ multi-gigabit transceivers (MGTs).4) September 30. TMS. AND RSVD) and the RocketIO MGT pins (AVCCAUXTX. VTRX. M0.00 mm 42.00 mm 35 x 35 576 FF1513 1. Table 1-2: Virtex-4 Device Virtex-4 Available I/Os and RocketIO MGT Pins per Device/Package Combination User I/Os & RocketIO MGT Pins Available User I/Os Virtex-4 Package SF363 FF668 240 N/A 120 240 N/A 120 320 N/A 160 448 N/A 224 448 N/A 224 448 N/A 224 FF672 FF676 320 N/A 160 448 N/A 224 FF1148 640 N/A 320 640 N/A 320 768 N/A 384 FF1152 FF1513 FF1517 FF1760 - XC4VLX15 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX25 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX40 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX60 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX80 RocketIO Transceivers Differential I/O Pairs 12 www.00 mm 27 x 27 448 FF1148 1.00 mm 40 x 40 960 FF1517 1.R Chapter 1: Packaging Overview Device/Package Combinations and Maximum I/Os Table 1-1 shows the maximum number of user I/Os possible in Virtex-4 flip-chip packages. TDO.com Virtex-4 Packaging and Pinout Specification UG075 (v2. VTTX. • • Table 1-1: Package Pitch (mm) Size (mm) Maximum I/Os SF denotes flip-chip fine-pitch BGA (0. MGTCLK. and GNDA). DONE. RXN.xilinx.80 mm pitch) FF denotes flip-chip fine-pitch BGA (1.00 mm 35 x 35 768 FF1152 1. TXN.00 mm pitch) Flip-Chip Packages SF363 0. and the number of differential I/O pairs for each Virtex-4 XC4VLX. RXP. TDI.

xilinx.Device/Package Combinations and Maximum I/Os R Table 1-2: Virtex-4 Device Virtex-4 Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued) User I/Os & RocketIO MGT Pins Available User I/Os Virtex-4 Package SF363 FF668 240 N/A 120 320 N/A 160 448 N/A 224 320 N/A 160 FF672 320 8 160 352 12 176 352 12 176 FF676 FF1148 768 N/A 384 768 N/A 384 640 N/A 320 FF1152 448 12 224 576 16 288 FF1513 960 N/A 480 960 N/A 480 960 N/A 480 FF1517 FF1760 - XC4VLX100 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX160 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VLX200 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VSX25 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VSX35 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VSX55 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VFX12 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VFX20 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VFX40 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VFX60 RocketIO Transceivers Differential I/O Pairs Virtex-4 Packaging and Pinout Specification UG075 (v2.com 13 . 2005 www.4) September 30.

D0 through D31 are configuration data pins. ULVDS. and they become regular user I/Os when not needed for clocks. The “_#” suffix appended to some pin descriptions indicates the bank in which that pin resides. CC (2) Input/Output GC (2) LC (2) Input/Output Input/Output 14 www. For a description of RocketIO pins. see the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076).xilinx. These lower capacitance clock pins connect to Clock Capable I/Os. Table 1-3: Virtex-4 Pin Definitions Direction Description Pin Name User I/O Pins IO_LXXY_# Input/Output All user I/O pins are capable of differential signalling and can implement LVDS. These lower capacitance pins do not support LVDS outputs. where ZZZ represents one or more of the functions described below. LXXY indicates a differential pair.R Chapter 1: Packaging Overview Table 1-2: Virtex-4 Device Virtex-4 Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued) User I/Os & RocketIO MGT Pins Available User I/Os Virtex-4 Package SF363 FF668 FF672 FF676 FF1148 FF1152 576 20 288 FF1513 FF1517 768 20 384 768 24 384 FF1760 896 24 448 XC4VFX100 RocketIO Transceivers Differential I/O Pairs Available User I/Os XC4VFX140 RocketIO Transceivers Differential I/O Pairs Pin Definitions Table 1-3 provides a description of each pin type listed in Virtex-4 pinout tables. Pins that do not have this suffix appended are not associated with any particular bank. 2005 . These pins do not support LVDS outputs. LVDSEXT. In SelectMAP mode. These lower capacitance clock pins connect to Global Clock Buffers. Each user I/O is labeled “IO_LXXY_#”. These pins do not support LVDS outputs.com Virtex-4 Packaging and Pinout Specification UG075 (v2. BLVDS. where: IO indicates a user I/O pin. with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair. These pins become user I/Os after configuration. ZZZ is one or more of the following: ADCn Dn Input/Output Input/Output ADC1 through ADC7 input pins are reserved for future use but can be used for I/O or other designated functions.4) September 30. Multi-Function Pins IO_LXXY_ZZZ_# Multi-function pins are labelled “IO_LXXY_ZZZ_#”. and they become regular user I/Os when not needed for clocks. For a given multi-function pin. unless the SelectMAP port is retained. or LDT pairs. LVPECL.

It does not require an external pull-up. In bit-serial modes. a Low on this output indicates that a configuration data error has occurred. DONE_0 Input/Output DOUT_BUSY_0 Output HSWAPEN_0 Input Bidirectional (open-drain) Input Input Input (unsupported) Input Input Input Output Input N/A INIT_B_0 M0_0. They become user I/Os when an external threshold voltage is not needed (per bank). BUSY controls the rate at which configuration data is loaded. Pin Name SMn VREF VRN VRP Dedicated Configuration Pins (1) CCLK_0 CS_B_0 D_IN_0 Input/Output Input Input Configuration clock. 2005 www. DONE is a bidirectional signal with an optional internal pull-up resistor.com 15 .xilinx. Output and input in Master mode or Input in Slave mode. Enable I/O pullups during configuration When Low. In bit-serial modes. the start of configuration is delayed.4) September 30. As an input. In SelectMAP mode. which is its default state. Cathode: TDN). to be pulled High with reference resistor). During configuration. This pin has a permanent weak pull-up resistor. In SelectMAP mode. this is the active-low Chip Select signal. this pin indicates that the configuration memory is being cleared. This pin is for the DCI voltage reference resistor of N transistor (per bank. TDN_0 Virtex-4 Packaging and Pinout Specification UG075 (v2. Driving this pin Low can adversely affect device operation and configuration. PWRDWN_B is internally pulled High. this pin indicates completion of the configuration process. D_IN is the single-data input. a Low level on DONE can be configured to delay the start-up sequence. DOUT gives preamble and configuration data to downstream devices in a daisy chain. These are input threshold voltage pins.Pin Definitions R Table 1-3: Virtex-4 Pin Definitions (Continued) Direction Input/Output Input/Output Input/Output Input/Output Description SM1 through SM7 input pins are reserved for future use but can be used for I/O or other designated functions. When held Low. this is the active-low Write Enable signal. In SelectMAP mode. Configuration mode selection Active Low asynchronous reset to configuration logic. Boundary Scan Clock Boundary Scan Data Input Boundary Scan Data Output Boundary Scan Mode Select Temperature-sensing diode pins (Anode: TDP. M2_0 PROG_B_0 PWRDWN_B_0 RDWR_B_0 TCK_0 TDI_0 TDO_0 TMS_0 TDP_0. Active Low power-down pin (unsupported). This pin is for the DCI voltage reference resistor of P transistor (per bank. to be pulled Low with reference resistor). M1_0. As an output.

xilinx.2V). Analog power supply for transmit circuitry of the RocketIO MGT (1.4) September 30. Positive differential receive port of the RocketIO MGT.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). This pin is reserved for future use and should be connected to GND. This pin is reserved for future use and should be connected to GND.R Chapter 1: Packaging Overview Table 1-3: Virtex-4 Pin Definitions (Continued) Direction Description Pin Name Reserved Pins AVDD_SM AVSS_SM VN_SM VP_SM VREFN_SM VREFP_SM AVDD_ADC AVSS_ADC VN_ADC VP_ADC VREFN_ADC VREFP_ADC RSVD Other Pins GND VBATT_# VCCAUX VCCINT VCCO_# Input Input Input Input Input Input Input Input Input Input Input Input N/A This pin is reserved and should be connected to 2. Decryptor key memory backup supply. This pin is reserved for future use and should be connected to GND.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). This pin is reserved for future use and should be connected to GND.5V). AVCCAUXRXB_# AVCCAUXTX_# AVCCAUXMGT_# GNDA_# RXPPADA_#. Reserved pin . Ground for the analog circuitry of the RocketIO MGT.com Virtex-4 Packaging and Pinout Specification UG075 (v2. This pin is reserved for future use and should be connected to GND. 16 www.2V). Power-supply pins for auxiliary circuits Power-supply pins for the internal core logic Power-supply pins for the output drivers (per bank) RocketIO Multi-Gigabit Transceiver (MGT) Pins AVCCAUXRXA_#. This pin is reserved for future use and should be connected to GND. 2005 .do not connect Input Input Input Input Input Ground. this pin should be tied to VCC or GND. This pin is reserved and should be connected to 2. RXNPADB_# Input Input Input Input Input Input Analog power supply for receive circuitry of the RocketIO MGT (1. Negative differential receive port of the RocketIO MGT. Analog power supply for global bias (2. RXPPADB_# RXNPADA_#. This pin is reserved for future use and should be connected to GND. This pin is reserved for future use and should be connected to GND. This pin is reserved for future use and should be connected to GND. This pin is reserved for future use and should be connected to GND.

All dedicated pins (JTAG and configuration) are powered by VCC_CONFIG.com 17 . Virtex-4 Packaging and Pinout Specification UG075 (v2. VTTXB_# Notes: 1.5V). Negative differential transmit port of the RocketIO MGT.xilinx.2V .1. VTRXB_# VTTXA_#. Receive termination supply for the RocketIO MGT (0V . 3. Transmit termination supply for the RocketIO MGT (1. see the Virtex-4 User Guide (UG070).4) September 30. For more information on lower capacitance pins. Pin Name TXPPADA_#. 2005 www. 2.Pin Definitions R Table 1-3: Virtex-4 Pin Definitions (Continued) Direction Output Output Input Input Description Positive differential transmit port of the RocketIO MGT. see the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076).5V). For more information on RocketIO pins. TXPPADB_# TXNPADA_#. TXNPADB_# VTRXA_#.2.

4) September 30.R Chapter 1: Packaging Overview 18 www. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

LX25. and FX12 devices are available in this package. FX60. LX60. • FF1517 Flip-Chip Fine-Pitch BGA Package FX140 and FX100 devices are available in this package. 2005 www. • FF1152 Flip-Chip Fine-Pitch BGA Package FX100. • FF676 Flip-Chip Fine-Pitch BGA Package LX15 and LX25 devices are available in this package. and FX12 devices are available in this package. LX25. and FX20 devices are available in this package. • FF668 Flip-Chip Fine-Pitch BGA Package LX15.4) September 30. LX80. SX25. • FF1148 Flip-Chip Fine-Pitch BGA Package LX40. LX40. and LX200 devices are available in this package. LX160.com 19 . • FF672 Flip-Chip Fine-Pitch BGA Package FX60.R Chapter 2 Pinout Tables Summary This chapter provides pinout information for the following packages: • SF363 Flip-Chip Fine-Pitch BGA Package LX15. FX40. LX100. and FX40 devices are available in this package. • FF1760 Flip-Chip Fine-Pitch BGA Package FX140 devices are available in this package. and SX55 devices are available in this package. Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160. SX35. LX60.xilinx. • FF1513 Flip-Chip Fine-Pitch BGA Package LX100.

Virtex-4 XC4VLX15. 2005 .xilinx.4) September 30.xilinx. Table 2-1: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SF363 Package — LX15. visit www. To be assured of having the very latest Virtex-4 pinout information.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX12 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number E13 E11 E9 F12 E12 E8 F11 F9 T13 R11 T10 T8 R12 R10 T9 T12 T11 R9 E10 F10 No Connects in LX15 and FX12 Devices 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 F15 E15 E6 F6 D15 E14 E7 D6 20 www. LX25. ASCII package pinout files are also available for download from the Xilinx website. and XC4VFX12 devices are available in the SF363 flip-chip fine-pitch BGA package.R Chapter 2: Pinout Tables SF363 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-1.com and check for any updates to this document. XC4VLX25. The “No Connect” column in Table 2-1 shows pins that are not available in LX15 devices.

and FX12 Devices (Continued) Pin Description IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 Pin Number D13 C13 C8 D8 D12 C12 C9 D9 No Connects in LX15 and FX12 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 V16 V15 V6 V5 T14 U13 U8 T7 V13 V12 V9 V8 U12 V11 V10 U9 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 B12 A11 A10 B9 C11 B11 B10 C10 B13 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 21 .xilinx.4) September 30. 2005 www.SF363 Flip-Chip Fine-Pitch BGA Package R Table 2-1: Bank 1 1 1 1 1 1 1 1 SF363 Package — LX15. LX25.

LX25. 2005 .xilinx. and FX12 Devices (Continued) Pin Description IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number A13 A8 B8 B14 A14 A7 B7 No Connects in LX15 and FX12 Devices 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 W13 W12 Y5 W5 Y12 Y11 Y6 W6 W11 W10 Y7 W7 Y10 Y9 W9 W8 5 5 5 5 5 5 5 5 5 5 IO_L1P_5 IO_L1N_5 IO_L2P_5 IO_L2N_5 IO_L3P_5 IO_L3N_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_5 IO_L5N_5 B15 A15 A16 B16 C15 C16 B17 C17 D16 E16 22 www.R Chapter 2: Pinout Tables Table 2-1: Bank 3 3 3 3 3 3 3 SF363 Package — LX15.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

LX25.SF363 Flip-Chip Fine-Pitch BGA Package R Table 2-1: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SF363 Package — LX15.com 23 . and FX12 Devices (Continued) Pin Description IO_L6P_5 IO_L6N_5 IO_L7P_5 IO_L7N_5 IO_L8P_CC_LC_5 IO_L8N_CC_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 Pin Number A18 B18 D17 D18 B19 C20 J17 J18 H20 G20 J15 J16 H18 H19 K16 K17 K20 J19 L16 L17 K18 K19 F18 E18 C18 C19 F16 F17 D19 E19 G16 G17 E20 F20 H16 H17 No Connects in LX15 and FX12 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.4) September 30.xilinx.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-1: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SF363 Package — LX15.4) September 30. 2005 . and FX12 Devices (Continued) Pin Description IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number F19 G19 M17 M18 M20 L20 M15 M16 M19 L19 N16 N17 N18 N19 P16 P17 P19 P20 No Connects in LX15 and FX12 Devices 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 B6 A6 A5 B5 C6 C5 B4 C4 D5 E5 A3 B3 D4 D3 B2 C1 24 www.xilinx. LX25.

and FX12 Devices (Continued) Pin Description IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 Pin Number J4 J3 H1 G1 J6 J5 H3 H2 K5 K4 K1 J2 L5 L4 K3 K2 F3 E3 C3 C2 F5 F4 D2 E2 G5 G4 E1 F1 H5 H4 F2 G2 M4 M3 M1 L1 No Connects in LX15 and FX12 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.com 25 .4) September 30. LX25. 2005 www.xilinx.SF363 Flip-Chip Fine-Pitch BGA Package R Table 2-1: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 SF363 Package — LX15.

4) September 30.R Chapter 2: Pinout Tables Table 2-1: Bank 6 6 6 6 6 6 6 6 6 6 6 6 SF363 Package — LX15. and FX12 Devices (Continued) Pin Description IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number M6 M5 M2 L2 N5 N4 N3 N2 P5 P4 P2 P1 No Connects in LX15 and FX12 Devices 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (1) IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 (1) IO_L26N_SM6_7 (1) IO_L27P_SM5_7 (1) IO_L27N_SM5_7 IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 (1) IO_L29N_SM4_7 (1) IO_L30P_SM3_7 IO_L30N_SM3_7 (1) (1) (1) (1) T17 T18 U18 U19 T15 U15 V19 V20 U16 U17 W18 W19 Y17 W17 V17 V18 R19 R20 R15 R16 T19 T20 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L31P_SM2_7 (1) IO_L31N_SM2_7 (1) IO_L32P_SM1_7 (1) IO_L32N_SM1_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 (1) 26 www. LX25. 2005 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

SF363 Flip-Chip Fine-Pitch BGA Package R Table 2-1: Bank 7 7 SF363 Package — LX15.xilinx. and FX12 Devices (Continued) Pin Description IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 Pin Number R17 R18 No Connects in LX15 and FX12 Devices 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 U3 U2 T4 T3 T6 U6 V2 V1 U5 U4 W3 W2 Y4 W4 V4 V3 R2 R1 R6 R5 T2 T1 R4 R3 0 0 1 1 2 2 3 VCCO_0 (2) VCCO_0 (2) VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 D10 U11 D7 D14 U7 U14 A9 See footnote #2 See footnote #2 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.com 27 . 2005 www. LX25.

com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX25.4) September 30. and FX12 Devices (Continued) Pin Description VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 Pin Number A12 Y8 Y13 K15 L15 A17 E17 L18 D20 J20 N20 D1 J1 N1 L3 A4 E4 K6 L6 T16 Y18 U20 U1 Y3 T5 No Connects in LX15 and FX12 Devices N/A N/A N/A N/A N/A N/A VREFP_SM (3) VREFN_SM (3) AVDD_SM VP_SM (4) W14 W15 W16 Y14 Y15 Y16 NC NC NC NC NC NC (3) VN_SM (3) AVSS_SM (3) N/A N/A GND GND B1 W1 28 www.R Chapter 2: Pinout Tables Table 2-1: Bank 3 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 7 8 8 8 SF363 Package — LX15.xilinx. 2005 .

SF363 Flip-Chip Fine-Pitch BGA Package R Table 2-1: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SF363 Package — LX15. LX25. and FX12 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number Y1 A2 Y2 G3 P3 C7 H7 J7 K7 L7 M7 N7 V7 G8 P8 G9 P9 G10 P10 U10 D11 G11 P11 G12 P12 G13 P13 C14 H14 J14 K14 L14 M14 N14 V14 G18 No Connects in LX15 and FX12 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.xilinx.com 29 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 . 3. and FX12 Devices (Continued) Pin Description GND GND GND GND GND GND GND Pin Number P18 A19 Y19 A20 B20 W20 Y20 No Connects in LX15 and FX12 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT H6 N6 F8 R8 F13 R13 H15 N15 G6 P6 F7 G7 P7 R7 F14 G14 P14 R14 G15 P15 1. Connect this reserved pin to 2. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide.4) September 30. LX25. 4. 30 www.xilinx. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). 2. Connect this reserved pin to GND.R Chapter 2: Pinout Tables Table 2-1: Bank N/A N/A N/A N/A N/A N/A N/A SF363 Package — LX15.

xilinx. LX40. and FX12 No Connects in LX15.com and check for any updates to this document. ASCII package pinout files are also available for download from the Xilinx website.com 31 .FF668 Flip-Chip Fine-Pitch BGA Package R FF668 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-2. LX60. SX25. SX25. 2005 www. the following Virtex-4 LX and SX devices are available in the FF668 flip-chip fine-pitch BGA package: • • • • • • • XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VSX25 XC4VSX35 XC4VFX12 Pinouts in the following devices are identical: • • LX15.xilinx. and FX12 devices. SX25. SX35. and FX12 LX25. LX25.4) September 30. and SX35 The “No Connect” column in Table 2-2 shows pins that are not available in LX15. LX60. SX25. Table 2-2: Devices Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF668 Package — LX15. LX40. To be assured of having the very latest Virtex-4 pinout information. visit www. and FX12 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 Pin Number G16 G14 G12 H15 G15 G11 H14 H12 Y16 W14 W13 Y11 W15 Y13 W12 Virtex-4 Packaging and Pinout Specification UG075 (v2.

SX25. LX40.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 . LX25. SX35. and FX12 Devices (Continued) Bank 0 0 0 0 0 Pin Description M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number Y15 Y14 Y12 G13 H13 No Connects in LX15. SX25. and FX12 Devices 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 F14 F13 F12 F11 F16 F15 D14 D13 D15 E14 C11 D11 D16 C16 E13 D12 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 AA14 AB14 AC12 AC11 AA16 AA15 AB13 AA13 AC14 AD14 AA12 AA11 AC16 32 www.xilinx.4) September 30.

SX25. and FX12 Devices 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 B15 B14 A12 A11 C15 C14 B13 B12 A16 A15 A10 B10 B17 A17 C13 C12 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 AF12 AE12 AC10 AB10 AB17 AC17 AF11 AF10 AE14 AE13 AE10 AD10 AD17 AD16 AD12 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. LX25. LX60. LX40.4) September 30.com 33 .xilinx. SX35. and FX12 Devices (Continued) Bank 2 2 2 Pin Description IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 Pin Number AC15 AC13 AD13 No Connects in LX15. SX25. 2005 www.

LX40. LX60.4) September 30. SX35. SX25. and FX12 Devices 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_5 IO_L1N_5 IO_L2P_5 IO_L2N_5 IO_L3P_5 IO_L3N_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_5 IO_L5N_5 IO_L6P_5 IO_L6N_5 IO_L7P_5 IO_L7N_5 IO_L8P_CC_LC_5 IO_L8N_CC_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 C17 D17 C20 B20 B18 A18 D20 D19 E17 F17 C21 B21 C19 D18 A24 A23 G19 F19 E23 E22 F20 E20 C26 C25 D23 C23 H20 G20 G22 G21 F24 F23 G18 G17 34 www. 2005 .R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. LX25. and FX12 Devices (Continued) Bank 4 Pin Description IO_L8N_GC_CC_LC_4 Pin Number AD11 No Connects in LX15.xilinx. SX25.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

and FX12 Devices 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 D10 C10 D9 C8 A8 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. and FX12 Devices (Continued) Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number B24 B23 F18 E18 E21 D21 A20 A19 D22 C22 A22 A21 D24 C24 D26 D25 H22 H21 E25 E24 G24 G23 F26 E26 H24 H23 G26 G25 H26 H25 No Connects in LX15.xilinx. SX35. SX25. 2005 www. LX25. LX60.com 35 .4) September 30. LX40. SX25.

2005 . LX60. LX40. and FX12 Devices (Continued) Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 Pin Number A7 D8 D7 F10 E10 A6 A5 E9 F9 B6 C6 E7 D6 E6 E5 F7 G7 C2 C1 H8 H7 D3 E4 G6 G5 E3 E2 G10 G9 F8 G8 B7 C7 C5 D5 A9 No Connects in LX15. and FX12 Devices 36 www.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. SX25. SX25.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. SX35. LX25.xilinx.

com 37 . LX25.4) September 30.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. LX60. and FX12 Devices 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (1) IO_L25N_CC_SM7_LC_7 (1) IO_L26P_SM6_7 (1) IO_L26N_SM6_7 (1) IO_L27P_SM5_7 (1) IO_L27N_SM5_7 IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 IO_L29N_SM4_7 IO_L30P_SM3_7 IO_L30N_SM3_7 (1) (1) (1) (1) (1) AD19 AC19 AA19 AA20 Y17 AA17 AB20 AC20 AC18 AB18 AF21 AF22 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 Virtex-4 Packaging and Pinout Specification UG075 (v2. SX25.xilinx. SX35. SX25. 2005 www. and FX12 Devices (Continued) Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number B9 A3 B3 A4 B4 C4 D4 D2 D1 E1 F1 F4 F3 G4 G3 H6 H5 G2 G1 H4 H3 H2 H1 No Connects in LX15. LX40.

and FX12 Devices (Continued) Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L31P_SM2_7 (1) IO_L31N_SM2_7 IO_L32P_SM1_7 IO_L32N_SM1_7 IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 (1) (1) (1) Pin Number AF18 AE18 AE21 AD21 AF19 AF20 Y19 W19 AF23 AE23 Y20 Y21 AA18 Y18 AF24 AE24 AE20 AD20 AC21 AB21 V21 V22 W25 W26 W21 W22 W23 W24 W20 V20 Y25 Y26 AB24 AB25 AA24 Y24 No Connects in LX15. and FX12 Devices See footnote #1 See footnote #1 See footnote #1 See footnote #1 38 www.xilinx. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX25. LX40. SX25. LX60. SX25. SX35.

SX35. and FX12 Devices (Continued) Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AC25 AC26 AB26 AA26 AD25 AD26 Y22 Y23 AC22 AB22 AB23 AA23 AD22 AD23 AC23 AC24 No Connects in LX15.com 39 .xilinx.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. SX25. and FX12 Devices 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 AF8 AF7 AA8 Y8 Y10 AA10 AC7 AB7 AC9 AB9 AE6 AD6 AF9 AE9 AD8 AC8 AF4 AE4 AD3 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. SX25. 2005 www. LX40. LX60. LX25.

SX25. LX25. 2005 . LX60. and FX12 Devices (Continued) Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Pin Description IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 Pin Number AC3 AF6 AF5 AA7 Y7 AA9 Y9 AD5 AD4 AE7 AD7 AC6 AB6 W2 W1 V6 V5 W7 V7 W4 W3 W6 W5 Y2 Y1 AA4 AA3 Y4 Y3 Y6 Y5 AB1 AA1 AC4 AB4 AB3 No Connects in LX15.4) September 30.xilinx. LX40. SX25. and FX12 Devices 40 www.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. SX35.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

SX35.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. 2005 www. SX25. and FX12 Devices (Continued) Bank 8 8 8 8 8 8 8 8 8 Pin Description IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AB2 AC5 AB5 AC2 AC1 AF3 AE3 AD2 AD1 No Connects in LX15. and FX12 Devices 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 N21 N20 P25 P24 P23 P22 R26 R25 P20 P19 R24 R23 R22 R21 T24 T23 J21 J20 J23 J22 K22 K21 J26 J25 L19 K20 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx. SX25. LX25. LX40. LX60.com 41 .

xilinx. 2005 . and FX12 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 42 www. LX40. SX25.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. SX25. SX35. and FX12 Devices (Continued) Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Pin Description IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 Pin Number L21 L20 K24 K23 K26 K25 M19 N19 L24 L23 M25 M24 L26 M26 M21 M20 M23 M22 N25 N24 N23 N22 R20 R19 T26 U26 U23 V23 U25 U24 U22 U21 T21 T20 U20 T19 No Connects in LX15.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. LX25.

LX25. and FX12 Devices (Continued) Bank 9 9 Pin Description IO_L32P_9 IO_L32N_9 Pin Number V26 V25 No Connects in LX15. LX60. SX25. SX35. LX40.xilinx.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. SX25. 2005 www.4) September 30.com 43 . and FX12 Devices NC NC 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 N7 M7 P5 P4 P8 N8 R4 R3 P7 P6 R2 R1 R6 R5 U1 T1 J7 J6 J5 J4 K7 K6 J2 J1 L7 L6 K5 K4 K3 K2 L4 L3 M8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx. LX25. 2005 . SX25. SX25. LX60. and FX12 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 0 0 1 1 VCCO_0 (2) VCCO_0 (2) V12 J15 E11 E16 See footnote #2 See footnote #2 VCCO_1 VCCO_1 44 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. SX35.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. LX40. and FX12 Devices (Continued) Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Pin Description IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10 Pin Number L8 L1 K1 M2 M1 M4 M3 M6 M5 N3 N2 N5 N4 P3 P2 R8 R7 T4 T3 T7 T6 U3 U2 V4 U4 V2 V1 T8 U7 U6 U5 No Connects in LX15.4) September 30.

4) September 30. SX35.com 45 . LX40. SX25.xilinx. LX25. and FX12 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. 2005 www.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. SX25. and FX12 Devices (Continued) Bank 2 2 3 3 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 8 8 8 8 8 8 Pin Description VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 Pin Number AB11 AB16 B11 B16 AE11 AD15 H18 B19 E19 H19 J19 B22 F22 F25 F2 B5 F5 B8 E8 J8 H9 H10 W17 W18 V19 AB19 AE19 AA22 AE22 AA25 AA2 AA5 AE5 V8 W8 AB8 No Connects in LX15.

R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15.xilinx. SX25. SX25. LX40.4) September 30. 2005 . and FX12 Devices (Continued) Bank 8 8 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 Pin Description VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 Pin Number AE8 W9 M18 K19 U19 L22 T22 L25 T25 P26 N1 L2 T2 L5 T5 K8 U8 R9 No Connects in LX15. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. SX35. LX25. and FX12 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A N/A N/A VREFN_SM (3) VREFP_SM AVDD_SM VN_SM VP_SM (3) (4) AE15 AE16 AF17 AF15 AF16 AE17 NC NC NC NC NC NC (3) (3) AVSS_SM (3) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND B1 P1 AE1 A2 B2 AE2 AF2 C3 J3 V3 46 www.

2005 www. SX35.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. and FX12 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number F6 N6 AA6 C9 AD9 M10 N10 P10 R10 K11 M11 N11 P11 R11 U11 E12 K12 L12 N12 P12 T12 U12 AB12 A13 J13 K13 L13 M13 N13 P13 R13 T13 U13 V13 AF13 A14 No Connects in LX15. LX25.4) September 30. SX25. and FX12 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.com 47 . LX40. LX60.xilinx. SX25.

SX35. and FX12 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number J14 K14 L14 M14 N14 P14 R14 T14 U14 V14 AF14 E15 K15 L15 N15 P15 T15 U15 AB15 K16 M16 N16 P16 R16 U16 M17 N17 P17 R17 C18 AD18 F21 P21 AA21 J24 V24 No Connects in LX15. SX25. LX25. SX25. 2005 .R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. and FX12 Devices 48 www. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX40.xilinx.4) September 30.

LX60. SX25. and FX12 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT M9 N9 P9 W10 H11 W11 J12 V15 H16 W16 H17 N18 P18 R18 K9 L9 T9 U9 J10 K10 L10 T10 U10 V10 J11 L11 T11 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. LX40. SX35.4) September 30. LX25.FF668 Flip-Chip Fine-Pitch BGA Package R Table 2-2: FF668 Package — LX15. and FX12 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND Pin Number AD24 A25 B25 AE25 AF25 B26 N26 AE26 No Connects in LX15.com 49 . 2005 www. SX25.

xilinx. and FX12 Devices 50 www. and FX12 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: 1. and FX12 devices. Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number V11 M12 R12 M15 R15 J16 L16 T16 V16 J17 K17 L17 T17 U17 V17 K18 L18 T18 U18 No Connects in LX15.5V (sharing the same PCB supply distribution as VCCAUX is acceptable).4) September 30. 2.R Chapter 2: Pinout Tables Table 2-2: FF668 Package — LX15. 4. 2005 . Connect this reserved pin to GND. LX40. SX25. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. SX25. 3. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. and SX35 devices. LX60. SM functionality is not available in LX15. Connect this reserved pin to 2. SX35.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX40. SX25. LX60. LX25. For LX25.

visit www.com and check for any updates to this document. Table 2-3: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF672 Package — FX60.com 51 . and XC4VFX20 devices are available in the FF672 flip-chip fine-pitch BGA package. To be assured of having the very latest Virtex-4 pinout information.xilinx. and FX20 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number K16 M14 L13 K17 L15 M12 K15 R11 L17 M16 U12 T10 P14 R13 U10 R15 T14 U11 E12 F12 No Connects in FX20 Devices 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 J15 J14 K13 J13 H14 G14 H13 H12 J16 Virtex-4 Packaging and Pinout Specification UG075 (v2. Virtex-4 XC4VFX60. ASCII package pinout files are also available for download from the Xilinx website. The “No Connect” column in Table 2-3 shows pins that are not available in FX20 devices. 2005 www.xilinx.4) September 30. XC4VFX40. FX40.FF672 Flip-Chip Fine-Pitch BGA Package R FF672 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-3.

R Chapter 2: Pinout Tables Table 2-3: Bank 1 1 1 1 1 1 1 FF672 Package — FX60.4) September 30.xilinx. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2. FX40. and FX20 Devices (Continued) Pin Description IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 Pin Number H16 K12 K11 G16 G15 H11 J11 No Connects in FX20 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 V16 W16 Y12 Y11 U16 U15 W11 V11 W15 W14 Y13 W13 U14 V14 V13 V12 3 3 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 F15 E15 F14 F13 D15 D14 D13 E13 C14 B14 C13 C12 52 www.

FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank 3 3 3 3 FF672 Package — FX60. 2005 www.xilinx.4) September 30.com 53 . FX40. and FX20 Devices (Continued) Pin Description IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number A14 A13 A12 B12 No Connects in FX20 Devices 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 AE15 AF15 AF14 AF13 AD15 AD14 AE13 AD13 AB14 AC14 AC13 AC12 AA14 AA13 AB12 AA12 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 IO_L2P_ADC6_5 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 (1) IO_L5N_ADC4_5 (1) IO_L6P_ADC3_5 (1) IO_L6N_ADC3_5 (1) IO_L7P_ADC2_5 (1) IO_L7N_ADC2_5 (1) IO_L8P_CC_ADC1_LC_5 (1) (1) (1) (1) (1) (1) G20 F20 H19 J19 E22 E21 G19 H18 G21 F22 F19 F18 E23 D23 E20 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 Virtex-4 Packaging and Pinout Specification UG075 (v2.

and FX20 Devices (Continued) Pin Description IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 (1) Pin Number D20 K20 L19 E17 F17 J23 K23 D18 E18 K21 J21 C18 C17 J24 H23 A17 B17 D24 C24 D21 C21 F24 F23 C23 C22 H22 G22 G17 H17 H24 G24 C19 D19 K22 L23 L18 K18 L24 No Connects in FX20 Devices See footnote #1 54 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx. FX40. 2005 .R Chapter 2: Pinout Tables Table 2-3: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF672 Package — FX60.

FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank 5 5 5 5 5 5 5 5 5 5 5 FF672 Package — FX60. 2005 www.xilinx. FX40.4) September 30. and FX20 Devices (Continued) Pin Description IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number M24 D16 E16 M22 N22 B16 C16 N24 N23 A15 B15 No Connects in FX20 Devices 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 H8 H7 A8 A7 F8 F7 G7 H6 E8 E7 B7 C7 D8 C8 D6 E6 B9 A9 C3 D3 G10 F10 E3 F3 E10 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 55 .

4) September 30.xilinx. and FX20 Devices (Continued) Pin Description IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 Pin Number D10 K6 J5 B10 A10 H4 G4 J9 K10 B6 C6 H9 G9 D5 E5 D9 C9 C4 D4 K8 K7 G5 F4 E11 D11 L7 M6 C11 B11 J4 H3 G12 G11 K3 J3 L10 L9 M5 No Connects in FX20 Devices 56 www. 2005 . FX40.R Chapter 2: Pinout Tables Table 2-3: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF672 Package — FX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

and FX20 Devices (Continued) Pin Description IO_L32N_6 Pin Number L5 No Connects in FX20 Devices 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 (2) IO_L26P_SM6_7 (2) IO_L26N_SM6_7 (2) IO_L27P_SM5_7 (2) IO_L27N_SM5_7 (2) IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 IO_L29N_SM4_7 IO_L30P_SM3_7 IO_L30N_SM3_7 IO_L31P_SM2_7 IO_L31N_SM2_7 IO_L32P_SM1_7 IO_L32N_SM1_7 IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 (2) (2) (2) (2) (2) (2) (2) (2) AB24 AC24 AB20 AB19 W20 W19 W18 V18 AD24 AD23 AA20 AA19 AC23 AC22 AB22 AB21 V21 U21 AC19 AC18 AA24 AA23 AA18 Y18 Y22 AA22 AD20 AD19 W21 Y20 AC21 AD21 P24 R23 AB15 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank 6 FF672 Package — FX60.xilinx. FX40.com 57 .

and FX20 Devices (Continued) Pin Description IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AA15 R21 R20 AD16 AC16 T23 T22 T17 U17 U24 T24 Y16 Y15 W24 V24 AB17 AB16 V23 V22 U19 T18 W23 Y23 AA17 Y17 U20 T20 AD18 AC17 No Connects in FX20 Devices 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 AC7 AC6 Y6 AA5 Y8 AA8 AB5 58 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-3: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF672 Package — FX60. FX40.xilinx.

com 59 . 2005 www.FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF672 Package — FX60. and FX20 Devices (Continued) Pin Description IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 Pin Number AB4 AB7 AB6 AD4 AD3 AA7 Y7 AD6 AD5 AD9 AD8 Y3 W4 AC9 AC8 AA4 AA3 AA9 AB9 Y5 W5 W9 W8 AC4 AC3 AD11 AD10 L4 L3 AB11 AC11 M4 N4 T9 T8 P5 R5 AA10 No Connects in FX20 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. FX40.4) September 30.xilinx.

FX40. 2005 .R Chapter 2: Pinout Tables Table 2-3: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF672 Package — FX60.xilinx.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX20 Devices (Continued) Pin Description IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AB10 P4 R3 W10 Y10 N3 P3 U6 U5 T4 T3 U7 V6 U4 V4 U9 V8 V3 W3 No Connects in FX20 Devices 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 M20 M19 P16 N16 N21 M21 N18 N17 P19 N19 R17 R16 P21 P20 R18 P18 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 60 www.

FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 FF672 Package — FX60. FX40.4) September 30. and FX20 Devices (Continued) Pin Description IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 Pin Number M10 M9 N8 N7 M11 N11 P8 R8 P11 P10 P6 N6 N9 P9 R7 R6 No Connects in FX20 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 0 0 0 0 1 1 2 2 3 3 4 4 5 5 5 5 5 5 5 5 VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 T11 M13 R14 L16 J12 H15 V15 W12 B13 E14 AB13 AE14 A16 D17 G18 K19 C20 F21 J22 M23 See footnote #3 See footnote #3 See footnote #3 See footnote #3 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.com 61 .

FX40.R Chapter 2: Pinout Tables Table 2-3: Bank 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 9 9 10 10 FF672 Package — FX60.4) September 30. 2005 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX20 Devices (Continued) Pin Description VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_10 VCCO_10 Pin Number E24 E4 H5 A6 L6 D7 G8 K9 C10 F11 AA16 AD17 U18 Y19 AC20 T21 W22 AB23 R24 M3 AB3 R4 V5 AA6 AD7 U8 Y9 AC10 P17 N20 P7 N10 No Connects in FX20 Devices NC NC NC NC N/A N/A N/A N/A AVCCAUXRXA_102 RXPPADA_102 VTRXA_102 RXNPADA_102 B20 A19 A21 A20 62 www.

and FX20 Devices (Continued) Pin Description AVCCAUXMGT_102 AVCCAUXTX_102 VTTXA_102 TXPPADA_102 TXNPADA_102 VTTXB_102 TXPPADB_102 TXNPADB_102 RXPPADB_102 VTRXB_102 AVCCAUXRXB_102 RXNPADB_102 MGTCLK_P_102 MGTCLK_N_102 AVCCAUXRXA_103 RXPPADA_103 VTRXA_103 RXNPADA_103 AVCCAUXTX_103 VTTXA_103 TXPPADA_103 TXNPADA_103 VTTXB_103 TXPPADB_103 AVCCAUXMGT_103 TXNPADB_103 RXPPADB_103 VTRXB_103 AVCCAUXRXB_103 RXNPADB_103 AVCCAUXRXA_105 RXPPADA_105 VTRXA_105 RXNPADA_105 AVCCAUXMGT_105 AVCCAUXTX_105 VTTXA_105 TXPPADA_105 Pin Number C25 B23 B22 A22 A23 B24 A24 A25 C26 B26 D25 D26 F26 G26 K25 J26 L26 K26 P25 M25 M26 N26 R25 P26 U25 R26 U26 T26 V25 V26 Y25 W26 AA26 Y26 AE24 AC25 AB25 AB26 No Connects in FX20 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2. FX40.FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF672 Package — FX60. 2005 www.com 63 .xilinx.4) September 30.

xilinx. FX40.4) September 30. and FX20 Devices (Continued) Pin Description TXNPADA_105 VTTXB_105 TXPPADB_105 TXNPADB_105 AVCCAUXRXB_105 RXPPADB_105 VTRXB_105 RXNPADB_105 MGTCLK_P_105 MGTCLK_N_105 RTERM_105 MGTVREF_105 AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 MGTCLK_N_110 RTERM_110 MGTVREF_110 AVCCAUXRXA_112 RXPPADA_112 VTRXA_112 RXNPADA_112 AVCCAUXMGT_112 AVCCAUXTX_112 Pin Number AC26 AD25 AD26 AE26 AE23 AF24 AF25 AF23 AF21 AF20 AE21 AE19 AD2 AC1 AE1 AD1 AE7 AE4 AE2 AF2 AF3 AE5 AF4 AF5 AE8 AF7 AF6 AF8 AF10 AF11 AE10 AE12 P2 N1 R1 P1 AA2 V2 No Connects in FX20 Devices NC NC NC NC NC NC 64 www. 2005 .R Chapter 2: Pinout Tables Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF672 Package — FX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 www.xilinx. and FX20 Devices (Continued) Pin Description VTTXA_112 TXPPADA_112 TXNPADA_112 VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 AVCCAUXRXA_113 RXPPADA_113 VTRXA_113 RXNPADA_113 AVCCAUXMGT_113 AVCCAUXTX_113 VTTXA_113 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 Pin Number T2 T1 U1 W2 V1 W1 AB2 AA1 Y1 AB1 B4 A4 A2 A3 G2 D2 C2 B1 C1 E2 D1 E1 H2 G1 F1 H1 K1 L1 No Connects in FX20 Devices NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A N/A N/A N/A N/A GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 A18 B19 B21 B25 E25 H25 E26 H26 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 65 . FX40.4) September 30.FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF672 Package — FX60.

R Chapter 2: Pinout Tables Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF672 Package — FX60.4) September 30. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. FX40. and FX20 Devices (Continued) Pin Description GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 Pin Number J25 L25 N25 T25 AF19 AE20 AE22 AF22 W25 AA25 AE25 AC2 AE3 AE6 AE9 AF9 AE11 AF12 N2 R2 U2 Y2 J1 M1 B2 F2 J2 K2 L2 M2 B3 A5 B5 No Connects in FX20 Devices N/A N/A N/A VREFN_SM (4) VREFP_SM (4) AVDD_SM (5) AE18 AE17 AE16 NC NC NC 66 www.

4) September 30.FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank N/A N/A N/A FF672 Package — FX60. FX40. and FX20 Devices (Continued) Pin Description VN_SM VP_SM (4) (4) (4) Pin Number AF18 AF17 AF16 No Connects in FX20 Devices NC NC NC AVSS_SM N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G3 U3 K4 Y4 C5 N5 AC5 F6 T6 J7 W7 B8 M8 AB8 E9 R9 H10 V10 A11 L11 AA11 D12 P12 T12 AD12 G13 N13 U13 K14 Y14 C15 N15 AC15 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 67 . 2005 www.xilinx.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. and FX20 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number F16 T16 J17 W17 B18 M18 AB18 E19 R19 H20 V20 L21 AA21 D22 P22 AD22 G23 U23 K24 Y24 No Connects in FX20 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT F5 T5 J6 W6 M7 N12 P15 H21 L22 P23 F25 G25 K5 G6 T7 V7 68 www. FX40.R Chapter 2: Pinout Tables Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF672 Package — FX60.xilinx. 2005 .

2005 www. and FX20 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number J8 L8 F9 V9 J10 R10 L12 R12 P13 T13 L14 N14 M15 T15 M17 V17 J18 T19 V19 J20 L20 Y21 R22 U22 No Connects in FX20 Devices 1. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. Connect this reserved pin to GND. Virtex-4 Packaging and Pinout Specification UG075 (v2. Connect this reserved pin to 2. 2. For FX60 devices. For FX40 and FX60 devices. 4.com 69 .FF672 Flip-Chip Fine-Pitch BGA Package R Table 2-3: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF672 Package — FX60. 5. ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). SM functionality is not available in FX20 devices.4) September 30. ADC functionality is not available in FX20 and FX40 devices. 3. FX40.xilinx.

The “No Connect” column in Table 2-4 shows pins that are not available in LX15 devices.xilinx.R Chapter 2: Pinout Tables FF676 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-4.4) September 30. ASCII package pinout files are also available for download from the Xilinx website.xilinx. Virtex-4 XC4VLX15 and XC4VLX25 devices are available in the FF676 flip-chip fine-pitch BGA package. visit www.com and check for any updates to this document. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2. To be assured of having the very latest Virtex-4 pinout information. Table 2-4: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF676 Package — LX15 and LX25 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number K16 M14 L13 K17 K15 M12 L15 R11 L17 M16 U12 T10 P14 R13 U10 R15 T14 U11 F12 E12 No Connects in LX15 Devices 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 J14 H14 J13 H13 J16 J15 K13 K12 G15 70 www.

com 71 .xilinx.FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank 1 1 1 1 1 1 1 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 Pin Number G14 H12 H11 H16 G16 J11 K11 No Connects in LX15 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 U16 V16 Y11 W11 W16 W15 V12 V11 U15 U14 Y13 Y12 V14 W14 W13 V13 3 3 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 A14 B14 C13 D13 D14 C14 E13 F13 E15 D15 B12 C12 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

R Chapter 2: Pinout Tables Table 2-4: Bank 3 3 3 3 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number F15 F14 A13 A12 No Connects in LX15 Devices 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 AA14 AA13 AB12 AA12 AB14 AC14 AC13 AC12 AD15 AD14 AD13 AE13 AE15 AF15 AF14 AF13 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_5 IO_L1N_5 IO_L2P_5 IO_L2N_5 IO_L3P_5 IO_L3N_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_5 IO_L5N_5 IO_L6P_5 IO_L6N_5 IO_L7P_5 IO_L7N_5 IO_L8P_CC_LC_5 B15 A15 C16 B16 D16 C17 H17 G17 B17 A17 E17 F17 A18 A19 C18 72 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .4) September 30.

FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L8N_CC_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 Pin Number C19 G19 G20 A22 A23 B22 C22 J20 K20 K18 L19 E22 F22 E23 F23 C23 D23 D18 D19 F18 E18 B19 A20 H18 J19 B20 B21 D20 C21 D21 E21 E20 F20 A24 B24 C24 D24 No Connects in LX15 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.4) September 30.xilinx.com 73 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-4: Bank 5 5 5 5 5 5 5 5 5 5 5 5 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number A25 B25 G21 G22 B26 C26 D25 D26 E25 E26 F24 F25 No Connects in LX15 Devices 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 G11 F10 E11 E10 D11 D10 G9 H9 C11 B11 B10 A10 A9 A8 C9 B9 F8 E7 B4 C4 E6 F7 J8 K8 74 www.

4) September 30.xilinx.com 75 . 2005 www.FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 Pin Number E5 D5 A2 B1 G7 G6 C3 C2 D9 C8 A7 B7 C7 B6 J9 H8 A5 B5 D8 E8 A4 A3 C6 D6 D4 D3 F5 F4 B2 C1 K10 L9 E3 F3 H6 G5 G4 No Connects in LX15 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 .xilinx.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-4: Bank 6 6 6 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number H4 J6 J5 No Connects in LX15 Devices 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (1) IO_L25N_CC_SM7_LC_7 (1) IO_L26P_SM6_7 (1) IO_L26N_SM6_7 (1) IO_L27P_SM5_7 IO_L27N_SM5_7 IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 IO_L29N_SM4_7 IO_L30P_SM3_7 IO_L30N_SM3_7 IO_L31P_SM2_7 IO_L31N_SM2_7 (1) (1) (1) (1) (1) (1) (1) (1) AB16 AA17 AF20 AE20 Y16 Y17 V17 U17 AB17 AA18 AD18 AD19 AC16 AD16 AC17 AC18 AF22 AF23 AA20 AB21 Y18 AA19 W18 V18 AE21 AE22 AD20 AD21 AA15 AB15 AC19 AB19 V21 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L32P_SM1_7 (1) IO_L32N_SM1_7 (1) IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 76 www.

com 77 .xilinx.FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number V22 Y23 W23 AA23 AA24 T18 T19 Y22 W21 AE25 AD25 AE26 AD26 AC24 AB24 AC23 AD24 AF24 AF25 AC22 AB22 V19 U19 W19 Y20 Y21 AA22 AE23 AD23 AB20 AC21 No Connects in LX15 Devices 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 AF8 AE8 AD10 AD9 AE10 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.4) September 30.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-4: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF676 Package — LX15 and LX25 Devices (Continued) Pin Description IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 Pin Number AF9 W10 Y10 AA10 AB10 AE11 AF10 AE12 AF12 AC11 AD11 AC6 AB6 AE6 AD6 AB7 AA7 W9 V8 AC8 AC7 AF7 AE7 AB9 AA9 AC9 AD8 AB1 AA2 AB2 AA3 AC2 AC1 V7 U7 AA4 Y5 No Connects in LX15 Devices 78 www. 2005 .4) September 30.xilinx.

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Table 2-4: Bank
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8

Pin Number
Y6 AA5 AB4 AC3 AE1 AD1 AF3 AF4 AB5 AC4 AD3 AE2 U9 T8 AE3 AF2 AD5 AD4 Y8 Y7 AF5 AE5

No Connects in LX15 Devices

9 9 9 9 9 9 9 9 9 9 9 9 9 9

IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9

N24 P23 P24 P25 R26 P26 R20 R21 R22 R23 T25 R25 T23 T24

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-4: Bank
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9

Pin Number
U22 T22 J21 K21 H22 H23 G24 G25 M20 M21 J23 K22 J24 H24 K23 L23 J25 J26 G26 H26 M22 N21 K25 K26 L24 M24 N22 N23 M26 N26 L26 M25 P20 P21 U24 U25 V26

No Connects in LX15 Devices
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-4: Bank
9 9 9 9 9 9 9 9 9 9 9 9 9

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9

Pin Number
U26 W24 V24 U21 T20 W25 W26 Y25 Y26 AB25 AA25 AC26 AB26

No Connects in LX15 Devices
NC NC NC NC NC NC NC NC NC NC NC NC NC

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10

R2 P3 N4 P4 R1 P1 P6 P5 T2 R3 U4 T3 T4 R5 U2 U1 D1 E1 H3 J3 G2 G1 K6

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-4: Bank
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10

Pin Number
L7 H2 H1 E2 F2 K5 L5 K3 K2 J1 K1 L4 L3 M5 M4 M7 M6 L2 M1 N3 N2 M2 N1 N7 N6 V2 V1 Y1 W1 U6 U5 R7 R6 W3 V3 W4 V4

No Connects in LX15 Devices
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-4: Bank
10 10 10 10

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10

Pin Number
Y3 Y2 V6 W5

No Connects in LX15 Devices
NC NC NC NC

0 0 0 0 1 1 2 2 3 3 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7

VCCO_0 (2) VCCO_0 (2) VCCO_0 (2) VCCO_0
(2)

T11 M13 R14 L16 J12 H15 V15 W12 B13 E14 AB13 AE14 A16 D17 G18 K19 C20 F21 B23 E24 A26 B3 E4 H5 A6 D7 G8 K9 C10 F11 AA16 AD17

See footnote #2 See footnote #2 See footnote #2 See footnote #2

VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7

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Table 2-4: Bank
7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10

FF676 Package — LX15 and LX25 Devices (Continued) Pin Description
VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10

Pin Number
U18 Y19 AC20 AF21 W22 AB23 AE24 AF1 AB3 AE4 AA6 AD7 U8 Y9 AC10 AF11 N20 T21 J22 M23 R24 H25 L25 V25 AA26 F1 T1 J2 W2 M3 R4 V5 L6 P7

No Connects in LX15 Devices

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

N/A N/A

VREFN_SM (3) VREFP_SM (3)

AE18 AE17

NC (See footnote #3) NC (See footnote #3)

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2005 www.xilinx.4) September 30.com 85 .FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank N/A N/A N/A N/A FF676 Package — LX15 and LX25 Devices (Continued) Pin Description AVDD_SM (4) VN_SM VP_SM (3) (3) (3) Pin Number AE16 AF18 AF17 AF16 No Connects in LX15 Devices NC (See footnote #4) NC (See footnote #3) NC (See footnote #3) NC (See footnote #3) AVSS_SM N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A1 L1 AA1 D2 P2 AD2 G3 U3 K4 Y4 C5 N5 AC5 F6 T6 AF6 J7 W7 B8 M8 P8 AB8 E9 N9 R9 AE9 H10 M10 P10 V10 A11 L11 Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-4: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF676 Package — LX15 and LX25 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number N11 AA11 D12 P12 T12 AD12 G13 N13 U13 K14 Y14 C15 N15 AC15 F16 P16 T16 J17 N17 R17 W17 B18 M18 P18 AB18 E19 N19 R19 AE19 H20 V20 A21 L21 AA21 D22 P22 AD22 No Connects in LX15 Devices 86 www.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

com 87 . 2005 www.xilinx.FF676 Flip-Chip Fine-Pitch BGA Package R Table 2-4: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF676 Package — LX15 and LX25 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND Pin Number G23 U23 K24 Y24 C25 N25 AC25 F26 T26 AF26 No Connects in LX15 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT J4 T5 W6 H7 AA8 P9 G12 N12 P15 N18 F19 AF19 W20 H21 L22 V23 K7 T7 L8 N8 R8 W8 F9 M9 T9 V9 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.

For LX25 devices.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide.4) September 30. 4. For LX25 devices.R Chapter 2: Pinout Tables Table 2-4: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF676 Package — LX15 and LX25 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number G10 J10 L10 N10 R10 M11 P11 AB11 L12 R12 P13 T13 L14 N14 M15 T15 Y15 E16 N16 R16 M17 P17 T17 J18 L18 R18 H19 M19 P19 L20 U20 No Connects in LX15 Devices 1. For LX25 devices.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). 2005 . 3. SM functionality is not available in LX15 devices. connect this reserved pin to GND. connect this reserved pin to 2. 2. 88 www.

visit www. LX80. LX60. Table 2-5: FF1148 Package — LX40.com and check for any updates to this document. the following Virtex-4 LX and SX devices are available in the FF1148 flip-chip fine-pitch BGA package: • • • • • • XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VSX55 Pinouts in the following devices are identical: • • LX40.4) September 30.FF1148 Flip-Chip Fine-Pitch BGA Package R FF1148 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-5.xilinx. 2005 www. LX60. and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. and SX55 LX80. and SX55 Devices Pin Number T18 R17 T16 U22 U21 U17 U15 U13 V22 V20 W21 V13 W20 V18 V14 W19 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 No Connects in LX40. LX100. LX60. ASCII package pinout files are also available for download from the Xilinx website. To be assured of having the very latest Virtex-4 pinout information.xilinx. and LX160 The “No Connect” column in Table 2-5 shows pins that are not available in LX40. LX100. LX60. and SX55 devices.com 89 . LX160.

LX60.4) September 30. LX160. and SX55 Devices (Continued) Bank 0 0 0 0 Pin Description DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number Y18 W17 F15 D15 No Connects in LX40. and SX55 Devices 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 IO_L9P_GC_LC_1 IO_L9N_GC_LC_1 IO_L10P_GC_LC_1 IO_L10N_GC_LC_1 IO_L11P_GC_LC_1 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 N19 N18 L15 L14 E21 D21 J14 K14 N20 M20 H14 H13 H22 J21 F13 G13 M18 L18 M17 N17 E19 D19 C17 D17 C19 C18 D16 C15 D20 C20 90 www. LX60. LX80.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX100. 2005 .

xilinx. LX100. LX60. LX80.com 91 . and SX55 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 AJ22 AJ21 AC15 AB15 AG22 AH22 AL14 AK14 AG21 AF20 AF14 AG13 AE21 AF21 AP15 AN15 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. LX160.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. 2005 www. and SX55 Devices (Continued) Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 IO_L23N_LC_1 IO_L24P_LC_1 IO_L24N_LC_1 Pin Number M16 N15 B20 A20 K16 L16 J20 L19 H15 J15 G21 H20 G15 F14 F21 F20 A15 B15 No Connects in LX40. LX60.

xilinx. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX60. LX160. LX100. and SX55 Devices 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 F18 G18 92 www. LX80. and SX55 Devices (Continued) Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L9P_GC_CC_LC_2 IO_L9N_GC_CC_LC_2 IO_L10P_GC_LC_2 IO_L10N_GC_LC_2 IO_L11P_GC_LC_2 IO_L11N_GC_LC_2 IO_L12P_GC_LC_2 IO_L12N_GC_VREF_LC_2 IO_L13P_GC_LC_2 IO_L13N_GC_LC_2 IO_L14P_GC_LC_2 IO_L14N_GC_LC_2 IO_L15P_GC_LC_2 IO_L15N_GC_LC_2 IO_L16P_GC_LC_2 IO_L16N_GC_LC_2 IO_L17P_LC_2 IO_L17N_LC_2 IO_L18P_LC_2 IO_L18N_LC_2 IO_L19P_LC_2 IO_L19N_LC_2 IO_L20P_LC_2 IO_L20N_VREF_LC_2 IO_L21P_LC_2 IO_L21N_LC_2 IO_L22P_LC_2 IO_L22N_LC_2 IO_L23P_VRN_LC_2 IO_L23N_VRP_LC_2 IO_L24P_CC_LC_2 IO_L24N_CC_LC_2 Pin Number AC19 AB18 AD16 AF15 AN20 AP20 AD17 AC17 AM20 AL19 AB17 AB16 AL18 AM18 AM17 AM16 AD21 AD20 AM15 AL15 AJ20 AL20 AJ15 AJ14 AG20 AH20 AG15 AH14 AD19 AE19 AL16 AK16 No Connects in LX40.

and SX55 Devices (Continued) Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number H17 J17 H19 H18 E18 E17 K18 K17 E16 F16 K19 J19 G17 G16 No Connects in LX40. LX60. LX100.xilinx. LX80.com 93 .4) September 30. LX160. and SX55 Devices 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 AF18 AE18 AG16 AF16 AH19 AH18 AK18 AK17 AG18 AG17 AE17 AE16 AJ19 AK19 AJ17 AH17 5 5 5 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 (1) IO_L2P_ADC6_5 (1) B23 A23 A26 See footnote #1 See footnote #1 See footnote #1 Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. 2005 www.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40.

R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40.xilinx. LX160. and SX55 Devices See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L8P_CC_ADC1_LC_5 (1) IO_L8N_CC_ADC1_LC_5 (1) IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 94 www. LX60. LX60. LX100. LX80. and SX55 Devices (Continued) Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L2N_ADC6_5 (1) IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 (1) IO_L5N_ADC4_5 (1) IO_L6P_ADC3_5 IO_L6N_ADC3_5 IO_L7P_ADC2_5 IO_L7N_ADC2_5 (1) (1) (1) (1) (1) (1) Pin Number B26 A24 A25 G25 H25 C23 C24 F25 F26 D24 D25 B27 C27 C22 B22 A30 B30 K24 J24 C29 C30 B21 A21 E28 F28 E22 D22 A31 B31 F23 E23 D26 E26 F24 E24 D27 No Connects in LX40.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .

com 95 . LX60.4) September 30.xilinx. 2005 www. LX80.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. and SX55 Devices 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 D12 C12 B10 C10 A11 B11 C9 C8 G12 Virtex-4 Packaging and Pinout Specification UG075 (v2. and SX55 Devices (Continued) Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number E27 G23 H24 A28 A29 B25 C25 J25 K26 B28 C28 D30 D31 G27 G28 F29 F30 D29 E29 L25 L26 B32 B33 E31 F31 No Connects in LX40. LX100. LX60. LX160.

and SX55 Devices 96 www. and SX55 Devices (Continued) Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 Pin Number G11 F10 G10 D11 D10 H10 H9 A14 A13 D7 D6 D9 E9 A4 A3 E13 E12 A5 B5 E8 E7 J9 K9 B13 B12 A8 B8 E11 F11 A6 B6 H12 J11 B7 C7 A10 No Connects in LX40.xilinx.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX60. LX100.4) September 30. 2005 . LX80. LX160.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60.

LX160. 2005 www. LX100. LX60. and SX55 Devices (Continued) Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number A9 F8 G8 C14 C13 E6 F6 C5 D5 G7 G6 E14 D14 B3 B2 H8 H7 K8 J7 No Connects in LX40.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40.xilinx. LX60. and SX55 Devices 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 (2) IO_L26P_SM6_7 (2) IO_L26N_SM6_7 (2) IO_L27P_SM5_7 (2) IO_L27N_SM5_7 (2) IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 (2) IO_L29N_SM4_7 (2) IO_L30P_SM3_7 (2) IO_L30N_SM3_7 (2) IO_L31P_SM2_7 (2) IO_L31N_SM2_7 (2) IO_L32P_SM1_7 (2) AL24 AL25 AL26 AK26 AN22 AN23 AJ25 AH25 AP24 AN24 AM26 AM27 AL23 AM23 AN25 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 97 .4) September 30. LX80.

LX80.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. and SX55 Devices (Continued) Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L32N_SM1_7 (2) IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 Pin Number AM25 AP21 AP22 AP29 AN29 AK24 AJ24 AK27 AK28 AG23 AF24 AG25 AG26 AH23 AH24 AN28 AM28 AK29 AJ29 AF28 AE27 AF26 AE26 AN32 AN33 AK21 AL21 AH28 AH29 AP30 AN30 AG27 AG28 AM21 AM22 AM30 No Connects in LX40.4) September 30.xilinx. and SX55 Devices See footnote #2 98 www. 2005 . LX160. LX60. LX100.

LX60. 2005 www. and SX55 Devices 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 AL11 AL10 AE11 AF11 AM12 AM11 AL9 AK9 AP11 AP10 AH10 AG10 AN12 AP12 AP9 AN9 AH12 AG11 AN7 AM7 AN10 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. and SX55 Devices (Continued) Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AL30 AP27 AN27 AP31 AP32 AK22 AK23 AL28 AL29 AP25 AP26 AJ27 AH27 No Connects in LX40.com 99 . LX160.4) September 30. LX80. LX100. LX60.xilinx.

LX60. LX100. and SX55 Devices 100 www. and SX55 Devices (Continued) Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Pin Description IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 Pin Number AM10 AF10 AE9 AJ12 AK12 AN8 AM8 AJ11 AK11 AP7 AP6 AL5 AL4 AK4 AJ4 AP4 AN4 AD10 AD9 AN14 AP14 AJ6 AJ5 AK7 AJ7 AN3 AN2 AK13 AL13 AL6 AK6 AL8 AK8 AH8 AH7 AM13 No Connects in LX40.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. LX160.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX60. LX80. 2005 .

LX60. and SX55 Devices (Continued) Bank 8 8 8 8 8 8 8 Pin Description IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AN13 AM6 AM5 AJ10 AJ9 AP5 AN5 No Connects in LX40.xilinx. LX100.4) September 30. LX60. LX80.com 101 . LX160. and SX55 Devices 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 P20 R19 L28 L29 P24 R24 H32 J32 M27 M28 H33 H34 J31 K31 L30 L31 H27 H28 C32 D32 J27 K27 M25 M26 N22 N23 H29 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. 2005 www.

LX60.xilinx. LX100.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and SX55 Devices 102 www. LX80.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX160.4) September 30. LX60. 2005 . and SX55 Devices (Continued) Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Pin Description IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 Pin Number H30 C33 C34 D34 E34 G30 G31 J29 J30 E32 E33 N25 P26 P22 R21 F33 F34 K28 K29 G32 G33 R22 R23 K32 K33 N27 P27 M30 M31 J34 K34 N29 N30 L33 L34 M32 No Connects in LX40.

LX80. LX160. LX60.4) September 30. and SX55 Devices (Continued) Bank 9 Pin Description IO_L32N_9 Pin Number M33 No Connects in LX40.xilinx.com 103 . 2005 www. LX100. LX60. and SX55 Devices 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 F1 G1 J4 K4 H3 H2 P10 P9 M7 N7 L5 L4 J2 J1 R11 T11 C4 C3 F5 G5 D4 E4 M10 L9 N13 N12 F4 F3 C2 D2 D1 E1 E3 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40.

LX60. LX80. and SX55 Devices (Continued) Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Pin Description IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10 Pin Number E2 J6 J5 H5 H4 N10 N9 P12 P11 G3 G2 L8 M8 K6 L6 K3 L3 K2 K1 M6 M5 M3 M2 L1 M1 N5 P5 P7 P6 T10 R9 No Connects in LX40.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX160.4) September 30.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. 2005 . and SX55 Devices 11 11 11 IO_L17P_11 IO_L17N_11 IO_L18P_11 AA23 AA24 AJ34 104 www. LX100.

LX60. LX160.4) September 30.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. LX100. and SX55 Devices (Continued) Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Pin Description IO_L18N_11 IO_L19P_11 IO_L19N_11 IO_L20P_11 IO_L20N_VREF_11 IO_L21P_11 IO_L21N_11 IO_L22P_11 IO_L22N_11 IO_L23P_VRN_11 IO_L23N_VRP_11 IO_L24P_CC_LC_11 IO_L24N_CC_LC_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11 IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 Pin Number AH34 AD27 AC27 AB25 AB26 AG30 AG31 AH32 AH33 AC25 AD26 AF29 AF30 AA28 AA29 W24 Y24 AB30 AA30 W25 Y26 AE33 AE34 AC32 AC33 AC29 AC30 AD34 AC34 AA25 AA26 AE32 AD32 AC28 AB28 AD30 No Connects in LX40. LX60.com 105 . and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.xilinx. LX80.

LX160. LX60. LX80. LX60.xilinx.4) September 30. 2005 . and SX55 Devices (Continued) Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Pin Description IO_L12N_VREF_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_11 IO_L15P_11 IO_L15N_11 IO_L16P_11 IO_L16N_11 IO_L25P_CC_LC_11 IO_L25N_CC_LC_11 IO_L26P_11 IO_L26N_11 IO_L27P_11 IO_L27N_11 IO_L28P_11 IO_L28N_VREF_11 IO_L29P_11 IO_L29N_11 IO_L30P_11 IO_L30N_11 IO_L31P_11 IO_L31N_11 IO_L32P_11 IO_L32N_11 Pin Number AD31 AG32 AG33 AF33 AF34 AE29 AD29 AF31 AE31 AK31 AK32 AK33 AK34 AM32 AM33 AJ31 AJ32 AB22 AB23 AL33 AL34 AM31 AL31 AJ30 AH30 No Connects in LX40.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX100. and SX55 Devices 12 12 12 12 12 12 12 12 12 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 AC9 AC8 AG3 AF3 AF6 AE6 AF5 AF4 AL1 106 www.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40.

FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. LX160. LX60. 2005 www.com 107 .4) September 30. and SX55 Devices (Continued) Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Pin Description IO_L21N_12 IO_L22P_12 IO_L22N_12 IO_L23P_VRN_12 IO_L23N_VRP_12 IO_L24P_CC_LC_12 IO_L24N_CC_LC_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 Pin Number AK1 AJ2 AJ1 AG6 AG5 AE7 AD7 AB6 AB5 AC3 AC2 Y11 AA11 AD2 AD1 Y14 AA13 AC5 AC4 AF1 AE1 AA9 AA8 Y13 Y12 AE3 AE2 AD6 AD5 AC7 AB8 Y16 AA15 AE4 AD4 AH3 No Connects in LX40. LX60. LX100.xilinx. and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. LX80.

2005 . LX60. and SX55 Devices (Continued) Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Pin Description IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 IO_L27P_12 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 Pin Number AH2 AG2 AG1 AC10 AB10 AK3 AK2 AF8 AE8 AH5 AH4 AB13 AB12 AM2 AM1 AG8 AG7 AM3 AL3 No Connects in LX40.xilinx. LX60. LX80.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. and SX55 Devices 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 V33 V34 U32 U33 V25 U25 V28 V29 V23 V24 W32 V32 Y34 W34 W30 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 108 www. LX160. LX100.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40.

com 109 .xilinx. LX80.4) September 30. LX100. LX160. and SX55 Devices (Continued) Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 Pin Description IO_L24N_CC_LC_13 IO_L1P_13 IO_L1N_13 IO_L2P_13 IO_L2N_13 IO_L3P_13 IO_L3N_13 IO_L4P_13 IO_L4N_VREF_13 IO_L5P_13 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 Pin Number V30 T23 U23 R26 T26 T24 T25 R27 R28 P29 R29 N32 P32 P30 P31 N33 N34 P34 R34 R31 T31 R32 R33 T28 U28 T29 T30 T33 T34 U26 U27 U30 U31 Y32 Y33 W27 No Connects in LX40. LX60. 2005 www. and SX55 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40.

com Virtex-4 Packaging and Pinout Specification UG075 (v2. and SX55 Devices (Continued) Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 Pin Description IO_L26N_13 IO_L27P_13 IO_L27N_13 IO_L28P_13 IO_L28N_VREF_13 IO_L29P_13 IO_L29N_13 IO_L30P_13 IO_L30N_13 IO_L31P_13 IO_L31N_13 IO_L32P_13 IO_L32N_13 Pin Number V27 Y29 W29 Y31 W31 AB32 AB33 AA33 AA34 AB31 AA31 Y27 Y28 No Connects in LX40. and SX55 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 V9 V8 V5 V4 W6 W5 W2 W1 V12 W12 W7 V7 Y4 W4 Y3 Y2 N4 P4 N3 N2 R8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 110 www.xilinx. LX80. LX60. LX160. LX60.4) September 30.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX100. 2005 .

xilinx. LX80. LX60. LX60. 2005 www. and SX55 Devices (Continued) Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Pin Description IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_LC_14 IO_L8N_CC_LC_14 IO_L9P_CC_LC_14 IO_L9N_CC_LC_14 IO_L10P_14 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 IO_L29P_14 Pin Number T8 R7 R6 P2 P1 R4 T4 R3 R2 R1 T1 T6 T5 T3 U3 U8 U7 U2 U1 U12 U11 U10 V10 U6 U5 V3 V2 AA5 AA4 AA1 Y1 AB3 AA3 AB2 AB1 AA6 No Connects in LX40.4) September 30. LX160.com 111 .FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. and SX55 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2. LX100.

4) September 30. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. LX160. and SX55 Devices NC NC NC NC NC NC NC 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 5 5 5 VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 U14 T17 W18 V21 G14 K15 C16 N16 B19 M19 E20 H21 AG14 AK15 AC16 AN16 AB19 AM19 AE20 AH21 F17 J18 AF17 AJ18 A22 D23 G24 See footnote #3 See footnote #3 See footnote #3 See footnote #3 112 www. LX100. and SX55 Devices (Continued) Bank 14 14 14 14 14 14 14 Pin Description IO_L29N_14 IO_L30P_14 IO_L30N_14 IO_L31P_14 IO_L31N_14 IO_L32P_14 IO_L32N_14 Pin Number Y6 Y8 Y7 Y9 W9 W11 W10 No Connects in LX40. LX60. LX80. 2005 .R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40.

xilinx. LX160. LX80. 2005 www.com 113 . LX60.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. LX100. LX60. and SX55 Devices (Continued) Bank 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 9 9 9 Pin Description VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 Pin Number K25 C26 F27 B29 E30 A32 A2 C6 F7 J8 B9 E10 H11 A12 D13 AL22 AP23 AG24 AK25 AN26 AF27 AJ28 AM29 AP33 AP3 AK5 AN6 AJ8 AM9 AE10 AH11 AL12 AP13 R20 P23 N26 No Connects in LX40.4) September 30. and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.

LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX100. 2005 . LX80. LX60. and SX55 Devices NC NC NC 114 www. LX160. and SX55 Devices (Continued) Bank 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 13 13 13 Pin Description VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 Pin Number J28 M29 H31 L32 D33 G34 H1 L2 D3 G4 K5 N6 M9 R10 P13 AA22 Y25 AC26 AB29 AE30 AH31 AL32 AD33 AG34 AH1 AL2 AD3 AG4 AC6 AF7 AB9 AA12 Y15 U24 T27 W28 No Connects in LX40.4) September 30.

LX60. and SX55 Devices (Continued) Bank 13 13 13 13 13 14 14 14 14 14 14 14 14 Pin Description VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 Pin Number R30 V31 AA32 P33 U34 V1 AA2 P3 U4 Y5 T7 W8 V11 No Connects in LX40.4) September 30. LX160. LX60. and SX55 Devices NC NC NC NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A N/A N/A VREFN_SM (4) VREFP_SM AVDD_SM VN_SM (4) (5) AN17 AN18 AP19 AP17 AP18 AN19 See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 (4) VP_SM (4) AVSS_SM (4) N/A N/A N/A N/A N/A N/A VREFN_ADC (4) VREFP_ADC AVDD_ADC (4) (5) B17 B18 B16 A17 A18 A16 NC NC NC NC NC NC VN_ADC (4) VP_ADC (4) AVSS_ADC (4) N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND B1 C1 N1 AC1 AN1 F2 T2 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. LX100.xilinx. 2005 www.com 115 . LX80.

and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AF2 AP2 J3 W3 AJ3 B4 M4 AB4 AM4 E5 R5 AE5 H6 V6 AH6 A7 L7 AA7 AL7 D8 P8 AD8 AP8 G9 U9 AG9 K10 Y10 AK10 C11 L11 N11 AC11 AN11 F12 K12 No Connects in LX40. and SX55 Devices 116 www. 2005 . LX60.xilinx.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX160. LX100. LX80.4) September 30. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. LX60. and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number M12 T12 AD12 AF12 J13 L13 R13 W13 AC13 AE13 AJ13 B14 M14 T14 AB14 AD14 AM14 E15 R15 W15 AE15 H16 P16 V16 AH16 AP16 L17 AA17 AL17 D18 P18 AD18 A19 G19 U19 AA19 No Connects in LX40.com 117 . and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. LX100.xilinx. LX80.4) September 30. LX160. 2005 www.

xilinx.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. LX160.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and SX55 Devices 118 www. LX80. LX60.4) September 30. 2005 . LX60. LX100. and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AG19 K20 T20 Y20 AB20 AK20 C21 L21 N21 AC21 AN21 F22 K22 M22 T22 Y22 AD22 AF22 J23 L23 W23 AC23 AE23 AJ23 B24 M24 AB24 AD24 AM24 E25 R25 AE25 H26 V26 AH26 A27 No Connects in LX40.

4) September 30. LX100.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40. and SX55 Devices N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX N8 F9 T9 AH9 J10 Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. LX80. 2005 www. LX60. and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L27 AA27 AL27 D28 P28 AD28 AP28 G29 U29 AG29 K30 Y30 AK30 C31 N31 AC31 AN31 F32 T32 AF32 A33 J33 W33 AJ33 B34 M34 AB34 AM34 AN34 No Connects in LX40. LX160.xilinx.com 119 .

and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AA10 M11 AD11 AG12 U16 AJ16 Y17 R18 F19 V19 H23 L24 AC24 P25 AF25 G26 W26 AJ26 AB27 K7 AB7 AF9 L10 K11 AB11 J12 L12 R12 AC12 AE12 K13 M13 T13 AD13 AF13 AH13 No Connects in LX40.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX80.xilinx.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40. and SX55 Devices 120 www. LX60. LX60. 2005 . LX100.4) September 30. LX160.

LX100.FF1148 Flip-Chip Fine-Pitch BGA Package R Table 2-5: FF1148 Package — LX40.com 121 . LX60. LX80. 2005 www. LX60. LX160. and SX55 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx. and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number N14 R14 W14 AC14 AE14 M15 P15 T15 V15 AD15 AH15 J16 R16 W16 AA16 P17 V17 U18 AA18 AC18 P19 T19 Y19 AF19 G20 L20 U20 AA20 AC20 K21 M21 T21 Y21 AB21 G22 J22 No Connects in LX40.

and SX55 devices.R Chapter 2: Pinout Tables Table 2-5: FF1148 Package — LX40.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). For LX80. and SX55 Devices (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: 1.xilinx. LX160. and SX55 Devices 122 www. Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number L22 W22 AC22 AE22 K23 M23 Y23 AD23 AF23 N24 AE24 AD25 J26 N28 AE28 No Connects in LX40. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. LX100. ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions. 2. LX60. 4. LX80. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. ADC functionality is not available in LX40. 5. 3. and LX160 devices. Connect this reserved pin to GND.4) September 30. LX100. LX60. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 . Connect this reserved pin to 2.

FF1152 Flip-Chip Fine-Pitch BGA Package R FF1152 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-6. visit www.com 123 . and XC4VFX100 devices are available in the FF1152 flip-chip fine-pitch BGA package. To be assured of having the very latest Virtex-4 pinout information. The “No Connect” columns in Table 2-6 show pins that are not available in FX60 and FX40 devices. 2005 www.4) September 30. FX60. Table 2-6: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF1152 Package — FX40. and FX100 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number P20 T18 R17 P21 P19 T16 R19 W15 R21 T20 AA16 Y14 V18 W17 AA14 W19 Y18 AA15 D17 C17 No Connects in FX60 Devices No Connects in FX40 Devices 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 G18 F18 H14 H13 G17 G16 G15 H15 Virtex-4 Packaging and Pinout Specification UG075 (v2.com and check for any updates to this document.xilinx. ASCII package pinout files are also available for download from the Xilinx website. XC4VFX60. Virtex-4 XC4VFX40.xilinx.

and FX100 Devices (Continued) Pin Description IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 Pin Number E18 E17 F15 F14 E16 F16 F13 G13 No Connects in FX60 Devices No Connects in FX40 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 AH22 AJ22 AK18 AK17 AG22 AG21 AH17 AJ17 AJ21 AJ20 AJ19 AK19 AG20 AH20 AH19 AH18 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 H17 J17 K16 L16 K18 K17 J16 J15 K19 J19 124 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-6: Bank 1 1 1 1 1 1 1 1 FF1152 Package — FX40.4) September 30.xilinx. FX60. 2005 .

FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 3 3 3 3 3 3 FF1152 Package — FX40. FX60.4) September 30. and FX100 Devices (Continued) Pin Description IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number J14 K14 H19 H18 L15 L14 No Connects in FX60 Devices No Connects in FX40 Devices 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 AD21 AD20 AF16 AE16 AE21 AF21 AE18 AE17 AF20 AF19 AG17 AG16 AD19 AE19 AF18 AG18 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 (1) IO_L2P_ADC6_5 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 (1) (1) (1) (1) (1) H24 J24 E23 F23 E24 F24 G23 H23 C24 D24 C23 C22 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L5N_ADC4_5 (1) IO_L6P_ADC3_5 (1) IO_L6N_ADC3_5 (1) Virtex-4 Packaging and Pinout Specification UG075 (v2.com 125 . 2005 www.xilinx.

and FX100 Devices (Continued) Pin Description IO_L7P_ADC2_5 (1) IO_L7N_ADC2_5 (1) (1) (1) Pin Number J25 H25 G22 H22 K26 J26 D21 E21 E27 D27 K23 L23 C28 C27 H20 J20 G28 G27 F20 G20 G25 F25 D22 E22 D25 C25 J22 K22 G26 F26 J21 K21 E26 D26 F21 G21 F28 No Connects in FX60 Devices See footnote #1 See footnote #1 See footnote #1 See footnote #1 No Connects in FX40 Devices See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L8P_CC_ADC1_LC_5 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 126 www.R Chapter 2: Pinout Tables Table 2-6: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1152 Package — FX40.4) September 30. FX60.xilinx. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

and FX100 Devices (Continued) Pin Description IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number E28 E19 F19 K24 L24 L21 M22 L26 L25 P22 N22 P24 N24 N23 M23 No Connects in FX60 Devices No Connects in FX40 Devices 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 G10 H10 D10 C10 F10 F9 H9 J9 F11 E11 D9 E9 D12 D11 C9 C8 J12 H12 E7 E6 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1152 Package — FX40.com 127 . 2005 www. FX60.xilinx.4) September 30.

2005 .4) September 30. and FX100 Devices (Continued) Pin Description IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 Pin Number E13 E12 K9 K8 E14 D14 C7 D7 C15 C14 F6 G6 C13 C12 E8 F8 J11 J10 G8 H8 G12 G11 J7 K7 K11 L11 G7 H7 D16 D15 D6 C5 K13 K12 D5 D4 M13 No Connects in FX60 Devices No Connects in FX40 Devices 128 www.R Chapter 2: Pinout Tables Table 2-6: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF1152 Package — FX40. FX60.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 6 6 6 6 6 6 6 FF1152 Package — FX40. 2005 www.xilinx. FX60.com 129 .4) September 30. and FX100 Devices (Continued) Pin Description IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number L13 E4 E3 M12 M11 C4 C3 No Connects in FX60 Devices No Connects in FX40 Devices 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 IO_L26N_SM6_7 IO_L27P_SM5_7 (2) (2) (2) (2) AH27 AJ27 AL25 AM25 AF26 AG26 AD24 AE24 AG25 AH25 AL26 AM26 AF25 AF24 AJ26 AJ25 AG28 AG27 AH23 AG23 AE28 AF28 AF23 AE23 AE27 AE26 AL24 AK24 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 IO_L27N_SM5_7 (2) IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 (2) IO_L29N_SM4_7 (2) IO_L30P_SM3_7 IO_L30N_SM3_7 IO_L31P_SM2_7 IO_L31N_SM2_7 IO_L32P_SM1_7 IO_L32N_SM1_7 IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 (2) (2) (2) (2) (2) (2) See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 Virtex-4 Packaging and Pinout Specification UG075 (v2.

FX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX100 Devices (Continued) Pin Description IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AK27 AK26 AJ24 AH24 AK32 AK31 AL19 AL18 AM32 AM31 AC23 AC22 AL31 AL30 AM20 AL20 AM30 AL29 AL21 AK21 AJ29 AK29 AM22 AM21 AH29 AH28 AE22 AD22 AM28 AM27 AM23 AL23 AK28 AL28 AK23 AK22 No Connects in FX60 Devices No Connects in FX40 Devices 130 www.4) September 30.R Chapter 2: Pinout Tables Table 2-6: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1152 Package — FX40.xilinx. 2005 .

com 131 . and FX100 Devices (Continued) Pin Description Pin Number No Connects in FX60 Devices No Connects in FX40 Devices 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 AG13 AH13 AJ12 AK12 AF11 AG11 AF9 AE9 AG12 AH12 AM13 AM12 AK14 AL14 AK13 AL13 AF15 AG15 AH10 AJ10 AJ16 AK16 AF10 AG10 AH15 AJ15 AL11 AM11 AH14 AJ14 AJ11 AK11 AB11 AA11 AK7 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. FX60. 2005 www.xilinx.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank FF1152 Package — FX40.

and FX100 Devices (Continued) Pin Description IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AJ7 AB13 AA13 AH8 AH7 AC12 AB12 AM8 AM7 AD14 AC13 AL8 AK8 AD12 AE12 AL9 AK9 AD11 AE11 AD10 AD9 AE14 AF14 AJ9 AH9 AE13 AF13 AL10 AM10 No Connects in FX60 Devices No Connects in FX40 Devices 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 L31 L30 J32 H32 N29 N28 132 www. FX60.R Chapter 2: Pinout Tables Table 2-6: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1152 Package — FX40. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx.

FX60.xilinx.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FF1152 Package — FX40. and FX100 Devices (Continued) Pin Description IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 Pin Number N27 M28 N30 M30 M32 M31 P31 P30 P27 P26 E31 D31 D29 C29 E32 F31 H28 H27 G30 F30 D30 C30 G32 G31 F29 E29 K29 J29 D32 C32 J31 J30 K28 J27 L29 L28 H30 No Connects in FX60 Devices No Connects in FX40 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.com 133 .4) September 30.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. FX60.R Chapter 2: Pinout Tables Table 2-6: Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FF1152 Package — FX40. and FX100 Devices (Continued) Pin Description IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9 Pin Number H29 K32 K31 M26 M25 P32 N32 R32 R31 R29 P29 R28 R27 T31 T30 T29 T28 T26 R26 U28 U27 No Connects in FX60 Devices No Connects in FX40 Devices 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 N5 N4 P5 P4 P10 P9 R4 R3 T5 T4 P7 P6 P11 R11 134 www.xilinx. 2005 .

FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 FF1152 Package — FX40.xilinx.com 135 . and FX100 Devices (Continued) Pin Description IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 Pin Number T6 R6 L9 L8 H5 H4 L10 M10 M8 M7 F5 G5 G3 H3 F4 F3 J5 J4 J6 K6 K4 K3 N10 N9 N8 N7 L6 L5 L4 L3 M6 M5 M3 N3 V5 U5 U3 No Connects in FX60 Devices No Connects in FX40 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. FX60. 2005 www.4) September 30.

and FX100 Devices (Continued) Pin Description IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10 Pin Number T3 U8 T8 R8 R7 T9 R9 V4 V3 T11 T10 U7 U6 No Connects in FX60 Devices No Connects in FX40 Devices 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 IO_L17P_11 IO_L17N_11 IO_L18P_11 IO_L18N_11 IO_L19P_11 IO_L19N_11 IO_L20P_11 IO_L20N_VREF_11 IO_L21P_11 IO_L21N_11 IO_L22P_11 IO_L22N_11 IO_L23P_VRN_11 IO_L23N_VRP_11 IO_L24P_CC_LC_11 IO_L24N_CC_LC_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 AA26 AA25 AC30 AC29 AB28 AB27 AB26 AB25 AD32 AD31 AD30 AD29 AC28 AC27 AG32 AH32 V29 V28 U32 U31 V30 U30 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 136 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.R Chapter 2: Pinout Tables Table 2-6: Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 FF1152 Package — FX40.4) September 30. 2005 . FX60.

FF1152 Flip-Chip Fine-Pitch BGA Package

R

Table 2-6: Bank
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11 IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 IO_L12N_VREF_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_11 IO_L15P_11 IO_L15N_11 IO_L16P_11 IO_L16N_11 IO_L25P_CC_LC_11 IO_L25N_CC_LC_11 IO_L26P_11 IO_L26N_11 IO_L27P_11 IO_L27N_11 IO_L28P_11 IO_L28N_VREF_11 IO_L29P_11 IO_L29N_11 IO_L30P_11

Pin Number
W25 W24 W32 V32 W26 Y26 Y29 W29 W27 V27 W31 W30 Y32 Y31 Y28 Y27 Y24 AA24 AA31 AA30 AB32 AC32 AA29 AA28 AB31 AB30 AE32 AE31 AD27 AD26 AF31 AF30 AC25 AD25 AE29 AF29 AJ32

No Connects in FX60 Devices

No Connects in FX40 Devices
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-6: Bank
11 11 11 11 11

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
IO_L30N_11 IO_L31P_11 IO_L31N_11 IO_L32P_11 IO_L32N_11

Pin Number
AJ31 AG31 AG30 AH30 AJ30

No Connects in FX60 Devices

No Connects in FX40 Devices
NC NC NC NC NC

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 IO_L21N_12 IO_L22P_12 IO_L22N_12 IO_L23P_VRN_12 IO_L23N_VRP_12 IO_L24P_CC_LC_12 IO_L24N_CC_LC_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12

AJ4 AK3 AE4 AE3 AM5 AL5 AC7 AB8 AL4 AK4 AF5 AF4 AF8 AE7 AH4 AH3 W5 W4 V8 V7 AA5 AA4 W7 W6 Y8 Y7 Y4 Y3 AC5 AB5

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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FF1152 Flip-Chip Fine-Pitch BGA Package

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Table 2-6: Bank
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 IO_L27P_12 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12

Pin Number
AB3 AA3 AB7 AB6 AA6 Y6 AG3 AF3 W9 Y9 AA9 AA8 AC4 AC3 AF6 AE6 AD5 AD4 AK6 AJ6 AM3 AL3 AG8 AG7 AD7 AD6 AM6 AL6 AG6 AG5 AC10 AC9 AJ5 AH5

No Connects in FX60 Devices

No Connects in FX40 Devices
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

0

VCCO_0 (3)

Y15

See footnote #3

See footnote #3

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Table 2-6: Bank
0 0 0 1 1 2 2 3 3 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
VCCO_0 (3) VCCO_0 VCCO_0
(3) (3)

Pin Number
T17 W18 R20 G14 F17 AJ18 AH21 K15 J18 AF17 AE20 E20 H21 L22 D23 P23 G24 K25 C26 F27 D3 C6 F7 J8 E10 H11 L12 D13 C16 AM19 AL22 AD23 AG24 AK25 AF27 AJ28 AM29

No Connects in FX60 Devices
See footnote #3 See footnote #3 See footnote #3

No Connects in FX40 Devices
See footnote #3 See footnote #3 See footnote #3

VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7

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Table 2-6: Bank
7 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 12 12 12

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12

Pin Number
AL32 AJ8 AM9 AE10 AH11 AA12 AL12 AD13 AG14 AK15 N26 T27 J28 M29 E30 R30 H31 L32 P3 G4 U4 K5 N6 T7 M9 R10 Y25 AC26 W28 AB29 AE30 V31 AH31 AA32 AD3 AG4 Y5

No Connects in FX60 Devices

No Connects in FX40 Devices

NC NC NC NC NC NC NC NC NC NC NC

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Table 2-6: Bank
12 12 12 12 12

FF1152 Package — FX40, FX60, and FX100 Devices (Continued) Pin Description
VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12

Pin Number
AK5 AC6 AF7 W8 AB9

No Connects in FX60 Devices

No Connects in FX40 Devices
NC NC NC NC NC

101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101

AVCCAUXRXA_101 RXPPADA_101 VTRXA_101 RXNPADA_101 AVCCAUXMGT_101 AVCCAUXTX_101 VTTXA_101 TXPPADA_101 TXNPADA_101 VTTXB_101 TXPPADB_101 TXNPADB_101 AVCCAUXRXB_101 RXPPADB_101 VTRXB_101 RXNPADB_101

B21 A20 A22 A21 B28 B25 B23 A23 A24 B26 A25 A26 B30 A28 A27 A29

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

102 102 102 102 102 102 102 102 102 102 102 102 102

AVCCAUXRXA_102 RXPPADA_102 VTRXA_102 RXNPADA_102 AVCCAUXMGT_102 AVCCAUXTX_102 VTTXA_102 TXPPADA_102 TXNPADA_102 VTTXB_102 TXPPADB_102 TXNPADB_102 AVCCAUXRXB_102

B32 A31 C34 A32 J33 F33 D33 D34 E34 G33 F34 G34 K33

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2005 www.xilinx. and FX100 Devices (Continued) Pin Description RXPPADB_102 VTRXB_102 RXNPADB_102 MGTCLK_P_102 MGTCLK_N_102 Pin Number J34 H34 K34 M34 N34 No Connects in FX60 Devices No Connects in FX40 Devices 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 AVCCAUXRXA_103 RXPPADA_103 VTRXA_103 RXNPADA_103 AVCCAUXMGT_103 AVCCAUXTX_103 VTTXA_103 TXPPADA_103 TXNPADA_103 VTTXB_103 TXPPADB_103 TXNPADB_103 AVCCAUXRXB_103 RXPPADB_103 VTRXB_103 RXNPADB_103 T33 R34 U34 T34 AC33 Y33 V33 V34 W34 AA33 Y34 AA34 AE33 AC34 AB34 AD34 105 105 105 105 105 105 105 105 105 105 105 105 105 AVCCAUXRXA_105 RXPPADA_105 VTRXA_105 RXNPADA_105 AVCCAUXMGT_105 AVCCAUXTX_105 VTTXA_105 TXPPADA_105 TXNPADA_105 VTTXB_105 TXPPADB_105 TXNPADB_105 AVCCAUXRXB_105 AG33 AF34 AH34 AG34 AN32 AL33 AJ33 AJ34 AK34 AM33 AL34 AM34 AN31 Virtex-4 Packaging and Pinout Specification UG075 (v2. FX60.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 102 102 102 102 102 FF1152 Package — FX40.com 143 .4) September 30.

R Chapter 2: Pinout Tables Table 2-6: Bank 105 105 105 105 105 105 105 FF1152 Package — FX40. 2005 .xilinx. and FX100 Devices (Continued) Pin Description RXPPADB_105 VTRXB_105 RXNPADB_105 MGTCLK_P_105 MGTCLK_N_105 RTERM_105 MGTVREF_105 Pin Number AP32 AN33 AP31 AP29 AP28 AN29 AN27 No Connects in FX60 Devices No Connects in FX40 Devices 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 AVCCAUXRXA_106 RXPPADA_106 VTRXA_106 RXNPADA_106 AVCCAUXMGT_106 AVCCAUXTX_106 VTTXA_106 TXPPADA_106 TXNPADA_106 VTTXB_106 TXPPADB_106 TXNPADB_106 AVCCAUXRXB_106 RXPPADB_106 VTRXB_106 RXNPADB_106 AN25 AP26 AP24 AP25 AN18 AN22 AN23 AP23 AP22 AN20 AP21 AP20 AN17 AP18 AP19 AP17 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 109 109 109 109 109 109 109 109 109 109 109 AVCCAUXRXA_109 RXPPADA_109 VTRXA_109 RXNPADA_109 AVCCAUXMGT_109 AVCCAUXTX_109 VTTXA_109 TXPPADA_109 TXNPADA_109 VTTXB_109 TXPPADB_109 AN7 AP6 AP8 AP7 AN14 AN10 AN9 AP9 AP10 AN12 AP11 NC NC NC NC NC NC NC NC NC NC NC 144 www.4) September 30. FX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FX60.com 145 . 2005 www.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 109 109 109 109 109 FF1152 Package — FX40.4) September 30. and FX100 Devices (Continued) Pin Description TXNPADB_109 AVCCAUXRXB_109 RXPPADB_109 VTRXB_109 RXNPADB_109 Pin Number AP12 AN15 AP14 AP13 AP15 No Connects in FX60 Devices No Connects in FX40 Devices NC NC NC NC NC 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 MGTCLK_N_110 RTERM_110 MGTVREF_110 AD2 AC1 AE1 AD1 AL2 AH2 AF2 AF1 AG1 AJ2 AH1 AJ1 AM2 AL1 AK1 AM1 AP3 AP4 AN3 AN5 112 112 112 112 112 112 112 112 112 AVCCAUXRXA_112 RXPPADA_112 VTRXA_112 RXNPADA_112 AVCCAUXMGT_112 AVCCAUXTX_112 VTTXA_112 TXPPADA_112 TXNPADA_112 N2 M1 P1 N1 Y2 U2 R2 R1 T1 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

4) September 30. FX60.R Chapter 2: Pinout Tables Table 2-6: Bank 112 112 112 112 112 112 112 FF1152 Package — FX40. and FX100 Devices (Continued) Pin Description VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 Pin Number V2 U1 V1 AB2 Y1 W1 AA1 No Connects in FX60 Devices No Connects in FX40 Devices 113 113 113 113 113 113 113 113 113 113 113 113 113 113 113 113 113 113 AVCCAUXRXA_113 RXPPADA_113 VTRXA_113 RXNPADA_113 AVCCAUXMGT_113 AVCCAUXTX_113 VTTXA_113 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 B6 A7 A5 A6 F2 C2 B4 A4 A3 D2 C1 D1 G2 F1 E1 G1 J1 K1 114 114 114 114 114 114 114 114 114 AVCCAUXRXA_114 RXPPADA_114 VTRXA_114 RXNPADA_114 AVCCAUXMGT_114 AVCCAUXTX_114 VTTXA_114 TXPPADA_114 TXNPADA_114 B17 A18 A16 A17 B10 B13 B15 A15 A14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 146 www.xilinx. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FX60.xilinx. 2005 www.com 147 .4) September 30.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 114 114 114 114 114 114 114 FF1152 Package — FX40. and FX100 Devices (Continued) Pin Description VTTXB_114 TXPPADB_114 TXNPADB_114 AVCCAUXRXB_114 RXPPADB_114 VTRXB_114 RXNPADB_114 Pin Number B12 A13 A12 B8 A10 A11 A9 No Connects in FX60 Devices NC NC NC NC NC NC NC No Connects in FX40 Devices NC NC NC NC NC NC NC 101 101 101 101 101 101 102 102 102 102 102 102 102 102 102 102 102 102 102 102 103 103 103 103 103 103 105 105 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_105 GNDA_105 A19 B20 B22 B24 B27 B29 A30 B31 A33 B33 C33 E33 H33 L33 M33 N33 P33 B34 L34 P34 R33 U33 W33 AB33 AD33 AE34 AP27 AN28 NC NC NC NC NC NC NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2.

R Chapter 2: Pinout Tables Table 2-6: Bank 105 105 105 105 105 105 105 106 106 106 106 106 109 109 109 109 109 110 110 110 110 110 110 110 110 110 112 112 112 112 112 112 113 113 113 113 113 FF1152 Package — FX40.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. and FX100 Devices (Continued) Pin Description GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 Pin Number AN30 AP30 AF33 AH33 AK33 AP33 AN34 AP16 AN19 AN21 AN24 AN26 AN6 AN8 AN11 AN13 AN16 AN1 AC2 AE2 AG2 AK2 AN2 AP2 AN4 AP5 AA2 AB1 M2 P2 T2 W2 B1 H1 L1 A2 B2 No Connects in FX60 Devices No Connects in FX40 Devices NC NC NC NC NC NC NC NC NC NC 148 www.4) September 30. FX60. 2005 .

FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank 113 113 113 113 113 113 113 113 113 114 114 114 114 114 114 FF1152 Package — FX40. 2005 www.4) September 30.xilinx. and FX100 Devices (Continued) Pin Description GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 Pin Number E2 H2 J2 K2 L2 B3 B5 B7 A8 B9 B11 B14 B16 B18 B19 No Connects in FX60 Devices No Connects in FX40 Devices NC NC NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VREFN_SM (4) VREFP_SM (4) AVDD_SM VN_SM VP_SM (5) (4) (4) (4) (4) (4) AL17 AL16 AL15 AM17 AM16 AM15 D20 D19 D18 C20 C19 C18 See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 NC NC NC NC NC NC AVSS_SM VREFN_ADC VREFP_ADC AVDD_ADC (5) VN_ADC (4) VP_ADC (4) AVSS_ADC (4) N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND J3 W3 AJ3 M4 AB4 AM4 E5 Virtex-4 Packaging and Pinout Specification UG075 (v2. FX60.com 149 .

R Chapter 2: Pinout Tables Table 2-6: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1152 Package — FX40. FX60.xilinx.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number R5 AE5 H6 V6 AH6 L7 AA7 AL7 D8 P8 AD8 G9 U9 AG9 K10 V10 Y10 AK10 C11 N11 W11 AC11 F12 P12 T12 V12 Y12 AF12 J13 R13 U13 W13 AJ13 M14 P14 V14 AB14 No Connects in FX60 Devices No Connects in FX40 Devices 150 www. 2005 .

com 151 . and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AM14 E15 N15 R15 U15 AC15 AE15 H16 P16 V16 Y16 AH16 L17 N17 U17 AA17 AC17 M18 P18 AB18 AD18 AM18 G19 U19 AA19 AG19 K20 M20 V20 Y20 AB20 AK20 C21 N21 U21 AA21 AC21 No Connects in FX60 Devices No Connects in FX40 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www. FX60.xilinx.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1152 Package — FX40.4) September 30.

xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 . and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number F22 T22 V22 Y22 AF22 J23 R23 U23 W23 AA23 AJ23 M24 T24 AB24 AM24 E25 R25 U25 AE25 H26 V26 AH26 L27 AA27 AL27 D28 P28 AD28 G29 U29 AG29 K30 Y30 AK30 C31 N31 AC31 No Connects in FX60 Devices No Connects in FX40 Devices 152 www. FX60.R Chapter 2: Pinout Tables Table 2-6: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1152 Package — FX40.4) September 30.

2005 www. and FX100 Devices (Continued) Pin Description GND GND GND Pin Number F32 T32 AF32 No Connects in FX60 Devices No Connects in FX40 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT AE8 V9 AB10 U11 N13 T14 M16 U16 AB16 AD16 L19 N19 V19 AC19 W21 AB22 V24 N25 U26 K27 AC8 U10 W10 AA10 V11 Y11 N12 R12 U12 W12 P13 T13 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank N/A N/A N/A FF1152 Package — FX40.com 153 . FX60.

xilinx.R Chapter 2: Pinout Tables Table 2-6: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1152 Package — FX40. FX60. and FX100 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number V13 Y13 N14 R14 U14 W14 AC14 M15 P15 T15 V15 AB15 AD15 N16 R16 W16 AC16 M17 P17 V17 Y17 AB17 AD17 L18 N18 R18 U18 AA18 AC18 M19 T19 Y19 AB19 L20 N20 U20 W20 No Connects in FX60 Devices No Connects in FX40 Devices 154 www. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

For FX60 and FX100 devices. Virtex-4 Packaging and Pinout Specification UG075 (v2. 5.com 155 . FX60.xilinx.4) September 30. Connect this reserved pin to GND. 2005 www. and FX100 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AA20 AC20 M21 T21 V21 Y21 AB21 R22 U22 W22 AA22 T23 V23 Y23 AB23 R24 U24 AC24 P25 T25 V25 M27 No Connects in FX60 Devices No Connects in FX40 Devices 1. ADC functionality is not available in FX40 devices. 4. 2. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions. Connect this reserved pin to 2. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide.FF1152 Flip-Chip Fine-Pitch BGA Package R Table 2-6: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF1152 Package — FX40. 3.5V (sharing the same PCB supply distribution as VCCAUX is acceptable).

4) September 30. and LX200 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number V23 W20 Y16 W22 V24 Y17 Y19 Y18 W24 Y22 Y21 AA16 Y23 AB16 AA18 Y24 AA20 AB17 H19 H20 1 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 F26 F25 K16 L16 E26 D26 J16 H15 M25 N24 156 www. visit www. Virtex-4 XC4VLX100.R Chapter 2: Pinout Tables FF1513 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-7.com and check for any updates to this document. XC4VLX160. LX160.xilinx.xilinx. Pinouts in each of these devices are identical. ASCII package pinout files are also available for download from the Xilinx website. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2. To be assured of having the very latest Virtex-4 pinout information. Table 2-7: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF1513 Package — LX100. and XC4VLX200 devices are available in the FF1513 flip-chip fine-pitch BGA package.

4) September 30.xilinx. 2005 www. LX160.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF1513 Package — LX100. and LX200 Devices (Continued) Pin Description IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 IO_L9P_GC_LC_1 IO_L9N_GC_LC_1 IO_L10P_GC_LC_1 IO_L10N_GC_LC_1 IO_L11P_GC_LC_1 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 IO_L23N_LC_1 IO_L24P_LC_1 IO_L24N_LC_1 Pin Number G16 G15 T23 R22 A16 B16 C20 D20 D19 E19 E21 D21 C19 C18 D22 C22 G20 F19 J22 H22 T20 T19 G22 F21 P19 N18 H23 G23 L18 M18 F23 E22 G18 H17 C23 B23 E18 F18 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 157 .

2005 .4) September 30.xilinx. and LX200 Devices (Continued) Pin Description IO_L25P_LC_1 IO_L25N_LC_1 IO_L26P_LC_1 IO_L26N_LC_1 IO_L27P_LC_1 IO_L27N_LC_1 IO_L28P_LC_1 IO_L28N_VREF_LC_1 IO_L29P_LC_1 IO_L29N_LC_1 IO_L30P_LC_1 IO_L30N_LC_1 IO_L31P_LC_1 IO_L31N_LC_1 IO_L32P_CC_LC_1 IO_L32N_CC_LC_1 IO_L33P_CC_LC_1 IO_L33N_CC_LC_1 IO_L34P_LC_1 IO_L34N_LC_1 IO_L35P_LC_1 IO_L35N_LC_1 IO_L36P_LC_1 IO_L36N_VREF_LC_1 IO_L37P_LC_1 IO_L37N_LC_1 IO_L38P_LC_1 IO_L38N_LC_1 IO_L39P_LC_1 IO_L39N_LC_1 IO_L40P_LC_1 IO_L40N_LC_1 Pin Number F24 E24 A18 B18 D24 C24 U20 U18 A24 A23 T18 R18 N23 M23 P17 R17 L24 K23 M17 N17 K24 J24 J17 K17 D25 C25 D17 E17 B25 A25 B17 C17 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 AN25 AN24 AT14 AR14 AV24 158 www.R Chapter 2: Pinout Tables Table 2-7: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF1513 Package — LX100.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160.

com 159 . 2005 www. LX160.xilinx. and LX200 Devices (Continued) Pin Description IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 IO_L9P_GC_CC_LC_2 IO_L9N_GC_CC_LC_2 IO_L10P_GC_LC_2 IO_L10N_GC_LC_2 IO_L11P_GC_LC_2 IO_L11N_GC_LC_2 IO_L12P_GC_LC_2 IO_L12N_GC_VREF_LC_2 IO_L13P_GC_LC_2 IO_L13N_GC_LC_2 IO_L14P_GC_LC_2 IO_L14N_GC_LC_2 IO_L15P_GC_LC_2 IO_L15N_GC_LC_2 IO_L16P_GC_LC_2 IO_L16N_GC_LC_2 IO_L17P_LC_2 IO_L17N_LC_2 IO_L18P_LC_2 IO_L18N_LC_2 IO_L19P_LC_2 IO_L19N_LC_2 IO_L20P_LC_2 IO_L20N_VREF_LC_2 IO_L21P_LC_2 IO_L21N_LC_2 IO_L22P_LC_2 Pin Number AW24 AV15 AU15 AL24 AM25 AP15 AP14 AJ24 AK24 AH15 AG16 AP22 AR22 AM18 AL18 AT21 AR21 AT19 AR19 AP21 AN20 AP19 AR18 AM21 AM20 AU20 AT20 AG22 AF21 AH17 AG17 AE22 AD21 AE18 AD17 AV22 AW22 AU18 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FF1513 Package — LX100.4) September 30.

xilinx. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-7: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FF1513 Package — LX100.4) September 30. and LX200 Devices (Continued) Pin Description IO_L22N_LC_2 IO_L23P_VRN_LC_2 IO_L23N_VRP_LC_2 IO_L24P_CC_LC_2 IO_L24N_CC_LC_2 IO_L25P_CC_LC_2 IO_L25N_CC_LC_2 IO_L26P_LC_2 IO_L26N_LC_2 IO_L27P_LC_2 IO_L27N_LC_2 IO_L28P_LC_2 IO_L28N_VREF_LC_2 IO_L29P_LC_2 IO_L29N_LC_2 IO_L30P_LC_2 IO_L30N_LC_2 IO_L31P_LC_2 IO_L31N_LC_2 IO_L32P_LC_2 IO_L32N_LC_2 IO_L33P_LC_2 IO_L33N_LC_2 IO_L34P_LC_2 IO_L34N_LC_2 IO_L35P_LC_2 IO_L35N_LC_2 IO_L36P_LC_2 IO_L36N_VREF_LC_2 IO_L37P_LC_2 IO_L37N_LC_2 IO_L38P_LC_2 IO_L38N_LC_2 IO_L39P_LC_2 IO_L39N_LC_2 IO_L40P_CC_LC_2 IO_L40N_CC_LC_2 Pin Number AT18 AU22 AU21 AN18 AP17 AM23 AN22 AW17 AV17 AK23 AL23 AU17 AU16 AG23 AH23 AN17 AM17 AH22 AJ22 AK17 AL16 AE23 AF23 AW16 AW15 AC22 AC20 AT16 AT15 AU23 AV23 AR16 AP16 AR23 AT23 AK16 AJ16 160 www. LX160.

FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 FF1513 Package — LX100.com 161 . 2005 www. LX160.4) September 30.xilinx. and LX200 Devices (Continued) Pin Description IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 Pin Number P20 N20 J19 K19 N22 M22 J21 J20 M21 M20 L20 L19 P22 P21 L21 K21 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 IO_L2P_ADC6_5 IO_L2N_ADC6_5 (1) (1) (1) AH20 AH19 AF19 AF18 AJ21 AJ20 AG20 AF20 AL20 AL19 AH18 AG18 AL21 AK21 AK19 AJ19 5 5 5 5 B26 A26 E28 F28 Virtex-4 Packaging and Pinout Specification UG075 (v2.

and LX200 Devices (Continued) Pin Description IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 IO_L5N_ADC4_5 (1) (1) (1) (1) Pin Number E27 D27 A30 A31 G25 G26 D29 E29 A28 A29 D30 D31 H25 J26 G30 H29 B32 B33 J29 K29 B30 B31 C33 C34 F31 G31 B35 C35 C27 B27 F29 G28 J27 H27 C32 D32 B28 C28 IO_L6P_ADC3_5 (1) IO_L6N_ADC3_5 (1) IO_L7P_ADC2_5 (1) IO_L7N_ADC2_5 (1) IO_L8P_CC_ADC1_LC_5 (1) IO_L8N_CC_ADC1_LC_5 (1) IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 162 www. LX160.R Chapter 2: Pinout Tables Table 2-7: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1513 Package — LX100.xilinx.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .

LX160.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1513 Package — LX100. 2005 www.4) September 30.com 163 . and LX200 Devices (Continued) Pin Description IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number A33 A34 C29 C30 E31 E32 M27 L28 E33 F33 H30 J30 G32 G33 A35 A36 J31 K31 B36 B37 L30 L31 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 A14 A13 E12 E11 B13 C13 D11 D10 D14 C14 A11 A10 E13 F13 B10 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

xilinx.4) September 30. LX160. 2005 .R Chapter 2: Pinout Tables Table 2-7: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF1513 Package — LX100. and LX200 Devices (Continued) Pin Description IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 Pin Number C10 J14 H13 E9 F9 C12 D12 B7 C7 D15 C15 G10 H10 A9 A8 E8 F8 F14 E14 H12 J12 G13 G12 C9 D9 B15 A15 F11 G11 B12 B11 B8 C8 E16 D16 D7 E7 A6 164 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

and LX200 Devices (Continued) Pin Description IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 IO_L26N_SM6_7 IO_L27P_SM5_7 IO_L27N_SM5_7 IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 IO_L29N_SM4_7 (2) (2) (2) (2) (2) (2) (2) Pin Number B6 J10 J9 F16 F15 H9 G8 K11 L11 L10 K9 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 AP27 AR27 AV30 AU30 AR26 AT26 AW29 AV29 AV27 AW27 AT29 AR29 AU26 AU27 AT28 AR28 AL26 AM27 AU31 AU32 AV28 AU28 AW32 AV32 AW25 AW26 IO_L30P_SM3_7 (2) IO_L30N_SM3_7 (2) IO_L31P_SM2_7 (2) IO_L31N_SM2_7 (2) IO_L32P_SM1_7 (2) IO_L32N_SM1_7 (2) IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.com 165 .FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 6 6 6 6 6 6 6 6 6 6 6 FF1513 Package — LX100. 2005 www.4) September 30. LX160.

and LX200 Devices (Continued) Pin Description IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AP29 AN29 AN27 AN28 AL28 AM28 AT33 AR33 AJ30 AK31 AM30 AL30 AM31 AL31 AP24 AR24 AP32 AN32 AN30 AP31 AK29 AJ29 AT24 AT25 AW34 AV34 AW30 AW31 AV33 AU33 AP25 AP26 AT31 AT30 AU25 AV25 AR31 AR32 166 www.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.R Chapter 2: Pinout Tables Table 2-7: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1513 Package — LX100. LX160. 2005 .

2005 www.4) September 30. LX160. and LX200 Devices (Continued) Pin Description IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 Pin Number AW12 AV12 AW9 AV9 AN14 AM13 AT11 AR11 AT13 AR13 AV10 AU10 AW14 AV14 AW11 AW10 AL14 AL13 AU8 AT8 AR12 AP12 AR9 AP9 AV13 AU13 AT10 AT9 AU12 AU11 AV8 AV7 AV5 AU5 AJ10 AJ9 AN9 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1513 Package — LX100.xilinx.com 167 .

and LX200 Devices (Continued) Pin Description IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AN8 AL9 AK9 AM15 AN15 AP7 AN7 AR8 AR7 AV4 AV3 AL11 AK11 AW5 AW4 AW7 AW6 AM10 AL10 AM11 AN10 AH13 AJ12 AN12 AP11 AU7 AU6 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 K33 L33 H37 H38 N30 P29 L34 L35 J36 J37 168 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-7: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1513 Package — LX100.xilinx. LX160.

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Table 2-7: Bank
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9

Pin Number
K36 L36 H39 J39 M33 N32 D34 D35 C37 C38 E34 F34 F35 G35 D36 D37 H33 H34 E36 F36 C39 D39 J32 K32 G36 G37 E37 E38 H35 J35 M30 M31 E39 F39 J34 K34 F38 G38

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Table 2-7: Bank
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9

Pin Number
R28 R29 M35 N35 K37 K38 N33 N34 P31 P32 K39 L39 L38 M38 M36 M37

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10

R14 T14 E2 E1 P12 R12 K7 L8 H5 J5 G3 G2 J6 K6 F1 G1 A5 A4 A3 B3 B5

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Table 2-7: Bank
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10

Pin Number
C5 C4 D4 D6 D5 C3 C2 E6 F6 H7 J7 G7 G6 F5 G5 M11 N12 F4 F3 R16 T15 M10 N10 E4 E3 D2 D1 P11 R11 T13 U13 M8 M7 P9 N8 L6 M6 N7

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Table 2-7: Bank
10 10 10 10 10

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10

Pin Number
P7 R9 R8 U12 T11

11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

IO_L17P_11 IO_L17N_11 IO_L18P_11 IO_L18N_11 IO_L19P_11 IO_L19N_11 IO_L20P_11 IO_L20N_VREF_11 IO_L21P_11 IO_L21N_11 IO_L22P_11 IO_L22N_11 IO_L23P_VRN_11 IO_L23N_VRP_11 IO_L24P_CC_LC_11 IO_L24N_CC_LC_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11

AR37 AR38 AM35 AL35 AP35 AN35 AT39 AR39 AG28 AH29 AP36 AP37 AN33 AN34 AU38 AT38 AG33 AF33 AC28 AD29 AD27 AC27 AE31 AE32 AD26 AE26 AF31 AG32 AH32 AH33 AJ34 AH34

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Table 2-7: Bank
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 IO_L12N_VREF_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_11 IO_L15P_11 IO_L15N_11 IO_L16P_11 IO_L16N_11 IO_L25P_CC_LC_11 IO_L25N_CC_LC_11 IO_L26P_11 IO_L26N_11 IO_L27P_11 IO_L27N_11 IO_L28P_11 IO_L28N_VREF_11 IO_L29P_11 IO_L29N_11 IO_L30P_11 IO_L30N_11 IO_L31P_11 IO_L31N_11 IO_L32P_11 IO_L32N_11

Pin Number
AD25 AE24 AE28 AE29 AL34 AK34 AP39 AN39 AF28 AF29 AN37 AN38 AH30 AG30 AK33 AJ32 AU35 AU36 AM33 AL33 AT34 AT35 AT36 AR36 AW36 AW37 AV37 AU37 AW35 AV35 AR34 AP34

12 12 12 12 12

IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12

AL6 AK6 AN3 AN2 AH10

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Table 2-7: Bank
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FF1513 Package — LX100, LX160, and LX200 Devices (Continued) Pin Description
IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 IO_L21N_12 IO_L22P_12 IO_L22N_12 IO_L23P_VRN_12 IO_L23N_VRP_12 IO_L24P_CC_LC_12 IO_L24N_CC_LC_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 IO_L14P_12

Pin Number
AH9 AK7 AJ7 AN5 AN4 AM5 AL5 AL8 AK8 AT1 AR1 AH5 AG5 AH3 AH2 AG7 AG6 AJ2 AJ1 AL1 AK1 AF9 AF8 AG8 AH7 AJ4 AH4 AJ6 AJ5 AK3 AK2 AF11 AG10 AE12 AE11 AM3 AL3 AM2

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xilinx. 2005 www. LX160. and LX200 Devices (Continued) Pin Description IO_L14N_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 IO_L27P_12 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 Pin Number AM1 AP2 AP1 AL4 AK4 AU2 AU1 AR3 AR2 AT4 AR4 AM7 AM6 AR6 AP6 AP5 AP4 AT6 AT5 AU3 AT3 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 IO_L24N_CC_LC_13 T38 U38 V29 V30 U36 U37 V32 W32 W26 W27 V34 V35 V37 V38 V39 W39 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 175 .4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 FF1513 Package — LX100.

and LX200 Devices (Continued) Pin Description IO_L1P_13 IO_L1N_13 IO_L2P_13 IO_L2N_13 IO_L3P_13 IO_L3N_13 IO_L4P_13 IO_L4N_VREF_13 IO_L5P_13 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 IO_L26N_13 IO_L27P_13 IO_L27N_13 Pin Number R31 R32 P34 P35 T29 U28 P36 P37 N37 N38 N39 P39 R34 T34 T31 U30 R36 T36 T33 U32 R37 R38 R39 T39 V25 U26 V27 U27 T35 U35 U33 V33 W34 W35 W36 W37 Y37 Y38 176 www. 2005 .R Chapter 2: Pinout Tables Table 2-7: Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 FF1513 Package — LX100. LX160.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.4) September 30.

xilinx. and LX200 Devices (Continued) Pin Description IO_L28P_13 IO_L28N_VREF_13 IO_L29P_13 IO_L29N_13 IO_L30P_13 IO_L30N_13 IO_L31P_13 IO_L31N_13 IO_L32P_13 IO_L32N_13 Pin Number Y39 AA39 AA36 Y36 Y33 Y34 AB36 AB37 AB38 AA38 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 U10 T9 R4 R3 T6 T5 R2 R1 T4 T3 U7 U6 V10 V9 U5 V5 H4 J4 K4 K3 H3 H2 J2 J1 L5 M5 K2 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www. LX160.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 13 13 13 13 13 13 13 13 13 13 FF1513 Package — LX100.4) September 30.com 177 .

2005 .R Chapter 2: Pinout Tables Table 2-7: Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 FF1513 Package — LX100.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160. and LX200 Devices (Continued) Pin Description IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_LC_14 IO_L8N_CC_LC_14 IO_L9P_CC_LC_14 IO_L9N_CC_LC_14 IO_L10P_14 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 IO_L29P_14 IO_L29N_14 IO_L30P_14 IO_L30N_14 IO_L31P_14 IO_L31N_14 IO_L32P_14 IO_L32N_14 Pin Number K1 L4 L3 M3 M2 N5 N4 L1 M1 P6 R6 P5 P4 N3 N2 V13 V12 T8 U8 P2 P1 T1 U1 U3 U2 V7 W7 W10 W9 W6 W5 AA10 Y9 AA11 Y11 Y13 W12 178 www.4) September 30.

2005 www.4) September 30. LX160.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 FF1513 Package — LX100.xilinx.com 179 . and LX200 Devices (Continued) Pin Description IO_L17P_15 IO_L17N_15 IO_L18P_15 IO_L18N_15 IO_L19P_15 IO_L19N_15 IO_L20P_15 IO_L20N_VREF_15 IO_L21P_15 IO_L21N_15 IO_L22P_15 IO_L22N_15 IO_L23P_VRN_15 IO_L23N_VRP_15 IO_L24P_CC_LC_15 IO_L24N_CC_LC_15 IO_L1P_15 IO_L1N_15 IO_L2P_15 IO_L2N_15 IO_L3P_15 IO_L3N_15 IO_L4P_15 IO_L4N_VREF_15 IO_L5P_15 IO_L5N_15 IO_L6P_15 IO_L6N_15 IO_L7P_15 IO_L7N_15 IO_L8P_CC_LC_15 IO_L8N_CC_LC_15 IO_L9P_CC_LC_15 IO_L9N_CC_LC_15 IO_L10P_15 IO_L10N_15 IO_L11P_15 IO_L11N_15 Pin Number AB27 AB28 AE34 AD34 AD31 AD32 AF36 AE36 AJ39 AH39 AG37 AG38 AH37 AH38 AF34 AF35 Y27 AA28 W29 W30 AA34 AA35 Y29 AA30 AC38 AC39 AA31 Y31 AC35 AB35 AB33 AA33 AC33 AC34 AD37 AC37 AC32 AB31 Virtex-4 Packaging and Pinout Specification UG075 (v2.

4) September 30.R Chapter 2: Pinout Tables Table 2-7: Bank 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 FF1513 Package — LX100.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. and LX200 Devices (Continued) Pin Description IO_L12P_15 IO_L12N_VREF_15 IO_L13P_15 IO_L13N_15 IO_L14P_15 IO_L14N_15 IO_L15P_15 IO_L15N_15 IO_L16P_15 IO_L16N_15 IO_L25P_CC_LC_15 IO_L25N_CC_LC_15 IO_L26P_15 IO_L26N_15 IO_L27P_15 IO_L27N_15 IO_L28P_15 IO_L28N_VREF_15 IO_L29P_15 IO_L29N_15 IO_L30P_15 IO_L30N_15 IO_L31P_15 IO_L31N_15 IO_L32P_15 IO_L32N_15 Pin Number AE39 AD39 AF38 AF39 AD35 AD36 AC30 AB30 AE37 AE38 AJ36 AJ37 AG35 AG36 AJ35 AH35 AK38 AK39 AM37 AM38 AL38 AL39 AM36 AL36 AK36 AK37 16 16 16 16 16 16 16 16 16 16 16 IO_L17P_16 IO_L17N_16 IO_L18P_16 IO_L18N_16 IO_L19P_16 IO_L19N_16 IO_L20P_16 IO_L20N_VREF_16 IO_L21P_16 IO_L21N_16 IO_L22P_16 AC8 AB8 AD2 AD1 AD5 AD4 AB13 AC13 AB15 AC14 AC10 180 www. 2005 . LX160.

xilinx. LX160. and LX200 Devices (Continued) Pin Description IO_L22N_16 IO_L23P_VRN_16 IO_L23N_VRP_16 IO_L24P_CC_LC_16 IO_L24N_CC_LC_16 IO_L1P_16 IO_L1N_16 IO_L2P_16 IO_L2N_16 IO_L3P_16 IO_L3N_16 IO_L4P_16 IO_L4N_VREF_16 IO_L5P_16 IO_L5N_16 IO_L6P_16 IO_L6N_16 IO_L7P_16 IO_L7N_16 IO_L8P_CC_LC_16 IO_L8N_CC_LC_16 IO_L9P_CC_LC_16 IO_L9N_CC_LC_16 IO_L10P_16 IO_L10N_16 IO_L11P_16 IO_L11N_16 IO_L12P_16 IO_L12N_VREF_16 IO_L13P_16 IO_L13N_16 IO_L14P_16 IO_L14N_16 IO_L15P_16 IO_L15N_16 IO_L16P_16 IO_L16N_16 IO_L25P_CC_LC_16 Pin Number AD9 AD7 AC7 AE3 AE2 V4 W4 V3 V2 W2 W1 Y7 Y6 Y4 AA4 Y3 Y2 AA3 AB3 Y1 AA1 AA14 AA13 AA6 AA5 AB6 AB5 AB2 AB1 AC3 AC2 AB7 AA8 AB11 AB10 AC5 AC4 AC12 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 181 . 2005 www.4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 FF1513 Package — LX100.

LX160. 2005 . and LX200 Devices (Continued) Pin Description IO_L25N_CC_LC_16 IO_L26P_16 IO_L26N_16 IO_L27P_16 IO_L27N_16 IO_L28P_16 IO_L28N_VREF_16 IO_L29P_16 IO_L29N_16 IO_L30P_16 IO_L30N_16 IO_L31P_16 IO_L31N_16 IO_L32P_16 IO_L32N_16 VCCO_0 (3) VCCO_0 VCCO_0 (3) (3) Pin Number AD11 AF1 AE1 AF4 AE4 AE6 AD6 AF6 AF5 AG2 AG1 AE9 AE8 AG3 AF3 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 AA17 W23 Y20 A17 B24 C21 D18 E25 F22 G19 H16 J23 L17 M24 P18 T22 U19 AC21 AD18 AF22 AH16 AJ23 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 182 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-7: Bank 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 FF1513 Package — LX100.xilinx.4) September 30.

xilinx.4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 2 2 2 2 2 2 2 2 2 3 3 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 FF1513 Package — LX100.com 183 . and LX200 Devices (Continued) Pin Description VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number AL17 AM24 AN21 AP18 AR15 AT22 AU19 AV16 AW23 K20 N21 AG19 AK20 A27 A37 B34 C31 D28 F32 G29 H26 K30 L27 A7 B14 C11 D8 E15 F12 G9 J13 K10 AK30 AL27 AN31 AP28 AR25 AT32 Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160. 2005 www.

2005 . and LX200 Devices (Continued) Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 Pin Number AU29 AV26 AW33 AJ13 AK10 AM14 AN11 AP8 AT12 AU9 AV6 AW13 AW3 D38 E35 G39 H36 J33 L37 M34 N31 P28 B4 C1 E5 F2 H6 L7 N11 P8 R15 T12 AD28 AE25 AF32 AG29 AJ33 AM34 184 www.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. LX160.R Chapter 2: Pinout Tables Table 2-7: Bank 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 FF1513 Package — LX100.

com 185 . LX160. and LX200 Devices (Continued) Pin Description VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 Pin Number AP38 AR35 AU39 AV36 AF12 AG9 AH6 AJ3 AL7 AM4 AN1 AR5 AT2 AA37 P38 R35 T32 U29 U39 V26 V36 W33 J3 M4 N1 R5 T2 U9 V6 W13 Y10 AA27 AB34 AC31 AD38 AE35 AG39 AH36 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank 11 11 11 11 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 15 FF1513 Package — LX100.

and LX200 Devices (Continued) Pin Description VCCO_15 VCCO_15 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VREFN_SM (4) VREFP_SM AVDD_SM VN_SM VP_SM (4) (5) Pin Number AL37 Y30 AA7 AB14 AB4 AC1 AC11 AD8 AE5 AF2 W3 N/A N/A N/A N/A N/A N/A AV19 AV20 AW21 AW19 AW20 AV18 (4) (4) (4) AVSS_SM N/A N/A N/A N/A N/A N/A VREFN_ADC (4) VREFP_ADC AVDD_ADC (4) (5) B20 B21 B22 A20 A21 A19 VN_ADC (4) VP_ADC (4) AVSS_ADC (4) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND GND GND B1 H1 V1 AH1 AV1 A2 L2 AA2 AL2 AW2 D3 P3 186 www.R Chapter 2: Pinout Tables Table 2-7: Bank 15 15 16 16 16 16 16 16 16 16 16 FF1513 Package — LX100. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160.xilinx.

2005 www.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100. LX160.xilinx.4) September 30. and LX200 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AD3 AP3 G4 U4 AG4 AU4 K5 Y5 AK5 C6 N6 AC6 AN6 F7 T7 AF7 AT7 J8 W8 AJ8 AW8 B9 M9 AB9 AM9 E10 R10 AE10 AR10 H11 V11 AH11 AV11 A12 L12 AA12 AG12 AL12 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 187 .

R Chapter 2: Pinout Tables Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100. LX160.xilinx. and LX200 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number D13 K13 M13 P13 AD13 AF13 AK13 AP13 G14 L14 N14 U14 W14 AE14 AG14 AJ14 AU14 K15 M15 P15 V15 Y15 AD15 AF15 AK15 C16 N16 U16 W16 AC16 AE16 AN16 F17 T17 V17 AF17 AT17 J18 188 www.4) September 30. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

and LX200 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number W18 AC18 AJ18 AW18 B19 M19 V19 AB19 AD19 AM19 E20 R20 AE20 AR20 H21 T21 V21 AB21 AH21 AV21 A22 L22 U22 AA22 AL22 D23 P23 AB23 AD23 AP23 G24 R24 U24 AA24 AC24 AG24 AU24 K25 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100.com 189 .4) September 30. LX160.

and LX200 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number P25 T25 Y25 AB25 AF25 AH25 AK25 C26 L26 N26 R26 AA26 AC26 AG26 AJ26 AN26 F27 K27 P27 T27 AF27 AH27 AK27 AT27 J28 N28 W28 AJ28 AW28 B29 M29 AB29 AM29 E30 R30 AE30 AR30 H31 190 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 . LX160.R Chapter 2: Pinout Tables Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100.4) September 30.xilinx.

4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100.xilinx. 2005 www.com 191 . and LX200 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number V31 AH31 AV31 A32 L32 AA32 AL32 D33 P33 AD33 AP33 G34 U34 AG34 AU34 K35 Y35 AK35 C36 N36 AC36 AN36 F37 T37 AF37 AT37 A38 J38 W38 AJ38 AW38 B39 M39 AB39 AM39 AV39 N/A VCCAUX H8 Virtex-4 Packaging and Pinout Specification UG075 (v2. LX160.

LX160. and LX200 Devices (Continued) Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number Y8 L9 AC9 P10 AF10 U11 AJ11 K12 Y12 AM12 J15 AL15 H18 AK18 AA19 AN19 G21 W21 K22 AM22 J25 AL25 H28 Y28 AK28 L29 AC29 P30 AF30 U31 AJ31 Y32 AM32 R7 AE7 K8 V8 AH8 192 www. 2005 .R Chapter 2: Pinout Tables Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.4) September 30.

xilinx. LX160.com 193 . and LX200 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AM8 N9 AA9 F10 T10 AD10 AP10 J11 W11 AG11 M12 AB12 AD12 AH12 AK12 L13 N13 R13 AE13 AG13 AN13 H14 K14 M14 P14 V14 Y14 AD14 AF14 AH14 AK14 L15 N15 U15 W15 AA15 AC15 AE15 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100. 2005 www.

and LX200 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AG15 AJ15 M16 P16 T16 V16 AD16 AF16 AM16 G17 U17 W17 AC17 AE17 AJ17 AR17 K18 V18 AB18 N19 R19 W19 AC19 AE19 F20 V20 AB20 AD20 AP20 R21 U21 AA21 AE21 AG21 V22 AB22 AD22 AK22 194 www. 2005 .R Chapter 2: Pinout Tables Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100. LX160.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

com 195 . 2005 www. LX160.xilinx.4) September 30. and LX200 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number E23 L23 R23 U23 AA23 AC23 AN23 H24 P24 T24 AB24 AD24 AF24 AH24 L25 N25 R25 U25 W25 AA25 AC25 AG25 AJ25 K26 M26 P26 T26 Y26 AB26 AF26 AH26 AK26 AM26 G27 N27 R27 AE27 AG27 Virtex-4 Packaging and Pinout Specification UG075 (v2.FF1513 Flip-Chip Fine-Pitch BGA Package R Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1513 Package — LX100.

SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. 3. and LX200 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AJ27 K28 M28 T28 V28 AH28 N29 AA29 AL29 F30 T30 AD30 AP30 W31 AG31 H32 M32 AB32 AK32 R33 AE33 1.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 5. 2005 . This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. 196 www. ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). 2.R Chapter 2: Pinout Tables Table 2-7: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF1513 Package — LX100. Connect this reserved pin to 2. 4. Connect this reserved pin to GND.4) September 30. LX160.

Table 2-8: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF1517 Package — FX140 and FX100 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number V23 W20 Y16 W22 V24 Y17 Y19 Y18 W24 Y22 Y21 AA16 Y23 AB16 AA18 Y24 AA20 AB17 E18 E19 No Connects in FX100 Devices 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 L24 K23 D17 E17 K24 J24 L16 M16 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.FF1517 Flip-Chip Fine-Pitch BGA Package R FF1517 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-8. visit www. The “No Connect” column in Table 2-8 shows pins that are not available in FX100 devices.com 197 . ASCII package pinout files are also available for download from the Xilinx website. To be assured of having the very latest Virtex-4 pinout information.com and check for any updates to this document. Virtex-4 XC4VFX140 and XC4VFX100 devices are available in the FF1517 flip-chip fine-pitch BGA package.xilinx.xilinx. 2005 www.

R Chapter 2: Pinout Tables Table 2-8: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 IO_L9P_GC_LC_1 IO_L9N_GC_LC_1 IO_L10P_GC_LC_1 IO_L10N_GC_LC_1 IO_L11P_GC_LC_1 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 Pin Number H24 H23 J16 K16 M25 N24 G15 H15 M21 N20 N19 P19 F21 E21 R18 P17 G22 G21 N18 M17 J22 H22 L18 M18 N23 N22 K18 K17 M23 L23 C18 C17 G23 F23 H17 J17 E23 No Connects in FX100 Devices 198 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 .xilinx.

4) September 30.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 1 1 1 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L23N_LC_1 IO_L24P_LC_1 IO_L24N_LC_1 Pin Number E22 G17 G16 No Connects in FX100 Devices 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 IO_L9P_GC_CC_LC_2 IO_L9N_GC_CC_LC_2 IO_L10P_GC_LC_2 IO_L10N_GC_LC_2 IO_L11P_GC_LC_2 IO_L11N_GC_LC_2 IO_L12P_GC_LC_2 IO_L12N_GC_VREF_LC_2 IO_L13P_GC_LC_2 IO_L13N_GC_LC_2 IO_L14P_GC_LC_2 IO_L14N_GC_LC_2 IO_L15P_GC_LC_2 IO_L15N_GC_LC_2 IO_L16P_GC_LC_2 IO_L16N_GC_LC_2 AM25 AN25 AL16 AK16 AN24 AM23 AJ16 AH15 AL24 AL23 AR17 AP17 AJ24 AK24 AM17 AM16 AF23 AE22 AG18 AH17 AR22 AR21 AR19 AR18 AH22 AG21 AP19 AN19 AG22 AF21 AG20 AH19 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.com 199 . 2005 www.

4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .R Chapter 2: Pinout Tables Table 2-8: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L17P_LC_2 IO_L17N_LC_2 IO_L18P_LC_2 IO_L18N_LC_2 IO_L19P_LC_2 IO_L19N_LC_2 IO_L20P_LC_2 IO_L20N_VREF_LC_2 IO_L21P_LC_2 IO_L21N_LC_2 IO_L22P_LC_2 IO_L22N_LC_2 IO_L23P_VRN_LC_2 IO_L23N_VRP_LC_2 IO_L24P_CC_LC_2 IO_L24N_CC_LC_2 Pin Number AH24 AH23 AK17 AJ17 AT23 AU23 AG17 AG16 AN23 AR23 AN18 AN17 AK23 AJ22 AM18 AL18 No Connects in FX100 Devices 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 J20 J19 K19 L19 H20 H19 G20 F20 L21 L20 F19 F18 K21 J21 G18 H18 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 AP22 AP21 200 www.xilinx.

com 201 .FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 Pin Number AN20 AP20 AM22 AN22 AL20 AL19 AK21 AL21 AK19 AJ19 AJ21 AJ20 AM21 AM20 No Connects in FX100 Devices 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 (1) IO_L2P_ADC6_5 (1) IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 (1) (1) (1) (1) C28 C27 K28 L28 K29 L29 G28 H28 J29 H29 E28 F28 E29 F29 J27 K27 G31 F31 D26 E26 E31 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 See footnote #1 IO_L5N_ADC4_5 (1) IO_L6P_ADC3_5 (1) IO_L6N_ADC3_5 (1) IO_L7P_ADC2_5 (1) IO_L7N_ADC2_5 (1) IO_L8P_CC_ADC1_LC_5 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.4) September 30.

R Chapter 2: Pinout Tables Table 2-8: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 Pin Number D31 G25 H25 L31 L30 F25 F24 K31 J31 C25 D25 D29 C29 G27 H27 J30 H30 D27 E27 G30 F30 J26 K26 D30 C30 F26 G26 E32 D32 M28 M27 G33 G32 L26 M26 F33 E33 No Connects in FX100 Devices 202 www. 2005 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.

FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 5 5 5 5 5 5 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 Pin Number D24 E24 C33 C32 C24 C23 No Connects in FX100 Devices 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 C10 D10 H10 J10 J11 K11 F10 G10 F11 G11 H9 J9 D11 E11 E9 F9 F13 E13 C8 C7 C13 C12 D7 E7 J14 H14 F6 F5 F14 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.com 203 .xilinx.4) September 30.

2005 .4) September 30.xilinx.R Chapter 2: Pinout Tables Table 2-8: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number E14 D6 E6 K13 J12 K9 L10 H12 G12 C9 D9 E12 D12 G8 H8 H13 G13 E8 F8 D14 C14 C5 D5 D15 C15 E4 F4 F16 F15 C4 D4 E16 D16 E3 F3 No Connects in FX100 Devices 204 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 www.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 IO_L26N_SM6_7 (2) (2) (2) Pin Number AT31 AU31 AR29 AT29 AP31 AR31 AN29 AP29 AL30 AM30 AT30 AU30 AN30 AP30 AK29 AL29 AP32 AR32 AU28 AU27 AM32 AN32 AT28 AR28 AJ30 AK31 AN28 AN27 AL31 AM31 AM28 AL28 AP37 AR37 AT24 AR24 AT36 No Connects in FX100 Devices See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 IO_L27P_SM5_7 (2) IO_L27N_SM5_7 (2) IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 (2) IO_L29N_SM4_7 IO_L30P_SM3_7 IO_L30N_SM3_7 IO_L31P_SM2_7 IO_L31N_SM2_7 IO_L32P_SM1_7 IO_L32N_SM1_7 IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 (2) (2) (2) (2) (2) (2) (2) See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 See footnote #2 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx.com 205 .

4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AU36 AU25 AT25 AP36 AR36 AP25 AP24 AP35 AP34 AU26 AT26 AT35 AU35 AR26 AP26 AR34 AT34 AR27 AP27 AU33 AU32 AM27 AM26 AR33 AT33 AK27 AL26 No Connects in FX100 Devices 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 AL13 AM13 AP11 AR11 AR14 AR13 AL11 AM11 206 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .xilinx.

xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 Pin Number AT14 AT13 AP12 AR12 AU13 AU12 AK11 AJ11 AN14 AP14 AP10 AN10 AK13 AK12 AJ10 AJ9 AJ12 AH12 AM10 AL10 AN13 AN12 AT11 AU11 AH14 AH13 AR7 AP7 AT18 AU17 AU8 AU7 AT16 AU16 AT8 AR8 AP16 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.com 207 .4) September 30. 2005 www.

R Chapter 2: Pinout Tables Table 2-8: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AR16 AN8 AN7 AT15 AU15 AT9 AR9 AN15 AP15 AP9 AN9 AM15 AL14 AL9 AK9 AJ14 AK14 AU10 AT10 No Connects in FX100 Devices 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 N33 M33 H37 G37 R32 P32 P31 P30 R31 T31 M35 L35 R33 T33 N35 N34 208 www. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

com 209 .4) September 30. 2005 www.xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 Pin Number K32 J32 D34 C34 G35 F35 D35 C35 E37 D37 F34 E34 G36 F36 H33 H32 J35 H35 E36 D36 L34 K34 J34 H34 J37 J36 N30 M31 N32 M32 L33 K33 T30 T29 U33 U32 U31 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank 9 9 9 9 9 9 9 9 9 9 9 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9 Pin Number U30 U27 U26 V28 U28 W26 V25 V30 V29 W27 V27 No Connects in FX100 Devices 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 L6 M6 M3 N3 K4 L4 N5 P5 N7 P7 P6 R6 N4 P4 R8 R7 N12 M11 M10 N10 G7 H7 L8 M7 210 www. 2005 .

xilinx. 2005 www.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 Pin Number P11 R11 J6 K6 P12 R12 G3 H3 G6 G5 P10 P9 K8 K7 H4 J4 H5 J5 L5 M5 N9 N8 K3 L3 T11 U11 R4 T4 T13 U12 T10 T9 R3 T3 T8 U8 T6 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.com 211 .

2005 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-8: Bank 10 10 10 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L31N_10 IO_L32P_10 IO_L32N_10 Pin Number T5 U10 V9 No Connects in FX100 Devices 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 IO_L17P_11 IO_L17N_11 IO_L18P_11 IO_L18N_11 IO_L19P_11 IO_L19N_11 IO_L20P_11 IO_L20N_VREF_11 IO_L21P_11 IO_L21N_11 IO_L22P_11 IO_L22N_11 IO_L23P_VRN_11 IO_L23N_VRP_11 IO_L24P_CC_LC_11 IO_L24N_CC_LC_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11 AG33 AG32 AH34 AJ34 AJ37 AK37 AJ36 AK36 AF30 AG30 AL36 AM36 AH33 AJ32 AK34 AL34 AC30 AC29 AC28 AD27 AD35 AD34 AC32 AB31 AD31 AD30 AE37 AD37 AD29 AE29 AE36 AD36 212 www.4) September 30.

com 213 .xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 IO_L12N_VREF_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_11 IO_L15P_11 IO_L15N_11 IO_L16P_11 IO_L16N_11 IO_L25P_CC_LC_11 IO_L25N_CC_LC_11 IO_L26P_11 IO_L26N_11 IO_L27P_11 IO_L27N_11 IO_L28P_11 IO_L28N_VREF_11 IO_L29P_11 IO_L29N_11 IO_L30P_11 IO_L30N_11 IO_L31P_11 IO_L31N_11 IO_L32P_11 IO_L32N_11 Pin Number AE32 AD32 AF35 AG35 AF36 AG36 AE34 AF34 AG37 AH37 AF31 AG31 AF33 AE33 AH35 AJ35 AF29 AE28 AN35 AN34 AM37 AN37 AH30 AH29 AL35 AM35 AM33 AN33 AK33 AK32 AG28 AF28 No Connects in FX100 Devices 12 12 12 IO_L17P_12 IO_L17N_12 IO_L18P_12 AM6 AL6 AH7 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

R Chapter 2: Pinout Tables Table 2-8: Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 IO_L21N_12 IO_L22P_12 IO_L22N_12 IO_L23P_VRN_12 IO_L23N_VRP_12 IO_L24P_CC_LC_12 IO_L24N_CC_LC_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 Pin Number AG7 AG10 AF10 AM5 AL5 AT4 AR4 AK6 AJ6 AR6 AP6 AH8 AG8 AB12 AB11 AB10 AC10 AA14 AA13 AC9 AC8 AC12 AD11 AD10 AD9 AC13 AB13 AD7 AC7 AF9 AF8 AE8 AE7 AC14 AB15 AG6 AG5 No Connects in FX100 Devices 214 www.xilinx.4) September 30. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx.4) September 30. 2005 www.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 IO_L27P_12 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 Pin Number AN3 AM3 AJ5 AH5 AP4 AN4 AL4 AL3 AU5 AT5 AK7 AJ7 AH10 AH9 AT3 AR3 AM8 AM7 AP5 AN5 AU6 AT6 AL8 AK8 No Connects in FX100 Devices 13 13 13 13 13 13 13 13 13 13 13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 AA36 AB36 AA35 AB35 W30 W29 AB37 AC37 Y32 Y31 AB23 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 215 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .4) September 30.xilinx.R Chapter 2: Pinout Tables Table 2-8: Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 IO_L24N_CC_LC_13 IO_L1P_13 IO_L1N_13 IO_L2P_13 IO_L2N_13 IO_L3P_13 IO_L3N_13 IO_L4P_13 IO_L4N_VREF_13 IO_L5P_13 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 Pin Number AA23 AA33 AB33 AA25 AA24 N37 M37 K37 K36 R36 P36 M36 L36 R37 P37 R34 P35 U36 T36 T35 T34 V37 U37 V35 U35 V34 V33 W37 Y37 W36 Y36 W32 Y33 W35 W34 Y34 AA34 No Connects in FX100 Devices 216 www.

com 217 .FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 IO_L26N_13 IO_L27P_13 IO_L27N_13 IO_L28P_13 IO_L28N_VREF_13 IO_L29P_13 IO_L29N_13 IO_L30P_13 IO_L30N_13 IO_L31P_13 IO_L31N_13 IO_L32P_13 IO_L32N_13 Pin Number AC35 AC34 AA26 Y26 AA31 AA30 AC25 AC24 AB28 AB27 AB26 AB25 AA29 Y29 AA28 Y27 No Connects in FX100 Devices 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 AF4 AE4 AC5 AB5 W17 W16 AD4 AC4 W14 Y14 AB7 AA6 W12 W11 AF3 AE3 U6 U5 V3 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx. 2005 www.

R Chapter 2: Pinout Tables Table 2-8: Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_LC_14 IO_L8N_CC_LC_14 IO_L9P_CC_LC_14 IO_L9N_CC_LC_14 IO_L10P_14 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 Pin Number U3 U15 V14 W4 V4 Y6 W6 W5 V5 U16 V17 W7 V7 AC3 AB3 Y4 Y3 V13 V12 AA5 AA4 Y11 W10 Y9 W9 V15 W15 Y8 Y7 AJ4 AH4 AD6 AD5 Y13 Y12 AA9 AA8 No Connects in FX100 Devices 218 www.xilinx. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 www.xilinx.com 219 .4) September 30.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 14 14 14 14 14 14 14 14 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description IO_L29P_14 IO_L29N_14 IO_L30P_14 IO_L30N_14 IO_L31P_14 IO_L31N_14 IO_L32P_14 IO_L32N_14 Pin Number AK4 AK3 AH3 AG3 AA11 AA10 AE6 AF5 No Connects in FX100 Devices 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 4 4 5 5 5 VCCO_0 (3) VCCO_0 VCCO_0 (3) (3) AA17 Y20 W23 H16 L17 D18 P18 N21 F22 J23 M24 AF22 AT22 AJ23 AM24 AH16 AL17 AP18 AU18 AG19 G19 K20 AK20 AN21 D22 E25 H26 See footnote #3 See footnote #3 See footnote #3 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 Virtex-4 Packaging and Pinout Specification UG075 (v2.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 9 9 9 9 9 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 Pin Number L27 D28 G29 K30 C31 F32 C3 E5 D8 G9 K10 C11 F12 J13 E15 AR25 AL27 AP28 AU29 AK30 AN31 AT32 AR35 AU37 AP8 AU9 AK10 AN11 AT12 AJ13 AM14 AR15 V26 U29 N31 T32 J33 No Connects in FX100 Devices 220 www.

xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank 9 9 9 9 9 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 13 13 13 13 13 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 Pin Number M34 E35 H36 C37 L37 J3 M4 R5 H6 L7 P8 U9 N11 T12 AD28 AG29 AC31 AF32 AJ33 AM34 AE35 AH36 AL37 AU3 AM4 AR5 AH6 AL7 AD8 AG9 AC11 AB14 AB24 AA27 Y30 W33 AB34 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.com 221 . 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .xilinx.R Chapter 2: Pinout Tables Table 2-8: Bank 13 13 13 14 14 14 14 14 14 14 14 14 FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCO_13 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 Pin Number R35 V36 AA37 W3 AJ3 AB4 AE5 V6 AA7 Y10 W13 V16 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_101 RXPPADA_101 VTRXA_101 RXNPADA_101 AVCCAUXMGT_101 AVCCAUXTX_101 VTTXA_101 TXPPADA_101 TXNPADA_101 VTTXB_101 TXPPADB_101 TXNPADB_101 AVCCAUXRXB_101 RXPPADB_101 VTRXB_101 RXNPADB_101 B22 A21 A23 A22 B29 B26 B24 A24 A25 B27 A26 A27 B30 A29 A28 A30 N/A N/A N/A N/A N/A N/A AVCCAUXRXA_102 RXPPADA_102 VTRXA_102 RXNPADA_102 AVCCAUXMGT_102 AVCCAUXTX_102 B32 A31 A33 A32 C38 B36 222 www.4) September 30.

com 223 .4) September 30.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VTTXA_102 TXPPADA_102 TXNPADA_102 VTTXB_102 TXPPADB_102 TXNPADB_102 AVCCAUXRXB_102 RXPPADB_102 VTRXB_102 RXNPADB_102 MGTCLK_P_102 MGTCLK_N_102 Pin Number B34 A34 A35 B37 A36 A37 D38 C39 B38 D39 F39 G39 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_103 RXPPADA_103 VTRXA_103 RXNPADA_103 AVCCAUXMGT_103 AVCCAUXTX_103 VTTXA_103 TXPPADA_103 TXNPADA_103 VTTXB_103 TXPPADB_103 TXNPADB_103 AVCCAUXRXB_103 RXPPADB_103 VTRXB_103 RXNPADB_103 K38 J39 L39 K39 U38 P38 M38 M39 N39 R38 P39 R39 V38 U39 T39 V39 N/A N/A N/A N/A N/A N/A AVCCAUXRXA_104 RXPPADA_104 VTRXA_104 RXNPADA_104 AVCCAUXMGT_104 AVCCAUXTX_104 AA38 Y39 AB39 AA39 AH38 AE38 NC NC NC NC NC NC Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.

xilinx.4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VTTXA_104 TXPPADA_104 TXNPADA_104 VTTXB_104 TXPPADB_104 TXNPADB_104 AVCCAUXRXB_104 RXPPADB_104 VTRXB_104 RXNPADB_104 Pin Number AC38 AC39 AD39 AF38 AE39 AF39 AJ38 AH39 AG39 AJ39 No Connects in FX100 Devices NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_105 RXPPADA_105 VTRXA_105 RXNPADA_105 AVCCAUXMGT_105 AVCCAUXTX_105 VTTXA_105 TXPPADA_105 TXNPADA_105 VTTXB_105 TXPPADB_105 TXNPADB_105 AVCCAUXRXB_105 RXPPADB_105 VTRXB_105 RXNPADB_105 MGTCLK_P_105 MGTCLK_N_105 RTERM_105 MGTVREF_105 AM38 AL39 AN39 AM39 AV37 AT38 AP38 AP39 AR39 AU38 AT39 AU39 AV36 AW37 AV38 AW36 AW34 AW33 AV34 AV32 N/A N/A N/A N/A AVCCAUXRXA_106 RXPPADA_106 VTRXA_106 RXNPADA_106 AV30 AW31 AW29 AW30 224 www. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description AVCCAUXMGT_106 AVCCAUXTX_106 VTTXA_106 TXPPADA_106 TXNPADA_106 VTTXB_106 TXPPADB_106 TXNPADB_106 AVCCAUXRXB_106 RXPPADB_106 VTRXB_106 RXNPADB_106 Pin Number AV22 AV25 AV28 AW28 AW27 AV24 AW25 AW24 AV21 AW22 AW23 AW21 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_109 RXPPADA_109 VTRXA_109 RXNPADA_109 AVCCAUXMGT_109 AVCCAUXTX_109 VTTXA_109 TXPPADA_109 TXNPADA_109 VTTXB_109 TXPPADB_109 TXNPADB_109 AVCCAUXRXB_109 RXPPADB_109 VTRXB_109 RXNPADB_109 AV10 AW9 AW11 AW10 AV18 AV15 AV12 AW12 AW13 AV16 AW15 AW16 AV19 AW18 AW17 AW19 N/A N/A N/A N/A N/A N/A AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 AM2 AL1 AN1 AM1 AV3 AT2 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.com 225 .xilinx. 2005 www.

xilinx.4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 MGTCLK_N_110 RTERM_110 MGTVREF_110 Pin Number AP2 AP1 AR1 AU2 AT1 AU1 AV4 AW3 AV2 AW4 AW6 AW7 AV6 AV8 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_111 RXPPADA_111 VTRXA_111 RXNPADA_111 AVCCAUXMGT_111 AVCCAUXTX_111 VTTXA_111 TXPPADA_111 TXNPADA_111 VTTXB_111 TXPPADB_111 TXNPADB_111 AVCCAUXRXB_111 RXPPADB_111 VTRXB_111 RXNPADB_111 AA2 Y1 AB1 AA1 AH2 AE2 AC2 AC1 AD1 AF2 AE1 AF1 AJ2 AH1 AG1 AJ1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC N/A N/A N/A N/A AVCCAUXRXA_112 RXPPADA_112 VTRXA_112 RXNPADA_112 K2 J1 L1 K1 226 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .

xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description AVCCAUXMGT_112 AVCCAUXTX_112 VTTXA_112 TXPPADA_112 TXNPADA_112 VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 Pin Number U2 P2 M2 M1 N1 R2 P1 R1 V2 U1 T1 V1 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_113 RXPPADA_113 VTRXA_113 RXNPADA_113 AVCCAUXMGT_113 AVCCAUXTX_113 VTTXA_113 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 B8 A9 A7 A8 C2 B4 B6 A6 A5 B3 A4 A3 D2 C1 B2 D1 F1 G1 N/A N/A N/A N/A AVCCAUXRXA_114 RXPPADA_114 VTRXA_114 RXNPADA_114 B18 A19 A17 A18 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 227 .4) September 30. 2005 www.

xilinx. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description AVCCAUXMGT_114 AVCCAUXTX_114 VTTXA_114 TXPPADA_114 TXNPADA_114 VTTXB_114 TXPPADB_114 TXNPADB_114 AVCCAUXRXB_114 RXPPADB_114 VTRXB_114 RXNPADB_114 Pin Number B11 B14 B16 A16 A15 B13 A14 A13 B10 A11 A12 A10 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_104 GNDA_104 B20 B21 B23 B25 B28 B31 B33 B35 A38 E38 F38 G38 B39 E39 H39 H38 J38 L38 N38 T38 W38 Y38 AB38 228 www.4) September 30.

4) September 30.xilinx.com 229 . 2005 www.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GNDA_104 GNDA_104 GNDA_104 GNDA_104 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 Pin Number AD38 AG38 AK38 W39 AV35 AL38 AN38 AR38 AW38 AK39 AV39 AW20 AV23 AV26 AW26 AV27 AV29 AV31 AW32 AV33 AW35 AV9 AV11 AV13 AV14 AW14 AV17 AV20 AK1 AV1 AL2 AN2 AR2 AW2 AV5 AW5 AV7 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx.4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GNDA_110 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 Pin Number AW8 W1 Y2 AB2 AD2 AG2 AK2 H2 J2 L2 N2 T2 W2 B1 E1 H1 A2 E2 F2 G2 B5 B7 B9 B12 B15 B17 B19 A20 No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A VREFN_SM (4) VREFP_SM AVDD_SM VN_SM VP_SM (4) (5) AT21 AT20 AT19 AU21 AU20 AU19 See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 (4) (4) (4) AVSS_SM 230 www. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

com 231 .FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VREFN_ADC (4) VREFP_ADC AVDD_ADC VN_ADC (4) (5) Pin Number D21 D20 D19 C21 C20 C19 No Connects in FX100 Devices See footnote #4 See footnote #4 See footnote #5 See footnote #4 See footnote #4 See footnote #4 (4) VP_ADC (4) AVSS_ADC (4) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D3 P3 AA3 AD3 AP3 G4 U4 AG4 AU4 K5 Y5 AK5 C6 N6 AC6 AN6 F7 T7 AF7 AT7 J8 W8 AJ8 M9 AB9 AM9 E10 R10 AE10 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.xilinx.

2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AR10 H11 V11 AF11 AH11 L12 AA12 AE12 AG12 AL12 D13 M13 P13 AD13 AF13 AP13 G14 L14 N14 R14 U14 AE14 AG14 AU14 K15 M15 P15 T15 Y15 AD15 AF15 AK15 C16 N16 R16 AC16 AE16 No Connects in FX100 Devices 232 www.xilinx.4) September 30.

com 233 .4) September 30.xilinx.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AN16 F17 T17 AD17 AF17 AT17 J18 U18 W18 AC18 AE18 AJ18 M19 T19 V19 AB19 AD19 AF19 AM19 E20 R20 U20 AC20 AE20 AR20 H21 P21 T21 V21 AB21 AD21 AH21 C22 L22 R22 U22 AA22 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AC22 AL22 AU22 D23 P23 T23 AD23 AP23 G24 R24 U24 AE24 AG24 AU24 K25 P25 T25 Y25 AD25 AF25 AH25 AK25 C26 N26 R26 AC26 AE26 AG26 AJ26 AN26 F27 P27 T27 AF27 AH27 AT27 J28 No Connects in FX100 Devices 234 www.xilinx.4) September 30. 2005 .

4) September 30. 2005 www.xilinx.com 235 .FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number N28 R28 W28 AJ28 M29 P29 AB29 AM29 E30 R30 AE30 AR30 H31 V31 AH31 L32 AA32 AL32 D33 P33 AD33 AP33 G34 U34 AG34 AU34 K35 Y35 AK35 C36 N36 AC36 AN36 F37 T37 AF37 AT37 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.

R Chapter 2: Pinout Tables Table 2-8: Bank FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description Pin Number No Connects in FX100 Devices N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT J7 U7 M8 AB8 R9 AE9 V10 K12 AM12 J15 AL15 AK18 AA19 W21 K22 J25 AL25 AK28 R29 M30 AB30 AE31 V32 AH32 AC33 AL33 AB6 AF6 V8 L9 L11 AE11 AG11 M12 AD12 236 www.xilinx. 2005 .4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 www.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AF12 L13 N13 R13 U13 AE13 AG13 K14 M14 P14 T14 AD14 AF14 L15 N15 R15 AA15 AC15 AE15 AG15 AJ15 P16 T16 AD16 AF16 N17 R17 U17 AC17 AE17 T18 V18 AB18 AD18 AF18 AH18 R19 No Connects in FX100 Devices Virtex-4 Packaging and Pinout Specification UG075 (v2.com 237 .xilinx.4) September 30.

xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.R Chapter 2: Pinout Tables Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number U19 W19 AC19 AE19 M20 P20 T20 V20 AB20 AD20 AF20 AH20 R21 U21 AA21 AC21 AE21 M22 P22 T22 V22 AB22 AD22 AK22 R23 U23 AC23 AE23 AG23 P24 T24 AD24 AF24 L25 N25 R25 U25 No Connects in FX100 Devices 238 www. 2005 .

ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions. Connect this reserved pin to 2. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. 3. 2. 5. SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions.FF1517 Flip-Chip Fine-Pitch BGA Package R Table 2-8: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF1517 Package — FX140 and FX100 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number W25 AE25 AG25 AJ25 P26 T26 AD26 AF26 AH26 AK26 N27 R27 AC27 AE27 AG27 AJ27 P28 T28 Y28 AH28 N29 AJ29 W31 AJ31 AB32 P34 No Connects in FX100 Devices 1.com 239 . 4.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). Connect this reserved pin to GND.xilinx.4) September 30. Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

only Virtex-4 XC4VFX140 devices are available in the FF1760 flipchip fine-pitch BGA package.xilinx. Table 2-9: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FF1760 Package — FX140 Devices Pin Description HSWAPEN_0 CCLK_0 D_IN_0 PROG_B_0 INIT_B_0 CS_B_0 DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 TMS_0 M0_0 TDO_0 TCK_0 M1_0 DOUT_BUSY_0 TDI_0 TDN_0 TDP_0 Pin Number V24 V23 W21 V25 Y22 Y20 W23 AC19 W25 Y24 AE20 AD18 AB22 AC21 AE18 AC23 AD22 AE19 H21 G21 1 1 1 1 1 1 1 1 1 1 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 K25 J25 H18 J18 P26 N26 J17 K17 T26 R25 240 www. ASCII package pinout files are also available for download from the Xilinx website.4) September 30. To be assured of having the very latest Virtex-4 pinout information.com and check for any updates to this document. visit www.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables FF1760 Flip-Chip Fine-Pitch BGA Package As shown in Table 2-9. 2005 .

com 241 .xilinx.4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 IO_L9P_GC_LC_1 IO_L9N_GC_LC_1 IO_L10P_GC_LC_1 IO_L10N_GC_LC_1 IO_L11P_GC_LC_1 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 IO_L23N_LC_1 IO_L24P_LC_1 Pin Number G17 G16 R27 P27 H16 J16 J23 H23 P20 R19 G23 G22 F21 F20 E23 E22 H20 H19 M24 L25 M19 N19 K24 K23 L19 K18 H24 G24 F19 G19 F24 F22 N18 P18 N25 M26 M18 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

2005 .xilinx.4) September 30.R Chapter 2: Pinout Tables Table 2-9: Bank 1 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L24N_LC_1 Pin Number L17 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_2 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 IO_L9P_GC_CC_LC_2 IO_L9N_GC_CC_LC_2 IO_L10P_GC_LC_2 IO_L10N_GC_LC_2 IO_L11P_GC_LC_2 IO_L11N_GC_LC_2 IO_L12P_GC_LC_2 IO_L12N_GC_VREF_LC_2 IO_L13P_GC_LC_2 IO_L13N_GC_LC_2 IO_L14P_GC_LC_2 IO_L14N_GC_LC_2 IO_L15P_GC_LC_2 IO_L15N_GC_LC_2 IO_L16P_GC_LC_2 IO_L16N_GC_LC_2 IO_L17P_LC_2 IO_L17N_LC_2 IO_L18P_LC_2 AT27 AT26 AH16 AG16 AP27 AR27 AK17 AJ17 AP26 AP25 AK18 AJ18 AR25 AR24 AH18 AG17 AM24 AN25 AV21 AV20 AU23 AT22 AP20 AN20 AR23 AR22 AU21 AU19 AJ23 AK24 AT21 AT20 AN26 AM26 AN18 242 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx.com 243 .FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L18N_LC_2 IO_L19P_LC_2 IO_L19N_LC_2 IO_L20P_LC_2 IO_L20N_VREF_LC_2 IO_L21P_LC_2 IO_L21N_LC_2 IO_L22P_LC_2 IO_L22N_LC_2 IO_L23P_VRN_LC_2 IO_L23N_VRP_LC_2 IO_L24P_CC_LC_2 IO_L24N_CC_LC_2 Pin Number AM18 AL25 AL24 AT19 AR19 AJ25 AK25 AN19 AP18 AT24 AU24 AL19 AL17 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 P22 P21 M21 N21 L22 K22 L21 L20 P23 N23 J22 J21 M23 M22 J20 K20 4 4 4 4 4 4 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 AN23 AP23 AK20 AJ20 AM23 AM22 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-9: Bank 4 4 4 4 4 4 4 4 4 4 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 Pin Number AM21 AN21 AK22 AL22 AL21 AL20 AJ22 AJ21 AP22 AP21 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L1P_ADC7_5 (1) IO_L1N_ADC7_5 IO_L2P_ADC6_5 (1) (1) D27 E27 H31 G31 F29 G29 J31 J30 D28 E28 H30 H29 K32 K30 (1) (1) IO_L2N_ADC6_5 (1) IO_L3P_ADC5_5 (1) IO_L3N_ADC5_5 (1) IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 IO_L5N_ADC4_5 (1) (1) IO_L6P_ADC3_5 (1) IO_L6N_ADC3_5 (1) IO_L7P_ADC2_5 (1) IO_L7N_ADC2_5 (1) IO_L8P_CC_ADC1_LC_5 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 C26 D26 L32 L31 E25 F25 D31 C31 D25 D23 F32 E32 244 www.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 Pin Number H26 J26 G33 G32 J27 K27 C29 C28 C25 C24 E30 E29 F27 G27 C30 D30 H28 J28 F31 F30 F26 G26 D33 D32 K28 L27 G34 F34 L29 M28 E34 E33 M29 N29 C34 C33 P30 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.xilinx.4) September 30.com 245 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 .xilinx.R Chapter 2: Pinout Tables Table 2-9: Bank 5 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L32N_5 Pin Number P28 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 D18 C18 D16 C16 H13 G13 E15 D15 G14 F14 E14 E13 K12 J11 C15 C14 L12 M12 E12 D12 K14 J13 C11 D11 K15 J15 F10 F9 E18 D17 G9 H9 F16 F15 G12 246 www.

com 247 .xilinx.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 Pin Number F12 H15 H14 D13 C13 F17 E17 H10 J10 L11 K10 G11 H11 M11 N11 D10 E10 E20 E19 C10 C9 N13 P13 E9 E8 P12 P11 C8 D8 7 7 7 7 7 7 7 IO_L25P_CC_SM7_LC_7 (2) IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 (2) (2) AT31 AT30 AR30 AR29 AR32 AT32 AY29 IO_L26N_SM6_7 (2) IO_L27P_SM5_7 (2) IO_L27N_SM5_7 (2) IO_L28P_7 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

2005 .xilinx.R Chapter 2: Pinout Tables Table 2-9: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L28N_VREF_7 IO_L29P_SM4_7 (2) Pin Number AY28 AP33 AR33 AV30 AV29 AP32 AN31 AY30 AW30 AW32 AY32 AU28 AU27 AU32 AU31 AW28 AV28 AW31 AV31 AU29 AT29 AN33 AM32 AP30 AN29 AJ32 AJ31 AJ30 AK30 AK32 AL32 AV24 AV23 AW35 AY35 AV25 AU26 IO_L29N_SM4_7 (2) IO_L30P_SM3_7 (2) IO_L30N_SM3_7 (2) IO_L31P_SM2_7 IO_L31N_SM2_7 IO_L32P_SM1_7 (2) (2) (2) IO_L32N_SM1_7 (2) IO_L17P_7 IO_L17N_7 IO_L18P_7 IO_L18N_7 IO_L19P_7 IO_L19N_7 IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L1P_7 IO_L1N_7 IO_L2P_7 IO_L2N_7 IO_L3P_7 IO_L3N_7 IO_L4P_7 IO_L4N_VREF_7 IO_L5P_7 IO_L5N_7 IO_L6P_7 IO_L6N_7 248 www.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

com 249 .4) September 30. 2005 www.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L7P_7 IO_L7N_7 IO_L8P_CC_LC_7 IO_L8N_CC_LC_7 IO_L9P_CC_LC_7 IO_L9N_CC_LC_7 IO_L10P_7 IO_L10N_7 IO_L11P_7 IO_L11N_7 IO_L12P_7 IO_L12N_VREF_7 IO_L13P_7 IO_L13N_7 IO_L14P_7 IO_L14N_7 IO_L15P_7 IO_L15N_7 IO_L16P_7 IO_L16N_7 Pin Number AV35 AV34 AY25 AW25 AY34 AY33 AW26 AV26 AU34 AU33 AY27 AW27 AR34 AT34 AM31 AL31 AV33 AW33 AR28 AP28 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 AW20 AW18 AV15 AW15 AR14 AR13 AV16 AW16 AY19 AY18 AR12 AT12 AW17 AY17 AT14 AU14 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.xilinx.R Chapter 2: Pinout Tables Table 2-9: Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L17P_8 IO_L17N_8 IO_L18P_8 IO_L18N_8 IO_L19P_8 IO_L19N_8 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 IO_L5N_8 IO_L6P_8 IO_L6N_8 IO_L7P_8 IO_L7N_8 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 IO_L9N_CC_LC_8 IO_L10P_8 IO_L10N_8 IO_L11P_8 Pin Number AM12 AP12 AY15 AY14 AP15 AR15 AV14 AV13 AN13 AP13 AN11 AM11 AU17 AU16 AU13 AU12 AJ15 AJ13 AU9 AT9 AK14 AL14 AY10 AY9 AL15 AM14 AV10 AV9 AM16 AN15 AW11 AW10 AN16 AP16 AV11 AU11 AP17 250 www. 2005 .

xilinx.com 251 .4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 8 8 8 8 8 8 8 8 8 8 8 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 IO_L13N_8 IO_L14P_8 IO_L14N_8 IO_L15P_8 IO_L15N_8 IO_L16P_8 IO_L16N_8 Pin Number AR17 AW12 AY12 AU18 AV18 AW13 AY13 AT17 AT16 AT11 AT10 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 J38 J37 J36 J35 H39 H38 L35 L34 M36 L36 G39 G38 J40 H40 N34 N33 G36 F36 D35 C35 C39 C38 H34 H33 H36 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-9: Bank 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 Pin Number G37 K33 J33 E39 E38 D36 C36 M34 M32 F35 E35 E40 D40 D38 D37 F40 F39 F37 E37 P33 P32 K35 K34 R33 R32 V28 U29 N36 N35 W28 W27 T34 T32 V30 V29 U34 U33 252 www. 2005 .xilinx.4) September 30.

4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 9 9 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L32P_9 IO_L32N_9 Pin Number V31 U31 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 E4 F4 J5 K5 R12 R10 M7 M6 P10 N9 H3 J3 R15 R13 K4 K3 C6 D6 G6 H6 D7 E7 F6 F5 F7 G7 M9 M8 H8 J8 J7 J6 C5 C4 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.com 253 .xilinx.

xilinx. 2005 .4) September 30.R Chapter 2: Pinout Tables Table 2-9: Bank 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10 Pin Number D3 E3 P16 R17 K7 L7 D5 E5 H5 H4 L9 K8 G4 G3 N8 P8 R9 R8 T14 U14 N6 N5 L5 L4 M4 M3 U13 T12 N4 N3 11 11 11 11 11 11 IO_L17P_11 IO_L17N_11 IO_L18P_11 IO_L18N_11 IO_L19P_11 IO_L19N_11 AK34 AJ33 AP37 AP36 AL35 AL34 254 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

com 255 .FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L20P_11 IO_L20N_VREF_11 IO_L21P_11 IO_L21N_11 IO_L22P_11 IO_L22N_11 IO_L23P_VRN_11 IO_L23N_VRP_11 IO_L24P_CC_LC_11 IO_L24N_CC_LC_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11 IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 IO_L12N_VREF_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 Pin Number AR37 AT37 AR39 AR38 AV38 AW38 AT40 AT39 AY39 AY38 AK40 AK39 AF29 AG29 AH35 AH34 AL40 AL39 AK38 AK37 AG31 AF30 AJ35 AK35 AN40 AN39 AH33 AH31 AG27 AH26 AM39 AM38 AN38 AP38 AL37 AL36 AH30 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.4) September 30.

R Chapter 2: Pinout Tables Table 2-9: Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L14N_11 IO_L15P_11 IO_L15N_11 IO_L16P_11 IO_L16N_11 IO_L25P_CC_LC_11 IO_L25N_CC_LC_11 IO_L26P_11 IO_L26N_11 IO_L27P_11 IO_L27N_11 IO_L28P_11 IO_L28N_VREF_11 IO_L29P_11 IO_L29N_11 IO_L30P_11 IO_L30N_11 IO_L31P_11 IO_L31N_11 IO_L32P_11 IO_L32N_11 Pin Number AH28 AP40 AR40 AM36 AN36 AV40 AW40 AP35 AR35 AU39 AV39 AT36 AU36 AN35 AM34 AV36 AW36 AU38 AU37 AW37 AY37 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 IO_L21N_12 IO_L22P_12 IO_L22N_12 IO_L23P_VRN_12 IO_L23N_VRP_12 IO_L24P_CC_LC_12 AK10 AJ10 AT5 AT4 AF14 AF12 AR7 AT6 AY7 AW7 AV5 AV4 AY8 AW8 AP8 256 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 .xilinx.

xilinx.com 257 .4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L24N_CC_LC_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 Pin Number AP7 AP6 AP5 AG9 AF9 AE13 AE12 AR3 AP3 AM8 AM7 AL7 AK7 AD16 AD15 AR5 AR4 AY5 AY4 AU4 AU3 AH11 AG11 AH10 AF10 AU7 AT7 AW3 AV3 AE15 AE14 AK9 AK8 AV8 AU8 AV6 AU6 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.R Chapter 2: Pinout Tables Table 2-9: Bank 12 12 12 12 12 12 12 12 12 12 12 12 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L27P_12 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 Pin Number AR10 AR9 AM9 AL9 AP10 AN10 AW6 AW5 AL11 AJ11 AN9 AN8 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 IO_L24N_CC_LC_13 IO_L1P_13 IO_L1N_13 IO_L2P_13 IO_L2N_13 IO_L3P_13 IO_L3N_13 IO_L4P_13 IO_L4N_VREF_13 V33 W33 AA27 AA26 V34 Y34 U37 U36 U39 U38 W31 AA31 V36 W36 AC25 AB26 L40 L39 K38 K37 R35 P35 M37 L37 258 www. 2005 .4) September 30.

2005 www.xilinx.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L5P_13 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 IO_L26N_13 IO_L27P_13 IO_L27N_13 IO_L28P_13 IO_L28N_VREF_13 IO_L29P_13 IO_L29N_13 IO_L30P_13 IO_L30N_13 IO_L31P_13 Pin Number P37 P36 K40 K39 P38 N38 M39 M38 T36 T35 AB24 AA25 R39 R38 N40 N39 R40 P40 Y28 Y27 T40 T39 T37 R37 V39 V38 Y30 W30 V40 W40 AB28 AB27 W35 Y35 AB29 AA29 W38 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 259 .4) September 30.

4) September 30.R Chapter 2: Pinout Tables Table 2-9: Bank 13 13 13 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L31N_13 IO_L32P_13 IO_L32N_13 Pin Number W37 Y32 AA32 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_LC_14 IO_L8N_CC_LC_14 IO_L9P_CC_LC_14 AA5 AA4 Y5 W5 V13 W13 W8 W7 W10 V10 AB4 AB3 Y15 Y14 AC4 AC3 T11 T10 T9 U9 P6 P5 P3 R3 R7 T7 R5 R4 T6 U6 T5 T4 U4 260 www. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.

4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L9N_CC_LC_14 IO_L10P_14 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 IO_L29P_14 IO_L29N_14 IO_L30P_14 IO_L30N_14 IO_L31P_14 IO_L31N_14 IO_L32P_14 IO_L32N_14 Pin Number U3 V5 V4 V14 W15 V8 U7 Y4 Y3 W3 V3 V11 U11 W6 V6 Y10 Y8 AA7 Y7 AB9 AA9 AB6 AA6 Y12 W11 AC6 AC5 AA12 AA11 AB8 AB7 15 15 15 15 15 IO_L17P_15 IO_L17N_15 IO_L18P_15 IO_L18N_15 IO_L19P_15 AD37 AE37 AE30 AD30 AD40 Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.xilinx.com 261 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-9: Bank 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L19N_15 IO_L20P_15 IO_L20N_VREF_15 IO_L21P_15 IO_L21N_15 IO_L22P_15 IO_L22N_15 IO_L23P_VRN_15 IO_L23N_VRP_15 IO_L24P_CC_LC_15 IO_L24N_CC_LC_15 IO_L1P_15 IO_L1N_15 IO_L2P_15 IO_L2N_15 IO_L3P_15 IO_L3N_15 IO_L4P_15 IO_L4N_VREF_15 IO_L5P_15 IO_L5N_15 IO_L6P_15 IO_L6N_15 IO_L7P_15 IO_L7N_15 IO_L8P_CC_LC_15 IO_L8N_CC_LC_15 IO_L9P_CC_LC_15 IO_L9N_CC_LC_15 IO_L10P_15 IO_L10N_15 IO_L11P_15 IO_L11N_15 IO_L12P_15 IO_L12N_VREF_15 IO_L13P_15 IO_L13N_15 Pin Number AE40 AD38 AC38 AE39 AE38 AE35 AF36 AF40 AF39 AF37 AG37 AA36 AA35 AB32 AB31 Y38 Y37 AB34 AA34 Y40 Y39 AC29 AC28 AC35 AC33 AD32 AC31 AA40 AA39 AB37 AA37 AC36 AB36 AD33 AE33 AB39 AB38 262 www.xilinx.4) September 30. 2005 .

xilinx.4) September 30. 2005 www.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L14P_15 IO_L14N_15 IO_L15P_15 IO_L15N_15 IO_L16P_15 IO_L16N_15 IO_L25P_CC_LC_15 IO_L25N_CC_LC_15 IO_L26P_15 IO_L26N_15 IO_L27P_15 IO_L27N_15 IO_L28P_15 IO_L28N_VREF_15 IO_L29P_15 IO_L29N_15 IO_L30P_15 IO_L30N_15 IO_L31P_15 IO_L31N_15 IO_L32P_15 IO_L32N_15 Pin Number AE29 AD28 AC40 AC39 AD36 AD35 AF34 AG34 AF32 AE32 AG39 AG38 AG36 AH36 AH40 AJ40 AH39 AH38 AJ38 AJ37 AG33 AG32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 IO_L17P_16 IO_L17N_16 IO_L18P_16 IO_L18N_16 IO_L19P_16 IO_L19N_16 IO_L20P_16 IO_L20N_VREF_16 IO_L21P_16 IO_L21N_16 IO_L22P_16 IO_L22N_16 IO_L23P_VRN_16 IO_L23N_VRP_16 AG8 AG7 AJ3 AH3 AD13 AC13 AH5 AH4 AJ7 AJ6 AH6 AG6 AC16 AC15 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 263 .

4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .R Chapter 2: Pinout Tables Table 2-9: Bank 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L24P_CC_LC_16 IO_L24N_CC_LC_16 IO_L1P_16 IO_L1N_16 IO_L2P_16 IO_L2N_16 IO_L3P_16 IO_L3N_16 IO_L4P_16 IO_L4N_VREF_16 IO_L5P_16 IO_L5N_16 IO_L6P_16 IO_L6N_16 IO_L7P_16 IO_L7N_16 IO_L8P_CC_LC_16 IO_L8N_CC_LC_16 IO_L9P_CC_LC_16 IO_L9N_CC_LC_16 IO_L10P_16 IO_L10N_16 IO_L11P_16 IO_L11N_16 IO_L12P_16 IO_L12N_VREF_16 IO_L13P_16 IO_L13N_16 IO_L14P_16 IO_L14N_16 IO_L15P_16 IO_L15N_16 IO_L16P_16 IO_L16N_16 IO_L25P_CC_LC_16 IO_L25N_CC_LC_16 IO_L26P_16 Pin Number AK4 AK3 AC11 AB11 AC9 AC8 AB14 AA14 AD7 AD6 AA16 AA15 AE3 AD3 AA17 Y18 AD10 AD8 AF4 AE4 AE5 AD5 AD12 AB12 AF6 AF5 AE10 AE9 AG4 AG3 AB17 AB16 AF7 AE7 AJ8 AH8 AK5 264 www.

4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 16 16 16 16 16 16 16 16 16 16 16 16 16 FF1760 Package — FX140 Devices (Continued) Pin Description IO_L26N_16 IO_L27P_16 IO_L27N_16 IO_L28P_16 IO_L28N_VREF_16 IO_L29P_16 IO_L29N_16 IO_L30P_16 IO_L30N_16 IO_L31P_16 IO_L31N_16 IO_L32P_16 IO_L32N_16 Pin Number AJ5 AB18 AA19 AL5 AL4 AM6 AL6 AM4 AM3 AN6 AN5 AN4 AN3 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) VCCO_0 (3) AD19 Y21 AC22 W24 H17 L18 P19 G20 F23 J24 M25 R26 AT23 AJ24 AM25 AR26 AH17 AL18 AP19 AU20 K21 N22 AK21 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 265 .xilinx. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-9: Bank 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 FF1760 Package — FX140 Devices (Continued) Pin Description VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 Pin Number AN22 C23 E26 H27 L28 D29 P29 G30 K31 C32 F33 D9 G10 K11 C12 N12 F13 J14 E16 D19 AW24 AV27 AP29 AU30 AK31 AY31 AN32 AT33 AW34 AU10 AY11 AN12 AT13 AJ14 AW14 AM15 AR16 266 www.4) September 30. 2005 .xilinx.

4) September 30.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 8 8 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 FF1760 Package — FX140 Devices (Continued) Pin Description VCCO_8 VCCO_8 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 Pin Number AV17 AY20 V27 U30 N32 T33 J34 M35 E36 H37 D39 G40 C3 F3 J4 M5 E6 H7 L8 P9 T13 R16 AH27 AG30 AJ34 AM35 AR36 AV37 AL38 AP39 AU40 AY40 AT3 AW4 AR6 AV7 AL8 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 www.com 267 .

xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-9: Bank 12 12 12 12 12 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 15 15 15 16 16 16 16 16 FF1760 Package — FX140 Devices (Continued) Pin Description VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_15 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VCCO_16 Pin Number AP9 AG10 AK11 AF13 AE16 AB25 AA28 Y31 W34 R36 V37 L38 P39 U40 T3 W4 AB5 R6 V7 AA8 U10 Y11 W14 AD29 AC32 AF33 AB35 AE36 AH37 AA38 AD39 AG40 AF3 AJ4 AM5 AE6 AH7 268 www. 2005 .4) September 30.

xilinx.4) September 30. 2005 www.com 269 .FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank 16 16 16 16 FF1760 Package — FX140 Devices (Continued) Pin Description VCCO_16 VCCO_16 VCCO_16 VCCO_16 Pin Number AD9 AC12 AB15 AA18 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_101 RXPPADA_101 VTRXA_101 RXNPADA_101 AVCCAUXMGT_101 AVCCAUXTX_101 VTTXA_101 TXPPADA_101 TXNPADA_101 VTTXB_101 TXPPADB_101 TXNPADB_101 AVCCAUXRXB_101 RXPPADB_101 VTRXB_101 RXNPADB_101 B22 A21 A23 A22 B29 B26 B24 A24 A25 B27 A26 A27 B30 A29 A28 A30 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_102 RXPPADA_102 VTRXA_102 RXNPADA_102 AVCCAUXMGT_102 AVCCAUXTX_102 VTTXA_102 TXPPADA_102 TXNPADA_102 VTTXB_102 TXPPADB_102 TXNPADB_102 AVCCAUXRXB_102 RXPPADB_102 VTRXB_102 B32 A31 A33 A32 B39 B36 B34 A34 A35 B37 A36 A37 B40 A39 A38 Virtex-4 Packaging and Pinout Specification UG075 (v2.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 2: Pinout Tables Table 2-9: Bank N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description RXNPADB_102 MGTCLK_P_102 MGTCLK_N_102 Pin Number A40 C42 D42 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_103 RXPPADA_103 VTRXA_103 RXNPADA_103 AVCCAUXMGT_103 AVCCAUXTX_103 VTTXA_103 TXPPADA_103 TXNPADA_103 VTTXB_103 TXPPADB_103 TXNPADB_103 AVCCAUXRXB_103 RXPPADB_103 VTRXB_103 RXNPADB_103 G41 F42 H42 G42 P41 L41 J41 J42 K42 M41 L42 M42 R41 P42 N42 R42 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_104 RXPPADA_104 VTRXA_104 RXNPADA_104 AVCCAUXMGT_104 AVCCAUXTX_104 VTTXA_104 TXPPADA_104 TXNPADA_104 VTTXB_104 TXPPADB_104 TXNPADB_104 AVCCAUXRXB_104 RXPPADB_104 VTRXB_104 RXNPADB_104 U41 T42 V42 U42 AD41 AA41 W41 W42 Y42 AB41 AA42 AB42 AE41 AD42 AC42 AE42 270 www. 2005 .4) September 30.xilinx.

xilinx.com 271 .FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank FF1760 Package — FX140 Devices (Continued) Pin Description Pin Number N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_105 RXPPADA_105 VTRXA_105 RXNPADA_105 AVCCAUXMGT_105 AVCCAUXTX_105 VTTXA_105 TXPPADA_105 TXNPADA_105 VTTXB_105 TXPPADB_105 TXNPADB_105 AVCCAUXRXB_105 RXPPADB_105 VTRXB_105 RXNPADB_105 MGTCLK_P_105 MGTCLK_N_105 RTERM_105 MGTVREF_105 AG41 AF42 AH42 AG42 AP41 AL41 AJ41 AJ42 AK42 AM41 AL42 AM42 AR41 AP42 AN42 AR42 AW42 AY42 AW41 BA41 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_106 RXPPADA_106 VTRXA_106 RXNPADA_106 AVCCAUXMGT_106 AVCCAUXTX_106 VTTXA_106 TXPPADA_106 TXNPADA_106 VTTXB_106 TXPPADB_106 TXNPADB_106 AVCCAUXRXB_106 RXPPADB_106 VTRXB_106 AU41 AT42 BB40 AU42 BA34 BA37 BA39 BB39 BB38 BA36 BB37 BB36 BA33 BB34 BB35 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

4) September 30.xilinx. 2005 .R Chapter 2: Pinout Tables Table 2-9: Bank N/A FF1760 Package — FX140 Devices (Continued) Pin Description RXNPADB_106 Pin Number BB33 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT BA31 BB32 BB30 BB31 BA24 BA27 BA29 BB29 BB28 BA26 BB27 BB26 BA23 BB24 BB25 BB23 BA14 BB13 BB15 BB14 BA21 BA18 BA16 BB16 BB17 BA19 BB18 BB19 BA22 BB21 BB20 BB22 N/A N/A AVCCAUXRXA_109 RXPPADA_109 BA4 BB3 272 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

2005 www.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description VTRXA_109 RXNPADA_109 AVCCAUXMGT_109 AVCCAUXTX_109 VTTXA_109 TXPPADA_109 TXNPADA_109 VTTXB_109 TXPPADB_109 TXNPADB_109 AVCCAUXRXB_109 RXPPADB_109 VTRXB_109 RXNPADB_109 Pin Number BB5 BB4 BA11 BA8 BA6 BB6 BB7 BA9 BB8 BB9 BA12 BB11 BB10 BB12 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 MGTCLK_N_110 RTERM_110 MGTVREF_110 AJ2 AH1 AK1 AJ1 AT2 AN2 AL2 AL1 AM1 AP2 AN1 AP1 AU2 AT1 AR1 AU1 AW1 AY1 AW2 BA2 N/A AVCCAUXRXA_111 W2 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 273 .xilinx.4) September 30.

R Chapter 2: Pinout Tables Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description RXPPADA_111 VTRXA_111 RXNPADA_111 AVCCAUXMGT_111 AVCCAUXTX_111 VTTXA_111 TXPPADA_111 TXNPADA_111 VTTXB_111 TXPPADB_111 TXNPADB_111 AVCCAUXRXB_111 RXPPADB_111 VTRXB_111 RXNPADB_111 Pin Number V1 Y1 W1 AF2 AC2 AA2 AA1 AB1 AD2 AC1 AD1 AG2 AF1 AE1 AG1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_112 RXPPADA_112 VTRXA_112 RXNPADA_112 AVCCAUXMGT_112 AVCCAUXTX_112 VTTXA_112 TXPPADA_112 TXNPADA_112 VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 J2 H1 K1 J1 T2 N2 L2 L1 M1 P2 N1 P1 U2 T1 R1 U1 N/A N/A N/A N/A AVCCAUXRXA_113 RXPPADA_113 VTRXA_113 RXNPADA_113 B9 A10 A8 A9 274 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .4) September 30.xilinx.

2005 www.com 275 .4) September 30.xilinx.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description AVCCAUXMGT_113 AVCCAUXTX_113 VTTXA_113 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 Pin Number F2 B5 B7 A7 A6 B4 A5 A4 G2 F1 A3 G1 C1 D1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A AVCCAUXRXA_114 RXPPADA_114 VTRXA_114 RXNPADA_114 AVCCAUXMGT_114 AVCCAUXTX_114 VTTXA_114 TXPPADA_114 TXNPADA_114 VTTXB_114 TXPPADB_114 TXNPADB_114 AVCCAUXRXB_114 RXPPADB_114 VTRXB_114 RXNPADB_114 B19 A20 A18 A19 B12 B15 B17 A17 A16 B14 A15 A14 B11 A12 A13 A11 N/A N/A N/A N/A N/A GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_102 B21 B23 B25 B28 B31 Virtex-4 Packaging and Pinout Specification UG075 (v2.

xilinx. 2005 .R Chapter 2: Pinout Tables Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_103 GNDA_103 GNDA_103 GNDA_103 GNDA_104 GNDA_104 GNDA_104 GNDA_104 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_105 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_106 GNDA_107 GNDA_107 GNDA_107 GNDA_107 GNDA_108 GNDA_108 Pin Number B33 B35 B38 A41 B41 C41 D41 E41 B42 E42 F41 H41 K41 N41 T41 V41 Y41 AC41 AF41 AH41 AK41 AN41 BA35 BA38 BA40 AT41 AV41 AY41 BB41 AV42 BA42 BA25 BA28 BA30 BA32 BA13 BA15 276 www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.

FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description GNDA_108 GNDA_108 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_109 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_114 GNDA_114 GNDA_114 Pin Number BA17 BA20 BA1 BB2 BA3 BA5 BA7 BA10 AV1 AH2 AK2 AM2 AR2 AV2 AY2 V2 Y2 AB2 AE2 H2 K2 M2 R2 B1 E1 A2 B2 C2 D2 E2 B3 B6 B8 B10 B13 B16 B18 Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx.com 277 .4) September 30. 2005 www.

2005 .R Chapter 2: Pinout Tables Table 2-9: Bank N/A FF1760 Package — FX140 Devices (Continued) Pin Description GNDA_114 Pin Number B20 N/A N/A N/A N/A N/A N/A VREFN_SM (4) VREFP_SM (4) AVDD_SM (5) VN_SM VP_SM (4) (4) (4) AW23 AW22 AW21 AY23 AY22 AY21 AVSS_SM N/A N/A N/A N/A N/A N/A VREFN_ADC (4) VREFP_ADC (4) AVDD_ADC VN_ADC VP_ADC (5) D20 D21 D22 C20 C21 C22 (4) (4) AVSS_ADC (4) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND L3 AA3 AL3 AY3 D4 P4 AD4 AP4 G5 U5 AG5 AU5 K6 Y6 AK6 AY6 C7 N7 AC7 AN7 F8 278 www.xilinx.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

4) September 30. 2005 www.xilinx.FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number T8 AF8 AT8 J9 W9 AJ9 AW9 M10 AB10 AM10 E11 R11 AE11 AR11 H12 V12 AH12 AK12 AV12 L13 AA13 AG13 AL13 D14 M14 P14 AD14 AH14 AP14 G15 L15 N15 U15 AG15 AU15 K16 M16 Virtex-4 Packaging and Pinout Specification UG075 (v2.com 279 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .R Chapter 2: Pinout Tables Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number T16 V16 Y16 AF16 AK16 AY16 C17 N17 U17 W17 AC17 AE17 AN17 F18 T18 V18 AF18 AT18 C19 J19 U19 W19 AG19 AJ19 AW19 M20 T20 V20 AB20 AD20 AF20 AH20 AM20 E21 R21 U21 AA21 280 www.xilinx.4) September 30.

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Pin Number
AE21 AG21 AR21 H22 T22 V22 AF22 AH22 AV22 L23 R23 U23 AA23 AE23 AG23 AL23 D24 P24 T24 AD24 AF24 AH24 AP24 AY24 G25 U25 AE25 AG25 AU25 K26 V26 Y26 AD26 AF26 AK26 AY26 C27

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Pin Number
N27 U27 AC27 AE27 AJ27 AL27 AN27 F28 T28 AF28 AK28 AM28 AT28 J29 R29 W29 AJ29 AL29 AW29 M30 T30 AB30 AM30 E31 N31 R31 AE31 AR31 H32 V32 AH32 AV32 L33 AA33 AL33 D34 P34

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Pin Number
AD34 AP34 G35 U35 AG35 AU35 K36 Y36 AK36 AY36 C37 N37 AC37 AN37 F38 T38 AF38 AT38 J39 W39 AJ39 AW39 C40 M40 AB40 AM40

N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

V9 L10 AC10 AF11 U12 AJ12 K13 AB13 AM13 N14

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

Pin Number
AL16 M17 AK19 AA20 AB23 N24 AL26 M27 AK29 L30 AA30 AN30 P31 AF31 U32 Y33 AM33 AE34 L6 P7 G8 U8 AE8 AR8 K9 Y9 AH9 N10 AA10 AL10 F11 AD11 AP11 J12 W12 AG12 AL12

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

Pin Number
M13 Y13 AH13 AK13 L14 R14 AC14 AG14 AN14 M15 P15 T15 V15 AF15 AH15 AK15 AT15 L16 N16 U16 W16 AJ16 P17 T17 V17 Y17 AD17 AF17 AM17 G18 R18 U18 W18 AC18 AG18 AR18 K19

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Table 2-9: Bank
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

FF1760 Package — FX140 Devices (Continued) Pin Description
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

Pin Number
T19 V19 Y19 AB19 AF19 AH19 AM19 AV19 N20 R20 U20 W20 AC20 AG20 AR20 T21 V21 AB21 AD21 AF21 AH21 R22 U22 W22 AA22 AE22 AG22 AU22 T23 Y23 AD23 AF23 AH23 AK23 E24 L24 R24

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xilinx.com 287 .FF1760 Flip-Chip Fine-Pitch BGA Package R Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FF1760 Package — FX140 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number U24 AA24 AC24 AE24 AG24 AN24 H25 P25 T25 Y25 AD25 AF25 AH25 AT25 L26 U26 W26 AC26 AE26 AG26 AJ26 T27 AD27 AF27 AK27 AM27 G28 N28 R28 U28 AE28 AG28 AJ28 AL28 AN28 K29 T29 Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30. 2005 www.

5. ADC inputs for this pin are reserved for future use but can be used for I/O or other designated functions. This voltage is also referred to as VCC_CONFIG in the Virtex-4 Configuration Guide. 4. Connect this reserved pin to GND.4) September 30.xilinx. 2. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2. 288 www.5V (sharing the same PCB supply distribution as VCCAUX is acceptable). SM inputs for this pin are reserved for future use but can be used for I/O or other designated functions. Connect this reserved pin to 2. 3.R Chapter 2: Pinout Tables Table 2-9: Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: FF1760 Package — FX140 Devices (Continued) Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number Y29 AH29 AM29 N30 R30 AC30 AL30 M31 T31 AD31 AP31 J32 W32 M33 AB33 AK33 R34 AC34 AN34 H35 V35 AF35 AT35 AJ36 AM37 1.

2005 www. LX60.4) September 30. • SF363 Package: • • • • “SF363 Package Pinout Diagram (LX15 and FX12).” page 299 “FF672 Color-Coded SelectIO and Bank Information. SX25.R Chapter 3 Pinout Diagrams Summary This chapter provides pinout diagrams for each Virtex-4 package/device combination.” page 291 “SF363 Package Pinout Diagram (LX25). and a pin description such as IO_L8P_D17_CC_LC_1 is represented with a D0-D31 symbol.” page 296 • FF672 Package: • • • • “FF672 Package Pinout Diagram (FX20).” page 300 Virtex-4 Packaging and Pinout Specification UG075 (v2.” page 298 “FF672 Package Pinout Diagram (FX60).” page 293 FF668 Package: • • • “FF668 Package Pinout Diagram (LX15. LX40. or VRN SM1 – SM7 ADC1 – ADC7 D0 – D31 GC CC LC For example. a pin description such as IO_L4N_GC_VREF_LC_4 is represented with a VREF symbol.” page 297 “FF672 Package Pinout Diagram (FX40). and FX12). with precedence given to functionality in the following order: • • • • • • • VREF. a pin description such as IO_L25N_CC_SM1_LC_7 is represented with an SM1-SM7 symbol.” page 294 “FF668 Package Pinout Diagram (LX25.” page 295 “FF668 Color-Coded SelectIO and Bank Information. and SX35).xilinx.com 289 .” page 292 “SF363 Color-Coded SelectIO and Bank Information. Note that multi-function I/O pins are represented in these diagrams by symbols for only one of the pin’s available functions. VRP.

” page 307 “FF1152 Package Pinout Diagram (FX60).” page 311 “FF1513 Color-Coded SelectIO and Bank Information. and SX55). and LX160). LX60.” page 314 “FF1517 Color-Coded SelectIO and Bank Information.” page 316 “FF1760 Color-Coded SelectIO and Bank Information.” page 310 • FF1513 Package: • • “FF1513 Package Pinout Diagram (LX100.4) September 30. and LX200).” page 305 “FF1148 Color-Coded SelectIO and Bank Information.” page 304 “FF1148 Package Pinout Diagram (LX80.” page 309 “FF1152 Color-Coded SelectIO and Bank Information.” page 315 • FF1760 Package: • • “FF1760 Package Pinout Diagram (FX140).” page 317 290 www.” page 302 “FF676 Color-Coded SelectIO and Bank Information. 2005 .” page 313 “FF1517 Package Pinout Diagram (FX140).” page 308 “FF1152 Package Pinout Diagram (FX100).” page 303 • FF1148 Package: • • • “FF1148 Package Pinout Diagram (LX40.” page 301 “FF676 Package Pinout Diagram (LX25).R Chapter 3: Pinout Diagrams • FF676 Package: • • • “FF676 Package Pinout Diagram (LX15).” page 306 • FF1152 Package: • • • • “FF1152 Package Pinout Diagram (FX40).com Virtex-4 Packaging and Pinout Specification UG075 (v2. LX100. LX160.xilinx.” page 312 • FF1517 Package: • • • “FF1517 Package Pinout Diagram (FX100).

2. M1.xilinx.SF363 Package Pinout Diagram (LX15 and FX12) R SF363 Package Pinout Diagram (LX15 and FX12) SF363 (XC4VLX15 and XC4VFX12) .4) September 30.ADC7 D0 .D31 CC N_GC P_GC LC SM1 . M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .com 291 . Dedicated SM and ADC pins are reserved for future use. 2005 www.SM7 VREF VRN VRP Notes: 1. ug075_02b_110504 Figure 3-1: SF363 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15 and FX12) Virtex-4 Packaging and Pinout Specification UG075 (v2. SM and ADC functionality in multi-function user I/O pins is reserved for future use.Top View 1 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y 17 18 19 20 B N L C Y H U J D P I O 2 0 MKWA 1 n n n n n n 8 9 10 11 12 13 14 15 16 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.

M1. 2.D31 CC N_GC P_GC LC SM1 . ug075_02_110504 Figure 3-2: SF363 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25) 292 www.R Chapter 3: Pinout Diagrams SF363 Package Pinout Diagram (LX25) SF363 (XC4VLX25) .SM7 VREF VRN VRP Notes: 1.com Virtex-4 Packaging and Pinout Specification UG075 (v2.Top View 1 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y 17 18 19 20 B N L C Y H U J D P I O 2 0 MKWA 1 S S S S S S 8 9 10 11 12 13 14 15 16 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. SM and ADC functionality in multi-function user I/O pins is reserved for future use.xilinx. Dedicated SM and ADC pins are reserved for future use. 2005 .ADC7 D0 . M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .4) September 30.

2005 www.4) September 30.com 293 .SF363 Color-Coded SelectIO and Bank Information R SF363 Color-Coded SelectIO and Bank Information SF363 .xilinx.Top View 1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 $ $ $ $ $ $ $ $ $ & & & $ $ $ $ $ $ $ $ $ $ $ $ $ & & & & & 2 $ $ $ $ $ $ $ $ $ $ $ & & & & & 3 $ $ $ $ $ $ $ $ $ $ $ $ & & & & & & " & " 4 5 $ $ $ $ $ $ $ $ $ $ $ $ $ $ & ! ! ! ! ! ! # ! ! ! ! ! ! ! ! #   ! !   #             $ $ $ $ $ & & & 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y # # # # # # # # # # # # # # # # % % % % % # # # # # # # # # # # # % % % % % % 17 # # # # # # # # # # # % % % % % 18 " " " " " " " " " " " " " " 6 7 8 9 10 11 12 13 14 15 16 # # # # # # # # # # # # # % % % % % 19 # # # # # # # # # % % % 20 1 ug075_02-color_122104 Figure 3-3: SF363 Color-Coded SelectIO and Bank Information Virtex-4 Packaging and Pinout Specification UG075 (v2.

and XC4VFX12) .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF B N L C Y H U J D P n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n KW 2 0 M I OA 1 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2. and FX12) 294 www.D31 CC N_GC P_GC LC SM1 .R Chapter 3: Pinout Diagrams FF668 Package Pinout Diagram (LX15. M1. 2005 . ug075_01b_110504 Figure 3-4: FF668 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .ADC7 D0 . SM and ADC functionality in multi-function user I/O pins is reserved for future use. SX25. SX25. Dedicated SM and ADC pins are reserved for future use. XC4VSX25.4) September 30.SM7 VREF VRN VRP Notes: 1. 2. and FX12) FF668 (XC4VLX15.

xilinx. LX40. 2. LX60. SM and ADC functionality in multi-function user I/O pins is reserved for future use. 2005 www. and SX35) FF668 (LX25.SM7 VREF VRN VRP Notes: 1.4) September 30. LX40. and SX35) R FF668 Package Pinout Diagram (LX25. LX60.com 295 . Dedicated SM and ADC pins are reserved for future use. M1. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 . ug075_01_110504 Figure 3-5: FF668 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25. LX40.ADC7 D0 . and SX35) . and SX35) Virtex-4 Packaging and Pinout Specification UG075 (v2. LX60. LX60.FF668 Package Pinout Diagram (LX25. LX40.D31 CC N_GC P_GC LC SM1 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 18 19 20 21 22 23 24 25 26 B N L C Y H U J D P KW 2 0 M I OA 1 S S S S S S 11 12 13 14 15 16 17 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .R Chapter 3: Pinout Diagrams FF668 Color-Coded SelectIO and Bank Information FF668 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF $ $ $ $ $ $     $ $ $ $ $             & & & & & & & & & & & 1 2 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $                   & & & & & & & & & & & & & & & & 4 3 $ $ $ $ $ $ $ $ $ $ $   $ $              & & & & & & & & & & & & & & & 6 5 $ $ $ $ $ $ $ $          & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $       & & & & & & & & & & & 8 7 9 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' % % % ' ' ' % % % % % % % % & % % % % % % % % % % & % % % % % % % " " % % % % % % % % " " % % % % % % % % % " " " " " % % % % % % % " " " " % % % % % " " " % % % % % % % 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25 ! ! $ $ $ $ $ ! ! ! ! ! ! !  ! ! ! !             ! ! !  #  # #  # # ug075_01-color2_121504 Figure 3-6: FF668 Color-Coded SelectIO and Bank Information 296 www.4) September 30.xilinx.

SM7 VREF VRN VRP V V V V Notes: 1. 2. 2005 www.xilinx. Figure 3-7: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX20) Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF V E V V E L J E V 1 2 V E E E X X P n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n E V DH Y N n n n B 2 C n n n n n n n n n n n n n n 0 n n n U 1 n O A M K I W V E V E 8 9 E X X n n n n n n n n n n n n n n n n E V T G X X 10 11 12 13 14 15 n n nG T n n n X X 16 17 18 19 20 21 22 V E E V 24 25 26 3 4 5 6 7 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. M1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.com V E V V V E V E 23 Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ug075_04c_122104 297 .D31 CC N_GC P_GC LC SM1 . M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E ADC1 .ADC7 D0 . Dedicated SM and ADC pins are reserved for future use.FF672 Package Pinout Diagram (FX20) R FF672 Package Pinout Diagram (FX20) FF672 (XC4VFX20) .

V Figure 3-8: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX40) 298 www. M1.SM7 VREF VRN VRP V V V Notes: 1.4) September 30. SM and ADC functionality in multi-function user I/O pins is reserved for future use.R Chapter 3: Pinout Diagrams FF672 Package Pinout Diagram (FX40) FF672 (XC4VFX40) .D31 CC N_GC P_GC LC SM1 . Dedicated SM and ADC pins are reserved for future use.com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF V E V V E L J X X B E V V E V E V 1 2 V E E E X X DH P Y 2 C 0 U M K I W O A E E E V V E 8 9 E E E V V E N 1 V V T S S SG X X S S S E 22 23 E E V T G X X 10 11 12 13 14 15 V E E V 24 25 26 3 4 5 6 7 16 17 18 19 20 21 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.ADC7 D0 . 2005 V V E V E V V V E V ug075_04b_110504 . 2.

M1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.com V V E V E V V V E V ug075_04_110504 299 . V Figure 3-9: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX60) Virtex-4 Packaging and Pinout Specification UG075 (v2. Dedicated SM and ADC pins are reserved for future use.4) September 30.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF V E V V E L J X X B E V V E V E V 1 2 V E E E X X DH P Y 2 C 0 U M K I W O A E E E V V E 8 9 E E E V V E N 1 V V T S S SG X X S S S E 22 23 E E V T G X X 10 11 12 13 14 15 V E E V 24 25 26 3 4 5 6 7 16 17 18 19 20 21 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. 2005 www.xilinx.ADC7 D0 . M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 .D31 CC N_GC P_GC LC SM1 . 2.SM7 VREF VRN VRP V V V Notes: 1.FF672 Package Pinout Diagram (FX60) R FF672 Package Pinout Diagram (FX60) FF672 (XC4VFX60) .

4) September 30.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25 26 $ $ $ $ $ $ $ $ $ $ $ $ $ & & & & & & & & & & & & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $       &     &    & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ! ! ! # $ ! ! # $ ! ! ! $ ! ! ! $ ! ! ! ! ! $ $                 " " " & " " & " " " & " " " " " % % % " " " # # # # # # # # # # # # # # # # # # #  # # #  # # #  # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # # # # # # # # # ' # ' # # ' % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # % % % % % % % % % 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ug075_04-color-2_121504 Figure 3-10: FF672 Color-Coded SelectIO and Bank Information 300 www. 2005 .R Chapter 3: Pinout Diagrams FF672 Color-Coded SelectIO and Bank Information FF672 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.

Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n J L n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n N B U M K I W Y H P D 2 C 0 1 A O n n n n n n n n n n n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .D31 CC N_GC P_GC LC SM1 .SM7 VREF VRN VRP Notes: 1.com 301 . Dedicated SM and ADC pins are reserved for future use. ug075_10a_113004 Figure 3-11: FF676 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15) Virtex-4 Packaging and Pinout Specification UG075 (v2. 2.4) September 30.FF676 Package Pinout Diagram (LX15) R FF676 Package Pinout Diagram (LX15) FF676 (LX15) .ADC7 D0 . SM and ADC functionality in multi-function user I/O pins is reserved for future use.xilinx. M1. 2005 www.

SM and ADC functionality in multi-function user I/O pins is reserved for future use.xilinx.D31 CC N_GC P_GC LC SM1 . Dedicated SM and ADC pins are reserved for future use. 2005 . 2.com Virtex-4 Packaging and Pinout Specification UG075 (v2.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 19 20 21 22 23 24 25 26 J L N B U M K I W Y H P D 2 C 0 1 A O S S S S S S 10 11 12 13 14 15 16 17 18 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.R Chapter 3: Pinout Diagrams FF676 Package Pinout Diagram (LX25) FF676 (LX25) .ADC7 D0 . ug075_10_113004 Figure 3-12: FF676 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25) 302 www.SM7 VREF VRN VRP Notes: 1. M1. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .4) September 30.

xilinx.com 303 .4) September 30.FF676 Color-Coded SelectIO and Bank Information R FF676 Color-Coded SelectIO and Bank Information FF676 . 2005 www.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF $ $ $ $ $ $ $ $ $ $ $ $  $ $ $   $ $  $ $ $   $ $    $   $                                           & & & & & & & & & & & & & & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $  $ $  $        &  & &  & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ! ! ! # $ ! ! # $ ! ! ! $ ! ! ! $ ! ! ! ! ! $              # # # # # # # # # # # # # # # # #  # #  # #  # # # # # # # # # # # # # # # ' # ' ' ' ' ' ' ' ' ' ' % % % % % % % % % % % % % " " " " " & " " " & " " & & " & " " % % % % % " % " " % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' % ' % ' % % % % % % % % % % % % % % % % % # # # # # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' % % % % % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ug075_10-color2_121504 Figure 3-13: FF676 Color-Coded SelectIO and Bank Information Virtex-4 Packaging and Pinout Specification UG075 (v2.

4) September 30. and SX55) 304 www.ADC7 D0 . M1. and XC4VSX55) . and SX55) FF1148 (XC4VLX40. 2005 . 2.D31 CC N_GC P_GC LC SM1 . LX60. Dedicated SM and ADC pins are reserved for future use.xilinx. XC4VLX60.SM7 VREF VRN VRP L TDN Notes: 1.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP n n n n n n J L n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n C n n n n n n n n n n n n H N n n n n n n U n n B Y P n n n n n n D n n n n n n MK n n n n n n n n 2 O n n n n n n n n n n n n 1 0W I n n n n n n n n A n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n S S S S S S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. LX60.com Virtex-4 Packaging and Pinout Specification UG075 (v2. ug075_05b_110504 Figure 3-14: FF1148 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX40.R Chapter 3: Pinout Diagrams FF1148 Package Pinout Diagram (LX40. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 . SM and ADC functionality in multi-function user I/O pins is reserved for future use.

SM7 VREF VRN VRP Notes: 1. XC4VLX100. SM and ADC functionality in multi-function user I/O pins is reserved for future use.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 23 24 25 26 27 28 29 30 31 32 33 34 Z Z Z Z Z Z J L C N U D MK B O I A H Y P 2 1 0W S S S S S S 13 14 15 16 17 18 19 20 21 22 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.xilinx. and LX160) R FF1148 Package Pinout Diagram (LX80. LX100.D31 CC N_GC P_GC LC SM1 . ug075_05_071505 Figure 3-15: FF1148 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX80. and LX160) FF1148 (XC4VLX80. 2005 www.4) September 30. and LX160) Virtex-4 Packaging and Pinout Specification UG075 (v2. and XC4VLX160) . LX100.FF1148 Package Pinout Diagram (LX80. 2. Dedicated SM and ADC pins are reserved for future use.ADC7 D0 . M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .com 305 . M1. LX100.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 3: Pinout Diagrams FF1148 Color-Coded SelectIO and Bank Information FF1148 . 2005 .xilinx.4) September 30.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 14 15    16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP $ $ $ $ $ $ $ $    $    $ $     $     $     $                         " " "  " " "   " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " "                                 & & &    & &   & & &    & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $             " "   "   " " " " " " " " " " " " " " "            & &   & &  & &   & & & & & & & & & & & & & & & & & & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $   $  $             ! ! ! ! !  ! ! !  ! !  !  ! !          " " "          # # #  # # #   # # #    # #   # # #   # #  # !   # !   # ! #     ' ' ' ' ' ' ' ' ' ' ! ! ! ! !       & & & & & & & & & & & & " " " " " " " " " " " " " " " " % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # # # # # # # # # # # # # # # # # ' ' ' # ' ' # ' ' ' # # ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !  ! !  ! ! !               % %  % %  % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % # # # # # # # ' ' ' # # ' ' # ' ' ' # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !  ! ! !  ! ! !                                 %    %    % % % % % % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ug075_05-color2_122104 Figure 3-16: FF1148 Color-Coded SelectIO and Bank Information 306 www.

M1. 2. Dedicated SM and ADC pins are reserved for future use.FF1152 Package Pinout Diagram (FX40) R FF1152 Package Pinout Diagram (FX40) FF1152 (XC4VFX40) .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP V V V E E n n n n n n n n n n n n n E n n n n n E n n n n n n n V n n n n n n n n n n n n n n n n n n n n n n n n E n T G n n X X E V E 2 E E X X E V V N B E n n n n n n n n n n n n n n n n n n n n n n 0 U M K I W O A 1 n n n n n n n n n n n n n n n n n n n n n V V V 1 V V E E X X Y H P D 2 C E n n n V n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n E n n n n n n E n n n V n n n V V E 30 S S n n n n n n n n n n n n n n n n n n 7 8 9 10 11 12 13 14 15 S S n n 16 S S n n n n n n n n n nG T n n n n n n n n n n X X 17 18 19 20 21 22 23 24 25 26 27 28 29 E 32 3 4 5 6 31 33 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.ADC7 D0 . V E V Figure 3-17: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX40) Virtex-4 Packaging and Pinout Specification UG075 (v2.com V E V E V E V 34 n n n n n n n n n n n n n n n n n n n J L n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n E V V V E ug075_06_071505 307 . 2005 www.D31 CC N_GC P_GC LC SM1 . SM and ADC functionality in multi-function user I/O pins is reserved for future use.4) September 30.xilinx.SM7 VREF VRN VRP V V V L TDN Notes: 1. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2. Dedicated SM and ADC pins are reserved for future use.4) September 30.SM7 VREF VRN VRP V V V L TDN Notes: 1. 2005 V E V E n n n n n n n n n n n n n n n n n n n J L n n Z Z n n Z Z n n n n n n n n n n n n n n n n n n n n n Z Z E V V V V E V ug075_06_011905 . M1.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP V V V E E V E V V E E T G X X 1 2 3 4 5 6 E E X X E V V N B E 0 U 1 O M A K I W V E E V E E V 7 8 9 10 11 12 V V E E X X Y H P D 2 C E V V E V V E E E V S S S S S S E E 16 E V 24 26 G T X X 28 29 30 E V V E E E 32 13 14 15 17 18 19 20 21 22 23 25 27 31 33 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.ADC7 D0 .D31 CC N_GC P_GC LC SM1 . 2. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 .R Chapter 3: Pinout Diagrams FF1152 Package Pinout Diagram (FX60) FF1152 (XC4VFX60) . SM and ADC functionality in multi-function user I/O pins is reserved for future use.xilinx. V V V E V V 34 Figure 3-18: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX60) 308 www.

com V V S S S S S S E E E E V 24 25 26 G T X X 28 29 30 E V V E E 32 27 31 33 Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB V V V E V V 34 V V V E V ug075_06_011905 309 .D31 CC N_GC P_GC LC SM1 .xilinx. 2. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E ADC1 . 2005 www. Figure 3-19: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX100) Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.FF1152 Package Pinout Diagram (FX100) R FF1152 Package Pinout Diagram (FX100) FF1152 (XC4VFX100) . M1.SM7 VREF VRN VRP V Notes: 1.ADC7 D0 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP V V V E E V E V V E E T G X X 1 2 3 4 5 6 V E V B E 14 15 16 V E E J Z Z Z L Z Z Z V 22 23 V V E E E E V V E V V E E X X E V V V V E E E V V E E V E E V E X X E V V N E 0 U 1 O M A K I W V E E V E E V 7 8 9 10 11 12 Y H P D 2 C 13 17 18 19 20 21 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. Dedicated SM and ADC pins are reserved for future use. SM and ADC functionality in multi-function user I/O pins is reserved for future use.

2005 .xilinx.com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 33 34 $ $ $ $ $                                            $ $ $ $  $  $                                         $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $                               &  &  &   & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $  $  $       $ $ $ $ $ $ $ $   $  $   $ ! $ $ ! $ ! $ $ $ $ $       ! ! ! ! !      ! ! ! ! ! # # ! ! ! # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ' # # # # #  & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & % % " " " % " " " " " % % " " " " " % " " " % % & & % % % % % % % % % % % %        %  % % % % % % % % % % % % # # ' ' # # ' ' # # # ' # # ' ' # # # ' ' ' ' ' # ' ' ' # ' ' # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '                              % % %  % %   % % %  % % %  % % %  % % % % % % % % % % % % ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '                      % % % % % 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ug075_06-color2_011905 Figure 3-20: FF1152 Color-Coded SelectIO and Bank Information 310 www.R Chapter 3: Pinout Diagrams FF1152 Color-Coded SelectIO and Bank Information FF1152 .

xilinx. LX160.SM7 VREF VRN VRP Notes: 1.ADC7 D0 .4) September 30. SM and ADC functionality in multi-function user I/O pins is reserved for future use. and LX200) FF1513 (XC4VLX100. Dedicated SM and ADC pins are reserved for future use. 2005 www. and LX200) R FF1513 Package Pinout Diagram (LX100.com 311 . LX160. and XC4VLX200) . ug075_07_111204 Figure 3-21: FF1513 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (LX100. 2.D31 CC N_GC P_GC LC SM1 . XC4VLX160. and LX200) Virtex-4 Packaging and Pinout Specification UG075 (v2. M1. LX160. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN Other Pins GND R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT ADC1 .FF1513 Package Pinout Diagram (LX100.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Z Z Z Z Z Z L J C N B U D M K A O I H Y P W 2 0 1 S S S S S S 16 17 18 19 20 21 22 23 24 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2.

Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW     " " " " " " " " $ $ $ $ $ $ $ $                              " " "  " "  " " " " " " " " " " " " " " " " " " " " " " " " " $ $ $ " $ $ " $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $                                 & & & & & & $ $ $ $  $  $             "  " " " " " " " $ $ $ $ $ $ $ $ $ $           &  &  &  & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $  $        " " " " " " " " " $ " $ $ $ $ $ $ $       & &  &  & & & & & & & & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $         " " " " $ $ $    $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $  $  $      " " $ $ $ $ $ $     $  $  $                                        ! ! !  ! !   ! ! !  ! ! !   ! !   ! ! !                   # #      # # # #  #  #  # # # # # ! ! ! ! ! ! # & & & & & & & & & & & & & & & & & & & & & & & & & & & & " " " " " " " " " " " " " " " " #       % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # # # # # # # # # # # # ' ' ' ' ' ! ! ! ! ! # # # # # # #  #          % % % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # ' # ' # ' ' ' ' ! ! ! ! ! ! # # # # # #       % % % % % % % % % % % % % % # # # # # # # # ' ' # ' # ' ' # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # # # # # # # # # #  # #  #   #  #             %  %   %  % %  %  # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # # # # # # # # # # # # # # #            ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # # # # # # # # # # # # # # #         1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ug075_07-color2_122104 Figure 3-22: FF1513 Color-Coded SelectIO and Bank Information 312 www.4) September 30.com Virtex-4 Packaging and Pinout Specification UG075 (v2.R Chapter 3: Pinout Diagrams FF1513 Color-Coded SelectIO and Bank Information FF1513 . 2005 .xilinx.

SM and ADC functionality in multi-function user I/O pins is reserved for future use.FF1517 Package Pinout Diagram (FX100) R FF1517 Package Pinout Diagram (FX100) FF1517 (XC4VFX100) . V V V V 39 Figure 3-23: FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX100) Virtex-4 Packaging and Pinout Specification UG075 (v2.com V V V V E V E E V E E E V V E V E V V V ug075_08b_110504 313 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW V E E X X E V V V 5 6 7 V V E V V 15 16 17 V E Z Z Z Z Z Z L J E V V E V 23 24 25 V E E E E X X E V V E V V E E n n n n n n n n n n n n n n n n E V V E E V 30 E E E V E C n n n n n n n n n n n n n n n n N B U D M K A O I H Y P W 2 0 1 E V V S S S S S S E E 20 V E 4 T G X X 8 9 E V 10 11 G 32 T X X 33 34 35 E 36 E E E E 37 1 2 3 12 13 14 18 19 21 22 26 27 28 29 31 38 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN Y INIT 2 1 0 M2. M1. Dedicated SM and ADC pins are reserved for future use.4) September 30. 2.SM7 VREF VRN VRP V V V Notes: 1.D31 CC N_GC P_GC LC SM1 .ADC7 D0 .xilinx. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 . 2005 www.

R Chapter 3: Pinout Diagrams FF1517 Package Pinout Diagram (FX140) FF1517 (XC4VFX140) .ADC7 D0 . M1. Figure 3-24: FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX140) 314 www. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS Y INIT J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E ADC1 .4) September 30. 2005 V V S S S S S S E E G 32 T X X 33 34 35 E 36 E E E E 37 29 31 38 Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB V V V V 39 V V V V E V E E V E E E V V E V V E V V V ug075_08_110504 .SM7 VREF VRN VRP V Notes: 1. 2.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW V E E X X E V V V 5 6 7 V V E V V 15 16 17 V E Z Z Z Z Z Z L J E V V E V 23 24 25 V E E E E X X E V V E V V E E E V V E V V E E E V V E E V 30 E E E V E C E V V E V V E V V E 4 N B U D M K A O I H Y P W 2 0 1 E E T G X X 8 9 E V 10 11 1 2 3 12 13 14 18 19 20 21 22 26 27 28 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN 2 1 0 M2. SM and ADC functionality in multi-function user I/O pins is reserved for future use.xilinx. Dedicated SM and ADC pins are reserved for future use.com Virtex-4 Packaging and Pinout Specification UG075 (v2.D31 CC N_GC P_GC LC SM1 .

FF1517 Color-Coded SelectIO and Bank Information R FF1517 Color-Coded SelectIO and Bank Information FF1517 . 2005 www.4) September 30.com 315 .xilinx.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 38 39 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $     $     $                                     " " "  " " " " " " " " " " " " " " " " " " " " " " " "   " " "  " " "   " " "  "     " "    "    " "                 & &    &    & &     &   & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $                    " " " " " " " " " " " " "                  & & & & & & & & & & & & & & $ $   $ $ $  $ $  $ $ $ !    ! $   ! $              " " " " " " " " " "    ! ! ! ! !     !  !   !  ! !  ! ! !    # # #  #  #            # # # # # # # # # # # #  # # # # # # # # # # # # # # # # # # # # # # # # # ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! !  & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & " " " " " " " " " " " " " " " " % % % % % % % % % % % % % % % % % % ' ' ' ' ! ! ! ! !               % % % % % % % % % % % % % % % % % % % % % % % % % % # # # # # # # # # # # # # # ' ' ' ' ' ' ' ' ' ' ! ! ! !     # # ' # ' # # ' # ' # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ' ! ' ' ! ! ! ! ! ! ! ! ! !  !                  %  %   % % % % % % % % % ' ' ' ' ' ' ' ' ' ' ' ! ' ! ' ! ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !                 % % % % % % % ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! !         % % 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ug075_08-color2_122104 Figure 3-25: FF1517 Color-Coded SelectIO and Bank Information Virtex-4 Packaging and Pinout Specification UG075 (v2.

4) September 30. 2005 V V E E V V V V V V V E E E X X E V E V E E E V E E V ug075_09_110504 .R Chapter 3: Pinout Diagrams FF1760 Package Pinout Diagram (FX140) FF1760 (XC4VFX140) .xilinx. Dedicated SM and ADC pins are reserved for future use.D31 CC N_GC P_GC LC SM1 . SM and ADC functionality in multi-function user I/O pins is reserved for future use. M0 P PROGRAM_B W PWRDWN_B U RDWR_B S SM K TCK I TDI O TDO M TMS Y INIT J TDP L TDN GND GNDA R RSVD VBATT VCCAUX VCCINT VCCO n NO CONNECT X MGTCLK G MGTVREF T RTERM E E E E Other Pins AVCCAUXRXA AVCCAUXRXB AVCCAUXTX AVCCAUXMGT VTRXA VTTXA VTRXB VTTXB RXNPADA RXPPADA TXPPADA TXNPADA RXNPADB RXPPADB TXPPADB TXNPADB ADC1 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB V V 6 V V 16 17 18 V E E Z Z Z Z Z Z J L V 1 A 23 24 25 V E E V E V 33 34 35 V V V E E V X X E E E V V E 39 V V E E E V V U M K I W E V E V E E V 1 2 3 4 5 7 8 9 E E E V CH P N D 2 B Y 0 O V E V V E E E V V V E V 26 27 28 29 30 31 32 36 37 38 10 11 12 13 14 15 19 20 21 22 E E V V E E X T X G S S n n n n n E n n n n n n n n n S S n n S S n n n n n n E n n n n n n n n n n V V E V 40 T X X G 41 42 User I/O Pins IO_LXXY_# Multi-Function Pins: Dedicated Pins Z ADC C CCLK B CS_B N D_IN D DONE A DOUT_BUSY H HSWAPEN 2 1 0 M2.ADC7 D0 .SM7 VREF VRN VRP V V V Notes: 1. M1. 2. V E E E Figure 3-26: FF1760 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX140) 316 www.

com 317 .4) September 30.xilinx.FF1760 Color-Coded SelectIO and Bank Information R FF1760 Color-Coded SelectIO and Bank Information FF1760 .Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 41 42                  " " " " " " " " " " " " " " " " $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $             $ $    $   $ $    $   $    $                   " "  " "   " " " " " " " " " " " " " " " " " " " " " " " " " " " $ $ $ $ $ $ $ $ $ $ $ $  $ $ $  $ $ $ $ $ $ $ $    $ $   $    $ $             &    &    &        & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $  $ $ $    " "   "   " " " " " " " " " " " " $ $ $ $ $ $ $ $ $ $            &  &  & & & &  & &  & &  & & & & & & & & & & & & & & & & & & & & & & & $ $ $ $ $ $ $ $ $ $ $ $ $ $     $    $    $              $    ! ! ! ! ! ! !  ! #       !  !  ! ! ! ! ! ! # # # #  #         # # # # # # # # # # # # #        # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ' ' ' ' ' ' ! ! ! ! # # # # # #  #  % % % % % % % % % % % % % % % % % % " " $ $ $ $ $ $ $ $ $ $    & & & & & & & & & & & & & & & & & & & & & " " " " " " " " " " " " " " " " ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # # # # #        % % & & & & & & % % % % % % % % % % % % % % % % % % % % % % % % % % % % % # # ' # ' # # ' # ' # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ' ! ' ! ' ' ! ! ! ! ! ! # # # # # # # # # # # #           %  %  % %  % % % % % % % % % % % ' ' ' ' ' ' ' ' ' ' ' ! ' ! ' ! ' ! ! ! ! ! ! ! ! ! ! # # # # # # # # # # # # # # #                 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # # # # # # # # # # # # # # # # # # # # # # #                           3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ug075_09-color2_121504 Figure 3-27: FF1760 Color-Coded SelectIO and Bank Information Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .4) September 30.R Chapter 3: Pinout Diagrams 318 www.xilinx.

com 319 .00mm pitch).” page 322 “FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.R Chapter 4 Mechanical Drawings Summary This chapter provides mechanical drawings of the following Virtex-4 packages: • • • • • • • • • “SF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.” page 326 “FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.” page 321 “FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).” page 324 “FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.” page 328 Virtex-4 Packaging and Pinout Specification UG075 (v2.” page 327 “FF1760 Flip-Chip Fine-Pitch BGA Package Specifications (1.80mm pitch).00mm pitch).” page 323 “FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).4) September 30.00mm pitch).00mm pitch).” page 325 “FF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1. 2005 www.xilinx.00mm pitch).” page 320 “FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).

xilinx.R Chapter 4: Mechanical Drawings SF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.80mm pitch) Figure 4-1: SF363 Flip-Chip Fine-Pitch BGA Package Specifications 320 www. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.

4) September 30.com 321 .00mm pitch) Figure 4-2: FF668 Flip-Chip Fine-Pitch BGA Package Specifications Virtex-4 Packaging and Pinout Specification UG075 (v2.Summary R FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.xilinx. 2005 www.

com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .00mm pitch) Figure 4-3: FF672 Flip-Chip Fine-Pitch BGA Package Specifications 322 www.R Chapter 4: Mechanical Drawings FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.4) September 30.

Summary R FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1. 2005 www.xilinx.com 323 .00mm pitch) Figure 4-4: FF676 Flip-Chip Fine-Pitch BGA Package Specifications Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.

00mm pitch) Figure 4-5: FF1148 Flip-Chip Fine-Pitch BGA Package Specifications 324 www.R Chapter 4: Mechanical Drawings FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.com Virtex-4 Packaging and Pinout Specification UG075 (v2. 2005 .xilinx.4) September 30.

00mm pitch) Figure 4-6: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications Virtex-4 Packaging and Pinout Specification UG075 (v2.4) September 30.Summary R FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.xilinx. 2005 www.com 325 .

com Virtex-4 Packaging and Pinout Specification UG075 (v2.xilinx. 2005 .R Chapter 4: Mechanical Drawings FF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 4-7: FF1513 Flip-Chip Fine-Pitch BGA Package Specifications 326 www.4) September 30.

xilinx.Summary R FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1. 2005 www.4) September 30.00mm pitch) Figure 4-8: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications Virtex-4 Packaging and Pinout Specification UG075 (v2.com 327 .

xilinx.00mm pitch) Figure 4-9: FF1760 Flip-Chip Fine-Pitch BGA Package Specifications 328 www.4) September 30.R Chapter 4: Mechanical Drawings FF1760 Flip-Chip Fine-Pitch BGA Package Specifications (1. 2005 .com Virtex-4 Packaging and Pinout Specification UG075 (v2.

The following topics are discussed: • • • • • Introduction Virtex-4 Power Management Strategy Some Thermal Management Options Support for Compact Thermal Models (CTM) References Introduction Virtex-4 devices are offered exclusively in thermally efficient flip-chip BGA packages. on-board digitally controlled impedance (DCI). and many other popular features contained in earlier Virtex products. The extent of system integration in a fully configured design that is exploiting the fabric and using several embedded circuits and systems (such as PowerPC devices. The end user’s operating conditions dictate the appropriate solution. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. The LX devices are the base family members. For this purpose. Unlike features in an ASIC or a microprocessor. 2005 www. Xilinx offers and supports a suite of integrated device power analysis tools to help end-users quickly and accurately estimate their design power requirements. with traditional Virtex-II features implemented in the smaller process technology. SelectIO buses with DCI. The SX devices include an embedded DSP. MGTs. all Virtex-4 family members feature versatile SelectIO resources that support a variety of I/O standards.4) September 30. The FX and SX family members take system integration a few steps further.xilinx. Similar to Virtex-II FPGAs. Therefore. Xilinx devices do not come with preset thermal solutions. the combination of FPGA features utilized in an end-user application will not be known to the component supplier. with the incorporation of embedded circuits on top of the base FPGA fabric. Virtex-4 Packaging and Pinout Specification UG075 (v2. This FPGA family’s three product lines have different thermal needs. Accurate estimates are obtained when the board design takes shape. Therefore. the FX family incorporates faster RocketIO multi-gigabit transceivers (MGTs) and one or more embedded PowerPC devices. In addition.com 329 . and so forth) presents a power consumption challenge that must be managed.R Chapter 5 Thermal Specifications Summary This chapter provides thermal data associated with Virtex-4 packages. it remains a challenge for Xilinx to predict the power requirements of a given Virtex-4 device when it leaves the factory.

4 11.4 7. 2005 .6 4.0 27.0 0.8 3.4 13.6 0.2 0.7 9.1 6.3 8.7 4.7 4.7 6.2 4.1 4.1 0.3 0.2 0.2 13.0 27.6 0.0 2.7 6.0 27.9 4.6 4.1 5.8 4.2 0.0 35.3 8.4 3.0 330 www.1 6.0 40.7 14.4 13.5 6.9 11.2 0.3 5.2 2.0 17.7 9.8 5.2 0.7 4.1 0.7 10.4 4.0 35.3 0.2 6.1 6.4 0.4 0.0 35.0 35.8 4.0 20.6 10.5 4.0 7.8 5.1 14.R Chapter 5: Thermal Specifications The Virtex-4 package offering (see Table 5-1) is tailored to include medium to high-power options that allow external management of power to suit the user application.2 2.4 6.3 7.8 2.0 11.4 10.3 9.4 12.3 8.5 4.5 5.7 13.7 8.0 35.0 10.2 13.3 2.6 0.4 2.2 0.0 12.9 3.2 20.xilinx.6 12.0 40.6 4.1 8.3 5.1 4.9 14.1 5.3 0.5 8.8 19.3 7.1 6.2 6.8 14.7 10.8 7.4 17.2 13.7 4.0 4.0 27.3 12.0 35.0 27.5 6.0 10.0 7.3 5.9 4.0 14.0 27.1 2.6 5.3 5.1 5.4 0.3 5.0 27.0 27.4 3.8 7.7 8.0 27.1 5.9 6.1 0.0 4. junctionto-case and junction-to-board data based on standard JEDEC four-layer measurements.0 35.5 12.2 9.5 0.3 6.9 4.5 2.3 9.jsp.0 7.8 7.6 4.1 9.xilinx.8 7.6 3.0 40.4 2.com/xlnx/xil_sw_updates_home.7 6.2 0.0 12. Compact thermal models for these products are available on the Xilinx support download center at: http://www.9 6. Table 5-1 also shows the thermal resistance data for Virtex-4 devices in the packages offered.4) September 30.6 2.7 6.4 6.9 7.8 6. The data includes junction-to-ambient in still air and at various air speeds (in LFM).3 9.9 12.7 8.6 2.4 4.0 35.0 27.7 6.2 0.4 0.1 0.3 4.0 27.0 35. Table 5-1: Package Thermal Resistance Data Device Package Body Size θJC θJB θJA @ 0 LFM θJA @ θJA @ θJA @ 250 LFM 500 LFM 750 LFM LX and SX Devices SF363 LX15 LX25 FF668 LX15 LX25 LX40 LX60 SX25 SX35 FF676 LX15 LX25 FF1148 LX40 LX60 LX80 LX100 LX160 SX55 FF1513 LX100 LX160 LX200 FX Devices SF363 FF668 FF672 FX12 FX12 FX20 FX40 FX60 FF1152 FX40 FX60 FX100 17.5 5.3 3.com Virtex-4 Packaging and Pinout Specification UG075 (v2.0 27.0 0.5 9.2 7.0 3.1 0.4 12.8 7.1 2.5 0.

5 4. Virtex-4 Packaging and Pinout Specification UG075 (v2.7 3.0 4.0 1.1 0.2 2.Virtex-4 Power Management Strategy R Table 5-1: Package FF1517 Thermal Resistance Data (Continued) Device FX100 FX140 Package Body Size 40.1 3.5 °C/watt.1 3.5 θJC 0. switching at faster rates.0 42.1 θJA @ θJA @ θJA @ 250 LFM 500 LFM 750 LFM 5.7 θJA @ 0 LFM 9. 2005 www. Thermal Interface Material (TIM) Lid-Heat Spreader Die Substrate UG075_c05_01_081905 Figure 5-1: Heat Spreader with Thermal Interface Material Materials with better thermal conductivity and consistent process applications deliver low thermal resistance up to the heat spreader. The junction-to-case thermal resistance (top of heat spreader) of all Virtex-4 packages is less than 0.1 0. Transistor leakage current is minimized (50% better than comparable devices) by using the power-efficient Virtex-4 architecture.0 40.3 °C/watt for the larger packages (35mm x 35mm and above). Despite these improvements. Typically this value is between 0. the Virtex-4 devices pack higher gate density and can do more in a shorter time than the previous generation of FPGAs. Xilinx has selected the more efficient flip-chip BGA packages. as shown in Figure 5-1.7 5.2 FF1760 FX140 Virtex-4 Power Management Strategy Xilinx relies on a multi-prong approach with regards to the heat-dissipating potential of Virtex-4 devices: • Design and Silicon Significant power reduction in Virtex-4 devices at the 90 nm node is achieved through innovative process and circuit design. This package incorporates a heat spreader with a thermal interface material (TIM).com 331 . • Packaging At the package component level. Compared to previous generations.6 7.1 to 0. with the increase in resources associated with higher gate density devices.4) September 30. thus dissipating more power than before.5 8.xilinx.6 4. However.1 θJB 2. Xilinx anticipates more work will be done more quickly. the power consumption is lower for the same design (same function and gate density) in a Virtex-4 implementation. which present a low thermal path to the outside. and a lower operating voltage.6 4.

ranging from simple airflow to schemes that can include passive as well as active heat sinks.xilinx. finned. the flip-chip BGA packages offered for Virtex-4 devices are thermally enhanced BGAs with the die facing down. external. Xilinx has left the heat sink solution to the system level designers who can tailor the design and solution to the constraints of their systems. At this point. being fully aware that the part has certain inherent capabilities for delivering the heat to the surface. providing the third prong in the thermal management strategy.R Chapter 5: Thermal Specifications • Heat Sinking Solutions at the System Level Depending on the system’s physical as well as mechanical constraints. 2005 . The Virtex-4 packages can be grouped into medium. Again.12° C/Watt Bare Package Package can be used with moderate airflow within a system Mid Range Passive H/S + Air 4 .2°C/watt) can offer quick thermal solutions in these packages. the use of spring-loaded pins or clips that transfer the mounting stress to a circuit board is advisable whenever a bulky heat sink is considered. The more efficient external heat sinks tend to be tall and heavy. As stated earlier.10 Watts 5 .6 Watts Bare Package with Moderate Air 8 . Some Thermal Management Options The flip-chip thermal management chart in Figure 5-2 illustrates simple but incremental power management schemes that can be applied on a flip-chip BGA package. the use of passive heat sinks and heat spreaders attached with thermally conductive double-sided tapes or retainers (with TIM around 0. The diagonals of some of these heat sinks may be designed with extensions to allow direct connection to the board. These high-end thermal packages lend themselves to the application of efficient external heat sinks (passive or active) for further heat removal efficiency.3° C/Watt or Better Package Used with Active Heat Sinks TEC and board level heat spreader techniques UG075_c5_02_091205 Figure 5-2: • Thermal Management Options for Flip-Chip BGA Packages For moderate power dissipation (less than 6 watts). This is particularly true for the bigger flip-chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 20 watts with arrangements that consider system physical constraints. the expectation is that the thermal budget will be maintained with custom or OEM heat sink solutions.4) September 30.20 watts in the bigger packages. To help protect component joints from heat sink induced stress cracks.25 Watts Active Heat Sink 2 . These packages have an exposed metal heat sink at the top. passive heat sinks can be effective for dissipating up to 10 .com Virtex-4 Packaging and Pinout Specification UG075 (v2. All Virtex-4 packages can use thermal enhancements. Low End 1 .10° C/Watt Packaged Used with Various Forms of Passive Heat Sinks Heat spreader techniques High End 8 . The use of lightweight. precautions must be taken to prevent component damage when a • • 332 www.and high-performance packages based on their power handling capabilities.

When considering the use of a TEC for heat management. As much as 60 to 80% of the dissipated heat can go through the BGA balls and thus to the board. These resistances are measured using a prescribed JEDEC standard that may not necessarily reflect the actual user environment. Delphi CTM models are available on the Xilinx support download center at: http://www. An otherwise cooler component can be heated by other heat contributing components on the board. Also condensation can be an issue with these devices. and JEDEC has traditionally recommended that these be used with that awareness. Though Xilinx will continue to support these figure of merit data. consultation with experts in using the device is important because these devices can be reversed and cause damage to components. These compact models seek to capture the thermal behavior of the packages more accurately at pre-determined critical points (junction. An otherwise cooler component can be heated by other heat contributing components on the board. • Support for Compact Thermal Models (CTM) Table 5-1 provides the traditional thermal resistance data for Virtex-4 devices. The effect of the board is dependent on its size and how it conducts heat. Board size. The cold ring junction-to-board thermal resistance for Virtex-4 packages are given in Table 5-1. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources.) with the reduced set of nodes as illustrated in Figure 5-3. these may not be enough. The two-resistor model can be made up with the data provided in Table 5-1. Unlike a full 3D model. Outside the package itself.jsp.xilinx. and θJC numbers are environmentally dependent. Table 5-1 lists the junction-to-board thermal parameters for Virtex-4 packages. the board on which the package sits can have a significant impact on thermal performance. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources on the board. A standard JEDEC type board in still air was used for the data estimation. 2005 www. Virtex-4 Packaging and Pinout Specification UG075 (v2.com/xlnx/xil_sw_updates_home. Two resistor as well as eight to 10 resistor network models are offered for all Virtex-4 devices. case. particularly if the board is not cooled effectively. and a system level thermal simulation may be required. For more accurate junction temperature prediction. these with their multiple internal vias show very efficient junction-to-board resistances. the number of buried copper planes all lower the junction-to-ambient thermal resistance for a package mounted on it. for Virtex-4 boundary condition independent compact thermal models (BCI-CTM) are available to assist end-users in their thermal simulations. leads etc.4) September 30. • An active heat sink may include a simple heat sink incorporating a mini fan or even a Peltier Thermoelectric Cooler (TEC) with a fan to carry away any dissipated heat.xilinx.Support for Compact Thermal Models (CTM) R bulky heat sink is attached. particularly if the board is not cooled effectively. these are computationally efficient and work well in an integrated system simulation environment. The quoted θ JA. Designs can be implemented to take advantage of the board's ability to spread heat. The thermal interface resistance needs to be controlled to take full advantage of these packages. top. Using the standard four-layer JEDEC boards.com 333 . the level of copper traces on it.

Flometrics .wakefield.Flowtherm .xilinx.http://www.aosco.bergquistcompany.aavid.http://www.com/ Harvard Thermal .4) September 30. 2005 .http://www.com Refer to the following websites for CFD tools for thermal simulation.powerdevices. • • • • • • • • http://www.com Virtex-4 Packaging and Pinout Specification UG075 (v2.com Refer to the following websites for interface material sources: Power Devices .http://www.chipcoolers.com AOS Thermal Compound .com http://www.http://www.flotherm.com/ 334 www.com Bergquist Company .harvardthermal.R Chapter 5: Thermal Specifications DELPHI BCI-CTM Topology for FCBGA TI TO Two Resistor Model Rjc Junction SIDE Junction Rjb BI BO UG075_c05_02_081905 Figure 5-3: Thermal Model Topologies References The following websites contain additional information on heat management and contact information.com http://www.

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