B. S. A.

College of Engineering & Technology, Mathura
(Established & Governed by Agarwal Shiksha Mandal)

Digital Electronics (EEC-302) Semester: 3rd Year: 2010-11 Lecture Schedule
L. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Date Topic Unit 1: Digital system and binary numbers: Signed binary numbers, binary codes Cyclic codes, error detecting and correcting codes Error detecting and correcting codes, Hamming codes. Floating point representation Gate-level minimization: The map method up to five variable, don’t care conditions Gate-level minimization: The map method up to five variable, don’t care conditions POS simplification, NAND and NOR implementation Quine Mc-Clusky method (Tabular method) Quine Mc-Clusky method (Tabular method) Revision Unit 2: Combinational Logic: Combinational circuits Analysis procedure, design procedure Analysis procedure, design procedure Binary adder- subtractor Decimal adder, binary multiplier Magnitude comparator Decoders Encoders Multiplexers Revision Unit 3: Synchronous Sequential logic: Sequential circuits Storage elements: latches, flip flops Storage elements: latches, flip flops Analysis of clocked sequential circuits State reduction and assignments Design procedure Registers and counters: Shift registers, ripple counter Synchronous counter Other counters Revision Reference

Branch: EC

1.6, 1.7, 7.4

3.1 to 3.7, 3.10

4.1 to 4.11

5.1 to 5.5, 5.7 to 5.8 6.1 to 6.5

1of 2

Wiley. 2of 2 . 8. 7. design procedure Reduction of state and flow table Reduction of state and flow table Race free state assignment Hazards Revision of Unit 1 Revision of Unit 2 Revision of Unit 3 Revision of Unit 4 Revision of Unit 5 Test of complete syllabus Reference 7. Pearson Education.5 to 7.5.4. design example Design with multiplexers Design with multiplexers Revision Unit 5: Asynchronous sequential logic: Analysis procedure Circuit with latches. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Date Topic Unit 4: Memory and programmable logic: RAM ROM PLA PAL Design at the register transfer level ASMs. Ciletti. “Switching Circuit & Logic Design”. No.10 9.3. Morris Mano and M. design example ASMs. 8. M.7 Text Book: 1. Hill & Peterson.1 to 9. “Digital Design”. D.L. Reference Book : 1. 4th Edition.1 to 7.7 8.

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