VLSI Lab Manual

VLSI LAB MANUAL (06ECL77)
Subject Code No. OF Practical Hrs/Week Total no. OF Practical Hrs. : 06ECL77 IA Marks : 03 : 42 Exam Hours Exam Marks : 25 : 03 : 50

PART – A
DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW
1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the waveform and synthesis the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation. i. ii. iii. iv. v. vi. vii. viii. An inverter A Buffer Transmission Gate Basic/universal gates Flip flop -RS, D, JK, T Serial & Parallel adder 4-bit counter [Synchronous and Asynchronous counter] Successive approximation register [SAR]

* An appropriate constraint should be given

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PART - B
ANALOG DESIGN Analog Design Flow
1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize Time, Power and Area to the given constraint***

2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier

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3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.

4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check OF LVS d. Extract RC and back annotate the same and verify the Design.

5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.

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VLSI Lab Manual PART – A DIGITAL DESIGN Steps to use Xilinx tool: Start the Xilinx Project Navigator by using the desktop shortcut or by using the  Start  Programs  Xilinx ISE  Project Navigator.v Define portsFinish  Select devicesGeneral purpose Spartan 3 ISE simulatorverilog BGSIT. BG Nagar Page 4 .  In the Project Navigator window go to FILE New project Click on new source verilog module and give the name inverter.

VLSI Lab Manual  In the create new source window select source type as verilog module give file name  assign inputs and outputs  click next finishyesnext nextfinish BGSIT. BG Nagar Page 5 .

INVERTER BGSIT.VLSI Lab Manual  Double click on source filecomplete the verilog code for inverter  Check syntax. Click on the symbol of FPGA device and then right clickClick on new sourceClick on verilog text fixtureGive file name with _tb finish  Generate test bench file after initial begin assign value for inputs Click on simulate behavioral model see the output.v file in the Sources in Project window. To run the Behavioral Simulation. BG Nagar Page 6 . and remove errors if present  Simulate the design using ISE Simulator Highlight inverter.

BG Nagar Page 7 . the output is a 1. NOT gate has 1 input and 1 output. the output is a 0. the output will have the opposite value. Write Verilog Code of an inverter circuits and their Test Bench for verification Objective: To design an inverter in verilog using xilinx tool and verify it on ISE simulator Tools : Xilinx ISE simulator . If the input is a 0. for example. Whatever the value is at the input. If the input is a 1. Symbol and truth table: Design Description: NOT gate.VLSI Lab Manual 1. B = ~A Waveform: BGSIT. will invert the data.

output b. BG Nagar Page 8 . output reg b. end endmodule //Test bench structure BGSIT. b). input a. b). endmodule // Behavioural model module in1(a.VLSI Lab Manual VERILOG CODE //Data flow model module in1(a. assign b=~a. input a. always @(a) begin b=~a.

// Wait 100 ns for global reset to finish // Add stimulus here a = 1.VLSI Lab Manual module iin_v. initial begin a = 0. Write Verilog Code of a Buffer circuits and their Test Bench for verification BGSIT.. // Inputs wire b. BG Nagar Page 9 . // Wait 100 ns for global reset to finish end endmodule Waveform: Conclusion: Design of an inverter is done using xilinx tool and is verified. reg a. BUFFER 2. #100. // Outputs // Instantiate the Unit Under Test (UUT) in1 uut (.b(b) ).a(a). #100.

Symbol and Truth table: Design Description: If we were to connect two inverter gates together so that the output of one fed into the input of another. Its symbol is simply a triangle. Tools : Xilinx ISE simulator . a special logic gate called a buffer is manufactured to perform the same function as two inverters. the two inversion functions would "cancel" each other out so that there would be no inversion from input to final output: For this purpose.VLSI Lab Manual Objective: To design a buffer in verilog using xilinx tool and verify it on ISE simulator. with no inverting "bubble" on the output terminal: B = A Waveform: BGSIT. BG Nagar Page 10 .

input a.VLSI Lab Manual // VERILOG CODE: //Data flow model module buffer(a. b). always @(a) begin b=a. input a. BGSIT. output reg b. output b. endmodule // Behavioural module buffer (a. BG Nagar Page 11 . assign b=a. b). end endmodule //Test bench structure module iin_v.

initial begin a = 0.. // Outputs // Instantiate the Unit Under Test (UUT) in1 uut (. #100. // Inputs wire b. #100. end endmodule Waveform: Conclusion: Design of a buffer in xilinx tool and is verified according to the truth Table. Transmission Gate 3. a = 1.VLSI Lab Manual reg a. BG Nagar Page 12 .b(b) ). Write Verilog Code of a transmission gate circuits and their Test Bench for verification BGSIT.a(a).

analogue switch or electronic relay depending on its use.VLSI Lab Manual Objective: To design a transmission gate in verilog using xilinx tool and verify it on ISE simulator. and so is also known as an analog gate.IN.OUT).IN. Tools : Xilinx ISE simulator . input A. BGSIT. It is made by the parallel combination of an nMOS and a pMOS transistor with the input at the gate of one transistor being complementary to the input at the gate of the other transistor. //VERILOG CODE module transmission_gate(A. Circuit Diagram and Truth table: A(Select ) 0 1 1 Design Description: IN X 0 1 OUT X 0 1 Transmission gate is an electronic element. It can be used to simplify digital logic circuits or to switch analog signals. It is a good non-mechanical relay. built with CMOS technology. BG Nagar Page 13 .

VLSI Lab Manual output OUT. A = 1. A = 0.OUT(OUT) ). IN = 0. // Outputs // Instantiate the Unit Under Test (UUT) transmission_gate uut ( .#100. reg IN.Abar.#100. endmodule //Test bench code module tg_tb_v. IN = 1. end endmodule Waveform: BGSIT. pmos(OUT.IN).IN). A = 1. BG Nagar Page 14 . .#100.A(A). wire Abar. // Inputs wire OUT. initial begin // Initialize Inputs A = 0. IN = 0.IN(IN). reg A. nmos(OUT. IN = 1.#100. assign Abar=~A. .A.

Objective: To design a basic gates in verilog using xilinx tool and verify it on ISE simulator. Write Verilog Code of a Basic gates circuits and their Test Bench for verification. BGSIT. BG Nagar Page 15 . BASIC GATES 4.VLSI Lab Manual Conclusion: Design of a transmission gate in xilinx tool and is verified according to the truth Table.

In any case. the output is only equal to 1 if all the inputs are equal to 1. no matter how many inputs it has. BG Nagar Page 16 . but an AND gate can have many inputs. The equation of an AND gate is: C = A & B Waveform: OR GATE: BGSIT. The above picture shows a two input AND gate. otherwise the output is 0.VLSI Lab Manual Tools : Xilinx ISE simulator . AND GATE: Symbol and Truth table of AND gate Design Description: The output of an AND gate is only equal to 1 if both inputs (A AND B in this case) are equal to 1. Otherwise the output is equal to 0.

The equation of an OR gate is: C = A + B Waveform: EX-OR GATE: BGSIT. BG Nagar Page 17 . Again. the above picture shows a two input OR gate. The output will be equal to 1 if any of the inputs is equal to 1.VLSI Lab Manual Symbol and Truth table of OR gate Design Description: The output of an OR gate is equal to 1 if either input (A OR B in this case) is equal to one. If neither input is equal to 1. the output is equal to zero. but an OR gate can have as many inputs as you like.

but equal to zero if both inputs are equal to zero or if both inputs are equal to 1.VLSI Lab Manual Symbol and Truth table of XOR gate: Design Description: The output of an XOR gate is equal to 1 if either input (A or B in this case) is equal to one. The equation OF an XOR gate is: C = A ^ B Waveform: NAND GATE: BGSIT. This is the difference between an OR gate and an XOR gate. BG Nagar Page 18 . an OR gates output will equal 1 if both inputs are equal to 1.

Essentially. The word "NAND" is a verbal contraction of the words NOT and AND. a NAND gate behaves the same as an AND gate with a NOT (inverter) gate connected to the output terminal. If any input is "low" (0). the output will go "high" (1). In such cases. The truth table for a NAND gate is as one might expect. The equation of an XOR gate is: C = ~(A &B) Waveform: BGSIT. To symbolize this output signal inversion. the NAND gate symbol has a bubble on the output line. the same general principle applies: the output will be "low" (0) if and only if all inputs are "high" (1). exactly opposite as that of an AND gate: As with AND gates.VLSI Lab Manual Symbol and Truth table of NAND gate: Design Description: A variation on the idea of the AND gate is called the NAND gate. BG Nagar Page 19 . NAND gates are made with more than two inputs.

The word "NOR" is a verbal contraction of the words NOT and OR. Essentially. BG Nagar Page 20 . the NOR gate symbol has a bubble on the output line. the same general principle applies: the output will be "low" (0) if any inputs are "high" (1). In such cases. If both the inputs is "low" (0). The truth table for a NOR gate is as one might expect. NOR gates are made with more than two inputs. a NOR gate behaves the same as an OR gate with a NOT (inverter) gate connected to the output terminal. Waveform: BGSIT. To symbolize this output signal inversion.VLSI Lab Manual NOR GATE: Symbol and Truth table of NOR gate: Design Description: A variation on the idea of the OR gate is called the NOR gate. the output will go "high" (1). exactly opposite as that of an OR gate: As with OR gates.

// na-> nand gate output assign x=(c^d).na.no. BG Nagar Page 21 . BGSIT.x).a. input c. output a.x.no.d .o.na.VLSI Lab Manual VERILOG CODE //Data flow model module gat(c. assign o=(c|d). // no-> nor gate output assign a=(c&d). // a-> and gate output assign na=~(c&d). // x-> xor gate output endmodule //Test bench structure module basi_v.d. //o -> or gate output assign no=~(c|d).o.

d = 0. Write Verilog Code of Flip flops circuits and their Test Bench for verification BGSIT.#100. . wire x. c = 1. FLIP FLOPS 5. d = 1. wire na. .d(d). wire a.#100. .x(x) ). d = 1. BG Nagar Page 22 . . c = 0.reg d.#100.na(na). // Inputs // Outputs . d = 0. c = 1. // Instantiate the Unit Under Test (UUT) gat uut (. wire no.no(no). initial begin c = 0.a(a).#100.VLSI Lab Manual reg c. wire o.o(o). end endmodule Waveform: Conclusion: Design of Basic gates in xilinx tool and is verified according to the truth Table.c(c). .

VLSI Lab Manual

Objective: To design Flip flops in verilog using xilinx tool and verify it on ISE simulator Tools : Xilinx ISE simulator . i) D FLIPFLOP

Symbol and truth table Design Description: D Flip Flop has two inputs, the clock and the D input, and one output, Q. In the picture D is connected to the node A, and Q is connected to the node B, so these are essentially names OF the same thing. As can be seen in the truth table, the output is equal to the input on the rising edge OF the clock. If there is no rising clock edge, the output will remain in its current state. Waveform:

// VERILOG CODE module d_ff( d, clk, q, q_bar); input d, clk;
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output q, q_bar; reg q; reg q_bar; always @ (posedge clk) begin q <= d; q_bar <= !d; end endmodule //Test bench structure module cc_v; reg d; reg clk; // Inputs

wire q; wire q_bar; // Outputs // Instantiate the Unit Under Test (UUT) d_ff uut (.d(d), .clk(clk), .q(q), .q_bar(q_bar) ); initial begin d = 0; d = 0; d = 1; d = 1; end endmodule clk = 0; #100;// Initialization of Inputs clk = 1; #100; clk = 1; #100; clk = 0; #100;

Waveform:

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ii) T FLIPFLOP

Symbol and truth table // VERILOG CODE module t_ff ( t, clk, q, q_bar); input t, clk; output q, q_bar; reg q; reg q_bar; always @ (posedge clk) begin q = ~t; q_bar = ~q; end endmodule //Test bench structure module cc_v;
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q(q).t(t). #100.clk = 0. . .clk = 0. #100.clk = 1. wire q_bar. // Inputs // Outputs // Instantiate the Unit Under Test (UUT) t_ff uut ( . // Initialization of Inputs #100. BG Nagar Page 26 . t = 0.VLSI Lab Manual reg t. end endmodule Waveform: iii) SR FLIPFLOP: BGSIT. wire q. initial begin t = 0. t = 1. #100 t = 1.clk = 1.q_bar(q_bar) ). .clk(clk). reg clk.

Once the outputs are established.VLSI Lab Manual Symbol and truth table Design Description: An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the inputs are turned off. bottom =0). The reset input causes the opposite to happen (top = 1. Waveform: // VERILOG CODE BGSIT. This simple flip flop circuit has a set input (S) and a reset input (R). the wiring of the circuit is maintained until S or R go high. or power is turned of to the circuit. The set input causes the output of 0 (top output) and 1 (bottom output). BG Nagar Page 27 .

output rer q. end else if(s==1 & r==0) begin q=1.r) begin if(clk==1) begin if(s==0 & r==1) begin q=0.r. end else if(s==1 & r==1) begin q=1'bz. qb=~q. qb=~q.s. qb= 1'bz.qb).qb. end end end endmodule //Test bench structure module rsff_v. BGSIT.r.q. BG Nagar Page 28 . input clk.s. always @(clk.VLSI Lab Manual module sr_ff(clk.s. qb=~q. end else if(s==0 & r==0) begin q=q.

end endmodule Waveform: r = 0. #100. r = 1.clk(clk). s = 1.reg s. BG Nagar Page 29 . #100.q(q). . // Outputs // Instantiate the Unit Under Test (UUT) ff uut ( initial begin clk = 0. r = 0. s = 0. . clk = 1. clk = 1. clk = 1.VLSI Lab Manual reg clk . wire qb. . .qb(qb) ). . r = 0. reg r. #100. IV) JK FLIP FLOP: BGSIT.s(s).r(r). clk = 1. #100. // Inputs wire q. // Initialization of the Inputs #100. s = 1. s = 1. r = 1. s = 0.

that is to say that the output at time t is complemented at time t+1. The difference is that the J-K flip-flop does not have any invalid states. Notice that for J=1 and K=1 the output toggles. Waveform: // VERILOG CODE module jk_ff(clk. Its function is identical to that of the S-R flip flop in the SET. RESET and HOLD conditions of operation.VLSI Lab Manual Symbol and truth table: Design Description: The J-K flip-flop is perhaps the most widely used type of flip-flop.q.k.qb). BG Nagar Page 30 . The logic symbol for the J-K flip-flop is presented in Figure 3-8 and its corresponding truth table is listed in Table 3-5.j. BGSIT.

qb. reg q. qb=~q. qb=~q. qb=~q. k.qb.VLSI Lab Manual input clk.j. end else if(j==1 & k==1) q=~q. end else if(j==1 & k==0) begin q=1. j. qb=~q. output q.k) begin if(clk==1) begin if(j==0 & k==1) begin q=0. always @(clk. end else if(j==0 & k==0) begin q=q. BG Nagar Page 31 . BGSIT. end end endmodule //Test bench structure module jk_v.

j = 0. qb.qb(qb) ). j = 0. . end endmodule Waveform: k = 0. clk = 1.q(q). j = 1.SR. Write Verilog Code of Parallel adder circuits and their Test Bench for verification Objective: BGSIT. clk = 1. #100. // Inputs wire q. k = 1. #100. Conclusion: Design of Flipflops(D. clk = 1.k(k). j = 1. . // Outputs // Instantiate the Unit Under Test (UUT) jk_ff uut (. k = 0. j. #100.VLSI Lab Manual reg clk. k . clk = 1. initial begin clk = 0. j = 0. .JK) in xilinx tool and is verified according to the truth Table. k = 1. #100. PARALLEL ADDER 6. #100.j(j). BG Nagar Page 32 . k = 0.T.clk(clk). .

Design Description: Parallel adders are digital circuits that compute the addition of variable binary strings of equivalent or different size in parallel. BG Nagar Page 33 . A number of full adders may be added to the ripple carry adder or ripple carry adders of different sizes may be cascaded in order to accommodate binary vector strings of larger sizes. BGSIT. For an n-bit parallel adder. it requires n computational elements (FA).VLSI Lab Manual To design parallel adder in verilog using xilinx tool and verify it on ISE simulator Tools : Xilinx ISE simulator . Block diagram of parallel adder.

// VERILOG CODE module padd(x. output s.c3).c3. output [3:0] sum.VLSI Lab Manual It is composed of four full adders.sum[0]. endmodule // Test bench code module aaa_v.y[2]. input [3:0] x. . assign s=a^b^cin. sum[1]. sum. reg c.cout).c0.cin. The final result creates a sum of four bits plus a carry out (c4).sum[3]. The carry out is then transmitted to the carry in of the next higher-order bit. input a. assign c0=(a&b)|(b&cin)|(cin&a). // Inputs wire [3:0] sum. . sum[2].cin. .y(y). FA stage3(x[3].y[3]. FA stage2(x[2]. s.x(x).sum(sum). // Outputs // Instantiate the Unit Under Test (UUT) padd uut ( . The augend’s bits of x are added to the addend bits of y respectfully of their binary position Each bit 6 addition creates a sum and a carry out.c0). reg [3:0] y. endmodule // Function of full Adder module FA(a.c1. c.c2).b.y. cout). FA stage0(x[0].c. input c. reg [3:0] x.c1).b.y[0].y[1]. wire cout. output cout. FA stage1(x[1]. BG Nagar Page 34 .y.c(c).c2. BGSIT.

VLSI Lab Manual . x = 4'b1011. c = 0. COUNTER 7. #100. c = 1. y = 4'b1100. y = 4'b0101. #100. Write Verilog Code of counter circuits and their Test Bench for verification Objective: To design counter in verilog using xilinx tool and verify it on ISE simulator BGSIT. #100. y = 4'b1011. initial begin // Initialize Inputs x = 4'b0101. end endmodule Waveform: Conclusion: Design of Parallel Adder in xilinx tool and is verified according to the truth Table. c = 0. x = 4'b0001. BG Nagar Page 35 .cout(cout) ).

Circuit Diagram: 1) 4bit Up Counter: Block diagram and truth table of Up counter.VLSI Lab Manual Tools : Xilinx ISE simulator . BG Nagar Page 36 . we are using edge-triggered master-slave flip-flops similar to those in the Sequential portion of these pages. output D is the high order of the count. Thus. while output A is the BGSIT. The output of each flipflop changes state on the falling edge (1-to-0 transition) of the T input. The count held by this counter is read in the reverse order from the order in which the flip-flops are triggered. Design Description: In the 4-bit counter to the right.

However. and runs from 0000 (decimal 0) to 1111 (decimal 15). BG Nagar Page 37 . that 1 bit is not held by any flip-flop and is therefore lost. the counter actually reverts to 0000. As a result. The next clock pulse will cause the counter to try to increment to 10000 (decimal 16). The binary count held by the counter is then DCBA. and the count begins again.VLSI Lab Manual low order. Waveform: BGSIT.

// VERILOG CODE BGSIT. BG Nagar Page 38 .VLSI Lab Manual 2) 4 bit Down counter: Block diagram and truth table of Down counter.

reset(reset).VLSI Lab Manual module counter_1 (clock . counter_out ). . output [3:0] counter_out . BGSIT.reset . always @ (posedge clock) begin if (reset == 0) counter_out <= 4'b0000. // Inputs wire [3:0] counter_out.clock(clock). input clock . reset . BG Nagar Page 39 . reg reset. reg [3:0] counter_out .counter_out(counter_out) ).//for down cntr counter_out<=counter_out-1. end endmodule //Test bench code module counter_tb_v. . else counter_out <= counter_out + 1. reg clock. // Outputs // Instantiate the Unit Under Test (UUT) counter_1 uut ( .

// cntd for further counts.VLSI Lab Manual initial begin // Initialize Inputs clock = 1. clock = 1. reset = 0. BG Nagar Page 40 . #10. #10.reset = 1. reset = 1. clock = 0. end endmodule Waveform: Up counter Down counter BGSIT. #10.

VLSI Lab Manual 3) Decade 4-bit Synchronous Counter: BGSIT. BG Nagar Page 41 .

else counter_out <= counter_out + 1. counter_out ). reset .VLSI Lab Manual Waveform: // VERILOG CODE module counter_1 (clock . output [3:0] counter_out . end endmodule //Test bench code BGSIT. BG Nagar Page 42 . if(counter_out== 4'b1001) counter_out<=4'b0000.reset . input clock . always @ (posedge clock) begin if (reset == 0) counter_out <= 4'b0000. reg [3:0] counter_out .

reset(reset).clock(clock). #10.reset = 1. . end endmodule Waveform: .counter_out(counter_out) ). clock = 1. reg reset.reset = 1. reg clock. // Inputs wire [3:0] counter_out. initial begin // Initialize Inputs clock = 1. // Outputs // Instantiate the Unit Under Test (UUT) counter_1 uut ( .reset = 0. #10.VLSI Lab Manual module ssss_v. BG Nagar Page 43 . Conclusion: Design of Counters in xilinx tool and is verified according to the truth Table. SUCCESSIVE APPROXIMATION ADC BGSIT. #10. //cntd for upto 14 counts. clock = 0.

3. A successive approximation register subcircuit designed to supply an approximate digital code of Vin to the internal DAC. BG Nagar Page 44 . Write Verilog Code of A successive approximation ADC circuits and their Test Bench for verification Objective: To design SAR in verilog using xilinx tool and verify it on ISE simulator Tools : Xilinx ISE simulator .VLSI Lab Manual 8. Circuit Diagram: successive approximation ADC: Design Description: A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion The successive approximation Analog to digital converter circuit typically consists of four chief subcircuits: 1. BGSIT. 2. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive approximation register (SAR). A sample and hold circuit to acquire the input voltage (Vin).

4. otherwise. Then the next bit is set to 1 and the same test is done. PART .VLSI Lab Manual An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital code output of the SAR for comparison with Vin. the bit is left a 1. BG Nagar Page 45 . which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. continuing this binary search until every bit in the SAR has been tested. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC). This code is fed into the DAC.B ANALOG DESIGN BGSIT. The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1.

VLSI Lab Manual Design the circuits with given specifications*. Extract RC and back annotate the same and verify the Design e. BGSIT. completing the design flow mentioned below: a. Draw the Layout and verify the DRC. ERC c. Check for LVS d.SCHEMATIC (S-edit): Start the tanner EDA by using the desktop shortcut or by using the  Start  Programs  tanner EDA tanner tool v13. Verify & Optimize Time.0 S-edit. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. BG Nagar Page 46 . Power and Area to the given constraint*** Steps to use Tanner tool: i.

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0 L-edit BGSIT.VLSI Lab Manual ii) Layout (L-edit): Start  Programs  tanner EDA tanner tool v13. BG Nagar Page 54 .

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BG Nagar Page 65 .VLSI Lab Manual INVERTER BGSIT.

print dc v(out) .in+ SIN (0 2m 1k) AC 1 .lib "C:\IMS\Technology_file\Generic_025.87 v3 in+ GND 3.dc lin source v4 -5 5 . BG Nagar Page 66 .print tran v(out) v(in-) .lib" TT .END Layout: BGSIT.2 v4 in.ac dec 10 1 10g .VLSI Lab Manual Design Description: In digital logic an Inverter or a NOT gateis a logic gate which implements logical negation.op .1 .tran .print ac vp(out) vdb(out) .01m 5m . Netlist: v1 vdd GND 5 v2 vref GND 3.

BG Nagar Page 67 .VLSI Lab Manual Waveform: SINGLE STAGE AMPLIFIER BGSIT.

if we required lesser gain we will go for single stage amplifier.end Layout: BGSIT.op .01m 5m . BG Nagar Page 68 . Netlist: v1 vdd GND 5 v2 vref GND 3.VLSI Lab Manual Design Description: The need of the amplifier is to amplify the weak input signal coming from transducers so that while traveling a longer distance signal or power would not get distorted and at the output stage we want.ac dec 10 10 10g . The predicted output gain of single stage amplifier should be 35 dB.lib" TT .tran .dc lin source v4 -5 5 .2 v4 vinp vinm SIN (0 2m 1k) AC 1 .print dc v(out) .87 v3 vinm GND 3.lib "C:\IMS\Technology_file\Generic_025.print ac vp(out) vdb(out) .print tran v(out) v(vinp) .1 .

VLSI Lab Manual Waveform: COMMON SOURCE AMPLIFIER BGSIT. BG Nagar Page 69 .

op .lib" TT .print dc v(out) . which amplifies the input voltage about 30 times.tran .VLSI Lab Manual Design Description: A common-source amplifier. The capacitor connected to the source is supposed to act as a short circuit at the input frequency.ac dec 10 1 10g .1 .lib "C:\IMS\Technology_file\Generic_025. Netlist: v1 vdd GND 5 v2 vbias GND 3. The predicted output gain is of common source amplifier should be 56.18 dB. The drain current goes through a resistor.print tran v(out) v(vinp) . A change in input causes a change in drain voltage.print ac vdb(out) vp(out) . The gain of this amplifier is determined partly the transconductance of the MOSFET.2 v4 vinp vinm SIN (0 2m 1k) AC 1 .87 v3 vinm GND 3. BG Nagar Page 70 .dc lin source v4 -5 5 . This depends on the bias point in the circuit.end BGSIT. This means that a change in the gate voltage causes a change in the drain current. so it and the source resistor can be ignored.01m 5m .

BG Nagar Page 71 .VLSI Lab Manual Layout: Waveform: COMMON DRAIN AMPLIFIER BGSIT.

It finds application in situation in which we need to connect a voltage signal source that is providing a signal of reasonable magnitude but has a very hih internal resistance to much smaller load resistance that has a unity gain voltage buffer amplifier.1 . The predicted output gain is of common drain amplifier should be 57dB.print tran v(out) v(vinp) .print ac vdb(out) vp(out) BGSIT.tran .VLSI Lab Manual Design Description: Common-drain amplifier is also known as source follower or grounded drain amplifier the voltage at the source follows that the gate giving the circuit its popular name of source follower.1 v4 vinp vinm SIN (0 2m 1k) AC 1 .ac dec 10 1 10g .79 v3 vinm GND 3.01m 5m .lib" TT .dc lin source v4 -5 5 .lib "C:\IMS\Technology_file\Generic_025. Netlist: v1 vdd GND 5 v2 vbias GND 3. BG Nagar Page 72 .

op Layout: Waveform: R2R DAC BGSIT.VLSI Lab Manual .print dc v(out) . BG Nagar Page 73 .

BG Nagar Page 74 . DAC design required several different precise input resistor values :one unique value per binary input bit.lib" TT BGSIT. Each bit contributes its part to the resulting voltage on the output Netlist: v1 vdd GND 5 v2 vin GND 2. The bits. enter the network via a resistor of a double value than the rest of the network.print tran v(out) .lib "C:\IMS\Technology_file\Generic_025.tran 10n 8500n . either at 0 or operating voltage.5 v3 b0 GND PULSE (5 0 0 1n 1n 500n 1000n) v4 b1 GND PULSE (5 0 0 1n 1n 1000n 2000n) v5 b2 GND PULSE (5 0 0 1n 1n 2000n 4000n) v6 b3 GND PULSE (5 0 0 1n 1n 4000n 8000n) .VLSI Lab Manual Design Description: An alternative to the binary weighted-input DAC is so called R/2R DAC which uses fewer unique resistor values.

end Layout: Waveform: BGSIT.VLSI Lab Manual .op . BG Nagar Page 75 .

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