TIRUMALA ENGINEERING COLLEGE

NARASARAOPET

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Name Designation Department Mail ID www.onlinepanorama.blogspot.com : Mr. P. Ramesh : Assistant Professor : ECE

: rameshjust4u@gmail.com

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IC APPLICATIONS AND ECAD LAB MANUAL III BTECH, ECE 1st SEMESTER

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IC APPLICATIONS AND ECAD LAB
SYLLABUS
Minimum Twelve Experiments to be conducted: (Six from each part A & B) PART A (IC APPLICATIONS LAB): 1. 2. 3. 4. 5. 6. 7. OP AMP Applications - Adder, Subtractor, Comparator circuits. Active Filter Applications - LPF, HPF [ first order ] Function Generator using OP AMPS. IC 555 timer- Monostable and Astable Operation Circuit. IC 566 - VCO Applications. Voltage regulator using IC 723. 4 bit DAC using OP AMP

PART B (ECAD LAB): Simulate the internel structure of the following Digital IC’s using VHDL/VERILOG and verify the operations of the Digital IC’s (Hardware) in the Laboratory: 1. D-flip flop - IC 7474 2. Decade counter - IC 7490 3. Shifts registers - IC 7495 4. 3 - 8 Decoder - IC 74138 5. 4-bit Comparator - IC 7485 6. 8 x 1 Multiplexer - IC 74151 and 2 x 4 Demultiplexer – IC 74155 7. RAM (16 x 4) – IC 74189 (Read and Write operations)

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IC APPLICATIONS AND ECAD LAB
PART A (IC APPLICATIONS LAB): 1. OP AMP Applications - Adder, Subtractor, Comparator circuits. 2. Active Filter Applications - LPF, HPF [ first order ] 3. Function Generator using OP AMPS. 4. IC 555 timer- Monostable and Astable Operation Circuit. 5. Voltage regulator using IC 723. 6. 4 bit DAC using OP AMP

PART B (ECAD LAB): 1. D-flip flop - IC 7474 2. Decade counter - IC 7490 3. Shifts registers - IC 7495 4. 3 - 8 Decoder - IC 74138 5. 4-bit Comparator - IC 7485 6. 8 x 1 Multiplexer - IC 74150

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PART A: IC APPLICATIONS LAB

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1. OP AMP APPLICATIONS - ADDER, SUBTRACTOR, COMPARATOR CIRCUITS
AIM: To study the applications of IC 741 as adder, sub tractor, comparator. APPARATUS: 1. IC 741 2. Resistors (1KΩ)—4 3. Function generator 4. Regulated power supply 5. IC bread board trainer 6. CRO 7. Patch cards and CRO probes CIRCUIT DIAGRAM: Adder:

Subtractor:

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Comparator:

THEORY: ADDER: Op-Amp may be used to design a circuit whose output is the sum of several input signals such as circuit is called a summing amplifier or summer. We can obtain either inverting or non inverting summer. The circuit diagrams shows a two input inverting summing amplifier. It has two input voltages V1and V2, two input resistors R1 ,R2 and a feedback resistor Rf. Assuming that op-amp is in ideal conditions and input bias current is assumed to be zero, there is no voltage drop across the resistor Rcomp and hence the non inverting input terminal is at ground potential. By taking nodal equations. V1/R1 +V2/R2 +V0/Rf =0 V0 = - [(Rf/R1) V1 +(Rf/R2) V2] And here R1 = R2 = Rf = 1KΩ V0 = -(V1 +V2) Thus output is inverted and sum of input.

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SUBTRACTOR: A basic differential amplifier can be used as a sub tractor. It has two input signals V1 and V2 and two input resistances R1 and R2 and a feedback resistor Rf. The input signals scaled to the desired values by selecting appropriate values for the external resistors. From the figure, the output voltage of the differential amplifier with a gain of ‘1’ is V0 = -R/Rf(V2-V1) V0 = V1-V2. Also R1 =R2 = Rf =1KΩ. Thus, the output voltage V0 is equal to the voltage V1 applied to the non inverting terminal minus voltage V2 applied to inverting terminal. Hence the circuit is sub tractor. COMPARATOR: A comparator is a circuit which compares a signal voltage applied at one input of an op-amp with a known reference voltage at the other input . It is basically an open loop op-amp with output ±Vsat as in the ideal transfer characteristics. It is clear that the change in the output state takes place with an increment in input Vi of only 2mv. This is the uncertainty region where output cannot be directly defined There are basically 2 types of comparators. 1. Non inverting comparator and. 2. Inverting comparator. The applications of comparator are zero crossing detector , window detector, time marker generator and phase meter. OBSERVATIONS: ADDER: V1(volts) V2(volts) Theoretical V0 = -(V1+V2) Practical V0 = -(V1+V2)

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SUBTRACTOR: V1(volts) V2(volts) Theoretical V0 = (V1-V2) Practical V0 = (V1-V2)

COMPARATOR: Voltage input Vref Observed square wave amplitude

MODEL GRAPH:

PROCEDURE: ADDER: 1. connections are made as per the circuit diagram. 2. Apply input voltage 1) V1= 5v,V2=2v 2) V1= 5v,V2=5v 3) V1= 5v,V2=7v. 3. Using Millimeter measure the dc output voltage at the output terminal. 4. For different values of V1 and V2 measure the output voltage.

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SUBTRACTOR: 1. Connections are made as per the circuit diagram. 2. Apply input voltage 1) V1= 5v,V2=2v 2) V1= 5v,V2=5v 3) V1= 5v,V2=7v. 3. Using multi meter measure the dc output voltage at the output terminal. 4. For different values of V1 and V2 measure the output voltage. COMPARATOR: 1. Connections are made as per the circuit diagram. 2. Select the sine wave of 10V peak to peak , 1K Hz frequency. 3. Apply the reference voltage 2V and trace the input and output wave forms. 4. Superimpose input and output waveforms and measure sine wave amplitude with reference to Vref. 5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe the waveforms. 6. Replace sine wave input with 5V dc voltage and Vref= 0V. 7. Observe dc voltage at output using CRO. 8. Slowly increase Vref voltage and observe the change in saturation voltage. PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The operation of IC 741 Op-Amp as adder, sub tractor and comparator is studied and values are noted.

VIVA QUESTIONS: 1. What is an op-amp? 2. What are ideal characteristics of op amp? 3. What is the function of adder? 4. What is meant by comparator?

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2. ACTIVE FILTER APPLICATIONS - LPF, HPF [ FIRST ORDER ]
AIM: To study Op-Amp as firs order LPF and first order HPF and to obtain frequency response. APPARATUS: 1. 2. 3. 4. 5. 6. 7. 8. IC 741. Resistors (10KΩ--2, 560Ω, 330Ω Capacitors(0.1Ω) Bread board trainer CRO Function generator connecting wires Patch cards.

CIRCUIT DIAGRAM: (a) LPF

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(a) HPF

THEORY: LOWPASS FILTER: The first order low pass butter worth filter uses an Rc network for filtering. The op-amp is used in the non inverting configuration, hence it does not load down the RC network. Resistor R1 and R2 determine the gain of the filter. V0/Vin = Af/(1+ jf/fh) Af = 1 + Rf/R1 = pass band gain of filter . F = frequency of the input signal. Fh = 1/2ΠRC =High cutt off frequency of filter . V0/Vin = Gain of the filter as afunction of frequency The gain magnitude and phase angle equations of the LPF the can be obtained by converting V0/Vin into its equivalent polar form as follows |V0/Vin| = Af/(√1 +(f/fl)2) Φ = - tan-1(f/fh) Where Φ is the phase angle in degrees . The operation of the LPF can be verified from the gain magnitude equation.

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1. At very low frequencies i.e f<fh, |V0/Vin| = Af. 2. At f =fh , |V0/Vin| = Af/√2. 3. At f>fh , |V0/Vin|<Af. HIGH PASS FILTER: High pass filters are often formed simply by interchanging frequency. Determining resistors and capacitors in LPFs that is ,a first order HPF is formed from a first order LPF by interchanging components ‘R’ and ‘C’ figure. Shows a first order butter worth HpF with a lower cut off frequency of ‘Fl’. This is the frequency at which magnitude of the gain is 0.707 times its pass band value. Obviously all frequencies, with the highest frequency determinate by the closed loop band width of op-amp. For the first order HPF , the output voltage is V0 =[1 + Rf/R1] j2ΠRCVin/(1 - j2ΠfRC) V0/Vin =Af[j(f/fl)/(1 =j(f/fl)] Where Af + Rf/R1 a pass band gain of the filter. F =frequency of input signal. Fl =1/2ΠRC = lower cutt off frequency Hence, the magnitude of the voltage gain is |V0/Vin| =Af(f/fl)/√1+(f/f1)2. Since, HPFs are formed from LPFs simply by interchanging R’s and C’s .The design and frequency scaling procedures of the LPFs are also applicable to HPFs. PROCEDURE: 1. 2. 3. 4. 5. 6. 7. 8. Connections are made as per the circuit diagram. Apply sine wave of amplitude 4Vp-p to the non inverting input terminal. Values the input signal frequency. Note down the corresponding output voltage. Calculate gain in db. Tabulate the values. Plot a graph between frequency and gain. Identify stop band and pass band from the graph.

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OBSERVATIONS: Low Pass Filter Frequency(Hz) V0(V) Gain in 20log(V0/Vi) db=

High Pass Filter Frequency(Hz) V0(V) Gain in 20log(V0/Vi) db=

MODEL GRAPH: High Pass Filter

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Low Pass Filter

PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The frequency response of LPF and HPF is plotted using IC741 Op-Amp.

VIVA QUESTIONS: 1. What is the function of the filter? 2. What are the different types of filters? 3. Define pass band and stop band of filters? 4. Define cut off frequency? 5. What is the difference between HPF&LPF?

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3. FUNCTION GENERATOR USING OP AMPS
AIM: To generate triangular and square wave forms and to determine the time period of the waveforms. APPARATUS: 1. Op-Amp IC 741 –2 Nos 2. Bread board IC trainer 3. Capacitor 0.1µF 4. Zener diodes (6.2V)—2 Nos 5. Resistors—10KΩ, 150KΩ1.5KΩ, 1MΩ, 8.2KΩCRO 6. Patch cards 7. Connecting wires CIRCUIT DIAGRAM:

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THEORY: The function generator consists of a comparator U1 and an integrator A2.The comparator U2 compares the voltage at point P continuously with the inverting input i.e., at zero volts. When voltage at P goes slightly below or above zero volts, the output of U1 is at the negative or positive saturation level, respectively. To illustrate the circuit operation let us set the output of U1 at positive saturation +Vsat (approximately +Vcc). This +Vsat is an input to the integrator U2. The output of U2, therefore will be a negative going ramp. Thus, one end of the voltage divider R2-R3 is the positive saturation voltage +Vast of U1 and the other is the negative going ramp of U2. When the negative going ramp attains a certain value –Vramp, point p is slightly below zero valts; hence the output of U1 will switch from positive saturation to negative saturation –Vsat (approximately –Vcc). This means that the output of U2 will now stop going negatively and will begin to go positively. The output of U2 will continue to increase until it reaches +Vramp. At this time the point P is slightly above zero volts. The sequence then repeats. The frequencies of the square are a function of the d.c supply voltage. Desired amplitude can be obtained by using approximate zeners at the output of U1. THEORETICAL VALUES: Time period, T= 4R5C (R3+R4)/ (R1+R2) = 0.492 msec. Positive peak ramp = VzR5/ (R1+R2) = 0.05 volts. PRACTICAL VALUES: Time periods of triangular wave= Time periods of square wave= Positive peak ramp= Voltage of square wave=

PROCEDURE: 1. The circuit is connected as shown in the figure. 2. The output of the comparator U1 is connected to the CRO through chennal1, to generate a square wave. 3. The output of the comparator U2 is connected to the CRO through chennal2, to generate a triangular wave. 4. The time periods of the square wave and triangular waves are noted and they are found to be equal.

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MODEL GRAPH:

PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The theoretical and practical values of time periods are found to be equal. VIVA QUESTIONS: 1. 2. 3. 4. Define function generator? Write some applications of function generator? What is the function of function generator? Draw the block diagram of function generator?

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4. IC 555 TIMER- MONOSTABLE AND ASTABLE OPERATION CIRCUIT MONOSTABLE OPERATION CIRCUIT:
AIM: To construct and study the operation of a monostable multivibrator using 555 IC timer. APPARATUS: 1. 2. 3. 4. 5. 6. THEORY: Monostable multivibrator is also known as triangular wave generator. It has one stable and one quasi stable state. The circuit is useful for generating single output pulse of time duration in response to a triggering signal. The width of the output pulse depends only on external components connected to the op-amp. The diode gives a negative triggering pulse. When the output is +Vsat, a diode clamps the capacitor voltage to 0.7V. then, a negative going triggering impulse magnitude Vi passing through RC and the negative triggering pulse is applied to the positive terminal. Let us assume that the circuit is instable state. The output V0i is at +Vsat. The diode D1 conducts and Vc the voltage across the capacitor ‘C’ gets clamped to 0.7V. the voltage at the positive input terminal through R1R2 potentiometer divider is +ßVsat. Now, if a negative trigger of magnitude Vi is applied to the positive terminal so that the effective signal is less than 0.7V.the output of the Op-Amp will switch from +Vsat to – Vsat. The diode will now get reverse biased and the capacitor starts charging exponentially to –Vsat. When the capacitor charge Vc becomes slightly more negative than –ßVsat, the output of the op-amp switches back to +Vsat. The capacitor ‘C’ now starts charging to +Vsat through R until Vc is 0.7V.  t / RC V0 = Vf +(Vi-Vf) е . ß = R2/(R1+R2) If Vsat >> Vp and R1=R2 and ß = 0.5, Then, T = 0.69RC. 555 IC timer Capacitors (0.1µF, 0.01µF) Resistors 10KΩ Bread board IC trainer CRO Connecting wires and Patch cards

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CIRCUIT DIAGRAM:

PROCEDURE: 1. 2. 3. 4. Connections are made as per the circuit diagram. Negative triggering is applied at the terminal 2. The output voltage is measured by connecting the channel-1 at pin3. The output voltage across capacitor is measured by connecting the channel-2 at the point ‘P’. 5. Theoretically the time period is calculated by T= 1.1R1C1 where R1 = 10KΩ C1 =0.1µF. 6. Practically the charging and discharging timers are measured and theoretical value of time period is measured with practical value

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MODELGRAPH:

PRECAUTIONS: 1. Make the null adjustment before applying the input signal. 2. Maintain proper vcc levels.

RESULT: Operation of monostable multivibrator using 555 IC trainers is studied and wave forms are noted. VIVA QUESTIONS: 1. What is another name for mono stable multi? 2. What is the purpose of pin reset? 3. Define duty cycle? 4. What are the various applications of one shot? 5. How many external triggers are necessary in one shot?

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ASTABLE OPERATION CIRCUIT:
AIM: To construct and study the operation of astable multivibrator using 555 timer APPARATUS: 1. IC 555 Timer 2. Resistors (10 KΩ, 4.7 KΩ) 3. Diode (IN 4007) 4. Capacitors (0.1µF, 0.01µF) 5. CRO 6. Patch cards 7. CRO Probes 8. Connecting wires CIRCUIT DIAGRAM:

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THEORY: A simple OP_AMP astable multivibrator is also called square wave generator and free running oscillator .The principle for the generation of square wave output is to force an OP_AMP to operate in the saturation region β=R2/(R1+R2) of the output is feedback to input. The output is also feedback to the negative input terminal after integrating by means of a RC LPF whenever the negative input just exceeds Vref, switching takes place resulting in a square wave output. In astable multivibrator both states are quasi stable states. When the output is +Vsat, the capacitor is now starts charging towards +Vsat through resistance R the voltage is held at +βVsat. This condition continuous until the charge on C just exceed βVsat.Then the capacitor begins to discharge towards – Vsat.Then the capacitor charges more and more negatively until its voltage just – βVsat.The frequency is determined by the time it takes the capacitor to charge from – βVsat and +βVsat Vc (t) =Vf+(Vi-Vf)e-t/RC Vc (t)=Vsat-Vsat(1+β)e-t/RC We get T1=RC ln((1+β)/(1-β)) T=2T1=2 RC ln ((1+β)/(1-β)),Vo(p-p)=2Vsat PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Pins 4 and 8 are shorted and connected to power supply Vcc (+5V) 3. Between pins 8 and 7 resistor R1 of 10KΩ is connected and between 7 and 6 resistor R2 of 4.7KΩ is connected. Pins 2 and 6 short circuited. 4. In between pins 1 and 5 a Capacitor of 0.01µF is connected. 5. The out put is connected across the pin 3 and GND. 6. In between pins 6 and GND a Capacitor of 0.1μF is connected. 7. Theoretically with out diode charging time Tc is given by Tc=0.69(R1+R2) C1, Discharging time Td is given by Td= 0.69R2C1 The frequency f is given by f= 1.45/(R1+2R2)C1 %of Duty cycle is (Tc/(Tc+Td))*100 8. Practically Td and Tc are measured and wave forms are noted and theoretical Values are verified with practical values 9. Connect diode between pins 7 and 2. 10. Theoretically with diode connected charging time is given by Tc=0.69R1C1 Discharging time is given by Td=0.69R2C1 11. Practically Td and Tc are noted and verified with theoretical values.

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OBSERVATIONS: With diode Theoretical Practical without diode Practical

Theoretical

MODEL GRAPH:

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PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels.

RESULT: The Operation of astable multivibrator using IC 555 timer is studied. VIVA QUESTIONS: 1. 2. 3. 4. 5. Define astable multi? Explain the pulse width of the astable multi? What is the other name for astable multi? Write one application of free running oscillator? How many external triggers are necessary for astable?

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5. VOLTAGE REGULATOR USING IC 723
AIM: To plot the regulation characteristics of the given IC LM 723.

APPARATUS: 1. 2. 3. 4. 5. 6. 7. 8. Bread board IC LM 723 Resistors(7.8KΩ ,3.9KΩ ) RPS DRB Capacitors 100µF Patch cards Connecting wires

CIRCUIT DIAGRAM:

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THEORY: A voltage regulator is a circuit that supplies constant voltage regardless of changes in load currents. Except for the switching regulators, all other types of regulators are called linear regulators. IC LM 723 is general purpose regulator. The input voltage of this 723 IC is 40 V maximum. Output voltage adjustable from 2V to 30 V. 150mA output current external pass transistor. Out put currents in excess of 10Ampere possible by adding external transistors. It can be used as either a linear or a switching regulator. The variation of DC output voltage as a function of DC load current is called regulation. % Regulation =[(Vnl-Vfl)/Vfl]*100 PROCEDURE: (1).LINE REGULATION 1. Connections are made as per the circuit diagram 2. Power supply is connected to 12 and 7 terminals 3. Volt meter is connected to 10 and 7 terminals 4. By increasing the input voltage corresponding volt meter reading is noted. (2).LOAD REGULATION 1. Connect the load to the terminals 10 and GND. 2. Keep the input voltage constant at which line regulation is obtained 3. The maximum load value is calculated from IC ratings. 4. Now, we decrease the load resistance and note down the corresponding value Of the output in volt meter. 5. Plot the graph for load verses load regulation.

OBSERVATIONS: (1).LINE REGULATION: Vnl= Line voltage (V) Output voltage(V)

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(2).LOAD REGULATION: Regulated output(V) Load current(mA) Load resistance(KΩ) Load regulation

% REGULATION=[(Vnl-Vfl)/Vfl]*100

MODEL GRAPH:

PRECAUTIONS: 1. While taking the readings of regulated output voltage load regulation , keep the input voltage constant at 15V. 2. Do not increase the input voltage more than 30 V while taking the reading for no load condition?

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RESULT: The regulation characteristics of the given IC LM 723 are successfully plotted.

VIVA QUESTIONS: 1. What is regulator? 2. What is meant by line regulation? 3. What is meant by load regulation? 4. Formula for % REGULATION? 5. What is full load in voltage regulation?

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6. 4 BIT DAC USING OP AMP
AIM: To construct and study digital to analog converter circuit. APPARATUS: IC 741 Multi meters Patch cards Connecting wires Resistors 1k, 2k, 8k IC bread board trainer

CIRCUIT DIAGRAM: (a) Weighted resistor DAC:

(b)R-2R ladder DAC

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THEORY: A digital to analog converter is used when a binary output from a digital system must be converted to equivalent analog voltage or current . A DAC converter uses an op amp and binary weighted resistors or R-2r ladder resistors. Weighted resistor DAC: It has n electronic switches –d1, d2, d3……….dn controlled by binary input Word. These switches are single pole double throw type. If the binary input to a particular switch is 1,it connects resistance to the reference voltage (-vr).And if the input is 0,the switch connects the resistor to the ground. The output current I0 for an ideal op amp can be written as I0=I1+I2+…………..In Vr/2Rd1+Vr/4Rd2+…….+Vr/2nRdn=V0=I0Rf=VrRf/R(d1,2….n) The weighted resistor DAC circuit uses a negative reference voltage .The analog output voltage is positive stair case .For a 3bit weighted resistor DAC (1) if the op amp is connected in non inverting mode, it can be connected in non inverting mode also .(2)The op amp is working as current to voltage converter.(3) The polarity of reference voltage is in accordance with type of switch used. R-2R ladder DAC: In binary weighted resistors method are used. This can be avoided by using R2R ladder type DAC where only 2 values of resistors are required .The binary inputs are simulated by switches B0-B3 and output is proportional to the binary inputs. Binary inputs can be high (+5V)or low(0V).

PROCEDURE: 1. Connections are made as per circuit diagram. 2. Pin2 is connected to resistor 1MΩand ground. 3. +Vcc are available at Pin7 and –Vcc is applied at Pin4. 4. Output is taken between pin6 and ground 5. Voltage at each bit (vr) is found at bits b0, b1, b2, b3. 6. Pin3 of op amp is connected to resistor 1kΩ and is given to b3 (msb). 7. A resistor of 2kΩ is connected between pin2 and pin 6 of op amp.

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OBSERVATIONS: D3 D2 D1 D0 Binary weighted R-2R ladder DAC (v)_________________________ resistor(v) Theoretical practical Theoretical practical

RESULT: Thus digital to analog converter is constructed and studied. VIVA QUESTIONS: 1. What is meant by resolution of DAC? 2. What is meant by linearity of DAC? 3. What is meant by accuracy of DAC? 4. What is meant by DAC? 5. What is disadvantage of weighted resistor DAC? 6. What is the value of resistor required in weighted resistor DAC if LSB resistor value is 12KΩ for 4 bit DAC? 7. What are the applications of DAC?

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7. IC 566 – VCO APPLICATIONS
AIM: To operate the NE/SE 566 as Voltage Controlled Oscillator and to find the frequencies for various values of R1 and C1; APPARATUS: 1. IC NE/SE 566 2. Resistors (1KΩ, 5KΩ, 4KΩ, 6KΩ, 8KΩ) 3. Capacitors (0.001μF,0.0001μF) 3. Function generator 4. Regulated power supply 5. IC bread board trainer 6. CRO 7. Patch cards and CRO probes CIRCUIT DIAGRAM:

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THEORY: Voltage Controlled Oscillator is also called as voltage to frequency converter. It provides the simultaneous square wave and triangular wave output. The frequency of output wave is the function of input voltage, hence the name Voltage Controlled Oscillator. Output frequency is also the function of external resistor R1 and capacitor C1. The output frequency fO is given by,

fO =
Where

2(V  VC ) R1C1V

3 V  VC  V ; 2KΩ < R! < 20KΩ 4

The triangular wave is generated by alternately charging the external capacitor C1 by one current source and then linearly discharging it by another. The charge discharge levels are determined by Schmitt trigger action. The external modulating signal is ac coupled with capacitor C at the pin 5. Now the output frequency is varied according to the amplitude of this applied modulating voltage. VCO is commonly used in converting low-frequency signals such as electroenphalograms (EEG) or electrocardiograms (ECG) into an audio frequency range signals, which can be transmitted over telephone lines or two way radio communication for diagnostic purposes.

PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Measure the output voltage and frequency of both triangular and squares. 3. Vary the values of R1 and C1 and measure the frequency of the waveforms. 4. Compare the measured values with the theoretical values.

OBSERVATIONS: Sl. No. R1 C1 Output Voltage (V) Square wave Triangular wave Theoretical frequency (KHz) 2(V  VC ) fO = R1C1V Practical frequency (KHz)

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MODEL GRAPH:

PRECAUTIONS: 1. Connect the wires properly. 2. Maintain proper Vcc levels. RESULT: The NE/SE 566 is operated as Voltage Controlled Oscillator also the output frequency for various values of R1 and C1 are observed. VIVA QUESTIONS: 1. What are the applications of VCO? 2. Draw the pin diagram of NE/SE 566. 3. What is the need of connecting 0.001μF capacitor between pin 5 and pin 6?

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PART B: ECAD LAB

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SIMULATION

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1. D FLIP-FLOP - 7474
AIM: Simulation and verification of D-FLIP FLOP using IC-74LS74A. APPARATUS: 1. Personal computer 2. Active HDL -1 no. -ver. 3.5

PROGRAM: library ieee; use ieee.std_logic_1164.all; entity dff is port(d,clk,pre_l,clr_l:in std_logic;q,qn:out std_logic); end dff; architecture dff1 of dff is signal pre,clr:std_logic; begin process(clk,pre_l,pre,clr_l,clr) begin pre<=not pre_l; clr<=not clr_l; if(clr='1' and pre='0')then q<='0';qn<='1'; elsif(pre='1'and clr ='0')then q<='1';qn<='0'; elsif( clk'event and clk='1')then q<=d;qn<=not d; end if; end process; end dff1; SIMULATION OUTPUTS:

RESULT: D flip-flop is simulated and verified.

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Owner: sivakumar @ ece in tec

2. DECADE COUNTER- 7490
AIM: Simulation and verification of DECADE COUNTER using IC-7490. APPARATUS: 1. Personal computer 2. Active HDL -1 no. -ver. 3.5

PROGRAM: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dec is port(clk,rst,st:in std_logic;cout:out std_logic_vector(3 downto 0)); end dec; architecture dec of dec is signal ci:std_logic_vector(3 downto 0):="0000"; begin process (clk) begin if rst='1' then ci<="0000"; elsif st='1' then ci<="1001"; elsif(clk'event and clk='1') then ci<=ci+'1'; if(ci="1001")then ci<="0000"; end if; end if; end process; cout<=ci; end dec; SIMULATION OUTPUTS:

RESULT: Decade counter is simulated and verified.

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Owner: sivakumar @ ece in tec

3. SHIFT REGISTERS- 7495
AIM: Simulation and verification of SHIFT REGISTER usingIC-7495A. APPARATUS: 1. Personal computer 2. Active HDL -1 no. -ver. 3.5

PROGRAM: library ieee; use ieee.std_logic_1164.all; entity shiftregister is port(clk,sein,mode:in std_logic; pllin:in std_logic_vector(3 downto 0); cout:out std_logic_vector(3 downto 0)); end shiftregister; architecture sr of shiftregister is signal cout1:std_logic_vector(3 downto 0); begin process (clk) begin if (mode='1' and sein='0')then cout1<=pllin; elsif (mode='0' and sein='1')then cout1(0)<='1'; cout1(1)<='0'; cout1(2)<='0'; cout1(3)<='0'; else cout1<="0000" ; end if; end process; cout<=cout1; end sr; SIMULATION OUTPUTS:

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Owner: sivakumar @ ece in tec

RESULT: shift register is simulated and verified

4. 3-8 DECODER- 74138
AIM: Simulation and verification of 3-8 DECODERS using IC-74138. APPARATUS: 1. Personal computer 2. Active HDL -1 no. -ver. 3.5

PROGRAM: library ieee; use ieee.std_logic_1164.all; entity dec38 is port(e1,e2,e3:in std_logic; a:in std_logic_vector(2 downto 0); cout:out std_logic_vector(7 downto 0)); end dec38; architecture dec38 of dec38 is signal cout1:std_logic_vector(7 downto 0); begin process(a,e1,e2,e3) begin if( not e1 and not e2 and e3) ='1' then cout1<="11111111"; else case a is when "000"=> cout1<="01111111"; when "001"=> cout1<="10111111"; when "010"=> cout1<="11011111"; when "011"=> cout1<="11101111"; when "100"=> cout1<="11110111"; when "101"=> cout1<="11111011"; when "110"=> cout1<="11111101"; when "111"=> cout1<="11111110"; when others=>cout1<="11111111"; end case; end if; end process; cout<=cout1; end dec38;

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SIMULATION OUTPUTS :

RESULT: 3-8 DECODERS using IC-74138 is simulated and verified.

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Owner: sivakumar @ ece in tec

5. 4 BIT COMPARATOR- 7485 AIM: Simulation and verification of 4 BIT COMPARATOR using IC-7485. APPARATUS: 1. Personal computer 2. Active HDL -1 no. -ver. 3.5

PROGRAM: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity cmp4 is port(a,b:in bit_vector(3 downto 0); a_gt_b,a_eq_b,a_lt_b: out bit); end cmp4; architecture cmp4 of cmp4 is begin process(a,b) begin if(a>b) then a_gt_b<='1'; a_lt_b<='0'; a_eq_b<='0'; elsif(a<b)then a_gt_b<='0'; a_lt_b<='1'; a_eq_b<='0'; else a_gt_b<='0'; a_lt_b<='0'; a_eq_b<='1'; end if; end process; end cmp4; SIMULATION OUTPUTS :

RESULT: 4 BIT COMPARATOR using IC-7485 is simulated and verified. www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

6. 8 x 1 MULTIPLEXER- 74150
AIM: Simulation and verification of 8 x 1 MULTIPLEXER using IC-74150. APPARATUS: 1. Personal computer 2. Active HDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity mux8 is port(a,b,c,d,e,f,g,h,strobe:in std_logic; ds:in std_logic_vector(2 downto 0); z:out std_logic); end mux8; architecture mux8 of mux8 is signal z1 : std_logic; begin process(strobe,a,b,c,d,e,f,g,h) begin if strobe='1' then z1<='1'; elsif strobe='0' then case ds is when "000"=>z1<=not a; when "001"=>z1<=not b; when "010"=> z1<=not c; when "011"=> z1<=not d; when "100"=> z1<=not e; when "101"=> z1<=not f; when "110"=> z1<=not g; when "111"=> z1<=not h; when others=>z1<='1'; end case; end if; end process; z<=z1; end mux8; -1 no. -ver. 3.5

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SIMULATION OUTPUTS :

RESULT: 8*1 MULTIPLEXER using IC-74150 is simulated and verified

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Owner: sivakumar @ ece in tec

7. RAM (16X4)
AIM: Simulation and verification of RAM (16 X 4). APPARATUS: 1. Personal computer 2. Active HDL PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.all; use iEEE.std_logic_unsigned.all; entity rammemory is port( rw : in STD_LOGIC; clk : in STD_LOGIC; addr : in STD_LOGIC_vector( 3 downto 0); datain : in STD_LOGIC_vector(3 downto 0); dataout : out STD_LOGIC_vector(3 downto 0) ); end rammemory; architecture ram1 of rammemory is type mem_type is array(15 downto 0)of std_logic_vector(3 downto 0); signal memory:mem_type; begin process (clk, rw) begin if (clk='1' and clk'event)then if rw ='1' then -- write mode memory (conv_integer(addr)) <= datain; else dataout <=memory(conv_integer(addr)); --read mode end if; end if; end process; end ram1; -1 no. -ver. 3.5

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SIMULATION OUTPUTS:
50 100 150 200 250 300 350 400 450 500 550 600 650 700 ns

memory rw clk addr addr(3) addr(2) addr(1) addr(0) datain datain(3) datain(2) datain(1) datain(0) dataout
U 0 1 2 0 1 2

(U,U,U,U,U,U,U,U,U,U,U,U,U,2,1,0)

1

0

2

1

0

RESULT: RAM (16X4) is simulated and verified.

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Owner: sivakumar @ ece in tec

HARDWARE

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1. D FLIP - FLOP- 7474
AIM: To verify the truth table of D-flip-flop using IC 7474. APPARATUS: 1. IC 74LS74. 2. Bread board IC trainer kit. 3. Patch cords. PIN DIAGRAM:

CIRCUIT DIAGRAM:

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LOGIC DIAGRAM:

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TRUTH TABLE:

THEORY: The D flip-flop is also known as the Data flip-flop or the Delay flip-flop. It is used to either store the data or introduce a delay. If a ‘0’ is given at Din ,then S is ‘0’ and R will be ‘1’. This resets the flip-flop. If a ‘1’ is given at Din, then S is ‘1’ and R ‘0’. This sets the flip-flop. Thus we find that Dout is always equal to Din. Hence this flip-flop can be used to store a binary digit. So it is known as the Data flip-flop. The D flip-flop can also be clocked similar to the RS flip-flop. In the clocked D flip-flop Dout will be made equal to Din only when the clock arrives. Thus the data bit is sent to the output after a delay. Therefore, the D flip-flop is also known as the Delay flip-flop. PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Connect the preset terminal to logic ‘1’ and then clear the circuit by connecting the clear terminal to logic ‘0’. Observe Q and Q1. 3. Connect the preset terminal to logic ‘0’ and clear terminal to logic ‘1’. 4. Observe Q and Q1. 5. Now apply +ve edge triggered circuit clock and change the values of D to ‘0’ and ‘1’. 6. Now verify the values of Q and Q1. PRECAUTIONS: 1. Avoid loose connections. 2. Identify correctly the pin numbers. VIVA QUESTIONS: 1. What is D-FF? 2. Define a latch? 3. Define a FF? 4. What is the difference b/w latch & FF? 5. In flip-flop how many stable states are there? 6. What is edge triggering 7. What is level triggering 8. I/P of D-F/F =’1’, then what is the O/P value Q= RESULT: Truth table of D-flip-flop is verified. www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

2. DECADE COUNTER-7490
AIM: To study the operation of decade counter using IC7490. APPARATUS: 1. 2. 3. 4. IC 7490 Bread board IC trainer kit. Connecting wires. Patch cords.

PIN DIAGRAM:

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LOGIC SYMBOL:

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OBSERVATIONS: Decimal Equivalent output 0 1 2 3 4 5 6 7 8 9

QD 0 0 0 0 0 0 0 0 1 1

QC 0 0 0 0 1 1 1 1 0 0

QB 0 0 1 1 0 0 1 1 0 0

QA 0 1 0 1 0 1 0 1 0 1

THEORY: The decade counter (mod-10 counter) is used most often. In order to count from 0 through 9, a counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from 0 to15 (16 states). Out of these 16 states, we should skip any 6 states. In the decade counter, when the output is 1010(for the 10th clock pulse), all the flip-flops should be reset. Thus the outputs Q3 and Q1 are given directly to the inputs of the AND gate and the outputs Q2 and Q0 are given through inverters. Therefore, for the 10th clock pulse, the counter output would be 1010 for a moment. This sends the output of the AND gate to HIGH clearing all the flip-flops. Thus a decade counter has been developed. PROCEDURE: 1. Connect the circuit as shown in the figure. 2. The clock pulse is given to pin-14 of IC 7490. 3. The Vcc supply is given to pin-5 of IC 7490. 4. Pin-12 and pin-1 to be shorted. 5. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS) inputs. 6. Pins-13, 14 has no connections. 7. Pins-2, 3, 6, 7 are inputs and is always ‘0’. 8. Pins-12, 9,8,11 are outputs. 9. Feed MR terminal with ‘1’ and MS terminals with ‘0’ then the display shows ‘0’. 10. Feed MR terminal with ‘0’ and MS terminals with ‘1’ then the display shows ‘9’. www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

11. Feed MR terminal with ‘0’ and MS terminals with ‘0’,now apply clock then the output varies between the values ‘0’ and ‘9’. PRECAUTIONS: 1. Avoid loose connections on the bread board. 2. No connections are to be given to pins-13, 14. 3. Vcc should not exceed +5v.

VIVA QUESTIONS: 1. What is a counter? 2. what are the asynchronous inputs 3. To restrict the count value of a counter, if takes the help of inputs. 4. To restrict the count value of a counter, if takes the help of inputs. 5. Define mod –up counter. 6. Define mod –down counter. 7. Difference b/w mod-up counter and mod-down counter. RESULT: The working of the decade counter is studied.

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Owner: sivakumar @ ece in tec

3. SHIFT REGISTER - 7495
AIM: To verify the following functions of shift register using IC7495. 1. Clearing the register. 2. Serial input/parallel output. 3. Parallel input/ parallel output. 4. Parallel input/serial output. APPARATUS: 1. 2. 3. 4. Bread board. IC 7495. Patch cords. Connecting wires.

PIN DIAGRAM:

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CIRCUIT DIAGRAM:

THEORY: A shift register is an n-bit register with a provision for shifting its stored data by one bit position at each tick of the clock. The serial input, SERIN, specifies a new bit to be shifted into one end at each clock tick. This bit appears at the serial output, SEROUT, after ‘n’ clock ticks, and is lost one tick later. Thus, an n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks. A serial-in, parallel-out shift register has outputs for all of its stored bits, making them available to other circuits. Such a shift register can be used to perform serial-toparallel conversion. Conversely, it is possible to build a parallel-in, serial-out shift register. At each clock tick the register either loads new data from inputs 1D-ND or it shifts its current contents, depending on the value of the LOAD/SHIFT control input. The device uses a 2-input multiplexer on each flip-flop’s D input to select between the two cases. A parallel-in, serial-out shift register can be used to perform parallel-to-serial conversion. By providing outputs for all of the stored bits in a parallel-in shift register, we obtain the parallel-in, parallel-out shift register. Such a device is general enough to be used in any of the applications of the previous shift registers.

PROCEDURE: www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

1. Mount the IC 7495 on logic trainer and make the required connections. 2. Connect pins-2, 3, 4, 5 of the IC to logic switches SW1, SW2, SW3 and SW4 for applying low and high logic levels at this input. 3. The serial input is given to pin-1 and mode control to pin-6. 4. Pins-8 and 9 are shorted and connected to clock pulse. 5. Connect Vcc=+5v to pin-14. 6. Pin-7 is grounded. Clearing Function: 1. 2. 3. 4. Set the mode control switch to low. Set the serial input switch SW3 to low. Set parallel inputs A, B, C and D to logic ‘0’. To clear the registers apply clock pulses till the output is “0000”.

Serial input/parallel output: 1. After the register has been cleared, any 4-bit serial number can be loaded into the register. 2. Set mode control switch to low. 3. Set the serial input to high. 4. Apply a clock pulse which will shift the serial input ‘1’ into the register, in this case QA is ‘1’. 5. Return serial input switch SW3 to low and apply three clock pulses. The register will show an output of “00001”. We can load any 4-bit number into the register in this way. Parallel input/ parallel output: 1. Set the Mode Control to high. 2. Apply the following inputs at A,B,C and D A B C D 1 0 1 1 3. If we apply a clk pulse the word will be loaded into the register. Parallel input/serial output: 1. If the loaded input is “1011”.Set the Mode Control to low. 2. Set the serial input pin-1 to low. 3. As you apply clk pulse, the word will be shifted out serially from QD and after four clock pulses the register will be cleared.

PRECAUTIONS:

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1. All the pins should be identified properly. 2. Supply voltage should not exceed +5v. VIVA QUESTIONS: 1. What is a register? 2. What is a shift register? 3. What are the operations performed by a shift register? 4. Applications of SISO shift register. 5. Applications of PISO shift register. 6. Applications of SIPO shift register. 7. Applications of PIPO shift register. 8. What is the IC package? 9. What is a universal shift register? 10. What are the operations performed by a universal shift register? 11. Applications of SISO universal shift register. 12. Applications of PISO universal shift register. 13. Applications of SIPO universal shift register. 14. Applications of PIPO universal shift register. 15. What is the IC package? 16. Difference b/w shift register and universal shift register. RESULT: Various functions of shift register using IC 7495 are verified.

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4. 3 - 8 DECODER- 74138
AIM: To verify the operation of 3 to 8 line decoder using IC 74138. APPARATUS: 1. 2. 3. 4. IC 74138. Bread board trainer kit Patch cords Connecting wires.

PIN DIAGRAM:

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LOGIC DIAGRAM:

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OBSERVATIONS:

THEORY: Decoder is the combinational circuit which contains ‘n’ input lines to 2n output lines. The decoder is used for converting the binary code into the octal code. The IC74138 is the 3*8 decoder which contains three inputs and eight outputs and also three enables out of them two are active low and one is active high. Decoders are used in the circuit where required to get more outputs than that of the inputs which also used in the chip designing process for reducing the IC chip area. PROCEDURE: 1. Connect the circuit as shown in the figure. 2. Apply Vcc=+5v to the Pin-16 of IC 74138. 3. Connect the inputs to Pins-1, 2&3. 4. Pins-4, 5, 6 are the enable inputs. 5. When E11 is high and E21 ,E3 are low then all the outputs are high irrespective of inputs A0 ,A1 ,A2 . 6. Similarly when E21is high, all the outputs are high irrespective of the inputs. 7. When E3 is low all the outputs are high irrespective of E11 and E21 and high. 8. If E11 and E21 are low and E31 is high, the inputs are low, the outputs O01 will be low with all the other outputs are low. 9. Similarly by changing the inputs we get (one) 1 output as low and all other outputs as high. 10. When all inputs are high O71 will be low and all other will be high.

PRECAUTIONS: 1. All the pins should be identified properly. www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

2. Supply voltage should not exceed +5v. 3. Avoid loose connections on the bread board. VIVA QUESTIONS: 1. What is decoder? 2. What is a encoder? 3. For a 2- I/P decoder how many O/P’s are produced 4. A decoder with ‘n’ input produces max. of __ no.of minterms. 5. The general representation of an encoder is 6. Draw the 2 to 4 line decoder with only nor gates. 7. Difference b/w de multiplexer and decoder 8. The general representation of an encoder is for economical realization, decoder is used to realize a function which contain ( Less no. of don’t cares) 9. A 16 to 64 decoder can be obtained by cascading of 10. Can more than one decoder O/P be activated at one time? RESULT: The working of the 3 to 8 decoder is verified using IC 74138.

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Owner: sivakumar @ ece in tec

5. 4-BIT COMPARATOR- 7485 AIM: To verify the operation of 4-bit magnitude comparator using IC 7485. APPARATUS: 1. IC 7485. 2. Bread board IC trainer kit. 3. Patch cords.

PIN DIAGRAM:

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Owner: sivakumar @ ece in tec

LOGIC DIAGRAM:

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FUNCTION TABLE:

THEORY: Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR gates. The outputs of 4 XOR gates are ORed to create a 4-bit comparator. The IC 7485 is 4-bit magnitude comparator. With respect to the 8 inputs 3 inputs are cascaded inputs. After the 8 input operations are performed further the outputs are based on the cascaded inputs.

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PROCEDURE: 1. Connect the circuit as per Pin diagram. 2. Give the inputs A [A3 ,A2, A1, A0] and B [B3,B2,B1,B0] according to function table. 3. Give the cascaded inputs IA>B ,IA=B ,IA<B and verify the outputs. 4. Tabulate the inputs and outputs according to function table. PRECAUTIONS: 1. All the pins should be identified properly. 2. Supply voltage should not exceed +5v. 3. Avoid loose connections on the bread board. VIVA QUESTIONS: 1. What is Magnitude Comparator? 2. To form a 12 – bit comparator how many 4-bit comparators are connected in cascaded form. 3. The IC 7485 is a package and is a ____ comparator. 4. How many cascaded input are there for a 4-bit comparator.

RESULT: The operation of 4-bit magnitude comparator is verified using IC7485.

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Owner: sivakumar @ ece in tec

6. 8 x 1 MULTIPLEXER-74150
AIM: To verify the operation of 8*1 multiplexer using IC 74150. APPARATUS: 1. 2. 3. 4. IC74150. Bread board IC trainer kit. Patch cords. Connecting wires.

PIN DIAGRAM:

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LOGIC DIAGRAM:

TRUTH TABLE:

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THEORY: A multiplexer is a digital switch- it connects data from one of n sources to its output. An 8*1 is multiplexer consists of 3 input lines as select lines and 8 input lines and 1 output line. A multiplexer is a unidirectional device which follows the data from input lines to output lines. Multiplexers are obviously useful device in any application in which data must be multiple source to destination. A common application in computers is the mux between the processors registers and its ALU. PROCEDURE: 1. Connections are made as per logic diagram. 2. Connect the inputs D0 to D7 . 3. Give data select inputs and verify outputs according to truth table. PRECAUTIONS: 1. All the pins should be identified properly. 2. Supply voltage should not exceed +5v. 3. Avoid loose connections on the bread board. VIVA QUESTIONS: 1. Mux is an implementation of – 2. Multiplexer is represented by – 3. De multiplexer is represented by –

RESULT: 8*1 multiplexer is verified using IC74150. www.onlinepanorama.blogspot.com
Owner: sivakumar @ ece in tec

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