Background Calibrated Pipeline ADC

Dusan Stepanovic, prof. Borivoje Nikolic, UC Berkeley

ADC Specifications
Technology Sampling Frequency Resolution ENOB Supply voltage Power Maximum Input Voltage 130nm 400MHz 10 bits >9 bits 1.2V
Gain Gain vs. Vout 45 TT FF SS SF FS

BWRC Summer Research Retreat 06/01/09 06/02/09

Simple One-Stage Amplifiers

vOP

Architecture of Pipelined ADC

9 stages

Mathematical Pipeline ADC Model

Ccmfb

cmref

ncs

Ccmfb

1.5b stage
cmb

1.5b stage

1.5b stage

3.5b flash

vON

cmref

Input

refp

40

35

Output

<220mW (analog) 1.4Vpp

G G d OUT = VIN + 1 1 1 + 2 1 2 + ... + Gd 1 Gd 1 Gd 2 + VOS1 G1 G2 + VOS 2 + ... + VOSN Gd 1 Gd 1Gd 2

30

G
j =1 dj

N 1

N
dj

G 1 N + N N +1 + GdN Gdj
j =1

25

refn

20

Reference Ladder

Differential Comparators

Sparkle Encoder

GN

G
j =1

VOSeq

15 -1

-0.8

-0.6

-0.4

-0.2

0 Vout[V]

0.2

0.4

0.6

0.8

LMS Calibration
Vin
D(nM )

Non-recursive LMS Filtering

dOUT (nM )

Recursive LMS filtering

DN +1
D1
DN 1
s2
1 Gd 1

SNDR vs. Amplitude Simulation

DN
DN +1
60 58 56 54 SNDR [dB] 52 50 48 46 600m 700m 800m 900m 0.45 0.5 0.55 0.6 0.65 Input Signal Amplitude [V] 0.7 0.75

e
1

D1 w1 '

D2
w2 '

W(n )

N +1

wN +1 '

d OUT , final
VOSeq
z-1

s1
Gcorr
z-1

sN 1
1 GdN 1

sN
1 GdN

sN +1

M
M
e(n )

z-1

z-1

z-1

OS
d (n )

corr
e

e
e

d OUT

OS
d OUT , final

1 1 d OUT = D1 + Gd 1 D2 + Gd 1 D3 + ... + DN + GdN D N +1 2

)))

d OUT = D1 + D2

1 1 1 1 + D3 + ... + DN +1 = WD Gd 1 Gd 1 Gd 2 j =1 Gdj
N

s N +1 = DN +1

d OUT , final = Gcorr d OUT + VOSeq

Gcorr (n +1) = Gcorr (n ) + corr e(n )d OUT (n )
VOSeq (n + 1) = VOSeq (n ) + OS e(n )

Nonlinear calibration:
, i = 1,..., N
Gd 1

44 42 0.4

si = Di + G s
d OUT = s1

D = [D1

D2 ... DN +1 ]

1 di i +1

a1

a3

W = [w1

w2 ... wN +1 ]

Simulations done for four different reference voltages.

a5

Linear vs. Nonlinear Simulation

SNDR
62
85

Chip Photo and Bonding Diagram

Testing Board

Test Setup

SFDR

60

80

58
75

SNDR [dB]

56

SFDR [dB]

70

54

65

52 700m linear 700m nonlinear 800m linear 800m nonlinear 0.45 0.5 0.55 0.6 0.65 Input Signal Amplitude [V] 0.7 0.75
60 700m linear 700m nonlinear 800m linear 800m nonlinear 0.45 0.5 0.55 0.6 0.65 Input Signal Amplitude [V] 0.7 0.75

50

48 0.4

55 0.4

Simulations done for two different reference voltages. Nonlinear calibration extends input amplitude range and imporves dynamic range

Top Layer Additional 4 layers used as power planes.

Bottom Layer

Two low-jitter RF signal generators provide input signal and sampling clock Test board and iBOB connected via LVDS signals PC connected to iBOB via Xilinx programming tools and Matlab interface for data capture

Measurements for Different Sampling Frequencies

18 x 10
9

Measurement Results and Analysis Fs=100MHz

Noise Power vs. Frequency, Vin=1.4Vp-p
100 SD SFDR/SNDR Fs=100MHz SFDR SNDR 3.12ps Jitter Limit S/(T+J+D)

SNDR/SFDR vs. Analog Voltage Supply

SNDR/SFDR vs. Vdda Fs=300MHz 60

Pipeline ADC Measured Results

fs=100MHz 80

Reference SNDR/SFDR vs. Input Frequency 80 75 70 SNDR/SFDR [dB] 65 60 55 50 45 40 SFDR 100MHz SNDR 100MHz SFDR 180MHz SNDR 180MHz SFDR 360MHz SNDR 360MHz
16 14 Noise Power in Digital Domain 12

Measured Theoretical
90

fs=180MHz 70
ref SFDR ref SNDR raw SFDR raw SNDR cal SFDR cal SNDR

80 SFDR/SNDR[dB]

55
70

65 60 55 SNDR/SFDR [dB] 50 45 40 35

10 8 6 4

70

SNDR/SFDR [dB]

60

SNDR/SFDR [dB]

50

60

ref SFDR ref SNDR raw SFDR raw SNDR cal SFDR cal SNDR

50

50

45

2 0
40 0 20 40 60 80 100 120 Frequency[MHz] 140 160 180 200

40

20

40

60

80 100 120 Frequency[MHz]

140

160

180

200

40

20

40

60

80 100 120 140 Input Frequency [MHz]

160

180

200

Predictedjitterpowerfrommeasurementsat160MHz Thermalnoisefromzeroinputsignalmeasurements Addmeasuredsfdr power Verygoodmatchingconfirmsassumptionsaboutjitter noiselimitations

1 2f in

Pjitter Psig

3.1 ps

SFDR 1MHz SNDR 1MHz SFDR 162MHz SNDR 162MHz 1 1.05 1.1 1.15 1.2 Vdda[V] 1.25 1.3 1.35 1.4

30

30
20 0 20 40 60 80 100 120 140 Input Frequency [MHz] 160 180 200

25

20

40

60

80 100 120 140 Input Frequency [MHz]

160

180

200

35

Calculatedatfin=160MHz