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Misr International University Faculty of Engineering Electronics and Communications Department LAYOUT AND MICROWIND

Misr International University Faculty of Engineering Electronics and Communications Department

LAYOUT AND MICROWIND

TUTORIAL

DIGITAL ELECTRONICS II COURSE

Prepared By

Eng. Waleed El - Halwagy

NMOS, PMOS and CMOS Construction

As the CMOS is composed of NMOS and PMOS we should at first present their properties and construction.

NMOS Properties

1.

The Substrate : P Type.

2.

The Drain and Source : n+ diffusion.

3.

The Select Area : p+ select.

4.

The p + select is connected to ground.

5.

The current flows from D to S.

6.

The Drain voltage > The Source voltage

is connected to ground. 5. The current flows from D to S. 6. The Drain voltage

NMOS Construction

NMOS Construction

PMOS Properties

1.

The Substrate : n Type.

2.

The Drain and Source : p+ diffusion.

3.

The Select Area : n+ select.

4.

The n + select is connected to V DD .

5.

The current flows from S to D.

6.

The Source voltage > The Drain voltage

is connected to V D D . 5. The current flows from S to D. 6.

PMOS Properties

PMOS Properties

CMOS Inverter Construction

Elevation View

CMOS Inverter Construction Elevation View
CMOS Inverter Construction Elevation View

CMOS Inverter Construction

Top View

CMOS Inverter Construction Top View

CMOS Inverter Construction

3D View

CMOS Inverter Construction 3D View

Fabrication Process of the CMOS Inverter

Mask 1: N well mask in the P substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Mask 1: N-well mask in the P-substrate

Fabrication Process of the CMOS Inverter

Mask 2: Active Mask Creation ( n+ and p+ )

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Mask 2 : Active Mask Creation (n+ and p+)

Fabrication Process of the CMOS Inverter

Mask 3: Poly Silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Mask 3 : Poly silicon Mask Creation

Fabrication Process of the CMOS Inverter

Mask 4: P+ region Mask Creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Mask 4 : P+ region mask creation

Fabrication Process of the CMOS Inverter

Mask 5: n+ region Mask Creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Mask 5 : n+ region mask creation

Fabrication Process of the CMOS Inverter

Mask 6: Contacts Mask Creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Mask 6 : Contact mask creation

Fabrication Process of the CMOS Inverter

Mask 7: Metal Mask Creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

Mask 7 : Metal mask creation

The Design Rules and Layout

It provides a set of guidelines for constructing the various

masks needed in the patterning process.

Scalable Design Rules : all dimensions are given as a function of λ

Micron Rules : all design rules are expressed in absolute dimensions

The Design Rules

It provides a set of guidelines for constructing the various masks needed in the patterning process

The Design Rules acts as the interface or even the contract

between the circuit designer and the process engineer.

Circuit designers generally want tighter, smaller designs, which lead to higher performance and higher circuit

density. The

engineer

reproducible and high yield process.

the

other

hand,

process

on

wants

a

Consequently, design rules are a compromise that attempts to satisfy both sides.

Design rules consists of:

Minimum width requirements.

Minimum spacing requirements.

Minimum Surface requirements.

Requirements between objects on the same or different layers.

The Design Rules

Scalable Design Rules : all dimensions are given as a function of λ

Even for the same minimum dimension, design rules tend

to differ from company to company, and from process to process. This makes porting an existing design

between different processes a time consuming task.

To address this issue we can use the scalable design rules, which defines all the design rules as a function of a single parameter λ.

Scaling of the minimum dimension is accomplished by simply changing the value of λ. This results in a linear

scaling of all dimensions.

For a given process, λ is set to a specific value and all design dimensions are consequently translated into

absolute numbers.

Minimum Feature size = 2 λ

The Design Rules

Disadvantages of the Scalable design rules approach

Linear scaling is only possible over a limited range of dimensions (for example between 0.25 μm and 0.18 μm). When scaling over large ranges, the relations between

different layers tend to vary in a non-linear way that can

not be converted by the linear scaling rules. Scalable design rules are conservative, they represent a cross section over different technologies, and they must

represent the worst case rules for the whole set. This results

in over dimensioned and less dense designs. For these and other reasons, scalable design rules normally are avoided by industry. (while not entirely

accurate, the lambda rules are still useful to estimate the

impact of a technology scale on the design area).

The Design Rules

Micron Rules: all design rules are expressed in absolute dimensions

As circuit density is a prime goal in industrial designs, most semiconductor companies tend to use

the micron rules, which express all design rules in

absolute dimensions and thus can exploit the features of a given process to a maximum degree.

Scaling and porting designs between technologies under these rules is more demanding and has to be

performed either manually or by using advanced CAD tools.

What is a Layout ?

A layout consists of a combination of

polygons, each of which is attached to a certain layer. The functionality of the circuit is determined by the choice of the layers, as well as the interplay between objects on

different layers.

A transistor A MOS transistor is formed by the cross section of the diffusion layer and the poly silicon layer.

W L
W
L

The Objective Is to design the minimum size inverter in the 0.18 μm technology and develop its seven masks.

The Objective Is to design the minimum size inverter in the 0.18 μ m technology and

DESIGN AN 0.18 μm technology CMOS INVERTER ( 2 λ = 0.18 μm )

The technology is specified by its minimum line width (minimum feature size) which is usually taken as the channel length of the transistor and it is denoted by 2λ

Design using minimum sized NMOS and take the W PMOS = 3 W NMOS and take the channel length of both transistors as 2λ

First : Select the Design Technology from the Microwind

First : Select the Design Technology from the Microwind

To get the Design Rules of the chosen technology

To get the Design Rules of the chosen technology

First : The minimum sized NMOS Transistor

Design

First : The minimum sized NMOS Transistor Design
First : The minimum sized NMOS Transistor Design

First: Design the minimum sized NMOS transistor.

What do we need to construct an NMOS transistor ?

P substrate Poly silicon for the gate. n+ diffusion regions for the drain and source. P+ select region that is connected to ground. Contacts to connect the active area with the metal layer.

Remark:

The

in

fabrication is doped with Boron, that is its a P-type

silicon ignot .

Microwind

the

Silicon

assumes

ignot

used

What are the design rules we need to know to be able to construct the NMOS ?

The Minimum Poly Width = 2λ The Minimum Poly Area = 16 λ 2 The
The Minimum Poly Width = 2λ
The Minimum Poly Area = 16 λ 2
The Minimum extra Poly
surrounding the n diffusion = 3λ
The Minimum extra n diffusion surrounding
the poly = 4λ
The Minimum
The Minimum
extra n
n diffusion
Width = 4λ
diffusion
surrounding the
The Minimum
contact = 2λ
n diffusion
Area = 16 λ 2
The Minimum spacing
The Minimum Contact
between the contact
and the Poly = 3λ
Width = 2λ

What are the design rules we need to know to be able to construct the NMOS ?

The Minimum p diffusion Width = 4λ The Minimum spacing between contacts = 4λ The
The Minimum
p diffusion
Width = 4λ
The Minimum spacing
between contacts = 4λ
The Minimum
p diffusion
Area = 16 λ 2

How to Check that the design Rules of the layout are satisfied ?

Design Rule Check ( DRC )
Design Rule
Check ( DRC )

If any of these design rules are not satisfied, the Microwind will signify it.

If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.

If any of these design rules are not satisfied, the Microwind will signify it.

If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.
If any of these design rules are not satisfied, the Microwind will signify it.

Now what is the minimum size and area of the NMOS Transistor in the 0.18 μm technology ?

L : is the length of the poly silicon.

W : is the width of the n+ diffusion region.

From the design rules:

Minimum poly silicon length = 2 λ.

Minimum n+ diffusion width = 4 λ.

Taking into consideration that the minimum extra poly surrounding the n+ diffusion is 3 λ.

Taking into consideration that the minimum extra n+ diffusion surrounding the poly is 4 λ.

Now what is the minimum size of the NMOS Transistor in the 0.18 μm technology ?

L = 2 λ The Minimum W = 4 λ extra Poly Area = 10
L = 2 λ
The Minimum
W = 4 λ
extra Poly
Area = 10 λ x 10 λ
surrounding the n
diffusion = 3λ
The Minimum extra
The
The Minimum extra
The Minimum
n diffusion
Minimum
n diffusion
n diffusion
surrounding the
Poly Width
surrounding the
Width
poly = 4λ
L = 2λ
poly = 4λ
W= 4λ
The Minimum
extra Poly
surrounding the
n diffusion = 3λ

Now lets add the contacts.

The contacts Design Rules:

Minimum contact width = 2λ

Minimum extra diffusion surrounding the contact = 2λ.

Minimum spacing between the poly and contact = 3λ.

As we can see that the last two design rules are not satisfied when L D = 4λ and W = 4λ , so we have to expand

them as follows :

L L = = 4λ 4λ D D W = 4λ λ 2λ λ λ
L
L
= = 4λ 4λ
D D
W = 4λ
λ 2λ
λ
λ
λ

L D = 3λ (poly contact) + 2 λ (contact width)+ 2λ (contact diff.) = 7 λ

Now lets add the contacts.

L = 2λ W = 6 λ Extra Poly Area = 16 λ x 12
L = 2λ
W = 6 λ
Extra Poly
Area = 16 λ x 12 λ
Contact –
diff= 2λ
Contact
W = 6λ
width= 2λ
Contact –
diff= 2λ
Contact
Contact
Poly
Extra Poly
Poly –
Poly –
Contact
Contact
– diff
width
Width
contact
contact
width
– diff
L =2λ

Optimizing the Aspect ratio and area of the NMOS Transistor

From the above discussion we conclude that:

Minimum L = minimum poly width = 2λ.

Minimum W = 2 ( minimum contact - diff) + minimum contact width = 6 λ.

The Question now is can not we optimize this aspect ratio.

We can not decrease L because we can not implement a dimension that is less than 2λ.

But from the design rules, the minimum diffusion width is 4λ. We were forced to implement it as 6λ due to the contact design rules constraints.

By a small trick we could let W = 4λ without altering the contact design rules constraints.

This can be accomplished by reducing the diffusion width to 4λ at

the poly silicon surface and widening it in the region surrounding

the contact.

Optimizing the Aspect ratio and area of the NMOS Transistor

7λ L =2λ 7λ Extra Poly 3λ diffusion Diffusion width at width at the poly
L =2λ
Extra Poly
diffusion
Diffusion
width at
width at
the poly
the
W = 4λ
contact
Extra Poly
L = 2λ
W = 4 λ
Area = 16 λ x 10 λ

Adding the P-select region

Taking into consideration the contact design rules restrictions Area of p select = 6λ x 6λ

L = 2λ Extra Poly W = 4 λ 2λ 3λ Area = 22 λ
L = 2λ
Extra Poly
W = 4 λ
Area = 22 λ x 10 λ
Contact
diff
Diffusion
width at
Contact
Contact –
the poly
width
Contact
W = 4λ
Contact
– diff
Extra Poly
Contact Contact
Poly –
Poly
Poly –
Contact
Contact Contact
Contact
Contact
– diff
width
contact
Width
contact
width
– diff – diff
width
– diff
L =2λ

Second : The PMOS Transistor Design

L PMOS = 2λ

and

W PMOS = 3 W NMOS

Second : The PMOS Transistor Design L PMOS = 2 λ a n d W PMOS
Second : The PMOS Transistor Design L PMOS = 2 λ a n d W PMOS

Now Design The PMOS with L PMOS = 2λ

and

W PMOS = 3 W NMOS

What do we need to construct a PMOS transistor ?

N well

Poly silicon for the gate.

p+ diffusion regions for the drain and source.

n+ select region that is connected to ground.

Contacts to connect the active area with the metal layer.

There are some additional design rules that we will need to know concerning the N-well before we proceed in our design of the PMOS.

The design rules concerning with the minimum width and area of the diffusion as well as the relation between the

poly and the contacts with the diffusion are the same for both n-type and p-type.

Design Rules Concerning the N-well

The minimum extra The minimum extra n-well surrounding the p diffusion = 2 λ n-well
The minimum extra
The minimum extra
n-well surrounding
the p diffusion = 2 λ
n-well surrounding
the p diffusion = 6 λ
The Minimum
n-well Area
= 144 λ 2
The Minimum
n-well Width
= 10 λ

The Number of Contacts in the PMOS

As a rule: the more the number of contacts, the

better the performance. This is because the

resistance through which the current flows will

decrease.

The following equation gives a relation between the diffusion width and the number of contacts.

W =

2 ( contact diff.) + N ( contact width )

+

( N 1 ) ( contact contact )

Example : W = 18 λ

W 18 λ
W
18 λ

18 λ = 2 ( 2 λ )+ N ( 2 λ ) + ( N 1 ) ( 4 λ ) ------- N = 3 contacts

Example : W = 17 λ 17 λ = 2 ( 2 λ )+ N ( 2 λ ) + ( N 1 ) ( 4 λ ) -------- N = 2.83, that is N = 2 contacts

L 2 λ 2 λ 2 λ 2 λ 2 λ 2 λ 3 λ
L
2 λ 2 λ
2 λ 2 λ 2 λ 2 λ
3 λ
2 λ
3 λ
2 λ 2 λ
6 λ
2 λ
2
λ
2 λ
W
24 λ
4 λ
12 λ
2
λ
2
λ
3
λ
L = 2λ
6 λ
W = 12 λ
3
λ
Area = 30 λ x 24 λ
30
λ

The CMOS is Constructed by connecting the NMOS and PMOS transistors together

The CMOS is Constructed by connecting the NMOS and PMOS transistors together
The CMOS is Constructed by connecting the NMOS and PMOS transistors together

The CMOS is constructed by interconnecting both the NMOS and PMOS

There are some additional design rule that must be taken in consideration when interconnecting the NMOS and PMOS to construct the CMOS Inverter.

The minimum spacing between the n-well of the PMOS and the n+ diffusion (drain) of the NMOS = 6 λ.

The metal used in the connections

Minimum metal width = 6 λ Minimum metal surface = 16 λ

Minimum Spacing between metal layers = 4 λ

Minimum extra metal surrounding the contact = 2 λ

We need metal to

NMOS: Connect the p+ select with the source to ground

PMOS: Connect the n+ select with the source to V

Connect the NMOS and PMOS drains to the output.

Connect the poly to the input.

NMOS :

L = 2λ

W = 4 λ

PMOS :

CMOS Area = 58 λ x 24 λ

L = 2λ

W = 12 λ

The minimum extra

metal surrounding the contact = 2 λ

The minimum metal spacing = 4 λ

the contact = 2 λ The minimum metal spacing = 4 λ The minimum spacing between

The minimum spacing between the n-well and

n-diffusion = 6 λ

The Seven Masks Extraction

After we have finished the CMOS layout design and computed its dimensions, we are ready to

extract the seven inverter masks to send them to the Fab to be manufactured.

CMOS Inverter Layout

CMOS Inverter Layout

Mask 1 : N well Mask

Mask 1 : N – well Mask

Mask 2 : Active Area Mask

Mask 2 : Active Area Mask

Mask 3 : Poly Silicon Mask

Mask 3 : Poly Silicon Mask

Mask 4 : p + Region Mask

Mask 4 : p + Region Mask

Mask 5 : n + Region Mask

Mask 5 : n + Region Mask

Mask 6 : Contacts Mask

Mask 6 : Contacts Mask

Mask 7 : Metal Mask

Mask 7 : Metal Mask