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Verification of digital Logic gates Verification of Boolean Theorems using Digital Logic Gates Design and Implementation of Combinational Circuits using basic gates for arbitrary functions Study of flip flops Design and implementation of adders and subtractors using logic gates Design and implementation of code converters using logic gates 1.BCD to excess-3 code and vice versa 2.binary to gray and vice versa 7. Design and implementation of 4 bit binary adder/subtractor and BCD adder using IC 7483 CYCLE 2 8. Design and implementation of 2 bit magnitude comparator using logic gates 8 bit magnitude comparator using IC 7485 9. Design and implementation of 16 bit odd/even parity checker generator using IC 74180 10. Design and implementation of multiplexer and de multiplexer using logic gates and study of IC 74150 and IC 74154 11. Design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147 12. Construction and verification of 4 bit ripple counter and MOD -10/MOD-12 Ripple counters 13. 14. Design and implementation of 3-bit synchronous up/down counter Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops

AUGMENTED EXPERIMENTS 1. Design and implementation of a synchronous counter using JK flip flop to count the following sequence 7,4,3,1,5,0,7 2. To design and implement the given Boolean function using multiplexer

1. VERIFICATION OF DIGITAL LOGIC GATES

Aim: To study the fundamental laws of Boolean algebra using AND, OR, NAND, NOR, EXOR and NOT gates.

Equipments required: Digital Trainer Kit IC 7400 - NAND IC IC 7402 - NOR IC IC 7404 - NOT IC IC 7408 - AND IC IC 7432 - OR IC IC 7486 - EXOR IC

Theory: The elemental blocks in a logic device are called digital logic gates. An AND gate has two or more inputs and a single output. The output of an AND gate is true only if all the inputs are true. An OR gate has two or more inputs and a single output. The output of an OR gate is true if any one of the inputs is true and is false if all of the inputs are false. An INVERTER has a single input and a single output terminal and can change a true signal to a false signal, thus performing the NOT function. An NAND gate has two or more inputs and a single output. The output of an NAND gate is true if any one of the inputs is false and is false if all the inputs are true. An NOR gate has two or more inputs and a single output. The output of an NOR gate is true if all the inputs are false and is false if the inputs are different. An EXCLUSIVE OR gate has two or more inputs and a single output. The output of an EXCLUSIVE OR gate is true if the inputs are different and is false if the inputs are the same.

Procedure: sthe power is off before you build anything. 1. Plug the chips you will be using into the breadboard. Point all the chips in the same direction with pin 1 at the upper-left corner. (Pin1 is often identified by a dot or a notch next to it on the chip package) 2. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard. 3. Connect the inputs of one of the gates to SW1 and SW2 (switches), and connect the output of the gate to Logic Indicator A (an LED). 4. Turn power on. 5. Flip the switches and observe the LEDs to confirm that the chip works as it should (for the switches, the up position is logic HIGH). 6. Test the possible combinations of inputs to verify the gate works as it should and fill in the truth table. 7. Turn the power off. 8. Repeat the above steps for each of the remaining gates.

Result: Thus the fundamental laws of Boolean algebra using AND, OR, NAND, NOR, EXOR and NOT gates were studied.

Pin Diagrams: AND GATE TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1

OR GATE TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 NOT GATE TRUTH TABLE A 0 1 Y 1 0 EX-OR GATE TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0 .

NAND-GATE TRUTHTABLE A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 NOR-GATE TRUTHTABLE A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 .

A+A¶=1 A. Verify the truth table for both LHS & RHS of the following postulates and theorems.2.1=A 2. Involution (A¶)¶=A . VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES Aim: To study the fundamental theorems of Boolean algebra using logic gates Equipments required: Digital Trainer kit IC 7432 ± OR IC IC 7408 ± AND IC Procedure: 1. Design the circuit diagram using basic gates 2.A=A 4. A+0=A A.0=0 5. A+A=A A.A¶=0 3. 1. A+1=1 A.

B).(A+C) 9.C) = (A. DeMorgan¶s theorem (A+B)¶=A¶B¶ (AB)¶=A¶+B¶ 10. Absorption Theorem A+AB=A A(A+B)=A Result: Thus the fundamental theorems of Boolean algebra were studied using logic gates .C) = (A+B). Commutative Law: A+B=B+A A.6.B=B.(B.A 7. Associative Law: A+(B+C) = (A+B)+C A. Distributive Law: A.C 8.(B+C) = (A.B)+C A+(B.

Consider as an example the following Boolean function: F = A + B¶C The function F is equal to 1 if A is equal to 1.3. A Boolean function expresses the logical relationship between binary variables. It is evaluated by determining the binary value of the expression for all the possible values of the variables. the function can be equal to either 1 or 0. F is equal to 0 otherwise. A Boolean function described by an algebraic expression consists of binary variables. DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING BASIC GATES FOR ARBITRARY FUNCTIONS Aim: To minimize and implement the Boolean functions by designing the combinational circuits using logic gates Equipments Required: Digital Trainer Kit IC 7400 . .or if both B¶ and C are equal to 1.NOR IC IC 7404 ± NOT IC IC 7408 ± AND IC IC 7432 ± OR IC IC 7486 ± EXOR IC Theory: Boolean algebra is an algebra that deals with binary variables and logic operations.NAND IC IC 7402 . and the logic operation symbols. For a given value of binary variables. the constants 0 and 1.

The number of rows in the truth table is 2. . The logic circuit diagram for F is shown in the above figure. A truth table is a list of combinations of 1¶s and 0¶s assigned to the binary variables and a column that shows the value of the function for each binary combination. There is an AND gate for the term B¶ C and an OR gate that combines the two terms. the variables of the function are taken as the input of the circuit and the binary variable F is taken as the output of the circuit. In logic-circuit diagrams.Gate implementation of F = A + B¶ C A C B F A Boolean function can be transformed from an algebraic expression into a circuit diagram composed of logic gates. Truth table for F = A + B¶ C A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 0 0 1 1 1 1 A Boolean function can be represented in the truth table. where n is the number of variables in the function. There is an inverter for input B to generate the complement.

Y=(A+B¶+C¶)(A+B¶+C) 2.Procedure: 1. Exercise: 1. Draw the truth table for the given exercise problems using the above description. Design the circuit diagram 2. . 3. Y=A¶B¶C¶+A¶B¶C+A¶BC¶+AB¶C¶+AB¶C Result: Thus Boolean functions were implemented by designing the combinational circuits using logic gates. Check the output.

STUDY OF FLIP FLOPS USING ICS Aim: To study the characteristics of RS. Verify the truth table of all the Flip Flops. D and T flip flops using IC¶s. JK. the flip-flop switches to its complement state that is the flip-flop toggles its output. The D input has only two inputs D and clk. Procedure: 1. Connect the circuit as shown in logic connections for JK.4. D and T flip flops using IC¶s were studied. Inputs J and K behave like S and R to set and clear the flip-flops respectively. When both inputs J and K are equal to 1. . T Flip Flop: The T flip flop is a single input version of the JK flip-flop. D and T Flip Flops. This is done in D flip flop. D Flip Flop: One way to eliminate the undesirable condition of the indeterminate state in the RS flip flop is to ensure that inputs S and R are never equal to 1 at the same time. If D=1 and clk=1 output goes to 1 and if D=0 and clk =1 then output goes to 0. The T flip-flop is obtained from the JK flip-flop when both inputs are together. 2. Equipments Required: Digital trainer kit IC 7476 ± JK Flip Flop Theory: JK Flip Flop: A JK Flip Flop is a refinement of the RS Flip Flop in that the indeterminate state of the RS type is defined in the JK type. The designation T comes from the ability of the flip-flop to toggle its state. JK. Result: Thus the characteristics of RS.

Truth Table: Pin details: Logic connections: .

A half adder circuit needs two binary inputs and binary outputs.The S output represents the least significant bit of the sum. S=X¶Y+XY¶ C=XY .4. The carry output is 0 unless both inputs are 1. The input variable designate the augend and the addend bits. The simplified Boolean functions for the two outputs can be obtained directly fro the truth table. ADDERS AND SUBTRACTORS Aim: To construct an adder and subtractor circuit using logic gates and to verify its truth tables. Equipments Required: Digital Trainer kit IC 7408 ± AND IC IC 7432 ±OR IC IC 7486 ± EXOR IC IC 7404 ± NOT IC Theory: HALF ADDER: A combinational circuit that performs the addition of two bits is called half adder. The output variables produce the sum and the carry.

The simplified Boolean functions for the two outputs can be easily obtained directly from the truth table. It consists of three inputs and two outputs. Binary variable C gives the output carry.the output is 0. The output variables produce the difference and borrow. The two outputs are designated by the symbols S for sum and C for carry.The c output has a carry of 1 if two or three inputs are equal to 1.FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of three input bis.The S output is equal to 1 when only one input is equal to 1. S=X¶YC¶+X¶YZ¶+XY¶Z¶+XYZ C=XY+XZ+YZ HALF SUBTRACTOR: A half subtractor is a combinational circuit that subtracts two bits and produces their differences. D=X¶Y+XY¶ B=X¶Y . A half subtractor needs two binary inputs and two binary outputs. When all inputs are 0. The input variable designate minuend and subtrahend bits. The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The binary variable S gives the value of the least significant bits of the sum.

FULL SUBTRACTOR: A full subtractor is a combinational circuit that performs a subtraction between three bits. The simplified Boolean functions for the two outputs can be obtained directly from the truth table. Verify the truth table Result: Thus an adder and subtractor circuit using logic gates were constructed and its truth tables were verified. b and c denote the minuend subtrahend and previous borrow. D= X¶Y¶Z+X¶YZ¶+XY¶Z¶+XYZ B=X¶Y+X¶Z+YZ Procedure: 1. 1 may have been borrowed by a lower significant bit. . The connections are given as per the circuit diagram 2. This circuit has three inputs and 2 outputs. The three inputs a. The two outputs D and B represents the difference and output borrow.

CIRCUIT DIAGRAM: HALF ADDER X INPUT X Y 0 1 0 1 OUTPUT S 0 1 1 0 C 0 0 0 1 Y 0 0 1 1 FULL ADDER INPUT X S X 0 Y 0 0 C 0 1 Z 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 OUTPUT S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1 .

HALF SUBTRACTOR X B INPUT Y D X 0 0 1 1 Y 0 1 0 1 OUTPUT B 0 1 0 0 D 0 1 1 0 FULL SUBTRACTOR X B Y D Z INPUT X 0 0 0 0 1 1 1 Y 0 0 1 1 0 0 1 Z 0 1 0 1 0 1 0 OUTPUT B 0 1 1 1 0 0 0 D 0 1 1 0 1 0 0 .

a BCD to excess -3 and vice versa Equipments required: Digital Trainer kit IC 7486 . For hexadecimal 12 can e represented in BCD as 0001 0010. The conversion of gray code to binary code can be electronically achieved by using EXOR gates Excess3 code is the modified form of BCD number. a four bit binary number to a gray code number and vice versa. DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING LOGIC GATES Aim: To design and implement a combinational circuit with four inputs and four outputs that converts 1. The excess3 code can be derived from the natural BCD code by adding 3 to each coded number. Gray code is a special purpose code and these codes are applied for error detection and error correction. Connect the circuit and verify the truth table.1 1 1 1 1 6. adding decimal 3 represented in BCD as 0011 to each digit we get excess 3 code as 0100 0101(12 in decimal).XOR IC Theory: Gray code belongs to a class of codes called minimum change codes in which only one bit in the code group changes when going from one step to the next. 2. With this information. the truth table for BCD to excess 3 code converter can be determined as shown in the tabulation. Procedure: 1.Now. It is also called Mirror reflecting code. .

a BCD to excess -3 and vice versa .Result: Thus a combinational circuit with four inputs and four outputs was designed and implemented that converts 1. a four bit binary number to a gray code number and vice versa. 2.

TRUTH TABLE: Conversion of gray code to binary Decimal Gray code ABCD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 Binary Code WXYZ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 .

Conversion of BCD to Excess 3 Decimal BCD EXCESS3 ABCD WXYZ 0 1 2 3 4 5 6 7 8 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 .

CIRCUIT DIAGRAM: BINARY TO GRAY W X Y Z A A=W B=WX¶+W¶X C=XY¶+X¶Y D=YZ¶+Y¶Z B C D GRAY TO BINARY A B C D W X Y Z W=A .

X=AB¶+A¶B Y=XC¶+C¶X Z=YD¶+DY¶ BCD TO EXCESS3 A B C D z y x w Z=D¶ Y=CD+C¶D¶ X=B¶C+B¶D+BC¶D¶ W=A+BC+BD .

EXCESS3 TO BCD W X Y Z A B C D A=Z¶ B=YZ+Y¶Z¶ C=X¶Y¶+XYZ+WYZ¶ D=WYZ+WX .

the input carry C0 is equal to 1 and the sum output is A plus the 2¶s complement of B. the input carry is equal to 0 and the sum generates A + B. 4-BIT BINARY ADDER / SUBTRACTOR AND BCD ADDER Aim: To design and implement a 4-bit binary Adder / Subtractor and 4 bit BCD adder using IC7483 Equipments Required: Digital Trainer Kit IC 7483 IC 7486-XOR IC Theory: IC 7483 is a 4-bit binary parallel adder. The sum is in proper BCD form. Add two BCD numbers using ordinary Binary addition. The 4-bit sum is obtained from S1 through S4. 2. 3. If the 4 bit sum is greater than 9 or if a carry is generated from the fourth bit sum. add them to the four bits of A. C0 is the input carry and C4 is the output carry. If 4 bit sum is equal to or less than 9. we complement the four bits of B. Thus when the mode select M = 1.7. Four EXOR gates complement the bits of B when the mode select M = 1 (because x 1 = x¶) and leave the bits of B unchanged when M = 0 (because x 0 = x). To perform A ± B. no correction is needed. When M is equal to 0. The Procedure for BCD addition is as given below: 1. . The subtraction of two binary numbers can be done by taking the 2¶s complement of the subtrahend and adding it to the minuend. the sum is invalid. and add 1 through the input carry. The 2¶s complement can be obtained by taking the 1¶s complement and adding 1. The two 4-bit input binary numbers are A1 through A4 and B1 through B4.

add it to the next higher order BCD digit.4. To correct the invalid sum add 0110 to the fourth bit sum. Inputs S3 S2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Outputs S0 Y 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 S1S0 00 S3S2 00 01 11 10 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 01 11 10 Y=s3s2+s3s1 Procedure: . If a carry results from this addition. Thus to implement BCD adder we require y y y Four bit binary adder for initial addition Logic circuit to detect sum greater than 9 and One more 4 bit adder to add 0110 in the sum if the sum is greater than 9 or carry is 1.

1. Test the 4-bit binary adder 7483 by connecting the power supply and ground terminals. 2. Then connect the four A inputs to a fixed binary number such as 1001 and the B inputs and the input carry to the five toggle switches. 3. Set the mode = 0 for 4 bit binary addition. 4. The five outputs are applied to indicator lamps. 5. Perform the addition of a few binary numbers and check that the output carry gives proper values. 6. Repeat the steps with mode =1 for binary subtraction. 7. Also show that when A u B, the subtraction operation gives the correct answer, A ± B, and the output carry C4 is equal to 1. But when A < B, the subtraction gives the 2¶s complement of B ± A and the output carry is equal to 0.

Result: Thus a 4-bit binary Adder / Subtractor and a 4 bit BCD adder were designed and implemented using IC 7483.

Pin Diagram: IC 7483 4-BIT BINARY ADDER .

4- Bit Binary Adder

**4 bit BCD adder `
**

B3 B2 B1 B0 A3 A2 A1 A0

Cout

16 14

4

7

11

1

3

8

10

5 13 12

Vcc Cin Gnd

4 bit Binary Adder

15

2

6

9

Output carry

0

5 16 Cout 14 4 7 11 1 3 8 10 13 Vcc Cin

4 bit Binary Adder 15 2 6 9

S3

S2

S1

S0

8. COMPARATOR Aim: To construct two 2 bit numbers using logic gates and compare two 8 bit numbers using IC 7485

Equipments Required: Digital Trainer kit-1 IC 7486-XOR IC IC 7404-NOT IC IC 7408-AND IC IC 7485

THEORY: The comparison of two numbers is an operation that determines if one number is greater than, less than or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A>B, A=B, A<B.

For comparing two four bit numbers A=A3A2A1A0 B=B3B2B1B0

The circuits should be implemented by the following Boolean function A>B: A1B1¶+A0B0¶(A1B1+A1¶B1¶) A<B: B1A1¶+B0A0¶(B1A1+B1¶A1¶) A=B: (A1 XNOR B1) . (A0 XNOR B0)

3. The connections are given as per the circuit diagram. Verify the output. Now give two 8 bit numbers as input to the two comparator ICs and verify the output. Result: Thus two 2 bit numbers were compared using logic gates and two 8 bit numbers were compared using IC 7485 . Procedure: 1. unsigned binary. There are three outputs to display if one number is equal. The magnitude comparator compares two numbers. A magnitude comparator compares the magnitude. i. The comparator has to be used to test all the three cases. The two inputs can be 4 bits long. of two numbers.Description of IC 7485: The four bit magnitude comparators perform comparison of straight binary and straight BCD codes. greater or smaller compared to the other. .e. The outputs are verified using LEDS. . Vcc has to be used to generate a logic one and ground to generate a logic zero. 2.

CIRCUIT DIAGRAM: .

A>B A<B A=B TRUTH TABLE: .

A1 A0 B1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 .

PIN DIAGRAM OF IC 7485: Vcc A3 B2 A2 A1 B1 A0 B0 16 15 14 13 12 11 10 9 IC7485 1 2 3 4 5 6 7 8 B3 A<Bin A=Bin A>Bin A>Bout A=Bout A<Bout Gnd FUNCTION TABLE OF IC7485: Comparing Cascading Inputs inputs A>B A=B I(A>B) X 1 X 0 0 1 A<B X I(A=B) X 0 1 0 0 0 X I)\(A<B) X 0 X 1 0 1 X Outputs A>B 1 1 0 0 1 0 0 A=B 0 0 1 0 0 0 0 A<B 0 0 0 1 1 0 1 8 BIT COMPARATOR USING 7485 .

MSB Input A A7 A6 A5 A4 MSB Input B B7 B6 B5 B4 A3 LSB Input A A2 A1 A0 LSB InputB B3 B2 B1 B0 5V 15 13 9 9 5 A>B 6 A=B IC 7485(2) 12 10 1 14 11 9 15 13 12 10 1 14 11 9 I(A>B) I(A=B) I(A<B) 2 3 4 5 A>B 6 A=B 7 A<B IC 7485(1) 16 8 I(A>B) I(A=B) I(A<B) 2 3 4 7 A<B 16 8 Vcc Gnd Vcc Gnd .

and Output=1 means odd parity) Parity Generator: 1. The circuit that checks the parity in the receiver is called a Parity Checker. A parity bit is used for the purpose of detecting errors during transmission of binary information. (Add one more EX-OR gate to generate odd parity bit) . The circuit that generates the parity bit in the transmitter is called a Parity Generator. Connect the circuit to three switches and one LED and note down the output as even parity. Draw the circuit diagram using EX-OR gates. construct and test a circuit that checks and generates an even parity bit and odd parity bit from four message bits using EX-OR gates and IC 74180 Equipment Required: Digital Trainer Kit. A parity bit is an extra bit included with a binary message to make the number of 1¶s either odd or even. including the parity bit.( Output=0 means Even parity. Draw the circuit diagram using EX-OR gates 2. Connect the circuit to four switches and one LED and check for proper operation. The message. is transmitted and then checked at the receiving end for errors.9. An error is detected if the checked parity does not correspond with the one transmitted. 2. 4 BIT ODD / EVEN PARITY GENERATOR / CHECKER USING LOGIC GATES AND MSI DEVICES Aim: To design. IC 7486 EXOR Theory: EX-OR functions are very useful in systems requiring error detection and correction codes. Procedure: Parity checker: 1.

Result: Thus a circuit that checks and generates an even parity bit and odd parity bit from four message bits using EX-OR gates was designed. . constructed and tested using logic gates.

Truth Table: (Even parity Generator) Message bits X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Parity Bit P 0 1 1 0 1 0 0 1 Design: yz 00 X 0 01 11 10 1 1 1 1 1 P=X Y Z Circuit Diagram: Parity Generator: (Even Parity) .

P=XYZ Truth Table: (Parity Checker) Parity error check C 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 4 bits Message Received X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Design: ZP 00 XY 01 11 10 1 00 1 1 1 01 1 11 1 1 1 10 C=X Y Z P .

PARITY CHECKER: C=XYZP Truth Table: (Odd parity Generator) Message bits X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Parity Bit P 1 0 0 1 0 1 1 0 Design: yz 00 X 0 01 11 10 1 1 1 1 1 .

P=X Y Z Circuit Diagram: Parity Generator: (Odd Parity) P=XYZ Truth Table: (Parity Checker) Parity error check C 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 4 bits Message Received X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 .

Design: ZP 00 XY 00 01 11 10 1 1 1 1 1 1 1 01 11 1 10 C=X Y Z P Circuit diagram for odd parity checker: .

Selection lines S1 and S0 are decoded to select a particular AND gate. The OR gate have at least one output is now equal to the value of I2. The function table lists the input to output path for each possible bit combination of selection lines. To demonstrate the circuit operation consider the case when S1S0=10. Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected. Digital trainer kit 2. In a 4 to 1 line multiplexer. The AND gate associated with input I2 has two of its inputs equal to 1 and third input connected to I2. each of four input lines I0 to I3 is applied to one input of an AND gate. which makes their output equal to 0.10. IC 7404 ± NOT IC 3. MULTIPLEXER AND DE-MULTIPLEXER Aim: To construct the multiplexer and demultiplexer using logic gates and to study IC 74150 and IC 74154 Equipments required: 1. IC 7432 ± OR IC Theory: Multiplexer and Demultiplexer: Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. A multiplexer is also called as data selector. IC 7408 ± AND IC 4. The other three AND gates have at least one input equal to 0. . thus providing path from the selected input to the output.

. Result: Thus multiplexer and demultiplexer was constructed using logic gates and IC 74150 and IC 74154 were studied. The function table is verified for multiplexer and demultiplexer.Demultiplexer is a circuit that receives information on a single line and transmits this information on one of a possible 2n output lines. Give the inputs to IC 74150 and IC 74147 as shown in the pin diagram and verify the outputs. 3. The connections are given as per the circuit diagram. Procedure: 1. The selection of a specific output line is controlled by the bit values of n selection lines. 2.

Circuit Diagram: .

IC 74150 as MULTIPLEXER INPUTS A3 A2 X X 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUTS En Q¶ 1 1 1 D0¶ 0 D1¶ 0 D2¶ 0 D3¶ 0 D4¶ 0 D5¶ 0 D6¶ 0 D7¶ 0 D8¶ 0 D9¶ 0 D10¶ 0 D11¶ 0 D12¶ 0 D13¶ 0 D14¶ 0 D15¶ .

IC 74154 as Demultiplexer A3 X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 INPUTS A1 A0 X X X 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 OUTPUTS En1¶ En2¶ Q=0 -----1 X X 1 -----0 0 Q0 0 0 Q1 0 0 Q2 0 0 Q3 0 0 Q4 0 0 Q5 0 0 Q6 0 0 Q7 0 0 Q8 0 0 Q9 0 0 Q10 0 0 Q11 0 0 Q12 0 0 Q13 0 0 Q14 0 0 Q15 .

as only one of 10 output lines is high or low at a time. This can be done using priority encoder. Equipments required: Digital Trainer kit IC 7404-NOT IC IC 7420/7421-4 input NAND IC IC 7432-OR IC Theory: ENCODER: An encoder provides binary coded outputs from an input selected from given number of inputs. then the input having highest priority will take precedence. DECODER:A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 unique output lines. Using this device the decimal digits can be converted into equivalent BCD codes. The encoder provides BCD output. DECIMAL TO BCD ENCODER & BCD TO DECIMAL DECODER Aim: To design and implement a Decimal to BCD Encoder and BCD to Decimal Decoder using logic gates and to study IC 7445 and IC 74147 as Decoder and encoder respectively. It has 2 power n in put lines and n output lines. BCD to decimal decoder is also called as 1 of 10 decoders. n . which will correspond to the highest order digit. If two or more inputs are equal to one simultaneously. This type of encoders are typically used for translating a decimal keyboard (calculator) into a binary or BCD codes.11. Decimal to BCD encoder is also known as keyboard encoder.

Result: Thus Decimal to BCD Encoder and BCD to Decimal Decoder was constructed using logic gates and the IC¶s 7445 and 74147 were studied. Truth table is verified for all the input combinations of both Encoder and Decoder. Verify the truth tables for IC 7445 and 74147. . 3.Procedure: 1. Connections are given as shown in the diagram 2.

Pin diagram of IC 7420: Truth table of IC7420: INPUT A 0 0 1 1 1 1 B C 0 1 0 1 1 1 0 1 1 0 1 1 D 0 1 1 1 0 1 OUTPUT Q 1 1 1 1 1 0 .

Circuit Diagram: .

.

.

IC 7445 as BCD to DECIMAL Decoder: IC 74147 as Decimal to BCD encoder .

This is because the most significant flip-flop (the farthest flip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock pulse). so that a single pulse can clear all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled through the other counters after propagation delays. Thus. a counter with n flip-flops can have 2 states. the flip-flops cannot be triggered simultaneously. ASYNCHRONOUS COUNTER Aim: To design and implement an Asynchronous counter & to verify its truth table. each one corresponding to a count value. the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. the above counter is an example of a divide-by-8 counter. n . producing an asynchronous operation. like a ripple on water. Usually. The 3-bit ripple counter circuit above has four different states. The number of states in a counter is known as its mod (modulo) number. Similarly. A mod-n counter may also described as a divide-by-n counter. but FF1 changes only when triggered by the falling edge of the Q output of FF0. FF0 changes state at the falling edge of each clock pulse. Equipments Required: Digital Trainer kit 74LS76 Theory: The external clock is connected to the clock input of the first flip-flop (FF0) only.12. So. Therefore. Thus a 2-bit counter is a mod-8 counter. all the CLEAR inputs are connected together. hence the name Ripple Counter. Because of the inherent propagation delay through a flip-flop.

Result: Thus an asynchronous counter was designed and implemented & its truth table was verified. Verify the Truth Table.Procedure: 1. Give the connections as per the circuit diagram 2. .

Pin Diagram: Truth table for 4 bit ripple counter: FF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Truth Table for MOD-10 counter: FF3 0 0 0 0 0 0 0 0 1 1 FF2 0 0 0 0 1 1 1 1 0 0 FF1 0 0 1 1 0 0 1 1 0 0 FF0 0 1 0 1 0 1 0 1 0 1 FF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 .

Truth Table for MOD-12 counter: FF3 0 0 0 0 0 0 0 0 1 1 1 1 FF2 0 0 0 0 1 1 1 1 0 0 0 0 FF1 0 0 1 1 0 0 1 1 0 0 1 1 FF0 0 1 0 1 0 1 0 1 0 1 0 1 Circuit Diagram: 4 bit ripple counter .

MOD-10 counter .

MOD-12 Counter .

the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter. In synchronous counters. The circuit below is a 3-bit synchronous counter. and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.13. Thus.1. The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. SYNCHRONOUS UP/DOWN COUNTER Aim: To design and implement a synchronous counter for the given state diagram using JK Flip Flop. Thus. A counter that follows the binary sequence is called a binary counter. n . all the flip-flops change state simultaneously (in parallel). FF1 has its J and K inputs connected to the output of FF0. The J and K inputs of FF0 are connected to HIGH. Equipments Required: Digital trainer kit IC 7476 Theory: A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2 .

Result: Thus a synchronous counter was designed and implemented for the given state diagram using JK Flip Flop. Verify the truth table. . Give the connections as per the circuit diagram 2.Procedure: 1.

Pin diagram : FLIP FLOP EXCITATION TABLE Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 X X K X X 1 0 Excitation table for up counter : Present State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next State Q2 Q1 Q0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 J2 0 0 0 1 X X X X K2 X X X X 0 0 0 1 Flip flop inputs J1 K1 J0 0 X 1 1 X X X 0 1 X 1 X 0 X 1 1 X X X 0 1 X 1 X K0 X 1 X 1 X 1 X 1 .

K maps for up counter: Q1¶Q0¶ Q1¶Q0 Q1Q0 Q1Q0¶ Q1¶Q0¶ Q1¶Q0 Q1Q0 Q1Q0¶ Q2¶ Q2 0 X 0 X 1 X 0 X J2=Q1Q0 Q1¶Q0¶ Q1¶Q0 X 0 X 0 Q1Q0 X 1 Q1Q0 X X Q1Q0 1 1 Q1Q0¶ X 0 Q1Q0¶ X X J1=Q0 Q1Q0¶ 0 0 K1=Q0 K2=Q1Q0 Q1¶Q0¶ Q1¶Q0 0 0 1 1 Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X X X Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 1 X X Q1Q0 X X Q1Q0¶ 1 1 J0=1 Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X 1 1 Q1Q0 1 1 Q1Q0¶ X X K0=1 .

Excitation table for down counter : Present State Q1 Q0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Next State Q1 Q0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 Flip flop inputs J1 K1 1 X 0 X X 1 X 0 1 X 0 X X 1 X 0 Q2 0 0 0 0 1 1 1 1 Q2 1 0 0 0 0 1 1 1 J2 1 0 0 0 X X X X K2 X X X X 1 0 0 0 J0 1 X 1 X 1 X 1 X K0 X 1 X 1 X 1 X 1 K MAPS for Down counter: Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 X 0 X Q1Q0 0 X Q1Q0 X 0 Q1Q0¶ 0 X Q1Q0¶ X 0 J2=Q1¶Q0¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X 1 X 0 K2=Q1¶Q0¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 1 0 0 Q1Q0 X X Q1Q0¶ X X Q1Q0¶ 1 1 Q1Q0¶ 1 1 J1=Q0¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X X X Q1Q0 0 0 K1=Q0¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 1 X X Q1Q0 X X J0=1 .

Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X 1 1 Q1Q0 1 1 Q1Q0¶ X X K0=1 Circuit Diagram: 3 bit up down counter .

each bit appears on its respective output line. Serial In . All the flip-flops are driven by a common clock. The difference is the way in which the data bits are taken out of the register.Serial Out Shift Registers The register is first cleared.Parallel Out Shift Registers For this kind of register. Most of the registers possess no characteristic internal sequence of states. mainly for storage of digital data. During each clock pulse. Parallel In Parallel Out 4. data bits are entered serially in the same manner as discussed in the last section. and all bits are available simultaneously . Parallel In Serial Out. Equipments Required: Digital Trainer kit IC 7474 Theory: Shift registers are a type of sequential logic circuit. SHIFT REGISTER Aim: To construct and verify the truth table of following shift register for 4 bit using D Flip Flop 1. one bit is transmitted from left to right. Serial In Serial Out 2. and all are set or reset simultaneously. forcing all four outputs to zero. Serial In Parallel Out 3. Once the data are stored.14. They are a group of flip-flops connected in a chain so that the output from one flipflop becomes the input of the next flip-flop. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). Serial In .

Result: Thus a shift register was constructed using D Flip Flop and its truth table was verified. Verify the truth table.Serial Out Shift Registers The circuit uses D flip-flops and NAND gates for entering data (ie writing) to the register. The D's are the parallel inputs and the Q's are the parallel outputs.Parallel Out Shift Registers For parallel in . To write data in. all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. . the mode control line is taken to LOW and the data is clocked in. D1. Procedure: 1. all the data at the D inputs appear at the corresponding Q outputs simultaneously.parallel out shift registers. D0. The connections are given as per the circuit diagram 2. The data can be shifted when the mode control line is HIGH as SHIFT is active high. where D0 is the most significant bit and D3 is the least significant bit. D2 and D3 are the parallel inputs. Parallel In . Once the register is clocked.Parallel In .

Pin diagram: Dual D Flip Flop Circuit Diagram: Serial in .Parallel Out Shift Registers: .Serial Out Shift Registers: Serial In .

Parallel In .Shift Left Serial In Parallel Out .Parallel Out Shift Registers Truth Table: Serial In Serial Out Input Sd3 CLK D1 D2 1 1 1 1 1 0 1 1 1 S.Serial Out Shift Registers: Parallel in Parallel out Shift registers: .No Rd1 1 0 1 1 1 2 3 1 1 1 1 4 1 Control Inputs Rd2 Rd3 Sd1 Sd2 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 D3 Output Q3 0 0 0 a1 a2 0 b3 b2 b1 Conditions clear × a1 a2 a3 a4 b1 b2 b3 c1 c2 c3 After clear Input Shift Left After clear Input Load After Load .

No Control Inputs Write / Shift 0 1 1 Input Output Conditions Rd1 1 2 0 1 1 3 1 Rd2 0 1 1 1 Rd3 0 1 1 1 Sd1 1 1 0 1 Sd2 1 1 0 1 Sd3 1 1 0 1 CLK D1 D2 D3 × a3 a2 a1 Q3 0 × a3 a2 clear Write after Write shift × a1 a1 a1 × a2 a1 a1 .Load after Load Sd3 1 1 0 1 CLK D3 × a3 b3 × a1 b1 × a2 b2 0 a1 0 b1 0 a2 0 b2 0 a3 0 b3 Parallel In Serial Out S.No Rd1 1 0 1 1 1 2 1 Control Inputs Rd2 Rd3 Sd1 Sd2 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sd3 1 1 1 1 1 CLK Input D1 D2 D3 × Output Q1 Q2 Q3 Conditions clear × a1 a2 a3 a4 × 0 a1 a2 a3 a4 0 0 a1 a2 a3 0 0 0 a1 a2 After clear Input Parallel In Parallel Out S.S.No Rd1 1 2 3 4 0 1 1 1 Control Inputs Rd2 Rd3 Sd1 Sd2 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 Input D1 D2 Output Q1 Q2 Q3 Conditions clear after clear input after clear input .

Such a counter is called the non sequential counting.0. Result: Thus a synchronous counter with non sequential counting was designed and implemented for the given state diagram using JK Flip Flop. .5.7 Equipments required: Digital trainer kit IC 7476 Theory: A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. Verify the truth table. The counters either count up or down continuously.4. But designing a counter which skips states in the middle is also possible. NON-SEQUENTIAL COUNTERS Aim: To design asynchronous counter using JK flip flop to count the following sequence 7.15. Procedure: 1.1. Give the connections as per the circuit diagram 2. Even in lessened modulus counters count is sequential but reset is enabled in the middle of the sequence.3.

Pin diagram : FLIP FLOP EXCITATION TABLE Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 X X K X X 1 0 Excitation table of the non sequential counter: Present State Q2 Q1 Q0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 Next State Q2 Q1 Q0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 1 1 J2 X X 0 1 X 1 K2 0 1 X X 1 X Flip flop inputs J1 K1 X 1 1 X X 1 0 X 0 X 1 X J0 X 1 X X X 1 K0 1 X 0 0 1 X .

K maps for non-sequential counter: Q1¶Q0¶ Q1¶Q0 Q1Q0 Q1Q0¶ Q1¶Q0¶ Q1¶Q0 Q1Q0 Q1Q0¶ Q2¶ Q2 1 X 1 X 0 X X X J2=Q1¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X 1 X 1 Q1Q0 X 0 Q1Q0 X X Q1Q0 1 1 Q1Q0¶ X X Q1Q0¶ X X J1=Q2¶ Q1Q0¶ X X K1=1 K2=Q1¶ Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 1 0 0 Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X X X Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 1 1 X X Q1Q0 X X Q1Q0 Q1Q0¶ X X Q1Q0¶ X X K0=Q2 J0=1 Q1¶Q0¶ Q1¶Q0 Q2¶ Q2 X X 0 1 0 1 .

Circuit Diagram: .

one output line.Multiplexer IC Theory: A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. Io through I3. The selection of particular input line and n selection lines whose bit combinations determine which input is selected.16. The OR gate output is now equal to the value of I2. If there are n variables. A 4-to-1 line multiplexer circuit has four data input lines. The function table lists the input that is passed to the output for each combination of binary selection values. The other three AND gates have at least one input equal to 0. The AND gate associated with input I2 has two of its inputs equal 1 and the third input connected to I2. which makes their outputs equal to 0. providing a path from selected input to the output. is applied to one input of AND gate. DESIGN AND IMPLEMENTATION OF BOOLEAN FUNCTION USING MULTIPLEXER Aim: To design and implement the given Boolean function using multiplexer 1. Procedure: 1. . and 2 selection lines S. connect n-1 variables to the selection line of multiplexer. To demonstrate the circuit operation consider the case when S1So =10. The output of AND gates are applied to a single OR gate that provides the one line output. F=C¶B¶A+C¶BA+CB¶A+CBA¶ 2.F=D¶C¶B¶A+D¶C¶BA¶+D¶CB¶A+D¶CBA¶+D¶CBA+DC¶B¶A¶+DC¶ BA¶+DCB¶A¶+ DCB¶A+DCBA Equipments Required: Digital Trainer kit IC 74151. Each of the four inputs. For this reason it is also called a data selector.

n-1 selection lines and one output. Fill up the min terms as shown in the table and choose. The input is 1. 3. 4. b) If both of the min-terms in the column are chosen. the variable in the row is the input. The input is 0.2. a) If none of the min-terms in the column are chosen. the min terms with 1 as output and encircle them 6. Result: Thus the given Boolean function was designed and implemented using multiplexer . Write the truth table for the function with n variables. c) If any one is chosen. Construct the block diagram of multiplexer with 2n-1 inputs. 5. Construct an implementation table with possible combinations of the remaining single variable as rows and the 2n-1 inputs as columns.

Pin diagram: F=C¶B¶A+C¶BA+CB¶A+CBA¶ Truth table: Input C 0 0 0 0 1 1 1 1 Circuit Diagram: B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Output Y 0 1 0 1 0 1 1 0 .

F=D¶C¶B¶A+D¶C¶BA¶+D¶CB¶A+D¶CBA¶+D¶CBA+DC¶B¶A¶+DC¶BA¶+DCB¶A¶+ DCB¶A+DCBA Truth table: Input D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Implementation Table: C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Y 0 1 1 0 0 1 1 1 1 0 1 0 1 1 0 1 .

1 .Circuit diagram: CONTENTS S.No. Name of the Experiments Verification of digital Logic gates Page No.

1.0.binary to gray and vice versa Design and implementation of 4 bit binary adder/subtractor and BCD adder using IC 7483 Design and implementation of 2 bit magnitude comparator using logic gates 8 bit magnitude comparator using IC 7485 Design and implementation of 16 bit odd/even parity checker generator using IC 74180 Design and implementation of multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154 Design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147 Construction and verification of 4 bit ripple counter and MOD -10/MOD-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter Implementation of SISO.BCD to excess-3 code and vice versa 2.2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Verification of Boolean Theorems using Digital Logic Gates Design and Implementation of Combinational Circuits using basic gates for arbitrary functions Study of flip flops Design and implementation of adders and subtractors using logic gates Design and implementation of code converters using logic gates 1. SIPO.7 To design and implement the given Boolean function using multiplexer .5. PISO and PIPO shift registers using flip-flops Design and implementation of a synchronous counter using JK flip flop to count the following sequence 7.4.3.

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