Intel x86 Processors
Presented by Kiyeon Lee
• • • • • • History Register Set Data Addressing Mode Real Mode & Protected Mode Memory Address Integer & Floating Point Operations Architecture (P5, P6, NetBurst)
Intel 4004 (1971)
♠ 4 bit microprocessor. 50 KIPS(Kilo-instructions per second) ♠ Main problems: speed. word width. memory size
♠ Successor to the Intel 4004. 4KB of memory ♠ 45 instructions. higher speed
♠ Extended 8-bit version of the 4004 microprocessor ♠ 16KB of memory
and higher clock frequency
♠ The first of the modern 8-bit microprocessors
8008 Not directly compatible with TTL 16KB of memory
8080 Compatible with TTL 64KB of memory
♠ Update version of the 8080 ♠ 246 instructions ♠ Internal clock generator. internal system controller.
2.000 variations of instructions ( 45 (4004) → 245 (8085) → +20.or 6-byte instruction cache or queue ♠ Over 20.History
8086 (1978) / 8088 (1979)
♠ 16-bit microprocessor.000 (8086) ) ♠ The popularity of the Intel family ensured in 1981 by IBM
♠ 16-bit microprocessor ♠ 16MB memory system ♠ The first Intel processor that could run all the software written for its predecessor
.5 MIPS ♠ 1MB of memory ♠ A small 4.
♠ 275.000 transistors ♠ Intel’s first practical 32-bit microprocessor ♠ 32-bit data bus and memory address ♠ 4GB of memory ♠ Memory management unit ♠ Multitasking
♠ 80386-like Microprocessor + 80387-like Numeric Coporcessor + 8KB Cache Memory System ♠ Speed improved
floating-point unit ♠ Basic clock frequency: 150 MHz and 166MHz ♠ 16K L1 Cache(8K for data and 8K for instructions) + 256K L2 Cache ♠ Execute up to three instructions at a time (It doesn’t matter even if the conflict!)
. 110MIPS / 100MHz. 150MIPS ♠ 16KB of cache size (8KB IC. 8KB DC) ♠ 4GB of memory system. 64-bit data bus ♠ Executes up to two instructions at a time (If they don’t conflict!)
Pentium Pro Processor (1995)
♠ P6 architecture ♠ 5.5M Transistors.History
Pentium Processor (1993)
♠ P5 architecture / 80586 ♠ Introductory version: 60MHz and 66MHz. 3 integer units.
450 and 500 MHz ♠ SSE(Streaming SIMD Extensions) instructions.5M Transistors. Improved L1 cache controller ♠ Low-end Celeron / High-end Xeon
Pentium II Processor (1997)
♠ P6 architecture ♠ 7.5 Million transistors. Initially ran at 233MHz and 266MHz ♠ 32KB L1 Cache + 512KB L2 Cache (External → 50% of processor speed) ♠ Arranging the amount of L2 Cache → Celeron(1999) or Xeon(1998)
Pentium III Processor (1999)
♠ P6 architecture ♠ 9.
♠ 64-bit microprocessor( by HP & Intel )
. Lower heat output than desktop
Itanium Processor. 1.History
Pentium 4 Processor (2000)
♠ NetBurst architecture ♠ Deep instruction pipeline. 2003
♠ M for Mobile: Laptop ♠ Execution core of the Pentium III + Pentium 4 compatible bus interface + improved instruction decoding/issuing front end + improved branch prediction + SSE2 support + a much larger cache ♠ Low average power consumption. SSE2. 64-Bit floating point computation ♠ 42 Million transistors.5 GHz ♠ Hyper Threading
Pentium M Processor.4 GHz and 1.
22H ♠ Direct addressing: MOV CX. [BX+4] ♠ Base relative-plus-index addressing: MOV AX. CL ♠ Register relative addressing: MOV AX.Data Addressing Modes
8086 through 80286
♠ Register addressing: MOV CX. [EAX+4*EBX]
. [BX] ♠ Base-plus-index addressing: MOV [BX+DI]. [ECX+4] ♠ Base relative-plus-index addressing: MOV EAX. EDX ♠ Immediate addressing: MOV EBX. CL ♠ Register relative addressing: MOV AX. ARRAY[BX+DI]
80386 and above
♠ Register addressing: MOV ECX. [ECX] ♠ Base-plus-index addressing: MOV [EAX+EBX]. 12345678H ♠ Direct addressing: MOV CX. LIST ♠ Register indirect addressing: MOV AX. DX ♠ Immediate addressing: MOV AL. LIST ♠ Register indirect addressing: MOV AL. ARRAY[EBX+ECX] ♠ Scaled-index addressing: MOV EDX.
8088 can only operate in the real mode Real mode operation
Allows the microprocessor to address only the first 1MB of memory
Real memory: The first 1MB of memory Segment address + Offset address Segmant address
The beginning address of any 64KB memory segment
Selects any location within the 64KB memory segment
.Real Mode Memory Addressing
Physical address? 10000H(Appended with a 0H on its rightmost end) + 2000H = 12000H
.Real Mode Memory Addressing
Ex) Segment register: 1000H. Offset address: 2000H.
.Protected Mode Addressing
80286 and above operate in either the real or protected mode Allows the access to data and programs located above the first 1MB of memory Selector → Descriptor Descriptor decides the memory segment’s location. length. and access rights.
Protected Mode Addressing
Log. Square Root. and Pop Arithmetic and logic: Logical Operations. Push.Integer & Floating Point Operations
Data movement: Move. and Absolute Value Comparison: Instructions to send the result to the integer CPU so that it can branch Transcendental: Sine. and Integer & Decimal Arithmetic Operations Control flow: Conditional Branches & Unconditional Jump. and Store Arithmetic: Add. and Exponentation
. Shifts. Cosine. Subtract. Test. Load Constant. String Compare
Floating Point Operations
Data movement: Load. Divide. Multiply. Calls and Returns String: String Move.
Write Back(WB) Secondary Pipe(V) ♠ Issued up to two instructions every cycle
The P6 microarchitecture(Pentium Pro ~ III)
♠ Out-of-order Execution. 10-stage pipeline ♠ Scheduler. Faster. Decode Stage 2(D2). Improved Branch Prediction Algorithms
. More Robust.Pipelining
The P5 microarchitecture
♠ ILP. Execute(E). ♠ Faster ALU. Reorder Buffer ♠ Improved branch prediction algorithms
The NetBurst microarchitecture(Pentium 4. FPU.5-Stage Pipeline ♠ Two General–Purpose Integer Pipelines & A Pipelined Floating-Point Unit ♠ Main Pipe(U): Pre-Fetch(PF). 20-Stage Pipeline. Decode Stage 1(D1).
• • • • • • • • Superscalar Execution Pipeline Architecture Branch Target Buffer (BTB) Dual 8KB On-Chip Cache Write-Back Cache 64-Bit Bus Instruction Optimization Floating-Point Optimization
P6 Architecture (Pentium Pro)
Three-way Superscalar. pipelined architecture
P6 Architecture (Pentium Pro)
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