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Global Distribution of Clocks and Power (1

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When ASICs are built on a deep submicron process with over tens of million gates and a clock frequency below 1GHz, the designer must consider many details in the clock and power circuitry. Normally these circuit elements are not given much thought; power is drawn from the rails drawn across the top and bottom of the page, and the clock has ideal characteristics: a square wave running at the specified frequency. In reality, many other effects need to be evaluated in the clocking and power distribution areas of the design when the total chip power consumption will be in the range of tens to over 100 W and the clock power can be as much as half of the total power consumption. The clocking scheme cannot be assumed to be a clean, uniform signal network. It might be a complicated distribution structure with architectures ranging from a large distributed clock buffer for the high-performance chips to a complex system with multiple derived sub-clocks to help manage power consumption. 

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and silicon area. ground bounce.  2 . The power and ground system will take up about half of the available package pins to be able to handle the tens of amperes of average current consumed by the IC. power. and glitches. The various secondary effects within the system. may exacerbate the problems by adding enough noise to the system to decrease the clock slew rates and the clock rise and fall times. Many side effects of the basic IC process will have to be addressed to make the chip meet all the requirements of speed. like voltage drops on the supply lines. crosstalk. noise margins and leakage currents may become significant problems.Global Distribution of Clocks and Power (2)  The interaction between clocks and power consumption may require the ability to generate clock signals which can be stopped in the inactive sections to minimize power consumption. If the supply voltage is reduced to take advantage of the power savings available at a lower supply voltage.