The 8255A Programmable Peripheral Interface.

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is widely used, r r le, r llel I/O devi e. € It e r r ed t tr sfer d t u der vari us diti s, fr si le I/O t i terru t I/O. € It is flexi le, versatile, and economical (when multi le I/O orts are required), ut somewhat complex. € It is an important eneral-purpose I/O device that can e used with almost any microprocessor.
€ The

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has 4 I/O pins that can e rouped primarily in two - it parallel ports: and B, with the remaining eight its as port C. € The eight its of port C can e used as individual its or e grouped in two 4 it ports: CU ER (CU) and CLOWER (CL). € The functions of these ports are defined y writing a control word in the control register.
€ The

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2011 5 .€ € € € € € The BSR mode is used to set or reset the its in port C. In the handshake mode. two types of I/O data transfer can be implemented: (1)status check ( ) interrupt. and Mode . 8255 Programable Interface Tuesday. all ports function as simple I/O ports. port can be set up for bidirectional data transfer using handshake signals from port C. and port B can be set up either in Mode 0 or Mode 1. The I/O mode is further divided into three modes: Mode 0. Mode 1. In Mode . In Mode 0. August 09. Mode 1 is a handshake mode whereby ports and/or B use bits from port C as handshake signals.

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€ The 8255 Programable Interface Tuesday.block diagram shows two -bit ports ( and B). 2011 9 . € Two 4-bit ports (CU and CL) € The data bus buffer. August 09. including a control register. € This block diagram includes all the elements of a programmable device. port C performs functions similar to that of the status register in addition to providing handshake signals. and control logic. € Simplified but expanded version of the internal structure.

August 09.control section has six lines. € WR (Write): This control signal enables the Write operation. the M U writes into a selected I/O port or the control register. 2011 10 . the M U reads data from a selected I/O port of the . Their functions and connections are as follows: € RD (Read): This control signal enables the Read operation. When the signal is low. € The 8255 Programable Interface Tuesday. When the signal goes low.

it clears the control register and sets all ports in the input mode. 0. 8255 Programable Interface Tuesday. respectively. CS is connected to a decoded address. 2011 11 . and 0 and 1 are generally connected to M U address lines 0 and 1. August 09. € CS.€ RESET (Reset): This is an active high signal. 1: These are device select signals.

August 09. 8255 Programable Interface Tuesday. 2011 12 . and 0 and 1 specify one of the I/O ports or the control register as given below: 1 0 Selected CS 0 0 0 port 0 0 1 ort B ort C 0 1 0 0 1 1 Control Register 1 x x 8255 is not selected.€ The CS signal is the master chip select.

0. and 1 lines. August 09.port addresses are determined by the CS. € The CS line goes low when 7 = 1 and 6 through 2 are at logic 0. the port addresses range from 80H to 83H. 2011 13 . € The 8255 Programable Interface Tuesday. € When these signals are combined with 0 and 1.

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€ The register is not accessible for a read operation. 2011 15 . specify an I/O function for each port. € The 8255 Programable Interface Tuesday. called the control word. August 09. € This register can be accessed to write a control word when 0 and 1 are at logic 1.contents of Control register. as mentioned previously.

€ The BSR control word does not affect the functions of ports and B. 8255 Programable Interface Tuesday. August 09.€ Bit D7 of the control register specifies either the I/O function or the Bit Set/Reset function. port C operates in the Bit Set/Reset (BSR) mode. € If bit D7 = 1 . Bits D6-D0 determine I/O functions in various modes. 2011 16 . € If bit D7 =0.

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€ 1. Write I/O instructions to communicate with peripherals through ports A. and C. B. 2011 18 . B. To communicate with peripherals through the 8255A. and C and of the control register according to the Chip Select logic and address lines A0 and A1. 3. 8255 Programable Interface Tuesday. 2. Write a control word in the control register. three steps are necessary: Determine the addresses of ports A. August 09.

August 09. Inputs are not latched.A and B are used as two simple 8-bit I/O ports € Port C as two .bit ports € The input/output features in Mode 0 are as follows: 1. Ports do not have handshake or interrupt capability. € Ports 8255 Programable Interface Tuesday. Outputs are latched. 2011 19 . 2. 3.4.

as input ports. Identify the port addresses in Figure shown.l. 2011 20 . 2. August 09. 8255 Programable Interface Tuesday. Write a program to read the DIP switches and display the reading from port B at port A and from port CL at port CU. Identify the Mode 0 control word to configure port A and port CU as output ports and port B and port CL. 3.

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Assuming all don't care lines are at logic 0. A0. when the address line A15 is high.l. A0= l) 8255 Programable Interface Tuesday. = 0) Port B = 8001H (A1 = 0. A0 = l) Port C = 8002H (A1 = l. 2011 22 . Port Addresses € This is a memory-mapped l/O. A0 = 0) Control Register = 8003H(A1 =l. the Chip Select line is enabled. August 09. the port addresses are as follows: Port A = 8000H {A1 = 0.

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€ € € € € € € € € € € € MVI A. Read switches at port B STA 8000H . Write word in the control register to initialize the ports LDA 8001H . August 09. Display the reading at port A LDA 8002H . Display data at port C1 HLT 8255 Programmable Interface Tuesday. of the accumulator RLC RLC RLC STA 8002H . 2011 24 . Rotate and place data in the upper half . these . Mask the upper four bits of port C. Load accumulator with the control word STA 8003H . bits are not input data RLC . Read switches at port C ANI 0FH .83H .

€ In the BSR mode. thus the I/O operations of ports A and B are not affected by a BSR control word. € A control word with bit D7 = 0 is recognized as a BSR control word. € The 8255 Programmable Interface Tuesday. 2011 25 . and it does not alter any previously transmitted control word with bit D7 = l. which can be set or reset by writing an appropriate control word in the control register. August 09.BSR mode is concerned only with the eight bits of port C. individual bits of port C can be used for applications such as an on/off switch.

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2011 27 .€ Write a BSR control word subroutine to set bits PC7 and PC3 and reset them after 10 ms. 8255 Programmable Interface Tuesday. Use the schematic in Figure 8255A Chip select logic and assume that a delay subroutine is available. August 09.

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2011 29 . August 09.€ Control register address = 83 H. 8255 Programable Interface Tuesday.

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8255 Programable Interface Tuesday. the following points can be noted: l. A BSR control word affects only one bit in port C. 2. 2011 31 .€ From an analysis of the above routine. To set/reset bits in port C. August 09. 3. a control word is written in the control register and not in port C. The BSR control word does not affect the I/O mode.

August 09. turn on a fan if the temperature is above a set point.system is expected to read the temperature in a room. display the temperature on a liquid crystal display (LCD) panel. € This illustration includes the interfacing of a temperature sensor using an A/D converter and I/O devices such as a tan and a heater. and turn on a heater if the temperature is below a set point. 2011 32 . € The 8255 Programable Interface Tuesday.

August 09. Interface a temperature sensor using an A/D converter and port A of the 8255. 3. Interface a fan and a heater using optocouplers and triacs to drive the I/O devices. turn on the heater. 2011 33 . and if the temperature is higher than 35ÝC.1. 2. Write instructions to read the temperature. turn on the fan. 8255 Programmable Interface Tuesday. If the temperature is less than 10ÝC.

following components are specified for interfacing: 1. 2. Optoisolator ² MOC 3011 and Triac 2N6071 € The 8255 Programmable Interface Tuesday. August 09. 2011 34 . 8 ² bit A/D converter ² National ADC 0801 and Temperature Sensor ² National LM135 3. 8255 ² port A in Mode 0 and Port C in BSR mode.

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Starting a conversion. 8255 Programable Interface Tuesday. reading data at the end of the conversion. Initialization of the ports and the stack 2. 2011 38 . and checking for set values 3.The program consists of three segments: 1. August 09. Turning on and off the fan and the heater accordingly.

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It checks high (35ÝC) and low temperature (10ÝC) limits and calls subroutines to turn on/off the fan or the heater accordingly. It reads the temperature.€ GETTEMP: This subroutine starts a conversion. checks the INTR input signal and continues to read Port A. August 09. the INTR goes low. 2011 40 . When the conversion is complete. which is already adjusted to be read in degrees C. 8255 Programable Interface Tuesday.

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The features of this mode include the following: 1.In Mode1. They can be configured either as input or output ports. 2. 4. 2011 44 . 3. August 09. The remaining two lines of port C can be used for simple I/O functions. handshake signals are exchanged between the MPU and peripherals prior to data transfer. Two ports (A and B) function as 8-bit I/O ports. Input and output data are latched. y 8255 Programable Interface Tuesday. Each port uses three lines from port C as handshake signals. Interrupt logic is supported.

PC1 and PC0. 2011 45 . and PC5. € Port B uses the lower three signals: PC2.following Figure shows the associated control signals used for handshaking when ports A and B are configured as input ports. € Port A uses the upper three signals: PC3 PC4. € The 8255 Programable Interface Tuesday. August 09.

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functions of these signals are as follows: € STB (Strobe Input): This signal (active low) is generated by a peripheral device to indicate that it has transmitted a byte of data. The 8255A, in response to STB, generates IBF and INTR. € IBF (Input Buffer Full) This signal is an acknowledgment by the 8255A to indicate that the input latch has received the data byte. This is reset when the MPU reads the data.
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€ INTR

(Interrupt Request): This is an output signal that may be used to interrupt the MPU. This signal is generated if STB, IBF and INTE (Internal flip-flop) are all at logic 1. This is reset by the falling edge of the RD signal.

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€ INTE

(Interrupt Enable): This is an internal flip-flop used to enable or disable the generation of the INTR signal. The two flipflops INTEA and INTEB are set/reset using the BSR mode. The INTEA is enabled or disabled through PC4, and INTEB is enabled or disabled through PC2.

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In this flowchart. The disadvantage of the status check I/O with handshake is that the MPU is tied up in the loop. This is a simplified flowchart.€ The 8255A can be programmed to function using either status check I/O or interrupt I/O. 8255 Programable Interface Tuesday. August 09. The technique is similar to that of Mode 0 combined with the BSR mode. Figure shows a flowchart for the status check I/O. the MPU continues to check data status through the IBF line until it goes high. however. 2011 52 . it does not show how to handle data transfer if two ports are being used.

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pin PC2 is used for the same purposes.€ The flowchart in Figure (b) shows the steps required for the interrupt I/O. Figure shows that the STB signal is connected to pin PC4 and the INTEA is also controlled by the pin PC4 (In port B. August 09. the INTEA is set or reset in the BSR mode and the BSR control word has no effect when ports A and B are set in Mode l. The confusing step in the interrupt I/O is to set INTE either for port A or port B. 8255 Programable Interface Tuesday. 2011 54 . assuming that vectored interrupts are available.) However.

€ In case the INTR line is used to implement the interrupt. 2011 55 . it may be necessary to read the status of INTRA and INTRB to identify the port requesting an interrupt service and to determine the priority through software. 8255 Programable Interface Tuesday. August 09. if necessary.

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August 09. 8255 Programable Interface Tuesday. This signal indicates to an output peripheral that new data are ready to be read.€ OBF {Output Buffer Full): This is an output signal that goes low when the MPU writes data into the output latch of the 8255A. It goes high again after the 8255A receives an ACK from the peripheral. 2011 57 .

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€ INTR (Interrupt Request): This is an output signal. and it is set by the rising edge of the ACK signal. 2011 59 . ACK. The INTR is set when OBF.(Acknowledge): This is an input signal from a peripheral that must output a low when the peripheral receives the data from the 8255A ports. and INTE are all one and reset by the falling edge of WR. This signal can be used to interrupt MPU to request the next data byte for output. August 09. € ACK 8255 Programable Interface Tuesday.

respectively. € PC4.5: These two lines can be set up either as input or output. August 09.€ INTE (Interrupt Enable): This is an internal flip-flop to a port and needs to be set to generate the INTR signal. 2011 60 . 8255 Programable Interface Tuesday. The two flip-flops INTEA and INTEB are controlled by bits PC6 and PC2. through the BSR mode.

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and port B is designed as the output port for a printer with status check I/O. August 09.€ Figure above shows an interfacing circuit using the 8255A in Mode l. Port A is designed as the input port for a keyboard with interrupt I/O. 8255 Programable Interface Tuesday. 2011 63 .

5. 8255 Programable Interface Tuesday. 4. August 09. 3.1. 2011 64 . Write initialization instructions and a printer subroutine to output characters that are stored in memory. 2. Determine the BSR word to enable INTEA (port A). Find port addresses by analyzing the decode logic Determine the control word to set up port A as input and port B as output in Mode l. Determine the masking byte to verify the OBFB line in the status check I/O (port B).

the output of the NAND gate -goes low and selects the 8255A. When the address lines A7-A2 are all l. Port Addresses: The 8255A is connected as peripheral I/O. The individual ports are selected as follows: 8255 Programable Interface Tuesday. 2011 65 .l. August 09.

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€ Port A used five signals from port C as handshake signals for data transfer.Bidirectional Data Transfer: mode is used primarily in applications such as data transfer between two computers or floppy disk controller interface. port A can be configured as the bidirectional port and port B either in Mode 0 or Mode 1. € This . € In this mode. € The remaining three signals from port C can be used either as simple I/O or as handshake for port B.

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For example.Illustration: Interfacing keyboard and seven-segment display. pushbutton keyboard is connected to port A and a seven-segment LED is connected to port B of the 8255A. the digit 7 should be displayed at port B. € Port A should be configured as an input port and port B as an output port: this is a simple I/O configuration in Mode 0 without the use of handshake signals or the interrupt. €A . as shown in Figure. € Write a program to monitor the keyboard to sense a key pressed and display the number of the key at the seven-segment LED. when the key K7 is pressed.

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2. 4. Obtain the seven-segment code and display it. Identify and encode the key in appropriate binary format. Check if a key is pressed. Debounce the key. . 3.The programming of this problem can be divided into the following categories: 1.

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August 09.Key Debounce: 8255 Programable Interface Tuesday. 2011 81 .

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August 09. 2011 83 .Seven Segment Display: 8255 Programable Interface Tuesday.

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