A fUlly oomplen:lentary static OlIOS gate eceapies more area. than required, this~lts in sttw speed 01: sometintes the' function ,may not befeasib~e ,as a purely eomplementary sb'U.cture. Under these. ci:rctunstmces it is betlerto cost o.f ~
I:.....__ ) ag~
~.-.-..:II .J.~

implementsm.aHer

and :faster' ,gales at

~gn

.

oomp~X1I"I.
c

-

-

li-

-"rn

b) Increased operational ,complexity. c) Decreased operational nw:gin., • To overcome these compled:tiesvariou~ used.'J:'hese $trudw:'~ are ~ 1. CMOSccmplementarylogic alternate CMOS logic stnlct1m!s are'

2. BiiCMOS logic 3. ~SeudonMas logic
4. Dynamic' CMOS logic 5. Cloeked CMOS logic tC2MOS)

6. Pass-tEansis,tor logic
7. CMOS demino logic J:tNP dlommo ,logic (Zipper CMOS)
9. Cascade Vo],m.ge Swi,kh Logic (CVSI..)

10. Source' F'ollow.er Ptill"up l.ogic (SFPL). 4.. CIMOS Complem,en,talllY 1
.'

Logic

The CMOS ,co:mplementary drcuit are designed. as ratioless dr-cuits... it means tnatfhere.iis no fixed ,ratio between pull.. p and pull-down structure. The u e:xamplles of CMOS oomplementary' circuits aM: inverter, ·NAND and NOR ga.t-es. :Fi._g. 4,1, shows these, d.t:cuits as ,ready reference. (4 ,," 1)1
Copyrighted material

4~2

-----\100

AB -

CMOS lrnvarier

8 -----

CMOS NOR

[F[ig~4.1 CMOS C'(nnple•• ntary ga1tes .' The pHnclple of ,ratiolessckruits is used, in, v,arWus layout' design strategies such, as pte arrays and ;sea~f~ates. The cin:Wltwillfun,dion properly if h' uansistors ate 01 same size. Implementation fur Y =AJ(B -II- C) +DE) is shown ,in Fig., 4.1.

~~"

an

__

.~__

......

!'T'-. •••

-_

•••

-_

••

_ ...

Copyrighted material

input threshold. or speed iis to increase or decrease supply voltage ..The effect: of variation of supply VoliUJJge is : The oithermethod. fot varying

~ ffigh.er noise immunity. ~ Decrease in power dissipation of circuit .
•' The supply voltage is increased within saEety mar,gin Le, 1.5 Vtu 2.0 V fur breakdown voltage of5 Vto '] V. Afsome point leakage current (trom source dramjundion)wUIcause ito cease ope·rating. This capabili:ly is osefulin power down sJ\tuations where very .now quieooent power dissfpatiiou is expected.. En. such. ,conditions on--dlip' voi,ta.getlegu1amr is desuab1e .. Fol' example, if 5 volts is reqwed by board. level but 3vo.us isrequboo by the on--cldp ci:ra.tiby .. p.ig. 4.2 show,s a typical ()n~pvolta.ge :regula~r fOr reducing()n~p VDosu.pply.
I"""""'...... ~ .................................... ,....... .........~, ......... ~~ ....................... ~ ....................................... --...... -

!I

ExtmnalIVm>

II OLKc -__
~
I!
:1

I

_

-'_~~~~.r----

I!
II II II II

__ ~t~: f . _...... ~._ __................__ _+R.eference

P:a :

.....1

vo,lilag-e

:i4 ..
..~I
'i'.

i=.

~~--

lDiffe~nitiala'mplifier ~~
.................. -

......... ....... .....;.........

'Ret:erem::evolta.ge g_ ooeralt.or~ .....·1 -_ '!.,......... .

CUr(,erd. mif!'OF ~ ......... -~~~-

Fig.,. 4.2 • Tr,ansisto:rsP1
..·~4

and Nl - N 2 ferm a diHere.n.tial amp]Jjjfierwhile tr,ansistor.s

.Po~ flO' form a voltagerekrenoo. The differential. pair' u.sed eseuerent pair cDmpares therefer:ence voltage and mtemaJ. chip VDn voltage. Ther-esulting output control voltage is fed to transistorP5 bebveenintemal ~upply· and ext-eJ:\'fial supply. 'The eLK signal was generated ahead of chip required lar-ge amount of current sothat internal supply did not droop,
::) __"

..

Copyrighted

material

4 .. 8:iCM.OS 2
"

logic
c y ... -....::; ""'_. -~ . --. - .... ...--:_

driu.~ ''''~ip.·!!iI,billty-.··..r f CM.·· i-OS.. "a. o~"''"' 'Y'U' L ... CI~_auy .. ~~ ~.~ ""<'Ii... De O"I"e ~~li--"':":"'.i\..,~"":,-",.l ... lo.gic. Fig. 4.3 shows B~CMOSN1AND gaf~witb npnpuU40wn
"ryO- ... '"*lI~fn.,"~I~·t--11IJe 'V'~.lF""-

~.i'C:-·"·i""""~OS-.~.'.' ""'.1
vl,\..lY""i

I

- 1--

_.

.z
-

IB---

-

.'

pull-down T-ransistOrB.N 1 and.N.2. 6uD_pply the pull-down npntransis,tors witih'basecurrent when input is lUgh. Transistor N 3, clamps f:he pull-down 'when ·the output is lUgh-lPi 01'P;jlsupply the base CW'l',e:nttothe'puU~up npn transistor.
Fiig.. 4.3 alCMOS lNANIDO_withNIPN

'.

'The B,iCMOSlogjc: finds its applica.tion in. 'bus appUcationswher-e a high. dri;ve capability is applications includ.e memory-sense amplifiers"
~~no!"\e ,r~·,~""&&IIIIrI."II;""_

~n):m::. -r." -'.,1""-

AI ·2· M' ,,_.1: '1' gliL OS- , -, •........ ..._ InvanlllJr

a;·'c~

,.The

very approach. of BiCMOS is to exploU the advantageous ,chatacteristics of bipolar and. CMOStechnol.ogies. .HencemBiCM06, d.eslgrt. the rational approach is to tlSe,MOS swi1tches to perform the ~ogic :lUndion. and. bipolar transistors to drive the output loads, The basic logic' el!ement :hem tgO' is, the inverter and a shnpleBiCMOS inverter' citnJjit can. be &rta;gimed .lik.ethe one
~1.. ~.~ mWWill

i...... •. .Ig u

p-,•.-. 4.41._

Copyrighted material

-----1-

,'V -Cl~l

''1

1

~-

'Ct
GN[l

,--~-~~--~-~~~~~--.. The ,inverter cirouilt consists

....... -_--_.....:L-_

"SS

Pig .. 4,,.4 P. siimlP:le 'e:iCMOS iimvelrtier of ilwo D,i\polar transistors

T1 and, 'T2 one MlOS
,1

transi:s,tor T a and one pMOS trans,islo[ T4\' Both the MOO devices enhancemept mode devices. 'I'he' functioning of 'the' circuit is as ,follows :

are

a) With Vm at logic 0 Le, Ovalts (GND), Tats, off wmchkeeps T~ non~o:ndudlng'. How,eyler T4is on and supplies base cu:rrertt to Tlwbien conduets and acts as a

b),When '¥in = logic 1 Le, ~5 V (170D)1 T.tf is off so' tha,t Tz wm, benon-eenductlng, But T 3 is on and supplies 'current to base 0.£ T:~,whidl conducts and acts as, Ii, current sink to the 'lioad Cl, wh.ich discharges, through Uta, 0 volts ~GND),. 'The Vou.,falls to '~v,oIts, 'p,Ius ,_ _ ,', "'~"'8i~ on ViQ_ ~ge =V;. -,', ,b _e_ ,_ ~ ,- -U' """",.Ii. (I,UU enu 'H"-, 0 ""T:'t. the 5ih~ __ - .- _-I""" = tw~ ~,_..I '" - er ,-f-' , ~ ,CESllIt o;.,,,,,,,' co ~""~
lI,1 , _ __
1

curren,t source til' cha.r,&!the load C[toward '*" 5val,ts (V DD~Th.e output Y:aul goes to +5 V less the baseto emli,tter dro:p' VBB ,of Ta.

:c"

, c) Ch.argitlg and diisdtar~ 0,,£ load CL is very bocabSe'uansiistOD T2 present low :impedances when turned on into saturation.

,are

m,t

1'1 and is qlWlte

.. , The: ()utp~t logic' levels 'will appr-oximale the r,ail vo~!tagessince

VC&al

~. and 'etluaJs 0.7 vol'ts app~oxima,te[y, ,lhemv~~ o£krs at low output impedance and a high. inp1!lt ilmpedam.JB.Itoorupiies a relatively small area. but still has a high current drive capahlli,ty. The .mv,erter clro.llii.t haswgb. noise margins.
• .Howev,er there

ir~E

is, a.
__

'constant

D.'C.pa,thbe,tw,eenilie

:r,ailsthroughT

3.

,and T]
.... ,"" ~-

which aDowsa

'significant

:sta.ti.c CIll.t'ret\t .flow whenever\f<in

.~. logic 1. 'lbisis
;IoL"_'~;io~, URllt;: -

_...... ~i-ble a ~~_. .l!1U'1.,

.arran~.c",_:.,.C·P.=fi-'-~·. ----"O~~"'~

"~I""' ''r'ir-,-- IS anCh,ILel' .--,-c.,..Ll-_:~,-,- .Ifl..,-t'. .. uu:a;-.::; "--,-II1L, ~Il' P.rUVIeDl,. Ulltl

discltar,gepath.ror
being ~off.

C1.IDent .£rom. the base of either npntransistor when it .is TIdsadv:ersdy ·affects the speed ofadinn of th.e! cir,allt.,

Copyrighted material

PundalDlenta,lsof

CMOS VLS.I

'.

The pliob~em,of the D.C.. paththmughTl

and T'3 is eliminated in an improved /

inverter circuit shown in Fig'.4.S. However the output voltage swmg gets reduced because the output cannot go below the base to emitter v.altage ."BE' of tra_nsb;,tor T i-

vin,--

I

--_ :
I I I I

CL

----~----

----

.......~--

ONiD

Figl• 4.5 A~ alltemative B:iCMOS Iinverter

wt:m

no statio ourre:nt fl!ow

., A further .Improv'ement in inverter 'Circuit can be acl:devedJmmgresi!s,t;1l!l'5,as • c·- 4' t:: .".... resistors provl,e antm:p[i()v~ swm_g o~ OU.~U' t· -' - - ..'d" -_. - - -~A - '. --f-' 8 h OW'D. U11:'18,' '-c.u.: 'H'.e:£e,';uB vdlm,gewnen ,ei,~herbipolar transistor .is off.
1

!p-

--.--------

...... ---Voo

-......,j

..... ------

......-

.......

:....-GNO

Fig. 4.18An lim;proved 'BiCMQS InverterwiUl

lbetteroulput

liogic

-awls

.. They also provide dischargel paths lor the lb_

,currents during mm"\l,ff~ Howevm:.. fabricatingresfstms lo,f suitable values innot always convenient and may loooopy largef'spam. Henoo other artangem:en,ts, I~ethe one shown .in.

F.ig.. 4;7 areused.
Copyrighted material

,,\

PUllldla:menlals oieMOI VLS!I:
,
\

.. -----i --'----,voo
c_::

\

\

Fig~ 4.,7 ,An iimlp:roved.aiCMQ6, inverteir' usii~g IMOS tta,nsis,tors 'fo.r base c,unent (Usch~rg:e
• In. flm clrrui.t shown inFig.4.,?:, arran~ent is madeto

turn on transistorsTs

.and T6 when T2, and T~ .res~vely Me bemgturIl:edJ off. That is when 'T2; 'is tobe' turned ,oiE, T'", OPts turned-· on and It'\wvides dischar~ plathf:o[' . base current F 0. (I"' \ 0- . . . of 12' Thns we' observe; 'that D.iCMOS Inverters -are more- swtable where high load. current smIdng and, sourdng is, required. '
v

4~2.2 Ble,MOS IDriv'Qlrs '.' S~e
with bipo:li:rrtrans$skt,rs, it is convenientto use bipolar transistor drlversasthe outpull stage of inverttn' and logic gate Cir-cu1)ts. Bipolar bansistors have far sUlleriol' cbaract'erlstlcs" especially the k,ansconduclance g~l and the ~entlarea II characteristics:, as A Qompued to those of MOO transistors. By virlue of these:, 8iCMOO devices, have high current drive ,capabilities' inspiim .of occupyingsmaUer areasiin

the BiCMOS tecl"m.oJQgy isenrichoo

silicon.
• , In the bipo,Jlartransistors.. there is an.exponentiall dependence of 'the ooUector (output) ament' lconfhe base to enutter (input), voltage V£ie.. Hence -t.:he bipoatfansis1tars can. be eperated' with much. smaller input voltage swings than MOStransistorsand sHU switch larger' curr,eots. This better switching performance is o,ffi;et by the m.d ,that a small amount of charge mrequbed to be .moved during switching,. Anoithe:roonsiderauon inbi-pc,lu devices ~ that of thetem:peratu:reeffect o,nin~t v:olta_geVbe• However here too, one properly that comes to ad.vantage is tha.taltlhough V"bels logariitbmiea:IJy dependent on collector CIL1ITe1lt1c and. se~v.erat,other parameters sueh as, base width", doping' levet, e1edron .mobility, it is simply :linearly depend.enton.k:mpeIahue. Now theitemperaMe' differencesaC'WSS an. Ie aIle not very high. 1hus.- the Vbe' values of the bipolar devices spread over the chip remain matched, and do not differ by mere than. a. few .mililivO:lts ..
l

Copyrighted material

Funda .. nrtalls of CMOS, ¥lSI'

4 ..8 driving a capacitive load can the help of the equivalenlt dreWt gitv1erl in Fig. 4.8.
a bipolar transistor

.. 'The switching pedarmanceof
be arudyzedtobegtnwith

~----tl----- vlJD

fig'. 4.8 ID;rivin,g a1biliily ,of bipolar tran:sis,mr

V~i r
I

f--------..----ovout
Ct
'Vas

,. The time At ~re'l:ujIed to change theoutput volmgeVQut by anamount equal to
the' innutv,oltap"p - ·c- '-' 0'-

v:.J~- is

a.t .~. Ct.
8m
"b:ansisto.r ..
where! CL, is the 10'ad.capacltance The value of At is smallbeeansethe

and gm thetransoonductance!

of the bipolar

tral'1lSCOndu.cta.n:oo ,0E the blp'~ola:rkartS~klt is ,

relativ-ely higher. •

.

A mere deWled. ,analYSE of the dday due to the bipolar transisto'r reveals tna,t it ,lis made1l1p due to MO main components viz Jin and Tr.. The tiime Tin is that required to fils! dmrge the base emitlerjuncition, of ·thebipolar (npn) t;ransistor. "f"b!~, tim.::_, '~"}r~)' ';.-. .. ... __ nsriVl!, _ ••••. J,.. :u::t ~ 0 il~ '~.' ,! ......~~V'.- 2·';',;.-, J!':A]i' 'til,; @ p!_lny~",",]!8~"'"ri,ot;·l-~_b-~I~ .. .J driv:'t". ''ry- ..,.. CDttfiter· __ ::.-~iC' -~~OS..ur _~. e_. J,.r,ru:: _ .• part to thls£or the CMOS driver is the tUne reqnired' to ,charge ilie mputga1w capad,bmoeand is 01 the or-der of 1. ns, Tin in. case' of GaAsdriver Is !Uound ~U)O .PS' Thus the Ti"~ror'bipomtrmsfstorsm the highest in.c~)mparisOn . the. timer'equiredto,
cltar~fhe output

.-,., Th.e!time!TL.is

load 'ca:padtance Ct. and

equa,ls (V lId) (lJhfo) e,L. 'Thisiis less for the! bipolar driver by a fact\x'of llJ~ as ,oompaadtolMOS drivers, The :parameter 12ft is the gain of titebifolar transistor. ThusTt, fur the bipoJartJcmsismr is less. 'D:rls ,oompensatesto,r'the .higher value O'f Tin.

sigoHicant aspect whl1le ,considering -delaymihecollooltor resiStmce .Rc·through: which the ,cbaJgingrurrent for C L flows. Hence a high. vaJ.:u:eof .Re resd,fs .into a .longer propagiltion delay. The efted .of vlilltle of Rc 00 'the dday can be understood &om~ig.4.9whi.ch shows typjmJj. delay values alhVa values of Cb asa functi.on of Rc. 'The use ·of thebnried. subcoB.edor (BCCD)
.Another region in. BiCMOS fabrication is to bepRc as low as possible.
Copyrighted material

Fwndamantals at CMOS

vun

.: eo!lectof resistance' (Q)'

Fig .• 4.,9 Ga .• dDlay as afunctioin

af cQI11acmr resiistanoe

..

All ,the,serequir,edl reahtres discussed above ave incorporated into the bipolar devices under the BiCMOS fabrication. process, The devices thus ha.ve~gh p" ~gh 8m' high: hft . and low Be. The p"esence of 80m ·efficient and advantageous devices on. chip offersa great d,eal,of scope and. ,freed.omto the . VLSI designer,

,4,.3 Pseudo nM'O,S, Laglie
.' CMOS logic gates .bavefoUowing drawbacks a.) Increased, area. c) Greater delay •
b) Increased. capaettanee,

d) COmplexity

Ther,emra pseudo, JUdOS ,logic is an alternate ga,te circuit that is used as supplem.ent fo:r complementaryMOS circuits, IPig.4.10 shows pseudo HMOS logic :i!nveriel .
The, adlvantage of pseudo nMOS over CMOS is.. each input is each input· must

•'

be' cQ,rmectedwthegat.e 0,1 only ,anaansiswr' or ,alterna.Hv,ely,ody·,.one additionaltransistor (nMOS) wID. be needed WI' each additionaIga.te input

Copyrighted material

Fundamentals of CM'QS VLSI

'-1.0

r

.. Transistor ~ Q N driven by input vo~~age whereas gate nftranststar Q 'p Is grounded. 'Iranslstor QNactsas driver and 'Op ad as load, hence the name . pseudo nMOS. The number .of h',ansISitors required in pseudo nMOS is less ,'. ; '.. than. complemencry CMOS. Fig. 4..11 shows four mput pseudo n'MOS .NQR and _: ' NAND operations,

A

Pseudo, rnMOS

¥.~ (.A+

!NOR operation
B"

c '+-D)

.PootldJ) nUDS. NAJNI[)
¥= ABCID

Ope:t:artJOIil

F:~g.4.11 • The pseudo nMOS is preferred where high output 'is needed for most oftbe time'. In. such ,condition. the static power dissipation, is much. less alsa fhe propagation d,e~aybecomes shart,er.+ oommo~ appti,canon ,ofpseudonMOS is m design .of address decodersformemory :chlps and. :bl· ROMs"
. \

,

\

,

4.. IDynamic CIM'Q,S,logiic 4 .. A d~mic,'~MOS logic cons]s:ts~ of~an n-trenststor logiC' structure of w rum uutput node, is preeharged '~O V DO by a pass trartsistor\ and discharged condiUonaUy by an n~tr~nsls,to!r \ connectedto V ss'. The preeherge phase occurs wh.en. eLK .~ O,ihe supplypath is dosed vila n-transistor' 'ground swikh' during ,eLI< = L 'Themput c'apacita'nce

.

.

"

\

\

-.
.... ---.. ......... i,

I~rnpum.

I

.N. ~•.~~.•. -_'.iIe ,L_~rlt:I" ~lroti.I_· '_ih_
I -,

,

,

,-CUK --

'-:

-I

of this gate is same as ps:eudo nMOS gate. 'The
Fig. 4.12 IBasi~cO,MOS dymall11i!c gatesU'ucb.ire
Copyrighted material

FUindallDel1tallls of CMOSiVLSI

CMOS,Logic Struct.ures
is

pull-up time is impR-lved by virtue of active switch, bat pull-downttme increased due flO' groood switch.

There cUle many advantages of dynamie CMOS logilc over staHc CMOS logic or_ pseudo nMOS IO,gjc. The elimination of complementary pMOS transistors S]gnUl.cant1yreduces~he :s,una.ce needed. roimplement fhe vano1!lS logic functions. The sWitching speeds are increased using the dynamic' logic.

.. Clocked CMOS logic: is used for low-power dissipaUon. 'I'his IO,gj-c structure IS meant to :in,co:rpora~elatches or interface with other form 'Olf logic. Fig. 4,]3 shows a docked CMOS gate.

I

'

--

-

II

I

- cU< --~-+--

I

.... --~_--~~-~_--- .......--+<II ---ilI

'.

Copyrighted material

Funda.menta,ls o~CMOS VLSI '. These ~ogjc structures

4 ·~·112
are Intreducedto

inco,tpO:fate latches OI.r·interface with other dynamic forms oflolPc, The c~ocked CMOS gatehav1e samelnput capacitance as other complementery gates butIarger rise and faU times because

Q!f series clocking transistors,
.. The series clock transistors can either be ,at the output of the gate or at the power supply ends. Since doc~ed. CMOS d.rcuit places 1m additiona1 n-transistors in series with logic tran_sistors it~s lIeQo.ro.mended remedy ~Ot ".hot . electron effects",.' . ...

Pass-transffitot legicmodel is shown in Pig;..4.14.. It has a set of oonb"oI si,gnais are appUed to the gates of n-tranststors Anothe~rset of pass signals are applied

to sources ef n~tr,angistor"S.
Cantro! sjgna~s
i

/0-'-"-'

'_'0_"'_"I' 0--"'_"'-"-",.

Pi

~
I

'I ~

'~ I
il
I

:Pass siglli1als ~

iiPrtlduct.
• I
1"1

te:rrJI

V, .,

II

'
1

---\:~., ~:_.~,'_._.. ._._,_._._.i _

i

Fig .. 4.114 Pass-tralnsistor model
-The product terms Pi consists of number 0:£ transistors In serles ·controUed. by .

control variab~es and. fed. with a pass var.~able. .
F

=

.P1(V1)+ .P2(V2J+

...• p~(Vn)

where, Vi art! the pass variables. ..

WhenI';

is true,Vj" Is pesaed to output. The pass variables take the values {O, 1, X:it ~:X it Zl ..
~ Xi is complement of i.th·vadalb:le .
.

where..X~ is ttuevalue of it:h. variables.

.z is high

impedance state.
,

A common 'U!S€ o,fpaS&'~rans]stor logic is iin the oonstruc~ti.on of a Boolean :function unit.. AU Boolean functions such. as OR" AND, .NAND! XOR,' NOR etc.

eanbeimplemented.

Copyrlqhted material

Fundamentals of Cr",DS VLSI

4 -113

CMOS Log!ic .StruC'tures, ..
-

'.

The nMOS version of pass-transistor logk has the fas~est faU time and CMOS verswn has the fastest r~8e time. The pass-transistor networks provide good. logic levels but .iincurexrra pull-down de[ays.. Also these networks has higher mternal node eapadtanc~.

4.. CMOS IDomino Logic 7
• Modification in ,docbad CMOS logic allows a single clockto precharge and evaluate a cascaded set of dynamic Io,gicb~ocks. The medication involves incorporating a. static CMOS .mve'.rte.r into. each gate. F~g., 4.1S iU[lSt:ra.~ CMQS

domino logic basic' gate,

--- z

O)Inamiic ga,te

lll!illveder

Fiigl.4 ..1.5 C:MOS domil'",o~ogic basiie gate

When el.K .~ 0 (ptemarge), the output mode of dynandc :fja~ is precilarg,ed high and buffer output is low. Sincesu.bsequent: logic stages. are fed .&omtms buffer ...transistors in this logjc blocks win be turned ·o.ff durmg p'recharge ' phase .. 'Th£ output win dischargewhen gate Js '~valua;ted, nl,a~kingbu.ffer oatputhigh ,condi.tionally. In thJs way 'eacb gate in sequence make at most one transition (1. tOIO) and. a buffer can make onlyone transition fr-om {) to 1.
Copyrighted material

4 -114 • ~. cascade,d .logic~locks, each...state. ~va~ua.tes an~ cause~ .the next stagew' eva.lua.re Similarly line of dOrmtn.osfaU .. 'Thus a. smgJ.e: dock can be used to precharge and evaluate all logic gates within a block.

4~ 1.1 Static Vers·i:ornof rCIMOS;DOrmiino Logic
• Static version of CMOS domino logic include a weakp ..ttansistor as shown. in Fig. 4.. 6. A weak p-transistor has low gain (smaUW IL) ratio. 1 "

r+ -1_/
i.

VCOo

.

Weak
p-devioo

eLK --_---

F'lg •. 41.116" Static CMOS, domhlo log,ic

.r

The p-translster has the gain such that
Domino Logic l,8;t:ehad· Velrsriion

it

does not flg;httbe

PUU-dOwD

transistt)rrs and can balance the ·effect o.f leakage.

4~7.2CMOSr

.. The Side,may also be made latching byindurling as shewn in Fig,. 4.t7.

a weak. P feedback transismr

----

-~.Z

InpUrts --

--

,

-

OUK ---~_.

~--:
_1-

Fig. 4.11 'CMOS dominlo logic I,atclhedve;rsionl
Copyrighted material

Fundamentals of C:MOSVLS~ .

4, .. 15

4.. Cascade~' 8 Voltag,eS~iteh

LOlgiic(CV,SL'
~OlgiC

A cascade voltage, switch logj.c i~ a diflere-ntiaI roml of

to.. be routed to, gates. It's structure c-onsists Qif two ,c-ompleme:P.ctarynMOS swiEch strD.chu:e are' constructed and then coaneeted

true' and ,c-omRlement signals
,C1)OSS

l'eqtthin_g boOth

to a pair of

coupled c-oupled P pull ..up transistors. Fig. 4.18 shows, CVSL.
\ "_,Voo

Q ~~
\

........ ~~..F

-,

"\.~_~_~'

~_

.....

_
\..

Q

Differ,el'lfi~1 ,lnputs,

nMOS
\..,

\_

-- ~

.,

--

\\

/"

Combinatoriall

- - Il'!etwr§rk -

Fig,. 4.18 Basic cascade' voltage, sWiltch II:og'ic


\

As 'input 5wikb.es, nodes Q and. Q. are. pulled ,high

or low.
,

iPosiHve ~eedback

applied. to P puJ]]-ups causes the gate to sWitch. The: static CVSLgate is :slower than conv~ti.onal comptem.entarygate employing ap-tree andn.ib"ee.Durln_g:

swit-dl . acting, the lPpull-ups have to aghtthe n pull-down trees, . 48' _.,.
'1'

,,' ""VS' , '-" .C'-I'1i,. ,d' v,,- .• L ',--!oc"e_

V,i' rsllQ:n ',.e " .•

,

.......

'II

A docked version o.f CVSL consists--·,o.fW,Q domino operating on true and cOlinple.ment inputs-With a. mi:runUzed :toglC' tree as sh.own. in Fig. 4.1'9.
'-

gates

"-, -,

C~iifla~I'
,i1Istworl!,

Fig •. 4.119 CVSiL cIOckecl've:rsia:n
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·,·16

CMDILoglicSbucturas

The advan.ta,~ of docked version of 'CYSL oyer do.mino logic is, its abflityto gene'raie! any IOglc expressianmakiing it a. completelogilc:fa:mlly. 'Ibis is very useful where automated. l!ogk synthesis is ,f;equiiIed.A four way ~OR gate lmplementadon is shown in Fig. 4.2.0.

Q_c_

:F:ig~ 4.2G4way

~.QR 'g.h, iR1ple.anitaltion

lin eVIL

,4.,8 :Sallpla4et .2 .

,.1l1t.e' amplliifier ~

DifferenUal ILogile ,(SSDIL) penormance o£ CVSL is gr-eatly imprurved by adding a latChing sense

,is caDed samp~ c:liftemntial logic:: (SS,DL). Fig. 4.21 ;shows :SSDL. The ,opera,tion is sHghtily ,dHfetent fr-om dyrulmic' CYSL.

Copyrighted material

FundamentaJls of C!MOS VILSI

4·..17

--Q

sense, iilrJilpliifi.er

ilalch!11Ig

DiH~liIijal;
iin:pWs

nMOS

./'

Cnmbiooional

- - netWOrk-

Fig.•• 'i2~ Sa.ple4et

DUferential1 Logic (SS:D:L)

'.

When. eLK .~.0.. PIt Pil andNl
fi b',ee6.

are turned

00. One

outprutat will be at VDn

and other will be sligh8.y below VDn since a. path. em'ts tOlJSS through one of • When CLK .~. 1, ·fIle· latching senseampllfier forces the lower ou.tputt to

Vss.

Ir-------------------~~-~-~-~-~-~--~-~-~-~-~~-~--~~--~-~-~~-~~--~1

'Therefore pull-down time .:is dewrminedby single pull~own .rather than series oonnedionpuH-downs. in. traditional CVSL. '

i

P'Qinls to IRem,8mber

1. Various CMOS, logic strl.tciltu.res re: a a) CMOS comp,lementary logic
C)-p, --, 4i~ _:Se1lQU

b) BiCMOS logic
d_·. '..).. :

nM~ _~_:\,..10'

100'l. .e.er •c

.f)..ff:i~ ,--, -,!tI!_, -,"'~~

·-_-ii~,C_·• .

~"l

~_-_I•_·· -••.• __..... _-_08.-..

_.-. .

1_·r'....-._-..•·K!"1I e ...i ~o~..

e) Clocked ,CMOS logic
g) CMOS domino logic

.£)1 Pa;ss-,transistor logic

~----------------------------------------------~~-~-~-~-~-~.-~---------'
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h)C8scade

volta&! switch iO,gic ,(CYSt.)

\

;:-=--::.-==~= -~=:=~-~-::--~==_--=~~=7=---_-:-=-_~=·_~=--_-::~~=-_~ ____ -_=::7=.--::~~=~_:-::\
-_=-

fundrame:nta,ls

of C!MOS VILSI -,

-::_~=- -::: ='.

=~=~::~.-- -=-=-=-=-=-=- =.-=- ===-=-=-=-=-=--=--=-=... =.-=.

'·18

===~\.
\

\

.\

- 1 1$ nOJSe umnune, t
!Ii if! ;to

_,

!

'

- .It dissipates no d.e, power,

'..

- It is fast. EasytQ .fabricate,.
- Large' fan-in.

3. BiCMOS logic is, preferred in. ' " -. ' -Mixed Si_paJ, sthlations.
.
,",,,

\

- ,ffigh speed a:pp1i.caOOD.S.
'.

\

7. CMOS domino logic is tied ,£orlow poWetol'Jugh speed applications.

;

8. CVSL logic is used, in ,fast gates using cascode CVSL or SSDt. 'The ga,tes are synthesizable.

Ri,evi:ew QlIestioins,
1. ,Expltiin CMOS ,oompJ~tIIry 2. Murl an BJCMOS logic ? B~n 3. 1J.riqly' ,expunn B~CM()S':ilmerter.
4. Di$mss BiCMOS ,~,

Wgk.
BiCMOS .NANDmith npnplln-iJuwn~

-

5,. ExplRin ,~nMaS £.','.. E-'~al1U,I'".e- WLu ~r~ :J.~t _. 't'r. t.~n"'~ t> 7~Whl

d,.,~....:,.".",,',:, "o'S'" ~ .. ~."_,~",,, O:~lIo',J_~M~""'. ,,,~nl!J_,"~''''"'tmnm.'"CM·" _, ,-t""'G' ......."'M~j_

",_,.4.1...

.1

Giw itsmmtB and demerits.

is cloekedCMOS ~fe? WIeR II .i5 preferred?' ,
IimilitltUms ofpass-·transist«

,
~?
I .

8. Wb~ .rwe· th bm~ts _

9. Explain CMOS domino' logic. ,Gi.its
i,
I

typical .trppJiaJtionaras.
.!I'r&l,

10'. E:xplRin slGfi,cva:sUm of CMOS dbmiuo logic. .fx.pltdn Cascade Vol1'll:ge Switch .Logic (CV;SL).. GiOOits prefenWl . ."mdton
12. Wht is CV8,1. clockwrswn ?

:. u.

13. Briefly' explain SSDL

tJl~1J
Copyrighted material

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