Trio Adiono

www.paume.itb.ac.id/~tadiono/el-4040/

Introduction to VLSI Technology
Week # Date

Topic Sub Topic What is Due? Pustaka
1 Introduction to VLSI Technology What and why VLSI Circuits ?, Moores Law, Important Issue in VLSI Cost Design, Technology
Improvement, State The Art of VLSI Technology Systems-on-a-Chip (SoC), Long-Term Trends
2 VLSI Technology Implementation -Semicustom
-Full Custom Technology
Full Custom and Semi Custom Technology
3 VLSI Technology Implementation -FPGA Technology FPGA cell architecture
4 ASIC Design Flow -Design Entry
-RTL Coding
-Logic Synthesis
-Placement & Routing
The detail design flow from design entry until chip layout for standard cell based design
5 ASIC Architecture Design -Arith Adder
-Arith Multiplier
-Arith Divisor
Mapping from algorithm to signal flow graph, block diagram and timing diagram
6 RTL Based Design -FFT Design
-BCH Encoder Decoder
-RSA Encoder/Decoder
Verilog Based Combinatorial and Sequential Circuit Design
7 Design Simulation & Verification -CAD Tools
-Waveform Based
-Script Based
Functional and Full Timing Simulation
8
Midterm Project
9 Logic Synthesis - Area and Speed Based Synthesis,
- Design Constrain,
- Bottom Up and Top Down Synthesis
10 Floorplanning - Cell Placement,
11 Placement and Routing - Power Routing,
- Detail Routing
12 Static Timing Analysis System Clock, Critical Path, Set-up Time, Hold Time
13 Design Rule Check Technology File, Design Rule Check
14 Design for Test Boundary Scan, ATPG, Full Scan, Half Scan
15
Final Project
Chip
Why VLSI?
Integration improves the design:
lower parasitic = higher speed
lower power
physically smaller
Give the control
High Performance
Easier to design
Integration reduces
manufacturing cost-(almost) no
manual assembly.
300 mm wafers & 90
nano-Technology
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
The First Computer
5
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
ENIAC - The first electronic computer
(1946)
6
The Transistor Revolution
Birth of Modern Electronics -- 1947
AT&T Bell Laboratories -- Invention of Point Contact Transistor
William Shockley, Walter Brittain, and John Bardeen
Winners of the 1956 Nobel Prize in Physics
Vacuum
tubes ruled
in first half of
20
th
century
Large,
expensive,
power-
hungry,
unreliable

Read Crystal Fire
by Riordan,
Hoddeson
First transistor
Bell Labs, 1948
The First Integrated Circuits
8
Bipolar logic
1960s
ECL 3-input Gate
Motorola 1966
Intel 4004 Micro-Processor
9
1971
1000 transistors
1 MHz operation
Intel Pentium (IV) microprocessor
10
Moores Law
11
In 1965, Gordon Moore
noted that the number of
transistors on a chip doubled
every 18 to 24 months.

He made a prediction that
semiconductor technology
will double its effectiveness
every 18 months
Gordon Moores Law (1969)
Two components:
Transistor dimensions reduce by 10.5%
every year
Density increases 22.1% every year
Additional 22% increase every year due
to:
Wafer and chip size increases
Circuit design and fabrication process
innovations
44% transistor count increase in
microprocessors every year
Transistor count more than doubles every
2 years
co-founder of Intel.
Annual Sales
10
18
transistors manufactured in 2003
100 million for every human on the planet
Moores Law
14
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
9
5
9
1
9
6
0
1
9
6
1
1
9
6
2
1
9
6
3
1
9
6
4
1
9
6
5
1
9
6
6
1
9
6
7
1
9
6
8
1
9
6
9
1
9
7
0
1
9
7
1
1
9
7
2
1
9
7
3
1
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4
1
9
7
5
L
O
G
2

O
F

T
H
E

N
U
M
B
E
R

O
F
C
O
M
P
O
N
E
N
T
S

P
E
R

I
N
T
E
G
R
A
T
E
D

F
U
N
C
T
I
O
N
Electronics, April 19, 1965.
Evolution in Complexity
15
Transistor Counts
16
1,000,000
100,000
10,000
1,000
10
100
1
1975 1980 1985 1990 1995 2000 2005 2010
8086
80286
i386
i486
Pentium

Pentium

Pro
K
1 Billion
Transistors
Source: Intel
Projected
Pentium

II

Pentium

III

Courtesy, Intel
Moores law in
Microprocessors
17
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
T
r
a
n
s
i
s
t
o
r
s

(
M
T
)

2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
Die Size Growth
18
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
D
i
e

s
i
z
e

(
m
m
)

~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moores Law
Courtesy, Intel
Frequency
19
P6
Pentium proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
F
r
e
q
u
e
n
c
y

(
M
h
z
)

Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
Power Dissipation
20
P6
Pentium proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P
o
w
e
r

(
W
a
t
t
s
)

Lead Microprocessors power continues to increase
Courtesy, Intel
Power will be a major problem
21
5KW
18KW
1.5KW
500W
4004
8008
8080
8085
8086
286
386
486
Pentium proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
P
o
w
e
r

(
W
a
t
t
s
)

Power delivery and dissipation will be prohibitive
Courtesy, Intel
Itanium Temperature Plot
[ Source: Intel ]
MOS Technology Trends
Summary of INTEL Processor
10
4
increase in transistor count, clock frequency
over 30 years!
Towards nano-scale
83 86 89 92 95 98 01 04
0.1
80286
80386
486
pentium
pentium II
1.0
0.2
0.3
2.0
0.05
Pentium IV
0.03
Itanium
07
Micron Sub-micron
Deep-sub
micron
Ultra
Deep-sub
micron
Nano
Towards nano-scale
E. Sicard -
introducting 90nm
300mm wafers In a 300mm fab
UMC taiwan
Power density
27
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)

Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
Technological improvements
Increased interconnection
layers > 10 and increasing!
Important improvements
Many interconnections ( 8 or 10 layers) are crucial
Improved fabrication
Better control of Vth
Optimised (low power) circuit libraries
(sometimes parameterised)
Reuse of Cores / IP (currently major issue !)
Good CAD tools for system-level design
Reliable compilers, optimization in speed and /
or power (e.g. Synopsis)
Important improvements
Memories are the technology pushers
Line width reduction
Current mass production: 0.13 um line width
Consequences for Vdd and Vth and speed
Current research: 64nm to 32nm line width
Transistor operation proved at much smaller
dimensions: problems of cost
State-of-the Art Design Goals
Very high integration density
Large silicon area available (12 inch mass
production = pancake size)
Very high speed: exceeding 4 GHz
Very low power dissipation
Combination of logic & embedded memory
(Flash & EEPROM, SRAM, DRAM, > 50% and
increasing)
Not Only Microprocessors
32
Digital Cellular Market
(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF
Power
RF
(data from Texas Instruments)

Cell
Phone
Challenges in Digital Design
33
Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.

Everything Looks a Little Different
Macroscopic Issues
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.


and Theres a Lot of Them!
DSM 1/DSM
?
Productivity Trends
34
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2
0
0
3

1
9
8
1

1
9
8
3

1
9
8
5

1
9
8
7

1
9
8
9

1
9
9
1

1
9
9
3

1
9
9
5

1
9
9
7

1
9
9
9

2
0
0
1

2
0
0
5

2
0
0
7

2
0
0
9

10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
x
x x
x
x x
x
21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded
Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
L
o
g
i
c

T
r
a
n
s
i
s
t
o
r

p
e
r

C
h
i
p

(
M
)

0.01
0.1
1
10
100
1,000
10,000
100,000
P
r
o
d
u
c
t
i
v
i
t
y

(
K
)

T
r
a
n
s
.
/
S
t
a
f
f

-

M
o
.

Source: Sematech
Complexity outpaces design productivity
C
o
m
p
l
e
x
i
t
y

Courtesy, ITRS Roadmap
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every
two years
Hence, a need for more efficient design methods
Exploit different levels of abstraction
35
Design Abstraction Levels
36
n+ n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Design Metrics
How to evaluate performance of a digital circuit (gate, block,
)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
37
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
38
NRE (Non-Recurrent Engineering)
Engineering cost
Depends on size of design team
Include benefits, training, computers
CAD tools:
Digital front end: $10K
Analog front end: $100K
Digital back end: $1M
Prototype manufacturing
Mask costs: $500k 1M in 130 nm process
Test fixture and package tooling
Recurring Costs
Fabrication
Wafer cost / (Dice per wafer * Yield)
Wafer cost: $500 - $3000
Dice per wafer:

Yield: Y = e
-AD
For small A, Y ~ 1, cost proportional to area
For large A, Y 0, cost increases exponentially
Packaging
Test
2
2
2
r r
N
A
A
t

=


The Cost of Fabrication
Current cost: $2-3 billion
Most profitable period is first 18 months-2
years


Cost factors in ICs
For large-volume ICs:
Packaging is largest cost
Testing is second-largest cost


For low-volume ICs:
Design costs may swamp all manufacturing
costs
NRE Cost is Increasing
42
Die Cost
Single die
43
Wafer
From http://www.amd.com
Going up to 12 (30cm)

Cost per Transistor
45
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
cost:
-per-transistor
Fabrication capital cost per transistor (Moores law)
Yield
46
% 100
per wafer chips of number Total
per wafer chips good of No.
= Y
yield Die per wafer Dies
cost Wafer
cost Die

=
( )
area die 2
diameter wafer
area die
diameter/2 wafer
per wafer Dies
2

t
=
Defects
47
o
|
.
|

\
|
o

+ =
area die area unit per defects
1 yield die
o is approximately 3
4
area) (die cost die f =
Some Examples (1994)
48
Chip Metal
layers
Line
width
Wafer
cost
Def./
cm
2
Area
mm
2
Dies/
wafer
Yield Die
cost
386DX
2 0.90 $900 1.0 43 360 71% $4
486 DX2
3 0.80 $1200 1.0 81 181 54% $12
Power PC
601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100
3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha
3 0.70 $1500 1.2 234 53 19% $149
Super Sparc
3 0.70 $1700 1.6 256 48 13% $272
Pentium
3 0.80 $1500 1.5 296 40 9% $417
Optimization for Chip
Core speed vs. area trade-off for a specific voltage, temperature, and
process
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
Understanding the design metrics that govern
digital design is crucial
Cost, reliability, speed, power and energy
dissipation

50
Top 15 Worldwide Semiconductor Rangking
Development Cost