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Dept. of Electronics and Communications Engg. CITY ENGINEERING COLLEGE BANGALORE – 62.

Manual Prepared by: Mr. Vishvakiran RC, Asst. Prof., CEC

Logic Design Lab

2013

10ESL38

TABLE OF CONTENTS

Experiments

IC Pin Configurations 1. 2. 3. Boolean Expression realization using Logic gates Half/Full Adder and Subtractor a. Parallel Adder/ Subtractor b. BCD to Excess-3 and Vice-versa 4. 5. 6. 7. 8. 9. Binary to Gray Conversion and vice versa MUX/DEMUX for arithmetic circuits Comparators Decoder Chip for LED Display Priority Encoder Flip-Flop verification

Page No.

2 4 7 10 14 16 21 27 31 33 35 38 50 55 57 59 60

10. Counters 11. Shift Registers 12. Ring Counter/ Johnson Counter 13. Sequence Generator Logic Design Lab Syllabus – 10ESL38 Possible Viva Questions

3rdSem, E&C Dept.

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Logic Design Lab

2013

10ESL38

**IC Pin configurations
**

Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS

2-Input OR Gate - 7432LS

2-Input NAND Gate - 7400LS

2-Input NOR Gate - 7402LS

2-Input EX-OR Gate - 7486LS

3-Input NAND Gate - 7410LS

4-bit Binary Full Adder74LS83

3rdSem, E&C Dept.

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Logic Design Lab 2013 10ESL38 Dual 4-Input NAND Gate .7420LS Dual 4-input Multiplexer74153 4-Bit Magnitude Comparator .7495 Synchronous Up/Down Counter– 74192 Decimal scalar . 3 VK . E&C Dept.7490 DualJKFlip-flop– 7476 3rdSem.7485 Decoders/Demultiplexer 74139 Shift Register .

IC 7486 (EX-OR) Procedure – 1. check them against the truth tables. Verify that the results are correct. IC 7432 (OR). Connect VCC and ground as shown in the pin diagram.Logic Design Lab 2013 10ESL38 Experiment No. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic. 10. 2. 8. Implementation Using Universal Gates 11. Realize the simplified expression using logic gates. 4. B. A: Implementation Using Logic Gates 5. 13. and then using only NOR gates. 1 BOOLEAN EXPRESSION REALIZATION USING LOGIC GATES Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates. Construct a truth table for the given problem. 9. 7. IC 7402 (NOR). Verify that the gates are working. 12. 3. 4 VK . Check the output readings for the given circuits. apply inputs according to the truth table and verify the results. Components Required: - IC 7408 (AND). 3rdSem. IC 7404 (NOT). E&C Dept. Connect the circuits according to the circuit diagrams. Simplify the given Boolean expression manually using the Karnaugh Map. Implement the simplified Boolean expressions using only NAND gates. Draw a Karnaugh Map corresponding to the given truth table.IC 7400 (NAND). Apply the different combinations of input according to the truth tables. Make connections as per the logic gate diagram. 6.

D)=BC+BD POS form Y=f(A. E&C Dept.B.C.B.C. 5 VK .Logic Design Lab 2013 10ESL38 Given Problem: Truth Table: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 Switching Expression: ∑ π Karnaugh Map Simplification: K-Map for SOP CD AB 00 01 11 10 BD 00 01 1 1 11 1 1 10 1 1 BC C+D AB 00 01 11 10 CD 00 0 0 0 0 01 0 11 0 10 0 B 0 0 0 K-Map for POS Simplified Boolean Expression: SOP form Y=f(A.D)=B(C+D) 3rdSem.

Logic Design Lab 2013 10ESL38 Expression Realization using Basic Gates: C B D 1 7408 2 4 7408 5 3 1 7432 2 6 3 Y=BC+BD B C D 1 1 7432 2 7408 3 2 3 Y=B(C+D) Realization using only NAND gates: Realization using only NOR gates: 2 1 5 7402 6 8 7402 9 10 C B D 1 7400 2 4 7400 5 3 9 7400 6 10 8 B 7402 3 4 Y=B(C+D) Y=BC+BD C D Realization using only NOR gates: C B D 2 7402 3 5 7402 6 8 7402 9 10 1 11 7402 12 4 2 7402' 3 1 13 5 7402' 6 8 7402' 9 4 10 Y=BC+BD Realization using only NAND gates: B C D 1 7400 2 4 7400 5 10 6 3 9 7400 8 11 7400 12 13 1 7400' 2 3 Y=B(C+D) 3rdSem. 6 VK . E&C Dept.

7 VK . the half subtractor and full subtractor circuits. 2 HALF/FULL ADDER AND HALF/FULL SUBTRACTOR Aim: – To realize half/full adder and half/full subtractor using Logic gates Components Required: - IC 7408. etc. IC 7486. on the trainer kit. Switch on the VCC power supply and apply the various combinations of the inputs according to the respective truth tables. 6. 3rdSem. Verify that the gates are working. Repeat the procedure for the full adder circuit. Note down the output readings for the half adder circuit for the corresponding combination of inputs. 5. Procedure: - 1. 3. E&C Dept.Logic Design Lab 2013 10ESL38 Experiment No. 2. Make the connections as per the circuit diagram for the half adder circuit. 4. IC 7432. Verify that the outputs are according to the expected results. Verify that the sum/difference and carry/borrow bits are according to the expected values. IC 7404. 7.

E&C Dept. Full Adder Using Logic Gates Full Adder Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1 3rdSem. 8 VK .Logic Design Lab 2013 10ESL38 A. Half Adder using Logic Gates: Half Adder Using Basic Gates A B 1 7486 2 1 7408 2 3 A 0 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 3 0 1 1 B.

9 VK .Logic Design Lab 2013 10ESL38 C. Half Subtractor Using Logic Gates Half Subtractor Using Basic Gates A 0 0 1 1 B 0 1 0 1 D 0 1 1 0 Bo 0 1 0 0 D. E&C Dept. Full Subtractor Using Logic Gates Full Subtractor Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1 3rdSem.

IC 7486. In order to implement the IC 7483 as a subtractor. 2. In order to Perform Addition take S=0. Take S=1. IC 7483 Pin Diagram 7483 3rdSem. Check the outputs and note them down in the table for the corresponding inputs. Procedure: 1. etc. 6. 3 PARALLEL ADDER AND SUBTRACTOR USING 7483 Aim: –i. 5. 4. Apply the B input through XOR gates (essentially taking complement of B). BCD to Excess-3 Code conversion and Vice Versa using IC7483 Components Required: - IC 7483.Connect the pins from S1 to S4 to output terminals. E&C Dept. 10 VK . Verify that the outputs match with the expected results. 8. To realize Parallel Adder and Subtractor Circuits using IC 7483 ii.C0 to XOR gate 1 input and other input take from C4 and obtain the Output Carry Cout (Output Borrow Bout). Connect one set of inputs from A1 to A4 pins and the other set from B1 to B4. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables.Logic Design Lab 2013 10ESL38 Experiment No. Short S. 3. 7. on the IC 7483.

E&C Dept. IC 7483 as a Parallel Adder Circuit Diagram: VCC A4 A3 1 3 8 10 16 4 5 14 C4 2 1 Output Carry 7486' S4 S3 S2 S1 3 Cout Input Data A A2 A1 1 15 2 6 9 B4 B3 B2 B1 7486 2 4 3 Data Output Input Data B 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=0 Truth Table:Input Data A A4 1 1 0 0 1 0 1 1 A3 0 0 0 0 0 1 1 0 A2 0 0 1 0 1 1 1 1 A1 0 0 0 1 0 0 0 0 4-BIT Parallel Adder Using 7483 where S=0 Input Data B B4 0 1 1 0 1 0 1 1 B3 0 0 0 1 0 0 1 1 B2 1 0 0 1 1 1 1 0 B1 0 0 0 1 1 1 1 1 Cout 0 1 0 0 1 0 1 1 S4 1 0 1 1 0 1 1 0 Addition S3 0 0 0 0 1 0 1 1 S2 1 0 1 0 0 0 0 1 S1 0 0 0 0 1 1 1 1 3rdSem.Logic Design Lab 2013 10ESL38 A. 11 VK .

12 VK . E&C Dept. Bout = 0 for A>B. IC 7483 as a Parallel Subtractor VCC Circuit Diagram: A4 A3 1 3 8 10 16 4 5 14 C4 Output Carry 1 7486' 2 3 Bout Input Data A A2 A1 1 15 2 6 9 S4 S3 S2 S1 B4 B3 B2 B1 7486 2 4 3 Data Output Input Data B 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=1 4-BIT Parallel Subtractor Using 7483 Where S=1 Truth Table: Subtraction Input Data A A4 A3 A2 A1 B4 Input Data B B3 B2 B1 Bout S4 S3 S2 S1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 Note: Bout = 1 for A<B.Logic Design Lab 2013 10ESL38 B. 3rdSem.

e. A4 _ A3_ A2_ A1= _ B4 B3 B2 B1= 1001 1100→(1's complement) of +3 = 0011 +1 ←C0=1(S&C0 shorted) 2‟s Complement of B input = -B The end around carry is disregarded 1 0110 C0 C4 = Bout = 0 +6 4 bit subtraction operation using 7483 for A<Bhere S=1 _ A4 _ A3_ A2_ A1= B4 B3 B2 B1= 1110 0000→(1's complement) of +15=1111 2‟s Complement of B input = -B The end around carry is disregarded 0 1111 →(2's complement) of +1=0001 C0 C4 = Bout = 1 +1 ← C0=1(S&C0 shorted) -1 3rdSem.addition can be performed Ex:If ↓C0=0 A4 A3 A2 A1=1100 B4 B3 B2 B1=0011 then Sum. 13 VK . E&C Dept.Logic Design Lab 2013 10ESL38 Example 4bit adder operation using 7483 if control input S=0.if S=1(i. C0=1).S4 S3 S2 S1 =1111 and C0C4 = Cout. S4 S3 S2 S1 = 0110 2's complement method of subtraction can be performed. 4 bit subtraction operation using 7483 for A>B here S=1 A4 A3 A2 A1= 1001 B4 B3 B2 B1= 1101 (2's complement) of +3=0011 The end around carry is disregarded 1 0110 C0 C4 = Bout = 0 Difference. Consider the above Example A4 A_ 1001 and B4 B3 B2 B1= 0011 3A 2A 1= _ _ _ 1‟s Complement of B4 B3 B2 B1is B4 B3 B2 B1= 1100 .

Logic Design Lab 2013 10ESL38 C.A1.A0.A2.B2. Circuit Diagram: 1 3 8 10 16 4 5 14 C4 E3 E2 E1 E0 X NC Input Data A 15 2 6 9 B3 = 0 7486 2 4 3 Data Output Input Data B B2 = 0 B1 = 1 B0 = 1 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=0 Truth Table : BCD to XCS3 using 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=0 BCD Inputs A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 X X X X X X Excess – 3 Outputs E2 0 1 1 1 1 0 0 0 0 1 X X X X X X E1 1 0 0 1 1 0 0 1 1 0 X X X X X X E0 1 0 1 0 1 0 1 0 1 0 X X X X X X 3rdSem. 14 VK . BCD To Excess-3 And Vice-Versa Conversion Using 7483 Chip I. E&C Dept.B0 = 0011 vary the BCD input at A3. BCD TO EXCESS-3 CONVERTER VCC A3 A2 A1 A0 1 Note: S = 0 and B3.B1.

E&C Dept.Logic Design Lab 2013 10ESL38 II.A0(E0).A1(E1).A2(E2). 15 VK . Circuit Diagram: A3 A2 A1 A0 1 VCC 1 3 8 10 16 4 5 14 C4 D C B A X NC Input Data A 15 2 6 9 B3 = 0 7486 2 4 3 Data Output Input Data B B2 = 0 B1 = 1 B0 = 1 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=1 Truth Table : XCS3 to BCD using 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=1 Excess-3 Inputs E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0 A 0 0 0 0 0 0 0 0 1 1 BCD Outputs B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 3rdSem.B1.B2.B0 = 0011 vary the Excess-3 input at A3(E3). EXCESS-3 to BCD CONVERTER Note: S=1 andB3.

test and verify the working of a Grey to Binary Converter.Logic Design Lab 2013 10ESL38 Experiment No. E&C Dept. Check the outputs at the G3-G0 pins and note them down in the table for the corresponding inputs. 2. Procedure: - 1. 7. Components Required: - IC 7486. i. 3rdSem. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray converter. 6. Write the proper truth table for the given Binary to Gray converter. 5. 4. Apply the Binary inputs at B3-B0 pins. 3. ii. Gray to Binary Converter using logic gates. Draw Karnaugh maps for each bit of output. etc. Binary to Gray Converter using logic gates. 4 BINARY TO GRAY CONVERTER AND VICE VERSA Aim: – To realize:. 8. according to the truth table.Verify that the gates are working properly. Verify that the outputs match with the expected results. Repeat the procedure to design. Simplify the Karnaugh maps to get simplified Boolean Expressions. 16 VK .

17 VK . Truth Table: Binary Input B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray Code Output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Karnaugh Maps: For G3: For G2: G3 = B3 3rdSem. Binary to Gray Converter.Logic Design Lab 2013 10ESL38 A. E&C Dept.

Logic Design Lab 2013 10ESL38 For G1: For G0: Circuit: 3rdSem. 18 VK . E&C Dept.

Gray to Binary Converter Truth Table Gray Code Input G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Output B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Karnaugh Maps: For B3: For B2: B3 = G3 3rdSem.Logic Design Lab 2013 10ESL38 B. 19 VK . E&C Dept.

E&C Dept. 20 VK .Logic Design Lab 2013 10ESL38 For B1: For B0: Circuit: 3rdSem.

4. and outputs are taken at Za (Difference) and Zb (Borrow). EA is made low and if MUX ‘B’ has to be initialized.In case of Half Subtractor. The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and are verified according to the truth table. EB is made low. Making Ea and Eb zero andthe output is taken at Za.The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. Verify outputs. and Zb. The corresponding outputs are taken at pin Za(Difference) and pin Zb(Borrow) and are verified according to the truth table. IC 7404. IC 7400. The inputs are applied either to ‘A’ input or ‘B’ input.Logic Design Lab 2013 10ESL38 Experiment No. An and Bn according to the truth table. A and B (S1 and S0) are changed as per table and the output is taken at Za as sum and Zb as carry. 5.In this case. 6.If MUX ‘A’ has to be initialized. connections are made according to the circuit.In full adder using MUX. and thus the truth table is verified. An and Bn according to the truth table. the inputs are applied at Cn-1. the inputs are applied at Cn-1. Inputs are applied at A and B as shown. IC 7420. 1.etc. For MUX IC 74153 IC 74153. 21 VK . 3. 10. Components Required: Procedure – A. I2a. IC 74139. Based on the selection lines one of the inputs will be selected at the output. E&C Dept. I1b. I2b and I3b) as shown. 8. I1a. 7. In full subtractor using MUX.The corresponding values of select input lines. I3a)and(I0b. the inputs A and B are varied. apply constant inputs at (I0a. 2. 3rdSem.In case of half adder using MUX. 5 MUX/DEMUX FOR ARITHMETIC CIRCUITS Aim: – To study IC 74153 and 74139 and to implement arithmetic circuits with them. 9.

E&C Dept.Logic Design Lab 2013 10ESL38 Half Adder Using 74153 Half Subtractor using 74153 Truth Table: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 Full Adder Using 74153 Full Subtractor using 74153 3rdSem. 22 VK .

In full adder using DEMUX. 8. 23 VK . the inputs are applied at Cn-1. In full subtractor using DEMUX. The corresponding outputs are taken at Sum and Carry. For DEMUX IC 74139 1. Verify outputs. connections are made according to the circuit. the inputs are applied at Cn-1. In case of Half Subtractor. If DEMUX ‘A’ has to be initialized. The corresponding outputs are taken at Difference and Borrow as shown. Based on the selection lines one of the inputs will be selected at the set of outputs. and are verified according to the truth table. The inputs are applied either to ‘A’ input or ‘B’ input. EB is made low. EA is made low and if DEMUX ‘B’ has to be initialized. 3. An and Bn according to the truth table. 6. In case of half adder using DEMUX. the corresponding values of select input lines. 7. Verify outputs. An and Bn according to the truth table. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.Logic Design Lab 2013 10ESL38 Truth Tables for Full Adder/Subtractor using 74153 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 Procedure – B. 5.Ea is set to 0. A and B (S1a and S0a) are changed as per table and the output is taken at Sum and Carry. 4. and outputs are taken at Differenceand Borrow. 2. and are verified according to the truth table. and thus the truth table is verified. Inputs are applied at A and B as shown. E&C Dept. 3rdSem.

24 VK . E&C Dept.Logic Design Lab 2013 10ESL38 Half Adder Using 74139 Half Subtractor Using 74139 Truth Tables: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 3rdSem.

Logic Design Lab 2013 10ESL38 Full Adder Using 74139 Full Subtractor Using 74139 3rdSem. E&C Dept. 25 VK .

Logic Design Lab 2013 10ESL38 Truth Tables: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 3rdSem. E&C Dept. 26 VK .

Connect pin 16 to Vcc and pin 8 to GND for the ICs. Outputs are recorded at pin 2 (A<B).Switch on Vcc. 4. 2. IC 7408. 5.Verify the working of the logic gates. Two-Bit Comparator: 3rdSem. Study of IC 7485: 1. 27 VK Outputs A>B 0 0 1 0 A=B 1 0 0 1 A<B 0 1 0 0 B 0 1 0 1 .Check the outputs and verify that they are according to the truth tables. B. 4. and to study the working of IC 7485. One-Bit Comparator: Circuit : Truth Table: 1bit Comparator Inputs A 0 0 1 1 B.Logic Design Lab 2013 10ESL38 Experiment No.Make the connections as per the respective circuit diagrams. IC 7432. pin 4 (A>B). E&C Dept.Apply the inputs as per the truth tables. IC 7485. etc. Comparators Using Logic Gates: 1.Apply the two inputs as shown. 3.Write the truth table for an4-bit comparator. IC 7486. Components Required: Procedure – A. IC 7404. pin 3 (A=B) pins and are verified as being according to the truth table. 3. making sure that the MSB and LSB is correctly connected. A. 2. 6 ONE/TWO BITCOMPARATOR AND IC 7485 Aim: – To verify the truth tables for one bit and two bit comparators after constructing them with basic logic gates.

28 VK .Logic Design Lab 2013 10ESL38 Truth Table : 2bit Comparator A1 A0 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 Karnaugh Maps: For A>B: For A<B For A=B 3rdSem. E&C Dept.

4-Bit comparator using IC 7485 Pin Diagram: 3rdSem.Logic Design Lab 2013 10ESL38 Circuit: C. E&C Dept. 29 VK .

30 VK .Logic Design Lab 2013 10ESL38 Truth Table: 4bit Comparator Input A A3 0 0 1 0 0 1 0 1 A2 0 1 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 B3 0 0 1 0 1 1 0 1 Input B B2 0 0 0 1 0 0 1 1 B1 0 1 1 1 0 1 1 1 B0 1 1 0 0 0 1 0 0 A>B 0 1 0 0 0 1 0 1 Output A<B 1 0 0 1 1 0 0 0 A=B 0 0 1 0 0 0 1 0 3rdSem. E&C Dept.

Connect Pin 16 to Vcc and Pin 8 to GND. Components required: - IC 7447. and observe the Decimal outputs displayed on the 7-segment LCD Display. 2. 6. Make the circuit connections as shown in the circuit diagram. 3. Test and verify that all the segments of the LED Display are working. Verify that the outputs match the expected results in the truth tables. 5. 4. etc. 7 DECODER CHIP FOR LED DISPLAY Aim: – Tostudy the use of a Decoder Chip (IC 7447) to drive a LED Display. Give the different BCD inputs according to the truth table. E&C Dept. Procedure: - 1. IC 7447 Pin Diagram 3rdSem.Logic Design Lab 2013 10ESL38 Experiment No. Connect the input pinsof the 7-segment LED Display to the respective pins (A3-A0) of the 7447 BCD to 7-Segment decoder driver chip. 7-segment LED Display. 31 VK .

Logic Design Lab 2013 10ESL38 Circuit Diagram: Output Table: BCD inputs segment outputs display D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 7-segment LED Display Schematic 3rdSem. E&C Dept. 32 VK .

B. 3. IC 74147 Pin Diagram 3rdSem. C. 8 PRIORITY ENCODER Aim: – Tostudy the use of a 10-line-to-4-Line Priority Encoder Chip (IC 74147). 33 VK . to the input switches of the trainer kit. Connect Pin 16 of the IC to Vcc and Pin 8 to GND.Logic Design Lab 2013 10ESL38 Experiment No. 7. 4. Verify that the outputs are as shown in the truth table. E&C Dept. Provide the inputs to the encoder chip as shown in the truth table. and note down the results for the respective inputs. 5. 6. Connect the Output pins designated A. Components Required: - IC 74147. D to the LED indicators of the trainer kit. Connect the pins designated Inputs 1 through 9. etc. Observe the outputs on the LED indicators. Procedure: - 1. Make the connections as shown in the circuit diagram. 2.

34 VK . E&C Dept.Logic Design Lab 2013 10ESL38 Truth Table: 1 1 0 X X X X X X X X 2 1 1 0 X X X X X X X 3 1 1 1 0 X X X X X X Decimal Input 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 X 0 1 X X 0 X X X X X X X X X 7 1 1 1 1 1 1 1 0 X X 8 1 1 1 1 1 1 1 1 0 X 9 1 1 1 1 1 1 1 1 1 0 BCD Output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 Decimal Value 0 1 2 3 4 5 6 7 8 9 3rdSem.

2. A. Procedure: 1. Make the connections as shown in the respective circuit diagrams. Check the outputs of the circuits. 9 STUDY OF FLIP-FLOPS Aim: – To study and verify the truth tables for J-K Master Slave Flip Flop.Logic Design Lab 2013 10ESL38 Experiment No. Clear 1 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 35 Clock X X 1 0 0 1 Status Set Reset No Change 0 1 1 0 Reset Set Toggle VK . Apply inputs as shown in the respective truth tables. 3. etc. verify that they match that of the respective truth tables. for each of the flip-flop circuits. T-type and DType Flip-Flops. J-K Master-Slave Flip-Flop Circuit: Truth Table : Preset 0 1 1 1 1 1 3rdSem. E&C Dept. Components Required: - IC 7410. IC 7400.

T-Type Flip-Flop Circuit: Truth Table : Preset 1 1 Clear 1 1 T 0 1 Clock 3rdSem. 36 VK . E&C Dept.Logic Design Lab 2013 10ESL38 B.

37 VK . E&C Dept. D-Type Flip-Flop Circuit: Truth Table: Preset 1 1 Clear 1 1 D 0 1 Clock 0 1 1 0 3rdSem.Logic Design Lab 2013 10ESL38 C.

Logic Design Lab

2013

10ESL38

Experiment No. 10

STUDY OF COUNTERS

Aim: – Realization of 3-bit counters as a sequential circuit and Mod-N counter Design (7476, 7490, 74192, 74193)

Components Required: -

IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7408, IC 7416, IC 7432, etc.

Procedure: A. Counter Circuits using IC 7476 1. Make the connections as shown in the respective circuit diagrams. 2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at QA, QB and QC pins of the 7476 ICs. 3. Verify that the circuit outputs match those indicated by the truth tables. B. Study of Counters IC 74192, IC 74193 1. Connections are made as shown in the respective circuit diagrams, except for the connection from the output of the NAND gate to the load input. 2. The data (0011) = 3 is made available at the data input pins designated A, B, C and D respectively. 3. The Load pin is made LOW so that the data 0011 appears at QD, QC, QB and QA respectively. 4. Now, the output of the NAND gate is connected to the Load input pin. 5. Clock pulses are applied to the “Count Up” pin, and truth table is verified for that condition. 6. Next, the data (1100) =12 (for 12 to 5 counter) is applied at A, B, C and D and the same procedure as explained above, is performed. 7. IC 74192 and IC 74193 have the same pin configurations. 74192 can be configured to count between 0 and 9 in either direction. Starting value can be any number between 0 and 9.

3rdSem, E&C Dept.

38

VK

Logic Design Lab

2013

10ESL38

A. 3-bit Asynchronous Up Counter

Circuit Diagram:

Timing Diagram:

**Truth Table: Clock 0 1 2 3 4 5 6 7 8 9
**

3rdSem, E&C Dept.

QC 0 0 0 0 1 1 1 1 0 0

39

QB 0 0 1 1 0 0 1 1 0 0

QA 0 1 0 1 0 1 0 1 0 1

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Logic Design Lab

2013

10ESL38

B. 3-bit Asynchronous Down Counter

Circuit Diagram:

Timing Diagram:

**Truth Table: Clock 0 1 2 3 4 5 6 7 8 9
**

3rdSem, E&C Dept.

QC 1 1 1 1 0 0 0 0 1 1

40

QB 1 1 0 0 1 1 0 0 1 1

QA 1 0 1 0 1 0 1 0 1 0

VK

41 VK .Logic Design Lab 2013 10ESL38 C. Mod-5 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 1 0 QB 0 0 1 1 0 0 QA 0 1 0 1 0 0 3rdSem. E&C Dept.

Mod-3 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 0 0 QB 0 0 1 0 0 1 QA 0 1 0 0 1 0 3rdSem. 42 VK . E&C Dept.Logic Design Lab 2013 10ESL38 D.

43 VK . 3-bit Synchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 3rdSem. E&C Dept.Logic Design Lab 2013 10ESL38 E.

Logic Design Lab 2013 10ESL38 F. E&C Dept. QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 44 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VK . 4-bit Ripple Counter Circuit: Truth Table: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3rdSem.

E&C Dept. 45 VK .Logic Design Lab 2013 10ESL38 G. Mod-10 Ripple Counter Circuit: Truth Table CLK 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 3rdSem.

46 VK . E&C Dept. Decade Counter (using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 3rdSem.Logic Design Lab 2013 10ESL38 H.

Logic Design Lab 2013 10ESL38 I. 47 VK . E&C Dept. Mod-8 Counter (Using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 0 0 0 0 0 0 0 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 3rdSem.

E&C Dept. 48 VK .Logic Design Lab 2013 10ESL38 J. Presettable counter using IC 74192/IC 74193 to count up from 3 to 8 Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 QD 0 0 0 0 0 1 0 0 QC 0 1 1 1 1 0 0 1 QB 1 0 0 1 1 0 1 0 QA 1 0 1 0 1 0 1 0 Decimal 3 4 5 6 7 8 3 4 3rdSem.

49 VK . Presettable counter using IC 74192/74193 to count down from 5 to 12 Circuit: Implementation of 4-Input OR gate: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 1 1 1 1 1 0 0 QC 1 1 1 0 0 0 0 1 1 1 QB 0 1 1 0 0 1 1 0 0 1 QA 1 0 1 0 1 0 1 0 1 0 Decimal 5 6 7 8 9 10 11 12 5 6 3rdSem. E&C Dept.Logic Design Lab 2013 10ESL38 K.

E&C Dept. SISO.Logic Design Lab 2013 10ESL38 Experiment No. PIPO operations using the same. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to HIGH. etc. Repeat the earlier step to enter data. 7. Apply a clock pulse. 5. QC. 4. and the new data appears at QA. We now observe that the earlier data is shifted from QD to QC. and connect clock input to Pin 9 (Clk 1). we notice that all 4 bits are available at the parallel output pins QA through QD. until all bits are entered one by one. Now. 5. Repeat the earlier step to enter data. 3. Make the connections as shown in the respective circuit diagram. SIPO. We observe that this data appears at pin 10 (QD). Components Required: Procedure: A. Apply a clock pulse. Apply the first data at pin 1 (SD1) and apply one clock pulse. until all bits are entered one by one. We observe that this data appears at pin 13 (QA). Serial In-Parallel Out (Left Shift): 1. B. Serial In-Parallel Out (Right Shift): 1. Apply the first data at pin 5 (D) and apply one clock pulse. 3rdSem. 6. 6. PISO. we notice that all 4 bits are available at the parallel output pins QA (MSB). Enter more bits to see there is a left shifting of bits with each succeeding clock pulse. Make the connections as shown in the respective circuit diagram. 7. Now. apply the second data at D. Shift right. At the end of the 4th clock pulse. 11 STUDY OF SHIFT REGISTERS Aim: – To study IC 74S95. QB. apply the second data at SD1. 4. QD (LSB). and the realization of Shift left. and the new data appears at QD. 3. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse. 50 VK IC 7495. At the end of the 4th clock pulse. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to LOW. . 2. We now observe that the earlier data is shifted from QA to QB. and connect clock input to Pin 8 (Clk 2). 2.

one by one. 2. Connections are made as shown in the SISO circuit diagram. Parallel In-Serial Out Mode: 1. 4. D (pins 2 through 5). the first data bit. Applying yet another clock pulse gets the third data bit „d2‟ at QD. 5. C. Set Mode Control M to HIGH to enable Parallel transfer. apply one clock pulse. Connections are made as shown in the PISO circuit diagram. 51 VK . B. Now set the Mode Control M to LOW. and so on. Apply the 4 data bits as input to pins A. 2. QDrespectively. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW. C. QDrespectively. QC. 3. 5. Now apply the 4-bit data at the parallel input pins A. Serial In-Serial Out Mode: 1. E&C Dept. The data applied at the parallel input pins A. Apply one clock pulse at Clk 2 (Pin 8). 2. 4. At the end of the 4th clock pulse. 5. B. C. QB. with serially applied inputs appearing as serial outputs. and apply clock pulses one by one. Parallel In-Parallel Out Mode: 1. 3rdSem. D appears at the parallel output pins QA. B. We observe now that the IC operates in PISO mode with parallel inputs being transferred to the output side serially. D. 3. D. Note that the 4 bit data at parallel inputs A. QB. QC. C. „d0‟ appears at the output pin QD. and connect clock input to Clk 1(Pin 9). Thus we see the IC 7495 operating in SISO mode. 6. Connections are made as shown in the PIPO mode circuit diagram. to get the second data bit „d1‟ at QD. B. E. Apply another clock pulse.Logic Design Lab 2013 10ESL38 C. Keeping the mode control M on HIGH. The 4 bits are applied at the Serial Input pin (Pin 1). 3. 4. D will appear at the parallel output pins QA. Observe the data coming out in a serial mode at QD. with a clock pulse in between each pair of inputs to load the bits into the IC.

E&C Dept. SIPO MODE (Right Shift) Circuit: Truth Table: Clock 1 2 3 4 Serial I/P 1 0 1 1 QA 1 0 1 1 QB X 1 0 1 QC X X 1 0 QD X X X 1 3rdSem. 52 VK .Logic Design Lab 2013 10ESL38 IC 7495 Pin Diagram: A. SIPO Mode (Left Shift) Circuit: Truth Table: Clock 1 1 Serial I/P 1 0 1 1 QA X X X 1 QB X X 1 0 QC X 1 0 1 QD 1 0 1 1 2 3 4 B.

E&C Dept. 53 VK . SISO Mode Circuit: Truth Table: Clock 1 2 3 4 5 6 7 Serial I/P d0=0 d1=1 d2=1 d3=1 X X X QA QB Q C 0 1 1 1 X X X X 0 1 1 1 X X X X 0 1 1 1 X QD X X X 0=d0 1=d1 1=d2 1=d3 D. PISO Mode Circuit: Truth Table: Mode Clk Parallel I/P A Parallel O/P B C D QA QB QC QD 0 1 1 1 X X X 0 1 X X 1 0 1 X 1 1 0 1 1 0 0 0 1 2 3 4 1 X X X X X X X X X X X X 3rdSem.Logic Design Lab 2013 10ESL38 C.

E&C Dept.Logic Design Lab 2013 10ESL38 E. PIPO Mode Circuit: Truth Table: Clk Parallel I/P Parallel O/P A B C D QA QB QC QD 1 1 0 1 1 1 0 1 1 3rdSem. 54 VK .

3. Apply an initial input (1000) at the A. 4. Select Mode = LOW (0) to switch to serial mode and apply clock pulses. Next. B. A. 55 VK .Logic Design Lab 2013 10ESL38 Experiment No. Make the connections as shown in the respective circuit diagram for the Ring Counter. IC 7404. 2. Components Required: - IC 7495. Ring Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 1 2 3 4 5 6 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 3rdSem. E&C Dept. 12 RING COUNTER /JOHNSON COUNTER Aim: – To design and study the operation of a ring counter and a Johnson Counter. 5. D pins respectively. Procedure: 1. C. record the observations and verify that they match the expected outputs from the truth table. Keep Select Mode = HIGH (1) and apply one clock pulse. etc. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation. 6. Observe the output after each clock pulse.

56 VK . Johnson Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 3rdSem. E&C Dept.Logic Design Lab 2013 10ESL38 B.

and Karnaugh maps are drawn in order to obtain a simplified Boolean expression for the circuit. The given sequence length S = 15 Therefore. etc. and clock pulses are fed through Clk 1 (pin 9). Mode M is set to LOW (0). 5. we need to use 5 flip-flops. Components Required: Theory: - IC 7495. Procedure:1. Connections are made as shown in the circuit diagram. 13 SEQUENCE GENERATOR Aim: – To design and study the operation of a Sequence Generator. in order to satisfy the condition . 2. If the sequence is not realizable by 4 flip-flops. and checked against the expected values from the truth table. Circuit: 3rdSem. it is necessary to use at least„N‟ number of Flip-flops. In order to generate a sequence of length „S‟. N = 4 Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. E&C Dept. 57 VK . Truth table is constructed for the given sequence. IC 7486. Clock pulses are applied at CLK 1 and the output values are noted. and so on.Logic Design Lab 2013 10ESL38 Experiment No. 4. The functioning of the circuit as a sequence generator is verified. 3.

Logic Design Lab 2013 10ESL38 Truth Table: Karnaugh Map: Map Value 15 7 3 1 8 4 2 9 12 6 11 5 10 13 14 O/p Clock QA QB QC QD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 3rdSem. E&C Dept. 58 VK .

12. 11.: IA Marks : 25 Exam Hours : 03 Exam Marks : 50 NOTE: Use discrete components to test and verify the logic gates. 59 VK . SISO.scribd. E&C Dept.Logic Design Lab 2013 10ESL38 Syllabus LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code :10ESL38 Hrs/ Week : 03 Total Hrs. 9. 13. 74139 for arithmetic circuits and code converter. http://www. (i)Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versausing 7483 chip.com/doc/62491691/Logic-Design-Lab-Manual-10ESL38-3rd-sem-2011 3rdSem. SIPO. 10. Shift right. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476. realization of Boolean expressions using logic gates/Universal gates.74193). Use of IC 74147 as Priority encoder. Use of Decoder chip to drive LED display. 4. 3. PIPO operations using 74S95. PISO. MUX/DEMUX – use of 74153. 7490. Simplification. Truth table verification of Flip-Flops: (i) (ii) (iii) JK Master slave T type D type. Shift left. Wiring and testing Ring counter/Johnson counter. 1. 6. Wiring and testing of Sequence generator. 2. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 8. 7. LabView can be used for designing the gates along with the above. Realization of One/Two bit comparator and study of 7485 magnitude comparator. 74192. Realization of Binary to Gray code conversion and vice versa 5.

List the applications of EX-OR and EX~NOR gates 11. Define LSI. 47. Give the block diagram of parallel adders 24. in 74LS00? 48. What is a code converter? 35. What is a shift register? 40. Realize logic gates using NAND and NOR gates only 9. What does LS stand for. Give the applications of johnson and ring counters 42. 2. What is modulus of a number? 39. What is race around condition? 22. How do you eliminate race around condition 23. Explain how transistor can be used as NOT gate 7. Explain AND and OR gate using diodes 8. Define multiplexer/ data selector 28. E&C Dept. Compare demux and decoder 33. What is a encoder and decoder 31. Give the block diagram of sequential circuits 18. State De-morgans theorem 5.Logic Design Lab 2013 10ESL38 Possible Viva Questions 1. 4. What is minterm and maxterm? 26. 49. What is a truth table? 12. Give examples 16. Explain how it can be used as EX-3 to BCD conversion and vice versa 27. Give the applications of mux and demux 30. MSI . Give examples for SOP and POS 6. What is an up counter and down counter? 43. What is an excitation table/functional table 20. What are BCD Give their applications or uses 25. What is a priority encoder? 34. What is a ripple counter? 38. Explain how a shift register can be used as ring and johnson counter 41. Give the applications of combinational and sequential circuits 17. 46. SSI 10. Differentiate between flip flop and latch 21. 60 VK . Define flip flop 19. What are basic gates? 3. Differentiate between half adder and half subtractor 14. Why NAND and NOR gates are called as universal gates. List the types of LCD's and LED's. What is common cathode and common anode LED? 44. 45. What is a Demultiplexer? 29. Explain the working of 7483 adder chip. Which is the fastest logic? 3rdSem. Differentiate between combinational and sequential circuits. What is a static and a dynamic display. What is a full adder? 15. Compare synchronous and asynchronous counters 37. What is LCD and LED. What are counters? Give their applications 36. Define a logic gate. What is a half adder? 13. Compare mux and encoder 32. Mention the different logic families.

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