Basic IBM Mainframe Assembly Language Programming

by

Kevin C. Ó Kane

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Copyright © 2011 by Kevin C. Ó Kane. All rights reserved. The author may be contacted at: kc.okane@gmail.com Department of Computer Science The University of Northern Iowa Cedar Falls, Iowa 50614-0507 http://www.omahadave.com

Graphics and production design by the Threadsafe Publishing & Railway Maintenance Co. Hyannis, Nebraska

Revision: 1.01 June 20, 2011 Text formatted using Open Office 3.3.0

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Table of Contents
1 Preface ................................................................................................................9 2 Basic Numbering Systems................................................................................11 2.1 Binary..............................................................................................................11 2.2 Hexadecimal....................................................................................................11 3 Assembly Language Overview........................................................................15 3.1 Instruction Set Architecture.............................................................................15 3.2 Assembler........................................................................................................16
3.2.1 Assembly Language Statements...........................................................................17

3.3 Line Format and Naming.................................................................................18 3.4 Program Structure............................................................................................18 4 Z390 Emulator and Hello World....................................................................21 4.1 The z390 Portable Mainframe Project.............................................................21 4.2 Running the Emulator......................................................................................21 4.3 Hello World.....................................................................................................22 4.4 Running Hello World......................................................................................23 4.5 Examining Hello.prn.......................................................................................24 4.6 More Basic Assembly Language Examples ...................................................25 5 Basic Instruction Formats...............................................................................27 5.1 Operands..........................................................................................................27 5.2 Operand Notation............................................................................................27 5.3 Operand Semantics..........................................................................................28 5.4 Operand Formats.............................................................................................28
5.4.1 RR Format............................................................................................................28 5.4.2 RX Format............................................................................................................28 5.4.3 RS Format............................................................................................................29 5.4.4 SI Format..............................................................................................................29 5.4.5 SS Format.............................................................................................................29 5.4.5.1 One 8 Bit Length Field..................................................................................29 5.4.5.2 Two 4 Bit Length Fields................................................................................30

6 Basic Addressing...............................................................................................31 6.1 Explicit Addressing.........................................................................................31 6.2 Symbolic Addressing.......................................................................................33 6.3 Machine Language Formats............................................................................35
6.3.1 RR Machine Language Format.............................................................................35 6.3.2 RX Machine Language Format.............................................................................36 6.3.3 RS Machine Language Format.............................................................................37 6.3.4 SI Machine Language Format...............................................................................38 6.3.5 SS Machine Language Format..............................................................................39

7 Program Status Word (PSW)..........................................................................41 7.1 Layout..............................................................................................................41 7.2 Addressing modes...........................................................................................41
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..................................................................................1....................1 Packed Decimal and Zoned Decimal Format Data.......................4 Data Addressing Alternatives..........................................................2 Branch and Save ......................................................................BXLE.3 Nomenclature..72 13.................42 8 Flow of Control & Branch Instructions.............................................2 Binary Integers and 2s Complement........................... BXH........................1 Arithmetic Data............75 13.........43 8.2.............................................1...........2 Halfword Instructions........................BAS and BASR................1 Declare Constant and Declare Storage (DC and DS).................................42 7....................................................6 Instruction Addressing.....................BCT (RX) and BCTR (RR)..........79 13...............79 13.....................................................55 9..............2 Analyzing the PRN File....84 14............................4 Threshold Binary Values.................................................................................................................................1 Program to Add Numbers..4 Overflows...................................................................................................................................3.............................3 Condition Codes After Binary Operations.................................................................................................................................................................66 12............................ High ............1 Conditional Branching (BC.........47 8..............49 9 Data Types......................................65 12..................................83 14...............6 Using Extended Mnemonics........................................57 10.....................................................................5 More Addressing Alternatives..............................................................................3 Looping Branch Instructions...................................................................................................................................83 14..6 Multiply (M....... BCR)............................................................66 12.....................46 8.......1 Branch Index Low..................................................................47 8..1 Subtraction...............47 8..................52 9..........................................................57 10..........3 XDECO/XDECI.46 8...............83 14.. ALR..67 13 Integer Arithmetic ..........47 8........................1........................................................................................................................................................................84 4 ....................2 Branch and Link Instructions....................................61 11..7. BRASL...2 XDUMP....41 7...1..........................3......................................69 13.....................3 Branch Relative and Save .......................................2................................61 11....59 11 Linkage..............BRAS....................................51 9.41 7....43 8..................................................................................................................................69 13...........................................1 Input / Output using XREAD and XPRNT...................4 XHEXO/XHEXI................................................................................2 Literals ...............................................................2 Branch on Count ..............................2..........................................1 BAL and BALR .............................Branch and Link .....65 12....83 14.......... MR)......4 Program Mask.......................51 9. Equal.......................................................................5 Problem / Supervisor State Bit..............................................................55 10 Data Declarations......3 Debugging (XDUMP)...........................................................3 Condition Code................................................................................. SL..1 Linkage Registers............................................................................................ SLR)......................................51 9.......................83 14............................................5 Unsigned Arithmetic (AL......................80 14 Other Binary Arithmetic Instructions...............61 12 Assist Macro Input/Output...............................................................................................................2 Save Area...

.....3 Translate (TR) and Translate and Test (TRT)... NC)........................7 Load Positive (LPR).....6.................................. Packed and Binary .............2......................................................................................................103 18...........88 15................105 19.103 19 Multiple Base Registers..................................4 Divide Packed (DP).....................................100 17............................................3 Compare Logical Characters (CLC).................1 Boolean Instructions........2..................6 Load and Test (LTR).................................87 15............................................................ SLA..................................... Subtract............................................................95 16.............................................................................................................89 15.95 16........................................................................................1.............................2 Character Long Instructions..........87 15....105 20 System Macro Input/Output ....................95 16....90 16 Miscellaneous Register Operations............................... XI........................95 16............................................................................................................1 Base Register Addressing ..........................................................................6....................4 Test Under Mask (TM) .............1...................................101 18....99 17............... Zero and Add Positive (AP............................3 Move Zones (MVZ)............95 16......................3 Exclusive OR (X.................................... DR)...............90 15................89 15.........................1................. OI............................................14...................103 18........................................................95 16......................................... NI.......................2 Move Immediate (MVI)............................98 17.....3.......................1........................................................................................................... SP.....111 5 ...............1..........................................................97 17....................................1 Load (L)...........1 UNPACK (UNPK).6 Miscellaneous Decimal Related Instructions...................5 Store Multiple (STM).......................................................2 Add....................................................................................5 EDIT (ED)..........................103 18.......... XR.............................................................................1 Basic Character Instructions.....97 17..............................................................................................................................................2 Move Character Long (MVCL).............................................................................100 17................................................................3 Shift...................................................................................2 Load (LR).............97 17.....1 Compare Logical Character Long (CLCL)...........1 Compare Logical Immediate (CLI)...........109 21 Converting Between Zoned............... SLL.................................................. XC)..........1 Logical (SRL.............101 18 Decimal Arithmetic..........................................8 Load Negative (LNR).....6.............................102 18..........2 Arithmetic (SRA........ OR............ SRDL.....89 15.. NR.................................1 Moving Characters (MVC)................................................................................3 Store (ST).................2 Move Numerics (MVN)...........................1..................2 OR (O.............................................. ZAP)..101 18......................................................3.........87 15................1.....................4 Load Multiple (LM).................85 15 Character Instructions....................................................................................................3 Multiply Packed (MP).............................................................................87 15.96 17 Bit Operations.....7 Divide (D.....................1 PACK..... OC)..............3.........97 17..................................................................................................102 18........... SRDA......................................99 17...........................96 16.98 17............................................................................................................................ SLDL) ....................102 18........ SLDA) ...............101 18..............1 AND (N.....................................2 Complement LCR ...5 Test and Set (TS) .........96 16.......

.............................................4 Bubble Sort a Table of Numbers...117 22......22 Programming Examples............120 22.....................................................................2 Random Numbers.........................................................................................................................................3 Convert Infix to Suffix ..............6 Print a String in Hexadecimal..................................................117 22...5 Search for Prime Numbers....................................................................................135 6 ....................125 22................................................7 Word Count Program.............................................................................126 22.................118 22...1 Console Input/Output....128 23 General Instruction Set.............................122 22.....................................................................................

....84 Table 20 General Instructions............122 Figure 51 Bubble Sort........................................77 Figure 33 ADD1.......................................53 Table 13 Decimal value of a binary number..106 Figure 43 QSAM Input/Output...................................124 Figure 52 Search for Prime Numbers................12 Table 3 Conversion from Hex to Decimal...................MLC ....45 Table 9 Extended mnemonics......65 Figure 23 ADD..MLC Step 4................119 Figure 50 Convert Infix to Suffix..........................................137 Index of Tables Table 1 Numbering Systems.......................69 Figure 24 ADD........37 Figure 14 SI Machine Language Format................................................................................................................................................53 Table 14 Binary nomenclature.........................................................70 Figure 26 ADD....................36 Figure 12 RX Machine Language Format.24 Figure 4 Macro expansion.........................................................................MLC Step 2................................................................61 Table 17 Save area........A Hollerith/IBM Punched Card................................................13 Table 4 Decimal to Hex Conversion.........................................PRN.....Index of Figures Figure 1 ..........................126 Figure 53 Print Hex Equivalent...............76 Figure 32 ..35 Figure 11 RR Machine Language Format.....39 Figure 16 BC example....................................................72 Figure 30 ADD...............................135 7 .............................25 Figure 5 Example program............................34 Figure 10 ......................................36 Figure 13 RS Machine Language Format...........................MLC Step 1..........50 Figure 19 Example DS/DC statements................116 Figure 47 Console I/O using WTO/WTOR............MLC Step 3...MLC Step 5................58 Table 16 Linkage registers.........44 Figure 17 BXLE loop example.................................................................................118 Figure 48 Random Numbers in C.129 Figure 54 Dictionary Program......................................................83 Table 19 CC after logical add/subtract.....59 Figure 21 SUBENTRY code........62 Figure 22 XREAD example..........................................113 Figure 45 Negative Decimal Arithmetic............RR Examples..........................Alternative 2..............................................................................................................................................38 Figure 15 SS Machine Language Format.....111 Figure 44 Decimal Arithmetic............119 Figure 49 Random Number Generator...44 Table 7 Decimal mask settings.........................................51 Table 11 Example packed decimal numbers........32 Figure 8 ............81 Figure 36 MVC Examples............................87 Figure 37 MVI Examples.....MLC Step 5..........................................................73 Figure 31 Add program exposed...........................88 Figure 39 TRT Table with ORG....81 Figure 35 Loop example.......................................................44 Table 6 Mask settings after a signed add....93 Figure 42 Multiple Base Registers...............................MLC Step 5..................................80 Figure 34 ADD2................................................................................88 Figure 38 CLC Examples .......................Alternative 1..........................62 Table 18 Conditions Codes..Explicit addressing.26 Figure 6 ..........91 Figure 40 TRT Example..132 Figure 55 Over-Extended Instructions (humor)...............56 Table 15 DS/DC Data Types.........................71 Figure 27 ADD...............49 Figure 18 BCT loop example...31 Figure 7 Memory operand.....52 Table 12 Powers of two.....MLC .........58 Figure 20 Literals.............................115 Figure 46 Example Execution.............................................................................Example symbolic addressing..........................................................................72 Figure 29 ADD................................................Example memory addressing.....45 Table 8 Decimal mask equivalents......46 Table 10 Numeric data types......................................................32 Figure 9 ...............23 Figure 3 Assemble and run Hello World.........................................71 Figure 28 ADD...................................70 Figure 25 ADD............................................13 Table 5 Condition Code after signed Add.............11 Table 2 Hex to Decimal Conversion..92 Figure 41 TRT Verifying Input....................Dump format..............................................19 Figure 2 Hello World..

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1 Preface The purposes of this book are: 1. Many computer architectures have come and gone in the past 50 years and only a few designs remain to this day. enterprise level configurations. All models of the IBM mainframe. Linux and virtual hosting applications. cloud computing. These are referred to as architecture levels. along with the portable. Similarly. The current series of IBM mainframes (System z10) had its origins in the 1964 with the introduction of the IBM 360 Series of machines. abstract RISC based architectures. the IBM mainframe. and ARCHLVL3 (System z10 machines). for the most part. as mainframe sales have grown rapidly and it is being increasingly deployed in large. the question of which assembly language architecture to teach in an introductory course in computer organization has arisen. even the most recent. 2. to give the reader a basic understanding of the IBM mainframe architecture from the perspective of the instruction set architecture and to serve as an assembly language text for introductory college courses in computer organization. 9 . open sourced. In recent years. This text seeks to address this need by giving the reader a basic understanding of the underlying mainframe architecture from the level of the instruction set. However. In many cases this is solved by the use of simulators for non-existent. few are aware of the other widely used architecture. This text. This book will deal mainly with the basic architecture for simplicity concentrating mainly on the original instruction formats. Simultaneously. both 64 bit addressing and 64 bit data are supported. These reflect the additions to the original design which are. are fully backward compatible with the earliest of the 360 series. ARCHLVL2 (zSeries and System z9 machines). as the programmers who wrote the billions of lines of mainframe assembly code since the introduction of the 360 in 1964 begin to retire. as the x86 architecture has become an increasingly more complex collection of exceptions and special cases. consistent with the original intent. At present. mission critical applications. While most computer users are familiar with the ubiquitous Intel microprocessor line. there are three architecture levels named: ARCHLVL1 (ESA 390 systems). additional facilities and instructions were added. The original architecture was based on a 24 bit address (16 MB address space) and 32 bit data. however. the demand for programmers to maintain and develop new code is growing. however. This was a family of computers designed to meet a wide range of applications both scientific and commercial. The system was conceived as a series of compatible machines ranging from small basic machines to large. In its latest models. Java based z390 emulator. seeks to provide a real world alternative. with each new generation.

Document Number: SA22-7832-03 (05/04/04) presently to be found at: http://publibz. sixteen bit access registers.ibm.The z/Architecture was introduced in 2000 and is represented by machines in the z9 and z10 families. and sixteen 64/32 bit control registers. sixteen 64 bit floating point registers. Memory addressing is implemented as either 24. 31 or 64 bits although much legacy programming is in 24 bit mode.org/ Which corresponds to the definition as found in the IBM z/Architecture Principles of Operation. In this book will deal mainly with 31 bit addressing and the z390 framework in order to be compatible with the free z390 emulator and assembler: http://www.com/cgi-bin/ bookmgr_OS390/BOOKS/DZ9ZR003/CCONTENTS 10 .boulder. It is a 64 bit CISC (complex instruction set computer) architecture with sixteen 64/32 bit general purpose registers.z390.

Each binary number is a sum of a series of values of powers of two.see below) numbers and the corresponding sum of the powers of 2. the binary series which is equivalent to the decimal number 10 is: 1*23 (810) + 0*22 (410) + 1*21 (210) + 0*20 (110) or. For example.2 Hexadecimal Internally. 10102 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F 3 3 2 Power of 2 20 21 21+20 22 22+20 22+21 2 +21+20 23 2 +20 23+21 23+21+20 23+22 23+22+20 23+22+21 2 +22+21+20 Table 1 Numbering Systems 2. stated as a single number. reading from right to left. Representing the contents of bytes as binary numbers yields 11 . uses an internal binary representation for numbers. decimal. characters. hexadecimal (base 16 . most modern computer memories are organized as a collection of 8 bit bytes. When writing a number. instructions.1 Binary The IBM mainframe.2 Basic Numbering Systems 2. represents a higher power of two as shown in Table 1. each position. Any decimal integer can be represented exactly by a corresponding binary number. as is the case with all other modern digital computers. This table shows the equivalence between the first 16 binary. pointers and so forth. Binary numbering consist of only two digits: 0 and 1.

if you have a binary number such as: 000 0001 1010 1011 0010 0011 0111 1000 Using the values from Table 1. we use the upper (or lower) case letters A. It gives. D. and F. for each hex digit position (up to an eight digit hex number). B. E. 12 . Since 16 is itself a power of two. representing the values 1010 through 1510. For the first 10 digits. For digits above nine. So. it can be represented in hex as: 000 0001 1010 1011 0010 0011 0111 1000 0 1 A B 2 3 7 8 Conversion from a hexadecimal (hex) number to its equivalent decimal notation. However. if you have the hexadecimal number such as: 01 AB 23 78. we can represent the content of a byte in base 16. When you want the decimal equivalent of a hex number. conversion between base 16 and base 2 and vice versa is trivial. requires more work because there is a fundamental change in base. To do this.inconveniently long sequences of 1s and 0s. however. it can be converted to decimal by adding the decimal equivalent contributions of each of the hex digits as shown in Table 3. Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal Equivalent by Digit Position 0 268435456 536870912 805306368 1073741824 1342177280 1610612736 1879048192 2147483648 2415919104 2684354560 2952790016 3221225472 3489660928 3758096384 4026531840 8 0 16777216 33554432 50331648 67108864 83886080 100663296 117440512 134217728 150994944 167772160 184549376 201326592 218103808 234881024 251658240 7 0 1048576 2097152 3145728 4194304 5242880 6291456 7340032 8388608 9437184 10485760 11534336 12582912 13631488 14680064 15728640 6 0 65536 131072 196608 262144 327680 393216 458752 524288 589824 655360 720896 786432 851968 917504 983040 5 0 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 4 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 Position Table 2 Hex to Decimal Conversion Each four bit binary number can be immediately converted to its hexadecimal equivalent by simple substitution. you need to add the contribution of each hex digit. the contribution of that digit as expressed in decimal. noting that a byte consists of two 4 bit fields. Thus. In base 16 we need 16 symbols to represent the digits of the numbering system (the equivalent of 010 through 1510). we use the same symbols as the decimal numbering system (0 through 9). a table such as that in Table 2 is useful. C.

The corresponding hex digit is retained as part of the answer. The easiest. insert a zero in the skipped position. 0 1 A B 2 3 7 8 0 16777216 10485760 720896 8192 768 112 8 27992184 Position 8 Position 7 Position 6 Position 5 Position 4 Position 3 Position 2 Position 1 Decimal equivalent of 01AB2378 Table 3 Conversion from Hex to Decimal Of course. For example. is to successively find the largest decimal value in the table and subtract it from your decimal number. if you have the decimal number: 123456789. If you skip a hex position in the process. another method to convert between binary. 123456789 6016277 773397 52501 3349 21 5 Subtract 117440512 hex digit 7 position 7 Subtract 5242880 hex digit 5 position 6 Subtract 720896 hex digit B position 5 Subtract 49152 hex digit C position 4 Subtract 3328 Hex digit D position 3 Subtract 16 hex digit 1 position 2 Subtract 5 hex digit 5 position 1 Result: 07 5B CD 15 Table 4 Decimal to Hex Conversion 13 . this can be rendered in hex as shown in Table 4. decimal and hexadecimal is to use the programming mode of a calculator such as that which comes with Ubuntu.Conversion from decimal to hex can be done in several ways. if you have Table 2.

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These are the binary codes between 00002 (010) and 11112 (1510). in newer implementations. The general purpose registers are addressed by a number between 0 and 15. As a result. we will work only with 32 bits. two bytes are used for some opcodes and the total number of permissible opcodes is now very much larger than the original 256. There are two classes of registers: general purpose registers and floating point registers. Each operand specification indicates if the operand is in memory. they were 32 bits in length but on more recent machines they are 64 bits long. the basic architecture uses an addressing scheme known as base/displacement addressing. in a register or a constant. each instruction is either 2. The first byte is always the opcode. there were six basic instruction formats and these are still the basis of many of the instructions in use today as well as the model for many of the newer formats. In actual practice. 20 bit signed displacements are possible). The 12 bit displacements are always treated as positive numbers. not all possible codes were originally used. The opcode is a numeric value that indicates which instruction is to be executed. However. displacements were always 12 bit unsigned numbers (in newer systems. For the most part. If an operand is in memory. the maximum number of unique opcodes is 256 (2 raised to the eighth power). Registers are very high speed memory locations located in the CPU. a register operand is always specified in field of 4 bits. There are 16 general purpose registers. Some instructions work only on the lower 32 of these bits while others work on all 64. In base/displacement addressing.1 Instruction Set Architecture In the original IBM S/360 architecture. Following the opcode is one or more (usually two) operand specifications. These are used mainly for integer calculations and for addressing. the address of the operand in memory is calculated by adding the contents of a register with a constant called a displacement. Originally. Originally.3 Assembly Language Overview 3. They can range from 010 (0000 0000 00002 or 00016) to 409510 (1111 1111 11112 or FFF16). since there are 8 bits in a byte. A program in memory consists of a series of instructions coded in binary. In the basic architecture. 4 or 6 bytes long. In all instructions. 15 . The floating point registers are used to perform floating point calculations and are not discussed in this book. Each instruction consists of an opcode (operation code) which tells the CPU which instruction to execute followed by one or more operands which tell the CPU what data the instruction works upon.

Since operand addresses are calculated relative to the base register. a different value will be loaded into the base register and the operands will be likewise relocated. we might be able to specify a more efficient 16 . when we write a program in assembly language. If a program used actual memory address constants to specify operand addresses. Instead of coding an Add instruction as 5A16 we use the mnemonic symbol A. This would make it very difficult for a computer to run multiple programs at the same time because programs might compete for the same memory locations. it would always need to be loaded at the same place in memory. That is. The end result is a binary coding of our program but with a lot less effort on our part. However. the ability to place a program anywhere in memory. The assembler translates our symbolic representation into binary. When we write in assembly language. when a program is loaded into memory. we use symbols for the instructions. people soon developed a class of programs known as assemblers whose purpose it was to allow programmers to write in a symbolic language and leave the job of translating the symbolic code into binary to the assembler. they will be correct if the base register is correct. Compare this to a line of code written in a language such as C or C++ where a single line of code may require many instructions to be executed. In the very earliest days of computing. some instructions have what is called an index register. Thus. Any register can be used as a base register except register zero. To improve productivity. In addition to base/displacement. it means there is no index register. Register zero never participates in address arithmetic. this was normally the case. Instead of coding a base and displacement. When we write in a high level language the compiler selects the instructions to execute. Index registers are useful for array manipulation where the base/displacement points to the start of an array and the index register is used to give an offset from this point into the array. If the program is placed somewhere else in memory. Thus.The purpose of base/displacement addressing is to achieve program relocatability. Base/displacement addressing makes it possible to load a program anywhere in memory. in many cases. However. if register zero is specified as an index register. each line usually consists of a single instruction to be executed. The assembler calculates and inserts the correct base and displacement. 3. the base register is loaded with an absolute memory address usually near the starting point of the program. we say that assembly language is a low level language and C/C++ is a high level language.2 Assembler It is technically possible (although very tedious) to write programs in binary or hexadecimal. however. For this reason. we use labels attached to data areas in our program. Memory addresses are all calculated relative to the contents of the base register. The contents of the index register are added along with the contents of the base register and the displacement to calculate an address.

Rather than write the code new each time. These are statements. Assembler directives. To build a final executable module we employ a program known as the link editor or loader which resolves these and either creates an executable on disk or loads the executable into memory. define one symbol to be the equivalent of another. The main assembler directive we will use are: A. they do not normally result the generation of code or data. the number of lines of code a programmer does per day is invariant with regard to language used. 17 .sequence of instructions. On the other hand. .declare constant). These are statements that inform or direct the assembler. F. add the contents of one register to another).1 Assembly Language Statements There are basically four classes of statements in an assembly language program: 1. This module is nearly executable lacking only library routines and internal address linkages (for example. G. one per line. we insert the macros containing the code into our programs. 3. end of the source module. B.start or continue control section. each data allocation statement results in data areas being incorporated into the run time module Note: it is possible. 4. USING END EQU LTORG CSECT ORG PRINT . which will be translated into machine language for execution at run time. These are statements that tell the assembler to reserve memory in the run time module for data. usually designating data in memory or registers upon which the instruction operates (for example. While these statements affect the way in which your machine language program is generated. for that matter) is a binary object module consisting of instructions and data.placement of literal pool.declare storage) or initialized (DC statement .2. D. The data may be uninitialized (DS statement .) 3. Macros statements. Macros are small. disk resident code modules that contain segments of frequently used code. Data Allocation statements (DS/DC). 2. Each instruction statement results in machine code being generated in the run time module. resolution of subroutine call addresses). in rare cases. (Note: an executable module on disk usually still requires some final adjustments as it is loaded into memory for execution. not generate any data as we will see in Figure 54 on page 132. So.designate a base register. high level languages increase programmer productivity but low level languages can increase program efficiency. E. This is not common. All instructions have one or more operands.assembler print options. a programmer working in a high level language will probably accomplish more per day than someone working in a low level language. . generally speaking. C. The output of the assembler (or a compiler. Instruction statements. For the most part. Thus. however. adjust location counter. that a DS or DC statement may. in fact. .

8. 5. Blank lines are ignored but are part of the overall line count. # or @. Labels begin in column one and are from one to eight characters in length The first character of a label is either a letter in the range A through Z. Characters after the first character may be any of the above as well as digits in the range 0 through 9. Introductory assembler directives and register renaming macros such as: PRINT NOGEN EQUREGS The assembler directive (PRINT) determines what information the 18 . After the operands and one blank. 2. $. If column 1 one is an asterisk. Internally. 3.From the program level. if any. data allocation statements and assembler directives but they may also contain statements in the macro language itself. assembly language programs were punched on 80 column cards and followed a format consistent with that media. Operands. If an operand is so long that it would extend beyond column 71.4 Program Structure The basic structure of a program will be: 1. macros may be a combination of instructions. macros look very much like instructions. 6.3 Line Format and Naming Historically. 9. The macro preprocessor inserts the macros into your program and executes and macro commands written in the macro preprocessor language. begin in column sixteen and may not include embedded blanks except within quoted strings. 4. There may be at most two continuation cards. place a character (usually an X) in column 72 and continue the operand on column sixteen of the next line. the remainder of the line is a comment. 3. Although there may have been some relaxation in the format in recent years. Comments may not extend beyond column 71. most assembly programmers follow the original format to this day: 1. The mnemonic (short abbreviation) for the operation code or assembly directive begins in column ten. comments may be written. it is first read by the macro preprocessor. Before your program is processed by the assembler. 10. 3. 7.

R3. 3. character strings. This macro tells the assembler that if you use symbols such as R0. pointers.. R2. You may also specify initial values for data areas as well. The program code appears at this point followed by the exit macro SUBEXIT which returns to the calling program. 4. R1..assembler will show in its printout of your program. Your program may have more than one instance of SUBEXIT. that you mean 0. Usually the data area consists of multiple labeled statements declaring what would be called variables in a high level languages. An entry linkage macro: SUBENTRY This macro establishes your base register and linkage to the calling program and performs a number of tedious housekeeping functions. The EQUREGS is the name of a macro on disk whose contents will be inserted at this point. Each of these statements causes the assembler to reserve a specific number of bytes in the run-time module. The data area.. Most programmers prefer to use R1. Unless you specifically tell the assembler that R1 means 1. 1. 2. 3. Figure 1 . These can include binary variable. Macros are small. you can't do this.. 2. when specifying registers. etc. . frequently used segments of code stored on disk for re-use. and others. .A Hollerith/IBM Punched Card 19 . In an assembly language program you tell the assembler how much data to reserve for program use.

20 .

quickly hit cancel and start again. assemble. download the most recent setup. At the end of the values for the Path variable. scroll down to the Path line. Linux..Enable z390 and zcobol users to compile. then click the Edit button. If you do. Note: if you have a 64 bit version of Windows. In this section we show how to run the emulator in a command prompt window. The emulator can be run either in a graphical user window or from a command prompt. To install the software.z390.exe file contained therein. you will be replacing the entire contents . and other platforms supporting the J2SE runtime. GPL project to ".do not do this. The results are the same but the examples used in this book were done in command prompt mode.C:\"Program Files"\"Automated Software Tools"\z390.2 Running the Emulator There are several ways to run the emulator. Click OK and close the windows. 4.4 Z390 Emulator and Hello World 4.1 The z390 Portable Mainframe Project The z390 portable mainframe macro assembler and emulator project is a Java based. The purpose of this is so you can execute the emulator from any directory. the emulator may have been installed in "Program Files (x86)" 21 .org/ where the Java code for the project can be found. add the following: .. Go to: Start | Settings | System | Advanced Settings and click on the Environment Variables button.. You should consult the documentation for details. The examples in this text were developed using this package. and execute mainframe COBOL and assembler problem state programs with minimum source code changes using Windows. click it. In the lower window." (from the web site): http://www. link. This assumes that you have installed the z390 emulator in the directory noted.zip. it may be all highlighted and this means that if you type something.. Be careful. First. not just the one containing the actual code.. You will see the current contents of the Path environment variable. you need to add some information to your systems program search path. unzip and execute the setup.

Be careful that you type it exactly. To create a directory. You probably want this to be at least double the screen height. type cmd into the run box. Normally this is done with macros. Macros are code segments stored on a system library designed to perform common. You may want to leave this window open in the event you need to make corrections.3 Hello World Now it's time to write the usual Hello World program as shown in Figure 2. In the command window. start notepad with the command: notepad hello. The buffer width should be the same as the screen width. A command window should appear. Enter the directory with the command: cd asmdir 4. the first few lines of an assembly program deal with assembler directives and linkage: connecting your program with the program that called it. establishing a base register for your program and creating a save area. width and position. click OK. Right click the top bar and the click Properties. Close does not count.mlc A window will open in which you can type your program and save it when done. In Properties. type: mkdir asmdir where asmdir is the name you chose. You may also want to adjust the colors if you prefer something other than white text on a black background. You will probably want to tailor this window so it is larger than its default size. Macros look like machine instructions but are directives to the assembler to insert and process code elements into you program. This involves saving the calling program's registers so they can be restored at exit. When finished. locate your system's command prompt icon. including blanks. You will probably want to create a directory in which you will place your assembly language programs. The Screen Buffer Size Height is the number of lines to remember at any given time. This can usually be found in Start | Programs | Accessories | Command Prompt Alternatively. Next. As the macro is inserted into your program.and you will need to add (x86) to the "Program Files" in the above. repetitive tasks and to simplify program development. 22 . The prompt in the command window should identify the directory path to your default user directory. click Layout and adjust the window size. Structurally. A typical macro can be from 3 to hundreds of lines long.

John R. Mashey at the Computer Science Department of The Pennsylvania State University. The program in Figure 2 writes the phrase Hello World returns to the operating system. save area and sets register 13 to be your initial base register. 4.4 Running Hello World Once you have typed and saved the program.mlc 23 . The directive PRINT NOGEN is a note to the assembler. EQUREGS. XPRNT prints data to the default output device (the screen for most users). Return is accomplished by the macro SUBEXIT. 2. 3 and so forth. The assembler calculates the base and displacement necessary to address the label MSG. It tells the assembler to display the names of the macros but not show the macro expansion itself. assemble and execute it by typing the command: assist hello. 1 2 HELLO 3 4 5 6 MSG 7 PRINT NOGEN SUBENTRY EQUREGS XPRNT MSG. the address of the field to be printed is given as MSG and the length as L'MSG. L'MSG is assembler short hand that evaluates to the value of the length attribute of the label after the L' figure which. usually the length of the memory reserved in the case of DS and DC statements). It takes two arguments: the address of the data field to be printed and its length. The purpose of EQUREGS is to make codes such as R1 and so forth the equivalent of their number part. the assembler will show the contents of the of the macro expansion (usually not very interesting). is 12 (note: all labels have a length attribute.L'MSG SUBEXIT DC C'Hello World!' END Figure 2 Hello World Another macro. In Figure 2. We will use several of these in the examples in this text. causes the assembler to accept notation such as R1. The resulting code is referred to as the macro expansion.it may be tailored or altered by the macro preprocessor. If omitted. Most programmers prefer to refer to the general purpose registers as a number preceded by the letter R however this notation is not accepted by the assembler. R3 and so forth as the equivalent of 1. part of the Assist package of macros originally developed by Dr. They provide simplified access to common tasks and are useful for novice programmers. The z390 emulator provides a macro called SUBENTRY that establishes your program's linkage. The program's output is done by the macro XPRNT. R2. in this case.

MLC C:\user>echo off 18:13:22 hello MZ390 START USING z390 V1.6.5. examine the area in the center of the display which will look something like Figure 4.prn (examined below) is the main assembler listing of your program. Further details on the meaning of this code will be covered below.prn file (usually referred to as the listing). For each macro.01b ON J2SE 1. lines 15 through 30 are due to the EQUREGS macro and lines 34 through 38 are the result of the SUBEXIT macro.mlc. The file hello. contains the translation of the program into binary and other information about the 24 .prn with the command: more hello.01b ON J2SE 1. Now modify the program and remove the PRINT NOGEN line and repeat the assist command.prn Look in the file hello. The assist command is the name of a Windows batch file in the emulator directory which runs the emulator with the Assist macro support feature enabled and then executes the result if the assembly was successful. extraneous text to the left has been removed.5 Examining Hello. C:\user>rem assemble. and exec ASSIST prgram hello. This will cause the macro expansions to appear. You will see the same messages in the command prompt window but there are other files.0_18 Hello World! 18:13:22 hello EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=21 INS=12 Figure 3 Assemble and run Hello World 4. The left hand portion of the .5. The number is the line number as determined by the assembler.prn This is one of the output files from the assembler.5. The assembler will create several files in your directory all with the file name hello but with different extensions.in the command prompt window.6. The code in the macro expansion sections is preceded by plus signs. the result is referred to as the macro expansion). The result should be several messages and the line Hello World! as shown in Figure 3 (note: some extraneous material at the end of longer lines has been cut). In this figure.6. It shows many things but for now. It contains error messages and a description of the machine language program created.01b ON J2SE 1.0_18 18:13:22 hello LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=32 18:13:22 hello EZ390 START USING z390 V1.0_18 18:13:22 hello MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 42 IO=681 18:13:22 hello LZ390 START USING z390 V1. What remains is the assembler's listing of your code and the expansion of the macros. link. Lines 2 through 12 are the expansion of the SUBENTRY macro (when a macro is inserted into our program. you see it's invocation followed by it's expansion.

we aren't interested in this code as it is always the same. 2.8(13) 10+ ST 13. The merely tell the assembler that when it sees a symbol such as R5 it really means 5.13) 36+ L 14.15 12+ USING HELLO+8. 1 HELLO SUBENTRY 2+HELLO CSECT 3+ STM 14.104(15) 5+ DC 18F'0' 6+ DC CL8'HELLO' 7+ DC CL8'09/06/10' 8+ DC CL8'19.12(13) 4+ BAL 15. It has all the basic components of any assembly language program: 1.4(15) 11+ LR 13. R2. The commands in EQUREGS are assembly directives and generate no code.02' 9+ ST 15. The left hand side is entirely in hexadecimal.12(. On line 1 we tell the assembler not to show macro expansion. etc. The right hand side is normally in decimal notation with some exceptions.28(13) 38+ BR 14 40 MSG DC C'Hello World!' 41 END Figure 4 Macro expansion 4. Normally.4(.12. we suppress macro expansion with the PRINT NOGEN directive as the contents of the expansion are not ordinarily very interesting.13) 37+ LM 2.0 35+ L 13.13 14 EQUREGS 15+R0 EQU 0 16+R1 EQU 1 17+R2 EQU 2 18+R3 EQU 3 19+R4 EQU 4 20+R5 EQU 5 21+R6 EQU 6 22+R7 EQU 7 23+R8 EQU 8 24+R9 EQU 9 25+R10 EQU 10 26+R11 EQU 11 27+R12 EQU 12 28+R13 EQU 13 29+R14 EQU 14 30+R15 EQU 15 33 SUBEXIT 34+ LA 15. 25 . Normally. On line 2 we include the macro which allows us to use R1.6 More Basic Assembly Language Examples The hello world program isn't very interesting.12. It doesn't actually do any calculations and mainly relies on system macros rather than actual instructions.executable module. In Figure 5 we see a program to add two numbers.

a character string of length 12. We use the symbolic label ONE and the assembler calculates the base and displacement for us and inserts the correct values into the instruction. 6. The SUBEXIT macro restores the registers that were saved by the SUBENTRY macro. 5. Linkage involves saving the contents of the calling programs registers so they can be restored on exit. Lines 11 and 12 reserve storage for two full word (4 byte) binary values and initialize them to 1 and 2 respectively. The XDECO converts the binary into printable decimal characters. Return is made by the SUBEXIT macro. One line 6 we write a title. we use a symbolic label and the assembler calculates the base and displacement address. The contents of R2 are in pure binary and cannot be printed directly. we will use 32 bit binary numbers although there are instructions to use 64 bit binary as well. 9. This is not a return statement . 10. On line 4 we load the 4 byte binary value from label ONE into register 2. PRINT NOGEN EQUREGS SUBENTRY L R2.TWO XPRNT MSG. Line 14 tells the assembler there is no more code.L'MSG XDECO R2. On line 5 we add the 4 byte binary value at label TWO to the contents of register 2. On line 8 we print the contents of OUT. 4. On line 9 we exit and return to the operating system. 7. Normally. The result of the addition remains in register 2.L'OUT SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DS CL12 END Figure 5 Example program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADD MSG ONE TWO OUT 26 . 11. 8.it merely marks the end of our assembly language program.OUT XPRNT OUT. 12. A base register needs to be setup and the assembler informed of this if program labels are to be used. On line 7 we convert the binary value in R2 to printable characters stored in the 12 byte character string at label OUT. it does not initialize it. Again. Line 13 reserves but does not initialize.ONE A R2. A DS differs from a DC in that a DS only reserves memory.3. The XPRNT macro needs to know where the beginning of the message is and its length. On line 3 we establish linkage and a base register.

unless we tell the assembler to the contrary.1 Operands In the basic IBM architecture. code letters are used to indicate what operands of instruction are. This is permitted so long as you include the EQUREGS macro (or equivalent) at the beginning of your program. an optional index register. B. For most of this text. be used for other purposes. When an operand is in memory. The address of a memory resident operand is calculated by adding the contents of the base register.5 Basic Instruction Formats 5. That is. In most cases. X. The index register is not often used but when it is. 5. the contents of register zero will not be used in the address calculation. R1. Operands can be registers. The terms base register and index register do not refer to another class of registers. the displacement and. Often. the displacement and base register will be automatically filled in by the assembler as is the case when we specify an operand as a symbolic label attached to a data declaration statement as we saw in Figure 5. I. L and D are used to indicate the nature of the operand. They are selected from the set of 16 general purpose registers.B2) 27 . you will see the registers designated as R0. The resulting number is the address of the operand in memory. the 32 bit binary Add instruction is shown in its explicit definition as: A R1. M. The only oddity concerning registers selected to be base or index registers is that if you specify register zero as either the base or index register. the memory address is specified as a combination of a base register and a displacement and. if specified. we will assume that SUBENTRY has been used and that the default base register is thus set to R13. the operand is specified by giving the register number (0 through 15). in some instructions. it is used in array-like operations where the base and displacement identify the start of an array and the index register gives an offset into it. When specifying operands the letters R. General purpose register 0 is not used for addressing. the contents of the index register. In most cases. however. it means no register.D2(X2. the assembler will set the index register to 0 meaning no register. immediate data or memory addresses.2 Operand Notation In the documentation for each instruction. however. R2 and so forth. Most have two. For example. operands can be in registers or memory. It may. When an operand is in a register. Instructions may have from one to three operands.

original instruction formats are RR (register-register). R is used. second. When the operand is a mask. SI (storage-immediate) and SS (storagestorage): 5. the operand will be composed of a base and displacement or an index. I is used.R2 OpCode M1. if any. M is used. and B. X.1 RR Format In RR format instructions there are normally two operands both of which reside in the general purpose registers (GPR). In the above. RR instructions are specified as: OpCode R1. RX (registerindexed storage). is 16 bits long. When the operand is in memory.4 Operand Formats The basic. 5. the Add instruction shown above has a first operand that is a register and a second operand that is composed of a displacement. M1 tells us that the first operand is a 4 bit mask. base and index register. third). When the operand is a byte contained as part of the instruction. RS (register-storage). 5. The instruction. 5.4.The letters tell us what the operand or operand component is and the numbers tell us which operand we are looking at (first. base and displacement. The address of the operand in memory is computed by taking the sum of the displacement and the contents of the base register and the index register. RR format instructions are also called register/register instructions. R I B D X M L means means means means means means means a general purpose register an immediate byte a base register a displacement an index register a mask a length Thus. therefore. The opcode is always the first byte. the first operand consists of only an R while the second operand is composed of D.4.3 Operand Semantics When the contents of a register are the operand.R2 The R1 tells us that the first operand is a register and the R2 tells us that the second operand is a register. L is used in instructions where the operands are of varying length. each in 4 bits. An RR instruction consists of an 8 bit opcode and two register designations.2 RX Format In RX format instructions there are normally two operands. The first operand is a register (shown as R1) or a mask 28 .

4.B2) ) is the address of the operand in memory. RS instructions are specified as: OpCode R1. displacement and index register.4. it means there is no index register.B2) OpCode M1.D2(B2) 5.I2 OpCode D1(B1) 5.4. There is no index register. The byte is a positive integer in the range 0 to 255.5. The first and third operands are registers and the second operand is base/displacement. SS instructions are six bytes in length and also called storage/storage instructions. In addition. In actual execution.3 RS Format In RS format instructions there are three operands.1 One 8 Bit Length Field In SS instructions.4 SI Format SI Format.B1). RS instructions are also called register/storage instructions. RS instructions are four bytes long. RX instructions are specified as: OpCode R1.D2(B2) 29 .D2(X2. there is a one byte field that gives the length of the target operand.R3.D2(X2. The displacement is a 12 bit field containing a constant between 0 and 4095. If the index register is specified as register zero (normally the case).(shown as M1). SI instructions are specified as: OpCode D1(B1). both operands are in memory and specified with base/displacement addresses. Registers are always specified with 4 bit numbers. The result is an absolute memory address. The second operand is a base register. the value of the displacement and the contents of the index (unless it is 0).5 SS Format 5.B2) 5.4. the value is interpreted as one greater that what is stored so a 0 is interpreted as meaning 1 and 255 is interpreted as 256 and so forth. SI instructions are 4 bytes long and are also called storage/immediate instructions. two are registers and one is a base/displacement. In SI format instructions the first operand is a base/displacement value and the second operand is a one byte constant called the immediate operand. The second operand (shown as D2(X2. SS-8 instructions are specified as: OpCode D1(L. The address of the operand in memory is calculated by adding the contents of the base. RX instructions are always four bytes long. The R1 is specified in a 4 bit field.

B2) where L1 and L2 are 4 bit length codes. SS-4 instructions are designated as: OpCode D1(L1. As before. the value is interpreted as one greater than what is actually in the instruction so a 0 means 1 and 15 means 16. the maximum length is 16.B1).4.where L is the 8 bit length code.5. this is a 6 byte instruction. The first length field applies to the first operand and the second to the second. 30 . As before.2 Two 4 Bit Length Fields This is really the same format as above except the length byte is viewed as two four bit fields. This the instruction has two lengths.D2(L2. 5. Because of the 4 bit length fields.

So. displacement. 6. displacement and. consider the examples in Figure 6. In the final example we see the LR or load register instruction. For example. However.1 Explicit Addressing This simplest form of addressing is register addressing.R5 *Contents of R5 copied to R4 Figure 6 . for an operand with base and displacement only. you simply specify the register number. this means you fill in 31 .RR Examples If. This instruction copies the contents of the second operand to the first. or (2) explicitly where you specify the base. As with the AR instruction. the SR instruction subtracts the contents of register 4 from the contents of register 3 and the result is placed in register 3. you fill-in each of the fields.R4 *Contents of R4 subtracted from R3. an index register. index addressing.R3 *Contents of R3 added to R2.6 Basic Addressing Operands in memory are addressed either by a single register which contains the absolute address of the operand or by means of a combination of base register. Here you see three examples of RR instructions RR instruction mnemonics always end in the letter R. you can see that register 2 is the first operand and register 3 is the second operand so the value (contents) of register 3 will be added to the value (contents) in register 2 and the answer (result) will be left in register 2. When using base. possibly (in RX instructions only). you must specify it's location by means of a base. you may specify the memory resident operand either (1) symbolically such that the assembler calculates the base and displacement. In the case of instructions the mnemonics are usually one to 4 character abbreviations of the name of the instruction. the assemblers require you to use numbers only to the example should not have the letter R. an optional index register. AR. in most cases. on the other hand. Note: technically. if an operand is in a register. In the second example we see the subtract register instruction. displacement and index or (3) as a mixture of symbolic and explicit. an operand is in memory. The first example involves the add register instruction. AR R2. displacement and. a system macro is invoked at the beginning of each program which makes the more easily read R form possible. In the most fully explicit way to express a memory operand. in RX instructions. A mnemonic is a short code to make information easier to memorize. result remains in R2 SR R3. More on this later. In the example. The instruction adds the contents of the register specified as the second operand tho the contents of the register specified as the first operand and leaves the result in the first operand. In an instruction. result in R3 LR R4.

In some instructions. Note: register 0 can be used for arithmetic and other things but it has this special meaning when used for addressing. D2 is the place where you put the displacement. the base is R5 and the index is either R6 or R0. the format as it appears on the so-called green card looks like those in the examples in Figure 7. second or third operand. In practice. displacement Figure 8 . In all but one case. D2(B2) D2(X2. index and displacement base. 0 is often seen in this position and the operand. is base. the displacement is added to contents of the register specified as the base register and the result is the amount of the shift. In Figure 7. displacement only. In this case. 1234(R5) 1234(R6. In general. the second operand is used to calculate the number of bits by which to shift the register(s). If 0 is used in an addressing context it means no register. index and displacement Figure 7 Memory operand Index registers are only used in RX instructions. no register will be used for that position. the value of the displacement is 1234.Example memory addressing Another way to specify an operand is called immediate addressing. if you put 0 into a B or X position. it is common to see code such as 32 .the value of the displacement and the register number. In each.B2) base and displacement base. immediate operands are always one byte in length. In the basic instruction set.R5) 1234(R0. no index. Since the index register is seldom used. respectively. 2 is used as most memory operands are second operands. No actual address is calculated. 1334 and 2234. In the case of the shift instructions.R5) base and displacement base. Thus. in effect. In the basic instruction set. They will not be used. in particular. Note that although the shift instructions are RS instructions by the R3 operand is not used. B2 is the place where you put the base register and X2 is the place where you put the index register. There are several ways to code an immediate operand but it is often specified either as a character constant such as C'A' (The letter A) or as a hexadecimal constant such as X'FF' (a byte all of whose bits are ones). The contents for R0 are unimportant. Often they are specified as 0. the operand is actually part of the instruction itself and not in a register or memory. most programs shift by a constant amount. Figure 8 gives a few examples. That is. immediate operands are the second operand and thus designated as I2 in the instruction format tables. the shift instructions. third operands are never of the base displacement variety. The number following each indicates if this is the first. the effective addresses (the result of the address arithmetic calculations) are 2234. however. In the example. If R5 has 1000 in it and R6 has 100 in it.

the base register will be setup by a system macro named SUBENTRY. 6. For example. displacements will be calculated as distances from that point. the assembler needs to know which register or registers it can use for base registers.10 which means. These labels usually appear on data elements or instructions. (For the examples in this book. In order to do this. It is the job of the assembler when you use a label in. an instruction. the assembler will do it for you. The assembler keeps track of the size of everything you write and knows how many bytes each label is from the start of your program.SRA R5. 3. 2. how does the number 10 become represented in the base/displacement operand specification? When you specify a number alone as a base/displacement/index operand. assembly programmers seldom use the explicit base and displacement format when writing programs. it needs to know where in your program these possible base register candidates are pointing so it can calculate the displacement from that point.0) which is to say. load a value from memory at label I into register 7 add to register 7 the value in memory of J store the result back into memory at label K 33 . Additionally. In practice this is not difficult in simple programs. When you write a program you need to tell the assembler not only which register or registers it can use as base registers but also where they are pointing. The labels refer to other parts or your program. for example. shift the bits in register 5 right by 10. no register contribution. for example. You use an assembler command called USING to tell the assembler which register(s) can be used as base registers and what their address contents are. to calculate the correct base and displacement for you and replace the label in the assembled code with these values. R12 is a base register and is pointing (has as its contents) the address of the first byte of your program. they use labels.) What this all means is that instead of you calculating a lot of base and displacement values. Instead. Labels can appear on either instructions or data. suppose you have a program in which you want to: 1.2 Symbolic Addressing In reality. The question is. Thus if. displacement 10. it is as though you specified: 10(0.

the four byte value from memory at I is now in register 7. The assembler first finds label I. Obviously.R13) The displacement is calculated relative to the base register. as is typical. Then it calculates how many bytes from the beginning of the the program the label is located. For this example. not the start of the program. the other instructions from Figure 9 will be translated to machine language as if they had been written as shown in Figure 10. label J is 404 bytes from the start. Note: R13 does not point at the beginning or your program but 8 bytes into it! So. it is only 392 bytes from the value in the base register. the displacement is 392. Figure 9 gives a code fragment that shows the code fragment (other parts of the program have been omitted). L A ST … I J K DC DC DS F'10' F'20' F Figure 9 . it is easier to have the assembler calculate the displacements than to do the calculation yourself.J R7. Hence. The first operand. established R13 as you base register and causes it to point to byte 8 of your program. I is more complex. While your label is 400 bytes from the start of the program. it has an index register position but. the second operand. However. we are not using it so R0 is placed there. The z390 emulator uses an entry macro named SUBENTRY which. Thus. be default.I The first instruction is the RX load instruction. Assume that your program is using R13 as its base register. and label K is 408 bytes from the beginning. R7. When the assembler sees the load instruction. given R13 as the base register pointing at byte 8 and the label I is located at location 400 from the actual start of your program. Assume that label I is 400 bytes from the start of the program. is simple. it scans and parses its operands. It loads the 32 bit value from the address specified by the second operand (I) into the register specified as the first operand.I R7. Next the assembler calculates the relative offset of label I from your base register. let us say that I is at offset 400 from the beginning of the program. the assembler will generate the explicit code: L R7.Example symbolic addressing R7.392(R0. 34 . Similarly. Since the load instruction is an RX instruction.Assume all values are 32 bit (4 byte) binary values.

In some recently added instruction types. Length specifications are always one byte.L A ST … I J K DC DC DS R7. In the earliest days of computing. F).392(R0. 4. SS. In the basic instruction set. 6. RX. those days are long gone. Each instruction type (RR.1 RR Machine Language Format The machine language format is shown in Figure 11 and an example explicit format is: AR R1. etc. 6.3. SI. the machine language code has the following similarities regardless of the instruction type: 1. 2.3 Machine Language Formats The end result of submitting your program to the assembler is a translation of your program into binary machine language. This is true for all basic instruction types but not true for some recent additions. Registers. they are not identical.R13) R7. Displacements are always twelve bits. This is not true with several of the newer instruction types added in recent years but is true for all the basic types. While these formats are similar to a certain point. happily. both base and index.R13) F'10' F'20' F Figure 10 . 5. Each instruction begins with an 8 bit opcode (operation code) that identifies the instruction to be executed. four or six bytes long. are always represented as four bit fields (that's because there are sixteen registers numbered 1 through F and you need four bits to represent the largest of these. the assembler translates from your symbolic assembly code to the actual binary code.400(R0. All immediate operands are one byte. depending on the instruction. Instructions are either two.R2 35 . programmers wrote in binary. 3. Instead.) has a specific machine language binary format.Explicit addressing 6. RS.396(R0. this is not true but it is true for all the basic instruction types.R13) R7. The entire 8 bits might be the length or the byte may be subdivided into two four bit length fields.

consider the instruction: AR R5. In this format. as discussed above. is 1A so the machine language translation of the above is the two bytes: 1A56 Where each hex digit represents four bits. 6. the index register (if it is not zero). For example. the opcode is in the first byte and the second byte is divided into two four bit fields for each of the registers. if you have an instruction of the form: A R5. Consequently.R6 which means to add the signed binary contents for register 6 to the signed binary contents of register 5 and leave the answer in register 5.LABEL 36 . This is the translation of your symbolic code to actual executable code. Address calculation always results in a positive (unsigned) number.B2) Figure 12 RX Machine Language Format RX instructions have two operands. it can never be negative). So. The displacement is treated as an unsigned twelve bit binary number (that is.3. When you run the assembler. The first is normally a register and the second is the address of an operand in memory. and the displacement.D2(X2.2 RX Machine Language Format The machine language format is shown in Figure 12 and an example explicit format is: A R1. the are two bytes in length. They consist of an opcode and two register specifications. in hexadecimal. The opcode for the AR instruction.Figure 11 RR Machine Language Format RR format instructions (see Figure 11) are the simplest. you will see this on the left hand side of the printable output of the assembler. The address of the memory resident operand is calculated by adding the contents of the base register.

240(R0. followed by 4 bits to designate the register being used as the first operand. At this point all the information needed to build the machine language instruction is known. it will be converted by the assembler to the explicit format. followed by the four bits of the index register specification (R0). after the assembler determines the base register and displacement.D2(B2) Figure 13 RS Machine Language Format RS instructions have three operands. 37 . The machine language format consists of an 8 bit opcode. The label LABEL refers to a line in your program where a full word binary valye is stored. might look like: A R5.3 RS Machine Language Format The machine language format is shown in Figure 13 and an example explicit format is: LM R1. The assembler will supply the base and displacement that together can calculate the address of LABEL. followed by 4 bits to designate the base register then 12 bits for the displacement.3. There is no index register. The base and displacement designate what is called the second operand even though it appears third in the actual machine language format. 6. The meaning of the two register operands varies depending upon the instruction being executed but the format of the machine language representation is always the same. The opcode for the Add (RX) instruction is 5A and thus the final result is: 5A50C0F0 In this representation (see Figure 12) the 8 bit op code is followed by the four bits specifying the first operand (R5).this means to add the contents of the signed 32 bit operand in memory at label LABEL to the signed binary contents of register 5 and leave the result in register 5. Your symbolic instruction from above.R3.12 is C in hex) followed by the twelve bit displacement 24010 which is 0F016.R12) where 24010 is the value calculated by the assembler as the displacement from the presumed contents of R12 to LABEL. two of which are designated as registers and the third a memory location in base/displacement format. followed by 4 bits designating the register being used as the third operand. followed by the base register specification (R12 . Since the second operand is specified as a symbol (rather than a specific displacement and register).

might be: LM R1.C'A' This instruction compares the byte in memory at the label MEMB with the immediate byte whose value is the letter A. less than or greater than the immediate operand. after the assembler has conveniently translated MEM into base displacement format. An example of such an instruction is: LM R1. the third operand (5).C'A' 38 . the symbolic instruction might be: CLI MEMB.MEM In this example. It compares a byte in memory with the immediate byte and sets some bits indicating if the byte in memory is equal. registers R1.Compare Logical Immediate. there is an instruction known as CLI . A more fully explicit version of the above.R5. For example.4 SI Machine Language Format The machine language format is shown in Figure 14 and an example explicit format is: CLI D1(B1). 6. the base C16 and the displacement (0C816). one of the RS format instructions is Load Multiple. R3. R2.3. It loads multiple registers from consecutive words in memory. After MEMB is translated to an appropriate base and displacement pair. For example. the symbolic instruction might look like: CLI 64(R12). Both the memory operand and the immediate operands are always one byte long.For example.I2 Figure 14 SI Machine Language Format The SI instructions all have one of their two operands actually in the instruction.200(R12) The opcode for LM is 9816 so the machine language instruction would look like: 9815C0C8 By now you should be able to see the opcode (9816). Altogether. R4 and R5 are loaded with the consecutive 32 bit full words in memory beginning at the label MEM. the first operand (1). 20 bytes of memory are accessed (5 words of 4 bytes each).R5. The other operand is the address of a byte in memory. If you want to test is a byte in memory has the value A.

200(R12) The opcode of MVC is D216 so the machine instruction would look like: D207C064C0C8 39 .D2(B2) AP D1(L1. C16 (12) is the base register and 04016 is the displacement. Both also have a length byte. if you want to copy the 8 bytes beginning at the label FROM to the eight bytes beginning at the label TO.B2) SS has two formats that differ slightly from one another with regard to the length field.FROM In fact. the I2 operand actually appears first and the first operand D1(B1) appears second. the length byte is taken as an unsigned 8 bit number. In SS instructions.R12). both operands are in memory and addressed in base and displacement format. in one format. 6.D2(L2. For example. If the explicit form of the above might look like: MVC 100(8. the assembler would use the length attribute of the target. The machine language formats are shown in Figure 15. In this case. This instruction copies up to 256 characters beginning at the address specified by the second operand to the target beginning at the address specified by the first operand. In the other variation.The opcode for CLI is 9516 and the machine language instruction for the above would look like: 95C1C040 where C116 is the letter A in hex.3. Note that in the instruction. the length designation (8) may be unneeded if the label TO has a length attribute of 8 (see below). The length byte is treated as an unsigned 8 bit number (a negative move length would be meaningless).5 SS Machine Language Format Example explicit formats are: MVC D1(L. the length byte is interpreted as two unsigned 4 bit numbers.B1). An example of the first format might be the Move Character (MVC) instruction. Figure 15 SS Machine Language Format However. All SS instructions are 6 bytes in length. you would express it symbolically as: MVC TO(8).B1).

C16 is the second base and 04016 is the second displacement. 02016 is the first displacement. For example. This is mainly used with a class of arithmetic instructions known as decimal or packed. there is an SS instruction known as Add Decimal (or Add Packed. Some SS instructions divide the length byte into two 4 bit fields in order to get 2 lengths. But wait. This was done because a length of zero had no use and it allowed the maximum length be be one longer (256 as opposed to 255). Translated to explicit format the above might look like: AP 32(5. respectively. the length is always one less.You can see the opcode (D2) the length (07). 2 is the second length. The length subfields give the length of the first and second operand. the length is 8 not 7? Correct but when represented in machine language. a typical AP instruction might look like: AP VAL1(5). C is the first base. It is normal for both base registers to be the same. 1 means 2 and so forth. given the opcode of FA16 yield the machine instruction: FA42C020C040 where FA16 is the opcode.R12) which would. the first displacement (06416). first base (C16).64(3. more commonly) with the mnemonic AP. 40 .VAL2(3) This means to add the three byte field from the second operand (VAL2) to the contents of the 5 byte field specified as the first operand (VAL1) and leave the result in the first operand. Thus 0 means 1. the second base (C16) and the second displacement (0C816). 4 is the first 4 bit length code (one less than 5 as above). So.R12).

however. In ESA/390 mode.2 Addressing modes In 24 bit addressing compatibility mode. 2 and 3 at any given instant. The meaning of the Condition Code value is connected with how it was set. In the Z architecture. Originally. the address portion is bits 33 through 63. it is a 128 bit (16 byte) register that has the same purpose and many of the same fields. After signed binary addition. the PSW is 64 bits in length and the address is 31 bits in length. The Condition Code is two bits in the PSW which reflect the result of a prior operation. The Program Mask determines which program exceptions will be recognized. it was a 64 bit (8 byte) register in the CPU which contained several important values relating to the status of the system at any given instant. Thus. is bit 31 is 1. 7. 31 bit mode is in effect and when they are both 1. the condition code tells you if the result was zero. For example. In the Z architecture. knowing which instruction that Condition Code is important to understanding it's meaning. the address in contained in the low order 31 bits of the second word of the PSW. 1. Many instructions set the Condition Code in order to indicate the result of their execution. in the other hand. 64 bit addressing is operational. It can have the values 0. if you execute a compare instruction. In 31 bit addressing mode. In 64 bit addressing mode the address is found in bits 65 through 127. Currently. In the Z390 emulator. when both are zero.1 Layout The PSW (Program Status Word) has been part of the IBM mainframe architecture since the beginning. negative. In the ESA/390 mode. the PSW is 128 bits and the address is contained in the last 64 bits. 24-bit addressing is in effect. Some of the important fields in the PSW in the ESA/390 level architecture are addressed in the following sections.7 Program Status Word (PSW) 7. The longer format is mainly due to an extension of the addressing from 24 to 64 bits over the years. there are also instructions that do not alter the Condition Code. 7. When bit 31 is 0 and bit 32 is 1. addressing is in 31 bit mode. The basic addressing mode is determined by bit 31 (ESA/390 mode) and 32 (Z architecture only).4 Program Mask The Program Mask is located in bits 20 through 23. less than or equal to one another. the address portion of the PSW is bits 40 through 63. But. in the latest models. 24 bit mode otherwise. the Condition Code will indicate if the operands were greater than.3 Condition Code The Condition Code is located at bits 18 and 19. The are: 41 . 7. positive or an overflow (the answer was too large).

6 Instruction Addressing The PSW contains the address of the next instruction to be executed. the system is in supervisor state and all instructions may be executed. In problem state.Enable floating point significance exception When the bit is 1.Enable decimal overflow exception Bit 22 . the address portion of the PSW is updated (incremented) to point to the address of the byte immediately following the instruction about to be executed. 7.Enable floating point underflow exception Bit 23 . When 0. 42 . When you alter this value.Bit 20 .Enable fixed point overflow exception Bit 21 . When an instruction is fetched. the next instruction to be executed will be fetched from this location. This is often referred to as the updated address portion of the PSW. Thus. In effect. 7. When 1.5 Problem / Supervisor State Bit The Problem State bit is located at bit 15. prior to its execution. the address portion of the PSW presumably points to the next instruction to be executed. the exception is enabled. not all instructions may be executed. Any of the branch instructions can alter the address portion of the PSW. the machine is in (unprivileged) problem state. a branch means changing the address portion of the PSW.

the destination address is calculated form the base. in the BCR. Normally. The instruction will branch is any tested value succeeds. the destination address is contained in a register specified as the second operand. Some times we want to skip blocks of code if some condition is true or false or we may want to loop through a block of code a number of times or we want to branch to a subroutine and return when the subroutine has finished. However this is not always desirable. In both instructions. the branch takes place.1 Conditional Branching (BC. If the Condition Code does not have one of these values. The conditional branch instructions branch or not depending on the Condition Code/ 8. The explicit formats are: BC M1. BCR) The conditional branch instructions branch or transfer control based upon the contents of the Condition Code. instructions that iterate and instructions that are used to call subroutines. if you want to skip a section of code if. no branch takes place. The mask tells the computer which setting or settings of the Condition Code should cause the instruction to branch. a computer will consecutively fetch and execute instructions one after another from ascending memory locations. displacement. The mask is 4 bits and these correspond to the 4 possible settings for the Condition Code. On the other hand. For example. index. the result of some arithmetic operation were negative.R2 In the BC instruction.B2) BCR M1. The most common form of the branch instruction is the conditional branch. the first operand is called a mask. In the basic architecture there are several branch instructions to handle these situations.D2(X2. 43 . for example. It resides in the 4 bits where there would normally be a register specification in the RX and RR format. If the Condition Code has one of these values. If a mask bit is off and the condition Code has the corresponding value. In both instructions the destination (where to branch to) is specified by the second operand.8 Flow of Control & Branch Instructions Every program needs a way to control the order in which instructions will be executed. execution resumes with the instruction next following the branch instruction. that means the branch will take place if the Condition Code has the corresponding value. If a mask bit is 1. These include instructions that branch if a condition is true. The two basic conditional branch instructions are the BC (an RX instruction) and BCR (the RR version of the BC). the instruction to make the transfer is a conditional branch.

All possible other combinations are shown in Table 6.For example. 0 1 2 3 Answer Answer Answer Answer was zero was less than zero was greater than zero caused an overflow Table 5 Condition Code after signed Add Let us say you want your program to branch to some label in your program if the result of the Add was zero. the third to 2 and the fourth to 3. the branch to label LAB1 will occur if the result in R3 is zero. B'0000' B'0001' B'0010' B'0011' B'0100' B'0101' B'0110' B'0111' B'1000' B'1001' B'1010' B'1011' B'1100' B'1101' B'1110' B'1111' Never branch Branch if overflow Branch if > zero Branch if > zero or overflow Branch if < zero Branch if < zero or overflow Branch if not zero or overflow Branch if not zero Branch if zero Branch if zero or overflow Branch if zero or > zero Branch if not < zero Branch if zero or < zero Branch if not > zero Branch if not overflow Branch always Table 6 Mask settings after a signed add 44 . you may combine all the conditions for which you want to branch into one mask on one BC instruction. this is wasteful. You need mask of 10002 as shown in Figure 16. the BC to branch if zero or negative becomes the single instruction: BC B'1100'. Thus. However.R4 BC B'1000'.LAB1 Figure 16 BC example What if you wanted to branch if the result in R3 was zero or less than zero (negative)? you could place a second BC instruction after the first such as: BC B'1000'. AR R3. the second to 1.LAB1 BC B'0100'. Instead. B'1000'.LAB1 Now the instruction will branch is the Condition Code is either 0 or 1. after a signed Add instruction the Condition Code will have the values shown in Table 5. The first operand. The first position in the mask corresponds to a Condition Code of 0. specifies a 4 bit constant.LAB1 which will work because the BC instruction does not alter the Condition Code. In this case.

you use a mnemonic which is indicative of the purpose.The mask can be specified in any manner.LAB 10.LAB 6.LAB B'1100'.LAB 9.LAB 3.LAB B'1111'. By adding the decimal equivalents of the bit positions. the decimal mask would be 9 (8+1).LAB 2.LAB 5. no branch takes place since R0 is not used in addressing contexts. Instead of using the mask codes.LAB 14. Table 7 gives examples. They are interchangeable. These are instructions where the assembler will fill in the mask for you. Note that this corresponds the the mask values in Table 7 as well.LAB or or or or or or or or or or or or or or BC BC BC BC BC BC BC BC BC BC BC BC BC BC 1.LAB B'1101'. a final decimal mask can be created. there are builtin extended mnemonic branch instructions. 45 .LAB B'1001'.LAB 8. Condition Code 0 1 2 3 Decimal Mask Value 8 4 2 1 Table 8 Decimal mask equivalents The BCR instruction is similar to the BC. The first operand is the four bit mask with the same meanings as in the BC instruction. The assembler uses a BC or BCR with a predetermined mask.LAB B'0110'. The equivalents are shown in Table 8.LAB B'1110'. BC BC BC BC BC BC BC BC BC BC BC BC BC BC B'0001'. When a decimal number is given.LAB B'1000'. if you want to branch if the Condition Code is either 0 or 3.LAB 12.LAB B'0100'.LAB B'0101'.LAB B'1011'.LAB 11. Additionally.LAB B'1010'.LAB Table 7 Decimal mask settings A simple way to construct a decimal mask is to remember that the bit positions in the mask each have a decimal equivalent. These are shown in Table 9. Some mask settings (such as 8) have more than one extended representation: BE after a Compare instruction and BZ after an arithmetic instruction.LAB 4. The second operand is a register which contains the branch address.LAB 13. The most popular methods are either as a decimal number or as a bit string.LAB 15.LAB B'0010'. its corresponding binary value determines the branch conditions. The purpose of these is to make your program more readable. However. So.LAB B'0011'. if the second operand is specified as R0.

D2(X2.B2) BE D2(X2. in which case no branch takes place.D2(X2. Normally.B2) BNL D2(X2.D2(X2.D2(X2.B2) BM D2(X2.B2) BNE D2(X2.B2) BCR 15.B2) 7.B2) BR R2 NOP D2(X2. The Instruction Length Code (bits 0 and 1) The Condition Code (bits 2 and 3) The Program Mask (Bits 4 through 7) 46 . the absolute memory address of the instruction following the BAL or BALR is placed into the register specified as the first operand.D2(X2.D2(X2.D2(X2. 2.D2(X2.D2(X2. In addition to placing the 24 bit in the rightmost bits of the register specified as the first operand.B2) After Test Under Mask B0 D2(X2. These instructions were on the earliest implementations of the 360 architecture and assume a 24 bit addressing mode. they always branch.B2) BNP D2(X2.1 BAL and BALR .B2) 4.D2.B2) 2.2 Branch and Link Instructions 8.B2) BP D2(X2. 3.B2) Branch Branch Branch Branch Branch Branch A high A low A equals B A not high A not low not equal After Arithmetic Instructions BO D2(X2.B2) 13.B2) 13. This is the linking operation.B2) BNE D2(X2.Extended B D2(X2.B2) 4.B2) BM D2(X2.(X2.B2) 8.D2(X2.B2) 8.R2 Meaning Branch always Branch always No operation No operation After Compare Instructions (A:B) BH D2. they also place.B2) BL D2(X2. in the high order 8 bits.D2(X2.B2) BZ D2(X2.B2) 11.B2) BC BC BC BC 1.D2(X2.B2) BNH D2(X2.B2) BCR 0.(X2.B2) 14.2. displacement address in the case of the BAL and the address contained in the register designated as the second operand in the case of the BALR except if the register specified is R0.B2) BNO D2(X2.B2) BC BC BC BC BC BC 2.D2(X2.B2) Branch Branch Branch Branch Branch Branch on overflow plus minus zero not plus not zero Table 9 Extended mnemonics 8.B2) 8.D2(X2.D2(X2.D2(X2. The branch is made to the address specified by the second operand: a base.B2) BZ D2(X2.B2) NOPR R2 Basic BC 15. the following fields from the PSW: 1. In both cases.D2(X2.B2) Branch Branch Branch Branch if if if if ones mixed zeros not ones BC BC BC BC BC BC 1.B2) 7.B2) 4.R2 BC 0.Branch and Link The BAL and BALR instructions unconditionally. index. they do not depend on the condition code.

3 Branch Relative and Save . In 31 bit addressing mode. They load the updated instruction address portion of the PSW in the register specified as the first operand. the immediate field is treated as the number of half words to jump from the current address. 8. in the BASR if the second operand is specified are R0 in which case no branch takes place.3 Looping Branch Instructions 8.=V(SUB1) * load the address of a subroutine BALR R14.3. Example: L R15. the 31 bit address is padded to the left with 1 bit whose contents are 1. a single one bit is appended to the left. there is a 32 bit immediate field which is also treated as a signed number. If in 24 bit addressing mode. it is sometimes used. Since this is such a common sequence of 47 .2 Branch and Save .BRAS. The BAS and BASR instructions differ from the BAL and BALR instructions mainly in that they do not place additional information in the high order bits of the address stored in the register specified as the first operand. 8 zeros are appended to the left. They both load the updated address portion of the PSW into the first operand and branch to the address specified by the second operand except. 8. the 24 bit address loaded into the first operand is padded to the left with 8 bits all of which are 1. In the BRASL. BRASL These instructions are similar to the BAS instruction. In 24 bit addressing mode.2. in combination with R0 as the second operand. a compare and a conditional branch. the loop mechanism involved an arithmetic operation. Equal. 8. That is.R15 * branch to subroutine Because the BAL/BALR place additional information in the high order 8 bits of the address saved in the first operand and the BAS and BASR do not. BXH In the examples above. in 31 bit addressing mode.2.BXLE. High . to load a register with the absolute memory address of the byte following the instruction. the BAS and BASR are now the preferred linkage instructions for 31 bit addressing. In both instructions. In the case of the BALR. the branch address is computed by adding the twice the value of the immediate field to the current instruction address.An important use for these instructions is to branch to a subroutine and load into a register the address of the return point.1 Branch Index Low.BAS and BASR These are similar to the BAL and BALR instructions and are intended to replace them. In the BRAS instruction there is a 16 bit immediate field which is treated as a signed binary number.

D2(B2) The instruction operates as follows: First. There are several instructions that use even/odd register pairs. R3 will be our counting register which we set to 1. The instruction is an RS instruction which has the explicit format: BXLE R1.R3. resulting in considerably faster execution. an increment is added to the contents of the register specified as the first operand. comparison and conditional branch into one instruction thus. On line 5. it is the even register of an even odd pair where the even register of the pair contains the increment and the odd register contains the limit value. DS statements only reserve the memory). Closely related to the BXLE is the BXH. R14/R15. R10/R11. The first of these is the BXLE instruction. If the register designated as R3 is even. is used to determine the increment amount and the limit value. also set to 1 and R5 is the limit register. respectively. 48 . R6/R7. On lines 5 through 8 we initialize the registers. the D2(B2). The valid pairs are R0/R1. set to 100. R8/R9. The BXLE branches to LOOP so long as the value in R3 is less than or equal to 100. R12/R13. The BXLE then increments R3 by 1 (R4) and compares the result with 100 (R5). in many circumstances. R4 will be the increment register. But. If the register designated as R3 is odd. the R3 in the above. The XPRNT prints the result to the screen. in a large loop. The third operand. the architecture provides several instructions that perform all three operations. In this program we add the first 100 numbers into R2 and then print the result. R2 is set to zero by subtracting it from itself. If the result of the comparison indicates that the contents of the first operand are less than or equal to the limit value. R4/R5. The BXH operands are the same in scope and function as the BXLE except that the branch takes place when the contents of the register specified as the first operand are greater than the limit value. If not. The program in Figure 17 gives an example of the BXLE in use. The second operand of the XPRNT is the length of the string OUT. The disadvantage is that it ties up several registers in the process. Branch on Index Low or Equal. execution continues with the XDECO which converts the binary value in R2 to printable characters in the 12 byte string OUT. R2/R3. The advantage of the BXLE instruction is that it combines the increment.events. the branch does not take place. The data declarations on line 15 and 16 create two full word binary values in memory initialized with the values 1 and 100. When R3 becomes 100. We add R3 to R2 in line 9. its contents are used as both the limit and increment and the limit values. The value in the first operand is then compared with a limit value and a branch takes place to the address specified by the second operand. The declaration on line 12 reserves storage for a character string of length 12 but does not initialize it (DC statements initialize. it is justified.

As before. 49 . The BCT instruction then decrements R5 and branches to LOOP is R5 is not zero.ONE L R5.OUT XPRNT OUT. On line 7 we add the counting register into the total (R2). in which case no branch ever takes place (R0 being used in an addressing context). the program from Figure 17 becomes the program in Figure 18. the BCTR becomes a decrement instruction on the register specified as the first operand. Using a BCT instruction. execution advances to the next instruction. we zero the contents of R2 (line 5) and load 100 into R5.2 Branch on Count . a branch is made to the address specified by the second operand. When the result is zero. In the case of the BCTR.R3 BXLE R3.R2 L R3. In the case of the second operand being R0. the count register.ONE L R4.LOOP XDECO R2.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SUM100 PRINT NOGEN EQUREGS SUBENTRY SR R2. If the result is not zero.3.BCT (RX) and BCTR (RR) A similar set of looping instructions are the BCT and BCTR or Branch on Count instructions.L'OUT SUBRETURN LTORG DC F'1' DC F'100' DS CL12 END Figure 17 BXLE loop example LOOP ONE HUNDRED OUT 8.HUNDRED AR R2.R4. In both of these. one is subtracted from the contents of the register specified as the first operand. the second operand is a register whose contents are the branch address except when the second operand is specified as register zero.

DBL XPRNT DBL.R5 BCT R5.HUNDRED AR R2.LOOP XDECO R2.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUM100 PRINT NOGEN EQUREGS SUBENTRY SR R2.R2 L R5.L'DBL SUBRETURN LTORG DC F'100' DS CL12 END Figure 18 BCT loop example LOOP HUNDRED DBL 50 .

a close cousin of packed decimal format. numbers up to 31 digits in length. In this format. 4. 1. 1111 and 1110 (hex digits C. Their main disadvantage is that arithmetic operations are relatively slow and thus they are not suitable for procedures which require multiple arithmetic steps. can be represented. 3. floating point and packed decimal. respectively. 4. In zoned format.1 Arithmetic Data The IBM hardware architecture supports three basic arithmetic data types: binary integer. plus a sign. F. packed decimal can be converted to printable numeric text very quickly as well. 1010. they do not have the range of magnitude often required for scientific calculations. Table 10 Numeric data types 9. Table 10 gives an overview. One advantage of packed decimal is that numbers in this format they can be used to perform accurate decimal arithmetic on values with many digits. Another advantage is that character versions of numbers (such a user might type on a terminal) can be converted to packed decimal very quickly and. hexadecimal or decimal radixes. Printable numbers are in what is called zoned format. the high order 4 bits of each byte are always ones (hex F) and the low order 4 bits are the digit 51 .1. Thus. often referred to simple as zoned. often referred to just simply as packed or BCD (binary coded decimal). Each byte contains two decimal digits except for the final byte which has one 4 bit digit and a 4 bit sign. The final byte has a digit in the high order 4 bits and the sign of the number in the low order 4 bits. Table 11 gives several examples of packed decimal numbers. half a byte.9 Data Types 9. and E) in the sign position indicate the number is positive while the codes 1101 and 1011 (hex digits D and B) indicate a negative number. 8 or 16 bytes length with either binary. Floating point numbers of either 4.1 Packed Decimal and Zoned Decimal Format Data The IBM mainframe has a data type called packed decimal. A. likewise. Each digit is stored in 4 bits. Further. The codes 1100. Signed binary integers of either 2. decimal numbers are represented in a string of from 1 to 16 bytes. Normally. Any code is equally valid but C and D are the defaults for positive and negative. The the decimal numbers 0 through 9 are represented by their binary equivalents 000 through 1001 (hex codes 0 through 9). 2. we only see the hex codes so it is easy to remember that the positive codes are CAFE and the negative are DB (as in debit). or 8 byte length Unsigned binary integers of either 4 or 8 bytes length Varying length signed packed decimals up to 16 bytes long. They are merely encodings of a decimal number with a sign appended to the end.

the instruction CVB converts a packed decimal to binary. The first is what is referred to as sign and magnitude. the number is positive and if it is one. However. in sign and magnitude notation -107 would be: 52 . how can you represent negative numbers? There are several possibilities. The CVD is unusual in that the target is addressed by the second operand. 9.1. The question becomes. Decimal +12345 -12345 +1 +12 Packed Decimal (in Hex) 12 34 5C 12 34 5D 1C 01 2C 3 3 1 2 bytes bytes byte bytes Table 11 Example packed decimal numbers When text numbers are read from a terminal or other user input device. the corresponding value of the power of two is added to the total.portion. Where there are 0s (not shown). Likewise. The ED (edit) and UNPK (unpack) instructions convert from packed decimal to zoned decimal and the PACK instruction converts from zoned decimal to packed decimal. Additional details are described in Chapter 21. is a sign bit. in an 8 bit computer. The CVD instruction converts a binary quantity in a register to packed decimal. This. the number is negative.2 Binary Integers and 2s Complement Positive binary integers are represented as a string of bits of zeros and ones. the larges number you can store in an 8 bit field is 28-1 or 255 (0 through 255 are 256 values. The positions are powers of two beginning with zero. In this table. one of the bits. An actual binary number is the sum of the values for its bit positions. the positive number 107 is: 0110 1101 and. the binary number (expressed to 32 bits): 0001 0000 1001 0000 1000 0000 1011 1001 is interpreted as shown in Table 13. internally this will be coded as the four bytes: F1 F2 F3 F4. Here. For this reason. where there are 1s. If it is zero. The last row is the largest value you can store in an unsigned binary integer: 2311. nothing is added to the final total from that position. the input machinery codes each digit in zoned format. the high order 4 bits of a byte are called the zone and the low order 4 bits are called the digit. not all numbers are positive. if you type 1234 into an EBCDIC terminal. Thus. however). the first one usually. Table 12 gives the powers of two from 0 to 31 (32 altogether) and the corresponding bit pattern in a 32 bit field. The value of a binary number is the sum of the values of the bit positions times the value at the position (0 or 1). For example.

has several problems.1110 1101 1 2 4 8 16 32 64 128 256 512 024 048 096 192 384 768 536 072 144 288 576 152 304 608 216 432 864 728 456 912 824 648 295 20 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232-1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0001 0010 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1 2 4 8 16 33 67 134 268 536 1 073 2 147 4 294 1 2 4 8 16 32 65 131 262 524 048 097 194 388 777 554 108 217 435 870 741 483 967 Table 12 Powers of two Sign and magnitude notation. The first of these is there are two ways of expressing zero: 0000 0000 1000 0000 1 x 228 268 435 456 1 x 223 8 388 608 1 x 220 1 048 576 1 x 215 32 768 1 x 27 128 1 x 25 32 1 x 24 16 1 x 23 8 1 x 20 1 ------------------277 905 593 Table 13 Decimal value of a binary number 53 . however.

2s complement is formed by adding one to the 1s complement. Yes. If I add the value of 107 and -107 I should get zero but I don't: 0110 1101 + 1110 1101 ----------1 0101 1010 The extra bit on the left is an overflow. 1s complement has two zeros too: 0000 0000 1111 1111 positive zero negative zero So. Another solution is called 1s complement. Another problem is that you can't do arithmetic directly on number in sign and magnitude notation. Does this work? It solves the arithmetic problem: 0110 1101 + 1001 0010 ----------1111 1111 And the answer is zero. are zero. This sort of thing confuses the hardware.The first is a positive zero and the second is a negative zero. In 1s complement we form the negative of a number by flipping (complementing) the bits. This is a problem. This. 107 and -107 appear as: 0110 1101 1001 0010 107 -107 As it turns out. we still have the problem of comparing two values but there is a solution: 2s complement. Both. To solve it. This adds complexity and reduces speed. The answer is not zero. both negative or mixed. you need more specialized hardware to take into account all the possible outcomes. 1111 1111 is zero. all negative numbers have a leading one bit so that position is still called the sign but the remainder of the number is quite different. however. If you compare two values you need to take into account that they could both be positive. Thus 107 becomes negative the following way: 0110 1101 1001 0010 1001 0011 107 1s complement 2s complement How does this solve the two zeros problem: 0000 0000 1111 1111 0000 0000 54 zero 1s complement 2s complement (overflow ignored) .

is 0000 or zero.000 Hz. This.In other words.4 Threshold Binary Values In many cases. A consequence of this is that one bit is lost to sign representation so. do range from 0 to 4.483. Can we do arithmetic? Yes: 0110 1101 + 1001 0011 ------------0000 0000 107 -107 There are special rules for handling overflows which won't be covered here. is how signed binary integers are represented in a modern computer. At 8 bits you can have numbers between 0 and 255. the largest binary number in 4 bits is 1111 which corresponds to 15 decimal.295 as shown above but.967. This lets them claim what appears to be a higher capacity for their offerings.967. 9.note the small print on the package. 9. Thus. The minimum number. Thus. Memory manufacturers.483.647.000. the instruction formats all allow 4 bits whenever a register is designated. you need 4 bits to be able to specify any register. it is important to know the maximum number that can be stored in an unsigned binary number with a particular number of bits.000 bytes a gigabyte .1. the range 0 to 15 has 16 values. you get the original zero again. it is currently fashionable among disk drive manufacturers to call 1. however.295. However.1. 2. For example." Clock rates are normally expressed in base 10 so 1 gHz is 1. they are shorting you more than 71 million bytes per "gigabyte.000. however.000. of course. the range is not 0 to 4. a total of 256 values. Unsigned 32 bit numbers.294. rather.073. 55 . 1 gigabyte of memory actually has 230 or 1. That is.294.147. Thus. the maximum number of binary codes in an 8 bit byte is 256. 4 bits are needed to specify any of registers in an IBM mainframe. are stuck with the higher binary values due to manufacturing issues. in the case of a 32 bit number.648 to + 2.000. expressed in decimal.741. In fact.824 bytes. if you try to create a negative zero. megabytes and gigabytes derive from these thresholds. Hence.147. however. Terms such as kilobytes.3 Nomenclature Table 14 gives the decimal values of several powers of two and along with the terms with which we refer to them. Note: there is one more negative number that positive numbers (that extra zero had to go some place). however.

56 .1 024 2 048 4 096 8 192 16 384 32 768 65 536 131 072 262 144 524 288 1 048 576 2 097 152 4 194 304 8 388 608 16 777 216 33 554 432 67 108 864 134 217 728 268 435 456 536 870 912 1 073 741 824 2 147 483 648 4 294 967 296 210 2 11 1 K 2 K 4 K 8 K 16 K 32 K 64 K 128 K 256 K 512 K 1024 K or 1 M (meg) 2 M 4 M 8 M 16 M 32 M 64 M 128 M 256 M 512 M 1024 M or 1 G (gig) 2 G 4 G 212 2 2 13 14 215 2 2 16 17 218 2 2 19 20 221 2 2 22 23 224 225 2 26 227 228 2 29 230 231 232 Table 14 Binary nomenclature Similarly.777. So.215. many older legacy programs still run in 24 bit addressing mode to this day. Many legacy assembly language programs have coding conventions that take this number into account. In 16 bits you can count from 0 to 65. 32 bit and 64 bit addressing modes. Many programs and operating system conventions used that byte to communicate information. Consequently. Thus. if your unsigned binary number has 12 bits. 16. If they were executed in 32 bit mode. Modern mainframes can execute programs in 24 bit. since addresses were almost always stored in 4 byte full words. the size of a displacement. one byte (the high order or leftmost) was not used for addressing. At 24 bits your numeric range is 0 to 16. It takes 3 bytes to hold a 24 bit number.777.215 (~16 meg) number is significant as it was the upper limit of memory size on the basic 360 Series. you can have 4096 values between 0 and 4095. the high order byte would be considered part of the address and lead to erroneous results.535. the maximum displacement from a base register is 4095.

When reserving memory. the DS/DC code tells the assembler the type of data you are reserving. you normally place a label on an area of memory. several data specification types have no implied length. This is for performance reasons as some operations execute quicker if the data is on aligned boundaries. however. Alignment refers to where the memory associated with the label can be put. FORTRAN. storage class and so forth. is normally 32 bits or 4 bytes because this is the size of a general purpose register in which data of this type is normally manipulated (note: on newer 64 bit architectures 64 bit or 8 byte values are possible). Note: in some cases the label can be omitted if there are other ways to address the data area. a long is 32 bits or 4 bytes in C/C++ while a char is 1 byte. These are defined with declaration statements that give the name of the variable. The first is a DC statement and the second is a DS statement. a fixed point binary integer. there are two main methods of reserving memory. C++. In your program. For example. Some data types require that the address of the memory holding the value be evenly divisible by 4 (word alignment). 57 . The assembler will remember the attributes with which you labeled the memory for future use. length and so forth of the memory being reserved. A DC (declare constant) statement reserves and initializes memory in your program whereas a DS (declare storage) statement only reserves memory without initialization. its dimensionality (if any). This label is then used to refer to the memory in program instructions in a manner analogous to variables in a high level program. a length and the alignment of the memory that will hold the value. the minimum length is 1 byte and the maximum is effectively unlimited. Depending upon the data type and dimensionality. an amount of memory is allocated for each variable. there is an implied length. the assembler will allocate an amount of memory at that location in your program. For example. In both forms you ordinarily (but not always) place a unique label complying with assembler naming rules (see page 18) beginning in column 1. you manipulate named variables. Based on your combination of codes. you include one or more spaces followed by either DC or DS. and so forth. In IBM Assembler. data type. In these. type F.10 Data Declarations 10. followed by one or more spaces followed by a series of codes that indicate the data type. you access and manipulate this memory by referring to the names of the variables. Each code implies a data type. Java. 8 (doubleword alignment) or 2 (half word alignment). In assembly language. There are several codes that may be used but the most common are given in Table 15. These will be discussed separately. In other data specifications.1 Declare Constant and Declare Storage (DC and DS) In a high level language such as C. dimensionality. Assembly language has a similar but different approach. After the label. In Table 15.

Initialization is normally a single-quoted string beginning immediately after the data type and any qualifications to the data type. DAT1 DAT2 DAT3 LAB1 LAB2 LAB3 LAB4 LAB5 DS DS DS DC DC DC DC DC DC F H D F'123' C'HELLO WORLD' B'1011101010001001' X'2F3C' P'1234' F'789' *fullword uninitialized *halfword uninitialized *doubleword uninitialized *binary full word *character string *bit string *hexadecimal string *packed decimal string *binary full word Figure 19 Example DS/DC statements 58 . Normally you won't notice this but if you look carefully. especially where you need to know the exact amount of memory used by variables in contiguous memory. the contents of each is undefined. 11. you do not provide initialization. the assembler will automatically skip one or more bytes in order that your value will be correctly aligned. In some cases. The memory reserved by labels LAB1 through LAB5 reserve 4.Type C X B F H D P Z A V Implied Length 4 2 8 4 4 Alignment byte byte byte word halfword doubleword byte byte word word Format characters hexadecimal digits binary digits fixed point binary fixed point binary long floating point packed decimal zoned decimal address value external address value Table 15 DS/DC Data Types In your program. If you use the DS statement. you will see the location counter increment by 6 and not 4 for your variable. 2. 2 and 8 bytes respectively. if the next available byte is not aligned properly for the data type your are creating. and 3 bytes respectively and initialize each as shown. If you use DC. Fore example. The unlabeled memory following LAB5 can be addressed as LAB5+3 (the length of the data at LAB5 is 3 bytes). consequently. 2. Figure 19 gives some examples. The first three labeled DS statements reserve 4. these extra padding bytes may be important. None of the data items at these labels are initialized and. The value in the string must be appropriate for the data type. if the next address available is divisible by 2 but not 4 and you are allocating a full word fixed point value (type F). the assembler will skip two bytes before allocating your data item. you give an initial value that will be loaded into the memory location when the program begins.

be placed at the end of your program or at point immediately after the LTORG directive. and so forth). As long as the first byte of the data area in within range of a base and displacement. Your label (lets say LOC) will be the address of the first fullword and the remaining 17 will be at successive 4 byte offsets from this location (LOC+4. it can be used without problem (you load the address of the area into a register and address it directly with this register). 59 .2 Literals Often for the sake of clarity or convenience. the LTORG can be used to dump the literal pool prior to the start of a large data area. In the first example from Figure 20.C'X' *loads R1 with 123 *moves the string to MESSAGE *moves an edit pattern to RESULT *immediate . These are not preceded by the equals signs and the two should not be confused. See the example in Figure 54 in Section Error: Reference source not found on page 132. The declarations for these constants will. you may also specify a count.=F'123' MVC MESSAGE. you permitted the literals to be placed at the end of the program. one which will extend beyond the range of any base and displacement combination.=C'Hello World' MVC RESULT. LOC+8. L R1. If you use the same literal more than once.=X'40202120' CLI LAB. The assembler keeps track of all the literal values and types your program has used. Thus. 10. however.no = sign Figure 20 Literals One reason for the LTORG directive has to do with base register addressing. Note: there is another form of notation for what are called immediate operands.In addition to the label and the data type. it will only be declared once. by default. they would be beyond the large data area and out of range of any base and displacement. Sometimes a program will need to use a very large data area. the literal is in the position of the memory operand of the load (L) instruction. So. Table 20 gives several examples. If. The effect of this is to load register 1 with a full word binary with the equivalent of the decimal number 123. You may use literal notation in an instruction in place of a label. A literal looks like a DC operand but is always preceded by an "=" sign. This is referred to as the literal pool. This is the number of items of the type you want to allocate. This is a shorthand notation which causes the assembler to make the declaration for you at another place in your program. if you say 18F you are asking for 18 fullwords. constants are not separately declared in DC statements but contextually with what are called literals. LOC+12.

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11 Linkage
Linkage refers to the set of conventions used by the operating system whereby programs call one another, pass arguments, and return values. The IBM mainframe still uses the original linkage conventions established when the machine was introduced in 1964 although there have been some additional modes added since then. For purposes of this text, we will deal with the legacy linkage as embodied in the SUBENTRY and SUBEXIT macros. Basically, linkage saves the contents of the calling program's registers in the calling program's save area, creates a local save area to be used by any programs our program calls, and sets up a base register. 11.1 Linkage Registers On entry into a subroutine, several registers have predefined contents as shown in Table 16.
R1 R13 R14 R15 Address Address Address Address of of of of a parameter list save area in calling program return point in calling program entry point in called program

Table 16 Linkage registers

The two main linkage registers are R14 and R15. R14 indicates where the called program is to branch to in the calling program in order to make a return. That is, when the subroutine is finished, it should branch to the address contained in R14. The calling program provides this. Secondly, R15 always contains the address of the entry point in the called program. Normally this is the address of the first instruction in the called program however some subroutines can have multiple entry points. In any event, R15 is the address of the first instruction to be executed. 11.2 Save Area Every program has a save area. A save area, as shown in Table 17, is an 18 full word (72 byte) area in which we place information that will be restored when the program completes as well as information helpful to debugging. When a subroutine starts, it immediately saves the contents of the general purposes registers (except R13) into the calling program's save area then it creates a save area of its own. The address of the calling program's save area will be in R13 upon entry. The code to save the calling program's registers and set up our local save area is in the SUBENTRY macro as shown in Figure 21 as copied from the assembler output file. The line numbers are from the assembler and the plus sign after each indicates that the code is from a macro expansion (non-macro code does not have a plus sign on the line number).
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Offset Word 0 4 8 12 16 20 24 28 32 36 40 44 50 54 58 62 66 70 Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Contents Address of calling program save area Address of called program save area Register 14 Register 15 Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Table 17 Save area

On line 3 we tell the assembler that this is the start of a control section and that it's name is ADD (from the label on the SUBENTRY). A CSECT is an assembler directive and does not generate code. On line 4 the STM (Store Multiple) causes registers R14, R15, R0, R1, … R11, R12 to be saved in successive 4 byte full words beginning at the fourth full word in the calling program's save area. Word 4 begins at offset 12 (see Table 17) from the start of the calling program's save area whose address is in R13 and thus the displacement of 12 past R13.
3+ADD 4+ 5+ 6+ 7+ 8+ 9+ 10+ 11+ 12+ 13+ CSECT STM BAL DC DC DC DC ST ST LR USING 14,12,12(13) 15,104(15) 18F'0' CL8'ADD' CL8'09/14/10' CL8'20.33' 15,8(13) 13,4(15) 13,15 ADD+8,13

Figure 21 SUBENTRY code

The next instruction, the BAL (Branch and Link), does two things: it causes a branch to the ST (Store) instruction on line 10 and it resets the contents of R15 to point to the first byte of the 18 full word save area immediately following it. The branch address is calculated by adding the contents of R15 and 104, the displacement. At the time it does this, R15 has the address of the STM in it (the first instruction of the program). The ST instruction at line 10 is 104 bytes from the beginning of the STM.

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But after the BAL calculates the branch address but before the actual branch, the BAL loads into the first operand, R15, the update address portion of the PSW, that is, the address of the byte immediately following the BAL. When an instruction executes, the address portion of the PSW always has the address of the byte immediately following the instruction. Normally, this is the address of the next instruction. In this case, however, it is the address of our (called) program's save area. At line 10, the ST instruction stores the address of our save area into the third word of the calling programs save area then stores the address of the calling program's save area in the second word of our save area. Thus, the calling program's save area points to ours and ours points to the calling program's save area. The contents of R15 (address of our save area) are copied to R13 and the assembler is told to use R13 as a base register and to assume that it is pointing at the 9th byte of the program (the 1st byte of the save area) which it is. You will note that after the 18 word save area are character fields containing the name of the CSECT and the date and time when it was assembled. Happily all this is done by the SUBENTRY macro. Like wise, the SUBEXIT macro reloads the calling program's registers and returns to the address contained in R14.

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64 .

12 Assist Macro Input/Output The overall issue of input/output on the s390 architecture also involves the underlying operating system and many other factors. and the man I And haughty Juno's u Expell'd and exil'd.5. Long labors.DONE XPRNT IN. 1 2 3 4 5 6 7 8 9 README LOOP PRINT NOGEN SUBENTRY XREAD IN. Expell'd and exil'd.20 BC B'1111'. forc'd by fate. left the Trojan shore.0_18 12:11:36 readme MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 42 IO=578 12:11:36 readme LZ390 START USING z390 V1. the simplified Assist pseudo instructions XREAD and XPRNT will be used. And the long glories of majestic Rome.01b ON J2SE 1. and built the destin'd town.6.01b ON J2SE 1. before he won The Latian realm. For purposes of this discussion.5.20 BC B'0100'. And haughty Juno's unrelenting hate. From whence the race of Alban fathers come. and the man I sing.XRD Arms.5.1 Input / Output using XREAD and XPRNT By default.6. And in the doubtful war.XPR extension and also appear in the console window. the XREAD pseudo instruction will read from a file with the same name as the file your are assembling but with the . who.0_18 Arms. Screen Output: C:\Documents and Settings\user>assist readme C:\Documents and Settings\user>echo off 12:11:36 readme MZ390 START USING z390 V1. Output will have the . Long labors. His banish'd gods restor'd to rites divine.01b ON J2SE 1. And settled sure succession in his line.XRD extension. both by And in the doubtful The Latian realm.0_18 12:11:36 readme LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=32 12:11:36 readme EZ390 START USING z390 V1.LOOP SUBEXIT DS CL20 END DONE IN README.6. both by sea and land. 12. an His banish'd gods re And settled sure suc From whence the race And the long glories 12:11:36 readme EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=30 INS=53 Figure 22 XREAD example 65 . he bore.

the Condition Code is set to 1. The LABEL is optional.LENGTH Where INFIELD is the area into which data will be read. the first operand designates the register to receive the number converted to signed binary and the second operand designates the address of a filed in memory containing the decimal character representation of the number.The general format of the XREAD is: XREAD INFIELD. those that exceed the length stated in the XREAD) will be truncated. This is an aid for debugging and discussed in greater detail in section 13. Note that the input line are truncated when printed. The number will be right justified with a leading minus sign if negative and padded to the left with blanks.3 below.D2(X2. 66 . Figure 13 gives an example. the floating point registers and the program memory segment to the standard output. 12. In the event of an error. Also note that the output.3 XDECO/XDECI These pseudo instructions are used to convert from internal binary numbers to character decimal representations and the reverse. The length is specified as either a constant or as a register enclosed in parentheses. On input. At end-of-file. the program aborts with an abend code of S013. the contents of the register at runtime will be the length.XPR 12. carriagereturn/line-feeds will be removed and short records will be padded with blanks (4016 in EBCDIC). The first operand is normal not machine register R1 as this register may be altered by the instruction. The address is specified in the same manner as a second operand in an RX instruction. Input lines are in ASCII but will be converted to EBCDIC. Long input records (that is. besides appearing on the screen. If specified as a register.D2(X2.2 XDUMP The XDUMP pseudo instruction will dump the contents of the general purpose registers.B2) In this case. is also placed in the file README. The XDECI has the format: LABEL XDECI R1. XDECO has the format: LABEL XDECO R1.B2) Where first operand designates the register containing the signed 32 bit binary number to be converted to printable decimal and the second operand gives the address of a 12 character field which will receive the converted number.

the instruction halts. The instruction scans the number until a non-decimal character is encountered (for example. R1 is set to the address of that character and the Condition Code is set to 3. If the first character is not numeric or a plus or minus sign. 12. a blank). Note: R1 in this case means the actual register 1. R1 is set to the first character which is not a digit. 67 . If there are more than 9 digits. not the first operand. however.XDECI scans the field. 1 if the number was less than zero and 2 if the number was greater than zero. the Condition Code is set to 3 and the first operand is unchanged.4 XHEXO/XHEXI These operations are similar to XDECO/XDECI except hexadecimal numbers are converted and there is no usage of either the plus or minus signs. The converted number is placed in the first operand and the Condition Code is set to 0 if the converted number was zero.

68 .

Initially we create the table of numbers as shown in Figure 23. Among these are binary integer. we will start with an initialized (i. we normally prefer to see numbers printed as decimal characters. Initially. we will need a register in which to do the calculations.mlc. however. floating point. we must examine the question of the internal representation of a number versus its external representation. Externally. Any activity involving numbers must convert between these formats when doing input or output operations. 1 2 3 4 5 6 7 8 9 10 11 12 ADD PRINT NOGEN SUBENTRY EQUREGS XPRNT MSG. We select a register in the range R2 through R12. First. however.MLC Step 1 MSG ONE TWO THREE FOUR FIVE In Figure 23 you can see we modified hello. A register is required because the integer arithmetic instructions are all of the RR or RX variety and.mlc as a starting point. one or both of the operands must be a register. 69 . This is because registers R0. the message (to Adding Numbers) and added five additional lines of storage declarations.e. Internally. not read in at run time) table of numbers between 1 and 5 decimal. add them and print the result.1 Program to Add Numbers As impressive as Hello World! was. computers represent numbers in several different formats. Since we are working with binary integers (the most common form of integer arithmetic programming).L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 23 ADD. Next we need to calculate the result. In this case we will select R2.. consequently. it can sometimes be altered by system calls and some instructions. and packed decimal. it can't compare with the thrill of actually doing arithmetic or some other ostensibly useful computational activity.13 Integer Arithmetic 13. Our program will be called add. R2 is a good choice but be careful. The total storage allocated is 20 bytes.mlc to change the name (to ADD). R1 and R13 through R15 have significance with regard to linkage. Each of the storage declarations creates a full word (4 bytes) whose contents are the binary equivalent of the decimal numbers in the quoted fields. The program will borrow from hello.

L'MSG SUBEXIT DC C'Adding Numbers' DC F'0' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 24 ADD. Next we need to add each of the values into R2.ZERO *Zero R2 XPRNT MSG. 70 . 1 2 3 4 5 6 7 8 9 10 11 12 13 ADD PRINT NOGEN SUBENTRY EQUREGS L R2. fullword aligned) from the memory address specified by the second operand into the register specified as the first operand. To do this. It is an RX instruction and the memory address is calculated using the Base.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 25 ADD. The SR instruction subtracts the contents of the register specified as the second operand from the contents of the register specified as the first operand and leaves the result in the first operand. Obviously we first need to put zero into the register. The L instruction loads the full word (4 bytes. One way is to load a full word constant zero into the register. This would use a 4 byte Load instruction and require a 4 byte constant in memory as shown in Figure 24. we could use a literal as shown in Figure 25 but this is really the same thing as the assembler merely makes the storage declaration for us (it will appear in the .MLC Step 3 MSG ONE TWO THREE FOUR FIVE The preferred alternative is to simply subtract the register from itself as shown in Figure 26. This is the quickest and uses the least memory (2 bytes).R2 will be out accumulator.=F'0' *Zero R2 XPRNT MSG. we use five Add (A) instructions as shown in Figure 27.MLC Step 2 MSG ZERO ONE TWO THREE FOUR FIVE Alternatively. Displacement and Index method. This can be done in two ways. That is.prn file). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADD PRINT NOGEN SUBENTRY EQUREGS L R2. we will add each of the values into it until it has the final total and then we will print the total.

1 2 3 4 5 6 7 8 9 10 11 12 13 ADD MSG ONE TWO THREE FOUR FIVE PRINT NOGEN SUBENTRY EQUREGS SR R2.THREE A R2.ONE A R2.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 27 ADD. This format means character length 12 or. one character string with a length attribute of 12.R2 *Zero R2 XPRNT MSG. However. XDECO takes the place of several actual instructions (CVD and EDIT) which will be discussed below.TWO A R2. To print it we need to convert it from binary to decimal characters.L'MSG SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' END Figure 26 ADD.FOUR A R2. this later notation 71 . Another way of allocating it would be an operand of 12C which means 12 character strings of length one (implied default length of a character). XDECO is a pseudo RX instruction in the Assist package that converts the signed binary integer in the register specified as the first operand to a 12 byte signed right justified decimal character (zoned decimal) representation padded to the left with blanks and placed in the 12 bytes of memory beginning at the address specified as the second operand. Note the operand on the DS statement labeled DBL.R2 *Zero R2 A R2.FIVE XPRNT MSG. In the z390 emulator the address of the 12 byte field need not be aligned. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2. The Assist package has a convenient instruction that does this for us named XDECO as shown in Figure 28. We need to print it.MLC Step 5 MSG ONE TWO THREE FOUR FIVE At the end of the Add instructions the answer is in R2 in binary format.MLC Step 4 The A instruction is an RX instruction that adds the full word aligned binary value from memory at the address specified as the second operand to the value in the register specified as the first operand and leaves the result in the first operand.

the starting byte of each line of code in the machine language image being created.MLC Step 5 MSG ONE TWO THREE FOUR FIVE DBL Running the code from Figure 28 results in the output shown in Figure 29 (long lines truncated).6.0_18 13:13:22 add LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 15 IO=35 13:13:22 add EZ390 START USING z390 V1. relative to zero.6.TWO A R2.L'MSG XDECO R2.FOUR A R2. 3.6.0_18 13:13:21 add MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 43 IO=733 13:13:22 add LZ390 START USING z390 V1. 1.01b ON J2SE 1. relative to zero.R2 *Zero R2 A R2.01b ON J2SE 1.5. The value of L'DBL would be 1. Column labels have been added at the top which do appear in the actual PRN file. It is in hexadecimal and gives.DBL XPRNT DBL. 12 would be the repetition count.prn now contains some interesting information as shown in Figure 30 (some parts now shown). Column 3 is the effective address. C:\Documents and Settings\user>echo off 13:13:21 add MZ390 START USING z390 V1.FIVE XPRNT MSG. not 12.would not work with the L'DBL figure in the XDECO. 2. of the first operand if the first operand is a memory address. Column 2 is also in hexadecimal and is the translation of the assembly language statement up to the first 8 bytes.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Figure 28 ADD.01b ON J2SE 1.MLC Step 5 13. not the length. 72 .ONE A R2.5.THREE A R2.5.2 Analyzing the PRN File The file add.0_18 Adding Numbers 15 13:13:22 add EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 19 IO=22 INS=20 Figure 29 ADD. Column 1 is what is known as the location counter. There are several things to take note of. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2.

The first byte (5A) is the opcode as shown in Figure 30. 5. Look at the line with the location counter value of 72 (leading zeros omitted). 6. Column 5 indicates the macro level. Hence. Col 3 Col 4 Col 5 (1/1)1 (1/2)2 (1/3)15 (1/4)33 (1/5)34 (1/6)35 (1/7)36 (1/8)37 (1/9)38 (1/10)39 (1/11)40 (1/12)41 (1/13)42 (1/14)49 (1/15)50 (1/16)51 (1/17)52 (1/18)53 (1/19)54 (1/20)55 (1/21)56 Col 6 ADD PRINT NOGEN SUBENTRY EQUREGS SR R2. Since a hex digit corresponds to four bits. Note that the location counter jumped from zero at the beginning of the program to 72 following the SUBENTRY. the first hex digit (2) is the first operand and the second hex digit (2) is the second operand.4. This is because the SUBENTRY macro used 72 bytes. Thus we get the hexadecimal machine language 5A20D0B0 16. As all RR instructions are two bytes in length. relative to zero.ONE A R2.TWO A R2.R2. With regard to the second byte. The opcode is 1B as determined from Table 20 on page 135.FIVE XPRNT MSG.1 above). the first operand is designated by the first four bits and the second operand by the second four bits.FOUR A R2. as is the case with nearly all RX instructions except the BC.ONE which says to fetch the 4 bytes beginning at the label ONE and add them to the 4 bytes in register R2. has the format shown in section 6. Column 6 contains your original card images. of the second operand if the second operand is a memory address. The next instruction is A R2. leaving the result in R2. the code 1B2216 is the result of SR R2.3.THREE A R2. the format consists of one byte (2 hex digits) containing the opcode and one byte containing the operands (see section 6.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Col 2 1B22 5A20D0B0 5A20D0B4 5A20D0B8 5A20D0BC 5A20D0C0 E020D0A2000E 5220D0C4 E020D0C4000C C1848489958740D5 00000001 00000002 00000003 00000004 00000005 0000B8 0000BC 0000C0 0000C4 0000C8 0000AA 0000CC 0000CC MSG ONE TWO THREE FOUR FIVE DBL Figure 30 ADD. the location counter advanced by 2 from 72 to 74. The Add instruction is an RX instruction and.DBL XPRNT DBL. The code 1B22 is represents the SR instruction. original line number.L'MSG XDECO R2.R2 *Zero R2 A R2. Col 1 000000 000000 000072 000072 000074 000078 00007C 000080 000084 000088 00008E 000092 000098 0000AA 0000B8 0000BC 0000C0 0000C4 0000C8 0000CC 0000D8 Column 4 is the effective address.PRN Column 2 for a line containing an instruction is the translation of that instruction to machine language. As an RR instruction.3.2 above. The next byte contains the first operand 73 . and actual line number taking into account macro statements.

This is how R13 gets the value 8. when the assembler see the label ONE in the Add instruction. Consequently. Hence we see a displacement of 0B016 and a base register of R13 in the machine code. 74 . The index register remains. Then the memory at label ONE will be at 1 000 0B816 or R13+B016. There is an R0 and you can use it for arithmetic but if you use it in an address it means no value is contributed regardless of the actual value in R0. the address of ONE will be the sum contents of R13 plus B016 (or 17610). The SUBENTRY macro expands the same each time except for the program name which it gets form the label on the invocation and the time and date which it gets from the assembler. the index register in an address will be R0 unless you explicitly use it (see below for an example). First. in the BAL on line 4. if the program is loaded beginning at location 1 000 00016 everything will work so long as R13 has 1 000 00816 in it. So how does the assembler know to use R13 as the base register? Line 12 in Figure 4 tells the assembler that R13 is the base register. When R0 is used in an addressing context it means no register. correctly. Then on line 11 the LR instruction copies this value to R13 (note: the systems macros use ordinary numbers for the registers. USING is a directive that does not generate code but tells the assembler something it needs to know. The full displacement is 0B0 16 or 17610. Next question. It shows the expansion of the SUBENTRY macro. ADD+8. it calculates. Several things happen here. not numbers preceded by the letter R). So the question becomes. Thus.R13) In response to our second operand label of ONE. Normally. what's in R13? If you look at the location counter you will see that ONE is at location B816 from the start of the program but the displacement relative to the contents of R13 is B016. in the case of our program. In this case the USING is telling the assembler that R13 is the base register and that it is pointing to the 8th byte of the program which is HELLO+8 or.176(R0. In fully explicit notation. R13 must have 8 in it? Look at Figure 4 on page 25. Thus the assembler knows that R13 can be used as a base register and that it is pointing 8 bytes into the program. It is specified as R0. Thus. The program can be loaded anywhere in memory because all the addresses are relative to R13. this would correspond to: A R2. that the label is B0 or 176 bytes from the 8th byte of the program. This means that when the program is run. R15 is effectively loaded with the location counter value of 8. the assembler has calculated the address of ONE is at a displacement of B016 (leading zero omitted) relative to the contents of register 13. The third byte has the base register (D or R13) and the first 4 bits of the displacement (0). will our program will be loaded into the computer memory at location zero every time? No.(2) and the index register (0).

the high order 32 bits of all the general purpose registers are F4. Alternatively. a programmer can explicitly request a dump with the XDUMP macro during program execution in order to analyze program execution. Where there is no printable character for a byte code. 2.3 Debugging (XDUMP) A dump is ordinarily produced when a program encounters a run time exception or interrupt. it loads the address of the byte immediately following the BAL into R15 and R15 is eventually copied to R13. RE (R14) and RF (R15). R2 and R3 while the last line displays the contents of registers RC (R12). For example. therefore. Where the byte code has a printable equivalent. the printable equivalents are not meaningful. As none of the floating point registers were used. all of their bytes are shown as F4. For example. if the program from Figure 28 were modified to include the XDUMP as shown in Figure 31 (shown as the . a period is printed.PRN file with macro expansion printing enabled). the result would be the text shown in Figure 32 (long lines truncated). Each group or 8 digits corresponds to one word (4 bytes) of memory and they are separated from one another to improve readability. 3. A similar pattern is shown for the floating point registers (F0 through FF). 75 . The contents of the dump are as follows: 1. On the right hand side is an attempted conversion of each byte in the row to a printable character. R1. 13. The contents of memory beginning at location 0000000016 through location 000FFFFF16. The contents of the 16 64-bit general purpose registers R0 through RF (R15). it is shown. how does R13 get 1 000 00816 in it? When the BAL instruction on line 4 of Figure 4 executes. In most cases. As the program only used 32 bit instructions and since the emulator preinitializes each byte of each register to F4. Each line. if the program is loaded into memory beginning at 1 000 00016 the byte immediately following the BAL will be at address 1 000 00816. RD (R13). the first line for the general purpose registers displays R0. The low order bits are F4 unless the register was used in the course of the program. The contents of the memory are shown in rows of 32 hexadecimal digits grouped into four fields of 8 digits each. There are four registers displayed per line. displays 16 bytes of memory. So.So. The contents of the 16 64-bit floating point register F0 through FF (F15). The contents of the general purpose and floating point registers are each displayed as 16 hexadecimal digits (corresponding to 8 bytes). At the beginning of each row is the address of the first byte in the row.

12.* means that it is the dump of the 16 memory locations beginning at 260016 through 260F16 inclusive (16 bytes of data).104(15) (2/169)6+ DC 18F'0' (2/170)7+ DC CL8'ADD' (2/171)8+ DC CL8'09/14/10' (2/172)9+ DC CL8'20.12(13) (2/168)5+ BAL 15.FIVE (1/10)39 XPRNT MSG. 76 .FOUR (1/9)38 A R2.13 (1/3)15 EQUREGS (3/41)16+R0 EQU 0 (3/41)17+R1 EQU 1 (3/41)18+R2 EQU 2 (3/41)19+R3 EQU 3 (3/41)20+R4 EQU 4 (3/41)21+R5 EQU 5 (3/41)22+R6 EQU 6 (3/41)23+R7 EQU 7 (3/41)24+R8 EQU 8 (3/41)25+R9 EQU 9 (3/41)26+R10 EQU 10 (3/41)27+R11 EQU 11 (3/41)28+R12 EQU 12 (3/41)29+R13 EQU 13 (3/41)30+R14 EQU 14 (3/41)31+R15 EQU 15 (1/4)33 SR R2. the address will increment by 1016..33' (2/173)10+ ST 15.13) (4/51)46+ L 14.28(13) (4/53)48+ BR 14 (1/15)50 MSG DC C'Adding Numbers' (1/16)51 ONE DC F'1' (1/17)52 TWO DC F'2' (1/18)53 THREE DC F'3' (1/19)54 FOUR DC F'4' (1/20)55 FIVE DC F'5' (1/21)56 DBL DS CL12 (1/22)57 END Figure 31 Add program exposed Thus... the following line: 00002600 *F0F961F1 F461F1F0 00000000 00000000* *09/14/10.TWO (1/7)36 A R2.13) (4/52)47+ LM 2. Because each line has 1016 (1610) bytes of data. The remaining 8 bytes did not have printable equivalents as indicated by the periods.ONE (1/6)35 A R2..DBL (1/12)41 XPRNT DBL.THREE (1/8)37 A R2. It tells us that the first eight bytes of the line's content correspond to the characters: 09/14/10 which appears to be a date..12(.4(15) (2/175)12+ LR 13.L'MSG (1/11)40 XDECO R2. On the far right column is the attempted character interpretation of the bytes.8(13) (2/174)11+ ST 13..0 (4/50)45+ L 13.12.000000 000000 000000 000000 000004 000008 000050 000058 000060 000068 00006C 000070 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000072 000074 000078 00007C 000080 000084 000088 00008E 000092 000098 00009E 00009E 0000A2 0000A6 0000AA 0000AE 0000B0 0000C0 0000C4 0000C8 0000CC 0000D0 0000D4 0000E0 90ECD00C 45FF0068 0000000000000000 C1C4C44040404040 F0F961F1F461F1F0 F2F04BF3F3404040 50FD0008 50DF0004 18DF 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 00000A 00000B 00000C 00000D 00000E 00000F 1B22 5A20D0B8 5A20D0BC 5A20D0C0 5A20D0C4 5A20D0C8 E020D0A8000E 5220D0CC E020D0CC000C E06000000000 41F00000 58D0D004 58E0D00C 982CD01C 07FE C1848489958740D5 00000001 00000002 00000003 00000004 00000005 0000C0 0000C4 0000C8 0000CC 0000D0 0000B0 0000D4 0000D4 (1/1)1 PRINT GEN (1/2)2 ADD SUBENTRY (2/77)3+ADD CSECT (2/167)4+ STM 14.R2 *Zero R2 (1/5)34 A R2.15 (2/188)13+ USING ADD+8.4(..L'DBL (1/13)42 XDUMP (1/14)43 SUBEXIT (4/33)44+ LA 15.

.... 15* 000080E0 *00000000 000F7F20 859999F1 4BF3F9F0* *............* 00000020 *00000000 00000000 00000000 00000000* *.?* 00008070 *18DF1B22 5A20D0B8 5A20D0BC 5A20D0C0* *............* 00002310 *00000000 00000000 00000000 00000000* *.............\...............52 &┘.* .* 00002080 *00000000 00000000 00000000 00000000* *.....5555555* 00008100 *80008000 000000E0 00000000 000F7EF8* *╪..... 00008050 *C1C4C440 40404040 F0F961F1 F461F1F0* *ADD 09/14/10* 00008060 *F1F74BF5 F2404040 50FD0008 50DF0004* *17.......╪....a?.?& ..* .....?* 000080D0 *00000005 40404040 40404040 4040F1F5* *...?.Ω?* 00008090 *D0CCE020 D0CC000C E0600000 000041F0* *}÷\?}÷......0_18 17:52:04 err1 LZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 14 IO=36 17:52:04 err1 EZ390 START USING z390 V1....* .......6...01b ON J2SE 1......C:\Documents and Settings\user\asm>assist err1 C:\Documents and Settings\user\asm>rem assemble...* 00002020 *00000000 00000000 00000000 00000000* *.* 00002150 *00000000 00000000 00000000 00000000* *... 00000040 *00000000 00000000 00000000 00002000* *....................╪\..... 00002300 *00002304 00000000 00000000 00000000* *....á0* 000080A0 *000058D0 D00458E0 D00C982C D01C07FE* *...╪..* 00000010 *00002000 00000000 00000000 00000000* *...* ..............5.......* . 000020D0 *000080E0 00000000 00000000 00000000* *.................................╪?... 000FFFF0 *F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5* *5555555555555555* 17:52:05 err1 EZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 21 IO=79 INS=21 Figure 32 . 00002600 *F0F961F1 F461F1F0 00000000 00000000* *09/14/10. 00008000 *90ECD00C 45FF0068 00000000 00002100* *░╓}..........390* 000080F0 *80008000 F5F5F5F5 01F5F5F5 F5F5F5F5* *╪...╪..??. 00002100 *00000000 00000000 80008008 00002018* *.?...Dump format 77 ...╟........... and exec ASSIST C:\Documents and Settings\user\asm>echo off 17:52:04 err1 MZ390 START USING z390 V1......║.....?..* 00002110 *80008000 80008000 00002300 F4F4F4F4* *╪. 00002140 *F4F4F4F4 F4F4F4F4 00000000 00000000* *44444444.......q?}.."?err1..╪.. link......* 00002610 *00000000 00000000 859999F1 40404040* *.6....01b ON J2SE 1.......err1 * 00002620 *00000000 00000000 00000000 00000000* *.....0_18 17:52:04 err1 MZ390 ENDED RC= 0 SEC= 0 MEM(MB)= 43 IO=737 17:52:04 err1 LZ390 START USING z390 V1.......* .....?........01b ON J2SE 1.ß?...5...* ..\-.5555..?............4444* 00002120 *F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4* *4444444444444444* .....................* 000020E0 *00000000 00000000 00000000 00000000* *.....╪............... 00002000 *859999F1 40404040 40404040 40404040* *err1 * 00002010 *00008108 00000000 0A030000 00000000* *.... ??!?}╜!?}»!?}{* 00008080 *5A20D0C4 5A20D0C8 E020D0A8 000E5220* *!?}D!?}H\?}y.5........∞}}?∞\}...........* .....0_18 Adding Numbers 15 R0-R3 F4F4F4F480008000 F4F4F4F400002300 F4F4F4F40000000F F4F4F4F4F4F4F4F4 R4-R7 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 R8-RB F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 RC-RF F4F4F4F4F4F4F4F4 F4F4F4F480008008 F4F4F4F400002018 F4F4F4F480008008 F0-F3 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4-F7 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F8-FB F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 FC-FF F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 00000000 *00000000 00000000 00000000 00000000* *..........⌂┌* 000080B0 *C1848489 958740D5 A4948285 99A2F6F6* *Adding Numbers66* 000080C0 *00000001 00000002 00000003 00000004* *.* 00008010 *00000000 00000000 00000000 00000000* *... 00002070 *00000000 9B000000 00000000 00000000* *.╪..* .............6..=8* 00008110 *F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5* *5555555555555555* ....?.* 00000050 *00000000 00000000 00000000 00000000* *.

F (R15) is the B2 field (base register). Details on subroutine linkage are given in section 11 above.R3. E (R14) is in the R1 field. the label DBL is . In the memory dump area. 201816 and register 15 has the same contents as R13. all programs will appear to begin at location 800016. If you look in the dump at address 800016 you will see the code for the STM instruction. 0 (R0) is the X2 (index register) field and 06816 is the D2 field (displacement in hex). In fact.From Figure 31 we can see that the first executable instruction is: STM 14.2 above. as expected. D (R13) is in the B2 field and 00C16 is in the D2 field. This can be deduced from the location counter address from the assembler for DBL which is D416. because of the emulator. C (R12) is in the R3 field. R13.D2(B2) The opcode is 9016. the first byte of the program. The 12 bytes beginning at label DBL can be seen to start at byte 80D416. are 8000800816 (High order bit is 1 but only the lower 31 bits are used for addressing). R14 has the return address.. therefore..12(13) which corresponds to the machine code: 90ECD00C An STM instruction is a Store Multiple and it is of type RS: STM R1.. Note that R2 has 15 (F16) in it which is the answer from the calculations. Since the program is loaded at location 800016. therefore. F (R15) is the R1 field. at 80D416. the presence of "…. This corresponds to the address of the start of the save area as described in section 11. Looking at the general purpose registers you can see the contents of the base register." in the address column means the missing lines are the same as the line above.104(15) which is the Branch and Link RX instruction and translates into the machine language: 45FF0068 Where 45 is the opcode.12. 78 . Moving on.. the next instruction following the STM is: BAL 15. 800016 is. In the instruction in the program.

13. to increment it and we need a loop mechanism. The purpose of the Compare instruction is to set the Condition Code. To do the test. Thus. For a register. Here only one label (ONE) is used for each of the second operands but with an increment that takes into account the number of bytes from the label ONE to the desired operand. 13. In Figure 34 we've selected R3 for our loop index register which we initially set to zero. we also need a way to test if we are done and loop if we are not. Thus. THREE. We've added a new label: LOOP which is where we'll branch to until we've added all the numbers. An alternative. few programmers would code as shown in either Figure 28 or 33 . The body of the program begins with the SR at 807216 followed by the Add instructions. TWO. we can select any register not otherwise in use except R0. which generates identical machine language.4 Data Addressing Alternatives The program in Figure 28 used several labels. 79 . 80C816. In Figure 33 the offsets from the label ONE become added to the displacement. 80C416. In the Add instruction following LOOP we increment the index register (R3) by 4 (using literal notation) then we compare the contents of R3 with the value 16 (again.at least not for any significant number items to be added.The full words for labels ONE.5 More Addressing Alternatives In reality. Using the dump and the assembler listing. the actual machine code is identical to that in Figure 28. Each DC statement generates exactly 4 bytes of data and these are arranged at consecutive memory locations. a loop would be used with a register that incremented by 4 for each iteration and its values added to a base address. To loop. can be seen in Figure 33. you will normally be given the address contents of the PSW at the time of the failure. need to initialize it. 80CC16 and 80D016. If your program fails. the actual problem is normally at the instruction preceding the address in the PSW. we will use the Compare instruction. it should be easy to locate where the error took place and determine how it was caused. For the loop mechanism. To do this we need an additional register. that is. As the PSW is always updated. the next at ONE+8 and so one. we will use a Branch Conditional (BC) instruction. FOUR and FIVE can be seen at 80C016. pointing at the next instruction. Instead. using literal notation). There are several ways to do this but the obvious one is to used the index register in the Add instruction (presently R0 meaning no register). the 4 bytes following label ONE are at ONE+4.

When the contents of R3 exceed 16. the XPRNT (line 10). the branch will not take place the the instruction following the BC instruction. The BC instruction will branch if the Condition Code is 0 or 1 as indicated in Chapter 8. The initializes R2 to 0 and R3 to 1 (lines 4 & 5). 80 . 13.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ADD MSG ONE DBL PRINT NOGEN SUBENTRY EQUREGS SR R2. It is a program to sum the integers from 1 to 100. Note: if you do not include a LTORG. They are.MLC .R2 *Zero R2 A R2.ONE+12 A R2. If the contents of R3 are equal to 16. the assembler will place any literals it has accumulated at the end of your program anyway.ONE+16 XPRNT MSG.ONE A R2. These will include the =F'4' and =F'16' used above. will execute. assembler generated DC statements.ONE+8 A R2. It adds R3 to R2 then increments R3 (lines 6 & 7).ONE+4 A R2.DBL XPRNT DBL. The LTORG directive at the end tells the assembler to place any undeclared literals at this place in your program. in effect.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 END Figure 33 ADD1. Then it tests R3 against the value 100 (line 8) and branches (line 9) back to LOOP if the contents of R2 are less than 101 or falls through to the next instruction (XDECO) when the contents of R3 become equal to 101. the Condition Code is set to 1. the Condition Code is set to 0. If contents of R3 are less than 16.6 Using Extended Mnemonics Figure 35 is a related example.L'MSG XDECO R2.Alternative 1 In the BC instruction (line 9) we tell the computer to branch to label LOOP if the Condition Code indicates that the Compare instruction (line 8) found that the value in R3 was less than or equal to 16.

=F'4' C R3.=F'1' * init R3 AR R2. They help make your program more readable but are.ONE(R3) A R3.=F'16' BC B'1100'.R3 *Zero R3 A R2. in reality.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ADD LOOP MSG ONE DBL PRINT NOGEN SUBENTRY EQUREGS SR R2.R2 *Zero R2 SR R3. There are several of these forms accepted by the assembler as shown in Table 9 on page 46.Alternative 2 In Figure 35 we see another form of the BC instruction is used: the extended mnemonic form. no different than the BC instruction with the appropriate mask.DBL XPRNT DBL.L'DBL SUBEXIT DC C'Adding Numbers' DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' DS CL12 LTORG END Figure 34 ADD2.R3 A R3.DBL XPRNT DBL.R2 * zero R2 L R3. BL on line 9 is really a BC with a mask of B'0100'.=F'101' BL LOOP XDECO R2.MLC .=F'1' * increment R3 C R3.L'DBL SUBRETURN LTORG DS CL12 END Figure 35 Loop example 81 .LOOP XPRNT MSG. 1 2 SUM100 3 4 5 6 LOOP 7 8 9 10 11 12 13 14 DBL 15 PRINT NOGEN SUBENTRY REGS SR R2.L'MSG XDECO R2.

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14. When a LH is executed. The S instruction is of type RX and the SR is of type RR. AH. The value in memory is unchanged. Both operate on 32 bit signed (2s complement) binary integers. S. Both subtract the contents of the second operand from the register specified as the first operand leaving the result in the first operand. Similarly. AR.1 Subtraction Similar to the A and AR instructions are the Subtract S and SR instructions. the low order 16 bits of the register are stored in memory at the address specified by the second operand. The first operand is treated as a 32 bit signed binary integer. the 2 bytes from memory are loaded into the low order two bytes of the register and then the sign bit of the value from memory is extended to the high order 16 bits of the register.2 Halfword Instructions In addition to full word Add and Subtract.14 Other Binary Arithmetic Instructions 14. there are also halfword RX versions of these: AH and SH along with the utility instructions Load Halfword (LH) and Store Halfword (STH). In the case of a STH. The second operand is a 2 byte location in memory. Result zero < zero > zero overflow Condition Code 0 1 2 3 Table 18 Conditions Codes 14. SH and SR can encounter situations where the result of the operation would overflow the register.3 Condition Codes After Binary Operations All signed arithmetic add and subtract instructions set the Condition Code to indicate the result of the operation as shown in Table 18. the 2 bytes from memory are expanded to 32 bits by extending the sign before the operation with the register takes place. 14.4 Overflows The signed arithmetic instructions A. when a SH or AH is executed. The first operand of each of the halfword instructions is a register. This happens in 32-bit addition when the result exceeds the maximum allowed for a 83 .

signed positive 32 bit number (+2,147,483,647) or the minimum allowed for a signed negative 32 bit number (-2,147,483,648). Overflows can also occur with the Shift Left Arithmetic (SLA) and Shift Left Double Arithmetic (SLDA) instructions when a bit unlike the sign bit is shifted into the sign bit position (the high order bit). As this would result in a sign change, it is considered to be an overflow. When an overflow occurs, the Condition Code is set to 3 and a fixed-pointoverflow exception interrupt is raised. This normally results in program termination unless bit 20 of the PSW is on in which case the interrupt is disallowed. 14.5 Unsigned Arithmetic (AL, ALR, SL, SLR) The architecture provides for unsigned arithmetic in the form of the Add Logical (AL and ALR) and Subtract Logical (SL and SLR) instructions. All four instructions treat both operands as unsigned 32 bit binary integers. The AL and SL instructions are of the RX type with the first operand the contents of a register and the second the contents of a specified memory address. In the ALR and SLR instructions, both operands are memory resident. As with the other Add and Subtract instructions, the result is placed in the first operand. An overflow cannot occur as a result of these instructions. Instead, the Condition Code indicates if a carry took place as shown in Table 19.
Condition code zero, no carry 0 not zero, no carry 1 zero, carry 2 not zero, carry 3 Table 19 CC after logical add/subtract Result

This information can be used to construct extended precision binary integer arithmetic. 14.6 Multiply (M, MR) The basic binary integer multiply instructions are the M and MR. In both, the first operand specifies the even register of an even/odd pair of registers. The multiplicand is a 32 bit signed integer which resides in the odd register of the pair. The multiplier is a 32 bit signed integer which resides either in the register designated as the second operand (MR) or at the memory address specified (M). The contents of the even register are ignored. The result is a 64 bit signed binary number which is placed in the even/odd register pair with the high order 32 bits or the result in the even register and the low order 32 bits in the odd register. The sign of the result is determined by rules of algebra except a zero result is always positive. No overflow can take place and the Condition Code remains unchanged.
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There is also a MH instruction where a 16 bit signed number from memory is multiplied by the 32 bit signed contents of the register specified as the first operand. The low order 32 bits of the result replace the contents of the first operand. No overflow can occur and the Condition Code remains unchanged. For example, If R5 contains 2010 and R6 contains 310, we can multiply them with the instruction:
MR R4,R6

The result will be in R4 and R5. As the answer is 6010, the result is effectively in R5. R6 will contain results only in the case when answers exceed 32 bits. 14.7 Divide (D, DR) The basic binary integer divide instructions are D and DR. In both, the register specified as the first operand, the dividend, is the even register of an even odd pair. Both registers are treated as one 64 bit signed binary integer with the high order part of the number in the even register. The divisor is a 32 bit signed number located in the register specified as the second operand (DR) or at the memory location specified by the second operand address. The result consists of a remainder located in the even register of the first operand and the quotient located in the odd register. The sign of the of the quotient is determined by the rules of algebra and the remainder has the same sign as the divided except that zero is always positive. A divide by zero will raise a fixedpoint divide exception. The condition code is unchanged. For example, if location VAR1 contains the 32 bit number 10, and location VAR2 contains the 32 bit number 3, you can divide the value at VAR1 by the value at VAR2 with the following:
L R2,VAR1 SRDA R2,32 D R2,VAR2

The result will be 1 in R2 (the remainder) and 3 in R3 (the quotient). Because all 64 bits of the even/odd pair R2/R3 participate, we load the dividend into the even register and then do a shift double arithmetic to the right by 32. In the SRDA instruction, both registers of the even odd pair participate. Effectively, we are loading the dividend into the odd register but insuring that the even register will contain bits like the sign bit of the dividend. See section 17.3.2 Arithmetic (SRA, SRDA, SLA, SLDA) on page 100 for full details on the arithmetic shift instructions.

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and so on.1. the length is expressed as an 8 bit field whose value is one less than the actual length to be moved. In the case where no length is supplied.1. The addresses may overlap.2 Move Immediate (MVI) The MVI (Move Immediate) instruction copies the immediate byte from the instruction to an address in memory.L2 *20 bytes from L2 are copied to L1 *10 bytes from L2 are copied to L1 LA R2.L1 is made * all blanks CL20 C'ABCDEFGHIJKLMNOPQRST' Figure 36 MVC Examples 15.=C' ' L1+1(19).L1 LA R3. These were extended in later versions of the architecture but we begin with the most basic.R2).R2). the actual length is coded (one will be subtracted from this value in constructing the machine language representation).see Figure 15 on page 39).0(R3) * 20 bytes from L2 are copied to L1 10(10. Thus. In the assembly language representation. Some examples are given in Figure 36. In the machine language coding of an MVC (as is also the case with other SS character instructions . It is an SS instruction and copies up to 256 bytes form the operand specified as the second to the operand specified as the first address. 15.1 Moving Characters (MVC) The basic character move instruction is the MVC instruction.L1 * blank is copied to the 1st byte of L1 * overlapped move . the second operand is a single byte contained in the 87 .L2 MVC MVC * MVC MVC * L1 L2 DS DC 0(20. in the machine language format.0(R3) * 10 bytes from L2 are copied to L1 * beginning at position 10 in L1 L1(1).15 Character Instructions 15.1 Basic Character Instructions The basic architecture has several instructions to compare and move strings of character data. In SI (storage immediate) instructions (see Figure 14 on page 38). the implied length attribute of the first operand is used.L2 L1(10). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MVC MVC L1. a length value of 0 means move 1 byte and a length value of 255 means move 256 bytes.

If the length is not specified.L3 * CC will be 2 CLC L1(3). they are compared one by one as unsigned 8 bit bytes. C'A' and never =C'A'). If all bytes are found to be equal. If the byte from the first operand 88 . As with the MVC. It is never a literal (for example. It is an SS format instruction using a single 8 bit length field as shown in the format in Figure 15 on page 39. is not possible.1.L2 * CC will be 0 . the second operand actually appears in the machine format before the first operand as shown in Figure 14 on page 38. and so forth). the length encoded in the machine language format is one less than the actual length.X'C1' L1.instruction. The first operand greater than the second.193 * * * * sets sets sets sets byte byte byte byte at at at at L1 L1 L1 L1 to to to to be the letter A A (C1 is hex for A) A (binary code for A) A (decimal equivalent) Figure 37 MVI Examples Note that the scond operand of the CLI is always a constant. when writing in assembly language.L2 * CC will be 1 CLC L1.B'11000001' L1. The instruction compares successively each corresponding byte of each operand (first with first. MVI MVI MVI MVI L1. the condition code is set to 0 and the instruction halts. 15. The condition code is set to indicate the result: CC=0 CC=1 CC=2 CC=3 All bytes in both operands are equal. However.3 Compare Logical Characters (CLC) The basic instruction for comparing strings of bytes is the CLC (compare logical character)instruction. When characters are compared. the instruction halts and the condition code is set to reflect the inequality. The first operand less than the second.only 3 bytes compared L1 L2 L3 DC C'ABCDEF' DC C'ABCDEX' DC C'ABCDEA' Figure 38 CLC Examples If the instruction encounters an unequal pair of bytes. the second operand appears second.C'A' L1. The byte with the larger absolute value is considered the greater of the two. The instruction continues so long as the bytes compared are equal. second with second. the assembler will use the length attribute of the first operand. CLC L1. This is called the immediate operand and is designated as I2 in the instruction set description. Figure 37 has some example. Because of the EX instruction.

Alternatively.1. otherwise. the first interrupt might be overwritten by the second. 15.C'A' In this case. The IBM 370 architecture introduced the CLCL and MVCL instructions with a string length limit of 224-1 (16 MB). The string length was said to be based on the maximum amount of time an instruction could execute on a low end version of the IBM 360 without the possibility of missing an interrupt.1 Compare Logical Character Long (CLCL) The CLCL instruction is an RR instruction. Both operands must designate the even register of an even-odd pair. should more than one interrupt take place while they are executing. For example: CLI XXX. Up to 16M bytes can be compared. if needed. The odd register of the first operand contains the first operand's length expressed in the low order 24 bits of the odd register.is less than the byte from the second operand. The instruction compares the bytes beginning at the address specified by the even register of the first operand (R1) with the bytes at the address specified by the even register of the second operand (R2).1 Compare Logical Immediate (CLI) The first one. the following has the same effect: CLI XXX. The odd register of the second operand contains an 8 bit padding byte followed by a 24 bit length. In the original architecture.2. compares one byte in memory with the instruction's immediate byte and sets the condition code accordingly. the CLC and MVC instructions were limited to character strings no longer than 256 bytes. 15. The condition code is set to reflect the relationship. 15. Both the MVC and CLC are uninteruptable and.3. the byte in memory at label XXX is compared with the immediate byte containing the EBCDIC code for the letter A. This is no longer an issue.X'C1' where the hexadecimal code C116 is the equivalent of the letter A. 2. Figure 38 gives examples. The shorter operand is considered to be extended to the right by the padding byte. the condition code is set to 1. CLI. Comparison is byte by byte.2 Character Long Instructions Two instructions were added to the architecture when the IBM 360 evolved into the IBM 370. These are the CLCL (compare logical character long) and MVCL (move character long). 89 .

15. The Condition Code is 3 and no copying is performed if a destructive overlap is detected. If all tested bytes are zero. 90 . The table is 256 bytes long.3 Translate (TR) and Translate and Test (TRT) Scanning input fields is important so the 360 architecture provided a single instruction to do this known as the TRT (Translate and Test) instruction. 1 if the fistr operand is shorter than the second. If the byte in the table is zero. Source bytes from the string are successively (left to right) used to index into the table. The instruction is interruptible.The comparison terminates when an inequality is found or at the end of the longer operand. Up to 16M bytes can be copied. and 2 if the first operand is longer than the second. The instruction is interruptible. The odd register of the second operand contains an 8 bit padding byte followed by a 24 bit length. and 2 if the first operand is greater than the second.2. the condition code becomes zero. the even registers of both operands contain the addresses of the unequal bytes. The Condition Code will be set to 0 if both operands are equal. If the first operand is longer than the second. The instruction copies the bytes beginning at the address specified by the even register of the first operand (R1) with the bytes at the address specified by the even register of the second operand (R2). If there was no destructive overlap the Condition Code is 0 if both length are equal. That is. 2. are bytes from the first operand used as source bytes after bytes have been moved into same. The odd register of the first operand contains the first operand's length expressed in the low order 24 bits of the odd register. the operation continues. The TRT uses a table (given as the second operand) and a string (the first operand).2 Move Character Long (MVCL) The MVCL instruction is an RR instruction. the first is padded to the right by the padding byte. 15. The instruction checks for destructive overlap. The length fields in the odd registers of both operands give the number of bytes remaining to be compared when the operation ended. If the byte in the table is non-zero. 1 if the first operand is less than the second. The byte found in the table at the offset determined by the source byte decides what should happen: 1. 3. If the operation ends with an inequality. Both operands must designate the even register of an even-odd pair. the operation terminates and the byte from the table is placed in the low order byte of register 2 and the address of the byte from the source string causing the halt is placed in register 1.

will cause the TRT to halt). you need to cause the location counter to spring back to where it was when you initially built the table (or subsequent code will overwrite the remainder of the table). Take for example the case where you want to scan a source string for the first non-blank character. To use a TRT to do the scanning you need a table that causes the TRT to continue to scan if blanks are encountered and to halt if a non-blank character is found. Hence the naked ORG (no argument) The effect of all this is to create a table mainly of X01 codes except in the offset position for blank. 91 . If a tested byte is non-zero. the Condition Code becomes 1 if the byte from the source string was not the final byte of the source string. we reset the location counter to the start for TAB plus C' ' (which is the equivalent of saying 4016 or 6410 but is easier to understand). This is shown in Figure 39.4. for example). Next. An ORG with no argument resets the location counter to the highest value it has ever held. While the concept of the table is simple. the assembly language provides short cuts: 1. While this may sound complicated it isn't. and prints the word. The example in Figure 45 scans each input record for the first word delimited by blanks. The source string is not altered. Now the location counter is in the table at the offset corresponding to a blank. Build a table all of whose bytes are non-zero (X'01'. The ORG directive resets the assembler's location counter to the value specified. since they are not zero. TAB DC ORG DC ORG 256X'01' TAB+C' ' X'00' Figure 39 TRT Table with ORG In Figure 39. Go into the table at offset 64 and change the value to X'00'. 6410) with X'00'. you need a table were all the values are non-zero except the value corresponding to the offset of the blank character (hex 40 or decimal 64). you back into the table and replace the byte corresponding to the offset of blank (4016 . 2. first you build a table of 256 bytes all initialized to X01 (these bytes. Putting it simply. Then. The Condition Code is set to 2 if the source string byte was the final byte of the source string. In this case. a not uncommon thing to do. However. it is also clear that typing 256 bytes is not pleasant. Here you place the X'00' and this replaces the X'01' that was here.

end move next loop source addr target addr * read a record * EOF? * write the record of word character PRNT WORD.L'WORD * print word WORD.1(R0.0(R3) R3.REC+30 R3.R3).R5).L'REC LA TRT BE LR LA MVC L1 LA LA LA CR BNL CLI BE MVC B XPRNT MVI MVC B R3.L'REC BC B'0100'.ATEND XPRNT REC.WORD 0(1.C' ' * blank to 1st position WORD+1(L'WORD-1).R3) R5.R4 PRNT 0(R3).1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 PRINT NOGEN START 0 REGS * PROGRAM TO SCAN AN INPUT IMAGE FOR THE FIRST * WORD DELIMITED BY A BLANK BEGIN LOOP SUBENTRY XREAD REC.0(R3) L1 * addr of non-blank * target * copy 1st byte * * * * * * * * * increment increment end addr at end? yes blank? yes .WORD * ripple move LOOP * again * * * ATEND EXIT * * * REC WORD MSG TAB EOJ processing XPRNT MSG.TAB EXIT * only blanks found R3.L'MSG SUBEXIT Literals LTORG DS DC DC DC ORG DC ORG END CL32 actual input record CL30' ' C'***** DONE *****' 256X'01' TAB+C' ' X'00' BEGIN Figure 40 TRT Example (continued on next page) 92 .1(R0.R5) R4.C' ' PRNT 0(1.R1 R5.R5).REC 0(L'REC.

C'1' 0(R1). sums and prints the result.L'REC NEGFLG.C' ' B'1111'.The input images are: TEST1 TEST3 TEST2 * * * Figure 40 TRT Example (continued) The example in Figure 45 reads records with numbers. 1 2 3 4 SUB 5 6 LOOP 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLUS 21 22 23 24 25 ERR 26 27 28 PCK 29 30 31 32 33 34 ADD 35 36 37 * 38 * 39 * 40 41 ATEND 42 43 44 PRINT NOGEN START 0 REGS SUBENTRY XREAD BC XPRNT MVI TRT BC CLI BC MVI MVI BC CLI BNE MVI BC REC.RET PACK CLI BC NI AP BC NBR.ADD NBR+7.SUM RSLT.BPLUS NEGFLG.PCK 0(R1).L'REC B'0100'.PCK read a record EOF? write the record set flag to 0 only blanks and numbers minus sign found? set flag to 1 make .L'RSLT Figure 41 TRT Verifying Input (continued on next page) 93 .a blank plus sign found make + a blank must be bad data XPRNT ERRMSG.C' ' B'1111'.l'MSG RSLT.NBR B'1111'. verifies their content.TAB B'1000'.C'0' REC.REC NEGFLG.LOOP is this number neg no yes: make its sign D .=X'4020202020202120' RSLT.L'ERRMSG BC B'1111'.C'-' B'0111'.C'+' ERR 0(R1).X'FB' SUM.negative loop EOF processing XPRNT MVC ED XPRNT MSG.C'1' B'0111'.PCK 0(R1).ATEND REC.

BAD DATA' 256X'01' TAB+C'0' 10X'00' TAB+C' ' X'00' SUM Figure 41 TRT Verifying Input (continued) 94 .45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 RET REC NBR NEGFLG SUM RSLT MSG ERRMSG TAB SUBEXIT LTORG DS DC DC DC DC DC DC DC ORG DC ORG DC ORG END CL10 actual input record PL4'0' C'0' PL4'0' X'4020202020202120' C'DONE***************' C'ERROR .

3 Store (ST) The store instruction stores the 32 bit contents of a register to a word in memory.L1 LM R6.R2.R3.2 Load (LR) The contents of the register specified as the second operand are copied to the register specified as the first operand.R4 and R5 are stored * R6. If the register specified as the first operand is greater than the register specified as the third operand. The Condition Code is unchanged.R1. ST R5.4 Load Multiple (LM) One or more general purpose registers are loaded from consecutive words beginning at the memory address specified as the second operand. … R4 are stored 95 .R6 16.R5.16 Miscellaneous Register Operations 16. If the first and third operands both specify the same register. The Condition Code is unchanged.R1. STM R1.5 Store Multiple (STM) One or more general purpose registers are stored to consecutive words beginning at the memory address specified as the second operand.R7. The registers to be loaded begin with the register specified as the first operand through and including the register specified as the third operand. The Condition Code is unchanged. only 4 bytes are loaded.R4. If the register specified as the first operand is greater than the register specified as the third operand.L1 16. The word in memory should be on a word boundary (a memory address evenly divisible by 4).R4.R4 and R5 are loaded * R6. … R4 are loaded.R5. The registers to be stored begin with the register specified as the first operand through and including the register specified as the third operand. … R0. … R0. If the first and third operands both specify the same register. wrap around occurs. The memory address should be a word boundary. 16.L2 * R1.L1 16.R3.L1 STM R6. It is an RX instruction.L2 * R1.R7.R2. The Condition Code is unchanged. LM R1. only 4 bytes are stored. L R5. The Condition Code is unchanged. LR R5. wrap around occurs.1 Load (L) The load instruction load a 32 bit word from memory into a general purpose register.

no overflow Overflow 16. The Condition Code is set. Both operands may be the same register. Often both operands are specified as the same register in which case the only effect is to set the Condition Code. no overflow Not possible Greater than zero.16. CC=0 CC=1 CC=2 CC=3 Zero.7 Load Positive (LPR) The absolute value of the signed binary value in the register specified as the second operand is loaded into the register specified as the first operand. CC=0 Zero CC=1 Negative CC=2 Positive 16.6 Load and Test (LTR) The contents of the register specified as the second operand are loaded into the register specified as the first operand and the Condition Code is set to reflect the value of the binary integer word copied.8 Load Negative (LNR) The 2s complement of the absolute value of the signed binary integer contained in the register specified as the second operand is loaded into the register specified as the first operand. The Condition Code is set. CC=0 CC=1 CC=2 CC=3 Zero Negative Not possible Not possible 96 .

the resulting bit is 0.the bits of the operand in the register designated as the second operand are or'ed with the bits of the register designated as the first 97 . The bitwise AND instructions are: 1. 2.SS format . NC) In the bitwise AND instructions.RR format . The number of bytes is determined by an 8 bit length field.1.1 Boolean Instructions In the Boolean instructions (AND. RX.1 AND (N. 4. The basic Boolean operations.2 OR (O. the resulting bit is 1.the bits in the immediate operand are and'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory. The bitwise OR instructions are: 1. If both bits are 0. the designated operation takes place between the corresponding bits of each operand and the result replaces the first operand.RX format . NC . If both bits are 1. NI . NR. 17.from 1 to 256 bytes beginning at the address specified by the second operand are and'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand. 3.1. NI. N .RR format . If either or both bits are 1. the resulting bit is 1. SI or SS instructions.the bits of the operand in the register designated as the second operand are and'ed with the bits of the register designated as the first operand and the result is placed in the first operand.17 Bit Operations Bit operations involve modification or manipulation of individual bit in an operand. The COMPLEMENT and SHIFT instructions work only on operands in registers. 17. corresponding bits from each operand are and'ed together.the bits from the word in memory addressed by the second operand are and'ed with the bits in the register designated as the first operand and the result is placed in the first operand. OR . and EXCLUSIVE OR). OC) In the bitwise OR instructions. OR. NR . EXCLUSIVE and OR can be RR. 17. AND. OR. If either or both bits are 0. OI. OR. the resulting bit is 0.SI format . the corresponding bits from both operands are or'ed.

The number of bytes is determined by an 8 bit length field. 5. 6. XC . A value of zero in is unchanged (the 2s complement of 0 is 0). 2.the bits from the word in memory addressed by the second operand are or'ed with the bits in the register designated as the first operand and the result is placed in the first operand. 4.the bits in the immediate operand are exclusive or'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory. XI . O . XR.SI format .1. XR . OI . The bitwise EXCLUSIVE OR instructions are: 1. OC .RR format .2 Complement LCR There is only one complement instruction: LCR.SI format .operand and the result is placed in the first operand. If one bit is 0 and the other is 1. XC) In the bitwise Exclusive OR instructions corresponding bits from both operands are exclusive or'ed with one another.the bits from the word in memory addressed by the second operand are exclusive or'ed with the bits in the register designated as the first operand and the result is placed in the first operand. If both bits are 0 or if both bits are 1. 17.3 Exclusive OR (X. the resulting bit is 1. The number of bytes is determined by an 8 bit length field. 7. 3.RX format . X .from 1 to 256 bytes beginning at the address specified by the second operand are exclusive or'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand.RX format .the bits in the immediate operand are or'ed with the bits of the byte in memory designated as the first operand and the resulting byte replaces the byte in memory. Both register designations may be the same in which case the contents of the designated register are complemented. The condition code is set: 98 .the bits of the operand in the register designated as the second operand are exclusive or'ed with the bits of the register designated as the first operand and the result is placed in the first operand. 17.from 1 to 256 bytes beginning at the address specified by the second operand are or'ed with the corresponding bytes beginning at the address specified by the first operand with the resulting bytes replacing the bytes from the first operand.SS format .SS format . XI. the resulting bit is 0. The LCR loads into the register designated as the first operand the 2s complement of the contents of the register designated as the second operand.

In many cases only the displacement is specified such as: SLL R5. When shifting to the left. Arithmetic shifts are cognizant of the sign bit. an overflow occurs. On both left and right shifts a zero bit replaces the shifted bit. bits like the sign bit replace the shifted bits. shifting a binary number to the right has the effect of dividing by 2. They are classed as either logical or arithmetic. Shifting a binary number to the left has the effect of multiplying it by 2. If the base is specified as any other register. Similarly. On a right shift. SLL.3.3 Shift The shift operators move bits either left or right in one or more registers.4. Logical shifts treat all bits the same.8. if a bit unlike the sign bit is shifted into the sign bit position. shifts may be either single (only one register participates) or double (two registers participate). No overflow can occur. SLDL) The logical shift instructions are: 99 . the register specified as the operand must be the even register of an even-odd pair. the amount of shift is the displacement. SRDL.1 Logical (SRL. the contents of the register plus the value of the displacement are the number of bits to shift.10 In this case the second operand is shorthand for: 0(R0) and thus the instruction means to shift the contents of R5 left 10 binary positions. 17. For all the shift instructions the first operand designates the register to be shifted and the second operand indicates the number of bit positions to be shifted.CC=0 CC=1 CC=2 CC=3 Result 0 Result negative Result positive Overflow 17. 3 positions by 8 and so forth. If the base is specified as zero. The number of bits to shift is calculated from the base and displacement of the second operand. Additionally. shifting it 2 positions to the left multiplies by 4. etc. There is no special treatment of the sign bit position. In the case of a double shift.

the Condition Code is set to 0.shift left arithmetic (single) SLDA .shift right logical (single) SRDL . For example.SRL . if a byte in memory at label L1 has the value: 0011 0101 The instruction: TM L1.B'11001010' will set the Condition Code to 0 (all tested bits were 0s). The bits of the byte in memory addressed by the first operand corresponding to those bits with a value or 1 in the the immediate operand are tested and the Condition Code is set.shift right double arithmetic SLA . 17.shift left double logical The Condition Code remains unchanged. Zeros are provided to replaced the shifted bits.shift left logical (single) SLDL .3. SRDA.shift right arithmetic (single) SRDA .shift left double arithmetic The Condition Code is set: CC=0 CC=1 CC=2 CC=3 Result is 0 Result is negative Result is positive Overflow An overflow can occur only in left shifts when a bit unlike the sign bit is shifted into the sign bit position.4 Test Under Mask (TM) The TM instruction is an SI instruction. 1. bits like the sign bit are provided to replace the shifted bits. The instruction: TM L1.B'00001111' 100 . 2. SLA. 3. The instruction: TM L1. 17. During right shifts.2 Arithmetic (SRA. the Condition Code is set to 3. SLDA) The arithmetic shift instructions are: SRA . During left shifts. If the tested bits are mixed 1s and 0s. zeros are supplied to replace the shifted bits. If all the tested bits are 0.shift right double logical SLL . the Condition Code is set to 1.B'00110101' will set the Condition Code to 3 (all tested bits were 1s). If all the tested bits are 1s.

The second operand is treated as a zoned decimal number. Regardless of the result. the byte in memory is set to 1111 1111. Subtract. When the first program regains control it believes that the byte is 0s. The zone and digit of first byte of the source are reversed and placed in the right most byte of the target. sees 0s and sets the byte to 1s. The Condition Code is unchanged. If the byte is all zeros a TS on the byte will reflect this in the Condition Code and mark the byte as all 1s. the zone removed and the digit portion stored in the next available half byte going right in the target. Further examples are given in Chapter 21.5 Test and Set (TS) The TS (Test and Set) instruction is an SI instruction but the immediate operand is omitted. The operands are processed from right to left. see 0s.2 Add. if the block is allocated and the byte is all 1s. The result occupies the first operand. 17. the Condition Code is set to 0. the Condition code is set to 1. If the bit is 0. Subsequent bytes (to the left) of the source are read. On the other hand. an interrupt occurs and another program gains control. 18.will set the Condition Code to 1 (tested bits were mixed). the first operand is padded to the left with zeros. but before it can set the byte. The instruction tests the leftmost (high order) bit of the byte in memory designated by as the first operand. likewise marks it as 1s and now two programs believe they own the block of memory. SP. 18 Decimal Arithmetic 18. The original purpose of this instruction was to provide an uninterruptible way in which to see if a resource is available and mark it as in use. Example. Likewise this program tests the same byte. If the bit is 1.the testing and setting take place in one operation. The TS instruction is uninterruptible . If the second operand is short. ZAP) 101 . Zero and Add Positive (AP. consider the case where a byte is used to indicate that some block of memory is available with all 0s indicating it is available for allocation and 1s indicating it is in use.1 PACK Both operands are in memory. What this instruction avoids is the situation where a program tests a byte. a TS will indicate this and have no real effect (the byte is still all 1s).

The first operand must be large enough to contain the result or a Decimal Overflow occurs. 2 if the result is greater than zero and 3 in the case of overflow. The quotient occupies the leftmost bytes of the result. When the significance indicator is off.4 Divide Packed (DP) The first operand is the dividend and the second operand is the divisor. The remainder occupies the remaining bytes of the first operand. Following the fill byte are a collection of pattern bytes and message bytes. 1 if the result is less than zero.e. A Decimal Divide exception occurs in the case of divide by zero or a quotient too large to fit in the digits available. 18. The first byte of the first operand is the Fill byte. The divisor may not be longer than 15 digits.In these instructions the first operand is the target and the second is the source. the multiplicand must include at least as many leading bytes of zeros as the number of bytes in the multiplier. 18. It stays off until a significant digit (i. a data exception occurs.3 Multiply Packed (MP) The multiplier (the second operand) is multiplied by the multiplicand (first operand) and the result is placed in the first operand. When the instruction begins the significance indicator is off. Its length is equal to the difference between the length of the dividend (L1) and the divisor (L2). they remain in the result. If the significance indicator is off. the result is the equivalent of an addition to zero. The multiplier may not be longer than 15 digits and must be shorter in length than the multiplicand. 18. The results are a quotient and a remainder which wil replace the dividend. non-zero) is encountered or turned on by a pattern byte. The first operand is a set of pattern codes that control the formatting process and the second operand is the packed number to be converted. It will be placed in the leading bytes of the result in place of non-significant leading zeros. message bytes are replaced by the fill byte. In order to prevent an overflow from occurring. The Condition Code is unchanged. The Condition Code will be zero if the result is zero. In the case of the ZAP.5 EDIT (ED) The ED instruction is used to convert packed decimal number to zoned decimal (printable) values. 102 .. The Condition Code is unchanged. If this is not the case. The result replaces the first operand. zeros in the source are replaced by the fill byte. If the significance indicator is on.

6. not the current digit. Further examples are given in Chapter 21. the next digit in the source field is selected. Further examples are given in Chapter 21. If encountered in the format. it becomes the digit in the final result byte but the zone becomes the sign. the significance indicator is turned off. The first is called the digit selector. If the sign is positive (CAFE). The pattern code X'21' is called the significance starter. The Condition Code is unchanged. The effect of this is to leave or replace trailing characters in the format.6.1 UNPACK (UNPK) The UNPK instruction converts its packed decimal second operand to zoned format. The (DB) will be replaced by the fill byte if the number is positive but remain in the result if the number is negative. The Condition Code is unchanged. Except for the digit. the fill byte replaces the digit selector. it remains on or is turned on.6 Miscellaneous Decimal Related Instructions 18. 18.6. In the case of the last digit.2 Move Numerics (MVN) This instruction uses only one length field.There are two main pattern bytes: X'20' and X'21'. If a non-zero digit is selected. When the last digit of a number is selected. (Note: you often see this in bank statements where a negative value is indicated at the end of the number). each digit in the source becomes a byte in the result with a leading X'F' zone. 18. The right-most 4 bits of each source byte (second operand) are moved to the right-most 4 bits of the target operand (first operand). If the digit is zero and the significance indicator is off. The left-most 4 bits of each source byte (second operand) are moved to the left-most 4 bits of the target operand (first operand). the final characters in the format could be (DB) indicating a debit or negative balance.3 Move Zones (MVZ) This instruction uses only one length field. If the sign is negative. the digit is converted to zoned decimal and replaces the digit selector. the sign is examined. 103 . the significance indicator is turn on if not already on. 18. It acts like the X'20' above except it always turns the significance indicator on if not already on. If the digit is non-zero or the significance indicator is on. Turning the significance indicator on affects the next digit. For example.

104 .

memory resident operands in RX. for large programs. are obviously longer than 4095 bytes in the real world. When a label is within this window of addressability we say that the label is within using of the base register. the index register is seldom used and addressing of the memory operand is usually accomplished by only the base register and the displacement.1 Base Register Addressing As we have seen. the assembler cannot address a label which is more than 4095 bytes from the address contained in the base registers. At the beginning of an assembly language program we load the base register with the absolute address of a location near the beginning of the program and then tell the assembler which register we have selected to be the base register and where it is pointing. the assembler selects the register that would yield the smaller displacement. In the case of RX instructions. no branch takes place because the second operand is R0. there are usually not enough spare registers so other techniques are employed. In these larger programs. In this case. That is. The base register addressability problem is solved by having multiple base registers with the second pointing 4096 bytes beyond the first and so forth. Displacements in the basic architecture are positive 12 bit numbers and thus can range from 0 to 4095 (more recent instructions may use longer displacements). SS and RS instructions are addressed by a combination of index register. the assembler selects which to use. Programs. One problem with the base-displacement addressing scheme used in the IBM mainframe is that the maximum displacement from a base register is 4095 bytes. However the first operand receives the absolute address of the byte immediately following the BALR. base register and displacement (in RX format). or displacement and base (in all others). however. From this point on. When there is more than one base register available. In the case were the scope of two base registers overlaps (the 4096 byte window beginning with the byte pointed to be a base register). SI. 105 . the assembler will calculate the addresses of labels as displacements from the point in the program whose address is contained in the base register. the base register (any register between R1 and R15 but usually R13 or lower) contains the absolute address of a location in memory in our program. When addressing a memory operand with base and displacement.19 Multiple Base Registers 19. The address of a memory resident operand is calculated as a forward displacement from the location in memory contained in the base register. blocks of code establish their own base register on entry so the same register or registers are re-used. However. Loading a base register with the an absolute address can be accomplished by a BALR instruction in which the second operand is specified as R0.

R12 The above loads the absolute address of the byte following the BALR into R12 then tells the assembler to use R12 as a base register. from the point or line in a program where a register is designated as a base register by USING until the point or line where it is dropped by a DROP. if any. as the asterisk refers to the current address. The format of the assembler directive USING is an address expression followed by one of more register designations.R11) LA R10. The use of USING and DROP are assemble-time directives . they are said to be in using. Note that the USING follows the BALR.R12) LA R11. This discontinues use of a base register. Outside that area. 11 and 10 maybe used as base registers.R0 USING *. Had it been the other way around. for example.R11. You will also note there is a DROP directive.2048(R0. This is because the address in R12 is the address of the byte immediately following the BALR and.2048(R0. if we want to establish R12 as a base register. the register is not a base register. In this case the programmer needs to be sure to load each register correctly. An example can be seen in Figure 42. However.So. The first register is assumed to contain the address of the address expression and subsequent registers.R11) LA R10. This could be accomplished with the following: BALR R12. The assembler assumes that these registers are set to 4096 and 8192 bytes apart.2048(R0. we would first want to load it with the absolute address of where we are in the program then inform the assembler that R12 is a base register and tell the assembler where the contents of R12 are pointing. hence. That is. As there are only fifteen register that can be used as base registers. the LA instruction is used to set 106 .R10 LA R11. 8192. In this case the address expression is asterisk meaning here.they cover areas of code and are not run time states. the USING needs to be after the BALR. if an operand is beyond the maximum 4095 byte displacement of any base register.R10 Figure 42 Multiple Base Registers The code in Figure 42 first loads R12 with the absolute address of the byte immediately beyond the BALR.2048(R0. the operand is said to be out of using. Then it tells the assembler that registers 12. When operands can be addressed with a valid base and displacement combination.R0 USING *. and so forth. are assumed to contain the address expression plus 4096.R12. 1 2 3 4 5 6 BALR R12. most large programs frequently re-use base registers rather than using many registers at once. the assembler would assume that the address in R12 was the address of the BALR. it is not unusual to have more than one base register available for addressing. the register may be selected by the assembler to construct a base/displacement address. Then. respectively.

Note that since the maximum displacement is 4095. two LAs are required to add 4096.R11 and R10 from the value in R12. 107 .

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20 System Macro Input/Output
Input/output operations on a mainframe traditionally have been record oriented. In most cases these involved fixed length records. Access to files is by means of input/output macros that are specific to the type of data being accessed. In the examples up to this point, the ASSIST pseudo-macros have been used as they simplify the process for novice users. In this section we introduce several basic QSAM (Queued Sequential Access Method) macros and show their usage. In order to perform either input or output it is first necessary to define a DCB (Data Control Block). The DCB is a table built partly by the user and partly by the system which defines the file being operated upon. The DCB has many options, only a few are shown here. A DCB is constructed with the DCB macro. Once a DCB has been constructed, a file is opened with the OPEN macro. The OPEN macro connects your program's DCB with the file being accessed. The OPEN and the DCB specify if the file is being opened for input, output or both. Once a file is open, you may access the file with several macros. Among these are GET and PUT. Others are also possible. When file processing is finished, you should issue a CLOSE macro to finalize any output, free buffers and disconnect from the file. In the example in Figure 43, 34 byte input records are read from one file and written to another. The input DCB is named INDCB and the output DCB is named OUTDCB. The DCB parameters used are as follows:
LRECL=34 RECFM=FT MACRF=GM MACRF=PM EODAD=ATEND DDNAME=IN DDNAME=OUT logical record length of 34 bytes fixed length records - ASCII/EBCDIC conversion the GET file access macro will be used the PUT file access macro will be used branch to label ATEND on end of input data DDNAME name to be opened and read DDNAME name to be opened and written

The LRECL determines the size of the input or output records. In the actual input file, the text records are actually 32 bytes long. The extra two bytes in the LRECL (and the associated input data area REC) allow for the carriage-return/line-feed (CR/LF) characters that are at the end of each line in a Microsoft text file. Note: Linux and Unix based systems have only one character at the end of a line, a linefeed (LF). The input records must each consist of 32 bytes of text. The RECFM parameter tells the system that the input and output files will consist of fixed length records. The MACRF parameter tells the system that the GET or PUT macros will be used for actual input and output. For input operations, the EODAD parameter tells the system the label to be branched to upon encountering the end of file. This parameter is not used for output DCBs.

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Finally, the DDNAME is used to link the program's DCB to an actual file. In the z390 emulator running of a Windows based PC, this will be the name of an environment variable set by the user which will have the actual file name to be used. Before running the program, the user needs to create environment variables IN and OUT and set them to values that are valid file names. For example, to the Command Prompt, type:
set IN=IN.DAT set OUT=OUT.DAT

When the assembly language program runs, it will attempt to read from the file IN.DAT and write to the file OUT.DAT. You can see the complete list of environment variables by typing the command set by itself. You can delete an environment variable by entering a set command equating variable with nothing such as:
set IN=

The selection of the DDNAMEs IN and OUT was arbitrary. You may use any names that the system accepts. In the program in Figure 43, after the usual initialization, the DCBs are opened by the OPEN macro for OUTPUT and INPUT, respectively. They could have also been opened individually with code such as:
OPEN OUTDCB,OUTPUT OPEN INDCB,INPUT

The WTO macro writes to the console that the OPENs succeeded. Next the program enters a three line infinite loop consisting of the GET and PUT macros and the unconditional branch. The GET macro reads from the file associated with INDCB into the data area REC and the PUT macro writes from the data area to the output file associated with OUTDCB. When the GET encounters the end of file, the GET macro causes a branch to the label ATEND as determined by the EODAD=ATEND parameter in the INDCB. The CLOSE macro at ATEND flushes the buffers and disconnects from the output file. Failure to CLOSE an output file will usually result in the loss of about 2 lines of data. The file OUT.DAT will be an identical copy of the input file.

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21 Converting Between Zoned. the above Zoned Decimal number.MACRF=GM.REC LOOP read a record write the record loop EOJ processing CLOSE INDCB SUBEXIT File DCB's DCB DCB LRECL=34. The last half byte contains the sign of the number.INDCB. they must be converted to one of the numeric types. Instead. Thus. and E mean the number is positive and the codes D and B mean its negative.MACRF=PM.DDNAME=OUT LRECL=34.A. The hex codes C. such as Packed Decimal or Integer (binary).RECFM=FT. A Packed Decimal is a string of bytes containing in each half byte a value (in bits) from 0 to 9 except for the last half byte. For example. such as Packed Decimal or Integer (binary). In this section we show how to convert between printable character.(INPUT)) WTO '*** FILES OPEN ***' GET PUT B INDCB.REC OUTDCB. 1 2 3 COPY 4 5 6 7 8 9 LOOP 10 11 12 * 13 * 14 * 15 ATEND 16 17 * 18 * 19 * 20 OUTDCB 21 22 INDCB 23 * 24 * 25 * 26 REC 27 PRINT NOGEN EQUREGS SUBENTRY OPEN (OUTDCB. packed decimal and floating point modes. Packed and Binary Arithmetic on an IBM mainframe can be carried out in binary integer. packed decimal and binary.F. in packed format would be: X'01234F' 111 .DDNAME=IN INPUT RECORD DS END CL34 COPY Figure 43 QSAM Input/Output Arithmetic may not be performed on these character representations of numbers.RECFM=FT. Floating point is not covered here. Instead. they are in Zoned Decimal format.(OUTPUT).EODAD=ATEND. When numbers are read from character (EBCDIC) input. they must be converted to one of the numeric types. the printable number 1234 in EBCDIC appears as: X'F1F2F3F4' Arithmetic may not be performed on these character representations of numbers.

With both 32 and 64 bit binary numbers additional conversion is required from/to packed format. however). The basic set of packed arithmetic instructions are: AP SP MP DP CP ZAP Add Packed Subtract Packed Multiply Packed Divide Packed Compare Packed Zero and Add Packed The example in Figure Error: Reference source not found illustrates some basic packed arithmetic operations. we must modify the numeric portion of the last byte. Packed decimal numbers can occupy up to 16 bytes and thus can represent numbers up to 31 digits in length. It reads in a table of positive numbers. 112 . then perform a CVB (convert to binary). We use the PACK instruction to convert a positive zoned decimal number to packed decimal. using a 32 bit binary value limits the results to about +/. it can handle more digits of accuracy and it does not need any further conversion. packed decimal is especially useful for business applications where many digits of accuracy are required. it can be seen that the zones have been eliminated and a sign appended. Once a number is in packed format. The CVB instruction converts a packed number to binary leaving the result in a register. Packed decimal operations do not create round-off errors that are common with floating point numbers.DAT is the name of the input file. To change the sign. you first must pack the number (PACK is very fast). The CVB is nontrivial.DAT where INPUT1. Note: either upper or lower case in the above is acceptable.2 billion (the range of values is much greater for 64 bit binary numbers. When using the z390 emulator for the program in Figure Error: Reference source not found you need first to establish the connection between the DDNAME=IN and the actual input file. This is done with the Windows command: set IN=INPUT1. packing them and adding them into a sum then prints the total and the average. you may do arithmetic on it. On the other hand. The PACK instruction removes the zones and packs the numerics except for the last byte of the zoned number where the zone and numeric are swapped. The PACK instruction packs into the first operand from the second. Each operand may be up to 16 bytes in length. To read in a number in and convert it to binary. packed arithmetic is faster and more flexible. all packed numbers appear to be positive (sign of F). For many commercial transactions where a record is read and updated (by adding or subtracting) then quickly written back to disk. Since the zone of a text number is always F. While packed or decimal arithmetic is slower than binary arithmetic.In this format.

NBR LOOP * * * * * READ A RECORD WRITE THE VALUE TO CONSOLE PACK THE NUMBER ADD TO TOTAL READ ANOTHER RECORD * * * ATEND EOF . 2. A sample execution can be seen in Figure 46 (note input echoed to the console).RSLTX) SUBEXIT File DCB's DCB LRECL=10. The program in Figure Error: Reference source not found operates as follows (see also Chapter 18): 1. The branch instruction on line 10 causes the loop to iterate. This pattern will convert up to seven packed digits to characters with a padding byte of blank. On line 16 the edit (ED) instruction is used to convert the packed value in SUM to printable characters in RSLT. 5. Note: leading blanks are also permitted as a blank (X'40') and a zero (X'F0') both PACK to zeros. Zero suppression will not apply to the last digit. The input file is opened on line 4 and connected with the DCB INDCB. The program in Figure 45 solves this problem by taking minus signs into account.(INPUT)) GET WTO PACK AP B INDCB. Initially RSLT has an edit pattern in it as can be seen in line 38. The program in Figure 45 operates as follows: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PRINT ADD LOOP NOGEN EQUREGS SUBENTRY OPEN (INDCB. echoed back to the console (line 7). Line 17 writes the output. PACKed (line 8) and summed into SUM (line 9). The loop ends when there is no more input due to the EODAD=ATEND option in the DCB on line 22.EODAD=ATEND.RECX) NBR. 3.DDNAME=IN Figure 44 Decimal Arithmetic (continued on next page) * DONE WITH INPUT * UNPACK AND FORMAT RESULT * * * INDCB 113 .REC MF=(E. 4.The input file for the program in Figure Error: Reference source not found is shown at the end. This triggers a branch from the GET on line 6 to the label ATEND when the GET encounters the end of file.BRANCH HERE WHEN OUT OF RECORDS CLOSE INDCB ED RSLT.RECFM=FT. The program in Figure Error: Reference source not found is fine as far as it goes but it only handles positive number.MACRF=GM. AT line 15 the input file (DCB) is closed. Line 6 through 10 are a loop in which lines of data are read (line 6).REC(8) SUM.SUM WTO MF=(E.

7. If it detects a minus sign. 4. 9. we And Immediate the last byte of the packed number with the mask byteX'FD' on line 44. 8. if NEGFLAG is 0. If it finds a minus sign.0) C'ANSWER=' X'4020202020202120' * EDIT PATTERN * ADD Sample input data: 00000010 00000020 00000030 00000040 Figure 44 Decimal Arithmetic (continued) 1. The low order digit of the last digit of the packed number must be F16 because it is the zone of the last digit of the input. this flag will reset to character one. ANDing this with D16 results in it becoming D16 as well . The input number was positive. If NEGFLAG is 1. After the number is PACKed. we add the result. If a sign is detected.23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 * * * RECX REC RECEND NBR SUM RSLTX RSLT RSLTEND input record DC DC DS EQU DS DC DC DC DC EQU END AL2(RECEND-*-2. It continues scanning the input is it sees a blank. 6. 114 . 5.a minus sign in packed format. a plus or a minus. A loop beginning on line 12 and extending through line 40 examines each character in the input. The number is PACKed (line 41). NEGFLAG is set to character 1. Each input record is treated as an 8 byte number and is assumed to be correct (that is. the program does minimal error checking). Now we add the negative number to the sum. the program sets NEGFLAG as appropriate and replaces the sign by a blank (we do not want the sign present when we pack the number). At end of input the results are printed. 3. The high order F16 in the mask byte will preserve the contents of the high order digit of the last byte. 2.0) * SUB 2 TO AVOID CR/LF C'INPUT=' CL10 * INPUT RECORD + 2 BYTES FOR CR/LF * PL8 PL4'0' AL2(RSLTEND-*. The input loop is basically the same as in Figure 44. it loads the address of the input record into R3 and sets a flag (NEGFLAG) to character zero. The loop scans the input until it finds a leading digit. On line 10.

C'+' PLUS 0(R3).C'1' 0(R3).REC MF=(E.1(R0.MAKE SIGN X'D' * LOOP ADD * * * ATEND EOJ processing CLOSE INDCB WTO 'DONE*******' ED RSLT.EXITING' SUBEXIT MVI MVI B MVI B CLI BH LA LA CR BL PACK CLI BNE NI AP B NEGFLG.C'-' MINUS 0(R3).C' ' BLANK 0(R3).C'1' ADD NBR+7.R3) R4.SUM WTO MF=(E.RECX) R3.X'FD' SUM.C'0' NUM * READ A RECORD * WRITE RECORD TO CONSOLE * MAKE FLAG 0 * MINUS SIGN FOUND? * PLUS SIGN FOUND? * BLANK FOUND? * 0 OR GREATER NUMERIC FOUND? L1 CLI BE CLI BE CLI BE CLI BNL ERR MINUS WTO 'BAD DATA .REC NEGFLG.REC+8 R3.INPUT)) GET WTO LA MVI INDCB.NBR LOOP * SET FLAG TO 1 * MAKE MINUS A BLANK * MAKE PLUS A BLANK * 9 OR LESS? * MUST BE BAD DATA * * * * INCREMENT POINTER GET ADDRESS OF END COMPARE ADDRESSES LOOP IF NOT DONE PLUS NUM BLANK * IS THIS NUMBER NEGATIVE? * NO * YES .C'0' 0(R3).RSLTX) SUBEXIT Figure 45 Negative Decimal Arithmetic (continued on next page) 115 .R4 L1 NBR.C' ' PCK 0(R3).C'9' ERR R3.C' ' PCK 0(R3).1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 ADD LOOP PRINT NOGEN EQUREGS SUBENTRY OPEN (INDCB.REC(8) NEGFLG.

0_18 05/16/11 IO=70 1.MACRF=GM. and go from mlc to 390 execution C:\DOCUME~1\user\ASMLAN~1>echo 12:42:32 addloop1 MZ390 START 12:42:32 addloop1 MZ390 ENDED 12:42:32 addloop1 LZ390 START 12:42:32 addloop1 LZ390 ENDED 12:42:32 addloop1 EZ390 START INPUT=00000001 INPUT=-0000002 INPUT=00000003 DONE******* ANSWER= 2 off USING RC= USING RC= USING z390 V1.5.0_18 05/16/11 IO=2414 1.6.mlc C:\DOCUME~1\user\ASMLAN~1>rem asmlg assemble.EODAD=ATEND.6.5.5.03 ON J2SE 0 SEC= 0 MEM(MB)= 15 z390 V1.03 ON J2SE 0 SEC= 0 MEM(MB)= 46 z390 V1.DDNAME=IN input record DC DC DS EQU DS DC DC DC DC DC EQU DC END AL2(RECEND-*-2. link.RECFM=FT.0) C'ANSWER=' X'4020202020202120' * EDIT PATTERN * C'DONE***************' BEGIN Figure 45 Negative Decimal Arithmetic (continued) C:\DOCUME~1\user\ASMLAN~1>asmlg addloop1.56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 * * * INDCB * * * RECX REC RECEND NBR NEGFLG SUM RSLTX RSLT RSLTEND MSG File DCB's DCB LRECL=10.0) * SUBTRACT 2 TO AVOID CR/LF C'INPUT=' CL10 * INPUT RECORD + 2 BYTES FOR CR/LF * PL8 C'0' PL4'0' AL2(RSLTEND-*.0_18 05/16/11 Figure 46 Example Execution 116 .6.03 ON J2SE 1.

The WTOR macro is similar.1 Console Input/Output In Figure 22 on page 65 we saw an example of reading and writing files using the XREAD and XPRNT macros. You may read and write directly to the console using the WTO and WTOR macros. The first will contain the length of the string to be written (including the half words). an optional length or the input field. Alternatively. Alternatively. you may read and write files using the GET and PUT macros or the ASSIST XPRNT and XREAD macros. its parameters are a message to be written. The second half word contains a zero. and an event control block (ECB) (A full word binary initially set to zero).MSG) where MSG refers to a data area such as the following: MSG DC AL2(MSGEND-*.0) MSG1 DS CL20 MSGEND EQU * The first line. In Figure 43 on page 111 we saw an example of QSAM based file input/output using the GET and PUT macros. This pauses the program until the reply has been entered. consists of 2 half words. The value of the first half word it the difference between the location counter at MSG (*) and the value of the location counter after the string and half words. 117 . MSG. Here we examine console based input output using the WTO and WTOR macros. This value is used in the line with label MSG. If the length is omitted. The simplest form is: WTO 'STRING TO BE WRITTEN' The above will write the contents within the quote marks (up to 119 characters) to the console window. it will be determined from the implied length of label. you can write a string stored in memory to the console with: WTO MF=(E. The macro is followed by a line with the WAIT macro with the ECB from the WTOR. Here we demonstrate the WTO and WTOR macros which are normally available in the IBM assembler. The WTO macro can be used to write a constant string to the console (your command prompt window) or it can be used to write a string stored in memory. This is then followed by the data area which will contain the string to be written.22 Programming Examples 22. in this case a string of length 20 whose contents are filled-in somewhere else in the program. The label MSGEND has as its value the location counter value of this point in your program. an area in memory to receive a reply.

EV WAIT ECB=EV WTO MF=(E. The result will be the quotient. Each iteration of the formula produces a new random number until the sequence repeats.2 Random Numbers Many random number generators operate on a formula of the form: x = ( a * x + b) % N where x is initially the seed. that is.MSG) SUBEXIT MSG DC AL2(STREND-*. For example. The values of a and b determine the overall performance of the program.20. Thus. The values for a and b are 214013 and 2531011. were taken from: 118 . Next. the low order 15 bits of the original number.STRING. Thus can be accomplished by and And instruction.The example in Figure 47 gives an example where a message is written by the simple form of the WTO macro. a and b are constants and N is usually a power of 2. if N is 32768 or 215 a divide by 32768 can be accomplished by a right shift of 15 bits. The reply is then printed using the extended form of the WTO. we can obtain modulo 32768 on a binary number by zeroing out all bits but the lower 15. another message is written by the WTOR macro and the program which waits for a reply. If N is a power of 2. For example. then the modulo operation can be performed as a shift rather than as a real division operation. in a 32 bit word.C'YOU TYPED ' STRING DS CL20 STREND EQU * EV DC F'0' END WTO Figure 47 Console I/O using WTO/WTOR 22. will be the bits shifted out of the register. respectively. The remainder. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PRINT NOGEN EQUREGS WTO SUBENTRY WTO 'CONSOLE READ/WRITE' WTOR 'ENTER A STRING'.0). however. we would And the word with the mask: X'00007FFF' whose lower 15 bits are: B'0111111111111111' Figure 48 contains a short C program to generate 1000 random numbers with this technique.

LOOP SUBEXIT A B X MASK OUT DC DC DC DC DS F'214013' F'2531011' F'79' X'00007FFF' CL12 * LOAD R2 WITH 8 * LOAD SEED OR LAST VALUE * MULT BY A * * * * ADD (LOGICAL) B MODULO 32768 STORE RESULT PRINT RESULT RAND * DECR R2.x). x.org/wiki/Random_number_generator_(included) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 #include <stdio. Also note the Add Logical instruction on line 13. i++) { x = ( a * x + b ) % N.A AL R5.h> int main() { unsigned int i. a. BRANCH IF > 0 END RAND Figure 49 Random Number Generator 119 . Note that the Multiply instruction on line 11 addresses the even register of the even/odd pair. The Multiply instruction. i<1000.X M R4. b.X XDECO R5. printf("%d\n".0) LOOP L R5. } } Figure 48 Random Numbers in C The assembly language equivalent of the program in Figure 48 can be see in Figure 49.12 BCT R2. This causes the number to be treated as an unsigned quantity for purposes of addition. b=2531011. a=214013. N.B N R5. // seed for (i=1. has a 64 bit result only the lower 32 bits of which we use and thus the matter of overflow is not an issue. x=79.OUT XPRNT OUT.MASK ST R5. on the other hand.http://rosettacode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PRINT NOGEN EQUREGS SUBENTRY WTO 'RANDOM NUMBERS' LA R2.8(0. N=32768.

the output should contain the translation to suffix and the stack should be empty.3 Convert Infix to Suffix In the example in Figure 50 we use a simplified algorithm to convert fully parenthesized infix notation the suffix notation. the operators appear between the operands. The address in R4 will always point at the next available position. copy it to the output string. The figure L'IN in the XPRNT tells the assembler to calculate the implied length of the data declared at label IN and place the number here. first out data structure. Stacks are very useful in many algorithms and the are an example of a last in. Check results. when we place a new item on the stack. if it is an operand. When done. there are no embedded blanks in the input string and that the input string has a dollar sign at the end as a terminator character. ignore it and go to step 1. and R4 will point to the next available byte in the stack. We load our main registers in lines 6 through 8. If it is a dollar sign. R3 will point to the next available byte in the output string. In lines 4 and 5 we copy blanks into the output field OUT. If it is a close parenthesis. R2 will point to the current byte in the input string. the operands appear after the operands. the existing items are pushed down. In infix notation. push it on the stack. On line 3 we print in the infix expression to be converted. In suffix notation. Thus. In our example we assume that all operands are a single character. byte 0 (the blank) is copied to byte 1 then byte 1 is copied to byte 2 and so forth. 3. 3. The easy way to do this is to place a blank in the first position (line 4) and then propagate it across the remaining 19 positions (line 5). In a stack. not 20. Fore example: ((A+B)*(C-D))$ yields AB+CD-* The program works as follows: 1. 6. The MVC on line 5 moves is offset by one from its source to its target and the length is 19. 2. The stack will start empty (R4 points to the start of STACK) and grow to higher addresses in STACK when items are added.22. 5. If it is a open parenthesis. pop the top element on the stack to the output string. Examine the next character in the input. When we remove an item. When items are removed from the 2. 120 . the remaining items pop-up. 4. The (simplified) infix-to-suffix procedure is as follows: 1. If it is an operator. The algorithm uses a stack. done.

In an SI instruction the first operand is addressed by a combination of displacement and base: D1(B1). the displacements are zero because the registers contain the entire address.stack. We must provide the length as the assembler can not calculate an implied length (it needs a label to do this). Line 15 tests for the terminating dollar sign and branches out of the loop to print the results. If it is not. the address in R4 will be decremented. It means zero displacement past the address in R2. Finally. 9. on line 29. After the byte from the stack has been copied to the output. In this example. we branch to label L1. 8. Remember. That is. Again. R2 has the address of the operand. On lines 32 through 34 we increment the input and stack pointers then branch to the top of the loop for the next input character. The MVC on line 31 copies the operator byte from the input string to the stack. the only alternative is that the character is an operand which we copy to the output string. beginning at line 44. 7. The main input character processing loop begins at line 13. If not. we branch to label L3. we test if the byte of input pointed to be R2 is a open parenthesis. Note that we needed to decrement the stack pointer first because it always points to the next available position. If it is. Lines 21 through 28 test if the input character is one of the operators. This line and several following it examine each character of input in order to determine how to handle same. 4. R2 points to the operator and R4 points to the next available position in the stack. increment the input and output pointers and branch to the top of the loop. we branch to the label OPR. On line 13 itself. we increment R2 (line 15) and branch back to the top of the loop (effectively. On line 36 we test if the input is a close parenthesis. the base position is taken by R2. the current position in the stack is no longer in use so the stack pointer (R4) is correct. we branch around the operator handling section to label L2. The 1 in the first operand is the length. At OPR we move the operator character onto the stack. Note the first operand on the CLI instruction on line 13. 5. If it is. 121 . Then we increment both the input and output pointers. 10. At line 49 we write out the output string and exit. If it is not. we ignore the open parenthesis). 6. we decrement the stack pointer and copy the byte from the stack to the next available byte in the output string (pointed to by R3). If it is. It needs to be decremented to point to the last used position.

=F'1' B LOOP MVC 0(1.C'+' BE OPR CLI 0(R2).L'IN MVI OUT.C'$' BE FIN CLI 0(R2).C'(' BNE L1 LA R2.4 Bubble Sort a Table of Numbers The program in Figure 51 performs a bubble sort on the ten full word binary numbers in the table beginning at label TAB.L'OUT SUBEXIT DC C'((A+B)*(C/D))$' DS CL20 DS CL20 END Figure 50 Convert Infix to Suffix * IS INPUT CHAR ( ? * NO * INCREMENT INPUT POINTER * PROCESS NEXT CHARACTER * IS INPUT CHAR $ ? * YES . The program consists of two loops: an outer loop beginning at OUTER and and inner loop beginning at LOOP.0(R2) A R4.0(R4) A R3. 122 .=F'1' A R2.=F'1' MVC 0(1.END OF INPUT * IS INPUT +.=F'1' B LOOP CLI 0(R2).C'-' BE OPR CLI 0(R2).STACK * ADDRESS OF STACK * * LOOP TO EXAMINE AND PROCESS INPUT * LOOP CLI 0(R2).=F'1' B LOOP XPRNT OUT.C' ' * PUT BLANK IN 1ST POSITION MVC OUT+1(19).R2) B LOOP CLI 0(R2).C'/' BE OPR B L2 OPR MVC 0(1.R3).OUT * ADDRESS OF OUTPUT STRING LA R4.=F'1' A R2.R4). * OR / ? * YES L1 * PUSH OPERATOR ONTO STACK * INCRMENT INPUT POINTER * PROCESS NEXT CHARACTER L2 L3 FIN IN OUT STACK 22.C'*' BE OPR CLI 0(R2).0(R2) A R3.1(R0.R3).IN * ADDRESS OF INPUT STRING LA R3.C')' BNE L3 S R4. -.OUT * PROPOGATE BLANK ACROSS FIELD LA R2.=F'1' A R2.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SUFFIX SUBENTRY EQUREGS XPRNT IN.

element 1 is compared with element 2 and so forth until element 9 is compared with element 10.. R2 is the counter from 0 to 9 and R8 is the swap flag. These are of the form 0. If the flag indicates that a pair of elements were swapped. their contents are swapped with one another.The inner loop examines each element of the table from element 0 to element 9 and compares it with the element in the position above it. This is a common trick for incrementing positive numbers by small amounts and is faster that an RX Add instruction. Inside the loop we convert the counter in R2 to an offset in R4. 2. The table is now sorted so we branch to the location where we print the results. . At the beginning of the outer loop these are both set to zero (lines 4 and 5). This. If the value in R2 is less than 9 we continue and execute another loop cycle (note: the value in R2 will range between 0 and 8 which is nine values . Now R5 is the offset into the table of the element just above the element whose value is in R3. Next we load into R5 the value of R4 incremented by 4 (Line 10). Note that the format of the statement in line 9 causes R4 to be used as the index register. In the program. 1. we branch to the top of the outer loop and reset R2 and R8. That is. If the value of an element is greater than the value of the element above it. We use the LA instruction which sums the value of R4 and the displacement (4) and places the result in R5. To convert the count into an offset we load the count into R4 and then shift the value left by two bits (lines 7 and 8). a flag is set to indicate that a swap has taken place.. If the contents of R8 are not zero. If not. If the flag indicates that no swap took place. while the counter may be 0. it means that all nine iterations of the inner loop resulted in no swap. We load the value from the table into R3 on line 9. After all elements have been examined the flag is examined. 8. If the contents of R3 are greater than the value of this element. 4..we want our first offset to be zero). we branch to the section of code where we swap the contents (SWAP). If we do not swap we advance to line 14 and increment R2 by one using the LA trick. That is. the value we load is at TAB+R4. the process is repeated. Next we check the contents of R8. 12. A shift left by 2 is the equivalent of multiplying by 4 and thus the value becomes our offset. element 0 is compared with element 1. .. we need the actual offset into the table in order to address the elements. On line 11 we compare the contents of R3 with the value in the table at offset R5. If the value in R8 is zero.. When a pair of elements are swapped. the fort is finished and the results are printed. we have completed a full 9 iterations of the inner loop. 123 . We compare the contents of R2 with 9.

=F'0' BE DONE B OUTER * FLAG * COUNTER * * * * MULT by 4 GET VALUE OFFSET OF NEXT VALUE COMP VALUES INC * INCR COUNTER * INNER LOOP DONE? * CHECK FLAG * DONE? * DO INNER LOOP AGIAN SWAP L R6.0) * SET FLAG B INC SR R2.2 L R3.TAB(R4) * LOWER L R7.R2) Figure 51 Bubble Sort (continued on next page) DONE PLOOP 124 .TAB(R5) * LOWER TO HIGHER LA R8. R4 becomes the offset as before by shifting it left by two.TAB(R4) LA R5.R2) C R2. compare it with 10 and iterate if the value is less than 10.R2 LR R4. AT DONE we do a very similar loop based on offsets and print the results. We increment R1 by 1. As before.TAB(R4) * HIGHER TO LOWER ST R6.=F'9' BL LOOP C R8.R2 SLA R4.1(0. R2 is a counter but this time it will range between 0 and 9 rather than 0 to 8.1(0.R8 SR R2.R4) C R3.OUT XPRNT OUT.R2 * LOOP AND PRINT RESULTS LR R4.4(R0. We load the value from the table into R3 then convert it to printable characters and print it (lines 31 through 33).2 L R3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 BUBBLE SUBENTRY EQUREGS OUTER LOOP SR R8.R2 SLA R4.TAB(R5) * HIGHER ST R7. We place a 1 in R8 indicating a swap has taken place then branch to label INC to increment the counter and test as described above. we load the values of the two elements that need to be swapped into R6 and R7 and then store the upper element's value (R7) into the lower element slot (R4 offset) then store the lower element's value in the upper element's slot (R5 offset).L'OUT LA R2.TAB(R5) BH SWAP LA R2.1(R0.TAB(R4) XDECO R3.In the swap section (lines 21 through 26).

If the value in R2 is greater than or equal to the value in R4.=F'10' BL PLOOP SUBEXIT 22. this divides the value in R4 by 2 and this gives us the upper limit for the inner loop counter. We load the counter (R3) into R4 then shift the value in R4 right by one. The program is a loop that tests each number between 4 and 999 to see if it is divisible by any number between 2 and one-half the number being tested. On lines 10 and 11 we set up the limit for the inner loop. The loop will iterate testing all the values between 2 and one-half the value being tested to see if they divide evenly. we branch to label PRIME and print the number. we exit the inner loop and try the next outer loop value. we begin our testing with 2. The program operates as on outer loop whose counter is the number to be tested and an inner loop whose counter iterates between 2 and one-half the outer loop counter. with the limit value in R4. On Line 13 we initialize the inner loop counter to 1. Consequently.5 Search for Prime Numbers The program in Figure 52 searches for prime numbers in the range of 4 through 999. The outer loop counter is R3 and it is initialized to the value 3 on line 4. we test the values between 4 and 999. In effect. We have tried all the alternatives. if equal. we begin with the counter having a value of 4). If we find a case where some counter value from the inner loop divides evenly (remainder of zero). we make it through the entire inner loop finding no value that divides evenly into our candidate value. The outer loop begins on line 6 where the counter is incremented by one (thus. If on the other hand. We compare the counter with 1000 and. we exit. First we increment the counter (hence.35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 * * TABLE OF NUMBERS TO SORT * TAB DC F'9' DC F'7' DC F'3' DC F'10' DC F'4' DC F'1' DC F'2' DC F'11' DC F'5' DC F'0' OUT DS CL12 END Figure 51 Bubble Sort (continued) C R2. the value must be prime so we print it and continue to the next. 125 . not 1). The inner loop begins on line 12 and extends to line 24. our inner loop counter. At line 16 we compare the value in R2.

32 DR R6. we test the next inner loop counter value.=F'1' C R3.R3 SRA R4. bits like the sign bit are supplied at the high end.R3 SRDA R6. For example.L'OUT+L'OUT1 B LOOP SUBEXIT DS CL12 DC C' IS PRIME' END Figure 52 Search for Prime Numbers 22. The quotient will be in R7 and the remainder in R6. 1 PRIME 2 3 4 5 6 LOOP 7 8 9 10 11 12 13 14 15 INNER 16 17 18 19 20 21 22 23 24 25 26 PRIME 27 28 29 30 DONE 31 32 OUT 33 OUT1 34 35 SUBENTRY EQUREGS L R3.=F'1' CR R2.Otherwise. Next we divide the candidate by the inner loop counter on line 21. the equivalent hexadecimal is: 126 .=F'1' A R2. If the remainder is not zero.=F'1000' BE DONE LR R4.R2 C R6.1 L R2.6 Print a String in Hexadecimal The program in Figure 54 prints a string of characters in their equivalent hexadecimal notation. If a number is prime. we print it at line 26 then branch back to the outer loop for the next candidate to test. If the remainder is zero (line 22).=F'0' BE LOOP B INNER * CANDIDATE NUMBER TO TEST * DONE? * CALCULATE INNER LOOP LIMIT * DIVIDE BY 2 * INNER LOOP COUNTER * INNER LOOP LIMIT TEST * PREPARE EVEN/ODD REGISTER PAIR * CHECK THE REMAINDER * NOT PRIME XDECO R3. This places the candidate into R7 and (since we are only using positive numbers) zeros out R6.OUT XPRNT OUT.R4 BNL PRIME LR R6. Since our numbers are all positive.=F'3' A R3. if the string is ABC123. the number is not prime and we branch back to the outer loop. Note: when doing a right arithmetic shift. we load the candidate outer loop counter into R6 and double shift it 32 bits to the right into R7. the sign bit is always zero.

We need to extract the high order four bits. For each byte. Registers R4 through R6 are set to zero (lines 8. The loop control is the BCT instruction on line 25. . if the four bit field has 1010 (10 in base 10).it is only and equate symbol. does exist at run time and will be initialized with the value of STRX. When R2 is zero. index. R5 will be a register into which we load the input characters and R6 will be an offset into the output string. STRLEN. no branch is made and the loop ends. 4.C1C2C3F1F2F3 The program will advance through the input string byte by byte. R4 will be an offset into the input string. it will index to the eleventh position in the table where there will be a character A. This value is declared as an A-type address constant whose value is the location counter value of the label STRX. The SRA on line 13 shifts the contents of R5 to the right by four. however.this instruction only modifies the low order 8 bits so the high bits remain zero). Beginning on line 12 we loop through the input until done. Each time the BCT is executed. When R2 is still greater than zero.9. For example. Atype address constants are often used for this purpose since they permit initialization of their run time content by computer values as is the case here. The length of the input string is loaded into R2 (line 7). it will first extract the high order four bits and use these as a number (between 0 and 15) to index into a table of equivalent printable characters which correspond to the value of the four bit field. our offset into the string. This removes the low order 4 bits and causes what were the high order four bits of the low byte to now be in the 127 2. STRX could not be loaded directly because it does not exist at run time . 3. and 10). On line 12 we use the Insert Character instruction to load a byte from the string into the low order 8 bits of R5 (we zeroed all the bits of R5 . 5. STRX gets it's location counter value from the EQU directive which calculates the difference between the current location counter and the location counter at the beginning of STRING. The assembler will construct the base and displacement for STRING and also place R4. the value in R4 will increment by one for each passage through the loop (line 23). As the loop progresses. it decrements the value in R2 (the string length) by one. The program proceeds as follows: 1. branch is made to LOOP. into the index register position. offset 10 into the table is to the eleventh element. The length is derived from the value stored at label STRLEN on line 33. and base format. The address of the byte to be loaded is computer with the displacement. do a lookup and copy a result to the output then do the same for the low order four bits. Note: the table begins at zero. Hence. While STRX is not really an address. We now have an input character in the low order 8 bits of R5.

the word data structure is contained in a table whose declaration is on line 120. Note that the length of the output is twice the length of the input (there are two character of hexadecimal for each input character). This is done on line 19. Line 25 determines if we should process any more characters as noted above. if the value in R5 is 10 (decimal). 6. 9.the size of the computer word on early mainframes. These are ones. Lines 20 through 22 do the lookup and store the result. 22. In this example. Information storage and retrieval systems often index documents based only on a maximum number of characters in a word. The previous contents of R5 are lost in this operation.low order position. we will load A into the low byte of R5 and likewise for any value in R5 between 0 and 15.7 Word Count Program The following program builds a dictionary of words. the data structure for each word will be eight characters of text followed by four bytes of of binary giving the number of time the word has occurred in the input text. Note that the table begins on a full word boundary. 7. We do this by and And instruction with a mask. The stem of a word is mainly in the first part of the word. line 23 increments the offset into the input. The Salton SMART System was originally based on six character words . This is insured by the declaration on line 116. R5 will consist of 28 bits of zeros (high order bits) followed by the four bits that were in the high end of the input character. Lines 18 through 22 process the low order four bits from the original character. Word counts are useful to identify common and infrequent words which may make poor indexing terms. As we have now processed all 8 bits of the input character. It stores up to 1000 words of length up to 8 characters and maintains a count of the number of times each occurs. R5 is now a number between 0 and 15 and the offset into our lookup table. we only need to eliminate the high four bits. The notation 0F in a DS statement causes the assembler to allocate zero instances of a full word binary but it has the effect of forcing the assembler to advance to the next full word boundary (an address value evenly 128 . only the low order four bits will remain. The mask is a 32 bit value in memory with binary zeros in all but the last four bits. TABLE is a string containing the characters 0 through A used to represent hexadecimal numbers. It is a 12000 byte table thus allowing for 1000 12 byte entries. On line 14 we use the Insert Character instruction indexed by the value in R5 to load a character from TABLE. Thus. When this mask is and'ed with another 32 bit value. On line 15 we store the low order byte from R5 into the output string and increment the offset into the output string on line 16. Line 27 writes to output. 8. To process the low bits. In the program in Figure 54.

The structure of the table at TAB is not visible in the declaration.OUT(R6) LA R6. the next declaration. We could have more than one base register but it 129 . BRANCH IF > 0 * PRINT RESULTS DC C'THIS IS A TEST STRING 0123456789' EQU *-STRING DC A(STRX) DS CL(STRX*2) DC X'0000000F' DC C'0123456789ABCDEF' END HEX Figure 53 Print Hex Equivalent This is important because each full word binary word count in the table must itself be on a full word boundary in order to be accessible by the Load and Store (and other) instructions. The LTORG causes any literals.OUT(R6) LA R6. Note that the table TAB is declared last.1(R0.STRX*2 SUBEXIT STRING STRX STRLEN OUT MASK TABLE * * * * * * * * * * * * * * * LENGTH OF STRING OFFSET INTO INPUT STRING REGISTER TO RCV STRING CHARS OFFSET INTO OUTPUT STRING LOAD NEXT INPUT CHAR MAKE 4 HIGH BITS the 4 LOW BITS LOAD CHAR FROM HEX TABLE STORE CHAR in OUTPUT STRING INCREMENT OUTPUT OFFSET LOAD INPUT CHAR AGAIN ZERO HIGH 4 bits LOAD FROM HEX TABLE STORE TO OUTPUT INCREMENT OUTPUT OFFSET INCREMENT INPUT OFFSET HEX * DECR R2.STRING(R4) N R5.R4 SR R5.R6) LA R4.MASK IC R5.STRING(R4) SRA R5. the largest displacement allowed. any literals will appear prior to our definition of TAB. Note that the LTORG appears before the TAB definition.R5 SR R6.1(R0.4 IC R5.1(R0. elements looking like =F'100'. the table TAB begins on a full word boundary.R4) BCT R2.LOOP XPRNT OUT.TABLE(R5) STC R5.R6) IC R5. to be placed in memory beginning at the point where the LTORG appears. What is the problem with TAB? Since the extent of TAB is much larger than 4095.divisible by 4). the structure is imposed on it by the code which maps this area of memory to be a table of 1000 elements. Rather.R6 LOOP IC R5.TABLE(R5) STC R5. Thus. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PRINT NOGEN EQUREGS SUBENTRY WTO 'HEXADECIMAL' L R2. Thus.STRLEN SR R4. anything placed after TAB would be out of using for our single base register.

is unnecessary. Next we modify the TR table offsets for the hyphen and single quote which will likewise be retained in the resulting input image. in this case. The net effect: input containing upper or lower case letters will be converted to upper case letters. after the TR instruction on line 9. 4. we replace the blanks in the table at the offsets associated with the upper and lower case character with the upper case equivalent. at the offset into the table associated with the letter a we replace the blank with a capital A. The TR table: We declare an area of memory 256 bytes long (as normally the case with a TR table) and we initialize each byte to blank . The ORG directive resets the assembler's location counter back into the address space of the table. That is. The input consists of lines of text up to 80 characters long. In these lines. we fall through to line 17 where we increment the pointer in R3. compare it with the limit value in R4. The first set of changes are lines 92 through 105. Thus. Thus. the DC statement replace the blanks. we scan each input image and extract each word. We only need that the first byte of TAB be within using as we can address it directly from that point as will be seen. Retention of hyphens and single quote marks was based on the input used (Dryden's translation of the Aeneid) to test this application in which these characters were important. 130 . hyphens and single quote marks. the input image consists only of blanks. The program works as follows: 1. If we have reached the end of the input. Each input line is processed by a Translate (TR) instruction to remove punctuation (except the hyphen character) and numerics. We do this for all the alphas. On Line 11 we load the address of the input image into R3 and the address of the end of the input image into R4. The TR uses the table declared on lines 91 through 112. every character looked up will return a blank.the default (line 91). Input is processed in a loop of code beginning at line 7 and extending through line 62. Input is read into the field IN on line 7 and a branch is made to EOF when there is no more data (line 8). If it is not. 3. upper case alphabetics. On line 14 we test if the byte being pointed to by the contents of R3 is a blank. when the TR looks up a lower case a. At this point. it will return (and substitute) a capital A. If it is. Once repositioned. Next. not counting the CR/LF. Next. 2. we backup into the table by means of the ORG directive and change some of the blanks. The TR converts all alphabetics to upper case (a common case for indexing terms is normally used in retrieval applications). is the address just beyond the TR table. The final ORG with no operand causes the location counter to spring back to the highest value it has had so far which. we branch to label L2. we branch to 5.

Lines 24 through 28 locate the end of the word by incrementing the input pointer (R3). Now we need to do a lookup on the table to see if we have this word. the start of the table is within using. Since the second byte of the MVC at label MVC is a zero. 9. we can load its address. 10. We then (line 27) test if the character pointed to by the contents of R3 are a blank. Thus. We copy R3 to R6 and subtract R5 from R6 leaving in R6 the length of the word that begins on at the address contained in R5. we ignore blanks in the input. Lines 38 and 39 test if we have examined the entire table. Each time we examine an entry. we advance to line 30. Initially. On line 37 we load the address of the table of words TAB into R6. On line 36 we load the count of the number existing entries in the table into R5. If not. If yes. we have examined all entries and we branch to L6 where we add our word from OUT as a new entry. we can address its contents without need for displacements as will be seen. The loop to search the table to see if our word in OUT is already in the table extends from lines 38 through 46. . R5 has the address of the starting point of the word and R3 has the address of the byte just beyond the end of the word. Reaching line 22 we know we are at the start of a word whose address we copy into R5 to preserve the origin of the word. we add it with a count of one. testing it against the limit.LOOP and read a new line of input. Thus. The CLC (Compare Logical Character) on line 41 131 8. we decrement the count in R5. If we do not find the word in the table. Thus. If not. the length of OUT). Once we have its absolute memory address in a register. If we reach the end of the input image. Lines 32 and 33 ripple move a blank across the field OUT (this program assumes no word will be longer that 30 characters. this effectively substitutes the low byte of R6 into the length portion of the MVC instruction and exactly R6 bytes are moved to OUT. we truncate long words. The EX uses the data area MVC at the label MVC. 6. The remaining bytes of OUT remain blanks. Lines 41 and 42 compare the first 8 bytes of the word in OUT with the word in the table. When the contents of R5 become zero. we branch to L1 to process the next character. COUNT is 0. This is the image of the MVC that the EX will execute after ORing the low byte of R6 (contains the length) with the second byte of the MVC at MVC. we loop and look at the next character When we get to line 30. 7. Each table word is followed by a four byte binary integer giving the number of times the work as appeared. 11. we branch to label L4. The words in the table are no longer than 8 bytes. In line 34 we use the EX (Execute) command to move R6 bytes from the input beginning at the address contained in R5 to OUT. Even though most of TAB is beyond the reach of using (base register + 4095).

TRTAB LA R3.R3) CR R3. Note there is no displacement. we arrive at label L6. We load into R5 the 4 bytes offset 8 bytes from the word in the table. PRINT NOGEN EQUREGS SUBENTRY WTO 'WORDS' 13.PROCESS NEXT CHARACTER L1 L1A CLI 0(R3).C' ' BNE L2 LA R3. increment it. The first operand begins at label OUT and the second operand begins at the address contained in R6. decrement the count in R5 and branch to look at the next entry.80(R0. At label L6 we know that R6 will be pointing at the 1st byte of the next available 12 byte slot in the table. If we looked at every entry in the table and did not find the word. To this we add 1 and then store the result back in the table. the 4 byte binary count entry.1(R0.R3) * CVT UPPER CASE & REMOVE NON-ALPHAS * ADDRESS OF END OF INPUT * BLANK? * BRANCH IF NOT BLANK TO PROCESS WORD * * * * INCR PTR INTO INPUT AT END? YES . test it against the table limit. load a 1 into R7 (line 54) and store the 4 byte binary 1 in the last 4 bytes of the 12 byte entry (line 55). If they do not. and store it (lines 56 through 60). we increment the contents of R6 by 12 (line 44). We load the original value of COUNT. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 WORDS LOOP XREAD IN.80 BC B'0100'. if any. lines 48 through 51 increment its count. If the words match. If we find the word.EOF TR IN. We simply copy the first 8 bytes from OUT to the 1st 8 bytes of the new entry we are creating (line 53). Then we branch to the top to process the next word (label L1A). we branch to L7 to increment the count for this word. The we return to the top to process the next word.END OF INPUT STRING NO . Lines 64 through 77 print the table of words and counts using a similar loop to that used to search the table above. 12.specifies an 8 byte length. R6 has the address. 14.IN LA R4. that is.R4 BNL LOOP B L1 Figure 54 Dictionary Program (continued on next page) 132 .

R4 BNL L4 CLI 0(R3).R6) S R5.1(R0.R0) ST R7.=F'1' ST R5.8(R0.=F'1' B L5 * COPY WORD START ADDR TO R5 * * * * * * * * * * * * * * INCR INPUT POINTER END? YES BLANK? NO .R5 MVC OUT(1).R5) BCT R6.COUNT B L1A L6 * PROCESS NEXT INPUT WORD * * * * * * * * * * TABLE ADDRESS COUNT OF ENTRIES EMPTY? DONE COPY WORD TO OUTPUT STRING LOAD WORD COUNT CVT WORD COUNT TO CHARS WRITE WORD AND COUNT INCR TO NEXT ENTRY DECR R6 AND REPEAT IF > 0 EOF L8 LA R5.1(R0.BLANK MVC OUT+1(29).CONTINUE COPY WORD END ADDR TO R6 LENGTH OF WORD IN R6 COPY BLANK TO POSITION 1 PROPOGATE BLANK COPY WORD TO OUT NUMBER OF ENTRIES IN TABLE START OF ARRAY OF ENTRIES NO MORE ENTRIES IN TABLE TO LOOK AT? YES L4 L5 * COMPARE NEW WORD WITH TABLE ENTRY * FOUND WORD IN TABLE * INCREMENT PTR TO NEXT ENTRY * DECREMENT LOOP COUNTER * CONTINUE * * * * * * * * * * * * WORD FOUND .L8 Figure 54 Dictionary Program (continued) (continued on next page) 133 .12(R0.TAB L R6.COUNT C R6.OUT+8 XPRNT OUT.1(R0.C' ' BNE L3 LR R6.OUT EX R6.0(R5) L R7.8(R0.R6).COUNT LA R5.12(R0.R3 SR R6.MVC L R5.R3) CR R3.R3 LA R3.8(R0.R6) B L1A MVC 0(8.=F'1000' BNL ERROR ST R5.R5) XDECO R7.OUT LA R7.8(R0.TAB C R5.22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 L2 L3 LR R5.=F'0' BE L6 CLC OUT(8).=F'0' BE BYE MVC OUT(8).COUNT LA R6.R6) L R5.LOAD COUNT INCR COUNT STORE COUNT LOOK FOR NEXT WORD IN INPUT COPY WORD TO TABLE LOAD 1 INTO R7 STORE IN COUNT FIELD MAIN COUNT OF ENTRIES INCR TEST LIMIT OVER LIMIT STORE UPDATED COUNT L7 L R5.R5) C R5.0(R6) BE L7 LA R6.20 LA R5.R6) A R5.

75 BYE L R5.0(R5) * FOR EX INSTRUCTION 86 IN DS CL80 * INPUT STRING 87 COUNT DC F'0' * NBR ENTRIES COUNT 88 * 89 * TRT TABLE TO CONVERT TO UPPER CASE AND REMOVE NON-ALPHAS 90 * 91 TRTAB DC 256C' ' 92 ORG TRTAB+C'a' 93 DC C'ABCDEFGHI' 94 ORG TRTAB+C'A' 95 DC C'ABCDEFGHI' 96 97 ORG TRTAB+C'j' 98 DC C'JKLMNOPQR' 99 ORG TRTAB+C'J' 100 DC C'JKLMNOPQR' 101 102 ORG TRTAB+C's' 103 DC C'STUVWXYZ' 104 ORG TRTAB+C'S' 105 DC C'STUVWXYZ' 106 107 ORG TRTAB+C'-' * RETAIN HYPHENS 108 DC C'-' 109 110 ORG TRTAB+C'''' * RETAIN SINGLE QUOTES 111 DC C'''' 112 ORG 113 114 LTORG * LTERALS NEED TO BE AHEAD OF TABLE 115 116 DS 0F * FULL WORD ALIGN 117 * 118 * TABLE IS 1000 ENTRIES. 120 * 121 TAB DS 12000C 122 123 END HEX Figure 54 Dictionary Program (continued) 134 .OUT * CVT TO PRINTABLE 77 XPRNT OUT.TABLE OVERFLOW' 81 SUBEXIT 82 83 BLANK DC C' ' 84 OUT DS CL30 * OUTPUT STRING & TEMP STORE 85 MVC MVC OUT(0).COUNT * TOTAL NUMBER OF ENTRIES 76 XDECO R5.12 * PRINT TOTAL 78 SUBEXIT 79 80 ERROR WTO 'ERROR . EACH ENTRY IS 8 CHARS FOR WORD 119 * AND 4 BYTES COUNT.

BRXLE CHECKSUM CKSM COMPARE CR COMPARE C COMPARE AND FORM CODEWORD CFC COMPARE AND SWAP CS COMPARE DOUBLE AND SWAP CDS COMPARE HALFWORD CH COMPARE HALFWORD IMMEDIATE CHI COMPARE LOGICAL CLR COMPARE LOGICAL CL COMPARE LOGICAL (character) CLC COMPARE LOGICAL (immediate) CLI COMPARE LOGICAL C. UNDER MASK CLM COMPARE LOGICAL LONG CLCL COMPARE LOGICAL LONG EXTENDED CLCLE COMPARE LOGICAL STRING CLST COMPARE UNTIL SUBSTRING EQUAL CUSE CONVERT TO BINARY CVB CONVERT TO DECIMAL CVD COPY ACCESS CPYA DIVIDE DR DIVIDE D EXCLUSIVE OR XR EXCLUSIVE OR X EXCLUSIVE OR (character) XC EXCLUSIVE OR (immediate) XI EXECUTE EX EXTRACT ACCESS EAR INSERT CHARACTER IC C C C C C C C C C C C C C C C C C C C C Table 20 General Instructions (continued on next page) 135 .23 General Instruction Set Name Mnemonic Type CC OpCode RR RX RX RI RR RX RR RX SS SI RR RX RR RX RR RR RR RX RR RX RS RS RI RI RI RSI RSI RRE RR RX S RS RS RX RI RR RX SS SI RS RR RS RRE RRE RX RX RRE RR RX RR RX SS SI RX RRE RX C C C C C C C C C C 1A 5A 4A A7A 1E 5E 14 54 D4 94 05 45 0D 4D 0C 0B 07 47 06 46 86 87 A75 A74 A76 84 85 B241 19 59 B21A BA BB 49 A7E 15 55 D5 95 BD 0F A9 B25D B257 B2|4F 4E B24D 1D B2|5D 17 57 D7 97 44 B24F 43 ADD AR ADD A ADD HALFWORD AH ADD HALFWORD IMMEDIATE AHI ADD LOGICAL ALR ADD LOGICAL AL AND NR AND N AND (character) NC AND (immediate) NI BRANCH AND LINK BALR BRANCH AND LINK BAL BRANCH AND SAVE BASR BRANCH AND SAVE BAS BRANCH AND SAVE AND SET MODE BASSM BRANCH AND SET MODE BSM BRANCH ON CONDITION BCR BRANCH ON CONDITION BC BRANCH ON COUNT BCTR BRANCH ON COUNT BCT BRANCH ON INDEX HIGH BXH BRANCH ON INDEX LOW OR EQUAL BXLE BRANCH RELATIVE AND SAVE BRAS BRANCH RELATIVE ON CONDITION BRC BRANCH RELATIVE ON COUNT BRCT BRANCH RELATIVE ON INDEX HIGH BRXH BRANCH RELATIVE ON INDEX LOW OR EQ.

INSERT CHARACTERS UNDER MASK INSERT PROGRAM MASK LOAD LOAD LOAD ACCESS MULTIPLE LOAD ADDRESS LOAD ADDRESS EXTENDED LOAD AND TEST LOAD COMPLEMENT LOAD HALFWORD LOAD HALFWORD IMMEDIATE LOAD MULTIPLE LOAD NEGATIVE LOAD POSITIVE MONITOR CALL MOVE (character) MOVE (immediate) MOVE INVERSE MOVE LONG MOVE LONG EXTENDED MOVE NUMERICS MOVE PAGE (facility 1) MOVE STRING MOVE WITH OFFSET MOVE ZONES MULTIPLY MULTIPLY MULTIPLY HALFWORD MULTIPLY HALFWORD IMMEDIATE MULTIPLY SINGLE MULTIPLY SINGLE OR OR OR (character) OR (immediate) PACK PERFORM LOCKED OPERATION SEARCH STRING SET ACCESS SET PROGRAM MASK SHIFT LEFT DOUBLE SHIFT LEFT DOUBLE LOGICAL SHIFT LEFT SINGLE SHIFT LEFT SINGLE LOGICAL SHIFT RIGHT DOUBLE SHIFT RIGHT DOUBLE LOGICAL SHIFT RIGHT SINGLE SHIFT RIGHT SINGLE LOGICAL STORE STORE ACCESS MULTIPLE STORE CHARACTER STORE CHARACTERS UNDER MASK STORE CLOCK STORE HALFWORD STORE MULTIPLE SUBTRACT SUBTRACT SUBTRACT HALFWORD SUBTRACT LOGICAL SUBTRACT LOGICAL ICM IPM LR L LAM LA LAE LTR LCR LH LHI LM LNR LPR MC MVC MVI MVCIN MVCL MVCLE MVN MVPG MVST MVO MVZ MR M MH MHI MSR MS OR O OC OI PACK PLO SRST SAR SPM SLDA SLDL SLA SLL SRDA SRDL SRA SRL ST STAM STC STCM STCK STH STM SR S SH SLR SL RS RRE RR RX RS RX RX RR RR RX RI RS RR RR SI SS SI SS RR RS SS RRE RRE SS SS RR RX RX RI RRE RX RR RX SS SI SS SS RRE RRE RR RS RS RS RS RS RS RS RS RX RS RX RS S RX RS RR RX RX RR RX C C C C C C C C C C C C C C C L C C C C C C C C C C BF B222 18 58 9A 41 51 12 13 48 A78 98 11 10 AF D2 92 E8 0E A8 D1 B254 B255 F1 D3 1C 5C 4C A7C B252 71 16 56 D6 96 F2 EE B25E B24E 04 8F 8D 8B 89 8E 8C 8A 88 50 9B 42 BE B205 40 90 1B 5B 4B 1F 5F Table 20 General Instructions (continued) (continued on next page) 136 .

Step Carefully (for improved accuracy) Rewind Tape and Break ReWind DiSK Scramble Program Status Word Seek Record and Scar Disk Water Binary Tree Figure 55 Over-Extended Instructions (humor) 137 . that is): ARG BDM CMN DDS EMR ETO FSE GSI GQS HEM IDD IKI IMU JPF JUM KFP LNM MAW NNI OBU PNG QWF QVC RWD SCE SDJ TTC UBC VDP VMB WAF XID YII ZAM PI POPI RASC RPM RSSC RTAB RWDSK SPSW SRSD WBT : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Agree to Run Garbage Branch and Destroy Memory Convert to Mayan Numerals Damage Disk and Stop Emit Microwave Radiation Emulate Toaster Oven Fake Serious Error Garble Subsequent Instructions Go Quarter Speed Hide Evidence of Malfunction Inhale Dust and Die Ignore Keyboard Input Irradiate and Mutate User Jam Paper Feed Jeer at Users Mistake Kindle Fire in Printer Launch Nuclear Missiles Make Aggravating Whine Neglect Next Instruction Overheat and Burn if Unattended Pass Noxious Gas Quit Working Forever Question Valid Command Read Wrong Device Simulate Correct Execution Send Data to Japan Tangle Tape and Crash Use Bad Chip Violate Design Parameters Verify and Make Bad Warn After Fact eXchange Instruction with Data Yield to Irresistible Impulse Zero All Memory Punch Invalid Punch Operator Immediately Read And Shred Card Read Programmers Mind Reduce Speed.SUPERVISOR CALL TEST AND SET TEST UNDER MASK TEST UNDER MASK HIGH TEST UNDER MASK LOW TRANSLATE TRANSLATE AND TEST UNPACK UPDATE TREE SVC TS TM TMH TML TR TRT UNPK UPT RR S SI RI RI SS SS SS E C C C C C C 0A 93 91 A70 A71 DC DD F3 0102 Table 20 General Instructions (continued) Over the years people have suggested a number of interesting if less practical extensions (humorously.

138 .

............................................................................................................................16 Index registers......................................16 Base/displacement addressing............................................................................................................................. 52..........................................................................................9 Immediate operand........................................................................................................................................................... 81 BCD................................................................................................87 Move Numerics.................110 Halfword Instructions.........................35 Machine Language Format................................15 GET... 84 Alignment...........................................................................................................................................................................................................................................................................................................................................................97 BXLE................89 CISC..................................................................51 139 .................................................................................................................. 109 LTR............. 9 ARCHLVL3.......................................................................................................................72 Logical shift instructions...........................................................................................................................................................................................95 Load Negative......................................................................................................................................................................................................................................................................................................87 MP.................. 66 Entry point...............................................102 MVC................................ 110 Compare logical character................... 95 Labels..................................................83 Hexadecimal.......................................................................................................90 Move Immediate........ 97 ARCHLVL1................ 109 CSECT................................... 83 Line Format..................................................................................70.....................................................43 CR/LF..............................................................................109 Mask......................102 DP................... 18 LCR.....96 Location counter......... 11 Binary integer......................................................52 Bit Operations............................................................................. 9 2s Complement.........................................................................................80 Floating point.................................................................................................................................................................................................................. 87 MVI)........................................ 97 NR.............48 EX......................................................................................................................................96 Load Multiple....................97 Boolean instructions.............. 88 Literals......................................... 75 EBCDIC......................................................................................................................................88 Compare Logical Character Long...................................... 10 CLC...... 49 Binary.......................................................................................................................................35 MACRF....... 96 LRECL.................................................................................. 48 CAFE....................................18 Linkage................ 110 DDNAME................95 Load and Test........................................................................................................................................................................................................................45 Extended Mnemonics.................................................... 103 MVZ.............................................. 87 MVN......... 85 DB......................................................110 EQUREGS..................................98 Explicit Addressing.......... 97 NI.......................................... 51 DC........................ 69 Floating point registers......................... 9 Arithmetic shift instructions.......................................................................................... 52 ED...........................................................................................................................................................................................101 Declare constant................................................................... 52......................................................................... 84 AND........ 84 Multiply..................................... 62 CVB................................ 102 End-of-file........................................ 49 BCTR........ 97 Numeric data types................................................................................................................................................... 87 MVCL....... 102 EDIT......................................................... 62 Base/displacement..................................................................................................................................59 LM..................................................................................................................................................................................................... 95 LNR..... 89 CLI...................32 L.............................................43 Conditional Branching (BC................ 85 Divide Packed........... 52 D....................57 Declare storage............... 71 AH......................................................................................................................................... 11 IBM 360..... 112 CVD...............................................54 24 bit address............................................................................. 69 Binary Integers.........................................43 Conditional branch...........103 Divide....................................................................44 MH................................................................................................... 98 LH....................................................................................................................................................................... 57 ALR.........................87 BC.................. 83 AL..................................99 LPR........ BCR)................................................................... 102 DR........................... 102 MR..................................15 General purpose registers............ 103 N.............31 Extended mnemonic...........................................................52 A................................................................... 57 Dump............................................................................................................................................. 51 BCT...............................................................................................................100 BAL................................................................................................................................................................................................................................................................................. 90 MVI.. 89 CLOSE........................................................................................................ 84 Machine language............................................................................... 57 DCB............................................................................................................................................................................98 Condition Code/.................51........................103 Move Zones.....................................................96 Load Positive............................................................................................................. 9 ARCHLVL2.............................. 32 Index register... 85 Move Character Long...................................................................................................................................................................................................................15 Basic Character Instructions..................................................................................................................... 61 EODAD...........................103 Moving Characters....... 51 Character Long Instructions............................... 96 Load..........................................29..........................................51......................................................................................................18................................................... 96 M.......................................... 97 NC.................................................... 106 DS.......................................................................................................................................84 Multiply Packed..57 Digit selector.............................................................................. 110 Decimal Arithmetic................................61 Literal............................................................................................................................................................................ 23 Even/odd register pairs............................................................................................................... 88 CLCL...........Alphabetical Index 1s complement...................................................................................................................... 61 Linkage Registers............. 88 Exclusive OR..........................................................................88 Complement................................................................................................. 85 DROP.................................................................... 43 Mask settings......................89 Compare Logical Characters................................................

........................................................................................................................................... 98 OC............................62............................. 97 ORG.............................................................19......38 Sign and magnitude........... 84 SLDA.....................65 Zoned Decimal.................... 98 OI..........................................36 S......................................................101.......................................................................................................................... 83 Save Area.................................................. 98 XPRNT.............................................. 98 XC............................................................................................................................................................................................. 100 TR.........................................................66.................................................................................. 61 SH........................................ 63 PUT.....................................................................................33 Test and Set................. 83 SS Machine Language Format.... 98 XREAD....................... 84 SR................................................................................................. 95 Store.............................................................67 XI..................... 110 QSAM.............................................................103 SL.............................................. 71 XDUMP........................................................ 84 SLR..................................................................... 90 Translate and Test............ 67 XDECO..................................................................................................................................................................................................... 98 XDECI...............................................33............................................. 83 Shift......................................................... 19 Subtraction... 99 SI Format..103 UNPK..........53 PRINT NOGEN.........................................................95 SUBENTRY................ 111 Zoned format..... 83 Symbolic Addressing....................................................................................................................................................................... 111 Padding bytes.......O...............................................................................................66 XDECI ..............................................................................................58 Powers of two................................................................................................ 101 UNPACK................................................................................................................................................................... 41................................................ 95 STH...............................................................16 RR Machine Language Format............... 23 PRN File................................................... 67.........................................................................................................................................................................52 Significance starter............ 103 Unsigned arithmetic............. 106 X.......................................................................39 ST...................................................................................... 29 SI Machine Language Format. 83 STM.................................................... 91 Overflow......................... 84 SLA.......... 83 PACK........................................... 112 Packed Decimal.....................................................................100 TM.................................................................... 90 TS...............................................67 XHEXO...............84 USING........................................................................................................................................................................................................................................................................51............................................................66 XHEXI...............................................................................................35 RS Machine Language Format................................................................................................................41 PSW........................................................................................ 83 Overflows........................ 109 Relocatability................................................................................................ 109 RECFM......101 Test Under Mask.............. 34 SUBEXIT.............................................................37 RX Machine Language Format....................................................................................... 65 XR.....95 Store Multiple...............................................................51...................90 TRT.............................................................................................. 69............................................................................................................. 70.... 98 OR.....................51 140 ....................18.................................................... 72 Program Status Word..........................................................................................................................................................................

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