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Astro Tips

Astro Tips

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1.powerful PhySiSys" technology and the new Milkyway-DUO" (Dynamic Unified Optimization) architecture.

2. including timing, signal integrity, crosstalk, power, die size, routability and manufacturability. 3.design closure 4.synthesis netlist optimization 5.physically accurate silicon models 6.Milkyway Duo is the run-time database. 7.Astro & Apollo: most of the key algorithms have been rewritten including logic optimization, timing analysis, placement, and clock tree synthesis. Other features have been added such as hierarchy preservation and overlap removal. 8.parasitic extraction, 9.dump out the HSPICE information 10.CG (netlist):CG: Common Graph: common graph is a bare bones netlist. 11.PDS: Placement Driven Synthesis 12.Call Back: 13.Overlap Removal:It allows functions like PDS and CTS/CTO to instantaneously determine the effects of a sized or added cell and then remove the change if it degrades performance. 14.Apollo/Saturn. 15.Some simple methods of optimizati on are not used by Saturn, such as gate duplication, net splitting, and inverter insertion. 16.Scan optimization includes the ability to maintain the original module ports in the hierarchical netlist. 17.Congestion based coupling estimation for preroute extraction. 18.manufacturability issues (such as antenna checking and fixing). 19.*************************** In addition to continuing to support Synopsys .lib format, with Astro, Synopsys adds translation of Synopsys STAMP models. In addition ALF model s are also supported. All of these are translated into Synopsys CLF format and/or Astro TIM model format. ***************************** Cadence: ILM model: Interface Logical Modeling 20.Create Capacitance Model: TLU Cap Models

Map ap2ast 22.Dont use EXP view to do astInitHierPreservation.Backslash before hierarchical name. Expand the netlist (.Loading Power Supply Information 27.HCG (Hierarchical Common Graph):astInitHierPreservation modules that must be preserved:astMarkHierAsPreserved 29. Add Cells not in the netlist such as pwr/gnd pads.NETL view) to create a . crosstalk analysis will still work since it can be based on a voltage value independent of supply value. Astro will only read SDC syntax for timing constraints. Create a cell view .AWE 26. For single voltage supply designs the result will be the same with or without the supply loaded.CEL and bind netlist view . crosstalk analysis will use power supply information loaded into the tool. then at a minimum. 34.Logically Equivalent Cell (LEQ) Information 25. astInitHierPreservation.TLU Wire Delay Model .If loaded.EXP. ****************************** If not provided. ******************************* 28. timing constraints are stored in the cell database in a TDF table.Read in verilog description to create .NETL view.StarRCXT ITF file. If you want to dump a hierarchical netlist using astDumpHierVerilog.ApolloToAstroCmdConversion. expanded netlist view (.In Apollo. should be done.CEL and TIM views in Apollo. 23. 24.Delete hicon ports using astRepairHierPreservation since PrimeTime can not find these nets.EXP view. CLF 30.EXP). users are recommended to load the power supply information in order to get accurate analysis since noise metrics are percentages of the power supply.Cell Delay Model . 32. use the CEL and NETL . Strip BackSlash This option will strip the backslash before the hierarchy separator. Set power/ground ports using Preroute > Connect Por ts to P/G Initialize hierarchy preservation information using 31. 33. For multiple voltage designs. In almost all cases it should be left at the default value of ON. 21.

Use astCheckHierPresConsistency.TLUPlus uses Star-RCXT model generation to create TLU capacitance tables. 36.Either astInitHierPreservation or cmCreateHierPorts should be run prior to loading SDC file in order that SDC constraints to hierarchical ports (which disappear during flattening) can be properly considered. 44. 40. This command checks if hierarchical information (HCG) in the cell is consistent with the flat CG. TDF: Timing Setup Tabs.LPF: 49. 51.ExamineSDC: set_propagated_clock set_case_analysis ******************************** 42.Astro can take both TCL based and non TCL based SDC constraints.Often constraints used for final timing verification. it is not correct to set propagated clocks or allow data/clock mixed paths prior to building the clock tree.Net Delay Model It is recommended to set Elmore prior to routing and AWE after routing. ******************************** 41.TDF pin/pad commands will be used to control the physical location of pins and pads only. It is better to load SDC with wildcards into Astro than an expanded SDC. . 37. 39. or for initial synthesis.Timing > Write Design Constraints (astWriteDC) Input is : SDC 47.views. It generates CGHIER errors. O ther examples include the use of case analysis. 35. PPO 46. It works on a current open cell and loads CG if it is not already loaded. during PrePlacement Optimization and using Astro CTS. There are no timing related TDF commands in Astro.SDC constraints that would be generated by the write_sdc function should be avoided since they are expanded. For example.There are two ways to buffer high fanout nets in Astro. Users should see a warning message on bus Style when generating hierVerilog.OV. 43.SDC information is not backward compatible 45.LEQ 48. if there is any difference in the HCG and CG data. are not appropriate at all stages of physical optimization. 38.Remember to set correct busStyle for the library. 50.

This path will not be fixed by preplace optimization because the net is partially cl ock. In a replay script. therefore. 65. 53. Note that this placement is not based on congestion or timing or any other normal placement parameters.TIM after loading the step. scan enables should be buffered by Astro CTS since the loads will be declared as scan clock in the port types file. 63.ataCompare: This will also allow current Astro timing constraints and Synopsys CLF information to be translated to Synopsys format so that PrimeTime or DC can use the same constraints and timing information Astro uses. Currently.Zero interconnect can hide problems with SDC affecting optimization of certain parts of a design.The ataCompare command will provide all the information needed to back annotate to Synopsys DC and PrimeTime. a situation where a latch output may drive its input through combination logic. 61. 54.Loading ataSetNetCapTransAndDelay will create a .52. 64. . you can avoid the query boxes that pop up for this command by doing the following: setDisplayMode "QueryBoxes" #f geSaveAllOpenCells This is especially helpful when running in nullDisplay mode. You should immediately save the . simply do not provide any wireload models in the . 62.TIM view to store the information. the design needs to be placed for astCheckDesign to work. 60. To keep PrePlacement Optimization from buffering these nets simply declare the scan enable as a clock. 57.Astro will automatically handle high fanout nets during the f low.Typically. COmbinational feedback loop 58.lib files read by PrimeTime.To run zero interconnect timing in PrimeTime.There is data and clock mixing causing a high fanout clock node in a critical path. 59. The . 55.is timing path from latch to latch and both driven by same clock with same path. A simple way to do this is to use astFastPlace (geGetEditCell). The best way is to use Cell > Save All Open Cells! (geSaveAllOpenCells). It simply places cells in legal locations.reports latch self loops.The zero interconnect timing report after preplacement optimization provides a good indicator of final timing result. for most nets.Setting Net Transition Defaults for Non -Clock Nets 56. there is no need to set a transition or cap default. It is recommended that the user should evaluate timing closely after clocks are inserted and post-place optimization is completed and prior to proceeding to routing.lib files dumped by Astro will not contain wire load models.

Max Distance to Extract Lateral Capacitance: Also in technology file there are Cap Multiplier (Individual) settings for each layer.Interconnect Technology Format (ITF) 75.Checking TLU Cap Model Parameters 71. It i s not recommended for production flow because only limited QA is done. However. A map file will also be needed.The preferred method to reconnect and optimize is to do it after placement and clocks .Soft blockages prevent cell instances from being placed inside except for cell instances that are either fixed or softfixed.A soft-fixed cell instance cannot legally stay within hard placement blockages. 76. Apollo and Astro both do take them 73.Connections between scan outputs and scan inputs in a scan chain may not be optimal for routing after placement.lib files. to create them you need a description of the process technology in Interconnect Technology Format (ITF).(hard or soft) placement blo ckage.05 70. now.To make preroute a little more pessimistic use the settings below 68.lib files when comparing Astro to PrimeTime. However. 78. scan clocks often run at higher frequencies so that the tool needs to optimize them as well. 74.It is design dependent. 67. Synopsys recommends always using original . which may be supplied by the foundry or created by the user.05 axSetRealParam "ek" "resMultiplier" 1.Assign a level shifter cell from one voltage group to another using astSetLevelShifter. 66. Settings to adjust preroute capacitance/resistance in Astro: axSetRealParam "ek" "capMultiplier" 1. 81. in general we would like to see pre -route RC results in reasonable but little pessimistic range than post-route in order to predict design closure quality and achieve consistent design convergence.the placer engine sees soft as hard. 80. In addition hold times need to be fixed after scan flipflops are placed and the chain connections are optimized. to map the process layers to the Milkyway library technology file.Guideline would be to make preroute 3 -5% pessimistic at most. and then use route optimizations to close remaining nets. 79. but optimization commands see soft as non existent.Adjusting Preroute Pessimism/Optimism of Cap s 69.Geometry Scaling Factor: 72. 77.ataCompare is meant to aid debugging in the case that the user does not have access to the original .TLUPlus models are generated using grdgenxo.

gate-sizing. If data/clock mixing is the cause of the high slack.max transition and max capacitance are concurrently optimized during postplacement and postrouting optimizations. our strategy has been. 82. high -fanout collapse. The only acceptable source for a large negative number is if data and clock mix. ************************************* 90. The netlist changes will apply cell movement so ECO-place will be invoked. It is intended that the first time transition and capacitance constraints are fixed is during postplacement phase 1 optimization. 85. then wait until after postplacement optimization to reconnect the chain. moving-cell. high-fanout net synthesis. Setting the value to 1 will remove all buffers from the design. gate-duplication.quick Boolean matching structural-based matching 93.Area Recovery will eliminate buffers and downsize cells. 87.Therefore. ************************************ * 89. If you do not want postplacement optimization to work on the re -connected chain. If not selected it will just run ECO placement. . Setting the value lower tends not to improve optimizations much. buffer/inverter bypassing.Release Note: Max Transition and Max Capacitance are no longer optimized by preplacement optimization nor placement with ipo. we need to do more massive changes such a HFN opt before the detailed placement begins. and remapping. 92. 84.Ideal Optimization will try to optimize the design with zero interconnect.Astro. This would allow postplacement optimization to optimize the chain for timing as needed. buffer insertion. 91.If the number is very negative.This function performs a quick placement. the user should look at the critical path with zero interconnect timing.In benchmarks it has been found that when synthesis inserts buffers for fanouts greater than 10 it can interfere with Astro optimizations and increase congestion. Overlap Removal (OV) is not invoked during prePlace optimization. area-recovery. 88. at an earlier stage. net-splitting. inverter insertion.are inserted and prior to post placement optimization.Enforce Full Place makes the tool do a full quick placement before trying to fix high fanout nets. On large designs it may be better to turn this off in order to save run -time. 86. but can increase the runtime since Astro must rebuffer these nets. By default the utilization at which this occurs is 50% . 83.as specified on the timing setup panel. turn off mixed edges during timing analysis and redo zero interconnect timing after preplace optimization.dbMarkScanPortPairs and dbDumpScanPortPairs should be used if a cell has multiple scan input and output ports. Use the timing setup panel to lower this threshold if you want more recovery to occur. it is recommended to rebuffer these in Astro based on the actual physical placement.

Dump Time Borrow Script: This is primarily for back annotation purposes (mainly to Synopsys PrimeTime).Macro and I/O Net Weighting Macro nets are defined as nets connected to any macro pins.94. 99. 105. 96.astEdit can be used on designs after placement. and transition for the net and to prevent HF optimization during preplacement optimization.postplace optimization phase 1 postplace optimization phase 2 100. or . Some users may find it more convenient to buffer large high fanout nets.Useful skew is a method of intentionally skewing a clock in order to improve the timing on a circuit. 101. and 10 having more emphasis on timing.The Constraint File on this form refers to a file that contains user -defined cell clusters that the placer should attempt to place together. and cell clusters.There are two basic flows given in the Astro Primer: CTS with Useful Skew. using this function after real placement is finished instead of during preplacement optimization.Incremental Place This is the same function as found in Astros ECO Placer. It can be run stand alone after a placement exists.The first uses optimizes the design completely using the useful skew budget and then recalculates useful skew prior to running CTS. and the second runs CTS based on the original budget and then finishes the optimization. 104. Useful Skew Budgeting normally be done at this stage of the flow . The borrowing script provides a way to minimize any correlation discrepancy.since it will account for errors in the original budgeting. 102. and Useful Skew Budgeting. delay. 98.Search and Refine capability. The script can be used to feed-back the amount of borrowing Astro is using for latch based designs.pdsHFNOptimization can be used to buffer non clock nets. 106.after preplacement and prior to placement. 107. Synops ys has found that you must use aggressive borrowing in order to optimize latch based designs. 95. This allows the user to specify master and instance padding. 103.Timing-driven (including IPO) Astro Place provides a smooth trade-off from 1 to 10 with 1 having more routability. like resets or enables. 97.User Place uses Overlap Removal (OV) package to incrementally remove overlap.How can I find all High Fanout Nets in a design? Use astDumpHFN: Syntax: astDumpHFN n This will dump out nets with n or more pins on it. ataSetNetCapTransAndDelayTime should be set on the net to specify a realistic capacitance. It is recommended to use the first flow in most cases . This is actually the function built into the HFN fixing contained in preplace optimization. net weights. after global route.

116. the directory will be removed automatically. 1. VSS Suppose that the vendor has spelled VDD as $VDD. etc.slew derate factor. e. buffers.after routing. A stage is uniquely identified by the net name. Suppose that the user has picked the condition to be the worst case. The user should type the worst case VDD--114. clock net. based on a qu ick global . If the user closes the Debugger Manager window. 112.g. In addition. 113.sp > temp. 120.sp mv temp. 108. 118.Note that the directory demTemp is temporary. Therefore.DETERMINING THE PROCESS TAG .sp subckt. For example.98 worst-case VDD = min best-case VDD = max typical-case VDD The GUI form has a box where the user can type the value of VDD.80.Topology Based Optimizations Topology-based optimization is used throughout the Astro design closure flow.Stage Delay Checker: A stage comprises a (signal) net. astEdit & astChangeNetlist 110. the user must suffer the consequences if they try something wrong.Topology based fixing can be run at the placement stage. that have not been accounted for in the IN place number).sp 115.Since this is done in the middle of placement. actual circuit simulation.sp subckt.placement and routing blockages. 1.sp Suppose that the vendor has spelled VSS as $VSS.astChangeNetlist: Force Change: This will allow you to change the netlist no matter what.The data book will quote three values of VDD. 117.LIB MODELSSlowSlow The third phrase is the process tag---SlowSlow in the example above.. 1. if the net is dont touch. the driver of the net and the load(s) of the net.sp > temp. 109. sed s/\$VSS/VSS/gsubckt.this is the reason POST can be worse than IN (if there were placement moves due to sizing. sed s/\$VDD/VDD/gsubckt. the timing models can be reverified against the sub circuit information.Timing/Library Debug Manager The purpose is to provide some automation to verifying the timing analysis results vs.sp mv temp. 111.SPELLING OF VDD.62. etc. etc. the timing result will not take into account all of the placement moves associated with optimization -. 119.

prior to and after propagating clocks.Clocks must be inserted after placement. Likewise because of overlap removal. With higher clock frequencies the requirement for lower skew is needed since the clock .Clock Tree Synthesis (CTS) using global skew is the traditional method of inserting clocks where CTS tries to make all the clock arrival times the same. Phase I: setup time is not considered. Fix Max Length On some designs it helps to place buffers/inverters at specified lengths prior to doing detailed optimization.**** In patch 2 of Astro In-place CTS (concurrent CTS) has been removed because of difficulties of getting the function to work dependably and non-proven results..Post-Placement Optimization Phase 1:] This is the step where we take advantage of topology based optimizations. as discussed above. in order to correctly predict this situation and place the buffer in the optimum location. it should only be run once. therefore. The overlap removal engine minimizes cell disturbances during CTS and CTO. Typically designers looked for global skews that were 200-300 ps. when inserting clocks after placement. 125. PostPS II can be done many times. prior to global routing or real routing. The reason the two are not on one form is allow the user more control. 127. ************************************************** *********** 128. Postplace phase 2 (astPostPS) should be used to close the timing by doing detailed optimizations.****************************** PostPS I can only be done oce. This tends to relieve congestion in the design.(phase 1) Redo HFN Synthesis At this stage we can base the high fanout clustering on the final placement. the timing result does not change much. Also CTO can be run after postplace opt. phase 1 will be either run before CTS or before initial phase 2 optimization (if phase 2 is done prior to CTS). the purpose of high fanout optimization was to aid optimizations and during preplacement the clustering is based on a fast placement which is enough for that purpose. 122. Typically. it is recommended to redo high fanout net fixing that may have been done previously.route. 123. Postplace phase 1 (astPostPS1) is typically done once to get the buffers inserted based on the to pology. Typically these are large designs or designs with a lot of macro blockages. ********************************** 126. In addition. Depending on if postplace phase 2 is run before or after CTS.Flow: PostPS I -> CTS -> PostPS II -> CTO ( For Patch 2) ************************************************** *********** 129. postplace opt does not disturb the CTS result significantly. Users should build clocks after placement and before postplace optimizations and then run clock tree optimizations after postplace optimizations. Previously. 121. This step will do high fanout net collapse and then redo high fanout net fixing. Phase 2 can be done as many times as desired. for example. 124.

and crosstalk Build the clocks using global skew Local Skew can increase the runtime of initial CTS Optimize the design using PostPlace Opt Phase 2 Can propagate the clocks at this time if desired Optimize the clock tree using Global or Local Skew Re-optimize using PostPlace Opt Phase 2 with clock propagation (if desired) ************************** 132.In order to handle gated clock tree. please set astDontUse property on the buffer . In the future this may be a valid addition to the above flow. cap.At this time it is not recommended to use Cl ock Tree Optimizations with useful skew. Global CTS & Local CTS.The clocks are considered in the order given on the astClockOptions form. we developed GCTS. then there can be power problems due to the simultaneous switching of all flip -flops in the design at nearly the same time.Post-Placement Clock Flow . 138. In addition. and cap to a capacitance value and then selects the smallest one. if local skew is used. if the global skew is too small. 135. please turn OFF CTA. however. If you want to set parameters yourself (like previous releases).Starting in patch 3. 136. . 130. 134.To ensure certain buffers are not used during embedded CTO. 139..period is less. using: axSetIntParam "acts" "CTA" 0 140.Basically astCTS will convert transition. 137.Useful Skew Flow: Propagate Clocks via SDC file 133.. Often. fanout.CTO will take any LEQ buffer set by astSetClockCell (or in library is astSetClockCell is not specified). This technique can reduce the skew on related flip-flops lower than the global skew of the design. 200ps skew for a 500MHz clock (2ns period) represents 10% of the clock cycle. For example. CTA (clock tree analyzer) is able to search the optimal parameters for CTS. It is recommended to put the most critical clock last in order to get best synthesis results.. Often it is difficult to reduce the global skew further on a design.Astro CTS can be used on gated and non gated trees b y selecting the Gated Clock Tree button near the top of form.Currently the best way to control the amount of useful skew is to adjust the clock period. length. strong buffers create electromigration problems.**********Flow The basic idea in this flow is to: PreplaceOpt --> gives better netlist to placer Placement with In-Place Optimization --> minimize congestion and timing PostPlace Opt Phase 1 --> redo HFN fixing and use topology based design rule fixing for transition. then the tool only tries to reduce the skew on logically related flip-flops while ignoring the skew between non related flip -flops. 131.

Top on the astCTS form Block should be used on designs consisting of mostly standard cells. The difference of embedded CTO to post-route (or standalone) CTO is that the CTS engine is able to dynamically refine its clock tree structure within the process of generating clock tree. The specified delay cells will not be used by normal Astro optimizations except hold time fixing. During CTO the tool will use all LEQ buffers defined in the library or from astSetClockCell (if set). 149.Block vs. some clusters are identified based on their locations. Qespecially if standard cells are placed around the macros When top is selected. this file may be incomplete. 147. To keep from using some buffers. 146.To control which delay cells astSetDelayCell can be used. 142. sometimes you want to CTS not to move sinks during/after CTS. the user can use astSetDontUse. The main purpose of this option is try to put fanou t pins to a same branch if they are in the closed area. CTO can delete/add nets. Each cluster is driven by a sub-tree. If you run astCTS more than once. level adjustment. ataDumpClockNets is the safest way to ensure you have dumped all clock nets. while post-route CTO focuses on further skew refinement after most of the layout implementation (especially clock tree routing) is complete. ************ ****************************** 145. Prior to patch 1. so that the nets contained in net.AstroCTS:] Sync Pins & Ignore Pins (??????????)) . Alternatively. delay cells.Embedded CTO Embedded CTO is the built-in CTO capability inside CTS. Also. Note that astSetClockCell prevents other Astro Optimizations from using the specified buffers/inverters for normal optimizations. 143. Normally both of these are not necessary.CTS produces a file of nets (net.During CTS the buffers are controlled by the selection on the clock options form. etc. However.141. dummy load insertion.g. you should rename the file before subsequent runs. Also.top should be used: chip level designs big designs (e. On the following design types.dummy load insertion. size > 1mm^2) macros are placed inside the design. the user can use separate functions specifically for Buffer Sizing and Dummy Load Insertion which provide greater control on the form for buffers. we recommend to customers to synthesize two clocks at the same time if they have logic overlap. so users must be careful in this area.acts) it creates. 148. customers utilized this file to determine which nets are part of the clock network. and nets used.Clocks with Logic Overlay: As a conclusion. It includes buffer resizing.Sometimes you may want to fix buffers/inverts after CTS to prevent them from moving in the future.acts is no longer valid. ****************************************** 144.

157. change a lot of cells locations and even change the netlist. Since CTO may break a lot of routed wires. then it does not hurt to optimize setup and hold.One method is to optimize the design at postplacement is to run postplacement opt several times: 156. 153. If setup and hold are the same as the normal operating conditions. It allows the user to provide a configuration file that completely specifies a non -gated clock tree structure and Astro will build it optimally.(above) (2) dbDefineSyncPin statements can be created for each sink on the desired net (3) pdsHFNOptimization can also be used as described at the end of the preplacement optimization chapter.Buffering Non Clock Nets using CTS: (Three Method.Buffering Non Clock Nets using CTS: (1) Define a clock using tcl . Dummy load cells should only have input p in capacitance and no logic function so that they have the smallest possible cell size to minimize the effect of additions on the layout utilization and congestion. Users should find that the Astro result is slightly pessimistic and will improve after routing. we recommend you use ECO CTS instead of CTO. then at a minimum optimize only transition and capacitance. (2) To set all inputs of a net to be synchronous. 155.Basic CTS is the Astro equivalent of Apollos MCTS (multi -level CTS). ******************************************* 152.axSetIntParam set_default_trigger_edge (3) set all back. at the same time.150. (3) remove disable timing statements from the SDC and generate timing report If the number of max transition or max capacitance constraints changes. addition of FFs and relocation of FFs).) (1) Instead of setting the trigger edge parameter. It is not expected that any significant increase in slack will occur between placed timing results . 158. The ECO CTS will consider routing costs while synthesizing and optimizing the clock tree. as well as transition and capacitance. If these ECO changes are made after routing.Synopsys recommends customers build specific dummy load cells instead of using generic buffers. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes.Incremental CTS: A design may have some ECO changes (such as deletion of FFs. If setup and hold constraints change.Astro is designed to accurately predict the routing capacitance.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing. ******************************************* 151.ensure default clock is enabled on the timing setup form (2) remove all case analysis statements and generate timing report. 154. the design should be optimized to fix the problems.Effects of SDC on Timing Analysis and Optimization: One technique to help check if there is a problem with max transition and max capacitance constraints is to examine various timing reports: (1) generate timing report with normal settings .create_clock.

track assign. 167. 164. *********???????????????????? 170. Route: during global route.in-route BI/GS 166.The recommend flow to fix crosstalk is to set prevention during global route and track assign.To see all available parameters use: axPrintParams all . or almost route. but can help on some designs.By default Astro will typically route more on the upper layers. If that is the case.Post Route CTO (astPostRouteCTO) should be used to optimize clocks after routing is completed. In many cases it would make designs unroutable.The parameter (axSetIntParam "route" "layerExtraCostByRC" 2) used to be recommended. The easiest way to do this is to use Route > Route Net Group and select All Clock Nets on the form.Similar to Apollo.e. trackassign..Global Route Optimi zation (astPostGR): This function may not always improve timing and should not be the standard flow. 162. Note that there are global route. for example.Release Note: It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. it is no longer recommended.Sometimes you will need to select CTS as Normal on the Route Common Options form in order to get routing to be completed without DRC error. This will allow tool to move clock routes further to clear errors. then ECO route should be run (with CTS nets selected with Minor Change Only on Route Common . Then run crosstalk analysis (xtXTalkAnalysis) followed by axgAdvRouteOpt with crosstalk to optimize timing and cross talk. may make some designs unroutable. adjust routing cost. 168. Following CTO. Run axgAdvRouteOpt (discussed later) without crosstalk to optimize timing . 160. ECO route should be used. therefore.. 163. To see only the route ones use axPrintParams route .The best routability will be achieved by using the defau lts. 161. as described below. it is recommended that critical clocks in Astro be routed before other signals so that they will have the most direct routing.and routed timing results. push routes more toward top or more toward the bottom.if significant timing improvement is necessary. to reconnect the routing. See Chapter13 for more details. It is recommended to only adjust the parameters after you have gotten a trial pass to route. i. Then achieve zero DRC violations after Search and Repair. and detail route. If you want to influence this. clean. 169. 159. 165. Adjusting the costs to use more upper layers (in order to utilize layers with more desirable properties). but it was found that this only works on designs that use a process with very high-resistance vias and with some customers with very different pitch/width/RC for different layers.

.Options) first. You should use axgAdvRout eOpt with only crosstalk noise.It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. Slow extraction uses the Astro TLU capacitance models.Cell > Edit-In-Place 180.Optimizing the design flow for large designs .time. If desired. and then it should be followed by Search and Repair. axgAdvRouteOpt should be run before astPostRT if normal extraction is used in astPostRT.. crosstalk and antenna fixing. ????????????????????????? 171.??? It uses In-Route extraction which will do incremental extraction and update of crosstalk information as routes are changed. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes. PARA views from Astro or StarRCXT can be used with this function. but it should be run after astPostRT if fast extraction (Real R . Therefore if using Slow extraction astPostRT should be run after axgAdvRouteOpt.Post Route Optimization (astPostRT): Fast Extraction: This runs based on Real R and Virtual C (based on actual route) in order to do a quick optimization without a full -blown extraction. On Page 218. and b) that Store coupling mesh should be used if you wish to analyze crosstalk using parasitic views. then astPostRT should be run before axgAdvRouteOpt. 174. Prior to Search and Repair.xtXTalkAnalysis (Xtalk analysis) (***) axgAdvRouteOpt has fixed crosstalk violations through buffer insertion. . so it is better to reanalyze xtalk. this can make other victims more critical. crosstalk-induced delay.logic. . to be able to step back 177. Also backup cell.astPostRT should be used after axgAdvRouteOpt to do final tuning of the design. Ensure coupling information is created by eithe r of the methods if you want to base optimizations using crosstalk-induced delays. 173.. 172. If using Fast extraction. 175. 181. Typically the Slow extraction is more accurate than the InRoute extraction done during axgAdvRouteOpt (which is roughly 5% pessimistic). the route options should be changed.HPO: High Performance Option 179. there should be no need to re-run this step. and R/C reduction to fix crosstalk without buffer insertion.power .Timing > Generate Parasitic View: Notes: a) MinMax should be used for concurrent setup/hold analysis/ optimization. need to re-read. 178. Therefore.Virtual C) is chosen on the astPostRT form. Note that In-Route extraction is approximately 5% pessimistic to normal Astro postroute extraction.combining timing. You should adjust the setup effort setting on the axgAdvRouteOpt form if you only want to fix crosstalk and only preserve timing during axgAdvRouteOpt.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing.. 176.. therefore.

When you save a cell. linear model is less accurate/// 187.When you open a cell in write mode. graphical specifications. It is recommended that any of these functions be added to the nominal.extension.Note: Examples of some supplemental CLF commands: definePad. Two mode: TLU and Linear model. 183. The most recent version if you do not include a version number. 192. . This way there is no doubt of what cells are logically equivalent. 184.Toggle and Radio selections are options selected by form buttons for specific option categories. gate size and diode protection). This creates the concept of Library LEQ and Design LEQ.The Synopsys applications make the following assumptions: The layout cell if you do not include an extension. the Synopsys application locks the cell from write access by other users by creating a lock file (<cellFileName>:<versionNumber>_lock).designName.Add supplemental CLF data into nominal CLF file antenna information (for example. but you do not want the tool interchanging them for each other. 196. 189. The advan tages of this system is that it allows the library provider or CAD group to explicitly set LEQ information in reference libraries but still allows the user to override this information without modifying reference libraries. and design rules. such as units of measure. For example. 190. or typical.A CLF file provides a Synopsys application with library -specific information. allowing write access to other users. defineGateSize. delay cells.versionNumber 191.Astro can utilize LEQ information prepared in the reference libraries or it can build that information when running on the design cell. 195. the Synopsys application removes the lock file. 193. signal buffers.A technology file defines the characteristics of a cell library. 194. A Radio is used to select only one allowable option of an option category.TLU model: Table Look-Up 185.Synopsys recommends that LEQ information be added as part of library preparation.The translate linear model button is used to create simple TLU models from linear models during the load.cell library format (CLF) file. When you close the cell.STAMP and ALF format translations 188.182. 186. the Synopsys application saves the previously saved version as a backup copy. 197. CLF file. A toggle is used to select one or more options of an option category. layer and device definitions. and clock buffers may all be similar logically. defineDiodeProtection.

200. placing.Top Design Format (TDF) Files: For each top-level design in your libraries. the via regions (areas where vias can be placed during routing).198. Pin/blockage cells represent the pins and blockage areas (areas where no routing on a particular layer can occur). . and the pin solutions (solutions for routing to pins). notch fill & gap fill 201. Expanded netlist cells represent the logical connectivity of a design at enough levels of hierarchy to provide information necessary for binding with the physical layout. Netlist cells represent the logical connectivity of a design at the top level of hierarchy. your Synopsys directory should contain one or more TDF files. and routing the design. Layout cells represent the physical layout of a design. These files provide your Synopsys application with special instructions for planning. For 199.

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