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Q1. What is the effect of temperature on intrinsic carrier concentration? Ans.

As the temperature is increased, the number of broken bonds (carriers) increases because there is more thermal energy available so more and more electrons gain enough energy to break free. Each electron that makes it to the conduction band leaves behind a hole in the valence band and there is an increase in both the electron and hole concentration. As the temperature is decreased, electrons do not receive enough energy to break a bond and remain in the valence band. If electrons are in the conduction band they will quickly lose energy and fall back to the valence band, annihilating a hole. Therefore, lowering the temperature causes a decrease in the intrinsic carrier concentration, while raising the temperature causes an increase in intrinsic carrier concentration. Q2. What is the difference between synchronous and asynchronous reset? Ans. Disadvantages of synchronous reset: Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal. Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets. Asynchronous reset: The biggest problem with asynchronous resets is the reset release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. Disadvantages of asynchronous reset: ensure that the release of the reset can occur within one clock period. if the release of the reset occurred on or near a clock edge such that the flip-flops went metastable. Q3.What are the various sources of noise in bipolar transistor? Ans. Q4.Explain why the turn-on transistor of a BJT is faster when the device is driven into oversaturation Ans. Q5.What is the limitations of MOSFET? How does single electron theory overcome this limitation? Ans.

This pressure is typically in the range of 0. Instead. . It can only be used to produce flat surfaces. the presence of contact between the mask and the resist somewhat diminishes the uniformity of attainable resolution across the wafer. It also involves no contact between the mask and the wafer. To alleviate this problem. Contact printing is capable of attaining resolutions of less than 1 micron. masks used in contact printing must be thin and flexible to allow better contact over the whole wafer. The capability of a lens to collect diffracted light and project this onto the wafer is measured by its numerical aperture (NA). and traversal across the gap between the mask and the wafer.3 atmospheres. it involves no contact between the mask and the wafer. Projection printing is the third technique used in optical lithography. The resolution achieved by proximity printing is not as good as that of contact printing. Light with a wavelength of about 400 nm is used in contact printing. the mask is usually only 20-50 microns away from the wafer. which defines the minimum distance between two images for them to be resolvable. Projection printing is the technique employed by most modern optical lithography equipment. such that Fresnel diffraction is no longer involved. photolithography is used due to its ability to perform more precise incisions. or near-field diffraction. The NA values of lenses used in projection printers typically range from 0. As its name implies. since it results from a small gap between the mask and the wafer.40. Rather than directly cutting into an integrated circuit. which collects diffracted light from the mask and projects it onto the wafer. this technique employs a large gap between the mask and the wafer. Thus. Projection printers use a well-designed objective lens between the mask and the wafer. During proximity printing. Contact printing refers to the light exposure process wherein the photomask is pressed against the resist-covered wafer with a certain degree of pressure.Q6. In fact. The resolution achieved by projection printers depends on the wavelength and coherence of the incident light and the NA of the lens. for any given value of NA. Photolithography is a highly complex technique and requires both an extremely clean substrate surface and ideal temperature conditions. However. The resolution achievable by a lens is governed by Rayleigh's criterion. which is why masks used with this technique have longer useful lives than those used in contact printing. What is photolithography? Explain any two photolithography techniques. Ans. Photolithography is the process of making integrated circuits through optical erosion. Proximity printing is another optical lithography technique. This type of diffraction is known as Fresnel diffraction.16 to 0. there exists a minimum resolvable dimension. This is due to the diffraction of light caused by its passing through slits that make up the pattern in the mask. Proximity printing resolution may be improved by diminishing the gap between the mask and the wafer and by using light of shorter wavelengths. which is also known as Fraunhofer diffraction.05-0. far-field diffraction is in effect under this technique.

It must be emphasized. In the following. What is the failure rate in metal interconnects? How can be it reduced? Ans. Lambda-based layout design rules were originally devised to simplify the industrystandard micron-based design rules and to allow scaling capability for various processes. List topological design rules (lambda based). Q8. Ans.14). that most of the submicron CMOS process design rules do not lend themselves to straightforward linear scaling. we present a sample set of the lambda-based layout design rules devised for the MOSIS CMOS process and illustrate the implications of these rules on a section a simple layout which includes two transistors (Fig.Q7. however. The use of lambda-based design rules must therefore be handled with caution in sub-micron geometries. 2. MOSIS Layout Design Rules (sample set) Rule number Description Rule Active area rules R1 Minimum active area width R2 Minimum active area spacing Polysilicon rules R3 R4 R5 R6 area) R7 Metal rules R8 R9 Contact rules R10 R11 R12 R13 R14 R15 Minimum poly width Minimum poly spacing Minimum gate extension of poly over active Minimum poly-active edge spacing Minimum poly-active edge spacing L3 L 3 L 2 L 2 L 2 L 1 L (poly outside active 3 L (poly inside active area) 3 L 3 L 2 2 1 1 3 2 L L L L L L Minimum metal width Minimum metal spacing Poly contact size Minimum poly contact spacing Minimum poly contact to poly edge spacing Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size .

Describe physical design cycle for ASIC? Ans. .R16 region) R17 R18 R19 R20 regions) Minimum active contact spacing Minimum active contact to active edge spacing Minimum active contact to metal edge spacing Minimum active contact to poly edge spacing Minimum active contact spacing 2 L (on the same active 1L 1L 3 L 6 L (on different active Q9.


During a latchup when one of the transistors is conducting. These can range from using pre-packaged ICs on a small printed circuit board (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a High Density Interconnection (HDI) substrate. MCM-C . circuits or layout specifically for one ASIC.which usually means until a power-down. 2) In a full custom ASIC. triggering a parasitic structure which disrupts proper functioning of the part. Latchup is a term used in the realm of integrated circuits (ICs) to describe a particular type of short circuit which can occur in an improperly designed circuit. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates. Q11. Multi-Chip Modules come in a variety of forms depending on the complexity and development philosophies of their designers. semiconductor dies or other discrete components are packaged onto a unifying substrate.What is latchup problem in cmos circuits? How do you overcome this Ans. The substrate is a multi-layer laminated PCB . Multi-Chip Module packaging is an important facet of modern electronic miniaturization and micro-electronic systems. A power cycle is required to correct this situation. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. The parasitic structure is usually equivalent to a thyristor (or SCR). an engineer designs some or all of the logic cells.laminated MCM. possibly even leading to its destruction due to overcurrent.Q10. thus illustrating its integrated nature. MCM-D . The MCM itself will often be referred to as a "chip" in designs. MCMs are classified according to the technology used to create the HDI (High Density Interconnection) substrate.Write a note on 1) MCM technology 2) Full custom based approaches Ans. a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. 1) A multi-chip module (MCM) is a specialized electronic package where multiple integrated circuits (ICs). More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit. the other one begins conducting too. • • • MCM-L .deposited MCM. facilitating their use as a single component (as though a larger IC). such as LTCC. The modules are deposited on the base substrate using thin film technology. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it . .ceramic substrate MCMs.

a. This breaks the parasitic SCR structure between these transistors. C_in). is a common cause of latchup. C_out. the LPT circuit shuts down the chip and holds it powereddown for a preset time. module Addfull_zero_delay (sum. output C_out. exceeding the rail voltage by more than a diode drop. Another possibility for a latchup prevention is the Latchup Protection Technology circuit. w2). where a layer of insulating oxide (called a trench) surrounds both the NMOS and the PMOS transistors. b. Q12. A spike of positive or negative voltage on an input or output pin of a digital chip. w2. in hot swap devices). wire w1. leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage. Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latchup. This frequently happens in circuits which use multiple supply voltages that do not come up in the proper order after a power-up. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed (e.The latchup does not have to happen between the power rails. b. Another cause is the supply voltage exceeding the absolute maximum rating. end module . input a. often from a transient spike in the power supply. Most silicon-on-insulator devices are inherently latchup-resistant. w1). it can happen at any place where the required parasitic structure exists. leading to a breakdown of some internal junction. C_in.g. halfadd_no_delay M1 (w1. When a latchup is detected. Prevention It is possible to design chips that are latchup-resistant. C_out. b). w2. halfadd_no_delay M2 (sum.Write a code for full adder in verilog Ans. or (C_out. sum. C_in. a. w3. w2. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine. Latchup is the low resistance connection between tub and power supply rails..

this trend took a turn when MOS technology caught up and there was a crossover between bipolar and MOS shares. it took 30 years before this idea was applied to functioning devices to be used in practical applications [3].1 A comparison of CMOS. and is one of the earliest versions to be used in practice. and the relation between MOS and bipolar sales was two to one. Ina. Ina. sum. In 1983. xor (sum. Around 1980.How BiCMOS technology is useful for low power devices? introduction The history of semiconductor devices began in the 1930s. and simple design. Inb). The principal BiCMOS circuit in the early days was the BiCMOS totem-pole gate [7] as shown in Figure 1. Complementary-MOS (CMOS) was finding more widespread use due to its low power dissipation. a bipolar-compatible process based on CMOS technology was developed. Since 1985. Inb). However.1.2. This circuit was proposed by Lin et al. and.2] first proposed the Metal Oxide Semiconductor (MOS) Field-Effect Transistor (FET). The state-of-the-art . bipolar devices were the mainstream digital technology. BiCMOS technologies developed beyond initial experimentation to become widespread production processes. such that. high packing density. output Cout. Inb. The existence of this gap. implies that neither CMOS nor bipolar had the flexibility required to cover the full delay-power space. In digital circuit applications. CMOS covered more than 90% of the total MOS sales. endmodule Q15.// Moudule for half adder. Inb) input Ina. as shown in Figure 1. up to the late 1970s. module halfadd_no_delay (Cout. and BiCMOS technology with both the MOS and bipolar devices fabricated on the same chip was developed and studied [4–6]. the objective of which is to combine bipolar and CMOS so as to exploit the advantages of both at the circuit and system levels. It is commonly referred to as the conventional BiCMOS circuit. and BiCMOS technologies in terms of speed and power. when Lilienfeld and Heil [1. 1. Ina. by 1990. This flexibility was achieved with the emergence of bipolar-compatible CMOS (BiCMOS) technology. there was a performance gap between CMOS and bipolar logic. Fig. sum. and (Cout. bipolar.

in the near future. support features. such as lap-top and palm-top computers.2 Conventional BiCMOS inverter [43] (Reprinted by permission of Pearson Education. its portability is often a key differentiator in a user's purchase decision. Although designers have different reasons for lowering power consumption. we anticipate that. At that time. almost half of the consumer electronics market will be in portable systems. However. minimizing the overall power dissipation in a system has become a high priority. especially when the BiCMOS process has been enhanced and integrated into the CMOS process without any additional steps [12]. such as pagers and cellular phones. and anywhere" era becomes a reality. to larger and more sophisticated products that support multimedia applications. the main design focuses were providing for high-speed operation and a design with minimum area.1 Low-Power Design: An Overview In the past. Fig. have enjoyed considerable success among consumers. pocket calculators. the convenience of using a portable system relies heavily on its . and highly functional VeryLarge-Scale-Integration (VLSI) circuits [8–11]. pacemakers. Today. BiCMOS has become one of the dominant technologies used for high-speed. however. The considerations for portability are due to numerous factors. ranging from small hand-held personal communication devices. Inc.bipolar and CMOS structures have been converging. As the "on the move with anyone. 1. these steps can be shared for both of them. depending on the target application. Because the process steps required for both CMOS and bipolar are similar. First. as power is the most important single design constraint. portability becomes an essential feature of the electronic systems interfacing with nonelectronic systems. low-power design is becoming the norm for all high-performance applications. due to a high degree of process complexity and the exorbitant costs involved. anytime. emphasizing efficient use of energy as a major design objective. Even though the performance. design tools were all geared toward achieving these two goals. and cost of a portable product are important to the consumers. the semiconductor industry has witnessed an explosive growth in the demand and supply of portable systems in the consumer electronics market. such as wrist watches. 1. the size and weight of the battery pack is fundamental. and some integrated sensors. The concern for power consumption has been part of the design process since the early 1970s. Since the early 1990s. Indeed. One of the most important reasons for this trend is the advent of portable systems. low-power circuit design and applications involving CMOS and BiCMOS technologies were used only in applications where very low power dissipation was absolutely essential. High-performance portable products. low-power.). Second. A portable system that has an unreasonably heavy battery pack is not practical and restricts the amount of battery power that can be loaded at any one time.

such as the rechargeable lithium or polymers. a 20-pound battery pack is required to stretch the recharge interval to 10 hours. high-quality audio. For example.recharging interval. or the lack of it in portable systems. Because the performance of a system is usually improved at the expense of silicon area. Finally. The issue of power also embraces reliability and the cost of manufacturing nonportable high-end applications. its throughput. future portable products will have either unreasonably heavy battery packs or a very short battery life. The area required to implement a circuit is also important as it is directly related to the fabrication cost of the chip. its capacity has only managed to increase by a factor of two to four in the last 30 years or so. and avoid expensive packaging and cooling techniques. bi-directional motion video. The power of such a terminal— when implemented using off-the-shelf components not designed for low power—is projected to reach approximately 40 W. Hence. consider a future portable multimedia terminal that supports highbandwidth wireless communication. this . low-power design is in line with the increasing global awareness of environmental concerns. The performance of a digital system is usually measured only in terms of the number of instructions it can carry out in a given amount of time. The rapidly increasing packing density. As a result. Based on the current Nickel-Cadmium (NiCd) battery technology. To maintain the reliability of their products. Now. and full texts/graphics. Both effects translate to higher cost. manufacturers are now under strong pressure to control. and computational power of microprocessors have inevitably resulted in rising power dissipation. that is. the DEC21164. Only a few years ago. which has a die area of 3 cm2 and runs on a 300-MHz clock frequency. with the rising importance of power. dissipates as much as 50 W of power. Larger die areas lead to more expensive packaging and lower fabrication yield. Although the battery technology has improved over the years. Such high power consumption requires expensive packaging and cooling techniques given that insufficient cooling leads to high operating temperatures. power has emerged as one of the most important design and performance parameters for integrated circuits. A system that requires frequent recharging is inconvenient and hence limits the user's overall satisfaction in using the product. the power dissipation of a circuit was of secondary importance to such design issues as performance and area. which tend to exacerbate several silicon failure mechanisms. the power dissipation of their products. a major task for integrated chip (IC) designers in the past was to achieve an optimal balance between these two often-conflicting objectives. To illustrate the importance of low-power design. and pen-based input. battery capacity is not expected to improve by more than 30 to 40% over the next 5 years. clock frequency. Even with new battery technologies. due to the increasing percentage of electrical energy usage for computing and communication in the modern workplace. if not reduce. The trends relating to the power consumption of microprocessors indicate that power has increased almost linearly with area-frequency product over the years. speech. which offers a capacity of 20 W-hour/pound. the computational power of digital integrated circuits has increased by more than four orders of magnitude. in the absence of low-power design techniques.

device miniaturization together with the search for even lower power and lower voltage requirements will continue. To cater to such an ever-increasing demand. Clearly. IC designers must design circuits with low-power dissipation without severely compromising the circuits' performance. reliability. and environmental concerns. The BiCMOS technology that combines the low-power dissipation and high packing density of CMOS with the high-speed and high-output drive of bipolar devices has proven to be an excellent workhorse for portable as well as nonportable applications. . Today. the CMOS/BiCMOS technology shall be the answer.balance is no longer sufficient. cost. For many years to come. power has become a major consideration in VLSI and giga-scale-integration (GSI) engineering due to portability.

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