Section 1 8051 Microcontroller Instruction Set

For interrupt response time information, refer to the hardware description chapter.

Instructions that Affect Flag Settings(1)
Instruction C ADD ADDC SUBB MUL DIV DA RRC RLC SETB C Note: X X X O O X X X 1 Flag OV X X X X X AC X X X CLR C CPL C ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit CJNE Instruction C O X X X X X X X Flag OV AC

1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.

The Instruction Set and Addressing Modes
Rn direct @R i #data #data 16 addr 16 addr 11 rel bit Register R7-R0 of the currently selected Register Bank. 8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)]. 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0. 8-bit constant included in instruction. 16-bit constant included in instruction. 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address space. 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction. Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Direct Addressed bit in Internal Data RAM or Special Function Register.

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Table 1-1. Instruction Set Summary
0 0 NOP 1 JBC bit,rel [3B, 2C] ACALL (P0) [2B, 2C] LCALL addr16 [3B, 2C] RRC A DEC A DEC dir [2B] DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 2 JB bit, rel [3B, 2C] AJMP (P1) [2B, 2C] RET [2C] RL A ADD A, #data [2B] ADD A, dir [2B] ADD A, @R0 ADD A, @R1 ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 3 JNB bit, rel [3B, 2C] ACALL (P1) [2B, 2C] RETI [2C] RLC A ADDC A, #data [2B] ADDC A, dir [2B] ADDC A, @R0 ADDC A, @R1 ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 4 JC rel [2B, 2C] AJMP (P2) [2B, 2C] ORL dir, A [2B] ORL dir, #data [3B, 2C] ORL A, #data [2B] ORL A, dir [2B] ORL A, @R0 ORL A, @R1 ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 5 JNC rel [2B, 2C] ACALL (P2) [2B, 2C] ANL dir, A [2B] ANL dir, #data [3B, 2C] ANL A, #data [2B] ANL A, dir [2B] ANL A, @R0 ANL A, @R1 ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7 6 JZ rel [2B, 2C] AJMP (P3) [2B, 2C] XRL dir, a [2B] XRL dir, #data [3B, 2C] XRL A, #data [2B] XRL A, dir [2B] XRL A, @R0 XRL A, @R1 XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7 7 JNZ rel [2B, 2C] ACALL (P3) [2B, 2C] ORL C, bit [2B, 2C] JMP @A + DPTR [2C] MOV A, #data [2B] MOV dir, #data [3B, 2C] MOV @R0, @data [2B] MOV @R1, #data [2B] MOV R0, #data [2B] MOV R1, #data [2B] MOV R2, #data [2B] MOV R3, #data [2B] MOV R4, #data [2B] MOV R5, #data [2B] MOV R6, #data [2B] MOV R7, #data [2B]

1

AJMP (P0) [2B, 2C] LJMP addr16 [3B, 2C] RR A INC A INC dir [2B] INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Note:

Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle

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Table 1-2. Instruction Set Summary (Continued)
8 0 SJMP REL [2B, 2C] AJMP (P4) [2B, 2C] ANL C, bit [2B, 2C] MOVC A, @A + PC [2C] DIV AB [2B, 4C] MOV dir, dir [3B, 2C] MOV dir, @R0 [2B, 2C] MOV dir, @R1 [2B, 2C] MOV dir, R0 [2B, 2C] MOV dir, R1 [2B, 2C] MOV dir, R2 [2B, 2C] MOV dir, R3 [2B, 2C] MOV dir, R4 [2B, 2C] MOV dir, R5 [2B, 2C] MOV dir, R6 [2B, 2C] MOV dir, R7 [2B, 2C] 9 MOV DPTR,# data 16 [3B, 2C] ACALL (P4) [2B, 2C] MOV bit, C [2B, 2C] MOVC A, @A + DPTR [2C] SUBB A, #data [2B] SUBB A, dir [2B] SUBB A, @R0 SUBB A, @R1 SUBB A, R0 SUBB A, R1 SUBB A, R2 SUBB A, R3 SUBB A, R4 SUBB A, R5 SUBB A, R6 SUBB A, R7 MOV @R0, dir [2B, 2C] MOV @R1, dir [2B, 2C] MOV R0, dir [2B, 2C] MOV R1, dir [2B, 2C] MOV R2, dir [2B, 2C] MOV R3, dir [2B, 2C] MOV R4, dir [2B, 2C] MOV R5, dir [2B, 2C] MOV R6, dir [2B, 2C] MOV R7, dir [2B, 2C] A ORL C, /bit [2B, 2C] AJMP (P5) [2B, 2C] MOV C, bit [2B] INC DPTR [2C] MUL AB [4C] B ANL C, /bit [2B, 2C] ACALL (P5) [2B, 2C] CPL bit [2B] CPL C CJNE A, #data, rel [3B, 2C] CJNE A, dir, rel [3B, 2C] CJNE @R0, #data, rel [3B, 2C] CJNE @R1, #data, rel [3B, 2C] CJNE R0, #data, rel [3B, 2C] CJNE R1, #data, rel [3B, 2C] CJNE R2, #data, rel [3B, 2C] CJNE R3, #data, rel [3B, 2C] CJNE R4, #data, rel [3B, 2C] CJNE R5, #data, rel [3B, 2C] CJNE R6, #data, rel [3B, 2C] CJNE R7, #data, rel [3B, 2C] C PUSH dir [2B, 2C] AJMP (P6) [2B, 2C] CLR bit [2B] CLR C SWAP A XCH A, dir [2B] XCH A, @R0 XCH A, @R1 XCH A, R0 XCH A, R1 XCH A, R2 XCH A, R3 XCH A, R4 XCH A, R5 XCH A, R6 XCH A, R7 D POP dir [2B, 2C] ACALL (P6) [2B, 2C] SETB bit [2B] SETB C DA A DJNZ dir, rel [3B, 2C] XCHD A, @R0 XCHD A, @R1 DJNZ R0, rel [2B, 2C] DJNZ R1, rel [2B, 2C] DJNZ R2, rel [2B, 2C] DJNZ R3, rel [2B, 2C] DJNZ R4, rel [2B, 2C] DJNZ R5, rel [2B, 2C] DJNZ R6, rel [2B, 2C] DJNZ R7, rel [2B, 2C] E MOVX A, @DPTR [2C] AJMP (P7) [2B, 2C] MOVX A, @R0 [2C] MOVX A, @RI [2C] CLR A MOV A, dir [2B] MOV A, @R0 MOV A, @R1 MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 F MOVX @DPTR, A [2C] ACALL (P7) [2B, 2C] MOVX wR0, A [2C] MOVX @RI, A [2C] CPL A MOV dir, A [2B] MOV @R0, A MOV @R1, A MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6. A MOV R7, A

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Note:

Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle

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8051 Microcontroller Instruction Set

Table 1-3. AT89 Instruction Set Summary(1)
Mnemonic Description Byte Oscillator Period Mnemonic Description Byte Oscillator Period

ARITHMETIC OPERATIONS ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry Add direct byte to Accumulator with Carry Add indirect RAM to Accumulator with Carry Add immediate data to Acc with Carry Subtract Register from Acc with borrow Subtract direct byte from Acc with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from Acc with borrow Increment Accumulator Increment register Increment direct byte Increment direct RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A & B Divide A by B Decimal Adjust Accumulator 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

LOGICAL OPERATIONS ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL 12 24 48 48 12 XRL CLR CPL RL RLC direct,#data A A A A A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12

3 1 1 1 1

24 12 12 12 12

Note:

1. All mnemonics copyrighted © Intel Corp., 1980.

LOGICAL OPERATIONS (continued)

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8051 Microcontroller Instruction Set
Mnemonic RR RRC A A Description Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumulator Byte 1 1 1 Oscillator Period 12 12 12 Mnemonic MOVX @Ri,A MOVX @DPTR,A PUSH POP Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 12 XCH 12 XCH 12 XCH 12 XCHD 12 24 12 12 24 24 24 24 12 MOV MOV MOV MOV @Ri,direct @Ri,#data 24 MOV 12 24 24 24 24 JC JNC JB JNB JBC bit,C rel rel bit,rel bit,rel bit,rel Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct Bit is set Jump if direct Bit is Not set Jump if direct Bit is set & clear bit 2 2 2 3 3 3 24 24 24 24 24 24 C,bit A,@Ri A,@Ri A,direct A,Rn direct direct Description Move Acc to External RAM (8-bit addr) Move Acc to External RAM (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order Digit indirect RAM with Acc Byte 1 1 2 2 1 2 1 1 Oscillator Period 24 24 24 24 12 12 12 12

SWAP A DATA TRANSFER MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A,Rn A,direct A,@Ri A,#data Rn,A Rn,direct Rn,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A

BOOLEAN VARIABLE MANIPULATION CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL C bit C bit C bit C,bit C,/bit C,bit C,/bit Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to CARRY AND complement of direct bit to Carry OR direct bit to Carry OR complement of direct bit to Carry Move direct bit to Carry 1 2 1 2 1 2 2 2 2 2 2 12 12 12 12 12 12 24 24 24 24 12

DPTR,#data16 Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Move External RAM (8bit addr) to Acc

MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri

PROGRAM BRANCHING ACAL L addr11 Absolute Subroutine Call Long Subroutine Call Return from Subroutine 2 3 1 24 24 24

DATA TRANSFER (continued) MOVX A,@DPTR Move Exernal RAM (16bit addr) to Acc 1 24

LCALL addr16 RET

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Atmel 8051 Microcontrollers Hardware Manual

8051 Microcontroller Instruction Set

Mnemonic RETI AJMP LJMP SJMP JMP JZ JNZ CJNE addr11 addr16 rel @A+DPTR rel rel A,direct,rel

Description Return from interrupt Absolute Jump Long Jump Short Jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is Zero Jump if Accumulator is Not Zero Compare direct byte to Acc and Jump if Not Equal Compare immediate to Acc and Jump if Not Equal Compare immediate to register and Jump if Not Equal Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation

Byte 1 2 3 2 1 2 2 3

Oscillator Period 24 24 24 24 24 24 24 24

CJNE

A,#data,rel

3

24

CJNE

Rn,#data,rel

3

24

CJNE

@Ri,#data,rel

3

24

DJNZ DJNZ NOP

Rn,rel direct,rel

2 3 1

24 24 12

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8051 Microcontroller Instruction Set

Table 1-4. Instruction Opcodes in Hexadecimal Order
Hex Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 Number of Bytes 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 Mnemonic NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC JB AJMP RET RL ADD ADD A A,#data A,data addr code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr,code addr code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr,code addr code addr Operands Hex Code 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A Number of Bytes 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL A A,#data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 code addr code addr data addr,A data addr,#data A,#data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 Operands A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 bit addr,code addr code addr

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Atmel 8051 Microcontrollers Hardware Manual

8051 Microcontroller Instruction Set

Hex Code 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70

Number of Bytes 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2

Mnemonic ORL ORL ORL ORL ORL JNC ACALL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL JNZ

Operands A,R3 A,R4 A,R5 A,R6 A,R7 code addr code addr data addr,A data addr,#data A,#data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 code addr code addr data addr,A data addr,#data A,#data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 code addr

Hex Code 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96

Number of Bytes 2 2 1 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 3 2 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1

Mnemonic ACALL ORL JMP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV SJMP AJMP ANL MOVC DIV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ACALL MOV MOVC SUBB SUBB SUBB

Operands code addr C,bit addr @A+DPTR A,#data data addr,#data @R0,#data @R1,#data R0,#data R1,#data R2,#data R3,#data R4,#data R5,#data R6,#data R7,#data code addr code addr C,bit addr A,@A+PC AB data addr,data addr data addr,@R0 data addr,@R1 data addr,R0 data addr,R1 data addr,R2 data addr,R3 data addr,R4 data addr,R5 data addr,R6 data addr,R7 DPTR,#data code addr bit addr,C A,@A+DPTR A,#data A,data addr A,@R0

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8051 Microcontroller Instruction Set
Hex Code 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 3 3 3 3 3 3 3 3 Number of Bytes 1 1 1 1 1 1 1 1 1 2 2 2 1 1 Mnemonic SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB ORL AJMP MOV INC MUL reserved MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE @R0,data addr @R1,data addr R0,data addr R1,data addr R2,data addr R3,data addr R4,data addr R5,data addr R6,data addr R7,data addr C,/bit addr code addr bit addr C A,#data,code addr A,data addr,code addr @R0,#data,code addr @R1,#data,code addr R0,#data,code addr R1,#data,code addr R2,#data,code addr R3,#data,code addr R4,#data,code addr Operands A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 C,/bit addr code addr C,bit addr DPTR AB Hex Code BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 Number of Bytes 3 3 3 2 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 3 1 1 2 2 2 2 2 2 2 2 1 2 1 Mnemonic CJNE CJNE CJNE PUSH AJMP CLR CLR SWAP XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH POP ACALL SETB SETB DA DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ MOVX AJMP MOVX Operands R5,#data,code addr R6,#data,code addr R7,#data,code addr data addr code addr bit addr C A A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 data addr code addr bit addr C A data addr,code addr A,@R0 A,@R1 R0,code addr R1,code addr R2,code addr R3,code addr R4,code addr R5,code addr R6,code addr R7,code addr A,@DPTR code addr A,@R0

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8051 Microcontroller Instruction Set

Hex Code E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

Number of Bytes 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1

Mnemonic MOVX CLR MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVX ACALL MOVX MOVX CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV

Operands A,@R1 A A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 @DPTR,A code addr @R0,A @R1,A A data addr,A @R0,A @R1,A R0,A R1,A R2,A R3,A R4,A R5,A R6,A R7,A

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1.1

Instruction Definitions

ACALL addr11
Function: Absolute Call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected. Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following instruction, ACALL SUBRTN

at location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC contains 0345H. Bytes: 2 Cycles: 2 Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ← (PC7-0) (SP) ← (SP) + 1 ((SP)) ← (PC15-8) (PC10-0) ← page address

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ADD

A,<src-byte>
Function: Add Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH (10101010B). The following instruction, ADD A,R0

leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1.

ADD A,Rn
Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 1 r r r

Operation: ADD (A) ← (A) + (R n)

ADD A,direct
Bytes: 2 Cycles: 1 Encoding: 0 0 1 0 0 1 0 1 direct address

Operation: ADD (A) ← (A) + (direct)

ADD A,@Ri
Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 1 1 i

Operation: ADD (A) ← (A) + ((Ri))

ADD A,#data
Bytes: 2 Cycles: 1 Encoding: 0 0 1 0 0 1 0 0 immediate data

Operation: ADD (A) ← (A) + #data

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ADDC A, <src-byte>
Function: Add with Carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The following instruction, ADDC A,R0

leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.

ADDC A,R n
Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 1 r r r

Operation: ADDC (A) ← (A) + (C) + (Rn)

ADDC A,direct
Bytes: 2 Cycles: 1 Encoding: 0 0 1 1 0 1 0 1 direct address

Operation: ADDC (A) ← (A) + (C) + (direct)

ADDC A,@R i
Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 1 1 i

Operation: ADDC (A) ← (A) + (C) + ((R i))

ADDC A,#data
Bytes: 2 Cycles: 1 Encoding: 0 0 1 1 0 1 0 0 immediate data

Operation: ADDC (A) ← (A) + (C) + #data

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AJMP addr11
Function: Absolute Jump Description: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP. Example: The label JMPADR is at program memory location 0123H. The following instruction, AJMP JMPADR

is at location 0345H and loads the PC with 0123H. Bytes: 2 Cycles: 2 Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

Operation: AJMP (PC) ← (PC) + 2 (PC10-0) ← page address

ANL

<dest-byte>,<src-byte>
Function: Logical-AND for byte variables Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following instruction, ANL A,R0

leaves 41H (01000001B) in the Accumulator. When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The following instruction, ANL P1,#01110011B

clears bits 7, 3, and 2 of output port 1.

ANL

A,R n
Bytes: 1 Cycles: 1 Encoding: 0 1 0 1 1 r r r

Operation: ANL (A) ← (A)

∧ (Rn)

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ANL

A,direct
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 1 0 1 direct address

Operation: ANL (A) ← (A)

∧ (direct)

ANL

A,@R i
Bytes: 1 Cycles: 1 Encoding: 0 1 0 1 0 1 1 i

Operation: ANL (A) ← (A)

∧ ((Ri))

ANL

A,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 1 0 0 immediate data

Operation: ANL (A) ← (A)

∧ #data

ANL

direct,A
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 0 1 0 direct address

Operation: ANL (direct) ← (direct)

∧ (A)

ANL

direct,#data
Bytes: 3 Cycles: 2 Encoding: 0 1 0 1 0 0 1 1 direct address immediate data

Operation: ANL (direct) ← (direct)

∧ #data

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ANL

C,<src-bit>
Function: Logical-AND for bit variables Description: If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0: MOV ANL ANL C,P1.0 C,ACC.7 C,/OV ;LOAD CARRY WITH INPUT PIN STATE ;AND CARRY WITH ACCUM. BIT 7 ;AND WITH INVERSE OF OVERFLOW FLAG

ANL

C,bit
Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 1 0 bit address

Operation: ANL (C) ← (C)

∧ (bit)

ANL

C,/bit
Bytes: 2 Cycles: 2 Encoding: 1 0 1 1 (bit) 0 0 0 0 bit address

Operation: ANL (C) ← (C)

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CJNE

<dest-byte>,<src-byte>, rel
Function: Compare and Jump if Not Equal. Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant. Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence, CJNE ; NOT_EQ: ; ... JC ... R7, # 60H, NOT_EQ ..... REQ_LOW ..... ;R7 = 60H. ;IF R7 < 60H. ;R7 > 60H.

sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to Port 1 is also 34H, then the following instruction, WAIT: CJNE A, P1,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data changes to 34H.)

CJNE A,direct,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 0 1 direct address rel. address

Operation: (PC) ← (PC) + 3 IF (A) < > (direct) THEN (PC) ← (PC) + relative offset IF (A) < (direct) THEN (C) ← 1 ELSE (C) ← 0

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CJNE A,#data,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address

Operation: (PC) ← (PC) + 3 IF (A) < > data THEN (PC) ← (PC) + relative offset IF (A) < data THEN (C) ← 1 ELSE (C) ← 0

CJNE R n,#data,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 1 r r r immediate data rel. address

Operation: (PC) ← (PC) + 3 IF (Rn) < > data THEN (PC) ← (PC) + relative offset IF (Rn) < data THEN (C) ← 1 ELSE (C) ← 0

CJNE @R i,data,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 1 i immediate data rel. address

Operation: (PC) ← (PC) + 3 IF ((Ri)) < > data THEN (PC) ← (PC) + relative offset IF ((Ri)) < data THEN (C) ← 1 ELSE (C) ← 0

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CLR

A
Function: Clear Accumulator Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected Example: The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H (00000000B). Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 0 0

Operation: CLR (A) ← 0

CLR

bit
Function: Clear bit Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5DH (01011101B). The following instruction,CLR P1.2 leaves the port set to 59H (01011001B).

CLR

C
Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 0 1 1

Operation: CLR (C) ← 0

CLR

bit
Bytes: 2 Cycles: 1 Encoding: 1 1 0 0 0 0 1 0 bit address

Operation: CLR (bit) ← 0

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CPL

A
Function: Complement Accumulator Description: CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected. Example: The Accumulator contains 5CH (01011100B). The following instruction, CPL A

leaves the Accumulator set to 0A3H (10100011B). Bytes: 1 Cycles: 1 Encoding: 1 1 (A) 1 1 0 1 0 0

Operation: CPL (A) ←

CPL

bit
Function: Complement bit Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin. Example: Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,CPL P1.1CPL P1.2 leaves the port set to 5BH (01011011B).

CPL

C
Bytes: 1 Cycles: 1 Encoding: 1 0 (C) 1 1 0 0 1 1

Operation: CPL (C) ←

CPL

bit
Bytes: 2 Cycles: 1 Encoding: 1 0 (bit) 1 1 0 0 1 0 bit address

Operation: CPL (bit) ←

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DA

A
Function: Decimal-adjust Accumulator for Addition Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DAA apply to decimal subtraction. Example: The Accumulator holds the value 56H (01010110B), representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B), representing the packed BCD digits of the decimal number 67. The carry flag is set. The following instruction sequence ADDC DA A,R3 A

first performs a standard two’s-complement binary addition, resulting in the value 0BEH (10111110) in the Accumulator. The carry and auxiliary carry flags are cleared. The Decimal Adjust instruction then alters the Accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of 56, 67, and 1 is 124. BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the following instruction sequence, ADD DA A, # 99H A

leaves the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the sum can be interpreted to mean 30 - 1 = 29. Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 1 0 0

Operation: DA -contents of Accumulator are BCD IF [[(A3-0 ) > 9] [(AC) = 1]] THEN (A3-0) ← (A3-0) + 6 AND IF [[(A7-4 ) > 9] [(C) = 1]] THEN (A7-4) ← (A7-4) + 6

∨ ∨

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DEC

byte
Function: Decrement Description: DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The following instruction sequence, DEC DEC DEC @R0 R0 @R0

leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.

DEC

A
Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 1 0 0

Operation: DEC (A) ← (A) - 1

DEC

Rn
Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 1 r r r

Operation: DEC (Rn) ← (Rn) - 1

DEC

direct
Bytes: 2 Cycles: 1 Encoding: 0 0 0 1 0 1 0 1 direct address

Operation: DEC (direct) ← (direct) - 1

DEC

@R i
Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 1 1 i

Operation: DEC ((Ri)) ← ((Ri)) - 1

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DIV

AB
Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case. Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The following instruction, DIV AB

leaves 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV are both cleared. Bytes: 1 Cycles: 4 Encoding: 1 0 0 0 0 1 0 0

Operation: DIV (A)15-8 ← (A)/(B) (B)7-0

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DJNZ

<byte>,<rel-addr>
Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence, DJNZ DJNZ DJNZ 40H,LABEL_1 50H,LABEL_2 60H,LABEL_3

causes a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence, MOV TOGGLE: CPL DJNZ R2, # 8 P1.7 R2,TOGGLE

toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin.

DJNZ R n,rel
Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 1 r r r rel. address

Operation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) - 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC) + rel

DJNZ direct,rel
Bytes: 3 Cycles: 2 Encoding: 1 1 0 1 0 1 0 1 direct address rel. address

Operation: DJNZ (PC) ← (PC) + 2 (direct) ← (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) ← (PC) + rel

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INC

<byte>
Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The following instruction sequence, INC INC INC @R0 R0 @R0

leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively.

INC

A
Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 0 0

Operation: INC (A) ← (A) + 1

INC

Rn
Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 1 r r r

Operation: INC (Rn) ← (Rn) + 1

INC

direct
Bytes: 2 Cycles: 1 Encoding: 0 0 0 0 0 1 0 1 direct address

Operation: INC (direct) ← (direct) + 1

INC

@R i
Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 1 i

Operation: INC ((Ri)) ← ((Ri)) + 1

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INC

DPTR
Function: Increment Data Pointer Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence, INC INC INC DPTR DPTR DPTR

changes DPH and DPL to 13H and 01H. Bytes: 1 Cycles: 2 Encoding: 1 0 1 0 0 0 1 1

Operation: INC (DPTR) ← (DPTR) + 1

JB

blt,rel
Function: Jump if Bit set Description: If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The following instruction sequence, JB JB P1.2,LABEL1 ACC. 2,LABEL2

causes program execution to branch to the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 0 0 0 0 0 bit address rel. address

Operation: JB (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + rel

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JBC

bit,rel
Function: Jump if Bit is set and Clear bit Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. Example: The Accumulator holds 56H (01010110B). The following instruction sequence, JBC JBC ACC.3,LABEL1 ACC.2,LABEL2

causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (01010010B). Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 0 0 bit address rel. address

Operation: JBC (PC) ← (PC) + 3 IF (bit) = 1 THEN (bit) ← 0 (PC) ← (PC) +rel

JC

rel
Function: Jump if Carry is set Description: If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. Example: The carry flag is cleared. The following instruction sequence, JC CPL JC LABEL1 C LABEL 2

sets the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 0 0 0 0 0 rel. address

Operation: JC (PC) ← (PC) + 2 IF (C) = 1 THEN (PC) ← (PC) + rel

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JMP

@A+DPTR
Function: Jump indirect Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected. Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL. MOV JMP JMP_TBL: AJMP AJMP AJMP AJMP DPTR, # JMP_TBL @A + DPTR LABEL0 LABEL1 LABEL2 LABEL3

If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 1 Cycles: 2 Encoding: 0 1 1 1 0 0 1 1

Operation: JMP (PC) ← (A) + (DPTR)

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JNB bit,rel
Function: Jump if Bit Not set Description: If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The following instruction sequence, JNB JNB P1.3,LABEL1 ACC.3,LABEL2

causes program execution to continue at the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 1 0 0 0 0 bit address rel. address

Operation: JNB (PC) ← (PC) + 3 IF (bit) = 0 THEN (PC) ← (PC) + rel

JNC

rel
Function: Jump if Carry not set Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set. The following instruction sequence, JNC CPL JNC LABEL1 C LABEL2

clears the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 1 0 0 0 0 rel. address

Operation: JNC (PC) ← (PC) + 2 IF (C) = 0 THEN (PC) ← (PC) + rel

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JNZ

rel
Function: Jump if Accumulator Not Zero Description: If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally holds 00H. The following instruction sequence, JNZ INC JNZ LABEL1 A LABEL2

sets the Accumulator to 01H and continues at label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 0 0 0 rel. address

Operation: JNZ (PC) ← (PC) + 2 IF (A) ≠ 0 THEN (PC) ← (PC) + rel

JZ

rel
Function: Jump if Accumulator Zero Description: If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally contains 01H. The following instruction sequence, JZ DEC JZ LABEL1 A LABEL2

changes the Accumulator to 00H and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 0 0 0 0 0 rel. address

Operation: JZ (PC) ← (PC) + 2 IF (A) = 0 THEN (PC) ← (PC) + rel

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LCALL addr16
Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memory address space. No flags are affected. Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. After executing the instruction, LCALL SUBRTN

at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0

Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC7-0) (SP) ← (SP) + 1 ((SP)) ← (PC15-8) (PC) ← addr 15-0

LJMP

addr16
Function: Long Jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. Example: The label JMPADR is assigned to the instruction at program memory location 1234H. The instruction, LJMP JMPADR

at location 0123H will load the program counter with 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0

Operation: LJMP (PC) ← addr 15-0

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MOV

<dest-byte>,<src-byte>
Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed. Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). MOV MOV MOV MOV MOV MOV R0,#30H A,@R0 R1,A B,@R1 @R1,P1 P2,P1 ;R0 < = 30H ;A < = 40H ;R1 < = 40H ;B < = 10H ;RAM (40H) < = 0CAH ;P2 #0CAH

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2.

MOV

A,R n
Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 1 r r r

Operation: MOV (A) ← (R n)

*MOV A,direct
Bytes: 2 Cycles: 1 Encoding: 1 1 1 0 0 1 0 1 direct address

Operation: MOV (A) ← (direct)

* MOV A,ACC is not a valid Instruction. MOV A,@R i
Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 1 i

Operation: MOV (A) ← ((R i))

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MOV

A,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 0 0 immediate data

Operation: MOV (A) ← #data

MOV

R n,A
Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 1 r r r

Operation: MOV (Rn) ← (A)

MOV

R n,direct
Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 1 r r r direct addr.

Operation: MOV (Rn) ← (direct)

MOV

R n,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 1 r r r immediate data

Operation: MOV (Rn) ← #data

MOV

direct,A
Bytes: 2 Cycles: 1 Encoding: 1 1 1 1 0 1 0 1 direct address

Operation: MOV (direct) ← (A)

MOV

direct,R n
Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 1 r r r direct address

Operation: MOV (direct) ← (Rn)

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0509C–8051–07/06

MOV

direct,direct
Bytes: 3 Cycles: 2 Encoding: 1 0 0 0 0 1 0 1 dir. addr. (dest) dir. addr. (scr)

Operation: MOV (direct) ← (direct)

MOV

direct,@R i
Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 1 1 i direct addr.

Operation: MOV (direct) ← ((Ri))

MOV

direct,#data
Bytes: 3 Cycles: 2 Encoding: 0 1 1 1 0 1 0 1 direct address immediate data

Operation: MOV (direct) ← #data

MOV

@R i,A
Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 0 1 1 i

Operation: MOV ((Ri)) ← (A)

MOV

@R i,direct
Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 1 1 i direct addr.

Operation: MOV ((Ri)) ← (direct)

MOV

@R i,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 1 i immediate data

Operation: MOV ((Ri)) ← #data

34
0509C–8051–07/06

MOV

<dest-bit>,<src-bit>
Function: Move bit data Description: MOV <dest-bit>,<src-bit> copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. Example: The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B). MOV MOV MOV P1.3,C C,P3.3 P1.2,C

leaves the carry cleared and changes Port 1 to 39H (00111001B).

MOV

C,bit
Bytes: 2 Cycles: 1 Encoding: 1 0 1 0 0 0 1 0 bit address

Operation: MOV (C) ← (bit)

MOV

bit,C
Bytes: 2 Cycles: 2 Encoding: 1 0 0 1 0 0 1 0 bit address

Operation: MOV (bit) ← (C)

MOV

DPTR,#data16
Function: Load Data Pointer with a 16-bit constant Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Example: The instruction, MOV DPTR, # 1234H

loads the value 1234H into the Data Pointer: DPH holds 12H, and DPL holds 34H. Bytes: 3 Cycles: 2 Encoding: 1 0 0 1 0 0 0 0 immed. data15-8 immed. data7-0

Operation: MOV (DPTR) ← #data15-0 DPH ← DPL ← #data15-8 ← #data7-0

35
0509C–8051–07/06

MOVC A,@A+ <base-reg>
Function: Move Code byte Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive. REL_PC: INC MOVC RET DB DB DB DB 66H 77H 88H 99H A A,@A+PC

If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. The INC A before the MOVC instruction is needed to “get around” the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead.

MOVC A,@A+DPTR
Bytes: 1 Cycles: 2 Encoding: 1 0 0 1 0 0 1 1

Operation: MOVC (A) ← ((A) + (DPTR))

MOVC A,@A+PC
Bytes: 1 Cycles: 2 Encoding: 1 0 0 0 0 0 1 1

Operation: MOVC (PC) ← (PC) + 1 (A) ← ((A) + (PC))

36
0509C–8051–07/06

MOVX <dest-byte>,<src-byte>
Function: Move External Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why “X” is appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using R0 or R1. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence, MOVX MOVX A,@R1 @R0,A

copies the value 56H into both the Accumulator and external RAM location 12H.

MOVX A,@Ri
Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 1 i

Operation: MOVX (A) ← ((R i))

MOVX A,@DPTR
Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 0 0

Operation: MOVX (A) ← ((DPTR))

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MOVX @R i,A
Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 1 i

Operation: MOVX ((Ri)) ← (A)

MOVX @DPTR,A
Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 0 0

Operation: MOVX (DPTR) ← (A)

MUL

AB
Function: Multiply Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction, MUL AB

will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared. Bytes: 1 Cycles: 4 Encoding: 1 0 1 0 0 1 0 0

Operation: MUL (A)7-0 ← (A) X (B) (B)15-8

38
0509C–8051–07/06

NOP
Function: No Operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence, CLR NOP NOP NOP NOP SETB Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 0 0 P2.7 P2.7

Operation: NOP (PC) ← (PC) + 1

ORL

<dest-byte> <src-byte>
Function: Logical-OR for byte variables Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the following instruction, ORL A,R0

leaves the Accumulator holding the value 0D7H (1101011lB).When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction, ORL P1,#00110010B

sets bits 5, 4, and 1 of output Port 1.

ORL A,Rn
Bytes: 1 Cycles: 1 Encoding: 0 1 0 0 1 r r r

Operation: ORL (A) ← (A)

∨ (Rn)

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ORL

A,direct
Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 1 direct address

Operation: ORL (A) ← (A)

∨ (direct)

ORL

A,@R i
Bytes: 1 Cycles: 1 Encoding: 0 1 0 0 0 1 1 i

Operation: ORL (A) ← (A)

∨((Ri))

ORL

A,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 0 immediate data

Operation: ORL (A) ← (A)

∨ #data

ORL

direct,A
Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 0 1 0 direct address

Operation: ORL (direct) ← (direct)

∨ (A)

ORL

direct,#data
Bytes: 3 Cycles: 2 Encoding: 0 1 0 0 0 0 1 1 direct addr. immediate data

Operation: ORL (direct) ← (direct)

∨ #data

40
0509C–8051–07/06

ORL

C,<src-bit>
Function: Logical-OR for bit variables Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV ORL ORL C,P1.0 C,ACC.7 C,/OV ;LOAD CARRY WITH INPUT PIN P10 ;OR CARRY WITH THE ACC. BIT 7 ;OR CARRY WITH THE INVERSE OF OV.

ORL

C,bit
Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 0 1 0 bit address

Operation: ORL (C) ← (C)

∨ (bit)

ORL

C,/bit
Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 0 0 0 bit address

Operation: ORL (C) ← (C)

∨ (bit)

POP

direct
Function: Pop from stack. Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction sequence, POP POP DPH DPL

leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H. At this point, the following instruction, POP SP

leaves the Stack Pointer set to 20H. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 0 0 0 0 direct address

Operation: POP (direct) ← ((SP)) (SP) ← (SP) - 1

41
0509C–8051–07/06

PUSH direct
Function: Push onto stack Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The following instruction sequence, PUSH PUSH DPL DPH

leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Bytes: 2 Cycles: 2 Encoding: 1 1 0 0 0 0 0 0 direct address

Operation: PUSH (SP) ← (SP) + 1 ((SP)) ← (direct)

RET
Function: Return from subroutine Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RET leaves the Stack Pointer equal to the value 09H. Program execution continues at location 0123H. Bytes: 1 Cycles: 2 Encoding: 0 0 1 0 0 0 1 0

Operation: RET (PC15-8) ← ((SP)) (SP) ← (SP) - 1 (PC7-0 ) ← ((SP)) (SP) ← (SP) - 1

42
0509C–8051–07/06

RETI
Function: Return from interrupt Description: RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. Example: The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RETI leaves the Stack Pointer equal to 09H and returns program execution to location 0123H. Bytes: 1 Cycles: 2 Encoding: 0 0 1 1 0 0 1 0

Operation: RETI (PC15-8) ← ((SP)) (SP) ← (SP) - 1 (PC7-0 ) ← ((SP)) (SP) ← (SP) - 1

RL

A
Function: Rotate Accumulator Left Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RL A

leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 0 1 1

Operation: RL (An + 1) ← (An) n = 0 - 6 (A0) ← (A7)

43
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RLC

A
Function: Rotate Accumulator Left through the Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. Example: The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The following instruction, RLC A

leaves the Accumulator holding the value 8BH (10001010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 0 1 1

Operation: RLC (An + 1) ← (An) n = 0 - 6 (A0) ← (C) (C) ← (A7)

RR

A
Function: Rotate Accumulator Right Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RR A

leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 1 1

Operation: RR (An) ← (An + 1) n = 0 - 6 (A7) ← (A0)

RRC

A
Function: Rotate Accumulator Right through Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The following instruction, RRC A

leaves the Accumulator holding the value 62 (01100010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 0 1 1

Operation: RRC (An) ← (An + 1) n = 0 - 6 (A7) ← (C) (C) ← (A0)

44
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SETB

<bit>
Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions, SETB SETB C P1.0

sets the carry flag to 1 and changes the data output on Port 1 to 35H (00110101B).

SETB C
Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 0 1 1

Operation: SETB (C) ← 1

SETB bit
Bytes: 2 Cycles: 1 Encoding: 1 1 0 1 0 0 1 0 bit address

Operation: SETB (bit) ← 1

SJMP

rel
Function: Short Jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it. Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction, SJMP RELADR

assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H. Note: Under the above conditions the instruction following SJMP is at 102H. Therefore, the displacement byte of the instruction is the relative offset (0123H-0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH is a one-instruction infinite loop. Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 0 0 rel. address

Operation: SJMP (PC) ← (PC) + 2 (PC) ← (PC) + rel

45
0509C–8051–07/06

SUBB A,<src-byte>
Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate. Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction, SUBB A,R2

will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by CLR C instruction.

SUBB A,R n
Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 1 r r r

Operation: SUBB (A) ← (A) - (C) - (R n)

SUBB A,direct
Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 1 direct address

Operation: SUBB (A) ← (A) - (C) - (direct)

SUBB A,@R i
Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 0 1 1 i

Operation: SUBB (A) ← (A) - (C) - ((R i))

SUBB A,#data
Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 0 immediate data

Operation: SUBB (A) ← (A) - (C) - #data

46
0509C–8051–07/06

SWAP A
Function: Swap nibbles within the Accumulator Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A

leaves the Accumulator holding the value 5CH (01011100B). Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 0 0

Operation: SWAP (A3-0 ) (A7-4 )

XCH

A,<byte>
Function: Exchange Accumulator with byte variable Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCH A,@R0

leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator.

XCH

A,R n
Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 1 r r r

Operation: XCH (A) ((R n)

XCH

A,direct
Bytes: 2 Cycles: 1 Encoding: 1

Operation: XCH (A) (direct)

XCH

A,@R i
Bytes: 1 Cycles: 1 Encoding: 1

Operation: XCH (A) ((R i))

0509C–8051–07/06

D

D D D

1

0

0

0

1

0

1

direct address

1

0

0

0

1

1

i

47

XCHD A,@Ri
Function: Exchange Digit Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. Example: R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCHD A,@R0

leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 1 1 i

Operation: XCHD (A3-0 ) ((Ri3-0))

XRL

<dest-byte>,<src-byte>
Function: Logical Exclusive-OR for byte variables Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the instruction, XRL A,R0

leaves the Accumulator holding the value 69H (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL P1,#00110001B

complements bits 5, 4, and 0 of output Port 1.

XRL

A,R n
Bytes: 1 Cycles: 1 Encoding: 0 1 1 0 1 r r r

Operation: XRL (A) ← (A) V (Rn)

48
0509C–8051–07/06

D

Document Revision History
Changes from 0509B - 08/05 to 0509C - 07/06
1. Correcto to MOV Direct, page 49.

49
0509C–8051–07/06

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