Andrei Vladimirescu
../
John Wiley & Sons, Inc.
New York Chichester Brisbane Toronto Singapore
ACQUISITIONS EDITOR Steven Elliot MARKETING MANAGER Susan Elbe PRODUCTION SUPERVISOR Richard Blander DESIGNER Kevin Murphy MANUFACTURING MANAGER Inez Pettis ILLUSTRATION COORDINATOR Anna Melhorn This book was set in Times Roman by Publication Services and printed and bound by Malloy Lithographing. The cover was printed by Phoenix Color Corp. The paper in this book was manufactured by a mill whose forest management programs include sustained yield harvesting of its timberlands. Sustained yield harvesting principles ensure that the number of trees cut each year does not exceed the amount of new growth. Copyright @ 1994, by John Wiley & Sons, Inc. Published simultaneously in Canada.
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Library of Congress Cataloging in Publication Data:
Vladimirescu, Andrei. The spice book / Andrei Vladimirescu. p. cm. Includes bibliographical references. ISBN 0471609269 1. SPICE (Computer file) 2. Electric circuit analysisData processing. S. Electronic circuit designData processing. I. Title. TK 454.V58 1994 621.319'2'028553dc20
9333667 CIP
Printed in the United States of America 10 9 8 7 6 5 4 3 2 1
PREFACE
This book is written for electrical engineering students and professionals who use one of the many versions of the SPICE program to analyze and design circuits. The topics presented in this book are universally valid for SPICE users no matter which version they use. This point is reinforced in the text by using the most popular SPICE versions to run the examples developed in the chapters. SPICE has become the standard computer program for electrical simulation, with over 40,000 copies in use worldwide. The name SPICE stands for Simulation Program with Integrated Circuit Emphasis and was inspired by the application to integrated circuit (IC) design, which made computer simulation mandatory. Today, SPICE in its many versions is used not only for IC design but also for analog printed circuit boards, power electronics, and other applications. The majority of the commercial SPICE packages are based on and support the functionality of SPICE2, version G6, from the University of California at Berkeley. The current circuit simulation development at the University of California at Berkeley is devoted to the SPICE3 program. Few commercial products are based on SPICE3, but a number of these programs support SPICE3 functionality that is not available in SPICE2. A commercial version of SPICE that has gained popularity in universities is PSpice, from the MicroSim Corporation. PSpice, which was first introduced as a Personal Computer Program, has become very popular because of the wide use of PCs. The material in this book was developed based on the SPICE2 program, whose functionality and syntax are supported by all other SPICE simulators. The SPICE netlist standard is defined by SPICE2, and all derivatives of the program accept a SPICE2 input file; functionality specific to a certain SPICE program and not available in SPICE2 is introduced as an extension to the SPICE language and is documented in the respective user's guide. Examples throughout this book are simulated alternatively on SPICE2, SPICE3, or PSpice. Functionality available only in SPICE3 is documented, and useful features proprietary to PSpice are mentioned. This book combines in a natural progression a tutorial approach on how to advance from hand solutions of typical electrical and electronic circuit problems to using SPICE, with some reference information on the program necessary for the more advanced user.
VII
viii
PREFACE
The text should be useful to the SPICE novice as well as to the experienced user. The reader is assumed to have a basic electrical engineering background and be able to use a computer. The approach in this book emphasizes that SPICE is not a substitute for knowledge of circuit operation, but a complement. The SPICE Book is different from previously published books on this subject in the approach of solving circuit problems with a computer. The solution to most circuit examples is sketched out by hand first and followed by a SPICE verification. For more complex circuits it is not feasible to find the solution by hand, but the approach stresses the need for the SPICE user to understand the results. Although the program can detect basic circuit specification errors, it cannot flag conceptual errors. It is up to the user to question the program through the various analysis modes in order to get insight into what is wrong with the circuit. Briefly stated, the results of SPICE are only as accurate as the circuit description and the component models used. The first six chapters provide information about SPICE relevant to the analysis of both linear passive circuits and electronic circuits. Each of these chapters starts out with a linear example accessible to any new user of SPICE and proceeds with nonlinear transistor circuits. The latter part of the book goes into more detail on such issues as functional and hierarchical models, distortion models and analysis, basic algorithms in SPICE, analysis option parameters, and how to direct SPICE to find a solution when it fails. This book is ideally suited as a supplement to a wide range of circuits and electronics courses and textbooks. It is of special interest in junior, senior, and graduate courses, from introductory courses on electric circuits up to analog and digital integrated circuits courses. The subject of computeraided circuit simulation is put in a historical perspective in the Introduction to this book. The milestones of the research in the late 1960s and early 1970s that led to the SPICE program are presented first. The proliferation of SPICE versions and the salient features of the most popular programs are described. The Introduction follows the evolution of the SPICE effort at the University of California at Berkeley from the beginning to the present day. This historical perspective concludes with the current research in the area of electrical computer simulation and the possible future SPICE developments in the 1990s. Chapter 1 is an introduction to the computer simulation of electrical circuits and the program SPICE. The approach used in SPICE to solve electrical problems is described in simple terms of the Kirchhoff voltage law, the Kirchhoff current law, and branch constitutive equations. A linear RLC circuit is used to exemplify the workings of SPICE. The reader is also introduced to the SPICE input language, the network specification, the analysis commands, and the types of result output available. The sequence of events for simulating a circuit is completed by examples on how to run SPICE on the most common computers. Chapter 2 presents in detail the circuit specification in terms of elements, models, and the conventions used. The SPICE syntax is detailed for twoterminal elements, such as resistors, capacitors, inductors, and voltage and current sources, and multi terminal elements, such as controlled sources, switches, and transmission lines.
PREFACE
ix
Chapter 3 introduces the semiconductor device elements and models available in SPICE. The dual specification as device and model is explained for semiconductor elements. Only the firstorder models are described in this chapter for devices represented by several levels of complexity. The model parameters are related to the branchconstitutive equations of the device as well as to electrical characteristics. The most important physical effects and corresponding parameters are described for the five semiconductor devices supported: diodes, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), metaloxidesemiconductor field effect transistors (MOSFETs), and metalsemiconductor field effect transistors (MESFETs). This chapter does not cover the details of each model but provides references dedicated to the subject. Chapter 4 contains an overview of the analysis modes of SPICE and a detailed description of DC analysis. In the DC mode SPICE can perform an operating point analysis, compute DC transfer curves, estimate the value of the transfer function, and perform sensitivity calculations. Chapter 5 describes the SPICE functionality in the smallsignal frequency domain. The AC mode analysis types, such as the frequency sweep, noise, and distortion analyses, are introduced by means of both linear and nonlinear circuit examples. Chapter 6 presents the timedomain, or transient, simulation. In the timedomain analysis mode SPICE computes the transient response of a circuit and the harmonics of a signal. At least one workedout circuit example is included for each analysis type. The reader acquires the basic knowledge of using SPICE by the end of this chapter. Chapter 7 introduces the concept of functional simulation. Higherlevel abstractions and hierarchy can be modeled in SPICE using controlled sources and subcircuit blocks. Logic gates and operational amplifiers can be described using the macromodeling approach. Examples demonstrate the compactness and efficiency of macromodeling for opamp circuits. The last three chapters of the book, Chaps. 8 to 10, are intended for the more advanced user. The material presented in the first part should be sufficient for solving most circuit problems encountered in undergraduate and graduate courses. There are three main topics in the second half, which can be be studied independently of each other. Chapter 8 covers in some detail distortion analysis, Chap. 9 contains an explanation of the solution techniques built into SPICE and the analysis options that may be necessary for solving complex circuits, and Chap. 10 uses the information in the previous chapter to steer the user on how to ensure the convergence of SPICE. Chapter 8 offers an indepth look at distortion analysis. The details of smallsignal and largesignal distortion analysis are described with the help of several examples. A brief overview of the algorithms and numerical methods used in SPICE is presented in Chap. 9. The purpose of this chapter is to offer some insight into the internal workings of SPICE for the user interested in taking advantage of all the available analysis controls or options, which are also described in this chapter. The main topics are solution of sparse linear equations, iterative solution of nonlinear equations and convergence, and numerical integration. Chapter 10, which concludes this book, is a primer on convergence and the actions a user can take to overcome DC and timedomain convergence problems. Solutions to
X
PREFACE
convergence problems are offered using initialization, analysis options, and nonlinear model parameters. The importance of understanding the operation of the circuit and the limitations of the models used is emphasized for obtaining accurate results. Five appendixes are included at the end of the book. The first contains the complete equations for the semiconductor devices and the full list of model parameters. The second appendix lists the most common error messages of SPICE2 and provides guidance on corrective action. The error messages included are common to most SPICE versions, although the exact wording may differ. Appendix C summarizes all the SPICE statements introduced in this book. Appendix D contains the Gear integration formulas of orders 2 to 6. The last Appendix contains a sample SPICE deck of a circuit that requests most analyses supported by SPICE2. This book is a result of my association with Professor D. O. Pederson, who has guided me during my academic studies as well as during my professional activity. I acknowledge Judy Lee for the graphic design and the presentation of the schematics and the simulation results. I also acknowledge the review and comments contributed by Dr. Constantin Bulucea in addition to the valuable comments made by the following reviewers for John Wiley and Sons: Kenneth Martin, UCLA; Richard Dort, University of California at Davis; Ron Rohrer, Carnegie Mellon University; Norb Malik, University of Iowa; Bruce Wooley, Stanford University; Darrell L. Vines, Texas Tech University; James R. Roland, University of Kansas; David Drury, University of Wisconsin, Platteville; Robert Strattan, University of Oklahoma; John O'Malley, University of Florida, Gainesville; Gordon L. Carpenter, California State University, Long Beach; and Elliot Slutsky, Cal Poly, Pomona. Together with colleagues and customers of Daisy Systems, Analog Design Tools, Valid, and Cadence, as well as University of CaliforniaBerkeley students, they have contributed to the material covered in this book. October 1993 Andrei Vladimirescu
CONTENTS
Introduction
SPICETHE THIRD DECADE
1 1
~,', I
1.1 THE EARLY DAYS OF SPICE 1.2" SPICE IN THE 19705 i.3 SPICE IN THE 19805 1.4 SPICE IN THE 19905 1.5 CONCLUSION REFERENCES
2 4 7 8 9
I.
Chapter One
INTRODUCTION SIMULATION
1.1 1.2 1.3
TO ELECTRICAL COMPUTER
12
PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS WHAT IS SPICE? USER INTERACTION WITH SPICE AND THE COMPUTER
1.3.1 1.3.2 1.3.3 Electric Circuit SpecificationThe SPICE Input SPICE Simulation, DC Analysis . SPICE Results for AC and TRAN Analyses
12 14 17 18
22
28
36
1.4 SUMMARY REFERENCES
37
XI
xii
CONTENTS
Chapter Two
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
2.1 2.2 ELEMENTS, MODELS, NODES, AND CONVENTIONS TWOTERMINAL ELEMENTS
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Resistors Semiconductor Resistors (SPICE3) Capacitors Semiconductor Capacitor (SPICE3) Inductors Independent Bias and Signal Sources 2.2.6.1 Pulse Function 2.2.6.2 Sinusoidal Function 2.2.6.3 FrequencyModulated Sinusoidal Function 2.2.6.4 Exponential Function 2.2.6.5 Piecewise Linear Function Coupled (Mutual) Inductors Dependent (Controlled) Sources 2.3.2.1 VoltageControlled Current 2.3.2.2 VoltageControlled Voltage 2.3.2.3 CurrentControlled Current 2.3.2.4 CurrentControlled Voltage Switches Transmission Lines
38 38
39
40 41 42 44 45 46 48 50 51 53 54 56 56 58 61 62 63 64 65 68 71 72
2.3
MULTITERMINAL ELEMENTS
2.3.1 2.3.2
Source Source Source Source
(VCCS) (VCVS) (CCCS) (CCVS)
2.3.3 2.3.4
2.4
SUMMARY
REFERENCES
Chapter Three
SEMICONDUCTORDEVICE
3.1 3.2 3.3 INTRODUCTION DIODES BIPOLAR JUNCTION TRANSISTORS
3.3.1 3.3.2 3.3.3 DC Model Dynamic and SmallSignal Models Model Parameters
ELEMENTS
73 73 75 78 79 83 86 96 101 102 103
108
3.4 3.5
JUNCTION FIELD EFFECTTRANSISTORS (JFETs) METALOXIDESEMICONDUCTOR
3.5.1 3.5.2 3.5.3
FIELD EFFECTTRANSISTORS (MOSFETs)
DC Model Dynamic and SmallSignal Models Model Parameters
4 5.1.1 4.5 4.1 6.3 4.5 5.2 4.6 3.CONTENTS xiii 109 112 113 3.1.3 5.4 4.2 ANALYSIS168 168 .6 INTRODUCTION AC FREQUENCY SWEEP NOISE ANALYSIS DISTORTION ANALYSIS POLEZERO ANALYSIS SUMMARY 141 141 .2 Simulation Modes and Analysis Types Result Processing and Output Variables Analysis Parameters: Temperature 114 114 114 115 116 117 125 129 133 136 139 140 4.7 OPERATING (BIAS) POINT DC TRANSFER CURVES SMALLSIGNAL TRANSFER FUNCTION SENSITIVITY ANALYSIS NODE VOLTAGE INITIALIZATION SUMMARY REFERENCES Chapter Five AC ANALYSIS 5.6 4.7 METALSEMICONDUCTOR SUMMARY FIELD EFFECTTRANSISTORS (MESFETs) REFERENCES Chapter Four DC ANALYSIS 4.1 5.1 ANALYSIS OVERVIEW 4.142 149 157 164 165 167 REFERENCES Chapter Six TIMEDOMAIN 6.169 ANALYSIS DESCRIPTION TRANSIENT ANALYSIS .3 4.2 5.1.
6 MACROMODElS 7.3.2 8.3 6.3.2 7.2 704.2.3 70404 7.1 7.2 AND HIERARCHICAL SIMULATION 193 193 194 194 195 195 204 205 209 213 213 215 223 224 227 228 HIGHLEVEl CIRCUIT DESCRIPTION SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 7.2 DISTORTION IN SEMICONDUCTOR CIRCUITS SMAllSIGNAL 8.5 7.1 7.2 7.2.5 CONTENTS INITIAL CONDITIONS FOURIER ANALYSIS SUMMARY 180 184 REFERENCES 191 192 Chapter Seven FUNCTIONAL 7.1 8.2.3.xiv 6.4 6.2.4 SUMMARY REFERENCES .1 SUMMARY REFERENCES 239 240 Chapter fight DISTORTION ANALYSIS 8.1 8.1 8.3 LARGESIGNAL DISTORTION ANALYSIS 8.3 .1 704.5.2 241 241 241 242 244 263 263 265 276 277 DISTORTION ANALYSIS HighFrequency Distortion Distortion in a OneTransistor Amplifier OneTransistor Amplifier Distortion SingleDevice Mixer Analysis 8.4 FUNCTIONAL MODElS 704.3 IDEAL MODElS 7.1 7. SUBCKT Definition Subcircuit Instance Circuit Hierarchy Operational Ampl ifiers Logic Gates and Digital Circuits Nonlinear (ArbitraryFunction) Analog Function Blocks Digital Function Blocks Equation Solution The Opamp MacroModel Controlled Sources in SPICE3 7.3.2.
1 Oscillators 10.2 Numerical Integration Integration Algorithms in SPICE.4. Accuracy.6 REFERENCES .4.3 Convergence of Large Circuits SUMMARY 10.1 Analysis Summary 9.5.2 Accuracy and SPICE Options DC SOLUTION OF NONLINEAR CIRCUITS 9.1 10.1 9.2 Linear Equation Options 9.1 9.2.2 AND OPTIONS 278 278 280 280 285 291 291 296 298 299 307 312.3.3 Nonlinear Solution Options 9.5.5.5.5.5 Miscellaneous Options REFERENCES Chapter Ten CONVERGENCE ADVICE 10.4 10.CONTENTS XV Chapter Nine SPICE ALGORITHMS 9.3 10. 312 314 315 315 316 317 OVERVIEW OF ALGORITHMS DC SOLUTION OF LINEAR CIRCUITS 9.5 SUMMARY OF OPTIONS 9.4 Numerical Integration 9.5.2.2.1 NewtonRaphson Iteration 9.5.1 Circuit Equation Formulation: Modified Nodal Equations 9.4 9.5.1 Circuit Description 10.3 9.2 Convergence and SPICE Options TIMEDOMAIN SOLUTION 9.3.5 10.2 Component Values DC CONVERGENCE TIMEDOMAIN CONVERGENCE CIRCUITSPECIFIC CONVERGENCE 10.2 8JT versus MOSFET Specifics 10. and Options 9.2 INTRODUCTION COMMON CAUSES OF SOLUTION FAILURE 319 319 320 320 326 330 353 362 362 367 373 375 377 10.2.
3. and AC Models Temperature Effects Noise Model DC Model Transient and AC Models Temperature Effects Noise Model DC Model Transient and AC Models Temperature Model Noise Model MODELS 378 378 379 379 380 380 381 382 383 383 384 385 389 390 390 390 A.5 B.4 B.l B.2 A. CIRCUIT TOPOLOGY ERRORS SUBCIRCUIT DEFINITION ERRORS ANALYSIS ERRORS MISCELLANEOUS ERRORS AND MODEL ERRORS 391 391 392 392 393 394 394 395 398 APPENDIXC SPICE STATEMENTS C.6 B.3 MOSFET A.3 ELEMENT STATEMENTS GLOBAL STATEMENTS CONTROL STATEMENTS 399 399 400 401 .2 BIPOLAR JUNCTION TRANSISTOR A.3.3. SEMICONDUCTORDEVICE.2 C.l DIODE A.l C.1.1 A.1.8 GENERAL SYNTAX ERRORS MULTITERMINAL ELEMENT ERRORS SOURCE SPECIFICATION ERRORS ELEMENT.3 A.2.2 A.2 B.2 A.2.2.3 A.1 A.XVI CONTENTS APPENDIX A SEMICONDUCTORDEVICE A.3 DC.3.4 A.3 B.1 A.4 REFERENCES APPENDIX B ERROR MESSAGES B.1.7 B. Transient.2.
CONTENTS xvii APPENDIX D GEAR INTEGRATION APPENDIX E SPICE INPUT DECK INDEX 403 FORMULAS 402 405 .
.
Rohrer. which in its various versions enjoys 1 . A general description of SPICE techniques. under the guidance ofD. Nagel 1975). analysis modes.Introduction SPICETHE THIRD DECADE This introduction is a review of the evolution of SPICE from the initial research project at the University of California at Berkeley in the late 1960s. Pederson and R. The current trends in electricalcircuit simulation and the role of SPICE in its third decade are presented in the last part. That this program was written by engineering students for engineers explains the simple and computationally efficient approach chosen for the network equations and the builtin semiconductordevice models. and into the 1990s. and circuits to be characterized is explored in order to clarify the merits and limits of this program. and intended areas of application is provided first. who had a mandate to produce the best computer program for the simulation of practical integrated circuits.1 THE EARLY DAYS OF SPICE SPICE in its different versions has been the main computeraided analysis program used in analog design for over 20 years. through the 1970s and 1980s. SPICE2 (Cohen 1975. ICs. 1. The program known as SPICE today was first released under the name CANCER (Nagel and Rohrer 1971) in 1970 and acquired the name SPICEI (Nagel and Pederson 1973) in 1972. SPICE is the result of the work of a number of talented graduate students in the Department of Electrical Engineering and Computer Science at the University of California at Berkeley. The relation between solution algorithms. semiconductordevice models.
The algorithms of TRAC evolved into the programs TIME (Jenkins and Fan 1971) at Motorola and SINC at Berkeley. and up to 100 nodes. nonlinear equation solution. McCalla. and nonlinear semiconductordevice modeling. a division of Rockwell Corporation.2 SPICE IN THE 19705 In the early 1970s L. The need for accurate largesignal timedomain simulation for the characterization of highly nonlinear circuits such as oscillators fueled the research for numerical integration and the development of the programs TRAC (Johnson et al. The universal acceptance is due not only to its robustness and ease of use but also to its free distribution by DC Berkeley. 1968) at Autonetics. and reordering schemes for sparse matrices. a program for the nonlinear DC solution of bipolar circuits. Jenkins. and the program was developed and initially used on a CDC 6400. and Pederson 1971) to address the analysis of linear bipolar ICs. The algorithmic research carried out during the development of these programs converged to the use of the NewtonRaphson solution of nonlinear equations. Pederson (1984). 1. continuing to develop the CANCER type of program. and CIRPAC (Shichman 1969) at Bell Labs. input language. was released in 1975. In the design oflinear ICs such as the /LA 741. sparsematrix solutions. The choice of the nodal admittance representation is based on the relative ease of setting up the circuit matrix and the quick access to the DC operating point. It is important to note that the early years of the SPICE development were dedicated to the investigation of the most accurate and efficient numerical methods for circuit representation. These efforts were continued through the 1970s with the MSINC program at Stanford and MTIME. which is still in use at Motorola. An excellent review of the algorithms. BIAS3 (McCalla and Howard 1971). The main goal of the SPICE project has been to provide an efficient computer tool for the design of the emerging ICs in the late 1960s and early 1970s. The emphasis on linear IC design using bipolar technology explains the priority given the implementation of bipolar device models. Nagel. A number of related programs originated from this research. First. was developed. and transistors. Simulation Program with IntegratedCircuit Emphasis. and milestones in circuit simulation evolution can be found in the paper by D. A better model for bipolar transistors. limiting techniques. with only 100 transistors and diodes. diodes. In May 1972 SPICEl was distributed for the first time in the public domain (Nagel and Pederson 1973). called the new version SPICE. integration algorithms. The most important addition to this program was in the area of semiconductor device models. it was later included in SUC (Idleman. CANCER (Nagel and Rohrer 1971) implemented the EbersMoll model (Ebers and Moll 1954) for the bipolar transistor described by 18 parameters. techniques. implicit integration methods using fixed time steps. checking the bias point and performing a smallsignal analysis were essential. the integral chargecontrol model .2 INTRODUCTION SPICETHE THIRD DECADE the largest use worldwide today. The circuit decks were submitted on punched cards. The circuit size was limited to 400 components.
The next major release of the program. such as drain and source . and these circuits used mostly nchannel MOS devices. which had introduced ECAP in 1965. This new representation added support for voltagedefined elements. A new approach to IC modeling. 1971). was introduced at this time to overcome the long run times required by the use of detailed transistorlevel schematics. Hodges (1968). variableorder integration and the NewtonRaphson nonlinear solution. included secondorder effects. A noteworthy event that took place in the second half of the 1970s was the introduction by NCSS of ISPICE (Interactive SPICE). LSI. and Scott 1973). which are simulated much faster. Shichman and D. and distortion. Mehta. was introduced in 1970. Models for two other semiconductor devices were added to SPICE1: the junction field effect transistor (JFET) and the metaloxidesemiconductor field effect transistor (MOSFET). A new circuit representation. It was important to add device geometry information. Poon (1971). The representation of MOSFETs in SPICE2 was significantly overhauled at this time. In this first implementation the two models were very similar and were based on the firstorder quadratic model of H. known as sparse tableau. leading to their classification as thirdgeneration circuit simulators (Hachtel and SangiovanniVincentelli 1981). such as highlevel injection and lowlevel recombination. known as macromodeling (Boyle. It allowed the program to allocate dynamically the entire available memory to the solution of the circuit. Ruehli. ASTAP and SPICE2 used implicit. A novel circuittheoretical concept. This model. IC technology had advanced the complexity of circuits to largescale integration. such as voltage sources and inductors. The accuracy and speed of the analysis were improved by the addition of a timestep control mechanism and the stiffly stable multipleorder integration method of Gear (1967). The first macromodels were developed for operational amplifiers by replacing many transistors through functionally equivalent controlled sources. Jimenez. This trend of commercial SPICE derivatives grew considerably in the 1980s. and Brennan 1975. which allowed access to all desired circuit state variables at the cost of run time and memory. In the late 1970s all semiconductor companies used circuit simulation and most adhered to SPICE. Gurnmel and C. Pederson. replaced the old nodal analysis. and represented a major advancement over the EbersMoll model. Quassemzadeh. known as modified nodal analysis (MNA) (Ho. noise. and Solomon 1974). This capability addressed the need to design larger ICs. the adjoint network. was completed in 1975 and offered significant improvements over SPICEl. Cohen. A memory management package was developed in SPICE2 (Cohen 1975). Mahoney. Independent research on circuit simulation conducted at IBM.SPICE IN THE 19705 3 of H. Macromodels are to this day the main approach to representing SPICE equivalent circuits for a variety of complex ICs. the first commercially supported version. was introduced by Director and Rohrer (1969) in the late 1960s and added to SPICE very efficient computation of sensitivity. available in SPICE1. Idleman et al. ASTAP used a different circuit representation. because by the mid1970s ICs had grown in complexity and the component limit of SPICE1 had become a serious limitation. led to the ASTAP program (Weeks. A new push was initiated by industry to improve the SPICE2 device models to keep up with technology. SPICE2 (Nagel 1975).
The need to measure subpicocoulomb charges in memory cells also led to the implementation of a chargebased MOS model (Ward and Dutton 1978) in addition to the existing piecewise linear Meyer capacitance model (Meyer 1971). With the proliferation of the number of users. The increase in circuit size also brought about the need for increasing the accuracy of the sparsematrix solution by allowing for runtime pivoting to correct any singularity that may occur during a long transient simulation. and transittime modeling were added to the GummelPoon model. 1984.4 INTRODUCTION SPICETHE THIRD DECADE areas. and Newton 1983). used in the SPLICE simulators (Kleckner.Vincentelli 1984) led to the waveform relaxation technique. exemplified by the RELAX2 program (White and SangiovanniVincentelli 1983). and SPICE saw a tremendous increase in use. . two more complex models were added. A number of approaches for speeding up electrical simulation by relaxing the accuracy or limiting the class of circuits to which it can be applied were used in several programs. carrier velocitylimited saturation. split basecollector capacitance. Algorithmic innovation in timing simulation (Newton and Sangiovanni. and the absence of feedback. timing simulators did not have the accuracy needed in the design of sophisticated microprocessor and memory chips. which was first introduced in the midl 970s. This class of electrical simulators achieved speedups in excess of an order of magnitude compared to SPICE for MOS digital circuits. and number of squares. 1. The attempt to use these programs to characterize analog circuits required the implementation of the more accurate and timeconsuming SPICE device models and often resulted in longer run times than SPICE. Kleckner. the infrequency of events in digital circuits. This need was the driving force of new businesses with the charter to upgrade and support publicdomain SPICE2. the introduction of the minicomputer gave engineering groups easier access to computer resources. Gummel. it became obvious that support for SPICE users was lacking. Examples include HSPICE from MetaSoftware (1991). Bipolar transistor geometries were also shrinking and the frequency of operation rising. substrate capacitance. LSI chips required electricalsimulation speeds in excess of an order of magnitude faster than SPICE. Large companies had internal CAD groups dedicated to support and enhancement of software packages for their engineers. had little help when using publicdomain programs such as SPICE. led the way to a number of programs that took advantage of MOSFET characteristics. Saleh. or MOS Timing Simulator (Chawla. that described such effects as subthreshold conduction. Small engineering firms. and iterated timing analysis. Improvements such as base pushout. and engineers were able to view the results of the simulation on their terminals as soon as the analysis had been completed. The VAX 11/780 quickly became the platform of choice for running SPICE. Newton 1978.3 SPICE IN TH E 19805 At the beginning of the 1980s. however. Timing simulators such as MOTIS. and Kozak 1975). perimeters. and shortand narrowchannel effects (Vladimirescu and Liu 1980). In addition to the simple squarelaw MOSFET model available in 1976. Although fast.
. the customization needed for the various parallel architectures. An alternate way to more speed has been to bui'ld dedicated hardware accelerators for circuitsimulation algorithms (Vladimirescu. All three addressed the most lucrative aspect of digital design first. and Valid. could be :simulated only a few times faster. was available on the IBM PCXT. Program SLATE (Yang.g. where individual blocks can be evaluated depending on the perforined function. Ng. of SIMUCAD Corporation for multipleinstruction multipledata (MIMD) computers.. The lack of impressive speed returns. White 1986). A major development by the mid1980s was the proliferation of the personal computer in the engineering field. . and the emergence of RISC workstations with everincreasing processing speeds doomed these efforts in the late 1980s. and the graphic display of results on the same screen/workstation had become obvious . In spite of these first programs.. often the result of layout extractors.against the desire of software tool companies to develop universal tools. Daisy took the lead in electrical simulation devel9pment by supporting an improved SPICE2 version. Danuwidjaja. simulation. simulation. DMV realized this need and linked its schematic capture to a SPICE version and developed waveform display tools. good commercial mixedmode simulators are lacking. the de facto reference for SPICE throughput. ... One possible explanation is that the need for customization of mixedmode simulators for specific applications goes. Weiss. or hybrid. Speedups of up to an order of magnitude were achieved for circuits having a regular hierarchical structure. based on the MSPLICE project at UC Berkeley. The need for an integrated analog simulation tool that would cover design entry. DSPICE. due to either insufficient performance or inflexibility . SPICE received an additional boost from the three companies Daisy. SPICE IN THE 19805 5 o i A differertt approach to faster simulation of complex ICs is the mixedmode. . 1980). Niraj. also referred to as DMV. e. PCbased SPICE programs have attracted many new users and considerably expanded the popularity of this electric simulator. whereas digital blocks can be evaluated using logic simulation. which was developed at UC Berkeley for C~AY vector computers. Mentor. Examples include CLASSIE (Vladimirescu 1982). Haji. which belong to the class of singleinstruction multipledata (SIMD) machines. which in 19811982 introduced integrated software packages for electronic design using microprocessorpowered engineering workstatio~s. • Yet another approach for speeding up electrical simulation was to tailor the directmethod algorithms of SPICE2 to various panHlel computer architectures. DIANA frQm the University of Leuven (DeMan et al. as part of its analog :. and PACSIM (Deutsch and Newton 1984).. These accelerators did not make it beyond a prototype. and Lass 1987.. the first pC ver'sion of SPICE.. and SAMSON from Carnegie Mellon University (Sakallah and Director 1980). By early 1984 PSPICE (MicroSim 1991). only analog blocks need electrical characterization.. which emerged from research at the University of Illinois at Urbana. Flatcircuit netlists. such as the Sequent or Alliant machines. decoupled the analysis of circuit blocks and took advantage of latency to ~peed up the timedomain simulation. Early efforts in this category include SPLICE from UC Berkeley. Although eight times slower than I ! on a VAX 11/780. The field they developed is called computeraided engineering. and Trick 1980).
An important achievement of the concurrent SPICE work in this decade was the elimination to a large degree of convergence problems. Tektronix. University research made new contributions to SPICE technology during this decade. who historically had been reluctant to use computers. The use of continuation methods and education of users contributed toward reliable DC analysis. modular. Newton. however. Most of these groups had provided output display tools on graphic terminals in the second half of the 1970s. easily understood. the goal of which was to rewrite and improve SPICE2 version 2G6 (Vladimirescu. Improved models and techniques for handling discontinuities resulted in robust timedomain simulation as well.6 INTRODUCTION SPICETHE THIRD DECADE Virtual Lab software. and additional functionality and userfriendly features. This feature was first available in ASTAP and then expanded in the SABER simulator (Analogy Inc. Texas Instruments. An interesting concept that gained support toward the end of the 1980s was to provide the user the capability of describing the functions that govern the operation of devices used in the simulation. and National Semiconductor. SPICE3 (Quarles 1989b) was released in the public domain in March 1985. promoted the behavioral representation of entire circuit blocks by timedomain or frequencydomain equations.and boardlevel analog designer and to add new functionality and models to the program to serve the needs of those applications. These limitations led to the SPICE3 project at UC Berkeley (Quarles 1989a). HewlettPackard. accurate semiconductor device modeling. . and Sangiovanni. Harris Semiconductor. Both ADT and Daisy developed analog component libraries needed by analog system designers. 1987) from Analogy. Zhang. such as TI SPICE. structured program with a graphic tool for the display of results. Analog Design Tools (ADT). Modeling entire circuit blocks at a functionallevel rather than transistor level speeds up the simulation and enables a designer to evaluate an entire analog board or system. initially developed as a piecewise linear electrical simulator addressed to the simulation of analog systems. an Apple Macintoshlike user interface called the Analog Workbench. The SPICE technology was also advanced by the contributions of talented CAD groups at Bell Labs. the widespread use of UNIX in the university research environment offered increased interaction between user and program. Although these proprietary developments were not available to the user at large. A new company. which extended electric simulation to boardlevel analog engineers and powersupply designers. was a FORTRAN batch program and was difficult to modify and limited in its potential use of Cshell utilities.Vincentelli 1981) using the C language to produce an interactive. SABER. ADVICE at Bell Labs. such as ADICE from Analog Devices and TekSPICE from Tektronix. and HP SPICE. while the other two offered a user interface with SPICE2 or deferred the choice of the simulator to the end user. SPICE2. Analog Devices. During the 1980s the effort was directed toward robust convergence. The major achievement of these CAE companies was to extend the use of SPICE to the system. ideas and results of this parallel research work eventually found their way into publicdomain or commercial software. Pederson. emerged in 1985 with a wellintegrated analog CAE product. At the beginning of the 1980s.
and others. Every major supplier of analog CAD/CAE software offers a wellsupported and enhanced version of SPICE2 or SPICE3. Another direction of research is steadystate analysis. An example of a stateoftheart analog CAE product is the Analog Workbench II (1990) from Cadence. a schematic replaces the SPICE deck. White. and SangiovanniVincentelli 1988). Timedomain simulation is controlled by popup menus. This mode is particularly important for circuits with long settling times. • . This approach is not very efficient for nonlinear transistor circuits. Viewlogic. which solves the above problem in the time domain. A number of interesting developments started in this direction at the end of the 1980s. no reliable program is available today. and tighter integration with schematic capture. and the resulting waveforms can be viewed and measured in an Oscilloscope tool. SPICE also lacks capabilities for specific applications. The major CAE companiesCadence and Mentoroffer a proprietary SPICE version as part of their analog CAE products: Analog Workbench and Analog Artist from Cadence and Accusim from Mentor. Intergraph. Specialized programs such as SWITCAP (Fang and Tsividis 1980) have been developed to fill this need. Similar analog CAE packages are available today from Microsim. All information needed for simulation is entered in graphical form and through menus. The main emphasis for the near future is on increased functionality. and component libraries. Mentor.Vincentelli 1986) a nonlinear frequencydomain analysis program developed at DC Berkeley. and SSPICE (Ashar 1989) is a vehicle for studying various troubleshooting techniques for the steadystate solution. such as filter design in general and switched capacitor filters in particular. In order to simulate a differential amplifier.SPICE IN THE 19905 7 1. introduced by Analog Design Tools in 1985. higherlevel modeling. Current research is under way at MIT and DC Berkeley. Solution in the frequency domain is especially useful for finding the steadystate response of circuits with distributed elements and highQ resonators. a similar setup with a Frequency Sweeper and a Network Analyzer tool is used to control and view the results of an AC smallsignal analysis. Input signals are defined and checked in a Function Generator tool. The circuit is entered as an electric schematic. as well as with physical design tools. display tools. One extension is exemplified by Harmonica (Kundert and Sangiovanni. such as switching power supplies. that is. Significant research will be dedicated to extending the functionality of electrical simulation beyond the established analysis modes of SPICE. Modeling technology is an important aspect of circuit simulation and is instrumental in defining the capabilities and the accuracy of a program .4 SPICE IN THE 19905 Today SPICE is synonymous with analog computeraided simulation. such as printed circuit boards and integrated circuit layout. Although research on this topic took place in the 1970s (Aprille and Trick 1972). Intusoft. Analogy. an envelopefollowing method is used in NITSWIT (Kundert. beyond nonlinear DC and timedomain analysis and smallsignal frequencydomain analysis. This trend of developing specific functionality for given applications not well suited to traditional SPICE analysis will continue in this decade.
and 1000 gigabytes of disk storage. by supporting blocks described by integrodifferential or algebraic equations. IDAC (Degrauwe et al. the author concludes that "for the foreseeable future nothing will supplant SPICE as the industry standard for analog simulation. During the next decade analog synthesis tools will evolve to facilitate the design of complex analog and mixed analogdigital systems. Centre Suisse d'Electronique et de Microelectronique (CSEM). Over the next few years the power of engineering workstations will increase to 1000 MIPS. such as nonlinear frequencydomain analysis and higherlevel modeling capabilities. 1990).5 CONCLUSION The new developments in circuit simulation do not make SPICE obsolete but rather complement it. in order to keep up with evershrinking semiconductor devices. can be used to design welldefined circuit blocks. The ability to represent entire circuit blocks by an equation or a set of equations will make simulation of complete analog systems possible. the synthesis tools these groups have developed. Advances in computer technology will also increase the applicability of circuit simulation.8 INTRODUCTION SPICETHE THIRD DECADE At the top level of circuit representation. At the transistor level of representation. and the University of California at Berkeley. OASYS (Harjani. and OPASYN (Koh." SPICE will probably add a number of analysis modes. from a collection of analog cells available in the knowledge base. Research work in the area of analog synthesis has been reported by groups at Carnegie Mellon University. Rutenbar. This translates into a 50. 1. according to Bill Joy's forecast at the 1990 Design Automation Conference (Joy 1990). One important up . Whereas for the last two decades circuit simulation has been used mostly for analyzing fullyspecified circuits. and Carley 1989). Such functionality creates the need for powerful modelgeneration software capable of automating the process. Sequin. Improved transistor models have been reported in technical journals during the last decade with little impact on the various SPICE releases.000transistor circuit simulation capability. SPICE will continue to be the main electrical simulator. more support will be developed for the behavioral/structural description of entire circuit blocks. which is reported to describe quasisaturation and highfrequency effects better than the current GummelPoon model and which could be a useful addition to SPICE. because it solves the fundamental equations of an electrical system. SPICE will form the analytic core of analog optimization and synthesis software tools. Also. 1000 megabytes of memory. in this decade more emphasis will be put on the design aspect. Analog Hardware Descriptive Language (Kurker et al. such as operational amplifiers. Examples include the MEXTRAM model (de Graaf and Klosterman 1986) for bipolar transistors. and Gray 1987). a description language for analog behavior. respectively. In conjunction with other software modules. is under development under the guidance of the IEEE Standards Coordinating Committee 30. 1987). SPICE will probably evolve to an open architecture that would enable CAD groups of IC manufacturers to implement better device models or upgrade the default ones. In a recent report on PCbased analog simulation published in the magazine EDN (Kerridge 1990).
"The Generalized Adjoint Network and Network Sensitivities. "Program Reference for SPICE2. and T. J. M. Ashar. 1986.. 1984." IEEE Transactions on Circuits and Systems CAS22 (December): 901909. 1970. Ebers." IEEE ISCAS Conference Proceedings: 977980. T. Gummel.. of Illinois. ACKNOWLEDGMENT The author would like to thank D. D. Moll. and J. E. of California. Deutsch. S. H. Rohrer. Fang. W. E. UCBIERL M75/520 (May). H. 1954.. Rye Brook. 1989. Tsividis." 21st ACM/IEEE DAC Conference Proceedings. T. Solomon. Inc. and J. and A. L. Gear. N. "MOTISAn MOS Timing Simulator. DeMan. J. "Implementation of Algorithms for the Periodic SteadyState Analysis of Nonlinear Circuits. Kozak. 1987 (December). "IDAC: An Interactive Design Tool for Analog CMOS Circuits. Berkeley. J. OR: Author." IEEE Journal of SolidState Circuits SC9 (December): 353363. 1969. K. N. Tokyo: 287290. C. and W. "Large Signal Behavior of Bipolar Transistors. R. 1975. Saber: A Design Tool for Analog Systems.. Conference on SolidState Devices and Materials. REFERENCES "Analog Workbench II Adds Framework Features. C." IEEE ICCC '80 Conference Proceedings. de Graaff. with Accurate Description of Collector Behavior. and R A. M.. Director. Chawla. and P. Univ. 1975. O. "An Integral ChargeControl Model of Bipolar Transistors.. 1974. Beaverton. Urbana. ." Report 221. "SteadyState Analysis of Nonlinear Circuits with Periodic Inputs." Univ. P. H.. C. c. NY (October): 356360. "Compact Bipolar Transistor Model for CACD. S." Proceedings IRE 42 (December): 17611772.. of Computer Science. B. Albuquerque. Aprille. 1980. "A Multiprocessor Implementation of Accurate Electrical Simulation. B." Bell System Technical Journal 49 (May): 827852." Proceedings of the IEEE 60: 108116. 1967. Newton. "Numerical Integration of Stiff Ordinary Differential Equations. Pederson for the inspiring discussions and suggestions that helped identify the various trends and the chronology of circuit simulation over the past three decades. R. Gummel. R. Dept." IEEE Journal of SolidState Circuits SC22 (December): 11061116. 1972. J. Poon. Klosterman. Cohen.P. ERL Memo No. "Modified Nodal Analysis with Improved Numerical Methods for Switched Capacitive Networks. of California. Cohen. Research Memo (March). Boyle. Pederson." High Peiformance Systems 11 (March). K. Analogy. 1987. Degrauwe. and H. 1980. "Macromodeling of Integrated Circuit Operational Amplifiers.. and Y. J. "DIANA: Mixed Mode Simulator with a Hardware Description Language for Hierarchical Design of VLSI. Berkeley. et aI..." IEEE Transactions on Circuit Theory CT16 (August): 318323. G. W. H.REFERENCES 9 grade needed in SPICE to make such a large simulation a reality is the decoupling of the analysis of circuit blocks at the level of the differential or nonlinear equations." Univ." Proceedings Ext. Trick. et aI.
White.Vincentelli. Orlando.0. A. Fan." Proceedings of the IEEE 1990 CICCoBoston (May): paper 5. Nagel. CAD5 (October): 521535. CAD3 (October): 308331. W... Nagel. FL (June). SangiovanniVincentelli. Joy. Excluding Radiation (CANCER)." Univ. and D. SC6 (August): 166182. Pederson. R. Version 5. C. of California. 1990. CA. D. ERL Memo No. A.. McCalla. Berkeley. Nagel. Anaheim. and A. J. Gray. MicroSim. Brennan. and P. of California. SangiovanniVincentelli. Santa Clara. Harjani. H. "Development of an Analog Hardware Description Language. and A.. R. CA (November): 446449. K. Koh." IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. of California. Kerridge. "SPICE (Simulation Program with Integrated Circuit Emphasis). O. "Computer Analysis of Nonlinear Circuits. C." IEEE Journal of SolidState Circuits SC6 (August): 182188.. E. Campbell. Santa Clara. B. M. J. Idleman. 1971. 1973. L. E. "A Historical Review of Circuit Simulation. Y. A. "TIMEA Nonlinear DC and TimeDomain Circuit Simulation Program. ERL Memo No. 1991. Irvine. D. T. McCalla. S. SangiovanniVincentelli. S. PSpice.. Sangiovanni. 1975. . S. S." IEEE ICCAD Conference Proceedings. UCB/ERL M75/520 (May)." EDN (June): 168180.. and R. and A." Univ.. and L. 1. CA (November): 502505. 1984." RCA Review 32 (March): 4263. 1984. "Engineering the Future... E. Jr. R.. 1990. Autonetics Div. W. 1987." Keynote address at the 27th ACM/IEEE Design Automation Conference. R. J. E. Kleckner. "Automatic Synthesis of Operational Amplifiers Based on Analytic Circuit Models. Berkeley. "The Modified Nodal Approach to Network Analysis. Ho. R. Jenkins. and D. 1975. of California. Santa Clara. "SLICA Simulator for Linear Integrated Circuits. "Advanced MixedMode Simulation Techniques. Berkeley. Rohrer." IEEE ICCAD Conference Proceedings.. Johnson." IEEE Journal of SolidState Circuits. F. et aI. "SPICE2: A Computer Program to Simulate Semiconductor Circuits. ERL Memo No. D.. O. CA: Author. North American Rockwell Corp. 1978. "PCBased Analog Simulation." Univ. and A. Newton. L. HSPICE User's Guide. 1989." IEEE ICCAD Conference Proceedings. S. Newton. "The Simulation of Large Scale Integrated Circuits." IEEE Journal of SolidState Circuits SC6 (August): 188204.. "MOS Models and Circuit Simulation. 1991. 1971. Meyer. Kundert." IEEE Transactions on Circuits and Systems CAS22 (June): 504509. E. Kundert. A." Univ. UCB/ERL M78/52 (July). F..10 INTRODUCTION SPICETHE THIRD DECADE Hachtel. Kurker.. "RelaxationBased Electrical Simulation. 1988. "Simulation of Nonlinear Circuits in the Frequency Domain." IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. 0. ERL Memo No. L. 1968 (June). CA (November): 492495." IEEE Transactions on Circuits and Systems CAS31 (January): 103111. Rutenbar. Berkeley." Proceedings of the IEEE 69 (October): 12641280. Howard. H. K. Sequin. Jenkins. J. 1981. "BlAS3: A Program for the Nonlinear DC Analysis of Bipolar Transistor Circuits. G. R.4. and W. and P." IEEE Journal of SolidState Circuits SC6 (February): 1419. w. L. 1971. 1971. S. P. C. ERL M382 (April). G.1984. Ruehli." Technical Report issued by Harry Diamond Labs. MetaSoftware.. W. "An EnvelopeFollowing Method for the Efficient Transient Simulation of Switching Power and Filter Circuits. L. A. 1986. Circuit Analysis User's Guide. W. and S. W. 1990. "Transient Radiation Analysis by Computer Program (TRAC). Carley. "Analog Circuit Synthesis for Performance in OASYS. Pederson. "A Survey of ThirdGeneration Simulation Techniques. Pederson. et ai. UCB/ERL M84/48 (June). 1971. A. CA: Author.
. ERL Memo No. A. D. YaAg. Quarles. 1. "Modeling and Simulation of InsulatedGate FieldEffect Transistor Switching Circuits." Dept.. W. W.. 1983.. and A. W." IEEE ICCD '86 Conference Proceedings. 1969. J. Rye Brook. A. "Parallelizing Circuit SimulationA Combined Algorithmic and Specialized Hardware Approach." IEEE Transactions on Circuit Theory CT20: 628634. "Computation of DC Solutions for Bipolar Transistor Networks. ERL Memo No. Director. 1968. "SPICE Version 2G User's Guide. "SLATE: A Circuit Simulation Program with Latency Exploitation and Node Tearing." IEEE Transactions on Circuit Theory CT16 (November): 460466. D.. Shichman. "SPICE3 Version 3Cl User's Guide. ERL 'Memo No. 1980. of California. H. Vladimirescu.. Miami (June). Hodges. and A. T. White.." ProceedingsIEEE International Sympo~ium on Circuits and Systems. 1980. Zhang. E. . 1. L. of California. and A. H. K. and T. L. "An ActivityDirected Circuit Simulation Algorithm. Berkeley. L. Weiss. R.REFERENCES 11 Quarles. R. "LSI Circuit Simulation on Vector Computers. 11981. . Pederson. and S. Berkeley (August). Niraj. White. 1980. and S.. Santa Clara. W. Quassemzadeh. K. Liu. "Iterated Timing Analysis and SPLICE1. Newton. A.D." IEEE ICCC '80 Conference Proceedings. UCBIERL M89/46 (April). Berkeley. Rye Brook. Scott. Trick. R. 1987. of California. Jimenez..1973." In ICCAD '83 Digest. J. L. Univ. Newport Beach. Mehta. Danuwidjaja. W~eks. P. 1986. A. Berkeley. K." 24th ACM/IEEE DAC Conference Proceedings. Berkeley. E. Rye Brook." Univ. UCBIERL M89/42 (April). 1989b." Univ. of California. "The Simulation of MOS Integrated Circuits Using SPICE2. Vl~dimirescu. CA. Kleckner. D. of California.~ . N. Vladimirescu. R. ERL Memo No. "Algorithms for ASTAPA Network Analysis Program. T. Ng.. I. A. "Analysis of Performance and Convergence Issues for Circuit SimulIation. H. and T. UCBIERL M80/7 (February)." IEEE Journal of SolidState Circuits SC13 (October): 703707. Lass." IEEE ICCC '80 Conference Proceedings. NY (October): 10321035. "A ChargeOriented Model for MOS Transistor Capacitances. "A Vector Hardware Accelerator with Circuit Simulation Emphasis.rd. Sakallah. A." Univ. A. "RELAX2: A New Waveform Relaxation ~pproach for the Analysis of LSI MOS Circuits. 1982. and R. Newton. Mahoney. SangiovanniVincentelli." Univ. T.. G. NY (October)." IEEE Journal of SolidState Circuits SC3: 285289. 1978. Vladimirescu. SangiovanniVincentelli. 1983.. S. Dutton. O. and D. N. K. of Electrical Engineering and Computer :Science. Hajj. Saleh. 1. CA (May). Shichman. Wa. 1989a. A. C. UCBIERL M82/75 (October). NY (October) .
The nonlinear equations become integrodifferential 12 .ed/from Kirchhoff's voltage law. Only small circuits can be solved by hand calculations. and current law. described by linear branch voltagecurrent dependencies. Engineers learn in electronics courses to make certain approximations in order to predict the DC operation of small circuits by hand. and the'branch constitutive equations. requiring the solution of the nonlinear branch equations simultaneously with the equations based on Kirchhoff's laws. The analysis of circuits that contain elements described by a nonlinear relation between current and voltage adds another level of complexity. The easiest problem is that of finding the DC operating point of a linear circuit. For larger linear circuits the DC solution and especially the frequencydomain or timedomain solutions are very complex. BCE. which yield only approximate results. which requires one to solve a set of equations deriv. the exact DC solution is readily available through hand calculations.1 PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS Knowledge of the behavior of electrical circuits requires the simultaneous solution of a number of equations.One INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION 1. KCL. KVL. For a small circuit with linear elements. Another level of complexity is added when one has to predict the behavior in time or frequency of ~n electrical circuit.
with mean time between failures (MTBF) drastically improved over the previous generation. Generalpurpose computers. photomicrographic plates used at each step during fabrication to obtain the desired circuit equivalent in silicon are produced from the layout.PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS 13 equations. Another important factor contributing to the development of computer programs for the analysis of electrical circuits was the advance in digital computers that occurred in the same years. currently called ASX. KVL. ICs and powerful computers. The firstgeneration programs. such as SPICEl. the wafers are tested for correct operation. a hybrid technology using silicon semiconductor diodes and transistors and a precursor of monolithic ICs. The fabrication of ICs on silicon wafers was and still is an expensive process both in cost and time. with architectural innovations that preceded the principles of today's supercomputers. and ECAP II (Branin. initially named CANCER (Nagel and Rohrer 1971). For many years designers working with discrete components have used breadboards to analyze and test the behavior of electronic circuits. Advances in numerical techniques led in the late 1960s to the development of nonlinear analysis programs. This could be produced on a digital computer by means of an electricalanalysis or simulation program. Hogsett. 1973). and their scope was fairly limited. a process needs to be defined. The fabrication of an IC requires several stages: first. To this day there are designers who use this approach for building analog circuits. SPICE2 (Nagel 1971) and ASTAP (Weeks et al. for example. a transistor became the standard load device in an IC as opposed to a resistor on a breadboard. But the breadboarding approach became inadequate with the breakthrough of integratedcircuit fabrication and associated novel circuit techniques in the years 19641965. The efforts of two decades ago have crystallized in the two circuit simulators now most often used. Not only did transistors integrated on the same silicon chip behave differently from discrete transistors on a breadboard. Lunde. such as the IBM 360 series. A number of socalled third generation circuit simulation programs available today have their roots in the above secondgeneration nonlinear programs. The CDC 6400/6600 scientific computer was also introduced at that time. Programs intended for the electrical analysis of networks without taking any shortcuts in the solution of the KCL. These two technological factors. such as ECAP I in 1965 (IBM 1965) could only solve piecewise linear networks. which can be solved by hand only under such approximations as smallsignal approximation or other limiting restrictions. after which the electrical design is carried out and a circuit layout generated. and BCE equations are called circuit simulators. finally. This costly fabrication flow required a correct electrical design the first time through. defined both the need and the tool for automating the design process of electronic circuits. A number of researchers started studying the best techniques and algorithms for automating the prediction of the behavior of electric circuits (Pederson 1984). based on solidlogic technology (SLT). but so did circuit elements in ICs differ from their discrete equivalents. were introduced offering capabilities similar to those of presentday computers. A . and Kugel 1971). Since the electrical design engineer did not have the luxury of a trialanderror approach in silicon to verify the correctness of the design. a virtual breadboard was needed. and.
metaloxidesemiconductor field effect transistors (MOSFETs).1 and find the current flowing through the bias voltage source.14 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION detailed overview of the evolution of circuit simulation in general and SPICE in particular is presented in the Introduction. The best way to understand how SPICE works is to solve a circuit by hand. independent voltage and current sources. diodes. EXAMPLE 1. associated with the above three basic simulation modes. and the most common semiconductor devices. are available in SPICE. The program is equally suited to solve linear as well as nonlinear electrical circuits. and metalsemiconductor FETs (MESFETs). the amplitude of the excitation sources are assumed to be small compared to the thermal voltage (Vth = kT / q = 25. This is a largesignal analysis: no restriction is put on the amplitude of the input signal. bipolar junction transistors (BITs). this type of analysis requires the smallsignal assumption. Thus the nonlinear characteristics of semiconductor devices are taken into account. VBlAS' Use the source and resistor values given in the figure. can be simulated with equal accuracy by SPICE.T circuit shown in Figure 1. junction field effect transistors (JFETs).1 Calculate the node voltages in the resistive bridge. 1. They are described in Chaps. dependent voltage and current sources. that is. The DC analysis part of the program computes the bias point of the circuit with capacitors disconnected and inductors shortcircuited. transmission lines. TheAC analysis mode computes the complex values of the node voltages of a linear circuit as a function of the frequency of a sinusoidal signal applied at the input. Only under this assumption can the nonlinear circuit be replaced by its linearized equivalent around the DC bias point. nonlinearities are due mainly to the nonlinear currentvoltage (IV) characteristics of semiconductor devices. and BCE equations for a circuit and solves them. inductors. . 4 through 6. capacitors. or 80.8 mV at 27°C. KCL.6°F). Circuits for various applications. SPICE sets up and solves the circuit equations using the nodal equations (Dort 1989. As outlined above. Paul 1989) in the same manner as one writes the KVL. The transient analysis mode computes the voltage waveforms at each node of the circuit as a function of time. such as transistor circuits. Nilsson 1990. For nonlinear circuits. Circuits can contain resistors. More types of analysis. mutual inductors. SPICE uses iterations to solve the nonlinear network equations. and linear AC analysis. from switching power supplies to RAM cells and sense amplifiers.2 WHAT IS SPICE? SPICE is a generalpurpose circuitsimulation program for nonlinear DC. In the first example the DC solution of a linear resistive network is calculated by hand by an approach similar to the SPICE solution. nonlinear transient. it solves the network equations for the node voltages.
The analysis of a onetransistor amplifier.G4 V] + (G] + G2 + G3)V2 .1 and 1.••..~ . ~..G3 V2 + (G3 + G4)V3 whereG].._... to IR2: '.2V2 + OAV3 = 204 OAV2 . . ' In SPICE. the voltages at nodes 2 and 3 are found by writing the corresponding nodal equations: .2 mho. In Section 1.2 the results derived by hand in this example are compared with those obtained from SPICE.3.•.0. 1.2 0. or 12 V. .oj •••... 9). This is a system oftwo equations and two unknowns that can easily be solved for V2 and V3: = 1..2) . . is described in the following example.G2.••_..1 Bridge. The current through the bias source is equal . Eqs.1 mho and G3 = G4 = 0.2 are formulated from a graph of the circuit topology and are solved using Gaussian elimination (see Chap. The hand derivation offers some insight on how SPICE automates the solution of the bias point for a nonlinear circuit.G3.G3 V3 = = 0 0 (Ll) (1.WHAT IS SPICE? 15 5n R4 CD + VB/AS 10n R1 0 10n R2 5n R3 12V Figure 1..andG4aretheconductancesofresistorsR] throughR4: G] = G2 = 0.G] V] .' node 2 : node 3: . Solution The voltage at node 1 is equal to VB1AS..2V3 The solution is V2 = 8 V and V3 = 10 V. a nonlinear circuit.T circuit.
the bipolar transistor has a current gain f3F = 100 and a saturation currentIs = 1016 A. . VBE is valid only as > 0. Solution The bias point of the transistor is defined by the collector and base currents.3 and 1.4: the BCE that defines the currentvoltage relation between Ie and VBE: (1.3) The most commonly used relation for the bipolar transistor equates the collector current Ie to the base current IB: (1.4) which is derived from the BCEs of the transistor. 1. VBE and VBe.6) + 5V =vee Figure 1. Ie and IB.5 V and VBe <0V (1.5) One more equation is needed in addition to Eqs. The two sets of equations needed for this solution are KVL and the BCEs of the bipolar transistor. and the junction voltages.2 Onetransistor circuit.2 Find the operating point of the onetransistor circuit of Figure 1. that is.2. The KVL equation is RBIB + VBE = Vee (1.16 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION EXAMPLE 1. This approximation long as the transistor operates in the forward active region.
is presented in Chap. the above solution until all data agree.15 rnA The assumption for VBE should be verified in Eq. Ie. no one would ever go to that much trouble for hand calculations. Eq.15 . Re = 2 kil.5. The above example has described in a nutshell the iterative procedure used in SPICE to solve a nonlinear circuit.7 V 200 kO IB = = 0.6 based on the value of Ie and then refined. is trivial.0. In the next section the SPICE input file for this circuit is listed and is followed by the computer simulation and verification of the hand results.3) V = 2. 1. 1. 1. 3) are coded in SPICE. IB. 1. It is obvious that writing and solving by hand the KVL and BCE equations for a circuit with a few transistors is tedious. Then Ie follows from Eq.15 V and indeed it satisfies Eq. If.3 USER INTERACTION WITH SPICE AND THE COMPUTER This section describes the steps a user must follow for performing a SPICE analysis.7 V and replace it in Eq.USER INTERACTION WITH SPICE AND THE COMPUTER 17 At this point two linear equations and one nonlinear equation must be solved to find the values defining the operating point of the transistor. One more detail must be checked before the above solution can be accepted: VBe must satisfy the condition in Eq. For a description of this step. or model. and the complete set of equations and parameters of the SPICE BIT model are listed in Appendix A. 1. however.4: Ie = 100IB = 2. The basic information on BIT equations and parameters. the transistor is saturated and the two BCEs must be modified. start with the assumption that VBE = 0. First.0215 rnA .4 is no longer valid. repeating. or iterating. 3.31.6. guaranteeing correct analysis regardless of t?e operation region. 1. or converge.3 to yield the following value for IB: 5 . VBe = Rele . VBe is calculated from the KVL equation for the BC jl. 1. Obviously. To solve Eqs. 1.5 for forward linear operation. .4. namely. the type of information .lnction mesh.RBIB = (2. and VBE. The complete BCEs of a BIT (see Chap. On a computer. the SPICE input language. however. the circuit schematic must be cast in a format that can be understood by SPICE.
which are a blank.2. Sangiovanni. in for input. spi for SPICE. which can be . Examples include the Analog Workbench and Analog Artist from Cadence. and Design Center with PSpice from MicroSim. Most statements are a single line long.T circuit in Figure 1. the above naming convention is recommended: circuit~ame. and so on.suffix The user can create the file with the editor of choice. with the exception of the SPJQ2 (Quarles 1989) or PSpice (MicroSim 1991) extensions. Newton.Vincentelli 1981). the input file is customarily named with the name of the circuit followed by a suffix. In order to identify files easily. that is. but SPICE accepts multiline statements. the SPICE2 syntax (Vladimirescu. Zhang. the input files should be readable by a variety of SPICE versions. and the user is advised to consult the users' guide of the specific version for the extra features. several commands must be issued to the host computer to run the simulator. cir for a circuit.3. save the output in a file. . batch or interactive. The SPICE input language is free format and consists of a succession of statements.18 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION contained in the SPICE input file is examined in more detail by formulating the SPICE description for the bridge. Highend SPICE products support a schematiclevel specification. Although the SPICE input file can have any name. extra blanks are ignored.T circuit of Figure 1. an equal sign (=). Second. Pederson. Newer and proprietary versions of SPICE have additional functionality.3 Write the SPICE input for the bridge.1 Electric Circuit SpecificationThe SPICE Input Before running SPICE on any computer. 1.1 and the onetransistor circuit in Figure 1. The elements of the SPICE language can be introduced naturally by creating the SPICE decks for the bridge. As long as one uses the functionality described in this text.1 and the onetransistor amplifier in Figure 1. a continuation line must start with a + in the first column. and inspect the results graphically or in ASCII format. . or SPICE deck. EXAMPLE 1.T circuit in Figure 1.1 and the onetransistor amplifier of Figure 1. a user must create an ASCII file containing two kinds of information: the circuit description and the analysis requests. SpiceNet from Intusoft. . a comma. A most important common feature of the various SPICE versions is that all accept the basic SPICE input language. The two circuits from the previous section are used to acquaint the user with SPICE. ckt or . or a left or right parenthesis.2. AccuSim from Mentor. This file is referred to as the SPICE input file. A statement contains a number of fields separated by delimiter characters.2.
as shown below. 1. which must always conclude a circuit and analysis description. ckt. Some details on how to run a SPICE simulation are presented in the next section. with the name first followed by nodes and values. Vee. Control statements contain a period in the first column and define the types of analysis to be performed and the output variables to be stored. Another type of statement needed in a SPICE input file is the control statement.oP line is required. in order to describe the circuit in Figure 1.OP • END The above circuit description is saved in the file bridget. three nodes must be specified. • END. an . which identifies the circuit. to a text file. respectively. a .1 and 1. can be specified with the same format used in the above deck. Following the approach used above.2 into the format required by SPICE: one element per line. element name. This input description is also known as a SPICE deck from the time that punched cards were used. identifying the circuit as BRIDGET CIRCUIT.2 are set up internally in SPICE and solved as a linear system. BRIDGET CIRCUIT VEIAS 1 0 12 R1 1 2 10 R2 2 0 10 R3235 R4 1 3 5 * * . Instead of a single value. The circuit description consists of the element statements on lines 3 through 7. and emitter. and value. The resistors Re and RB and the voltage source. which is always the same. these are comment statements and are used to document the circuit description and analysis requests. and each element can be easily identified from Figure 1. Nodal equations identical to Eqs.2. which is used as input to SPICE. A number of lines start with an asterisk in the first column. and the. respectively. The circuit contains resistors. In order to verify the hand calculation of the bias point of the circuit. These two lines must always be the first and the last. The first character for a BJT is Q. Other lines in the SPICE input file are the title. such as a resistor. two comment lines. A new element not present in the BRIDGET CIRCUIT deck is the BJT. so the name is Ql.1. base. The circuit description is read by SPICE and compiled into an internal representation. Next consider the onetransistor circuit of Figure 1. that is. we transcribe the information from Figure 1. and must conclude with an end statement. for the collector. connectivity. a bipolar transistor. Therefore. which requests the DC operating point analysis.USER INTERACTION WITH SPICE AND THE COMPUTER 19 Solution Any SPICE input file must start with a title statement. and a voltage source. END line. starting with an asterisk in the first column. The SPICE specification is componentoriented.1 one needs to transfer the information in the figure.
Hence. 1 PF. The values of resistors Rc and RB in the above example.N= lE9. . a floatingpoint number in engineering notation. The model parameters for transistor QI. This name replaces the value field on a transistor line. We save the circuit in a file called bj t . U= lE6. a floatingpoint number.20 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION BJT is characterized by a number of parameters defined by a • MODEL statement. The circuit description consists of a number of element statements. Is. are specified in the global • MODEL statement for QMOD. 20MHZ is not 20 megahertz but 20 millihertz. the circuit nodes to which the element is connected. SPICE2.END ". MIL= 25. P = lE12.2) * 2 1 0 QMOD 2 3 1K 3 1 200K 3 0 5 QMOD NPN IS=lE16 BF=100 * . and 10HZ represent the same number. IF in SPICE is 1015 and not 1 farad. MEG = lE6.65E5.OP . the forward gain {3F. such as 3.14159. IMIL is not 0. K= lE3.input specification looks as listed below. and the saturation current. and 0 . such as 5 or 123. A number field can contain an integer. SPICE distinguishes between name fields and number fields. Ql through VCC in the above example. 10. A name field. lK and 20 OK. MEG. Each element statement contains the element name. 10. MA. Many users like to append the units to the number fields. Another common mistake is to confuse M.54 microns. are expressed in kiloohms using the scale factor K. assume that the name of the model that describes QI is QMOD. and MIL. G= lE9. 1. 4E6. ckt. The transistor is of type NPNand the SPICE parameter names for {3F and Is are BF and IS. respectively. the SPICE .MODEL * . for example.1 millimeter but 2.M= lE3. 103. andF = lE15. as in 10V. and PSpice are case insensitive. such as 1E16 or 2. or either an integer or a floatingpoint number followed by one of the following scale/actors recognized by SPICE: T= lEl2. or 1 OUM. and M. must start with a letter (AZ) followed by additional letters or numbers. MMHOS represent the same scale factor. a letter that immediately follows a scale factor or that immediately follows a number and is not a scale factor is ignored. These are all valid specifications as long as the physical unit is not confused with the scale factor. SPICE3. ONETRANSISTOR Q1 RC RB VCC CIRCUIT (FIG. such as or QMOD. MSEC. but some versions of SPICE for specific computers may require that the input file be uppercase. respectively. 10V. RB. In a number field. and the values of the parameters that Ql. 10VOLTS. After all the statements described so far are typed in an editor of choice.
. The general format of a •MODEL statement is «» • MODEL MODELname MODELtype PARAMl=valuel PARAM2=value2 . for missing value fields.. the saturation current. Alternatively.1. MODELname. as defined in Chaps. some elements. node2. and most commercial SPICE versions allow node names as well. From zero up to the maximum number of model parameters supported for a specific model type can be specified. and BF. The general format of an element Aname nodel node2 <node3 . The •MODEL statement belongs to a different category of statements. and those whose names are lowercase are number fields. one of the two MODELtypes supported in SPICE for BJTs. are characterized by several values. The model statement allows one to specify only once a set of parameters common to a number of elements. The fields enclosed in angle bracket are optional or need to be present depending on type. The following fields... The period in the first column differentiates global and control statements from element statements. > The first field always contains the name of the element. depending on context. Throughout this text. Model QMOD defines only two parameters.USER INTERACTION WITH SPICE AND THE COMPUTER 21 determine the electrical characteristics statement is of the element. <node3 . such as transistors. which are grouped on a separate line. such as R for resistor. Each of PARAMl. IS. SPICE2 restricts the name to eight characters. fields whose names are uppercase or start with an uppercase character are name fields. called the model statement.. these elements reference the name of the model definition that contains the parameters. the parameters of all transistors with the same geometry integrated on one silicon chip.. Instead of referencing a value field. Except for the first letter.. the forward current gain. must be one of the accepted keywords for the model type. PARAM2. respectively.. A comprehensive list of all conventions used in this text can be found in Section 2. and V for voltage source. SPICE3 and PSpice do not. The name of the model that defines the parameters of QI in the example is QMOD. >. and MODELtype is one of the seven or eleven types of models supported by SPICE2 or SPICE3.. they represent the node numbers at which the element is connected.. the global statements. the rest of the element name can contain both characters and numbers. nodel.. SPICE2 accepts only numbers fornodes. Transistor QI in Example 1. Q for BJT. for example. .3 is an NPN transistor. PSpice. For each MODELname referenced. for QI in the onetransistor circuit. This number field is shown as optional because SPICE provides defaults such as 0 or 1. Bold characters are used in this book to identify key words and parameter names that are part of the SPICE language. MODELname uniquely identifies one set of parameters common to one or more elements. the circuit specification must contain a •MODEL statement. whereas SPICE3. which must start with the letter that identifies the element type. 2 and 3 and Appendix A. are lowercase to identify them as number fields. Note that either a value or a model name should end an element line. Each element must be characterized by at least one valuel. ><MODELname><valuel .
< and>. EXAMPLE 1. are characterized by both device parameters.1 and 1. every SPICE input file has the following general structure: Title statement * Comment statements Element statements Global statements Control statements . The redirection signs.ckt > bjt. complex elements. Upon completion of the simulation. and model parameters. DC Analysis The next step is to run the simulation. out and bj t.2. Thus an element that references a •MODEL statement may require some values that are specific to it. such as transistors. bridget. or printing it. out can be inspected by having it typed on the screen.4 Print the result files bridget.3.3 can be accomplished in UNIX by typing % spice2 < bjt. All control statements start with a dot in the first column. The simulation of bridget. W. out and bj t. grouped in the •MODEL statement.3 the DC bias point is requested by the • OP line. END (end statement) 1. out and compare the results with the hand calculations of Examples 1. SPICE2 is available on a variety of computers and operating systems worldwide. Therefore. The last category of statements necessary in a SPICE deck is the control statement.out assuming that the executable program is called spice2 and that it is located in a directory that is in the search path of the user. the different channel widths. defined on the element line. L. In Example 1.2 SPICE Simulation. viewing itthrough an editor. 4 through 6 describe in detail all control statements. of MOSFETs are defined in element statements.22 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION MOSFETs of different geometric sizes can be characterized by the same model parameters. define the file where the input data reside and the file where the results are stored. ckt or bj t . In summary. it is presently available on a variety of computers ranging from the Personal Computer to the Cray. and lengths. and this section does not enumerate all possibilities but is limited to the computers most often used by students and professionals. UNIX is the operating system of choice in universities. For example. . ckt created in Example 1. such as threshold voltage and thinoxide thickness. Chaps. Control statements specify the analyses to be performed by SPICE as well as define initial states. respectively.
and the solution can be verified to be identical to the.6 BRIDGET CIRCUIT CIRCUIT DESCRIPTION ********* **** *************************************************************************** VBIAS 1 0 12 R1 1 2 10 R2 2 0 10 R3 2 3 5 * R4 1 3 5 * . out produced by SPICE2 is listed in Figure 1. Many errors can be identified by carefully comparing the circuit description output by SPICE with the original s. It is important to note that SPICE2 and PSpice always echo back the circuit description received.000E01 9. The SPICE2 output contains several sections. First. 9/21/84 ********* 06:47:36 ******* 03/19/91 ********* SPICE2G.hand calculation.4.3.6 BRIDGET CIRCUIT 9/21/84 ********* 06:47:36 ******** **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.0000 NODE VOLTAGE SOURCE CURRENTS CURRENT 8. 60E+00 WATTS TOTAL POWER DISSIPATION Figure 1.0000 NODE 2) VOLTAGE 8.3 SPICE2 results for DC operating point. The contents of bj t.OP .000 DEG C *************************************************************************** NODE 1) VOLTAGE NAME VBIAS VOLTAGE 12. the CIRCUIT DESCRIPTION is echoed so that the user can check for potential errors. Next.chematic. the BJT MODEL PARAMETERS defined in a . Solution The output bridget. out are shown in Figure 1.END ******* 03/19/91 ********* SPICE 2G.MODEL " . .0000 NODE 3) VOLTAGE 10.USER INTERACTION WITH SPICE AND THE COMPUTER 23 .
7 V in the hand calculations. 1. According to these values. the voltages. VBE. 1. The node voltages listed as part of the SMALL SIGNAL BIAS SOLUTION agree with the ones obtained through hand calculations in Example 1. and the TOTAL POWER DISSIPATION are also listed in this section. and VCE. statement are printed.MODEL QMOD NPN . it continues to iterate until Eqs. . 00E16 BF 100 NFl BR 1 NR 1 Figure 1. VBC. out: DC analysis results.2) 9/21/84 ******* 23:07:40 ********* ONETRANSISTOR **** BJT MODEL PARAMETERS *************************************************************************** QMOD NPN IS 1. defines the region of operation.3. 1.6 are satisfied. and 1.2.4. QI is ******* 03/25/91 ******* CIRCUIT SPICE 2G. in this case the source Vcc. The difference.OP • END * * ******* 03/25/91 ******* CIRCUIT SPICE 2G. power consumption. The OPERATING POINT INFORMATION of transistor QI.6 (FIG. Ic. 1. The VOLTAGE SOURCE CURRENTS.24 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION . Although SPICE2 computes a first solution with a similar assumption.2) 9/21/84 ******* 23:07:40 ************ ONETRANSISTOR **** CIRCUIT DESCRIPTION *************************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * * . of the order of tens of millivolts. Finally.4 File bj t . and smallsignal characteristics computed by SPICE2 are listed. consisting of IB.6 (FIG. is due to the assumption that VBE = 0.
OOE+OO 1.6 (FIG.OOE+OO O.000 DEG C *************************************************************************** NODE 1) VOLTAGE NAME VCC VOLTAGE . 1.4 .000 8.2) __.USER INTERACTION WITH SPICE AND THE COMPUTER 25 ******* 03/25/9. ******* CIRCUIT SPICE 2G. 1.6 WATTS 9/21/84 TOTAL POWER DISSIPATION ******* 03/25/91 ******* ******* 23:07:40 ********* ONETRANSISTOR CIRCUIT _(FIG.10E03 0.8967 SOURCE CURRENTS CURRENT 2.23E+03 O.793 2.06E02 SPICE 2G.100 2.13E02 1.000 1.OOE+OO O.OOE+OO 100. 00E+12 O.10E05 2.OOE+OO O.000 **** OPERATING DEG C *************************************************************************** **** NAME MODEL IB BIPOLAR JUNCTION TRANSISTORS Q1 QMOD 2.124E03 1. 29E+18 (continued) IC VBE I VBC VCE BETADC GM RPI RX RO CBE CBC CBX CJS BETAAC FT Figure 1.0000 NODE VOLTAGE 2) 2. 9/2.1/84 ******* 23:07:40 ************ ONETRANSISTOR **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.7934 NODE VOLTAGE NODE 3) VOLTAGE 5.2) POINT INFORMATION TEMPERATURE = 27.900 100.
SPICE3 can also be run in batch mode through the command % spice3 b bjt. op. the results of various analyses can be either viewed graphically on the screen or printed out. is computed that takes into account the Ie and 18 for each transistor. The results of the different runs have been saved in temporary files. is interactive. however. namely. The resulting information listed on the screen is much more verbose. ckt. runs the DC operating point. which are displayed before the program exits. and in release 3d2 this information can be accessed only on a devicebydevice basis by using the show ql command. Figure 1. each command is followed by the results displayed on the screen by the program. SPICE3. listing. BETADC.26 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION biased in the forward active region. Input files can be edited and repeated simulations can be performed from within the SPICE3 shell. running the simulation. The rest of the data represent the values of the elements in the linear equivalent model of the transistor and are described in more detail in Chap. lists the input file for verification. When you have finished. The above examples are intended to show a new user of computer simulation how natural the SPICE input language is and how straightforward is the output information provided by the program for a simple DC analysis. type quit to exit SPICE3. source. The first command. the previous steps must be repeated. as predicted by hand calculations. that is. At this point the user needs a few additional commands not available in SPICE2 in order to communicate with the program. the second. If a circuit element must be changed or an output request has been omitted. Note that the print command does not provide the OPERATING POINT INFORMATION of SPICE2. the same information found under the SMALL SIGNAL BIAS SOLUTION header in SPICE2.5 is the transcript of an interactive SPICE3 session of the same simulation as performed above for bj t. SPICE3 saves all node voltages of all simulations performed during the same SPICE3 session and provides for the interactive display of selected waveforms while the simulation is running. SPICE2 is a batch program. and the fourth. 3. as well as the best approaches for using SPICE to solve electrical circuits. A value of {3F. In this and the following chapters all supported elements and analysis modes are described. editing the input file. print all. and the user has a last chance to save any desired results. lists all node voltages and currents through voltage sources. the third. and viewing the output file.ckt > bjt. While one circuit is active. For larger circuits it is useful to display all available output variables. As can be seen. and the user is transferred inside a spice shell upon invocation of the program: Spice 1 > SPICE3 commands must be entered at the prompt. but print or plot only selected ones.out . defines the input file.
Although SPICE2 is not available from DC Berkeley for the PC. Some packages offer DOS shells. ~~ .r flag is used.__ _ _~ __ . ckt.2) .ckt Circuit: ONETRANSISTOR CIRCUIT (FIG. the display data are stored in a file called rawspice. _ . raw. This is a sarrplenew.•. ..••. running SPICE. SPICE3 also produces a raw/tie containing data to be displayed graphically when the . SPICE3 is distributed by DC Berkeley for the PC.934384eOl v(2) = 2. and HSPICE from Meta Software.!il~_~stYJ.896719e+OO v(3) = 5.iJJ .••_ •. IsSpice from Intusoft.3d2 done Figure 1.. a number of commercial offerings.••.b~_P. 1. • The most common platform for running SPICE has becomy the IBM PC and PC clones. and .2) Spice 2 > listing ONETRANSISTOR CIRCUIT (FIG. the models supported range from the AT to the 486.•••••. out contains information similar to but in a different format from what is produced by SPICE2. 1.model qrnodnpn is=le16 bf=100 15 .. ..USER INTERACTION WITH SPICE ANDTHE COMPUTER 27 . which facilitate the simulation sequence of creating or modifying the input circuit.2) 1 : onetransistor circuit (fig. 1.2) 3 ql'2 1 0 qrnod'" . operating point Are you sure you want to quit (yes)? yes Spice. the command to simulate may differ from package to package. Although the sequence of operations remains the same._w_.••• ~_ •. 1.5 Transcriptof interactiveSPICE3 analysi'sof bj t .r::!pt~~ whenever spice or nutmeg is started. such as PSpice from MicroSim.end Spice 3 > op Spice 4 > print all v(l) = 7.~"'. The companion postprocessor for the SPICE3 rawfiles is called Nutmeg.'•• .. .s .•_ .12431e03 Spice 7 > quit Warning: the following plot hasn't been saved: op2 ONETRANSISTOR CIRCUIT (FIG. __ " ro ••_ n. At completion bj t . 4 rc 2 3 lk 5 rb 1 3 200k 6 vcc 3 0 5 9 .." ._ Spice 1 > source bjt. run under DOS or Windows. If no filename is specified.000000e+OO vcc#branch = 2.
input and output units. SPICE3 and Nutmeg can be run similarly on a Pc. INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION '*' viewing the results. The name of the output file must not be specified unless a different suffix than . and then runs Nutmeg on the result file RAWSPICE.3 SPICE Results for AC and TRAN Analyses So far we have learned how to write a SPICE circuit file. When one runs PSpice from DOS. SPICE3 is run in batch mode.. (The two commands can be saved in a . and how to interpret the results of a DC analysis in the output file. Although in Windowsbased packages most operations can be performed from menus. then Nutmeg is run to view the results. Job control statements define the user identification. 1.CKT BJT. When the input file is ready. BAT. Although not as common as on the PC. such as IBM. OUT as saved by PSPICE is similar in format to that saved by SPICE2. BAT file. and Cray. for several computers and operating systems. SPICE3 transfers to its shell.. the input and output file names follow the program name as command arguments: C > PSPICE BJT. and the program to be run. computer resources. Both SPICE2 and SPICE3 are distributed by the University of California. The schematic capture available in the Design Center from Mi. it is still useful to follow filenaming conventions similar to those introduced above for circuit identification. RAW created by BSPICE..sm. the name of batch SPICE3 on a PC.) More on displaying results is presented in the following two sections. • OP. the same steps as in UNIX must be followed for simulating circuits. time limit. SPICE2 and SPICE3 run in batch mode on a variety of mainframe computers.OUT The output file from PSpice is of the same format and contains the same information as that from SPICE2. SPICE is also available on the Apple Macintosh. SPICE3 . what types of statements are available. has . Note that BJT . Only one control statement. the jobs submitted to such computers contain job control statements in addition to the SPICE circuit description.28 . Berkeley. CDC. PSpice and IsSpice are offered on the Macintosh. type $ run spice SPICE2 will prompt for an input file and then for an output file. Typically. from Deutsch Engineering. The Electronics Research Laboratory at UC Berkeley tells where users can get a copy of SPICE for a specific mainframe computer. where the same commands as in UNIX are valid.~e.£oSim and SpiceNet frQillTutusoftallow the circuit specificati~entered grap!!'[ ically rather than through the. as is MacSpice. OUT is desired. how to run the analysis on the most common computers.3. which runs BSPICE. For the VMS operating system on DEC computers. which is specifically tailored for the Macintosh interface. First.
Of postprocessing programs.j16 '= jO. this was sufficient for obtaining all computed node voltages in the output files. 10 3 (1. V2 and V3.103 0. 1/ I + l/iwC1 III = 0. In addition to a DC analysis.) l . SPICE also performs a steadystate sinusoidal analysis.5 Compute the node voltages and the current for the series RLC circuit shown in Figure 1.out. Solution First. But as the circuits grow. Vin = 5 cos 27T1Ot Write the SPICE deck and run the program to . Forsmall circuits such as the ones in Examples 1. more generally. out and bj t .2. or AC. The crihent is ".2. The interpretation of the results of SPICE simulations is best understood if exernc plified for typical applications. The following example introduces the SPICE frequency.31 . due to the fact that each node voltage is computed for all frequencies or times. analysis and how to display the results as a Bode plot. various versions of SPICE have additional control lines or interactive commands that let the user access results that have been saved in binary files and display them in graphical mode with the help. V3. this may not bea problem. the resistanceR1 and the inductorreactancewL1 can be neglected compared to the reactance of the capacitor. Thus the • PRINT and • PLOT control statements define the node voltages of interest or.verify the results derived from hand calculation.6 assuming the following periodic input signal: . vary the frequency of the input signal Vi~ from 1 Hz to 10 kHz and obtain the Bode plot of the magnitud~ and the phase of the voltage across the capacitor C1. the desired output variables . bridget.1 and 1. so will the size of the output files. TRAN line. LI = 90° Z R1 = Vin = Vin 5'. Then. closely follow the input signal: . invoked by the . 7) The voltages at nodes 2 and 3. EXAMPLE 1.31 rnA. w C 1. invoked by the.ANDTHE COMPUTER 29 been introduced so far. the solution for the network is obtained using phasor calculations. making the results of interest more difficult to find.• PRINT and • PLOT define only the results saved in the output file. and a timedomain analysis.USER INTERACTION WITH sPICE. In calculating the current. These analyses result in large amounts of data.AC control line.
is necessary if the user wants the results of the analysis to be written into the output file. therefore. ckt. which in this case are the same.143E04 9. 1. AC voltages and currents are phasor quantities and can be expressed in terms of either real and imaginary parts.30 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION o . Unlike the case of the DC operating point analysis.000E+00 7. rIc. PRINT keyword must be followed by the type of analysis.125 Cl 3 0 10 R1 1 2 200 . LIN. and the starting and ending frequencies. For AC variables the character V (for voltage) or I (for current) must be followed by one or more additional characters specifying whether polar or rectangular values are desired. as in VR (2 ) and VI (2 ) . the number of frequencies. for the other analyses the user must specify which data are to be saved in the output file. a current requested on a • PRINT line must always have as argument a voltage source name.072E+01 5. SERIES RLC CIRCUIT VIN 1 0 AC 5 0 L1 2 3 0. including SPICE2 and SPICE3. • PRINT. AC in this case. only the currents flowing through voltage sources can be measured. The SPICE deck for this circuit. • OP. and circuit variables to be saved in the output file.PRINT AC 1M (VIN) IP(VIN) VM(2) VP(2) VM(3) VP(3) • END * Two new control statements are used. The . is based on the previous examples.000E+01 3. as in VM( 2) and VP ( 2 ) . 5 and 4. •AC and • PRINT. The first statement represents a request for a steadystate frequencydomain analysis and defines the type of frequency variation. In most SPICE versions. respectively. These two statements are described in detail in Chaps. or a magnitude and a phase.125mH Figure 1. The following results are computed by SPICE for the desired phasors at 10Hz: FREQ 1M (VIN) IP(VIN) VM(2) VP(2) VM(3) VP(3) 1.002E+00 7.203E01 5.203E01 . 10Hz.6 Series RLC circuit.AC LIN 1 10 10 . The second statement. where SPICE automatically prints the results in the output file.
USER INTERACTION WITH SPICE AND THE COMPUTER 31 If the amplitude of the input signal were 1 V. because it provides an even number of analysis points in all ranges. and the output request line. In addition to the.6 3/15/83 ******** 19:45:56 ******** **** TEMPERATURE = 27. The only two statements that need to be changed are the. The next part of this example is to obtain the Bode plot of the magnitude and phase of the voltage across the capacitor for the frequency range from 1 Hz to 10 kHz. PRINT capability. 0 ******* 09/08/92 SERIES RLC CIRCUIT AC ANALYSIS ******** SPICE 2G. ACstatement. and the phase changes by 180 because of the two complex poles (see also Chap. au t. rIc. SPICE offers two choices of logarithmic intervals. the voltage at each node computed by SPICE would represent the transfer function at that node referred to the input.7 SPICE2 ASCII plot of VDB (3) and VP (3) . to reflect the desired frequency range. OCT. The phase of the current. SPICE supports a • PLOT command.AC line is . 6). shown in Figure 1. The new .AC DEC 10 1 10K This statement requests an AC solution of the RLC circuit at 10 frequencies per decade in the interval from 1 Hz to 10kHz.7. The amplitude peaks at 450 Hz.PLOT AC VDB(3) VP(3) Note that the magnitude ofthe voltage is requested in decibels as specified by the suffix DB.000 DEG C *********************************************************************** LEGEND: *: VDB(3) +: VP(3) Figure 1. . which produces an ASCII character. We also change the amplitude of Vin to 1 V in order to obtain the transfer function V3/ Vin' For the frequency variation a logarithmic scale is desirable.The most commonly used frequency interval is the decade. The resulting Bode plot. plot. The new •AC line and the above • PLOT line should replace the existing •AC and • PRINT lines in the SPICE input file rlc. and we will use it for obtaining the Bode plot. is negative because the direction of flow is assumed in SPICE to be from the positive to the negative terminal through the voltage source. or lineprinter. is taken from the SPICE output file. the decade. DEC.ckt. the resonant frequency of the circuit. For the desired Bode plot the requesting statement is . I P (VIN) . and the octave. The information entered on the • PLOT line is identical to that entered on a • PRINT line.
.
out Before a rawfile created by SPICE2 can be opened in Nutmeg.8. I( SPICE3 is used for simulation. on the command line: spice2 r rlc_sp2.8 Nutmeg.USER INTERACTION WITH SPICEAND THE COMPUTER 33 There are ways to obtain SPICE plots with highquality graphics on a computer screen or printer. as shown in Section 1. the sconvert utility must be run.raw a rlc_sp3.2. The rawfile created by SPICE3 can be assigned any name with the r filename option on the command line. . 20  VDB(3) VP(3) .ckt > rlc. SPICE 2G6 and SPICE3.3. as in the following: spice3 b r rlc..r f i 1ename.raw rlc. PLOT commands of SPICE2 and most other commercial SPICE programs.ro o 20 eO e1 e2 e3 e4 Figure 1.raw The Bode plot of the capacitor voltage magnitude and phase produced by Nutmeg from a SPICE2 rawfile is shown in Figure 1. If SPICE3 is run in batch mode. the plot of any desired circuit variable can be obtained while running the program interactively from the spice3 shell.raw < rlc. the graphic postprocessor is Nutmeg. For the UC Berkeley releases.ckt > rlc. raw. Bode plot ofVDB (3) and VP (3) from . which can then be directly loaded and viewed in Nutmeg.out Note that SPICE3 does not support the • PRINT and. which translates the file to the SPICE3/Nutmeg raw file format: sconvert 0 rlccsp2. it creates by default a binary result file called rawfile. SPICE2 plots can be viewed or printed in Nutmeg on a UNIX system by setting the rawfile option.
the control line • THAN must be included. a control statement. EGA. Besides using the regular output file. a few headers are added.2M 50M . timedomain.PRINT TRAN V(3) V(l) • END * The first difference from the input file used in the AC analysis is found on the VIN line: the two nodes are followed by the keyword PWL.125 C1 3 0 lU R1 1 2 50 . The tabular output created by the SPICE2 • PRINT command can be used as input to xgraph. CGA. a pulse with the defined characteristics must be assigned to the voltage source VIN. and the results can then be viewed or printed in the xgraph tool. consult the manual page of xgraph for the details.TRAN . best takes advantage of PC graphics. analysis. Commercial PC SPICE packages offer postprocessing for all popular PC graphics.01M L1 2 3 0. The rest of this section is dedicated to introducing the third major analysis mode of SPICE. The complete SPICE deck for the transient analysis is listed below. and Hercules. The following example describes how to obtain the SPICE timedomain solution for the above RLC circuit.34 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION Another graphics package available on UNIX machines that run XWindows is xgraph. the user can view the results of the simulation in graphic mode. The data produced by the • PRINT command are extracted from the SPICE output file.. VGA. On Macintosh computers tabular output created by the • PRINT command on a Macintosh or another computer can be viewed and printed using plotting programs such as Cricket Graph or Kaleidograph. which identifies a piecewise linear . which defines the time interval for the analysis. In order to generate the graphics file PROBE. which can display and perform arithmetic operations on waveforms. the postprocessor for IsSpice. SERIES RLC CIRCUIT 0 VIN 1 0 PWL 0 0 10N 5 25M 5 25. or transient. First. EXAMPLE 1. Use R] = 500. DAT. • PROBE. MicroSim offers Probe. Find the waveform of V3(t) between 0 and 50 ms.6 Use SPICE to compute the timedomain response of the series RLC circuit of Figure 1.6 to a pulse with an amplitude of 5 V applied at the input at time 0 for 25 ms. Second. must be added to the PSpice input file. IntuScope. Solution Two new items must be introduced in the SPICE deck of the RLC circuit in order to perform a transient analysis. including SVGA.
0000 Time.9. Note that both the AC and transient analyses can be made part of a single SPICE run by the addition of the PWL specification to the AC characteristics on the VIN line and the inclusion of the •AC and • TRAN lines together with the relevant output request lines in the same input file.9 xgraph plot of transient waveform V ( 3 ) . Two waveforms are requested. TRAN.2.0000 30.00 <Ii ~ E a. TRAN line is used only for result output purposes. and the starting time. complete information on independent sources is in Section 2. The • TRAN control line contains three values: the time step.00 2. which produces the plot of Figure 1.00 4. and V ( 3 ) . Rle 8. V ( 1 ) . This behavior corresponds to the peaked frequency characteristic displayed by the circuit. If PSpice is used for this analysis and the line • PROBE is included in the deck.7 and 1. SPICE uses an internally adjusted. see Figures 1.00 0. is also present in the deck.00 V(1) V(3) > "0 4.0000 20. ms Figure 1.8. which takes almost the entire pulse width to settle. The voltage across capacitor C1 displays an overshoot.0000 10.0000 40.00 2. The values following the keyword represent pairs of timevoltage values. variable time step for solving the circuit equations (see also Chaps. the voltage across the capacitor. which is the interval at which values are printed or plotted by a • PRINT or . 6. Other waveform functions can be generated by a source. 6 and 9).6.0000 50.10. All the details on specifying a timedomain analysis can be found in Chap. the final time. upon completion of the SPICE run the user is transferred into the Probe program. the input. « 0. PLOT command. the value on the. The tabular output saved in r 1 C • au t is used in this case as input for xgraph.USER INTERACTION WITH SPICEAND THE COMPUTER 35 function generated by the input source.00 6. which enables the results to be viewed on the screen or a hardcopy to be produced as shown in Figure 1. A • PRINT statement followed by an analysis type. .
> . For uniformity. Alternatives for obtaining graphs of the results have been presented. The main analysis modes of SPICE as well as how to display the results of the analyses have been covered in this section. The solution process of SPICE was linked to the knowledge of electric circuits necessary for using the simulation.. 1. the plots in the rest of the book are produced using the Oscilloscope and Network Analyzer tools of the Analog Workbench because of their superior graphic quality.. You should be able to write a SPICE input deck for a simple linear circuit. run the basic analyses. the list of graphics packages available on computers.36 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION RLC Daterrime 10 run: 09/16/92 16:43:41 Temperature: 27. which defines the parameters for a number of elements: • MODEL MODELname MODELtype <PARAM1=valuel PARAM2=value2 .4 SUMMARY This chapter introduced the basic capabilities of the electrical simulation program SPICE. « 0 5 o 10 20 Time. <MODELname> <value> Associated with complex elements.. and personal computers is intended not to be complete but only to exemplify an approach for obtaining highquality plots from SPICE • PRINT data. such as transistors.10 Probe plot of transient waveform V ( 3 ) . and save the results in a output file or create a plot. All the elements used so far can be specified in SPICE according to the following format: Aname nodel node2 <node3> . ms 30 40 50 o v(3) Figure 1. is the global statement • MODEL. engineering workstations..0 > "C 5 ai E :E c.
E. 1971. of Electrical Engineering and Computer Science. O. New York: McGrawHill. 1989. J. O. Dept. [l620EE02X] User's Manual. SPICE2: A computer program to simulate semiconductor circuits. R. such as Nutmeg. SPICE results are requested with the following control statements: • PRINT ANALYSIS OULvarI OUT_var2 . 1991. Berkeley. The plots in the following chapters of this book are all created using the display tools of the Analog Workbench. or timedomain analysis. W. F. .. Mehta. ' Quarles. IEEE Transactions on Circuit Theory CT20 (November): 620634. Berkeley. D. T. Hogsett. respectively. Nilsson. L. Introduction to Electric Circuits. K. Zhang. MA: AddisonWesley. A. 1990. excluding radiation (CANCER). of California. L. and T. Pederson. R. PSpice: Circuit Analysis Users Guide Version 5. TRAN TSTEP TSTOP <TSTART> for performing a DC. Examples of several plotting tools were presented. . Irvine. R. Electric Circuits. SPICE version 2G user's guide. Lunde. REFERENCES Branin. C. 1971. A. L. The general structure of SPICE deck is shown on page 22. Computer analysis of nonlinear circuits. Newton. . 1984.. R. of California. IEEE Journal of SolidState Circuits SC6 (August): 166182. Mahoney. MicroSim. of California. Vladimirescu. Quassenizadeh. Pederson. 1973. . 1981 (August). and L. ECAP IIA new electronic circuit analysis program. SangiovanniVincentelli. H. • PLOT ANALYSIS OULvarI OUT_var2 .op • AC INTERVAL numpts fstart fstop . A historical review of circuit simulation. IEEE Transactions on Circuits and Systems CAS31 (January): 103111. Reading. Univ.REFERENCES 37 The following analysis control statements are defined: . W. Algorithms for ASTAPA network analysis program. 1989. IBM. and Probe. SPICE3 version 3Cl user's guide. IEEE Journal of SolidState Circuits SC6 (August): 146165. ERL Memo UCBIERL M75/520 (May).0. Berkeley. all SPICE circuit descriptions must start with a title line and end with an • END line. Nagel. R. D. 1989. A.. 1975.. G. New York: John Wiley & Sons. L. D. CA: Author. 1965. A. Scott. Rohrer. H. 1620 electronic circuit analysis program [ECAP]. . UCBIERL Memo M89/46 (April). Weeks. W. Dorf. G. Univ. R. Jimeniz. and A. L. frequencydomain. Analysis of Linear Circuits. and R. J. xgraph. Univ. C. Paul. T. Kugel. IBM Application Program File H2001701. Nagel. 3d ed.
The circuit nodes need not be numbered sequentially. Sec: G 38 . Model statements are necessary for defining the parameters of complex elements. common to all SPICE versions. Zhang. these model types. The circuit nodes must always be positive integers in SPICE2 or positive integers and names in SPICE3. Every node in the circuit must have at least two elements connected to it. the values of the defined element.'and semiconductor devices. 1. Pederson. A circuit must always contain a ground node. multiterminanlemenfs. NODES. An element statement contains connectivity information and. Quarles. MODELS. and the nodes of unterminated transmission lines. Pederson. presented in 2. 2. which has internal connections to the drain and to the source. SPICE3 and PSpice. have extended model support to most elements. and PSpice (MicroSim 1991) circuit definitions. 3.3. are described in Chap. The following conventions must be observed in the SPICE2 (Vladimirescu. 3.Vincentelli 1981). SPICE elements areclassified in threecategories:. but not all implement the newer element types of SPICE3.3.2.1~ ELEMENTS.two::tertniiial elements. and Sangiovanni.Two CIRCUIT ELEMENT AND NETWORK DESCRIPTION 2. presented in Chap. and SangiovanniVincentelli 1991).1. Newton. Every element type accepted by SPICE2 and SPICE3 is presented in this and the following chapter. All commercial SPICE versions support the elements available in SPICE2. SPICE3 (Johnson. described in Sec. AND CONVENTIONS Element statements and model statements represent the core of the circuit description. SPICE2 supports models only for semiconductor devices. which must always be number O. however. as shown in Sec. Newton. either explicitly or by reference to a model name. the only exceptions are the substrate node in MOSFETs.
Ruehli. see Chap. in uppercase. Uppercase versus lowercase in SPICE statement definitions: • Variables in uppercase or starting with uppercase in statement definitions denote a character field. In DC. Boldface monotype is used for: • Command names. Monotype is used for: • Computer (program) input and output • References made in the text to names. and optional keywords or values appear between angle brackets. The following description summarizes the conventions for different typesets. McCalla 1988. the value may be denoted by the same characters as the name. This requirement prevents the occurrence of floating nodes. KCL. Any violation of the above restrictions results in an error message and termination of the SPICE program. and Brennan 1975. The IV . the same type is used whether these keywords appear in a statement definition or are referred to in the text 3. but italic type 2. Because SPICE2 uses modified nodal analysis (Ho. < >.TWOTERMINAL ELEMENTS 39 Every node in the circuit must have a DC path to ground. two restrictions must be observed: the circuit cannot contain a loop of voltage sources or inductors. Several conventions are observed in the following sections in the presentation of element statements. and characters that are keywords for the program. parameter names. and the latter due to Kirchhoff's current law. and it cannot contain a cutset of current sources or capacitors. titles. for which the program cannot find a bias point. 1. model and analysis types. 9) to solve for both node voltages and currents of voltagedefined elements. tc2 • Exception: when a parameter name is followed by its value. capacitors represent open circuits and inductors represent shorts. KVL. or variables appearing in a computer input or output 2. The former is disallowed due to Kirchhoff's voltage law. In the statement format definition the characters or keywords that must be present in an actual statement are boldface. The possible error messages and corrective actions are described in Appendix B.2 TWOTERMINAL ELEMENTS This section describes both the syntax and the branchconstitutive equations (BCEs) of all twoterminal elements except the semiconductor diode. The semiconductor diode is presented together with multiterminal semiconductor devices in Chap 3. for example the parameter name is L and the variable is L • Highlighting new concepts 4. such as MODELname • Variables in lowercase denote a numeric field in a statement as in TC= tel. Italic type is used for: • Variable names (subscripted characters as well) • Names of fields in SPICE statement definitions • Reference to the value of a program parameter with the same name. such as voltage sources and inductors.
nonlinear magnetic cores. as shown in Figure 2. SPICE supports the following twoterminal elements: Resistors (linear) Capacitors (linear and nonlinear) Inductors (linear and nonlinear) Independent Independent voltage sources (linear) current sources (linear) analytic equations. except the diode. are described by simple BCEs. inductors. and have no associated model statements. is negative. SPICE3 supports the following model types introduced in this chapter: R C URC SW CSW Diffused resistor model Diffused capacitor model Uniformly distributed RC model Voltagecontrolled Currentcontrolled switch model switch model JCSpice also supports modeLstatem.ents for resistors. 2. and switches for all elements except for sources. is positive. The branch voltage across any element is computed as Ve1em = Vnodel Vnode2 and the current is assumed to flow from node node} to node node2. Only the first 7 characters in name are used by SPICE2 to identify this resistor. Diodes (nonlinear) The type of IV branchconstitutive equation implemented in the program for each element listed above is specified in parentheses. On any twoterminal element statement the first node. node2.40 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION relations of semiconductor elements an~ expressed by complex which require many parameters. . These special elements have an associated. require only one or a few parameters. capacitors.1. node}. connected between nodes node} and node2 of the circuit. which can be specified by geometric and process parameters.1 Resistors The general form of the resistor statement is Rname node} node2 rvalue <TC = tc1<. SPICE3 supports semiconductor resistors and capacitors.tc2» R in the first column identifies a resistor labeled Rname.2. and the second node. SPICE3 does not restrict the length of name. All twoterminal elements supported by SPICE2. MODEL statement for the process parameters.
TWOTERMINAL
ELEMENTS
41
niJde1 I __
R
rvalue' Rname. VR
node2
~
Figure 2.1
Resistor model.'
The BCE of a resistor is
(2.1)
where the proportionality constant rvalue is the resistance measured in ohms, VR the ,voltage across the resistor in volts, and IR t1).e current in amperes. The resistance may be positive or negative but cannot be zero. SPICE models the temperature variation of the resistance by a secondorder polynomial: rvalue(TEMP)
=
rvalue(TNOM)[l
+ tel(TEMP  TNOM) + te2(TEMP  TNOM)2]
(2.2)
The keyword TC must be present if one or both temperature coefficients are specified; tel and te2 are the first and secondorder temperature coefficients of the resistor specified in parts per °C or eq2, respectively. TNOM is the nominal temperature, 27°C, assumed in SPICE2, and TEMP is a different simulation temperature specified in a • TEMP statement. Note that SPICE3 and PSpice require the temperature coefficients to be specified onthe resistor. MODEL line. PSpice also supports a second temperature dependence, described by an exponential function. Examples
R1 2 45 100 Rci 12 17 1K TC=O.001,0.015 (SPICE2) RC1 12 17 RMOD 1K (SPICE3,PSpice) .MODEL RMOD R TC1=0.001 TC2=0.015
2.2:2
Semiconductor
Resistors (SPICE3)
SPICE3 supports an extension of the general resistor element that allows a convenient description of a diffused resistor from geometric and process information. The general form of a semiconductor resistor statement is Rname nodel node2 <rvalue><Mname><L'=L><W= W>
If rvalue is specified, this statement is equivalent to 'the ge~eral resisto~ statement and any information following the value is discarded. Note that SPICE3 does not support temperature coefficients on the resistor statement. A model statement with the general format described in Sec. 1.3.1 must be used in order to define the parameters listed in Table 2.1 for a model of type R.
42
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
Table 2.1
Semiconductor
Resistor Model Parameters Parameter Units lIoC lI("C2) flIsq. m m Default 0.0 0.0 0.0 106 0.0 Example 5E3 20E6 50 2E6 lE7
Name TCl TC2 RSH DEFW NARROW
Firstorder temperature coefficient Secondorder temperature coefficient Sheet resistance Default width Narrowing due to side etching
The resistance is computed from the length L and width W of the diffusion specified in the resistor statement and the values RSH and NARROW of the model statement:
rvalue
=
RSH.
LNARROW W  NARROW
(2.3)
The temperature behavior is modeled the same way as for regular resistors (see Eq. 2.2). Note that the program provides default values only for Wand DEFW, and not for L, because the width of most diffused resistors on a chip is equal to the minimum feature size; a default value for DEFW also prevents division by zero in Eq. 2.3 when W is omitted.
EXAMPLE 2.1
RDIFFl 1 2 RMODl L=50U W=5U .MODEL RMODl R RSH=lOO NARROW=.25U
The above statements define a resistor of resistance rvalue
=
100. 50  0.25 5  0.25
n=
1047
n
2.2.3
Capacitors
The general form of a capacitor statement is Cname node] node2 cvalue <IC
=
Veo
>
The C in the first column identifies a capacitor labeled Cname and connected between nodes node] and node2 of the circuit, as shown in Figure 2.2. The BeE of a capacitor is
Ie
.
=
eva ue .
I
dve ;It
(2.4)
TWOTERMINAL
ELEMENTS
43
nog_e1_<I •...__ I
IC~ Cname Vc
cvalue
n(oge2
Figure 2.2
Capacitor model.
where cvalue is'the capacitance in farads and represents the proportionality constant between the current through the capacitor, ic, and the rate of change of the voltage across the capaCitor, Ve. The integral variant of Eg. 2.4 is used in SPICE to model the capacitor:
,
.
Ve
=
1 .lcva ue
It iedt + Veo
0
(2.5)
IC is optional and is used to input Veo, the initial value (time t = 0) of the capacitor voltage. This value is used at t = 0 only when UlC (use initial conditions) is specified in the. TRAN statement (see Chap. 6).
Examples
C2 2 0 lOP CGS1 12 14 50F
CLOAD 310 20P IC=5
The above SPI and PS "linear polynomial The general
statement ice a 0 function form of a
describes a linear capacitor with constant capacitance. su ort nonlinear capacitors whose capacitance is a nonof the termina vo age Ve. nonlinear cap~citor statement is
Cname node] node2 POLY cO c1 <c2 ... ><IC
= Veo >
The keyword POLY identifies the capacitor Cname as nonlinear, and the values cO, c1,." are the coefficients of the corresponding powers ofve. The value of this capaCitor is computed at each time point as
cvalue
=
cO + c1 . Ve
+ c2
. v~
+ . ,:
(2.6)
The BCE for the nonlinear capaCitor becomes.
Ie
,
dq d. = 'dt = d/cvalue'
vc)
d = dt (' cO.
Ve
+,.c1 . Ve
2
+ c2.
Ve
3
+ ... )
(2.7)
Thus the coefficients cO,c1, c2, ... should not be mistaken for a polynomial representation of the charge q. .
44
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
EXAMPLE 2.2
CI 3 5 POLY IN 75P 200F
The value of C 1 is evaluated for every new value of Vc across the capacitor according to Eq. 2.6: cvalue
=
109
+ 75
. 1O12vC
+ 200.
1O15v~
+ ...
farad
2.2.4
Semiconductor Capacitor (SPICE3)
SPICE3 supports an extension of the general capacitor element to allow for a convenient description of the capacitance of a planar diffused region from geometric and process information. The general form of a semiconductor capacitor statement is Cname node} node2 <cvalue><Mname><L=L><W= W><IC
= Vco >
If cvalue is specified, this statement is equivalent to the general capacitor statement and any information following the value is discarded except the initial value. If Mname is specified, the capacitance is calculated from the process information in model Mname and the given length, L, and width, W. Note that if cvalue is not specified, Mname and L must be provided; W assumes the default value in the model if not specified. Also note that either cvalue or Mname, L, and W may be specified, but not both. A model type C statement must be used in order to define the parameters listed in Table 2.2. The capacitance is'computed as follows: cvalue
=
CJ(L  NARROW)(W
 NARROW) (2.8)
+ 2 . CJSW(L + W
EXAMPLE 2.3
CDIFF PDIFF, 0 PCAP L=5U W=5U .MODEL PCAP C CJ=IOOU CJSW=IN
 2 . NARROW)
Table 2.2 Name CJ CJSW DEFW NARROW
Semiconductor Capacitor Model Parameters Parameter Junction bottom capacitance Junction sidewall capacitance Default device width Narrowing due to side etching Units Fm2 Fm1 m m Default Example 5E5 2Ell 2E6 lE7
106 0.0
TWOTERMINAL
ELEMENTS
45 and node
The above statements define a diffused capacitor between node 0, with a value computed according to Eq. 2.8:
cvalue
=
PDIFF
104. 5 . 106 . 5 . 106 F + 2 . 109 . (5 + 5) . 106 F
=
22.5 iF
Note that node names are accepted in SPICE3.
2.2.5
Inductors The general form of an inductor statement is
Lname node] node2 lvalue <IC = iLO
>
The L in the first column identifies an inductor labeled Lname and connected between nodes node] and node2 of the circuit, as shown in Figure 2.3. The BCE of an inductor is
VL =
lvalue'
dt
diL
(2.9)
lvalue is the inductance in henries and represents the proportionality constant between the voltage across the inductor and the rate of change of the current through the inductor. The integral variant of Eq. 2.9 is used in SPICE to model the inductor: .
lL
=
II1 
It
0
va ue
VL
d
t
. + lLO
(2.10)
IC is optional and is used to input the initial (time t = 0) inductor current, iLO' This value is used at t = 0 only when UIC is specified in the • TRAN statement, as described in Chap. 6.
Examples
LXTAL 5 6 0.8 LSHUNT 23 51 lOU IC=15.7M
The statements presented so far describe linear inductors characterized by the constant inductance lvalue. SPICE2 also supports nonlinear inductors the inductance of
no~e2 lL~ Lname VL
Figure 2.3
Inductor model.
46
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
which is a nonlinear polynomial function of the current iL. The general form of a nonlinear inductor statement is Lname node] node2 POLY ZOII < 12 ... > <IC The keyword
= iLO>
and the values ZO,
POLY identifies the inductor Lname as nonlinear
ll, ... as the coefficients of the corresponding powers of iL. At least one other coefficient must be specified besides ZO. The value of this inductor is computed at each time
point as lvalue
=
to + II . iL + 12 . if + ...
(2.11)
The BCE for the nonlinear inductor becomes VL
= ~~ =
:t(lvalue'iL)
=
:t(ZO'iL+ll'if+12'it+
... )
(2.12)
The coefficients to, ll, 12, ... are the coefficients for a polynomial representation not of the magnetic flux <p but of the inductance.
EXAMPLE
2.4
LPAR 21 0 POLY 0 5M 1
The BCE for inductor LPAR is obtained from Eq. 2.12: VL which is solved at each time point. :t (0.005 . if
=
+ it)
2.2.6
Independent Bias and Signal Sources
Voltage and current sources that are independent of any circuit variables are defined by the following general statements: Vname node] node2 < <DC> devalue> <AC <ac...mag <aephase> >>
+ <TRAN_junction + <TRAN_junction
<value] <value]
<value2 ... devalue> <value2 ...
»> »>
Iname node] node2 «DC>
<AC <ac...mag <aephase»>
The V and the I in the first column identify a voltage source and a current source, respectively, connected between nodes node] and node2. The polarity conventions are shown in Figure 2.4. The devalue is the voltage difference between nodes node1 and
TWOTERMINAL
ELEMENTS
47
Vname
Iname
Figure 2.4
Independent
voltage and current sources.
node2 for a voltage source and the current flowing from node nodel to node node2 through the source for a current source. The voltage across the terminals of a voltage source is independent of the current flowing through it. Likewise, the current Bowing through a current source is independent of the voltage across its terminals. Independent sources are used to describe biases and signals for the three analytic modes of SPICE: DC, transient (timedomain), and smallsignal AC.1f a source definition contains no other information except the name and the nodes, the program assumes a DC source of value O. . .
EXAMPLE 2.5 vee
10 0 DC 5 IE 0 1 lOU IBl 1 0 'lOU VMEAS 4 5
All four statements define DC sources. The keyword DC is not necessary for defining the DC value of vee and is used mostly for clarity when a lot of information is present on the source line. The current IB flows from ground into node 1 of source lB. I B 1 is identical to I B since both the order of the nodes and the sign of the current have been changed. VMEAS is a zerovalue.voltage source used in SPICE to measure currents (see also Chapter 4). The DC value of a source remains constant during a transient analysis if no other information is provided.
acmag and acphase are the magnitude and phase in degrees of an AC smallsignal voltage or current. These values must be preceded by the keyword AC and are used only in conjunction with an AC analysis request, described in Chapter 5. If the keyword AC is alone, a magnitude of 1 and a phase of 0 are assumed by the program. The value of the transfer function at any point in the circuit referred to the input can be obtained by monitoring an AC voltage or current. The input Vin(jw) is defined by the AC source. The output variables computed by the program, such as Vout(j w), are
48
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
identical to the transfer function, T(jw), phase of 0: Vout(jw) since Vin(jw)
if the input signal has a magnitude of 1 and
=
T(jw)Vin(jw)
=
T(jw)
(2.13)
= acmag'
exp(j . acphase)
=
1
(2.14)
For the largesignal timedomain analysis, SPICE supports five types of timedependent signals: pulse, exponential, sinusoidal, piecewise linear, and singlefrequency frequency modulated. The TRAN function specification in a source statement contains a keyword that identifies one of the five functions and a set of parameters. In the following description of the five functions, the parameters and their defaults are specified.
2.2.6.1 Pulse Function
The general format of the TRAN function specification of the source statement is PULSE (Vi V2 <TD <TR <TF <PW <PER»»» where the seven parameters have the meanings shown in Figure 2.5 and described in Table 2.3. The order of the values following the TRAN_function is essential for the correct specification of the signal characteristics. The parameters must be input in the given order. The initial and pulsed values, Vi and V2, must be specified. If no values follow the function name, SPICE2 and SPICE3 perform the simulation and do not flag an error; PSpice, however, announces an error and aborts the analysis. The rest of the values, TD through PER, need not be input, but all values preceding the last nonzero parameter must be specified. The default values listed in Table 2.3 are used for unspecified parameters and are related to TSTEP and TSTOP of the transient analysis introduced in Chap. 1 and described in detail in Chap. 6; TSTEP is the output resolution of the waveforms, or time step, and TSTOP is the end of the time interval.
Amplitude,
V or A
Time, S
PER
Figure 2.5
SPICE PULSE source function.
VIN is a rectangular signal. and VSAW a sawtooth. such as VD.3 Name VI V2 TD TR Pulse Source Parameters Parameter Initial value Pulsed value Delay time Rise time Fall time Pulse width Period Units VorA VorA s Default 0.6 VD 3 0 PULSE (1 1 1U) IKICK 0 2 PULSE (0 1M 1U 0 0 2U) VIN 1 0 PULSE (0 5 0 IN IN 99N 200N) VSAW 3 4 PULSE (0 1 0 IOU IOU O.lU 20.1U) The waveforms generated by the four statements are shown in Figure 2.0mA 52 OmA 5. Neither SPICE2 nor PSpice accepts a DC value different from the first value of the PULSE function. . a single pulse.0 s s s TF PW PER s 0. The DC value of each of the above sources is equal to the initial value of the pulse.:> ~ 1.0V 0 > 1. The PULSE source can describe a step function.6.6 Sample PULSE source functions.TWOTERMINAL ELEMENTS 49 Table 2. such as VIN and VSAW.0V <.0V ov 5 10 Time. SPICE3. such as IKICK.0V z :> ~ « en > ov 1. For a step function neither PW nor PER need to be specified. IlS Figure 2. and for a single pulse PER must not be specified.0 0. or a periodic signal. however.0 TSTEP TSTEP TSTOP TSTOP EXAMPLE 2. allows the user to define a DC value different from 1.
Due to the numerical integration algorithm used by SPICE. s Figure 2. 9. SPICE.50 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION the starting value VI of the PULSE function.TD))eTHETA(tTD) (2. Values smaller than TSTEP can be specified for TR and TF.2. but the faster rise and fall times cannot be seen on the lineprinter plot.6. .15) Amplitude. PW. the program substitutes the default value. 2. Thus a value one or two orders of magnitude smaller than TR and TF needs to be specified. a voltage or current change in zero time can cause the solution not to converge. Therefore. For the sawtooth voltage source. however.4.7 SPICE SIN source "function. SPICE uses the defaults of TSTEP for the fall time and TSTOP. TSTOP. The single pulse IKICK defines a pulse of 2 fJs width and zero TR and TF. TSTEP for TR and TF. the end of the transient analysis. VSAW. The step function described by VD does not need any additional information besides the initial and pulsed values and the delay time of the step. the pulse width. In the absence of devalue. for the pulse width. does not accept a zero value for PW and replaces it by the default value. a warning message is output stating that the time zero value is used for DC. should be zero. V or A T VA 1/FREQ t VA 1 1/THETA Time. the other values are optional.7 and described in Table 2.2 Sinusoidal Function The general format of the sinusoidal function in the source statement is SIN(VO VA <FREQ <TD <THETA»» where the five parameters are illustrated in Figure 2. The offset and the amplitude must always be specified. explained in more detail in Chap. The source assumes the offset value VO for times from t = 0 to t = TD and behaves according to the following function for t > T D: f(t) = VO + VA sin(27TFREQ(t .
implements a cosine signal by specifying a negative delay equal to 2. the period is equal to the time interval of the analysis.8 over a time interval of 10 fL s. Therefore. 2. veas.0 EXAMPLE 2. .73.6. The last source. or a quarter of a period. The SFFM source is a special case of a sinusoidal source. The waveforms produced by the three sources are plotted in Figure 2.2 rnA amplitude. in SPICE2 the signal veas would be a sine wave.5U) The first example describes a sinusoidal signal of 1 V amplitude. the length of the time interval for the transient analysis. in other words. equal to 2. The number of periods that can be viewed for this interval are 10 for VSIN. indeed. modulation.3 FrequencyModulated Sinusoidal Function The general format for a singlefrequency frequencymodulated (SFFM) transient function on a source statement is SFFM (VO VA <Fe <MDI <FS»» The five parameters are defined in Table 2. the SIN and SFFM functions produce identical waveforms. The default for FREQ according to the parameter table is lITSTOP. Note that an SFFM function does not contain any delay. The second example is a current source that supplies a sinusoidal signal of 1 rnA DC current.7 VSIN 33 34 SIN(O 1 1MEG) I2 2 0 SIN (1M .2M 10MEG 1U 1MEG) veas 5 6 SIN (0 5 lOOK 2. The last two parameters differ between the two functions. 0. and 10 MHz frequency that is delayed by 1 fLs and decays by a factor of e.0 0. The number of signal periods depends on TSTOP.4 Name VO Sinusoidal Source Parameters Units Default 0. over 10 periods. zero DC offset.TWOTERMINAL ELEMENTS 51 Table 2.5. but not SPICE2. if only the first three parameters are defined and if they are identical.2. 90 for 12. SPICE3 and PSpice allow a negative delay.5 fLs. and 1 for veas. A singleperiod sinusoid independent of the transient analysis interval can be specified by omitting the frequency.0 VTSTOP 0. and 1 MHz frequency. in one case defining damping characteristics and in the other.0 Parameter VA FREQ TD THETA Offset Amplitude Frequency Delay Dampingfactor VorA VorA Hz s SI 0.
A signal described by an SFFM function has the following time behavior: f(t) = va + VAsin(27TFC' t + MDlsin(27TFS' t)) (2.0V 0 C> > 5.2 mA C\l O. ~s 6 8 Figure 2.9.52 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION 1V z ii5 > 1 V (J) 5.16) EXAMPLE 2.0V 1. It is shown in Figure 2.8 Example SIN source functions.5 Name VO FrequencyModulated Sinusoidal Source Parameters Parameter Offset Amplitude Carrier frequency Modulation index Signal frequency Units VorA VorA Hz Default 0.0 l/TSTOP 0.8mA 2 4 Time.8 VIN 3 0 SFFM (0 1 lMEG 2 250K) The above source produces a 1 MHz sinusoid of 1 V amplitude modulated at 250 kHz. > Table 2.0 0.0 l/TSTOP VA FC MDI FS Hz .
Jls 6 8 Figure 2. must be specified. 2. Vi and V2. .10 SPICE EXP source function. and the other parameters need not be specified.6. The time behavior of an exponential source is described by the following functions of time t: Amplitude.2. the defaults listed in the table are used for any missing parameter values.TWOTERMINAL ELEMENTS 53 1V z :> 2 4 Time. The initial and pulsed values.4 Exponential Function The general format of the EXP TRAN_function in the source statement is EXP (Vi V2 <TDi TAW TD2 <TAU2») where the six parameters are as illustrated in Figure 2. V or A Time. S TD1 TD2 Figure 2.9 SPICE SFFM source function.6.10 and are described in Table 2.
This is why after a short decay with a time constant equal to TSTEP.17) EXAMPLE 2. otherwise the current may start increasing before the end of the analysis interval TSTOP.9 VEXP 1 0 EXP (0 5 0 1U 1) IDEC1 3 1 EXP (1M 0 0 0 0 1U) The first source. the current resumes increasing back towards 1 rnA with a time constant equal to 1 JLs.Thus. 1 second.0 0. ») . on the VEXP line is necessary for defining T the delay TD2 before the source starts decaying. by default the value of VEXP would start to fall after TSTEP seconds. of IDECl is larger than the pulsed value. The three waveforms are plotted in Figure 2.Note that since the initial value.0 TSTEP TDI + TSTEP TSTEP v(t) = Vi VI(t) { V2(t) + (V2 = VI (t) + (Vi = Vi Vl)(1 .6 Name VI V2 TDl TAUl TD2 TAU2 Exponential Source Parameters Parameter Initial value Pulsed value Rise delay time Rise time constant Fall delay time Fall time constant Units VorA VorA s s s s Default 0. IDEC1. must be specified for TD2. The second source. that is.V2) e(tTDl)/TAUI) eUTD2)/TAU2) (1  for 0 ::5 t::5 TDi for TDi < t ::5 TD2 for TD2 < t ::5 TSTOP (2.54 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Table 2. is intended to be a current that exponentially decays from 1 rnA to 0 with a time constant of 1 JLs. and TD2 and TAU2 become the rise delay and time constant. respectively.1 JLS. V2. respectively. until TD2 = TSTEP. 1. where TSTEP = 0.5 Piecewise Linear Function The general format of a piecewise linear function on a source statement is PWL (tl VI < t2 V2 < t3 V3 .6. VEXP. the meanings of rise and fall are reversed.0 0. TDi and TAUl become the fall delay and time constant..11.. 2.2. Vi. he last value. the correct definition of a decaying current is the following: IDEC2 3 1 EXP 1M 0 0 1U 1 Note that a large value. represents an exponential signal that rises from 0 to 5 V with a time constant of 1 JLs.
from 8.tnI . VI). There is no limit to the number of coordinate pairs specified.1U 0 4U 0 4.11 Example EXP source functions. the source assumes the last value.TWOTERMINAL ELEMENTS 55 4V a x U.tnI tn .J 9 OmA Time. Vi).lU 1M 2U 1M 2. note that SPICE does not accept more than one PWL source value for a given time point. If tl > 0.Vnd EXAMPLE 2. the first coordinate pair assumed by SPICE is (0. J. 0 and TSTOP.2U 5) + The two waveforms are shown in Figure 2. if the time of the last coordinate pair.2U 5 3U 5 3. The parameters for this function are timevalue coordinates.1U 0 7U 0 7. This type of function is useful for describing sequences of pulses. The signal described by a PWL statement is formed of straight lines that connect the pairs of coordinates (ti.1U 0) VDATA 21 0 PWL (0 0 0.2U 0 6U 0 6. Both IBITl and VDATA are specified with finite rise and fall times. Vn. tn.1U 1M 8U 1M 8.1U 1M 5U 1M 5. equal to 10 JLS.J > OV 1 mA () U. IBITl preserves its last specified value. at TSTOP in SPICE2. . Neither tl nor the last defined time needs to coincide with the transient analysis limits. is greater than TSTOP. 0.1 JLS through TSTOP.10 IBITl 1 0 PWL (0 0 lU 0 1.12. SPICE3 and PSpice interpolate the source value at TSTOP: V(TSTOP) = VnI + (Vn TSTOP .Is Figure 2.
k is the coefficient of coupling.12 PWL functions. 2. defined somewhere else in the input file. which are treated separately in Chap. .56 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION « « 0 f 5.3. This section covers multi terminal elements with the exception of semiconductor elements. SPICE3 contains models for: Switches Uniformly distributed RC lines Lossy transmission lines In PSpice the switch and the lossy transmission line are also supported.3 MULTITERMINAL ELEMENTS elements: SPICE2 supports the following types of multiterminal Mutual inductors (linear and nonlinear) Controlled sources (linear and nonlinear) Transmission lines (linear) Bipolar and field effect transistors (nonlinear) In addition to the above element types.13.1 Coupled (Mutual) Inductors The general format of a coupled inductors statement is Kname Lnamel Lname2 k K in the first column identifies a mutual inductance specification between the two inductors Lnamel and Lname2. !is Figure 2. generally. 3. which must be greater than 0 and less than or equal to 1. require only simple specifications.0V > OV 1. The elements presented in this section. 2.0mA f ~ OmA Time. See Figure 2.
The above equations must be modified accordingly to include all mutual inductances and terminal pairs. . .19) Systems of coupled inductors are not limitt. Note that the positive inductor node..99 mHo The BCEs of coupled inductors in SPICE are (2.13 Coupled inductors. Kname Figure 2.d to two and can be extended to a multitude of inductor pairs. The mutual inductance of the coupled inductors is M = .11 The SPICE specification of two coupled inductors L1 and L2 is L1 121M L2 4 3 1M KL1L2 L1 L2 .MULTITERMINAL ELEMENTS 57 EXAMPLE 2. The value of the mutual inductance M is computed as M = kJL]L2 (2. must be defined first on the inductor statement.18) where k is the coupling coefficient and L] and ~ are the inductances. containing the dot.99 The polarity of coupling between the two inductors is defined by the position of the dots as shown in the schematic representation in Figure 2. .13.
a currentcontrolled current source. Additionally. and the secondary. supply voltages or currents that are functions of voltages or currents in other parts of the circuit.12 Write the SPICE2 input for a transformer that has turns ratio NdN1 primary has selfinductance L1 = 1 mHo = 5 and whose Solution First calculate the inductance of the secondary knowing that the inductance is proportional to the square of the turns: L2 = N2)2 ( N1 Ll = 25 mH (2. CCVS. VCVS. a voltagecontrolled voltage source. and the voltages and currents obey the following relations: (2.3. with N2 turns. An ideal transformer has two pairs of terminals. also known as controlled sources. and a currentcontrolled voltage source. the primary. Dependent sources are useful for implementing a variety of largesignal input/output transfer functions (Epler 1987). . SPICE supports four types of dependent sources. CCCS. such as SpicePLUS.20) (2. 2.22) The coupling coefficient for an ideal transformer is 1. implement a nonlinear magnetic core model.2 Dependent (Controlled) Sources Dependent sources. PSpice and other commercial SPICE versions. with N1 turns.21) EXAMPLE 2.58 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Coupled inductors can be used to model an ideal transformer in SPICE. and therefore the SPICE2 input specification for the transformer is the following: LPRIM 121M LSEC 3 4 25M KXFRMR LPRIM LSEC 1 '¥ ~ G ote that PSpice restricts the value of k to less than 1. a voltagecontrolled current source. VCCS.
pz. A nonlinear controlled source is limited to a polynomial function of an arbitrary number of circuit variables in SPICE2. . or H.14. Thus. and neither the keyword POLY nor ndim needs to be specified. . x3 be three controlling variables. with all optional fields deleted and only one coefficient given. and the output is equal to the input. A linear controlled source has two ports.1 and Sec. all types of nonlinear controlled sources have B as the first character of the element name. PI.. SPICE3 and PSpice accept an arbitrary nonlinear function of both voltages and currents in the circuit. The input values represent the following coefficients: (2. The general format of dependent sources is CSname node+ node. Only SPICE2 and PSpice recognize the POLY specification. The onedimensional polynomial (ndim = 1) is the default in SPICE2.4. or controlling variable. A nonlinear source can depend on more than one current or voltage. In this case that value becomes the coefficient of the linear term.. are coefficients for the polynomial description.. see Sec.MULTITERMINAL ELEMENTS 59 SPICE supports both linear and nonlinear dependent sources. F. on the dependent source statement denote polynomial coefficients. Let Po. CTRLname/ sources or a voltage source name that measures the controlling current for currentcontrolled sources. Xl. PI... a linear controlled source statement is a special case of the general POLY statement. . Pz.4. E.23) An exception to the above assignment of coefficients is made when only one value appears on the source statement.<POLY(ndim» CTRLname/nodes Po < PI < pz . the symbols and controlling elements are shown in Figure 2.4. 7. The sequence of values in the dependent source statement is a function of the number of dimensions of the polynomial.. Po. 7. Xz. In SPICE3 only linear controlled sources are identified by G. Xl . The four types of dependent sources are as follows: VCCS VCVS CCCS CCVS G E F H = = VE = VE = IF = IF = VH = VH = Ie Ie GVe g(Vc) EVe e(Vc) FIe f(lc) HIe h(lc) linear nonlinear linear nonlinear linear nonlinear linear nonlinear The different types listed next to the four kinds of controlled sources represent the identification character on an element statement. times a proportionality constant. » nodes is a pair of nodes for voltagecontrolled For a linear source only the information outside the brackets is specified. and f (x) be the dependent polynomial function.
60 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION nc+~+ 11 nc+o. 82.E 11 G + 11 + 11+ F H Figure 2.4. is interpreted like a regular polynomial source in SPICE2 but causes an error in PSpice. nc Vnc+.13 G1 3 2 1 2 1E3 G1 3 2 POLY(l) 1 2 1E3 G2 5 6 3 4 10M 1M (SPICE2) G2 5 6 VALUE = (O.4)} (PSpice) The first two statements represent the same VCCS. 7. because in this way the general nonlinear dependent source statement takes the particular form of a linear controlled source for ndim = 1. or transconductance.14 Dependent sources.Ol+lE3*V(3. The value of 82 is evaluated according to the following equation: .+ 11+ Vnc+. The third example.nr llCO  11+ nce>. VI. The fourth statement represents the preferred syntax for PSpice. between nodes 1 and 2: The above discrepancy in the meaning of Po has been deliberately chosen for onedimensional polynomial sources.2. the third statement is accepted by PSpice ifthe keyword POLY (1) is included. 82 must be described by a B statement in SPICE3 (see Sec. The second statement is rejected by SPICE3. of a current of 1 rnA flowing from mode 3 through the source to node 2 and controlled by the voltage.1). EXAMPLE 2.
The general format of a nonlinear VCCS is Gnamen+ n. . PI. the voltage difference Vnc+.2.. respectively.nc (2..25) + p]6Xi + P17X~X3 + P]8X2X~ + P]9X~ + .nc. The linear VCCS is only a special case of the more general nonlinear VCCS. nc2+. Controlled sources are useful for emulating analog and digital circuit blocks.. which can be present only when a nonlinear VCCS is specified..gvalue A G in the first column followed by up to seven characters and digits define the unique name of a VCCS. converters.are the nodes between which the current source is connected.. The . The coefficients Po. must be specified. > + Po < p] < P2 .. The BCE of a VCCS is Ie = gvalue . and nc 1 + and nc 1.. take the meaning described above depending on the number of controlling variables. X2. n+ and n.24) A threedimensional polynomial function assigns the values on the source statement to coefficients in the following order: f(x].1 VoltageControlled Current Source (VCCS) The general format of a linear VCCS is Gnamen+ n.nc+ nc.14)..MULTITERMINAL ELEMENTS 61 A twodimensional polynomial function is expressed as = Po f (x]. such as gain stages. and many others.26) where gvalue is the transconductance in mhos. Vnc2+. n. operational amplifiers. . > The first difference between this statement and that of a linear VCCS is the keyword POLY. The second difference is that for each additional controlling voltage a pair of controlling nodes. with current flowing from the positive node.is the controlling variable. X2) + PIX] + P2X2 + P3XI + P4X]X2 + P5X223223 X] + P7X]X2 + P8X]X2 + P9X2 + P6 (2.nc2.. ndim is the number of controlling voltages. through the source to the negative node. Vnc+. The positive and negative controlling nodes are nc+ and nc.are the terminals of the first controlling voltage. X3) = Po + PIX] + P2X2 + P3X3 + P4XI + P5X]X2 + P6X]X3 + P7X2 + P8X2X3 + P9X3 + PIOX] + PllX]X2 2 2 3 2 + P12XIX3 + P13X]X~ + P]4X]X2X3 + P]5X]X~ (2. nc2.3...nc1. n+. 2.(see Figure 2. P2. > > <Ie = Vnc1 +.<POLY( ndim) > nc1 + nc1 < nc2+ nc2.
62 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION third difference from the statement for a linear VCCS is that initial conditions can be defined for the controlling voltages.are the positive and negative nodes of the voltage source. n+ and n. at t =0 the terminal voltage.is the controlling variable. If no initial values are present. EXAMPLE 2. see Chap. if the ure option is chosen.3 The first example represents a nonlinear conductance.nc+ nc.5 V and 1. The linear VCVS is only a special case of the more general nonlinear VCVS. Ve is 2 V. respectively.14 GRPOLY 17 3 POLY (1) 17 301M 1. because the terminal nodes of the controlled current source are identical with the nodes of the controlling voltage. but not in SPICE2.5 .are the positive and negative controlling nodes.27) where evalue is the voltage gain. The BCE of the nonlinear conductance GRPOLY is Ie = 0.001.1. V3. the controlling voltages are assumed to be zero. V~ In a transient analysis. Note that the keyword POLY is needed in PSpice for a onedimensional source.14. These values are used only in conjunction with the ure option in the • TRAN statement to initialize the controlled source at the first time point. 1O6Vts In a transient analysis that starts from initial conditions (that is.001. The BeE of a VCVS is VE = evalue' Vnc+.3 V.0015 . the two controlling voltages are initialized details.nc (2.2 + 3. to 2. VI. nc+ and nc. the voltage difference Vnc+. as shown in Figure 2. The second example is a twodimensional nonlinear VCCS of value Ie = 0. respectively. because the re keyword and initial value are present on the GRPOLY line. when the ure flag is on). or equal to the resulting value from the DC bias point otherwise.evalue An E in the first column followed by up to seven characters and digits defines the unique name of a VCVS.017.nc.5U IC=2.3.2 VoltageControlled Voltage Source (VCVS) The general format of a linear VCVS is Ename n+ n.S + 0. Ve + 0. 6 for 2. 5M IC=2 G2DIM 23 17 POLY (2) 3 5 1 201M 17M 3. .5.2.
2. > > <IC= vllcl +. E 1.75 ESUM 17 0 POLY(3) 1 0 2 0 3 0 0 1 1 1 1C=1.1.0. Use different values for VI. ncl + and ncl.are the terminals of the first controlling voltage.are the positive and negative nodes of the current source. P2. for each additional controlling voltage. 2.14)..O. these values are used only in conjunction with the UIC option in the • TRAN statement to initialize the controlled source at the first time point. IC is optional and defines the initial values of the controlling voltages.Vname fvalue An F in the first column followed by up to seven characters and digits defines the unique name of a CCCS..Ilcl. n+ and n... V21. ..0.75. EXAMPLE 2.llc2. and V3.17+ 1. the controlling voltages are assumed to be zero. 15 E1 3 4 POLY (1) 21 17 10. The coefficients Po. since the value of the controlled source ESUM is the sum of Vl. 5 and 7. take the meaning described above depending on the number of controlling variables.5 + 2. or equal to the resulting value from the DC bias point otherwise. Exercise Run an AC analysis of the voltage summer ESUM using SPICE and verify if this VCCS still performs the add function. V2. Vname is the voltage source through which the controlling current flows. For an explanation of the result. ne2 .<POLY (ndim) > nel + ne1+ <ne2+ ne2 .3.0. defines a nonlinear voltage gain function VE = 10.3 CurrentControlled Current Source (CCCS) The general format of a linear CCCS is Fname n + n .. > Po < PI < P2 . V2.0. and V3. must be specified. see Chaps. if the UIC option is chosen. and current flows from the positive node through the source to the negative node (see Figure 2. > The keyword POLY must be present when a nonlinear VCVS is specified.1 1. ndim is the number of controlling voltages.o. ne2 +.5 2..MULTITERMINAL ELEMENTS 63 The general format of a nonlinear VCVS is Ename n+ n. Vh17 The second example represents a voltage summer. If no initial values are present. Vllc2+.. a pair of controlling nodes. .2.. PI.3 The first example.
> The keyword POLY must be present when a nonlinear CCCS is specified. ndim is the number of controlling currents. The current of F2 is equal to the product of the currents flowing through voltage sources . If no initial values are present. > Po <PI <P2 . the controlling currents are assumed to be zero if the UIC option is chosen.001 1E4 1E5 F2 2 3 POLY (2) VCON1 VCON2 0 0 0 0 1 FeON defines a current that is a quadratic function of the current flowing through the voltage source ve 1: . Vnamel is the voltage source measuring the first controlling current.28) where fvalue is the current gain.Vname hvalue . The coefficients Po.. The general format of a nonlinear CCCS is Fname n+n<POLY (ndim» Vname1 <Vname2 . for each additional controlling current a voltage source must be specified. or equal to the resulting value from the DC bias point otherwise. Exercise Replace transistor QI in Example 1..16 FCON 13 4 POLY (1) VC1 0. i(Vname2) . IC is optional and defines the initial values of the controlling currents. Explain the difference and modify the circuit to obtain the same answer. The linear CCCS is only a special case of the more general nonlinear CCCS. take the meaning described above depending on the number of controlling variables.4 '~ CurrentControlled Voltage Source (CCVS) Th~ general format of a linear CCVS is •Hname n + n ... 2.. 1.. these values are used only in conjunction with the UIC option in the •TRAN statement to initialize the controlled source at the first time point. and show that the bias point obtained by SPICE is close to the one obtained in Chap.3..2. veONl and veON2. » + <IC = i(Vnamel). . EXAMPLE 2.. The BCE of a CCCS is h = fvalue 'I(Vname) (2.2 with a CCCS connected from collector to emitter having value fvalue = Ih = 100 and controlled by the current iRB. P2. PI.64 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION I(Vname) is the controlling variable.
for each additional controlling current a voltage source must be specified. I(Vname) is the controlling variable. The general format of a nonlinear CCVS is Hname n+ n. depending on a controlling voltage or current.3 Switches SPICE3 and PSpice support a nearly ideal switch model. EXAMPLE 2..29) where hvalue is the transresistance in ohms. The coefficients Po.14. If no initial values are present. The switch is therefore a resistor that toggles between a very small value. ndim is the number of controlling currents. than the other resistances in the circuit.are the positive and negative nodes of the voltage source. Vnamel is the voltage source measuring the first controlling current. > Po <PI <pz . This behavior can be approximated satisfactorily with ON and OFF resistances that are significantly smaller or larger...<POLY (ndim) > Vnamel <Vname2 . + <IC = i(Vnamel). and a very large value. the ON resistance. n + and n . 2.1.3.. or equal to the resulting value from the DC bias point otherwise. The linear CCVS is only a special case of the more general nonlinear CCVS. these values are used only in conjunction with the OIC option in the • TRAN statement to initialize the controlled source at the first time point. as shown in Figure 2.. respectively. .5. PI. and the value of HXYis equal to the square of the difference of the currents through voltage sources VINl and VIN2. An ideal switch has zero ON resistance and infinite OFF resistance. IC is optional and defines the initial values of the controlling currents.. take the meaning described above depending on the number of controlling variables. The BCE of a CCVS is VH = hvalue' I(Vname) (2.17 HRNL 1 2 POLY (1) V12 0 0 1 HXY 13 20 POLY(2) V1N1 V1N2 0 0 0 1 2 1 10=0.. the controlling currents are assumed to be zero if the OIC option is chosen. .3 The voltage between nodes 1 and 2 of HRNL is equal to the square of the current flowing through V12. pz.. i(Vname2) .MULTITERMINAL ELEMENTS 65 An Hin the first column followed by up to seven characters and digits defines the unique name of a CCVS. the OFF resistance. Vname is the voltage source through which the controlling current flows. > » The keyword POLY can be present only when a nonlinear CCVS is specified.
0 0. GMIN in the table is a minimum conductance. and IT and IH are replaced by ION and IOFF for a Wswitch.66 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Voltage. and for modifying it see Chap. 3.0 0. and CSW.CSW .30) ~ Another remedy for convergence failure of circuits with switches is the addition of capacitors across the controlling voltage and inductors in series with the controlling current. Model is the name of the model statement that contains the parameters of the switch. The switch in SPICE3 displays hysteresis.15. the voltagecontrolled switch. The parameters VT and VH are replaced by VON and VOFF for an S switch. that is. The switch is connected between nodes n + and n . SW.nc+ nc. in order to avoid the situation in which the time step is too small (see Chap.CSW SW.0 0. switching at Vcontrol = VT when Vcontrol is rising and at VT . Each model type defines four parameters. There are two types of switch models. Note that the PSpice switch does not have hysteresis.0 1. a W identifies a currentcontrolled switch.and currentcontrolled switches have the following general formats: Sname n+ n.Vname Model <ON/OFF> where an S in the first column identifies a voltagecontrolled switch.VH when Vcontrol is falling. It is strongly recommended that ROFF < 1012 RON (2. shown in Table 2.7 Name VT IT VH IH RON ROFF Switch Model Parameters Parameter Threshold voltage Threshold current Hysteresis voltage Hysteresis current ON resistance OFF resistance Units V A V A Default 0. Because switches are highly nonlinear. the currentcontrolled switch. 9). SW CSW SW CSW SW.Model <ON/OFF> Wname n+ n.0 lIGMIN Model n n.or by the current flowing from the positive node to the negative node of the voltage source Vname.7. Table 2. used in SPICE to protect against an illconditioned set of nodal equations.and is controlled either by the voltage between nodes nc+ and nc. RON should be negligible compared to the smallest resistance and ROFF should be large enough not to affect the total value when connected in parallel to the largest resistor. The interval between the two variables is used to provide for a smooth transition between RON and ROFF. The resistance of the switch as a function of the controlling variable is shown in Figure 2. 9. their use in a circuit can lead to convergence problems. for other uses of GMIN see Chap. and the flag ON/OFF specifies the initial state of the switch. In order to prevent the failure of the timedomain analysis. which prevent sudden changes in the controlling variables.
the circuit is equivalent to the MOS implementation of a NOR gate with the transistors replaced by switches and a load resistor connected to 5 V. Rs V'l"  ~1' R4 V4   Figure 2. EXAMPLE 2.16. respectively. The values are RON = 1 0" ROFF = 1 Mo'.MULTITERMINAL ELEMENTS 67 Rswitch ROFF RON VT Vcontrol Figure 2. o Vee.16 NOR gate implemented with switches. .18 Use switches to model a NOR gate in SPICE3. The value of the load resistor is 1 ko'. Solution A straightforward implementation is shown in Figure 2. than 1 ko'. RON and ROFF are selected such that they are much smaller and much larger. For best results in SPICE.15 Switch resistance as a function of controlling voltage.
introduced in Sec.TRAN .01U 5 2U 5 2. one additional characteristic . 7 for more details on this subject. SPICE3 and PSPICE support also lossy transmission lines.n2.n4.3:4 Transmission Lines The general form of a transmission line statement is Tname nl n2 n3 n4 ZO=ZO <TD=TD><F=freq <NL=NL» + <IC=Vnl. NOR GATE WITH SWITCHES * * NORGATE * RL 2 1 1K Sl 1 0 3 0 SW S2 1 0 4 0 SW vee 2 0 5 * * INPUT SIGNALS * 3 0 PWL 0 0 V3 R3 3 0 1 R4 4 0 1 1U 0 1. as well as for different values of RON and ROFF.for currentcontrolled switches. and n3 and n4 are the nodes at port 2.68 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION The SPICE3 input description is listed below.5. model type ISWITCH. Only lossless lines are supported in SPICE2.6.MODEL * . See also Chap.01U 5 0 3U 0 3. ii.2. END SW SW RON=l . and ION and IOFF must be specified. Vn3.01U 5 V4 4 0 PWL 0 0 2U 0 2. represent the two inputs of the NOR gate.PLOT . VH. nl and n2 are the nodes at port 1.17. The controlling terminals. ZO is the characteristic impedance of the line. 2. PSpice users must replace VT and VHwith VON and VOFF and the model type byVSWITCH. The two input signals are a sequence of logic 0 and 1 described as PWL voltage sources.02U 4U V(3) ROFF=lMEG VT=1 VH=O TRAN V(l) V(4) Exercise Run this circuit in SPICE3 and study the impact of various values for the hysteresis width.01U * . A transmission line together with the SPICE equivalent model is shown in Figure 2. i2 > A T in the first column identifies a transmission line element. nodes 3 and 4. 2.
n4(t . These values are used only in conjunction with the UIC option on the • TRAN statement. IC. which can be either the line delay. The BCEs of the transmission line are expressed as the following functional forms of the voltage sources VI (t) and vz(t) in the equivalent model (Branin 1967) of Figure 2. expressed in wavelength units.n2(t . at a given frequency jreq.TD) + 20 . NL.Jreq is the quarterwave frequency.TD) The two equations represent the incident and reflected waves along a lossless transmission line. iz(t .TD) Vnl.MULTITERMINAL ELEMENTS 69 n1 n2 0_0 0>0 Tname n3 n4 n1 n2 Figure 2.33) (2.25. are optional and consist of the currents and voltages at the terminals of the two ports. If only a frequency is specified andNLis omitted. The three parameters are described by the following equation: TD where NL I = NL jreq (2.31) = A (2.17: VI (t) VZ(t) = = Vn3.32) with I the physical length of the line and A the wavelength. .17 Transmission line and equivalent model. must be specified about the line. Initial Conditions.34) + 20. TD. NLdefaults to 0. iI(t .TD) (2. or the normalized electrical line length. that is.
18 Transmission line response for RL = 50 nand RL = 100 n.32.cry 0 3.1N 0.10 . . .. 40 .5 :. The SPICE input is listed below: TRANSMISSION LINE EXAMPLE VIN 1 0 PULSE 0 5 0 0. ns Figure 2. 0 .5 cry RL= 50n :. . Tl 1 0 2 0 ZO=50 TD=10N T1 1 0 2 0 ZO=50 F=100MEG NL=1 T1 1 0 2 0 ZO=50 F=25MEG A coaxial cable is described by two transmission lines. and the second the shield with respect to the outside world: TINT 1 2 3 4 ZO=50 TD=1.5 N :.TRAN .0 2. 30 .PLOT TRAN V(2) V(3) * 2.19 The following three definitions ofline Tl are equivalent. I . I . .25N SON .5N TEXT 2 0 4 0 ZO=100 TD=1N Study the difference in the response ofline TLINE to a pulse when terminated with a load resistor RL of 50 nand 100 n. . . see Eq. the first representing the inner conductor with respect to the shield.33 RL=100n :.31 and 2.N 0 2. . 2.1N 5N SON RIN 1 2 50 TLINE 2 0 3 0 ZO=50 TD=10N RL 3 0 50 .70 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION EXAMPLE 2. 20 Time.
a voltagecontrolled current source. controlled (dependent) sources.. R. Independent voltage and current bias and signal sources can be specified using the following generic SPICE statement: V/Iname nodeI node2 «DC> <valueI dc_value><AC <value2 . polynomial expressions of voltage and current. resistor. RL.. and ZOo 2. END V(3) The waveforms at the input and output of TLINE for the two values of the load resistor RL are shown in Figure 2.. The difference is that a matched line with Rin = RL = ZO delays the input pulse by TD while the unmatched line reflects the pulse between input and output with an attenuation corresponding to the values of Rin. and inductor. were defined. Coupled inductors have the following syntax: Kname Lname I Lname2 k Four types of controlled sources are supported in SPICE. T~ese elements use the following SPICE syntax: Rname nodeI node2 rvalue <TC= tcl. <acJ11ag <acphase»> + <TRAN_function »> where TRANfunction can be one of the following: PULSE (VI V2 <TD <TR <TF <PW <PER»»» SIN (Va VA <FREQ <TD <THETA»» SFFM (va VA <Fe <MDI <FS> >» EXP (VI V2 <TDI <TAW <TD2 <TAU2»») PWL (tl VI <t2 V2 <t3 V3 . the twoterminal passive elements. C. a currentcontrolled .. type E. ») For each of the optional parameters SPICE provides default values. Both the syntax and the relation between the branchconstitutive equations and SPICE statement parameters were explained and exemplified.18. type G. <tc2» Cname nodeI node2 cvalue <IC Lname nodeI node2 lvalue <IC = = Vco > ho > Capacitors and inductors can be also defined as nonlinear. respectively. switches. Multiterminal elements supported in SPICE include coupled inductors.4 SUMMARY This chapter describes all the elements supported in SPICE with the exception of the semiconductor devices. a voltagecontrolled voltage source. L. First. capacitor.SUMMARY 71 . and transmission lines.PRINT TRAN V(2) .
. 1991. A. Newton... Nonlinear polynomial controlled sources use the following general syntax: G/E/FlHnamenode+ node. type H. 1988. McCalla. IEEE Transactions on Circuits and Systems. PSpice. » More complex nonlinear dependent sources supported in SPICE3 and PSpice are defined in Chap. Transient analysis oflossless transmission lines. the operation of the switch can be controlled by a voltage (type S) or a current (type W). O. 1987. Boston: Kluwer Academic. A nearly ideal switch is implemented in SPICE3 and PSpice.72 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION current source. Univ. of California. W. . F. Berkeley: Univ. and a currentcontrolled dent source has the following syntax: voltage source. The modified nodal approach to network analysis. C. Pederson. D. Fundamentals of ComputerAided Circuit Simulation. Vladimirescu. SPICE Version 2G User's Guide. Epler.. Zhang. B. SPICE3 Version 3E User's Manual. + < Ie = VnI. SPICE2 application notes for dependent sources. IEEE Circuits and Devices Magazine 3 (September): 3644. 7. Circuit Analysis User's Guide. and A. A. 1991. L.Model <ON/OFF> Wname n+ n. Quarles. i2 = TD> <F =freq <NL = NL> > devices. Vn3. The syntax for the two types of switches is Sname n+ n. CAS22 (June): 504509. Irvine. A.nc+ nc. The last element introduced in this chapter is the ideal transmission line defined by the following statement: Tname nl n2 n3 n4 Zo = ZO <TD iI.Vname Model <ON/OFF> One or more switch elements reference a . B. A linear depen G/Ename node+ node.value F/Hname node+ node.Vname value Vname is the name of the voltage source used to measure the controlling current. Ruehli.0. Johnson.POLY(ndim) Vname/ncnodes Po PI + <P2 <P3 . 1967. Pederson. E. CA: Author. Brennan. Department of Electrical Engineering and Computer Science. A. w. MicroSim.. Newton. and P.n4. R.Vincentelli. Proc.n2. D. of California. T. (April). and A. REFERENCES Branin. Ho. H. SangiovanniVincentelli. A. R. type F. > This chapter has detailed all SPICE circuit elements except semiconductor which are the subject of the following chapter. J. 1981 (August). Sangiovanni. Version 5. O. Berkely. L. IEEE 55: 20122013.nc+ nc. 1975.MODEL statement that defines the necessary parameters. K.
and the 73 .value2>. The element statement for any semiconductor device has the following general format: DEVname node] node2 <node3 . and M corresponding to the four kinds of semiconductor elements accepted by SPICE2.. Unlike the elements described in Chap.of .Three SEMICONDUCTORDEVICE ELEMENTS 3. SPICE2 was initially developed for integrated circuits (ICs). and SPICE3 and PSpice accept five different semiconductor devices. Q. These parameters are specified in a • MODEL statement. J. MODname is the name of a model statement that contains the parameter values. is identified by a Z in SPICE3 and a B in PSpice.. bipolar transistor (BJT).junction field effect transistor (JFET). Up to seven characters can follow to identify the element. the metalsemiconductor field effect transistor (MESFET). 2. > + <OFF> <IC=v]<.. semiconductor elements are defined by complex nonlinear BCEs characterized by a large number.v2. As mentioned in the beginning of Chap.. 2. one or more semiconductor devices can reference the same model. ... > MODname <value] <. .1 INTRODUCTION Semiconductor elements are presented together as a group because they have a common specification methodology. diode. and metaloxidesemiconductor field effect transistor (MOSFET). The additional semiconductor device supported in SPICE3 and PSpice. » The device name DEVname starts with one of four characters D. respectively. Two to four node numbers specify the connection of the semiconductor element terminals. SPICE2 supports four different semiconductordevice models.earameters.
The OFF flag is a toggle that initializes the device in the nonconducting state for the DC solution. The iterative DC solution process assumes that at the start all semiconductor elements are either conducting or on the verge of conduction. area. These initial conditions are optional and are seldom used. OFF devices are held in the cutoff state until convergence is reached. valuel. The rest of the information in a semiconductor element statement specifies the initial state of the device. The companion model statement for semiconductorelement statements has the following general format: • MODEL MODname MOD type <PARAMl=valuel <PARAM2=value2 . each semiconductor device has certain geometric characteristics. such as channel dimensions and areas. The optional IC specification defines the values of the terminal voltages of a semiconductor device at time zero. SPICE2. which precludes the computation of a DC bias solution. and MESFETs use only one parameter. to scale their geometry with respect to a unit device. More complete geometric information is available for MOSFETs because of the importance of this device type in LSI and VLSI circuits. MOSFETs require more detailed geometric information. Besides the process parameters. MODtype is one of seven recognized device types in SPICE2 and one of twelve in SPICE3. value2. at which point the constraint is removed and iterations continue until the first converged solution is confirmed or a new solution is found. Diodes. In other words. and so on. and PSpice support the following model types: D Diode model npn BJT model pnp BJT model nchannel JFET model pchannel JFET model nchannel MOSFET model pchannel MOSFET model model types: NPN PNP NJF PJF NMOS PMOS SPICE3 supports the following additional semiconductor R Diffused resistor model Diffused capacitor model c .74 3 SEMICONDUCTORDEVICE ELEMENTS commonality of model parameters can be traced back to the common process parameters. BJTs.. » MODname is a unique eightcharacter name in SPICE2 and a name of arbitrary length in SPICE3 associated with the parameter values defined in this statement. 6. see Chap. JFETs. The values defined as part of the IC option are used only when the UIC option is specified in the •TRAN statement. This specification is used only in conjunction with a transient analysis. a device initially assumed to be OFF may tum out to be conducting at the completion of the SPICE DC solution. SPICE3. This name is referenced by the device statements. that are unique and differentiate it from other devices having the same model parameters.. In all other circumstances these values are ignored. which are general model parameters.
or cathode. Four sets of semiconductor parameter names occur in SPICE2. for the DC solution. Sze 1981) are suggested. In this chapter each element is described together with its model parameters.1) (3. npn and pnp bipolar transistors. For the initial iterations of the DC bias solution. the keyword OFF initializes the diode in the cutoff region. The following sections describe the supported semiconductor elements. with VD = 0. eight in SPICE3. K. D identifies a diode and can be followed by up to seven characters in SPICE2. or nonideality coefficient. Only those parameter names must appear on the model statement that are assigned different values from the defaults built into the program. VDO is used as initial value only when the UIC option is present in the • TRAN statement. or anode. area defaults to 1. and T is the temperature in degrees Kelvin. The descriptions of both the element and the companion model are presented. and five in PSpice.DIODES 75 URe NMF Uniformly distributed RC model nchannel MESFET model pchannel MESFET model PMF PSpice also has a builtin model for an nchannel galliumarsenide FET. The variable area is a scale factor equal to the number of identical diodes connected in parallel. N is the emission. The BCE of the diode in DC is described by an exponential function: ID = IS(eqVD/NkT .1) where IS is the saturation current. called a GASFET.2 DIODES The general format of a diode element statement is Dname n + n. More than one model type can share the same parameters. called an LPNP.MODname <area> <OFF> < IC=VDO > The letter D must be the first character in Dname. A model statement with no values assigns the defaults of the specific type to that model name. Muller and Kamins 1977. for example. M 0Dname is the name of the model defining the parameters for this diode element. and nis the negative node. The parameters and supporting equations for the firstorder models are introduced. q and k are the electron charge and Boltzmann's .1. The keyword IC defines the voltage VDO at time t = 0 for a time domain analysis. several reference texts (Grove 1967. otherwise diodes are initialized at the limit of tumon. n+ is the positive node. The schematic symbol of a diode is presented together with its pnjunction SPICE implementation in Figure 3. For details on the semiconductordevice physics underlying the models described in this chapter. 3. The complete equations and list of parameters for semiconductor devices are contained in Appendix A and in more detail in Semiconductor Device Modeling with SPICE (Antognetti and Massobrio 1988). and an additional BJT model type for a lateral pnp.6 V.
The two model parameters.1 nDiode element. (h) Figure 3. can be easily derived as the slope and the intercept at the origin of the log ID versus VD plot. . these two constants and the diode temperature define the thermal voltage. The IV characteristic of the diode described by Eq. that is. 3.76 3 SEMICONDUCTORDEVICE ELEMENTS n+ Figure 3.1. of a semilogarithmic plot of Eq. 3. the diffusion charge and the depletion charge./ .38x 1022 JK1. see Appendix A for complete equations . is defined. constant. BV. IS and N. Vth = kT / q. 106 108 1010 1012 IS . equal to 1. (b) log ID versus YD. The breakdown current occurring when the diode is reversebiased is also modeled if the value of the breakdown voltage parameter. The variation in time of the diode current of a shortbase diode (Muller and Kamins 1977) is controlled by the two types of charge storage in a semiconductor pn junction.2.6x 1019 C and 1.1 is shown in Figure 3.2 1V characteristics of a diode: (a) ID versus VD. The current at the breakdown voltage is set to the value of parameter IBV. . respectively.
the diode is modeled as the conductance in the operating point gd and two capacitances CD and C] corresponding to the two charges. ID (3. such as silicon pnjunction diodes.. VJ. EXAMPLE 3. 1 dID dVD (3.DIODES 77 The diffusion charge QD is defined by QD = TT. The general format 'of the diode model statement is .5) (3. In the smallsignal AC analysis.2) .. C]: CJO VD/VJ)M (3. RS. and grading coefficient.1 Following are the SPICE descriptions for two diodes.MODELMODnameD <IS=IS <N=N . respectively.1 summarizes the diode model parameters introduced so far along with the default values assigned by SPICE2. where TT is the average transit time of minority carriers through the narrow region of a shortbase diode. other semiconductor junctions. and the energy gap. and Schottky diodes. gd . DIN' 0 1 DMOD OFF .3) C] = (l  (3. respectively. The scale'factor column indicates whether and how the parameter is scaled by the factor area appearing in the device statement. The latter is used to differentiate between different types of diodes.4) CJO. EG. and M are the zerobias junction capacitance.6) CD = TT. The depletion charge Q] at the pn junction is stored in a voltagedependent junction capacitanc~. » Table 3. two additional parameters needea for a' firstorder definition onhe diode model afetl'ie""parasiticseries resistance. builtin voltage.MODEL DMOD D .
3.MODEL DS1 D IS=lP CJO=O.7 M=O.5 EG=O. Only default parameters are used to model DIN. The fourth number.67 Ge 40 IOU Scale Factor area l/area area n s F V eV V A EG BV lEV 00 103 area DIN describes a protective diode at the input of another device that is normally off. nb.4 V. and its specification is optional.2P VJ=O. because of the absence of minority carriers.78 3 SEMICONDUCTORDEVICE ELEMENTS Table 3.69 Sbd 0. DSBD 11 17 DS1 IC=O. The value of EG corresponds to an aluminumsilicon contact.33 1. MODname is the name of the model defining the parameter values for this transistor. The keyword OFF initializes the transistor in the cutoff . base.69 The above two statements define a Schottkybarrier diode.6 0. and emitter nodes.IN 2P 0. The junction is initialized at 0. area defaults to 1. the substrate is assumed to be connected to ground. respectively. ns.1 Name IS N RS TT CJO VJ M Diode Model Parameters Parameter Saturation current Emission coefficient Ohmic resistance Transit time Zerobias junction capacitance Junction potential Grading coefficient Activation energy Breakdown voltage Current at breakdown voltage Units A Default 1014 I 0 0 0 I 0.3. Two BIT device types are supported. the value ofthe voltage drop when conducting.3 BIPOLAR JUNCTION TRANSISTORS The general form of a bipolar junction transistor (BIT) statement is Qname nc nb ne <ns> MODname <area> <OFF><IC= VBEO.11 Example IE16 1.5 1. is the substrate node. Q identifies a BJT and can be followed by up to seven characters in SPICE2. and ne specify the collector. NPN and PNP.11 Si 0. The scale factor area is equal to the number of identical transistors connected in parallel.4 . The schematic symbols for the two types of BITs are shown in Figure 3. nc. also note that TT = 0.5 100 O. VCEO > The letter Q must be the first character in Qname. If ns is not present.
8) = (1 . The currents flowing through the two sources.cxR)IR (3. are chosen as reference: Icc = IS(eQV8e1NF'kT . BJTs are initialized in the forward active region. The SPICE implementation of the EbersMoll model is a variant known as the transport version and is shown in Figure 3. a SPICE BJT model parameter. is the saturation current of the transistor. Ic.10) ICE = IS(eQV8c1NR.1) (3. which represent the transistor effect of the two backtoback pn junctions.1 DC Model The basic DC model used in SPICE to describe the BCEs of a bipolar transistor is the EbersMoll model (Muller and Kamins 1977). IE.3. By default. 3. The model shown in Figure 3. These two currents satisfy the reciprocity equation (3. which uses diode currents IF and IR as reference: (3. 3.IR IF + cxRIR + (1 . VSEO and VCEOat time t = 0 for the transient analysis. respectively.7) where the emission coefficients (see Eq.9) where IS. The keyword IC defines the values of the junction voltages. The injection version is commonly documented in textbooks and has been repeated above for comparison with the transport version.cxF)IF IEs and Ics are the saturation currents of the BE and BC junctions.kT . and Is can be expressed as functions of the two reference currents and the forward and reverse current gains.6 V and Vsc = 1.1) have been assumed to equall. with VSE = 0. VSEO and VCEO are used as initial values only when the UIC option is present in the • TRAN statement. of the commonbase (CB) connected BJT: Ic IE Is = = cxFIF .0 V for the DC solution. The three terminal currents of the transistor.4 is the injection version of the EbersMoll model.1) .BIPOLAR JUNCTION TRANSISTORS 79 region for the initial iterations of the DC bias solution. CXF and CXR.5.
4 EbersMoll injection model of an npn transistor. VEC IEB ICE f3R C Ic leT + + VEE Icc f3F ~ Figure 3. npn and pnp bipolar transistor C Ic vEC IE~ B IR a~R + VEE IF a~F Figure 3. .80 3 SEMICONDUCTORDEVICE ELEMENTS nc (C) nc (C) !I C tIc tIE ne (E) npn tIE ne (E) pnp Figure 3.5 EbersMoll transport model of an npn transistor.3 elements.
VBE and VBC. The suffixes F and R in many SPICE parameter names indicate the region of operation. of a bipolar transistor in the commonemitter (CE) configuration. RB. respectively. and emitter regions.VBC' The reverse Early voltage. the transistor can operate in the following four modes: Forward active Reverse active Saturation Cutoff VBE VBE VBE VBE > 0 and VBC < 0 < 0 and VBC > 0 > 0 and VBc > 0 < 0 and VBC < 0 In most applications the transistor is operated in the forward active. VBc) plane where the extrapolations of the linear portions of all Ic characteristics meet. The Early voltage is the point on the VBC axis in the (Ic. or linear. The IV characteristics described by Eqs.ICE 1 f3R Ie = ICE . These characteristics are ideal. has a similar interpretation for the reverse region.6 for positive values of VBE and V CE. VAF and VAR.11 are shown in Figure 3.11) IB where = f3F Icc + f3R ICE = 1 IBC + IBE ICT = Icc . The finite output conductance of a BJT is modeled in SPICE by the Early effect (Muller and Kamins 1977) implemented by two parameters.ICE f3F and f3R in the above equations are the forward and reverse current gains. SPICE parameters BF and BR.ICE f3R + 1 f3R = ICT . Depending on the values ofthe two controlling voltages. 3. region.Icc f3F + 1 f3F 1 = ICT 1 . and RE.BIPOLAR JUNCTION TRANSISTORS 81 The three terminal currents assume the following expressions: Ic = Icc . . VAR. and in some situations in the saturation region.7 for the Ic = !(VCE) characteristics: VCE = VBE . This geometric interpretation of the Early effect and its SPICE implementation is shown in Figure 3.Icc f3F (3. ignoring the effects of finite output conductance in the forward and reverse regions and the parasitic series resistances associated with the collector. base. these resistances are modeled by parameters RC. For most practical applications VAF is important and VAR can be neglected.
' VAF ••I Figure 3.2mA « E 200 .3mA la= 400 JlA 100 o 200 400 VeE' mV 600 800 1000 Figure 3.6 BJT IV characteristics described by the EbersMoll model.• () la= 1. VAF..0 mA 400 la=3.7 Early voltage parameter.82 3 SEMICONDUCTORDEVICE ELEMENTS 500 la= 4. .1mA 300 la= 2. ...
are associated with the mobile carriers. modeled by . ICE TF and TR are the forward and reverse transit times. and Qcs. the builtin potential.{3/CE = ICT . The depletion charges can be derived using the nonlinear equation that defines the depletion capacitance. collector. QJC. The three voltagedependent junction capacitances are described by the following functions: CJE (l .8.2 Dynamic and SmallSignal Models The dynamic behavior of a BIT is modeled by five different charges. 3.3.4. QBC. denoting the emitter.ICE) ( 1 . The SPICE largesignal implementation of the three depletion charges is according to Eq. or substrate junction. 3. The five charges are consolidated into three: QBE. Ic and ICT in Eqs. respectively.BIPOLAR JUNCTION TRANSISTORS 83 With the addition of the Early voltage. CJ.VAF . VJX.11 are modified as follows: Ic = (Icc . QJE. C. the zerobias junction capacitance.VBdVJE)MJE CJC (l .14) CJS (l . which includes QDC and QJC. of the injected minority carriers through the neutral base.IBc VBC VBE) I (3. These are the diffusion charges represented by the current sources Icc and ICE in the EbersMoll model. The diffusion charges are modeled by the following equations in the largesignal transient analysis: QDE QDC = TF. which includes QDE and QJE.VAR . The nonlinear BIT model in SPICE including charge storage and parasitic terminal resistances is depicted in Figure 3. Eq. Two charges. Icc (3. and collectorsubstrate. QDE and QDC. or S. X stands for E. of a pnjunction. respectively.VBclVJC)MJC (3. which defines the charge QJ. QJs. 3.VcS/VJS)MJS Each junction can be characterized in SPICE by up to three parameters: CJX. basecollector.3. the grading coefficient.12) 3. The other three charges model the fixed charges in the depletion regions of the three junctions: baseemitter. and MJX.13) = TR.
15) = = = = =  1 To alCT aVBC = alB aVBC alc . base pushout. Figure 3. the collectorsubstrate capacitance. also known as the hybrid1T model. The complete model includes secondorder effects.84 3 SEMICONDUCTORDEVICE ELEMENTS Ccs.8 Largesignal SPICE BJT model.aVBC . The linearized smallsignal model of a BJT. . and temperature effects.giL gmF . such as f3F and 'TF dependency on Ie.gmR alc aVBE .5 are replaced by the following linear resistances (conductances) and transconductances: gn giL gmF gmR gm 1 = Tn 1 TiL alCT aVBE go alB aVBE alB aVBC 1 dlcc f3F dVBE 1 dIcE f3R dVBc (3. The complete equations and model parameters are summarized in Appendix A.8 is a firstorder representation of the complete GummelPoon BJT model available in SPICE and is sufficiently accurate for many applications.go nc (C) Re RB nb(B) B' VB'C' + QBe C' + VB'E' ~ IB QBE ~ Ie E' ns (8) f" RE ne (E) Figure 3. The nonlinear diodes and the current generator lCT in Figure 3.9. is shown in Figure 3.
' C' Re ne (C) B' nb (B) r~ C~ gmvb'e' ~ ro I • E' fa ns (8) ne (E) Figure 3.= 0 VAF VAF gmVth 1 go Ie .Vee in the second term.17) 1 g~ 00. gmFvbe qIc gm = gmF = ~Fg~ r~ =rlJ. 3. if these resistances are present.= = NF.16) f where Vbe has been replaced by Vbe .BIPOLAR JUNCTION TRANSISTORS 85 C~ . terminal voltages VB'E' and VB'creplace VBEand VBC' ' The smallsignal AC collector current ie. . can be expressed from Eqs.kT (3.~ ro. The above smallsignal parameters have been derived assuming no parasitic terminal resistances Re.9) as (3. ~F gm glJ.15 and the hybrid7T model (see Figure 3. RE.9 Smallsignal SPICE BJT model.12 and 3. In the forward active region the smallsignal equations assume the more commonly known expressions (Gray and Meyer 1993): ie = gm Vbe :. andRE.
20) 3. The junction capacitances are defined by Eqs.9) the two types of capacitances for the BE and BC regions are consolidated in C7r and CM. must be specified. CDE and CDC: (3.3. Table 3. The diffusion charges are modeled by two diffusion capacitors.MODEL MODname NPNIPNP <IS=IS <BF=BF .19) CM = CDC + CJc An important characteristic of a BJT is the cutoff frequency. corresponding to QBE and QBC.86 3 SEMICONDUCTORDEVICE ELEMENTS In smallsignal AC analysis chargestorage effects are modeled by nonlinear capacitances. (3.15).18) CDC = dQDC dVBC = alcT TRaVBC = TR'gmR where gmF and gmR are the forward and reverse transconductances of the BJT (Eqs. EXAMPLE 3.. 3.5. respectively. fr. 3. indicating the transistor type.6. QX12 14 15 21 QMOD IC = 0. In the smallsignal BJT model (Figure 3.14. » In every model one of the keywords NPN or PNP.MODEL QMOD NPN BF=200 RB=100 CJC=5P TF=10N ..2 The following are two BJT specifications. where the current gain drops to unity.3 Model Parameters The general form of the BJT model statement is .2 summarizes the model parameters introduced in this section together with the default values assigned by SPICE2. fr can be expressed as a function of the smallsignal parameters: (3.0 .
33 2P 0.5 2P 0.5 100 250 200 2 100 IN lOON 2P 0. Generally.8. QFF2 is specified OFF in order to speed up the solution of the DC bias point.MODEL QQ PNP IS=lP BF=50 CJE=lP CJC=2P QFFl and QFF2 are the two transistors of a flipflop. The measurement techniques leading to the SPICE parameters of bipolar transistors are presented in detail by Getreu (1976). 6).75 0 I/area I/area I/area area area area QX12 is initialized at VBEO = 0. model parameters must be derived. For more detail on flipflop initialization. however. This topic is addressed in the following pages.75 0.5 Scale Factor area Saturation current Forward current gain Reverse current gain Forward emission coefficient Reverse emission coefficient Forward Early voltage Reverse Early voltage Collector resistance Emitter resistance Base resistance Forward transit time Reverse transit time BE zerobias junction capacitance BE builtin potential BE grading coefficient BC zerobias junction capacitance BC builtin potential BC grading coefficient CS zerobias junction capacitance CS builtin potential CS grading coefficient V V 11 11 11 s s F V F V F V 0 0 0 0 0 0 0.6 0. its switching time is governed by the BC junction capacitance and the forward transit time.BIPOLAR JUNCTION TRANSISTORS 87 Table 3. The characteristics of IC transistors are derived from a test structure built on the same wafer. The same measurements can be used to characterize discrete transistors if lab equipment and the transistor of interest are available.33 0 0.6 0.6 V and VCEO = 5. Defaults are used for the remaining parameters.2 Name IS BF BR NF NR VAF VAR RC RE RB TF TR CJE VJE MJE CJC VJC MJC CJS VJS MJS BJT Model Parameters Parameter Units A Default 1016 100 I I I 00 00 Example lEI6 80 3 2 1. and how the SPICE parameters can be derived for physical transistors becomes an important question. A different approach is necessary for discrete . For some standard parts SPICE parameters are available from semiconductor manufacturers because of the widespread use of SPICE simulation in circuit design.33 0 0.6 0.0 V in a transient analysis (see Chap. see Example 4. QFFl 1 3 0 QQ QFF2 2 4 0 QQ OFF .75 0.
Next. they . Simulate the Ie = f(VeE. 1015 A (3. Choose hFE1 = 150 at Ie = 1 rnA hFE2 = = 200 at Ie 240 at Ie = = 10 rnA 100 rnA = hFE3 The average of these three values results in BF 190.88 3 SEMICONDUCTORDEVICE ELEMENTS transistors when the only information available is a data sheet. 3. Obtain from Eqs. hFE. which is the default value in SPICE (see Table 3. Because BF is a constant and because hFE dependence on Ie is not supported in the firstorder model. 1988) for electrical characteristics. smallsignal. The extraction of the main parameters from a data sheet is outlined in the following example.11 a relation between Ie. .10 are then used with N F = 1 to obtain the following expression for IS: IS = Is (Ie + _l_)eVBEsat/Vth 1CXR = 0. many transistor data sheets contain graphs of several electrical quantities. because the graphs represent a typical device. Several categories of characteristics are included.015. Solution The information needed for extracting the model parameters is found in the MPS2222 data sheet.5.3 Derive the SPICE DC model parameters for the MPS2222 npn transistor. From the graph entitled ON Voltages. provided as minimum or maximum values. similar to a 2N2222. namely the OFF.10.85 V. This approximation is of no consequence unless the transistor is operated in the reverse region most of the time. as a function of Ie for a set ratio lei Is. The first parameter to be extracted is the saturation current. under electrical characteristics. an average value should be chosen for hFE over the Ie range that the transistor is expected to operate. and VSEsat by substituting the current ICE from the Is equation into the Ie equation. 3. In addition to these data. or BR = 1.2). EXAMPLE 3. equal to 10 for this transistor. we derive a value for BF.should be used as primary sources of characteristic data. we obtain the BE voltage in saturation. and switching characteristics. VSEsat. Eqs. Use the Motorola Semiconductors Data Book (Motorola Inc.21) Is In the above calculation it has been assumed that CXR = 0. Choose Ie = 150 rnA and the resulting VSEsat = 0.14. When graphs are available. Figure 3. This can be obtained from the plot of the DC current gain.0258 = 1. 12eO. the current gain factor. as a function of Ie. Is) characteristics with SPICE. ON. IS. Is.85/0.
VCE = 10 Vde. VCE = 1. A* CollectorEmitter Voltage CollectorBase Voltage EmitterBase Voltage Collector Current  Total Device Dissipation @TA = 25'C Derate above 25'C Tota' Device Dissipation @ TC = 25'C Derate above 25'C Operating and Storage Junction Temperature Range THERMAL CHARACTERISTICS Characteristic Thermal Resistance.MAXIMUM RATINGS Rating Symbol VCEO VCBO VEBO Continuous IC Po Po TJ. VCE = 10 Vde)(1) CollectorEmitter Saturation Voltage(1) (lC = 150 mAde. Figure 3. TA (VCB = 50 Vde.3 1.0 Vde) MPS2222A ICBO MPS2222 MPS2222A MPS2222 MPS2222A lEBO MPS2222A IBL 3. 'B = 50 mAde)  • Also available as a PN2222.3 200 Unit GENERAL PURPOSE TRANSISTORS NPN SIUCON 'c/w 'c/w ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted.0 Unit Vde Vde Vde mAde mW mWrC Watts mWrC MPS2222.0 6. TA = 55'C) (lC = 150 mAde. 'E = 0) (VCB = 50 Vde.1 2 CASE 2904. IE = 0) (VCB = 60 Vde.0 Vde. Junction to Ambient 'c .0 600 625 5.5 12 55 to + 150 40 75 6.0 mAde. IB = 15 mAde) hFE 35 50 75 35 100 50 30 40 VCE(sat) MPS2222 MPS2222A MPS2222 MPS2222A MPS2222A only    300 MPS2222 MPS2222A Vde 0.:~"=' 1 Emitter 3 Symbol ReJC ReJA Max 83. VEB(offl V(BR)CEO MPS2222 MPS2222A V(BR)CBO MPS2222 MPS2222A V(BR)EBO MPS2222 MPS2222A ICEX 3.4 0.0 Vde)(1) (lC = 500 mAde. VCE = 10 Vde) (lC = 1.0 60 75 30 40   Vde 10 Vde Vde =  nAde ~de Collector Cutoff Current (VCB = 50 Vde. IE = 0) EmitterBase Breakdown Voltage (IE = 10 ~de.A. IE = 0. VCE = 10 Vdel (lC = 10 mAde. TA Emitter Cutoff Current (VEB = 3.) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS CollectorEmitter Breakdown Voltage (lC = 10 mAde. Tstg MPS2222 MPS2222A 30 60 5.01 0. VCE = 10 Vde)(1) (lC = 150 mAde.01 10 10 10 20 nAde nAde =  DC Current Gain (lC = 0. IC = 0) Collector Cutoff Current (VCE = 60 Vde. VCE = 10 Vde) (lC = 10 mAde.1 mAde. 'B = 0) CollectorBase Breakdown Voltage (lC = 10 ~de.10 MPS2222 data sheet.0 1. VEBloffl ON CHARACTERISTICS = =   125'C) 125'C)  0. STYLE 1 TO92 (TO226AA) .6 1. 89 . IC = 0) Base Cutoff Current (VCE = 60 Vde.0  (lC = 500 mAde. IE = 0.0 Vde) MPS2222A 5. Junction to Case Thermal Resistance.
0 kHz) Collector Base TIme Constant (IE = 20 mAde.4 V .TURNQFF TIME v _I 1+16V~ 0 1. IB1 = IB2 = 15 mAde) (Figure 2) td tr ts tf 10 25 225 60 ns ns ns ns (1) Pulse Test: Pulse Width'" 300 /LS.8 MHz) Noise Figure (lC = 100 !LAde. and oscilloscope.0 kHz) (lC = 10 mAde. VCE = 10 Vde.". f = 100 MHz) Output Capacitance (VCB = 10 Vde.6 2.0 mAde.TURNON TIME +30 200.10 . . f = 1.ELECTRICAL CHARACTERISTICS (continued) (TA Characteristic = 25°C unless otherwise noted.5 Vde. . IB = 15 mAde) 0. VCE = 10 Vde.0 kHz) (lC = 10 mAde.5 Vde. TIME EQUIVALENT TEST CIRCUITS FIGURE 2 .0 MHz) Cibo MPS2222 MPS2222A hie MPS2222A MPS2222A hre MPS2222A MPS2222A hfe MPS2222A MPS2222A hoe MPS2222A MPS2222A rb'Ce MPS2222A NF MPS2222A 5.Duty Cycle'" 2.Bandwidth Produet(2) (lC = 20 mAde.) Symbol VBE(sat) MPS2222 MPS2222A MPS2222 MPS2222A Min Max 1. VCE = 10 Vde. f= 1.hunt capacitance of test connectors. (2) IT is defined as the frequency at which Ihfel extrapolates to unity. f = 1.0%.S. VCE = 20 Vde.0 kHz) Voltage Feedback Ratio (lC = 1.0 kO. IC = 150 mAde. ___J < 10 pF Scope < 4 ns Total . SWITCHING FIGURE 1 .0 to 100 . VCE = 10 Vde.0 0. VCE = 10 Vde. VCE = 10 Vde. VCE = 10 Vde. IC = 150 mAde.0 mAde. IB1 = 15 mMe) (Figure I) (VCC = 30 Vde. VCE = 10 Vde. ___ J _L_ < 10pF Rise Time 14 V  I jig.0 kHz) SWITCHING CHARACTERISTICS MPS2222A only Delay TIme Rise Time Storage Time Fall Time k{}     (VCC = 30 Vde. f = 1. RS = 1.0 25 35 200 150 4. f = 1. VCB = 20 Vdc.0 ps dB 50 75 300 375 ILmhos 2. <20n5 :Cs. VCE = 10 Vde.0 kHz) (lC = 10 mAde. f = 1. . +30 DUTY v 200 CYCLE"'2% _l_ T:Cs. IB = 50 mAde) IT SMAllSIGNAL CHARACTERISTICS MPS2222 MPS2222A Cobo 250 300 CurrentGain .0 mAde.0 kHz) (lC = 10 mAde.0 MHz)   Input Impedance (lC = 1. f = 1. f = 31.0 0. f = 1.90 (continued) .0 mAde.0 1.3 1. VBE(off) = 0. Figure 3.0 Unit Vde BaseEmitter Saturation Voltage(1) (lC = 150 mAde. IC 8.0 kHz) Output Admittance (lC = 1.0 4. f = 1.2 2. f = 1.0 kHz) SmallSignal Current Gain (IC = 1.0 30 25 MHz  pF pF = = 0.6  (lC = 500 mAde. IE Input Capacitance (VEB = 0. f = 1.25 8. lk lN914 .25 X 104 8.
COLLECTOR CURRENT (rnA) Figure 3..0 ....005 0.0 k IC.. . 2......0 2...•...0 7.. 300 500 7.11/S If If): ~~~c 1"'_ g w 30 20 10 7.. " I •••••• 70 50 30 '" .0 10 20 30 50 70 100 200 300 500 IC.0 1\ ..!" .. 200 10 .02 0.~50C .S 0.... ..• '" . ..•.1 0. COLLECTOR CURRENT (rnA) ..01  \ I' 0.DC CURRENT GAIN •• •.....••.. ..:: •.0 2. I  ~ c ~ I I ...0 10 20 30 50 IS..5 1. A FIGURE 1000 700 500 TJ=1250C I . I •.•. SASE CURRENT (mAl FIGURE 200 5 .7 1.MPS2222.0 3...0 rnA lOrnA 150mA 0..0 5...1 I '..0 O.0 5.3 0.0 5.. COLLECTOR CURRENT (mAl FIGURE 4 .:: II ..0 5...6 l IC = 1...@l VCC = 30 V 'd@lVESloffl = 2..3 0.TURN'()FF TIME VCC = 30 V IC/IS = 10 100 70 50 t'..5 0.0 5. .0 3..0 V_ 'd@lVES(off) = 0 100 c w FIGURE 6 .0 VCE=1..0 7.COLLECTOR SATURATION REGION TJ = 25°C 1..2 0..0 10 20 30 50 70 100 200 300 500 700 1..2 o 0..TURN'()N TIME ICIIS = 10 TJ = 25°C 500 300 200 '.4 1\ \ \ 500 rnA \ \ \ 0...05 0.••....•.0 5....03 0.2 0..••• "'7'" 0. IC....0V VCE=10V I I I I III 7.10 (continued) 91 ....l 25°C 3 . '" '" B u z 300 200 100 70 50 30 20 10 0. 20 3.I.0 10 20 30 50 70 100 .1 i"..
0k 5.3 0.0 3.: w 1\ l/ )' ~ 50 100 500 .2 0.CAPACITANCES 30 20 FIGURE 1Q .2 0.1.. 0.0 10 20 50 100 I.0k .0 I I 10 20 30 REVERSE VOLTAGE (VOLTS) 50 1. 200 500 1. COLLECTOR CURRENT ImA) FIGURE 11 . .. .0 V / 1/ J J / I I I j IC=50.. ~ w <.MPS2222.5 1.0 2..0 0.0 5.1 0...5 1..0 .0 1/ ".0 5.b + I t.0 :> <.05 0.5 1.5 o 0. 3: z '/ " .0 5.4 f:: w c I.0 II .0 'IOO.0 5. ~ w 8.t'1J.0k 2.FREQUENCY EFFECTS 10 10 FIGURE 8 . rr C.A 1.0 0 z ~.TEMPERATURE COEFFICIENTS +0.: ~ o 4.CURRENT... COLLECTOR CURRENT (mAl Figure 3. 0. c z . 10 7.0 2.1 11111 0.•• .0 10 II 20 50 100 200 500 0."ON" VOLTAGES 1..250C 300 200 I I ~ ~ w Z g g: or :.02 o a 0. 0. COLLECTOR CURRENT (mA) IC. '' ~ .0 k IC.0 w ~ <.0 RIN8forV8E ./ 10k 20k 50k 100.5 1.SOURCE RESISTANCE EFFECTS II 1111111 t.2 0.A 6. . > >' .0 FIGURE 12 .0 Ccb r.0 V 0... '' . c5 .0 ~ 6. SOURCE RESISTANCE 10HMS) FIGURE 9 . V8Elon)@VCE = 10 V ~ .6 ~ E :.0mA I '" 4.GAIN BANDWIDTH PRODUCT ~ I I .01 0.0 2.5 1.::.8 '" ':. :> VCE = 20 V TJ..0 1.0 10 20 30 50 70 100 IC.A '" .0 2.2 0...0 2.0 10 20 50 100 200 500 1. A FIGURE 7 .0 3.5 2.1 0.1 0.0 z ~.. z 2.2 VCElsat) r.0 5.•. FREQUENCY 1kHz) RS. z 2.0 2.10 (continued) 92 ..0 ./ / 100 1/ 70 ~ / '" ~ '" '" B ~ 50 3. .0 ~H~ I III II 1111 8.::. '' 0.o IC/18' 10 2.0 5.5 III I RINCfor VCElsatll ~ ~ ~ Il 0..0 7.
14F BF=190 VAF=100 * WI MAX VALUES. and hoe.9M . This parameter can be calculated from the smallsignal characteristics. or hybrid parameters. Vin and io relate to iin and Vo through the hybrid parameters hie. The hybrid model is based on a twoport representation of the transistor with iin and Vo as the independent variables. For a transistor in a CE configuration.10 V Ic 102 A = 100 V The data for hoe are measured at V CE = 10 V.MODEL Q2N2222 NPN IS=5. as in Figure 3.7.PRINT DC I (VCl .22) hoe is the data sheet parameter used for evaluating VAF.11. Both a minimum and a maximum value are listed for two values of Ic. Then VAF is computed from geometric considerations.VCE = 102• 106 mho .V CE curve at the measured Ic and V CEo Ideally the extrapolations of the two tangents to the Ic.DC VC 0 10 0. The setup is shown in Figure 3.V CE curves intersect at V CE = . The smallsignal value of hoe is the slope of the Ic.END . 1 rnA and 10 rnA.MODEL Q2N2222 NPN IS=1.V CE characteristics of the BIT. h fe.4M 4M 0.5 IB 0.BIPOLAR JUNCTION TRANSISTORS 93 The next parameter to be evaluated is the Early voltage for forward operation. VAF = hoe .VAF.25E14 BF=190 VAF=100 RC=3.7. The corresponding SPICE input follows: IV CHARACTERISTICS OF 2N2222 Q1 2 1 0 Q2N2222 IE 0 1 . A reasonable estimate for VAF is obtained by first choosing a value between Min and Max for hoe at the higher current. which are given as h parameters. A transistor can therefore be described by the following hybrid equations: Vin + hrevo io = hfeiin + hoevo = hieiin (3.4 RB=37 . We have now obtained the main BJT SPICE parameters for simulating the DC behavior of transistor MPS2222. VAF. as shown in Figure 3.OP . we can describe a measurement setup for displaying the I c. NO GRAPHS . if this current is not outside the range of the application. With the information presented so far about SPICE.075M VC 2 0 10 * * * * * * PARAMETERS DERIVED BY HAND WI TYPICAL VALUES FROM GRAPHS *. hre.
3 V 0. are obtained from the saturation characteristics.12.94 3 SEMICONDUCTORDEVICE ELEMENTS Figure 3. These values are too high for following the extraction procedure outlined above.IC2 1.35 A = 3. the validity of the model can be verified for a few operating points given in the data sheet.2 V 0.4M 4M 0. VCEsatM and VBEsatM.40 (3.24) The approximation of attributing the VBEsatM difference to an ohmic voltage drop is supported by the fact that it takes approximately only VBE = Vth = 26 mV to increase IB from 15 rnA to 50 rnA. A slightly different approach must be followed if no graphs are available and all parameters must be derived from the electrical characteristics data. Note that the different curves are equally spaced in the firstorder model based on a constant value of h FE.5 IB 0. this statement is described in detail in the following chapter. the difference in VBEsat can be attributed in large part to the voltage drop across the parasitic base resistance.VCE characteristics. The two maximum values. the value of which is RC = V CEsatMl  V CEsatM2 ICl .9M which defines the range over which the VC supply and the base current source IB are swept. IB) characteristics simulated by SPICE with the above parameters is shown in Figure 3. The plot of the Ic = f(VCE.DC VC 0 10 0.035 A r\ = 37 H (3. equal to BF. .23) Similarly. resulting in a resistor value RB = VBEsatMl IBI  VBEsatM2 IB2 1. The difference in VCEsatM for the two values of Ic can be attributed to the ohmic collector resistance. The only statement that has not been defined so far is . No I C = f (V CE. I B) characteristic is available from the data sheet for comparison with the above simulated curves.11 Measurement setup for !c. RB. RC.
are derived from the former characteristics. the highest. which lists the minimum values of hFE for several values of Ic.69 V = = VCEsatMI = = = ICleVBEsatM/Vth 0.15.BIPOLAR JUNCTION TRANSISTORS 95 IB=4.10 and 3.5.74 V 0. I (VCE. 3.0 IB=1.0 o Ic = 10 Figure 3.25.• v 200. In) characteristics of the MPS2222 npn transistor simulated Now IS can be derived from Eqs. TF.1mA 600. closer to the minimum.11 and the corrected values of and V CEsatM: VBEsatM VBEsatM VCEsatM IS = VBEsatMI  RB.3mA •. RC' IBI ICI = 0. Choose hFEI in the range between Min and Max. Calculate hFE2 and hFE3 at two other values of Ic such that they represent the same multiple of the corresponding minimum values as hFEI• BF results as the average of the three midrange values of hFE: BF = 110.0mA IB=3.1013 A 5. The junction capacitances. BF can be estimated from the ON characteristics table. The chargestorage characteristics can be derived from the plots of capacitances versus reverse voltage and switching characteristics. Usually both a minimum and a maximum hFE value are given for a single Ic value. is estimated from the latter.1014 A In the absence of the DC current gain plots.0 IB=400~A 200.0 IB = 2. The three characteristic parameters of a junction capacitance. and the transit time. . CJC and CJE.3..12 by SPICE.2mA 4: E 400. The extraction ofVAF is the same as the above.
= I (VCE. JFETs are initialized at the threshold voltage. IB) characteristics similar 3.13.7 NE=2.7 + + + ISE=70. . with VGS = VTO and VDS = 0.75 A number of parameters that are not in Table 3. area is a scale factor equal to the number of identical transistors connected in parallel. Two JFET models are supported.3333 FC=.. should be evaluated from a plot of log Cj versus I (Vj). ng. from MicroSim Corp. and source nodes. area defaults to 1. see Eqs. J identifies a JFET and can be followed by up to seven characters in SPICE2. VDSOand VGSOare used as initial values only when the UIC option is present in the • TRAN statement. MODEL statement because Parts uses the complete GummelPoon model in the extraction. MODname is the name of the model that defines the parameter values for this transistor.11 VAF=90. For transistor MPS2222. from Symmetry Design Systems (1992). respectively. ' The above parameter extraction approach can be automated by writing a small program for repeated use.348 IKR=O RC=O CJC=2P TR=10N TF=1N XTB=l. MODPEX.12. VDSO and VGSO. Another parameter extraction package.and highcurrent behavior.14. and ns are the drain. The package Parts.4 JUNCTION FIELD EFFECT TRANSISTORS (JFETS) The general form of a junction field effect transistor (JFET) statement is Jname nd ng ns MODname <area> <OFF> <IC= vDSO. nchannel (NJF) and pchannel (PJF). MlX.3333 VJE=. The keyword IC defines the values of the terminal voltages. nd.vGso> The letter J must be the first character in lname. which is a straight line. such as low. t time t = 0 in a timedomain a analysis. 78P IKF=3.5 CJE=5P ITF=O VTF=O XTF=O) 08/02/91 AT 13:59 BF=223. gate.2 are present in the above. ~" ~ Exercise Verify that the parameters from Parts result in Ic to those in Figure 3.75 MJC=. 3. can scan a data sheet and generate SPICE parameters. The schematic representations of the two types of JFETs are shown in Figure 3.MODEL Q2N2222 NPN(IS=15. Secondorder effects can be added. By default. computes SPICE parameters for all the supported semiconductor devices from data book characteristics. 837 VJC=. Parts finds the following DC parameters using typical data: * Q2N2222 MODEL CREATED USING PARTS VERSION 4. The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution.0 for the DC solution.96 3 SEMICONDUCTORDEVICE ELEMENTS ClX. and VlX.01F XTI=3 EG=1. 5 BR=1 NC=2 ISC=O MJE=.03 ON * W/ VALUES FROM GRAPHS OR AVERAGED * .
and therefore the pn junction current is negligible.VTO (3.VDs)(l + LAMBDA. characterized by the saturation current IS. The quadratic ShichmanHodges model (Shichman and Hodges 1968) is used in SPICE to solve the BCEs. junctions.3. the transconfactor. BETA. OD. VDS VDs(2(VGS . VDS) fora < VDS < VGS . (VGS . introduced in Sec.VTO) . respectively. the drain and the source swapping roles. and linear.3.1. 3.13 n. and LAMBDA CGD (l . IDs. respectively.VTO::::. is defined by the following three equations for the three regions of operations.and pchannel JFETs.25) are the threshold. The current IDs flows in the opposite direction. The drainsource current. The dynamic behavior of a JFET is modeled by two charges associated with the gatedrain. voltage. the behavior of the JFET is symmetrical. VT 0 I_BETA DS  { BETA. and gatesource. ductance CGS (l .VGD/PB)O.5 . respectively: a for V GS ::::. or pinchoff. The gate pn junctions are reverse biased. 3.VGs/PB)O. These charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eq. There is an additional current component due to the pn junction current.VTO)2(l + LAMBDA. VDS) fora < VGS . The above equations are valid for VDS > O. and output conductance factor in saturation. saturation. OS.5 (3.26) VTO. Note that LAMBDA is measured in VI and is equivalent to the inverse of the Early voltage for the BJT. If VDS changes sign.JUNCTION FIELD EFFECT TRANSISTORS (JFETS) 97 nd(D) t ng (G) IDS + ns (8) nchannel ns (8) pchannel Figure 3. cutoff. VGS is replaced by VGD. and VDS is replaced by its absolute value in the above equations.
and 3. 3.s' must be used in Eqs. . and builtin gate junction potential.14 Largesignal nchannel JFET model. The expression of IDS appropriate t.27 when RD and RS are nonzero.14 and the smallsignal model in Figure 3.98 3 SEMICONDUCTORDEVICE ELEMENTS CGS. In the largesignal timedomain analysis the gate charges are computed from Eq.26. 3. zerobias gatedrain capacitance.o the region of operation (Eqs. nd(D) ns (8) Figure 3. respectively. These capacitances are used in the smallsignal analysis.25) must be used when deriving gm and rds' Note that in nOmlal operation the GD and GS diodes are reverse biased and the corresponding smallsignal conductances can be neglected. and PB are the zerobias gatesource capacitance. 3. The largesignal JFET model is shown in Figure 3. 3. The transconductance gm and the drainsource resistance rds of the smallsignal model are defined as follows: gm = = dIDs dVGS 1 rds (3.4 using Eqs.26. 3.25.15.27) dIDs dVDs gds VGS and VD. CGD.
0E. they are normally on. Table 3. is signsensitive. or pinchoff. Table 3. JFETs operate in depletion mode.16 Scale Factor area l/area l/area area area area n n F F Y A .0 104 0 0 0 0 0 1 1014 Example 2. must be specified. Because of a bug in all recent versions of SPICE2.15 Smallsignal JFET model.0E3 1. Therefore VTO is negative for nchannel devices (NJF) and should be positive for pchannel devices (PJF).3 summarizes the model parameters introduced so far. with the corresponding default values assigned by SPICE2.JUNCTION FIELD EFFECT TRANSISTORS (JFETS) 99 D' nd(D) ns (S) Figure 3. The general form of the JFET model statement is •MODEL MODname NJF/PJF <VTO=VTO <BETA=BETA ... VTO.0E4 100 100 5P IP 0. » In every model statement one of the keywords NJF or PJF. the sign of VTO for a depletion pchannel JFET should be entered as negative. VTO for a pchannel JFET is defined with the same sign as for an nchannel JFET.5 1.6 1. indicting the transistor type. in other words. voltage.3 Name YTO BETA LAMBDA RD RS CGS CGD PB IS JFET Model Parameters Parameter Threshold (pinchoff) voltage Transconductance parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zerobias GS junction capacitance Zerobias GD junction capacitance Gate junction potential Gate junction saturation current Units Y AYZ yI Default 2. This discrepancy is present in SPICE3 as well as PSpice. The threshold. however. that is.
27.5 V < VDS From Eqs.LAMBDA(VGS .5 V)2 2 = 0.MODEL Mom PJF VTO=3 RD=20 RS=20 EXAMPLE 3. in the data book. BETA is computed as a function of !DSS' BETA = .VTO)2 = Yos (3.25.4 J1 20 1 21 Mom . the smallsignal DS conductance. VTO. VGS(off). voltage.3 RD=20 RS=20 Jl is a normallyon nchannel JFET with parasitic series drain and source resistances. is readily available from the commonsource transfer characteristics plot. we choose to derive the SPICE parameters from graphical data if such graphs are available.28) . the commonsource output admittance in the data sheet: gds = BETA . which is the average between the minimum and maximum values provided by the data sheet. The threshold. defined by Eqs. 3. and therefore the transistor is saturated. !DSS' The measurement in the data book is taken at VDS = 15 V.5 V. according to Eqs.VTO)2 4mA (3. which measures the output conductance in saturation. MODEL Mom NJF VTO=. The transconductance parameter BETA can be obtained from the zerogatevoltage drain current. data book the SPICE DC model parameters Solution As in Example 3. For the 2N4221 this value.3. 3. 3. or pinchoff.327 rnA V !DSS has been set at 4 rnA.100 3 SEMICONDUCTORDEVICE ELEMENTS EXAMPLE 3.The last parameter of importance for DC is LAMBDA. is referred to as the gate source cutoff voltage. to Yos. the value is VTO = VGS(off) = 3. .25: VGS . This value is obtained from equating the expression of gds.VTO = 3. A normallyon pchannel JFET that conducts the same current as Jl in similar bias conditions is described by the following MODEL statement: . !DSS (VGS .5 Derive from the Motorola semiconductor for the 2N4221 nchannel JFET. the channel modulation parameter.
= SPICE3 and PSpice additionally support a metalsemiconductor FET.16.4. or MESFET. VI ID These values are used in Example 4. ns. in the following chapter.5 METALOXIDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) The general form of a metaloxidesemiconductor field effect transistor (MOSFET) statement is .METALOXiDESEMiCONDUCTOR FiELD EFFECT TRANSISTORS (MOSFETs) 101 and LAMBDA = Yas 10. VBSO> The letter M must be the first character in Mname.6. Mname nd ng ns nb MODname «L=>L> «W=>W> <AD=AD> <AS=AS> + + <PD=PD> <PS=PS> <NRD=NRD> <NRS=NRS> <OFF> <IC=VDSO. and nb are four numbers that specify the drain. Two MOSFET models are supported. . gate. vcso. Vcs) characteristics. M identifies a MOSFET and can be followed by up to seven characters in SPICE2. MESFETs can be represented by the same models as those shown in Figures 3. MODname is the name of the model that defines the parameters for this transistor. Note that a MOSFET can be represented either as a fourterminal or threeterminal device. The details of the MESFET models can be found in Sec. the bulk terminal is often nd(D) t nd(D) IDS t nd(D) IDS nd(D) iDS + VDS ng(G)~ Vcs ng(G)~ Vcs + VDS nb (8) ng(G)~ Vcs t + + ns (5) t ng(G)~ Vcs iDS VDS VDS nb (8) + + ns (5) ns (5) nchannel ns (5) pchannel Figure 3.mho 4. 103 . ng. 3. nchannel (NMOS) and pchannel (PMOS). which can be checked against the characteristics in the data book. nd. 103 A 5 = IDss 25.15 for JFETs. and bulk nodes. for computing the f(VDS. respectively. 3.14 and 3.and pchannel MOSFET elements. The schematic representations for the two types of MOSFETs are shown in Figure 3.16 n. source.
5. and VBS = 1. and decoders need to be predicted reliably. of the drain and source diffusions of the MOSFET. sense amplifiers. AD and AS multiply the bulk junction capacitance per square meter. in the computation of the drainbulk (DB) and sourcebulk (SB) junction capacitances.102 3 SEMICONDUCTORDEVICE ELEMENTS omitted. VDSO.5). and VBSO at time t = 0 in a timedomain analysis.1 DC Model The most basic MOSFET model used in SPICE to describe the static BCEs of a MOSFET. NRD and NRS are the equivalent number of squares of the drain and source diffusions. in square meters. The SPICE2 builtin defaults for Land Ware 1 m. the threshold voltage. other SPICE versions may differ in the values assigned to these defaults. Note that the following parameters are used only for the very accurate modeling of MOS ICs. This detail of geometry specification is not necessary for firstorder analysis. The defaults for NRD and NRS are 1. the LEVEL = 1 model. in the computation of the parasitic drain and source series resistances. are described in Appendix A and references (Antognetti and Massobrio 1988.5. where the operations of the memory cell. respectively. NRD and NRS multiply the sheet resistance. and VBSO are used as initial values only when the UIC option is present in the • TRAN statement. for the DC solution. The key letters Land Ware optional. respectively. in meters. CJ. CJ is a model parameter defined by model MODname. The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution. By default MOSFETs are initialized cutoff at the limit of turnon. in SPICE2 the defaults of the two areas are each 100 /Lm2. if they are omitted. between source and drain. RSH. More complex SPICE MOSFET models. . Default values can be defined as DEFL and DEFW in an • OPTIONS control statement (see also Section 9. It is recommended to set either Land W or DEFL and DEFW. CJSW. in that order. the two values that follow MODname are interpreted as length and width.0. in the computation of the DB and SB junction sidewall capacitances. VDSO. PD and PS multiply the sidewall bulk junction capacitance per meter. In SPICE2 the defaults for PD and PS are zero. Land Ware the length and width of the conducting channel beneath the gate. VGSO. VDS = 0. with VGS = VTO. Vladimirescu and Liu 1981). AD and AS are the areas. 3. Up to eight geometry parameters can be specified for each MOSFET. because all nchannel transistors have the bulk connected to the most negative voltage and all pchannel transistors have the bulk connected to the most positive voltage. PD and PS are the perimeters of the drain and source diffusions in meters. Default values can be set at DEFAD and DEFAS in an • OPTIONS statement. which incorporate secondorder effects. VGSO. The keyword IC defines the values of the terminal voltages. alternatively. is the quadratic ShichmanHodges model (Shichman and Hodges 1968). such as RAMs.
VDS) for 0 < VGS . surface potential.5. LD.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 103 The drainsource current. respectively: o KP W for VGS ::s. The above equations are valid for VDS > O. PHI . Wand L. is generally applicable to FETs with minor changes to account for the specifics of each device category. PHI) (3. The current IDs flows in the opposite direction. The drain and source pn junctions are reverse biased.VTH) (l 2 + LAMBDA. KP. respectively. and linear. VBS is replaced by VBD.VTH) . and the process characteristics.LD is the effective channel length corrected for the lateral diffusion. 3.VBs . For a pchannel MOSFET the same current equations apply. JS. of the drain and source. IS. the behavior of the MOSFET is symmetrical. For a MOSFET the transconductance factor KP depends both on the device geometry. by its density. equivalently.30) is the threshold voltage in the presence of backgate bias.VTH VDS 2L KP W VDs(2(VGS . VBS < 0. VTH :5 IDS = 2 (VGS Lefj . similar to the JFET model. surface mobility. and VDS is replaced by its absolute value in the above equations. and LAMBDA are the electric parameters of a MOSFET model. IDs. There is an additional current component. due to the pnjunction current. and VTH = VTO + GAMMA ( J2. or.2 Dynamic and SmallSignal Models The dynamic behavior of a MOSFET is governed by the charge associated with the gateoxidesemiconductor interface and by the charges associated with the drain and source diffusions.VDs)(1 efj + LAMBDA.0. and thinoxide thickness. VTO. characterized by the saturation current. of an nchannel device is defined by the following three equations for the three regions of operations cutoff. bulk threshold parameter.J2. and output conductance factor in saturation. . If VDS changes sign.VTH (3. This model. saturation. GAMMA.29) whereLefj = L2. transconductance factor. forO VDS) < VDS < VGS . the absolute values are used for the terminal voltages and the current flows in the opposite direction. PHI. and therefore the pnjunction currents are negligible in a firstorder analysis. representing the threshold voltage. the drain and the source swapping roles: VGS is replaced by VGD.
and bulk by the gate. and CGBO should be used to describe the actual overlap of the drain. Ccs.32) = where Eox and EO are the permitivities of Si02 and free space. respectively.VTH The definition of the overlap capacitances needs to be changed when voltagedependent capacitances are used. TOX. CCD = 0. the GD overlap capacitance per unit channel width. Details on the gate charge and capitance formulations can be found in Appendix A. It is preferable to let SPICE use the voltagedependent capacitances shown in Figure 3.33) CCD = Ccs = !CoxWL. 3. CCB = CoxWL CCB = 0 for Vcs :::. This distinction is especially important in smallsignal frequency analysis. and TOX is the thinoxide thickness. CGDO. CGSO. For analog circuits a more careful evaluation of CGDO is necessary. VTH forO Ccs = ~Cox WL. In the three regions of operation the three capacitances are CCD = Ccs = 0. CGSO by W. VDS (3. CCD. is specified.31) For a firstorder analysis the constant gate capacitances itances approximated by CGDO CGBO = are specified as overlap capac CGSO 0 = ~CoxL (3. a channel.104 3 SEMICONDUCTORDEVICE ELEMENTS Three distinct charges can be identified on the plates of the MOS capacitor: a gate.32 for a transistor in the linear region. represented by CGDO. < Vcs . the GS overlap capacitance per unit channel width. and CGBO. The thinoxide capacitance per unit area is defined by C ox = EoxEO TOX (3. 3. source. The above approximation is appropriate for digital circuits. the GB overlap capacitance per channel length. respectively. and CGBO by L. It is recommended to set it to zero for a transistor biased in saturation and to the value given in Eqs. These charges are voltagedependent. The three gate capacitances used by SPICE are computed by adding the capacitances in Eq.17 by specifying TOX in the •MODEL statement. CCB = 0 for 0 :::. variable gate capacitances are computed for a LEVEL = I model only if the value of the thinoxide thickness parameter. CGSO.V DS < Vcs . Voltagedependent capacitances are always computed for the LEVEL = 2 and LEVEL = 3 models. are computed i~ SPICE by multiplying CGDO by W. and CCB. This capacitance has an important effect on the bandwidth of an MOS amplifier. beyond the channel. The actual gate capacitances.33 to the respective overlap capacitances: . For a firstorder model it can be assumed that the three MOS charges are associated with three constant capacitors.VTH:::. and a bulk charge.
3: CBD = CBD (l . CGDO CGBO = = CGSO = !CoxLD (3. and a sidewall junction capacitance per unit length. PB. C fox is the fieldoxide (isolation) thickness. and Wov is the gate width extension beyond the channel. CBS. the zerobias bulksource capacitance. in which case one of the more accurate models presented in Appendix A is recommended.35) where CBD. and MJ are the zerobias bulkdrain capacitance. 3.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 105 o 14 VCS.VBS/ PB)MJ (3. The design of LSI and VLSI circuits requires the most accurate representation of the actual physical realization of the circuit. SPICE2 provides the means for an accurate specification of the junction capacitance for each device geometry and diffusion profile.34) C foxWov where LD is the length of the gate extension over the drain and source diffusions.VBD/ PB)MJ CBS (l . one can omit the overlap capacitances when voltagedependent gate capacitances are used in LEVEL = 1. The DB and SB junction capacitances have a great impact on the operation speed of an IC. Unless a very accurate simulation is needed. CJ. and the junction grading coefficient. Both drain and source junction can be characterized by a bottom junction capacitance per unit area. The depletion charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eqs.17 MOSFET gate capacitances per unit channel area versus VGs. . the builtin bulk junction potential.V Figure 3.
The nonlinear current generator IDs is replaced by the resistance r ds and transconductances gm and gmbs de nd(D) ng (G) IDS VBD. and the geometryoriented specification are available.19.36. CJSW (1 . Scaled by the device geometry parameters.18. CJSW OvBsjPB)MJ+ OvBsjPB)MJSW Note that whenever both the total zerobias junction capacitance. 3. the DB and SB junction capacitances can be expressed as CBD CBS = = o . The capacitances introduced so far are used in the smallsignal analysis.32 through 3. the total capacitances take precedence. the largesignal MOSFET model is shown in Figure 3. CBD or CBS. The reason for this differentiation is the smaller grading coefficient of the sidewall of the diffusion.VBDj PB)MJSW (3. AD. In the largesignal timedomain analysis the gate charges and bulk junction charges are computed from Eq. CJ PS . AS. CJ + PD. 3. .VBDj PB)MJ AD.4 using Eqs. introduced above. which can make the sidewall contribution the dominant junction capacitance.36) AS .106 3 SEMICONDUCTORDEVICE ELEMENTS CJSW. and PS.18 Largesignal MOSFET model. The smallsignal MOSFET model is shown in Figure 3. PD. + nb (B) QGS +  VBS' + VGS' QBS S' QGB Rs ns (S) Figure 3.
i :l 3. (.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 107 .1 '.5 for the conductance of a diode. '. nb (8) S' " f .. and gmbs' In alLMOSFET equations terminal voltages must be referred to nodesD' and..( RD D'. L " .odeL U t . f ng (G) . fined by the following equations: '. .'" J CCD • . .. nd(D) . gds = rds 1 ~. resistances RD and RS are nonzero.•.S' when the parasitic terminal.29) must be used when deriving gm.19 . dIDs dVDS (3. . 3. " " .COD hI.i:1 .. 3.Smailsignal I ~. Usually.~ . Figure ~ • _.. The values of gbd and gbs are computed using Eq.37) dIDs dVGS dIDs dVBs The expression of IDS appropriate to the region of operation (Eqs. gds. The diodes representing the drain and source junctions are modeled by the conductances gbd and gbs in the smallsignal analysis. '\ gmVgs' ~ +gnrbsvbs' ~ r d. I ns(S) MQSFET •••• m. these diodes are turned off and gbd and gbs have very small values.J.
OOI CGJX)=3. must be specified. Note that the VTO specification of the PMOS incorporates the sign.4 summarizes the model parameters introduced so far along with the default values assigned by SPICE2. the gates are connected at node 1.5.8 and 10. node 3. > > In every model statement one of the keywords NMOS or PMOS. The model parameter is multiplied by the geometry parameter listed in the Scale Factor column on the device statement. The sequence is similar to the one described in Example 3.6 The following statements are examples of MOSFET definitions in SPICE.MODEL ENH NMOS VTO=l . The channel length. VTO. Table 3. node 0. and the source and bulk of the PMOS are connected to the supply. and defaults are used for KP and the other parameters. The SPICE parameters of MOSFETs are often derived from measurements of IV characteristics of test structures on IC wafers.lU GAMMA=.45N CGS0=3. L. Such limited specification may be useful only for a DC analysis. MN 2 1 0 0 MODN L=lOU W=20U LAMBDA=.108 3 SEMICONDUCTORDEVICE ELEMENTS 3.. and not the individual values of Wand L. indicating the transistor type. where only the ratio of W / L affects the solution. LEVEL = 1 MOSFET equations are used if this parameter is absent from the • MODEL statement.45N CGS0=3.MODEL DEP NMOS VTO=3 W=20U W=lOU TOX=. EXAMPLE 3. The absence of any chargestorage elements from the above model may cause the simulator to abort a transient analysis. default to 1 meter.MODEL Mom NMOS VTO=l.. Ml 1 2 0 0 Mom . the source and bulk of the NMOS are connected to ground.MODEL MODP PMOS VTO=l KP=15U These statements describe a CMOS inverter.lU TOX=. see Examples 10.10 for details. W.5 LAMBDA=.5 for a JFET. the only model parameter that is defined is the threshold voltage.MODEL MODN NMOS VTO=l KP=30U .3 Model Parameters The general form of the MOSFET model statement is • MODEL MODname NMOS/PMOS <VTO=VTO <KP=KP . MDRIV 2 1 0 0 ENH L=lOU MLOAD 3 2 2 0 DEP L=20U .OOI LAMBDA=.45N CGJX)=3. The drains are connected together at node 2.Ol LAMBDA=. and width. except that the characteristics are obtained from a curve tracer.45N MP 2 1 3 3 MODP L=lOU W=40U .005 .5 Ml is an NMOS transistor with no geometry data specified.
5 1.6 1.6 0 0 0 0 0 0 0 0. 3.OE4 10 10 10 5P IP 2.0E9 0.2D Scale Factor X 105 n n OIsq F F Fm2 Fml NRD NRS AD AS PD PS Y A Fm1 Fml FmI m m W W L 0 The statements on the previous page describe an enhancementdepletion NMOS inverter.0EI6 4.3.4 Name YTO KP GAMMA PHI LAMBDA RD RS RSH CBD CBS CJ MJ CJSW MJSW PB IS CGDO CGSO CGBO TOX LD MOSFET Model Parameters Parameter Threshold voltage Transconductance parameter Bulk threshold parameter Surface potential Channel length modulation parameter Drain ohmic resistance Source ohmic resistance D and S diffusion sheet resistance Zerobias BD junction capacitance Zerobias BS junction capacitance Zerobias bulk junction bottom capacitance Bulk junction grading coefficient Zerobias bulk junction sidewall capacitance Bulk junction grading coefficient Bulk junction potential Bulk junction saturation current GD overlap capacitance per unit channel width GS overlap capacitance per unit channel width GB overlap capacitance per unit channel length Thinoxide thickness Lateral diffusion Units Y Ay2 yl/2 Y yI Default 0 2.33 I 1014 0 0 0 00 Example 1.METALSEMICONDUCTOR FIELD EFFECT TRANSISTORS (MESFETS) 109 Table 3.0 I.0Ell 2.25 0.5 0 0.7 I.5 0. The depletion transistor is normally on and its threshold voltage is negative. introduced in Example 3.lD 0.OE3 0. Exercise Build SPICE decks for the CMOS inverter and enhancementdepletion inverter defined above and trace the I/O transfer characteristic using the •DC statement.0E1O O.0E4 0. vGso> .6 METALSEMICONDUCTOR FIELD EFFECT TRANSISTORS (MESFETS) In SPICE3 the general form of a metalsemiconductor field effect transistor (MESFET) statement is Zname nd ng ns MODname <area> <OFF> < IC=VDSO.0EII 4.0 0 0.
110
3
SEMICONDUCTORDEVICE
ELEMENTS
The letter Z must be the first character in Zname; Z identifies a MESFET only in SPICE3. In PSpice the identification character is B. nd, ng, and ns are the drain, gate, and source nodes, respectively. MODname is the name of the model that defines the parameters for this transistor. Two MESFET models are supported, nchannel (NMF) and pchannel (PMF). The schematic representations of the two types of MESFETs are identical to those of the corresponding types of JFETs, shown in Figure 3.13. The scale factor area is equal to the number of identical transistors connected in parallel, and defaults to 1. The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution. By default MESFETs are initialized conducting, with Ves = VTO, the pinchoff voltage, and VDS = 0.0 for the DC solution. The keyword IC sets the terminal voltages, VDSOand Veso, at time t = 0 in a time domain analysis. VDSOand Veso are used as initial values only when the UIC option is present in the . TRAN statement. The SPICE3 BCEs for this device are given by the Raytheon model (Statz, Newman, Smith, Pucel, and Haus, 1987). The drainsource current, IDs, is given by the following three equations for the three regions of operations, cutoff, saturation, and linear, respectively: 0
IDs = {3(Ves  VTO)2
[1  (1 
ALPHA
V~s
J].
for Ves ::; VTO (l
+ LAMBDA.
VDs)
1
(3
(3(Ves  VTO)2(1 BETA
+ LAMBDA.
VDS)
for 0 < VDs ::; 3/ ALPHA for VDS > 3/ ALPHA
(3.38)
=
1 + B(Ves  VTO)
VTO, BETA, ALPHA, B, and LAMBDA are the threshold voltage, transconductance factor, saturation voltage parameter, doping tail extending parameter, and output conductance factor in saturation, respectively. The above equations are valid for VDS > O. If VDS changes sign, the behavior of the MESFET is symmetrical, the drain and the source swapping roles: Ves is replaced by VeD, and VDS is replaced by its absolute value in the above equations. The current IDS flows in the opposite direction. The dynamic behavior of a MESFET is modeled by two charges associated with the GD and GS junctions. These charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eq. 3.3.
Ces
=
CGS (l  Ves/ PB)o.5 CGD
VeD/ PB)o.5
(3.39)
CeD = (l 
CGS, CGD, and PB are the zerobias gatesource capacitance, zerobias gatedrain capacitance, and the builtin gate junction potential, respectively. The MESFET imple
METALSEMICONDUCTOR
FIELD EFFECT TRANSISTORS (MESFETS)
111
mentation of these capacitances uses voltagedependent factors that control the continuity of the equations around VDS = O. The largesignal and smallsignal MESFET equivalent models are similar to the corresponding JFET models shown in Figures 3.14 and 3.15. The general form of the MESFET model statement is
• MODEL MODname NMF /PMF <VTO=VTO <BETA=BETA ... > >
In every model statement, one of the keywords NMF or PMF must be specified for the transistor type. Table 3.5 summarizes the model parameters introduced so far along with the default values assigned by SPICE3. The threshold voltage, VTO, is signsensitive. MESFETs operate in depletion mode, i.e., they are normally on; therefore VTO is negative for nchannel devices, NMF.
EXAMPLE
Zl
3.7
1 2 3 MODZ ALPHA=l RD=20 RS=20
.MODEL MODZ NMF VTO=3
Zl is a normally on nchannel MESFET with parasitic series drain and source resistances. A normally on pchannel MESFET that conducts the same current as Zl in similar bias conditions is described by the following • MODEL statement:
.MODEL MODZ PMF VTO=3 ALPHA=l RD=20 RS=20
PSpice supports two MESFET models, both with the MODtype keyword GASFET. In addition to the Raytheon model (Statz, Newman, Smith, Pucel, and Haus, 1987) available in SPICE3, PSpice also supports the Curtice model (Curtice 1980).
Table 3.5
Name VTO BETA B ALPHA LAMBDA RD RS CGS CGD PB
MESFET Model Parameters
Parameter Threshold (pinchoff)voltage Transconductance parameter Doping tail extending parameter Saturation voltage parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zerobias GS junction capacitance Zerobias GD junction capacitance Gate junction potential Units V AV2 VI VI VI Default 2.0 104 0.3 2 0 0 0 0 0 1 Example 2.5 1.0E3 0.3 2 1.0E4 100 100 5P IP 0.6 Scale Factor area area area l/area l/area area area
n n
F F V
112
3
SEMICONDUCTORDEVICE
ELEMENTS
3.7
SUMMARY
This chapter has described the semiconductor devices implemented in the most common SPICE programs. The SPICE analytical models and syntax for the diode, the bipolar junction transistor, and the three kinds of field effect transistors, JFET, MOSFET, and MESFET, have been presented in detail. Examples have demonstrated the meanings and the derivations of the model parameters. Each of the semiconductor devices is defined by an dement statement and a set of parameters contained in a •MODELstatement. The same •MODELstatement, that is, the same set of parameters, can be common to more than one device. The diode is defined by the following line: Dname n+ n MODname <area> <OFF> <IC=VDO >
The model parameters describing a diode are listed in Table 3.1 and can be specified in statements of model typeD. The BJT specification is Qname nc nb ne <ns> MODname <area> < OFF> <IC
=
VBEO, CEO> V are
Two types of BJTs are supported in SPICE, NPN and PNP; the model parameters summarized in Table 3.2. The format for JFETs is Jname nd ng ns MODname <area> <OFF> < IC=VDSO,VGSO>
Two types' of JFETs are available in SPICE, NJF and pJF; the model parameters be found in Table 3.3. A MOSFET is defined by the following line: Mname ndng ns nbMODname + «L=>L> < <W=> W> <AD=AD> <OFF> <AS=AS>
can
<PD=PD> <PS= PS> <NRD=NRD> <NRS=NRS> <IC=VDSO, VGSO, BSO> V
+
The two types of MOSFETs supported in SPICE are the NMOSand PMOS devices; the model parameters are listed in Table 3.4. MESFETs are not supported in SPICE2 but are available in SPICE3, PSpice, and most commercial SPICE programs; the syntax differs among SPICE versions. SPICE3 uses the following format: Zname nd ng ns MODname <area> <OFF> <IC=VDSO, vGSO>
The same syntax is used also in PSpice with the sole difference that the identification character is B. The two types of MESFET devices are NMFand PMF. The model parameters are summarized in Table 3.5. The BJT and the MOSFET are described by very complex equations having many parameters. The description in this chapter has not covered secondorder effects. Complete equations of the semiconductor models implemented in SPICE can be found in the book by Antognetti and Massobrio (1988) or in Appendix A.
REFERENCES
113
REFERENCES
Antognetti, P., and G. Massobrio. 1988. Semiconductor Device Modelil1;gwith. SPICE. New York: McGrawHill. Curtice, W. R. 1980. A MESFET model for use in the design of GaAs integrated circuits. IEEE Transactions on Microwave Theory and Techniques MTT28, pp. 448456. Getreu; 1.1976. Modeling the Bipolar Transistor. Beaverton, OR: Tektronix Inc. Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits. 3d ed. New York: John Wiley & Sons. Grove, A. S. 1967. Physics and Technology of Semiconductor Devices. New York: John Wiley & Sons. Motorola Inc. 1988. Motorola Semiconductors Data Book. Phoenix, AZ: Author. Muller, R. S., and T. I. Kamins. 1977. Device Elettronics forlntegrated Circuits. New York: John Wiley & Sons.. . ".. • Shichman; H., and D. A. Hodges. 1968. Modeling and simulation of insulatedgate fieldeffect transistor switching circuits. IEEE Journal of SolidState Circuits SC3 (September), pp.285289. Statz, H., P. Newman, I. W. Smith, R. A. Pucel, and H.A. Haus, 1987. GaAs FET device and circuit simulation in SPICE. IEEE Transactions on Electron Devices (February), pp. 160169. Symmetry Design Systems. 1992. MODPEX. Los Altos, CA: Author. Sze, S. M. 1981. Physics of Semiconductor Devices. New York: John Wiley & Sons. Vladimirescu, A., and S. Liu. 1981. The simulation of MOS integrated circuits using SPICE2, Univ. of California, Berkeley, ERL Memo UCBIERL M80/7 (March). :.' ,.: .. ,. ,,~\., . .,
;. :
"..
~.
:1' •
"
.1'
'j;
j
."
•..•.•'
"
. L'
Four
DC ANALYSIS
4.1
ANALYSIS OVERVIEW This chapter and the following two chapters describe the different analysis types performed by SPICE in its three simulation modes, DC, smallsignal AC, and largesignal transient. Each simulation mode supports more than one analysis type. The specifics of each analysis are explained in the chapters on the corresponding simulation modes. All statements introduced in this chapter and the following two chapters, analysis specifications and output requests, are control statements as defined in Chap. 1 and start with a period in the first column.
4.1.1
Simulation Modes and Analysis Types
The first simulation mode, DC, always computes and lists the voltages at every node in the circuit. The DC node voltages are computed prior to an AC or transient (TRAN) simulation. In the TRAN mode the DC solution can be specifically prohibited. DC supports the following four analysis types:
OP
DC voltages and operating point information for nonlinear elements Smallsignal midfrequency transfer function Transfer curves Sensitivity analysis
TF
DC
SENS
These analyses are presented in the following four sections of this chapter. The last section describes node voltage initialization. SPICE finds the DC solution in most cases
114
ANALYSIS OVERVIEW
115
without any additional information; in the situations where SPICE fails to find the DC solution, initialization options are available. The AC analysis described in Chap. 5 computes the frequency response of linear circuits and of the smallsignal equivalents of nonlinear circuits linearized near the DC bias point. Two additional analysis types can be performed in the frequency domain:
NOISE DISTO
Smallsignal noise response analysis Smallsignal distortion analysis of diode and BJT circuits
In the TRAN mode SPICE computes the largesignal timedomain response of the circuit. An initial transient solution, which is identical to the DC bias, precedes by default a TRAN simulation. The only additional analysis in the timedomain is
FOUR
Fourier analysis
The timedomain analysis is presented in Chap. 6.
4.1.2
Result Processingand Output Variables The results of the different analyses must be requested in • PRINT or . PLOT statements, introduced in Sec. 1.3.3. These statements identify circuit variables, voltages, and currents, to be computed and stored for specific analyses. Analyses are omitted in SPICE2 if no results are requested. SPICE3 performs the specified analyses even in the absence of a • PRINT or . PLOT statement; the results are stored in a rawf ile and can be displayed using the postprocessing utility Nutmeg. Similarly, PSpice runs the analysis and stores the results only if a • PRINT, . PLOT, or the proprietary. PROBE line is present in the input file; • PROBE saves the output results in a binary or a text file, which is used by the graphic display program Probe . . PRINT provides tabular outputs, whereas • PLOT generates lineprinter plots of the desired variables, as seen in Figure 1.7. The general format of the output request statement is
. PRINT/PLOT
AnalysisTYPE OULvar} <OULvar2 ... > <ploLlimits>
where AnalysisTYPE can be DC, AC, NOISE, DISTO, or TRAN and is followed by up to eight output variables (OULvar), which are voltages or currents. If more than eight output variables are desired, additional PRINT/PLOT statements must be used. There is no limit on the number of output variables. Output variables can be node voltages, branch voltages, and currents through voltage sources. A voltage output variable has the general form V (nodel <,node2> ) . If only node} is present, that node voltage is stored; if two nodes are specified, the output variable is the branch voltage across elements connected between node} and node2. A current output variable is of the form I (Vname) where Vname is an independent voltage source defined in the input circuit. The current measured by Vname flows
116
4
DC ANALYSIS
through the source from the positive to the negative source node. PSpice provides the convenience of identifying the current flowing through any circuit element by the expression I <pin> (Element...name) where Element...name corresponds to an element present in the circuit file and pin must be used only for multiterminal devices, such as transistors. I (R3 ), I (L1) , and Ie (Q7) are accepted current variables in PSpice representing the currents flowing through the resistor R1, the inductor L1, and the collector of the BJT Q7. In AC analysis the V and the I are followed by one or more characters specifying the desired format of the complex variable. In the NOISE and DISTO analyses, output variables are limited to the specific functions detailed in Sec. 5.3 and Sec. 5.4, respectively.
4.1.3
Analysis Parameters: Temperature
All element values specified in a SPICE deck are assumed to have been measured at a nominal temperature, TNOM, equal to 27° Celsius (300 K). The simulation of the circuit operation is performed at the nominal temperature of 27° C. The nominal temperature can be set to a different value using the • OPTIONS statement, described in Chap. 9. In practical design situations the operation of the circuit must be verified over a range of temperatures. In SPICE the circuit can be simulated at other temperatures defined in a global statement, • TEMP, with the following syntax:
• TEMP tempI
<temp2 ...
>
The simulation is performed at temperatures tempI, temp2, ... when a • TEMP line is present in the SPICE input file. The temperature values must be specified in degrees Celsius. Note that if the value of the nominal temperature is not present on the • TEMP line, the circuit is not simulated at TNOM. The effects of temperature on the values of different elements is computed by SPICE, and the updated values are used to simulate the circuit. Resistor values are adjusted for temperature variations by the following quadratic equation: value(TEMP)
=
value(TNOM)[l
+ tel(TEMP + tc2(TEMP
 TNOM)  TNOM)2] (4.1)
where TEMP is the circuit temperature, TNOM is the nominal temperature, and tel and tc2 are the first and secondorder temperature coefficients. The behavior of semiconductor devices is affected significantly by temperature; for example, temperature appears explicitly in the exponential terms of the BIT and diode current equations (see Chap. 3), as well as in the expressions of the saturation currents (1s), builtin potentials (cf>]), gain factor ({3F), and pnjunction capacitance (e]). The detailed temperature dependence of the model parameters of semiconductor devices is described in Appendix A. When a circuit is analyzed at a temperature different from TNOM, SPICE2lists the TEMPERATURE ADJUSTED VALUES for each element or model affected by tempera
OPERATING (BIAS) POINT
117
ture. Note that SPICE3 does not support the. TEMP statement; the ambient temperature must be defined on an • OPTIONS line. Exercise Add the statement
.TEMP 100
to the onetransistor input file used in Example 1.3, run SPICE2, and note the differences in the model parameters and DC operating point. Which behavior of the circuit is most affected by temperature variation?
4.2
OPERATING (BIAS) POINT The DC mode solves for the stable operating point of the circuit with only DC supplies applied. Capacitors are open circuits and inductors are shorts in DC. The DC solution consists of two sets of results; first, the DC bias solution, or the voltages at all nodes; and second, the operating point information, or the current, the terminal voltages, and the element values of the smallsignal linear equivalent, computed only for the nonlinear devices in the circuit. SPICE computes and prints the bias solution prior to any other analysis. The operating point, however, is not printed unless requested by an .OP statement. The only time this information is printed without the presence of .OP is when no analysis request is present in the input file. The voltages at all nodes, the total power consumption, and the current through each supply are printed as part of the SMALLSIGNAL BIAS SOLUTION (SSBS). Currents, terminal voltages, and smallsignal equivalent conductances of all nonlinear devices are listed in the OPERATING POINT INFORMATION (OPI) section of the output. The information provided by SPICE about the DC operation of a circuit is best explained by two examples, a linear and a nonlinear circuit.
EXAMPLE 4.1
Replace resistors R 1 and R3 in the bridge T circuit of Figure 1.1, by two capacitors, C1 = Cz = 1 JLF. Verify the DC solution with SPICE. The new circuit is shown in Figure 4.1.
Solution
The DC solution for the resistive circuit was computed in Example 1.1. A capacitor is equivalent to an open circuit in DC; therefore we expect the following DC solution:
V (1)
= V (3) = 12 V; V (2) = 0 V.
The modified SPICE input file and the results of the analysis are shown in Figure 4.2. The information in the SSBS is a complete characterization of the circuit. The
0000 VOLTAGE NAME SOURCE CURRENTS CURRENT O.T circuit with capacitors.000 DEG C NODE VOLTAGE VOLTAGE 12. .2 DC solution of bridge.OOOE+OO 0 .1 capacitors.OOE+OO WATTS VI TOTAL POWER DISSIPATION Figure 4.0000 TEMPERATURE NODE VOLTAGE 3) 12.0000 = 27. BridgeT circuit with BRIDGET CIRCUIT CIRCUIT DESCRIPTION **** * Cl 1 2 lu C2 2 3 lu VI 1 0 12 AC 1 R3 2 0 lk R4 1 3 lk * • E!'ID BRIDGET **** NODE 1) CIRCUIT SMALL SIGNAL BIAS SOLUTION NODE VOLTAGE 2) 0.118 4 DC ANALYSIS 1 kQ Figure 4.
the currents through voltage sources are listed in the SSBS. GMand RPI are computed according to Eqs. 3. 3. 3. VAF.A = 8. reproduced here in Figure 4. plus a secondorder resistance (see Appendix A for more detail). 1 are repeated in Figure 4. RO is infinite.3.T circuit. Relate the SPICE2 parameters listed under the OPI with the BIT model presented in Sec.3 Onetransistor circuit.2 Consider next the onetransistor amplifier of the first chapter.9 are part of the OPI section.23 k!1 j" is equal to RB. internally 1 kn Rc + 5 v= Vee Figure 4.OPERATING (BIAS) POINT 119 only data not computed by SPICE are the branch currents. but the node voltages and element values are sufficient for the derivation of any current. EXAMPLE 4. As seen in the two DC solutions of the bridge. . and RO is the collectoremitter output resistance.1.15 and 3. 10. introduced in Chap.2. the series parasitic base resistance.2.0258 V = BE~:C 1.4 for convenience. If a specific current is desired from SPICE.3. a dummy voltage source must be added in series with the element of interest.14. Figures 1. In the absence of the Early voltage.3 and 4.17: GM RPI RX = IC = 2.102 mho Vth = 3 0. Solution The values of the smallsignal equivalent model components of QI shown in Figure 3. The SPICE2 results obtained in Chap.
0000 VOLTAGE SOURCE CURRENTS NAME CURRENT VCC 2.000 DEG C ************************************************************************ Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * * * .120 4 DC ANALYSIS *******12/20/88 ONETRANSISTOR **** ******** CIRCUIT SPICE 2G.6 (FIG.4 .WIDTH OUT=80 ******** CIRCUIT SPICE 2G.06D02 WATTS *******12/20/88 ******** SPICE 2G.3) 3/15/83 ********17:11:05***** INPUT LISTING TEMPERATURE = 27.OP .MODEL QMOD NPN . OP results for onetransistor circuit.8967 NODE ( 3) VOLTAGE 5. .124D03 TOTAL POWER DISSIPATION 1.6 3/15/83 ONETRANSISTOR **** CIRCUIT (FIG.000 DEG C ********17:11:05***** OPERATING POINT INFORMATION *********************************************************************** Figure 4. 4.3) TEMPERATURE = 27.6 (FIG.000 DEG C 3/15/83 ********17:11:05***** * • END *******12/20/88 ONETRANSISTOR **** SMALL SIGNAL BIAS SOLUTION ') *********************************************************************** NODE 1) VOLTAGE 0.7934 NODE ( 2) VOLTAGE 2.3) TEMPERATURE = 27. 4. 4.
depends on the model parameters of the two .19 and 3. VOH and VOL.OOE+OO O.10E05 2. cpr and CMU.897 100.10E03 0. or TR.OPERATING (BIAS) POINT 121 **** MODEL IB IC VBE VBC VCE BIPOLAR JUNCTION TRANSISTORS Q1 BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT QMOD 2.OOE+OO O. however. which defaults to 1012 n and can be set as an option parameter (see Chaps.00E+12 O.20.793 2.3 Two important characteristic values of a logic gate are the high and low output voltages.103 2.4 SPICE2 clamps the maximum resistance to lIGMIN. which corresponds to a low VIN. and the corresponding cutoff frequency. CBX and CCS. are only relevant for secondorder effects. The remaining capacitances.23E+03 O.000 1. this explains the very high value of FT in Figure 4. fT. TF.OOE+OO 1. respectively. the supply voltage. VoH. is infinite. FT. which corresponds to high VIN.OOE+OO O. 9 and 10).4. CJC. Another example of DC operating point information is included for the depletionload NMOS inverter shown in Figure 4.29E+18 (continued) Figure 4. VOL. For a correctly designed enhancementdepletion (ED) inverter. are also part of the bias information and are computed according to Eqs. The smallsignal capacitances.OOE+OO 100.000 8. EXAMPLE 4.5. is equal to VDD. in the •MODEL statement the cutoff frequency. For more than one transistor or other nonlinear element the OPI is computed for each such element. Since no values are defined for CJE. 3.13E02 1.
respectively. transistors. M[ and ML.5 using the following MOS model parameters: VTOE = 1 V. Verify the result with SPICE. and PHI = 2<jJF = 0. VOL is calculated by equating the currents of . 3.86 V In the above calculation VOL has only been estimated at 0. Solution First calculate the threshold voltage of the depletion device taking into account the body effect. and the geometry ratio. where VTOE and VTOD are the enhancement and depletion transistor threshold voltage. of the ED inverter of Figure 4. as in Eq.6 V. VOL. (W / L)[ = 4.14 V =  JPHI) (4. GAMMA = 0.122 4 DC ANALYSIS 5V Figure 4.3V + GAMMA ( JPHI + VOL + 0.5 V in order to account for the body effect of the depletion device. VTOD = 3 V.5 V1/2. Assume that VIN = VDD = 5 V. (4.5 Enhancement depletion NMOS inverter circuit. KP = 20/LA/V2. and (W / L)L = 1. KR.2) Find the low output voltage.30: VTHD = VTOD . of the inverter (Hodges and Jackson 1983): .3) 2.
29: 1m = IDL (4. according to Eqs. ******** 12/29/88 ******** PSpice 3. .6 V. and depletion transistor. but the result is very close to the SPICE solution. because VDSI = VOL < VGSI  VTOE since VOL has been approximated at 0. such as the value of PHI. 4.5 V. models EMOS and DMOS. For all the default values of MOSFET parameters see Table 3. followed by the MOSFET MODEL PARAMETERS of transistors MI and ML. The circuit description is listed first.MODEL EMOS NMOS .4.MODEL DMOS NMOS VTO=l VTO= KP=20U 3 KP=20U GAMMA=. the new solution is VOL = 0. 0.02 (Mar 1987) ******** 00:11:01 ******** ED NMOS INVERTER **** CIRCUIT DESCRIPTION **************************************************************************** MI 2 1 0 0 EMOS w=40U L=10U ML 3 2 2 0 DMOS TtF10U L=10U VDD 3 0 5 VIN 1 0 5 * * . Note that only the parameter values specified in the input file are listed.3 yields a simple quadratic equation in VOL for Eqs. The current flowing through the inverter is These results of the SPICE2 analysis are shown in Figure 4.6 SPICE2 input and operating point of MOS inverter. The correction in VTHD has been overestimated.6. and not the default values for other parameters.27 V. 3. 4. The SSBS and OPI list the node voltages and smallsignal values of the transistors. 5 * .4.OPERATING (BIAS) POINT 123 the enhancement transistor. Substitution of the guess for VOL in Eq.OP * • END Figure 4.4) MI is assumed to operate in the linear region. ML. MI.
OOE+OO O.84E05 O.OOE+OO O.OOE+OO O.00E05 0.OOE+OO O.00E+00 2.OOOE+OOO 4.92E+00 5.000 1.OOE+OO O.00E05 0.OOE+OO O.500 TEMPERATURE NODE 3) VOLTAGE 5.**** TYPE LEVEL VTO KP GAMMA MOSFET MODEL EMOS NMOS 1.0000 NODE 2) VOLTAGE 0.OOE+OO 1.98E04 O.76E01 O.OOE+OO (continued) ML DMOS 8.2758 = 27. 000 3.OOE+OO O.52E05 O.000 DEG C MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOV CGDOV CGBOV CGS CGD CGB MI EMOS 8.0000 **** NODE 1) VOLTAGE NAME VDD VIN SMALL SIGNAL BIAS SOLUTION VOLTAGE 5.76E01 2.72E+00 2.523E005 O.000 DEG C NODE VOLTAGE SOURCE CURRENTS CURRENT 8.21E05 2.26E004 WATTS TEMPERATURE = TOTAL POWER DISSIPATION **** **** MOSFETS OPERATING POINT INFORMATION 27.0 PARAMETERS DMOS NMOS 1.52E05 5.OOE+OO O.OOE+OO O.000 2.OOE+OO 1. 92E+00 2.000 2.OOE+OO O.OOE+OO O. 56E05 O.00E+00 2.6 124 .OOE+OO Figure 4.OOE+OO O. OOE+OO 4.OOE+OO O.OOE+OO 4.OOE+OO O.OOE+OO O.
the backgate biascorrected threshold voltage. rather than gather all curves in a single plot. VGS. Note that VTH for the load transistor ML is corrected to 2.19 and are GDS. The biaspoint information contains the drain current. as well as the overlap capacitances. SPICE2 and other SPICE versions allow the user to vary the value of a resistor.3. Rname. vli2_value.v/i2_value) + step1) The value viiI _value of source VllnameI is swept first over the interval from startI to stopI for each value.92 V according to Eq.PRINT DC OULvarI <OULvar2 > . The value of the output variable is evaluated by sweeping the variables in the following order: v/i2_value = start2 for (v/i2_value :5 stop2. the outer variable. CBS. The following statement defines the source and the range of swept values: • DC V/InameI startI stopI step] <V/Iname2 start2 stop2 step2> The voltage or current source names VnameI. the program generates one plot for each value of the second source. and VTH. the outer variable. VTH also contains corrections due to smallsize geometry for higherlevel MOSFET models. Any node voltage or current through a voltage source can be defined as an output variable. CBD. and CGB. 4. 4. of Vllname2. Vname2 or InameI. The graphic display tools Nutmeg and Probe can overcome this problem. GM. CGS. v/iLvalue = v/iLvalue OULvar = f (vii Lvalue. or the temperature. In addition to the voltage and current of an independent source. GMBS. v/i2_value = v/i2_value + step2) v/iLvalue = startl for (v/iLvalue :5 stopl. The output variables of interest must be requested as either a tabular print or a plot . Iname2 must be defined in another independent source statement. TEMP.ploUim2> . CGD. Source Vllname] is also called the inner variable and source Vllname2.DC TRANSFER CURVES 125 The output voltage at the drain of MI agrees to two decimal points with the hand calculation. as presented in more detail in the works by Antognetti and Massobrio (1988) and Vladimirescu and Liu (1981) and Appendix A. The smallsignal characteristics for a MOSFET correspond to the smallsignal model of Figure 3.3 DC TRANSFER CURVES This analysis computes the DC states of a circuit while a voltage or current source is swept over a given interval. PLOT DC OUT_varI <OULvar2 > <ploUimI. Iv. The variation of two sources does not result in a comprehensive lineprinter plot. and VBS. Vvs. the terminal voltages. SPICE allows a second source to be varied as an outer variable.
PLOT DC I (VICQ9) The above three statements are part of a SPICE input file requiring the computation of DC voltage and current transfer curves. VGs) characteristics of the junction field effect transistor 2N4221. The third statement generates a lineprinter plot of the current flowing through the voltage source VICQ9.8 0.5 Y. a dummy voltage source connected at the collector of a transistor. 104 A/y2. and from the Motorola data book we can derive the following model parameters: VTO = VGS(ofj) = 3. Example .5 0. A different SPICE simulator and plotting package can be used. use the Motorola Semiconductors Data Book (Motorola Inc. Solution The measurement setup is shown in Figure 4. The second statement produces a tabular output listing of the values of the voltage at node 6 and the voltage difference between nodes 10 and 11.RD = 200. Two very common applications for using DC transfer curves are described in the following examples.4 Use PSpice and Probe to represent graphically the IDs = f(VDS. The first line specifies that voltage source VIN is to be swept from 0. Figure 4. SPICE deck.LAMBDA = 0. to measure the values of Ie. .1.5. The derivation of the SPICE model parameters from data book characteristics is described in Example 3. 1988) for the electrical characteristics.7 Measurement setup for JFET Yes) characteristics with IDS = f(VDs.PRINT DC V(6) V(lO.7.002 y1.126 4 DC ANALYSIS In SPICE2 if no DC output variable is defined in either print or plot format. the DC sweep analysis is omitted.25 .8 Y in steps of 0.25 V. EXAMPLE 4. BETA = 4.DC VIN 0.5 Y to 0.11) . Q9.
the 5 4 « E 3 2 o 5 10 15 20 25 Figure 4.2 V.002 RD=200 *. Note that no • PRINT or .5 BETA=4.PROBE * OTHER SPICE *.8.25 are used to compute the current IDS for values of VDS from 0 to 25 V in steps of 1 V at four values of VGS. VD and VG.1E4 LAMBDA=O. VGs) characteristics of a JFET.OP . Note that in spite of using a very simple model with just basic parameters.1 V.MODEL MODJ NJF VTO=3. are defined by the •DCstatement. PLOT lines are necessary for graphical results in PSpice. and 0 V. .8 Simulated IDS = f(VDS.3 V. IV CHARACTERISTICS Jl 2 1 0 MODJ VD 2 0 25 VG 1 0 2 OF JFET 2N4221 * * .END * The output characteristics of the transistor computed by SPICE are shown in Figure 4. The range of values and increments for the two bias sources.DC TRANSFER CURVES 127 The SPICE input description is listed below.PRINT DC I(VD) .DC VD 0 25 1 VG 3 0 1 * ONLY FOR PSPICE . . 3. . . Eqs. all that is needed is a • PROBE statement.
The input voltages VIH and VIL are defined by the points where the slope of the voltage transfer characteristic is unity (Hodges and Jackson 1983). Use the parameters of Example 4.9. can be easily observed in a repetition of the above analysis.3.5.25 .28 V. the gate of transistor M1 is swept from 0 to 5 V. in Wand L. VIH = 1. which require a thorough characterization of the noise margins.22 V The above values guarantee a proper operation of the ED NMOS inverter when connected with other logic gates implemented in the same technology that is. that is.5 Find the noise margins NMH and NML of the NMOS inverter in Figure 4. These result in NMH and NML = = VOH .6: . and VIL.128 4 DC ANALYSIS computed IV characteristics are close to those in the data book. VIH. and VIL = 2. respectively. This example also shows the usefulness of a lineprinter plot for an accurate reading of the output voltages for given input voltages. Another common use of DC transfer curves is for the design of logic gates. The four voltages VOH.VOL = 2.PLOT DC V(2) must be added to the input circuit description in Fig The resulting SPICE2 plot is shown in Figure 4. The effect of changes in the geometry of the transistors. VOL = 0. More accurate model parameters can be obtained using parameter extraction programs. NMH and NML. EXAMPLE 4. such as Parts from MicroSim.VIH = 3. defining the high and low noise margins.5 V. The four voltages are: VOH = 5 V. .5 V VIL . in NMOS. Solution The following two statements ure 4.5 V.DC VIN 0 5 0. are marked on the plots. VOL.
750E+00 4.500E+00 3.000E+00 2.000E+00 5.000E+00 5. 4.947EOl 2.943E+00 4.0000E+00 6.500E+00 2.4 SMALLSIGNAL TRANSFER FUNCTION At the completion of the DC bias solution the linearized network of a nonlinear input circuit is available.000EOl 7. a transconductance.000E+00 1.541EOl 4.0000E+OO TEMPERATURE = 27. The output variable can assume any of the forms described for output variables on PRINT and PLOT DC statements.OOOE+OO 2.923EOl 5. TF statement. The gain can be a voltage or current gain.000E+00 4. * * * * * * * * * * VOL Figure 4.750E+00 3.SMALLSIGNAL TRANSFER FUNCTION 129 ED NMOS INVERTER **** VIN DC TRANSFER CURVES V(2) O.000 DEG C (*)O. dIo/ dVi.000E+00 5.000E+00 4. for a BJT SPICE has computed the values of all the elements of the smallsignal BIT model shown in Figure 3.419EOl 3.250E+00 1.9 and listed in Figure 4.4.721EOl 3. For example. dVo/ dh .0000E+00 VIR VIL 5.250E+00 2.758EOl * * * * * *.9 DC transfer characteristic of NMOS inverter.866E+00 2. dVo/ dVi or dIo/ dIi.500E+00 1.250E+00 4.0000E+00 8.500E+00 4.000E+00 5.432E+00 3.124EOl 4.000E+00 4. or a transresistance. TF OUT_var V/Iname control statement.500EOl 5.240EOl 7.165EOl 2. VlIname identifies an independent voltage or current source connected at the input of the two ports defined by the above statement.763E+00 4. SPICE2 computes the gain and the input and output resistances of the twoport circuit defined by the.OOOOE+OO 2.750E+00 5.101EOl 5.546E+00 9.500EOl 1.000E+00 3.250E+00 3.087EOl 3.750E+00 2. The twoport characteristics of the linearized circuit can be obtained by using the .
Vn is the amplitude. This source represents the AC input signal ii. and cjJ is the phase shift of the AC signal. which is a valid approximation of the nonlinear circuit as long as it does not deviate significantly from its bias point. EXAMPLE 4. the voltage or current at any node is 7T where VN is the DC bias value. Therefore. A pure resistive network is assumed in the transfer function solution. In order that a • TF analysis can be performed.20 or taken directly from the OPI of transistor QI. TF analysis of SPICE2. Their values range from 1 nF to 1 p. such as C and C!L for a BJT and Cos and COD for a MOSFET. listed in Figure 4. In the largesignal timedomain analysis Vn can have any value. the thermal voltage. coupling capacitors are shorted and highfrequency capacitors are open. This assumption is valid for frequencies at which chargestorage effects can be neglected. that is. Highfrequency capacitors limit the bandwidth at high frequencies and are exemplified by transistor internal capacitances. the validity of the • TF analysis is limited to circuits that contain only highfrequency capacitors and lowfrequency inductors.130 4 DC ANALYSIS An important assumption of • TF is that the midfrequency behavior of the circuit is to be computed. The easiest approach to adding a signal source without perturbing the DC state is to use a current source Ii that has a DC value of zero at the input. .F. node 1. A source in SPICE has also a DC component. Solution The midfrequency smallsignal equivalent circuit of the onetransistor amplifier is shown in Figure 4.10. 3.15 through 3. Inductors at midfrequency are assumed to be shorted or open depending on which end of the frequency range they affect. the addition of a voltage input source at the base of QI. The inclusion of a smallsignal transfer function in a largesignal DC analysis needs a few more explanations. SPICE treats all capacitors as open and all inductors as shorted in the DC analysis. The additional midfrequency assumption simplifies the AC component of the signal to a real rather than complex value. in the frequencydomain analysis the assumption that the signal is small limits Vn to Vth.6 Find the twoport midfrequency characteristics of the onetransistor amplifier of Figure 4. an input signal source must be added to the circuit in Figure 4.4. The values of the linearized network can be computed using Eqs.3. With this assumption the AC response can be computed on a linear network. would change the operating point of the transistor. Coupling capacitors are used to decouple amplifier stages from each other and from signal generators for proper bias. which can perturb the DC bias of the circuit. Verify the results using the. In general.3.
Q c Ii t I I E L____ _ __ I I I I I l Figure 4. Note in the SSBS that the zerovalued input current source.TF V(2) II The modified input circuit and the SPICE2 results of the analysis are shown in Figure 4.5) (4. II. the input resistance.7) transfer function: The voltage gain can be obtained from the transresistance Va Vi av = ar Ri (4.!i0 I I I I I r~ IgmVb. and a current input. V2.4 for performing the transfer function analysis in SPICE2: II 0 1 . . Ra: ar = Va ii Vi ii Va ia = V2 RB RB r71' Ii RB II Rc + f3FRc r71' (4. ar. The transfer function characteristics of the onetransistor circuit for a voltage output.SMALLSIGNAL TRANSFER FUNCTION 131 B i. and output resistance. The results confirm the above hand calculations.11.10 Smallsignal midfrequency equivalent of onetransistor amplifier.8) The following two statements must be added to the input description of Figure 4. Ii.6) Ri Ra = II a r = Rc (4. Ri. are the transresistance. does not disturb the operating point of the circuit. at the collector of Ql.
using a voltage transfer function. .WIDTH OUT=80 . 4.END SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.222Dt03 = 1.000 DEG C NODE 3) VOLTAGE 5.000 DEG C Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 II 0 1 * * * .0000 **** NODE 1) VOLTAGE SOURCE CURRENTS NAME VCC CURRENT 2.11 .TF V(2) .132 4 DC ANALYSIS ONETRANSISTOR CIRCUIT (FIG. av.3) **** INPUT LISTING TEMPERATURE = 27.8967 TEMPERATURE = 27. derived above in Eq.939Dt04 = 1.124D03 TOTAL POWER DISSIPATION 1. TF analysis results for a onetransistorcircuit.MODEL * * QMOD NPN II .06D02 WATTS **** SMALLSIGNAL CHARACTERISTICS = 9. A voltage transfer function can be obtained by replacing resistor RB with a Thevenin equivalent at node I and specifying the added voltage source as input in the .000Dt03 V(2) III INPUT RESISTANCE AT II OUTPUT RESISTANCE AT V (2) Figure 4.8. 4. Exercise Confirm the value of the voltage gain.7934 NODE 2) VOLTAGE 2. TF statement.
consider the sensitivity results in the DC SENSITIVITY ANALYSIS section. Assume that {3F = 100 and assign the default values to the remaining BIT model parameters. > where output variables OUT_var 1. note in the OPI section that the value of Ie2 is very close to the above estimate. and the relative sensitivity. There are two sensitivity numbers listed for each parameter value: the absolute sensitivity. ELEMENT SENSITIVITY. These values reflect the sensitivities of DC voltages and currents with respect to perturbations in circuit element values.02 = 0. and sensitivity results of the SPICE2 simulation are listed in Figure 4. OUT_var2. The sensitivities with respect to every element in the circuit and all DC model parameters of diodes and BITs are computed for each output variable defined in the.7 Use SPICE2 to compute the sensitivity of the current provided by the current mirror (Gray and Meyer 1993) shown in Figure 4.98 rnA 1 rnA = REF 5 . Solution The current supplied by this current source is Ie2 IREF = IREF 1 + 2/ Vee  {3F VBE(on) lA 1. No sensitivity analysis is available in SPICE2 for AC or timedomain response. Second.12 with respect to the circuit parameters.103 n The input specification.5 SENSITIVITY ANALYSIS Sensitivity analysis offers insight into the effect of the values of circuit elements and variations of model parameters on selected output variables and hence on circuit performance. In this example a single output variable has been requested. The fourcolumn tabular output lists the ELEMENT NAME. SENS statement. the absolute sensitivity in amperes or volts per . are defined in the same manner as for the • PRINT and • PLOT statements.7 V 4. avj apj.. EXAMPLE 4.. No sensitivities with respect to model parameters of IFET or MOSFET transistors are available. .. and all results appear under the header DC SENSITIVITIES OF OUTPUT I (VMEAS). operating point. (avj apj)(pj/ 100).13. First.SENSITIVITY ANALYSIS 133 4.. The same data are computed for each output variable on the • SENS statement. The sensitivity analysis request has the following form: • SENS OULvarl <OULvar2 . ELEMENT VALUE. SPICE3 does not support this type of analysis.0.3.
3k Ql 2 2 0 QMOD Q2 1 2 0 QMOD VMEAS 3 1 VCC 3 0 5 * * . REF. and IS.13 SPICE2 sensitivity results for the current mirror.WIDI'H OUI'=80 • END Figure 4. REF Figure 4. Vcc.OP . The most informative data are the normalized sensitivities. the supply. For this small circuit it is easy to spot that a I % change in the value of any of the following elements causes roughly a 1OILA variation in IC2: the reference resistor. and the NORMALIZED SENSITIVITY in amperes or volts per I % variation in the value of the respective element.SENS I (VMEAS) * . . An increase of REF and IS causes I C2 to CURRENT MIRROR CURRENT SOURCE REF 3 2 4.12 current source. Current mirror unit of the respective element. the saturation current of transistors Ql and Q2.MODEL * QMOD NPN BF=100 VA=50 .134 4 DC ANALYSIS 0.
OOOE+OO O.05E03 7.028E+l3 O.000E+00 O.OOOE+OO O.OOOE+OO O.01E002 WATTS **** OPERATING POINT INFORMATION TEMPERATURE = 27.OOOE+OO 1.OOOE+OO O.000E+Ol O.OOOE+OO 5.OOOE+OO 1.OOOE+OO O.OOE+OO 7.000 DEG C NODE VOLTAGE 3) VOLTAGE NODE VOLTAGE 0.73EOl Q2 QMOD 9.038E05 O.0000 VOLTAGE SOURCE CURRENTS NAME CURRENT VMEAS 1.OOOE+OO 5.927E05 2.13 (continued) 4.OOOE+OO O.OOOE+OO REF VMEAS VCC Ql RB RC RE BF ISE BR ISC IS NE NC IKF IKR VAF VAR Figure 4.OOOE+OO 1.OOOE+OO 1.415E07 1.73EOl 4.64E06 1.23E+00 5.OOOE+OO O.OOOE+OO 1.OOOE+OO O.028E05 O.300E+03 O.7733 ( 5.OOOE+OO O.OOOE+OO O.OOOE+OO O.325E05 O.000E+00 O.649E04 O.OOOE+OO = DC SENSITIVITY ANALYSIS **** DC SENSITIVITIES OF OUTPUT I(VMEAS) ELEMENT ELEMENT VALUE NAME 27.OOOE+OO O.OOOE+OO O.000E16 1.73EOl O.64E04 7.045E003 VCC 2.OOOE+OO 1.OOOE+OO O.028E003 TOTAL POWER DISSIPATION 1.OOOE+OO O.OOOE+OO O.000 DEG C NORMALIZED SENSITIVITY (AMPS/PERCENT) 1.00E+00 TEMPERATURE ELEMENT SENSITIVITY (AMPS/UNIT) 2.**** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 5.OOOE+OO 1.018E07 O.OOOE+OO O.64E06 9.0000 NODE 2) TEMPERATURE = 27.018E07 O.OOOE+OO O.OOOE+OO O.500E+00 2.OOOE+OO 1.OOOE+OO O.OOOE+OO 135 .000 DEG C **** BIPOLAR JUNCTION TRANSISTORS NAME MODEL IB IC VEE VEC VCE Ql QMOD 9.OOOE+OO O.OOOE+OO O.000E+02 O.
000E16 1.6 NODE VOLTAGE INITIALIZATION All nonlinear electrical simulation programs compute the solution iteratively. The number of requested output variables in sensitivity analysis should be kept small.OOOE+OO 1. The following example shows the effect •NODESET has on the final solution.OOOE+OO 2. SPICE2 uses the initial values only as a guidance until it finds a first solution. > The effect of this statement is to assign valueI to the voltage of node nadel.OOOE+OO O.OOOE+OO O. There are exceptions when SPICE cannot find the solution in .OOOE+OO decrease.056E18 O.OOOE+OO O. Initially SPICE assumes that all node voltages are zero.OOOE+OO 1.NODESET V(nodel)=valueI <V(node2)=value2 .OOOE+OO O.OOOE+OO 1. .035E+13 O... but it must not be identical with them.OOOE+OO O. the search for the DC voltages continues. 629E06 O.OOOE+OO 1.OOOE+OO O.500E+OO 2. For these situations a node voltage initialization statement is available with the following general format: .OOOE+OO O. in the first few solution iterations.OOOE+OO O.000E+Ol O.13 (continued) O. with the initialization constraint removed until the final solution is reached. because a large amount of information is generated by this analysis.018E07 O.OOOE+OO 1. however.OOOE+OO 1.OOOE+OO O.the default number of 100 iterations.OOOE+OO O.035E05 O.OOOE+OO O. A good example of the use of the • NODESET statement is the DC analysis of bistable circuits. The iterative process starts with an initial guess of the voltages. In most cases the user does not need to specify any information about initial voltages. 4.000E+02 O. The effect of a perturbation in BF is far less important.OOOE+OO O. value2 to node node2. if they are correct.136 4 DC ANALYSIS Q2 RB RC RE BF ISE BR ISC IS NE NC IKF IKR VAF VAR Figure 4.OOOE+OO 2.OOOE+OO O.056E16 O.OOOE+OO 8.OOOE+OO 1. and so on.OOOE+OO O.147E07 O.000E+OO O.OOOE+OO 1.OOOE+OO O. whereas an increase in Vee brings about an increase in Iez. The final solution may differ from the values specified by •NODESET.018E07 O.OOOE+OO O. The final solution is probably in agreement with the •NODESET values.OOOE+OO 5.
14 MOS flipflop.14 has two stable operating points: the first is with MIl ON and M12 OFF.25 V (V (1) = 0. Another approach to node voltage initialization.16 is according to expectations. The solution obtained by SPICE2 in the presence of the • NODESET statement and shown also in Figure 4. with both MIl and M12 conducting. and the other would be OFF. Note that the voltage at node 1.3 for the same inverter.NODE VOLTAGE INITIALIZATION 137 EXAMPLE 4. Solution The input specification and the bias point obtained from SPICE2 are shown in Figure 4. this is equivalent to initializing transistor MIl in the OFF state. . This is a metastable state.3. one inverter would assume the ON state.3 in conjunction with the timedomain analysis . VDD. The solution found by SPICE2 has both inverters biased identically. The physical imbalance can be reproduced in SPICE2 by initializing the drain voltage of MIl to 5 V (V (2) = 5) and the drain voltage of M12 to 0. is a corrected value of the initial guess. In reality the two inverters are not physically identical.• IC can be used to find the DC bias Figure 4. The same result can be obtained by adding the keyword OFF to the MIl line.8 Find the DC solution of the flipflop circuit shown in Figure 4. V (1) = 0.25). and the second is with MIl OFF and M12 ON. Use the same MOSFET model parameters as in Example 4. is presented in Section 6. and upon connecting the supply. • IC. The flipflop or bistable circuit.16. which in reality would not last.3.14. as listed in the modified input in Figure 4.2758. The latter value is roughly equal to VOL estimated in Example 4. which is equal to the solution found in Example 4. of Figure 4.15.
0000 = 27.25 V(2)=5 .MODEL EMOS NMOS VTO=l KP=20U .WIDTH OUT=80 .END **** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 2.NODESET V(1)=0.OPTION NOPAGE 2 3 1 3 3 1 2 2 1 0 0 2 0 1 5 0 0 0 0 EMOS DMOS EMOS DMOS w=40U W=10U w=40U W=10U L=10U L=10U L=10U L=10U MIl ML1 MI2 ML2 VDD * * * * .0000 NODE TEMPERATURE VOLTAGE 3) 5. NODESET.MODEL DMOS NMOS VTO=3 KP=20U GAMMA=. .OP HERE * .0000 = 27.16 SPICE2 bias solution of a MOS flipflop with .2758 NODE 2) VOLTAGE 5. NODESET.5 .000 DEG C NODE VOLTAGE Figure 4.OP .2701 NODE 2) VOLTAGE 2.000 DEG C NODE VOLTAGE Figure 4.138 4 DC ANALYSIS NMOS FLIPFLOP * . NMOS FLIPFLOP * * CIRCUIT DESCRIPTION COMES * .END **** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.2701 NODE 3) TEMPERATURE VOLTAGE 5.15 SPICE2 bias solution of a MDS flipflop without .
SUMMARY 139 solution. > <ploUimits> In the DC mode.. smallsignal transfer function. AnalysisTYPE can be only DC. and sensitivityare specified by the following control lines: .OP . NODESET is that node voltages are forced to the values specified by the user in the • IC statement and are not corrected after an initial pass. This chapter has presented an overview of the SPICE analysis modes and has described in detail the an. DC V/Iname1 startl stopl stepl <V/Iname2 start2 stop2 step2> . TF OULvar V/Iname . respectively.. . Node voltages can be initialized for a DC computation using the following statement: . which defaults to 27°e.. The ambient temperature for the circuit analysis is defined by . Examples have shown how to apply the various DC analyses to specific circuit problems.NODESET V(nodel)=valuel <V(node2)=value2 . > Note that the final values of the voltages at the nodes nodel. node2. transfer curves.. PRINT/PLOT AnalysisTYPE OUT_varl <OUT_var2. and result processing are also outlined as part ofthe analysis overview. The general format of the output request is .. PLOT control statement.. 'output variables...7 SUMMARY . . > With the exception of the DC operating point information. results are stored in the output file only for specified circuit variables. OUT_var. Analysis parameters. may differ from the initialization values.node2> ) I (Vname) The output variables for a • DC transfer curve analysis can be saved either in tabular or lineprinter plot format using the • PRINT or .. TEMP templ <temp2 . The DC analysis typesoperating point..alysis types of the bc mode. the major difference from . TNOM.SENS OUT_varl <OULvar2 . 4. . which can be voltages or currents: v (nodel <. > All circuit element values and model parameter values are defined at the nominal temperature.
Motorola Semiconductors Data Book. Hodges. AZ: Author. G. 1983. Massobrio. New York: McGrawHill.. 1988. Gray. Memo UCBIERL M8017 (March). and R. Jackson.. New York: John Wiley & Sons. Motorola Inc. Analysis and Design of Digital Integrated Circuits New York: McGrawHill. and H. G. . Semiconductor Device Modeling with SPICE. Phoenix. Liu. 3d ed. 1993. P. REFERENCES Antognetti. and S. Vladimirescu. P.. R.. 1981. Meyer. D. A.140 4 DC ANALYSIS . and G. The simulation of MOS integrated circuits using SPICE2. Analysis and Design of Analog Integrated Circuits. A. 1988.
sinwt. 141 .1 INTRODUCTION In AC mode SPICE computes the frequency response of linear circuits. Small input signals. and phase. In the frequency domain the voltages and currents of the circuit are also complex numbers. are assumed for nonlinear circuits that are linearized around the DC operating point. and an imaginary part. lVI. The periodicity factor.Five AC ANALYSIS 5. frequencydependent entities of the form Y = G + jwC + _1_ jwL (5. is implicitly assumed for all variables in an AC analysis. VR. In AC the node admittances are complex.2) 4J = Phasors consist of a real part.l) where w = 27T f is the angular frequency measured in radians per second andfis the frequency in Hertz. Vth = kT / q. 4J. called phasors: v IVI = = VR + jVI = IVieN J~ + Vi arctan ( ~~ ) (5. VI. with amplitudes less than the thermal voltage. and can also be expressed as magnitude.
EXAMPLE 5.024 MHz. presented in Sec. for a frequency sweep. presented in Sec. The 10 frequency values in each subinterval are selected on a logarithmic scale. These are .AC.1 Describe the differences in the AC analysis for the three types of intervals.5.AC OCT 4 1K 1MEG . The following statement specifies the frequency interval and scale: • AC Interval numpts fstart fstop where Interval is one of the three keywords that indicate whether the frequency varies by decade (DEC). This analysis provides meaningful results if there is at least one independent source with a specified AC value in the input circuit. betweenfstart.142 5 AC ANALYSIS SPICE2 supports several smallsignal analysis types in the frequency domain. Solution The following three •AC statements cover the same frequency range but cause circuit evaluations at different frequency points: . The second statement divides the frequency range into subintervals defined by the following relation between endpoints: h = 2f1. four per octave.4. with the endpoint of each subinterval being h = 10II. and fstop. the starting frequency. The points in each interval are selected on a logarithmic scale. DISTO. SPICE3 also offers a polezero analysis. 5. The circuit is evaluated at 30 frequencies.AC LIN 1000 1K 1MEG The first statement divides the frequency interval between 1 kHz and 1 MHz into three subintervals. • NOISE. 5. the final frequency. presented in Sec. since fstop = 1000fstart and 210 = 1024. The variable numpts specifies the number of frequency points used per interval. Ten subintervals are needed.AC DEC 10 1K 1MEG . for input and output noise computation. 5. with the last analysis at 1. where f1 is the starting frequency of the subinterval. 5. 5. • PZ. Prior to an AC analysis SPICE always computes the DC operating point. by octave (OCT). which is described in Sec. A total of 41 circuit evaluations are performed. for analysis of distortion due to semiconductor device nonlinearities. or linearly (LIN). which becomes the reference for linearizing nonlinear circuit elements.2.3. . for the linear interval numpts is the total number of frequency values betweenfstart andfstop.2 AC FREQUENCY SWEEP This analysis computes the values of node voltages in the circuit over a specified frequency interval. and.
PRINT AC or • PLOT AC statement is necessary in order for SPICE2 to perform the analysis. The results of an AC analysis can be viewed in either tabular or lineprinter format by adding one or more of the following statements: ACOULvarl <ACOULvar2 • PLOT AC AC_OUT_varl <ACOUT_var2 • PRINT AC > > <ploLliml. Solution The transfer function can be derived from the KVL and the BCE relations. PROBE line. IVI or III Phase of complex number Decibel value of magnitude.1. At least one.3) . EXAMPLE 5. and PSpice needs either a PRINT/PLOT line or a . 5. The accepted names for ACOUT_var are the following: VRor IR VI or II VMor IM VP or IP VDBor IDB Real part of complex value Imaginary part of complex value Magnitude of complex number. because it is consistent with a Bode plot of the circuit response.2. AC_OUT_varl.T circuit shown in Figure 4. contain additional information besides the type. For R Rj = R2 and C = Cj = C2 it is equal to: R2C2S2 R2C2s2 = + 2RCs + 1 + 3RCs + 1 (5. The decade is the most commonly used frequency interval. and the frequency varies linearly betweenfstart andfstop.AC analysis performed with SPICE.. The extra characters contained in the output variable's name differentiate among various representations of complex numbers.AC FREQUENCY SWEEP 143 The third statement divides the frequency range in 1000 equal parts. V or I. and verify with an . . ploLlim2> Output variables for the AC analysis. 20 loglO(IVI) or 20 loglO(!II) As in DC analysis a current output variable is specified as l(Vname) where Vname can be any voltage source in the circuit description. as in Eqs. One thousand evaluations are necessary in this analysis. .2 Derive the transfer function V3/ Vj of the bridge. SPICE3 does not require an output statement. sketch its Bode plot. and the node numbers.
see also Sec. END The Bode plot of VDB (3) and VP (3) is reproduced in Figure 5. The SPICE input for the circuit is listed below. and the phase. The two zeros are equal and are ZI = Z2 = 103 rad/s. a polezero analysis can be performed in SPICE3. The • PLOT AC statement requests a lineprinter plot.7. BRIDGET * V1 C1 C2 R3 R4 1 1 2 2 1 0 2 3 0 3 CIRCUIT 12 AC 1 1u 1u 1k 1k DEC 10 10 10k .PLOT AC VDB(3) VP(3) . of the voltage at node 3 to be saved in the output file. . The quadratic equations in the numeratorand denominator must be solved for the zeros and poles. When this example is run on PSpice. VP ( 3 ) .PROBE * .82.WIDTH OUT=80 * PSPICE ONLY *.AC * . of the magnitude in decibels.144 5 AC ANALYSIS where s is the complex frequency.1. similar to the one of Figure 1. corresponding to 159 Hz. this circuit is also called a notch filter.5. Because it attenuates signals of a given frequency. the • PROBE line should be added in order to save all the phasors of the circuit. In addition to the frequency sweep.3. respectively. VDB ( 3 ) . 102 rad/ s 7 61Hz P2 = 3 2 1 RC The locations of the poles and zeros point to a dip in the frequency characteristic centered around 159 Hz. Note that a decadic interval is specified and the transfer function requested is from 10 Hz to 10 kHz. The graphical representation validates the above hand calculations. s = (J" + jw. 5. The two poles surround the double Zero on the negative real frequency axis and are 3 PI + 2 J5 J5 1 RC . in order to be able to represent the Bode plot (Dorf 1989).
a 5" 0CD ::2: '"CD 3 5 10 CD (J) 4 100 Frequency. Identify important frequency points.2 and the modified SPICE2 input in Figure 5.3. Hz 1000 Figure 5.3 by running an • AC analysis. CIC = 2pF. First.T transfer function. A value different from 1. The AC amplitude of lA at the input scales the resulting complex voltages and currents to represent the transfer functions with respect to the input. Add the values of the BE and BC junction capacitances to the model parameters: CIE = IpF. the input signal source Ii must be connected to the base of Ql. Solution The transfer function of interest is gm f3(jw) g'Tr + jw(C'Tr + CIl) = (5.3.1 Magnitude and phase of the bridge. node 1: IIIOACI This source has a zero DC current and therefore does not disturb the DC bias point. EXAMPLES.4) Several statements must be added to the SPICE2 input for the onetransistor amplifier in Figure 4. The equivalent smallsignal circuit for the frequency sweep of the current gain is shown in Figure 5. A .AC FREQUENCY SWEEP 145 0 10 lD "0 "0 1 5 OJ Q) (J) ::T cD 2 0 'c Cl ro .3 Find the frequency variation of the current gain of the onetransistor amplifier of Figure 4.
1U * .WIDTH OUT=80 .2  ~    Currentgain amplifier: (a) amplifier circuit.END Figure 5. . (b) smallsignal equivalent.3 SPICE2 onetransistor currentgain circuit with bias information.6 (FIG. 5.lMEG lOG .2) 3/15/83 ********17:36:16***** INPUT LISTING TEMPERATURE = 27.146 5 AC ANALYSIS o mom C I Ii + RB r" CT"  gmVbe Rc VMEAS +  w Figure 5.000 DEG C *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * II01AC1 VMEAS 4 2 CSHUNT 4 0 .PLOT AC IDB (VMEAS) IP (VMEAS) .AC DEC 10 O.MODEL * * QMOD NPN CJE=lP CJC=2P . *******01/14/89 ONETRANSISTOR **** ******** CIRCUIT SPICE 2G.OP .
7934 NODE 2) VOLTAGE 2.124D03 O.000 8.000 NODE 3) VOLTAGE 5.8967 TEMPERATURE = 27.OOODtOO VCC VMEAS TOTAL POWER DISSIPATION 1.00012 2.897 100.OOE+OO 100./ ..793 2.OOE+OO 1.OOE+OO O.06D02 WATTS **** OPERATING POINT INFORMATION TEMPERATURE = 27.000 1.13E02 1.000 DEC C **** NODE 1) TEMPERATURE =27.00D16 100.000 4.00E+12 1.**** TYPE IS BF NF BR NR CJE CJC BJT MODEL PARAMETERS QMOD NPN 1.2.0000 NODE 4) DEG C VOLTAGE 2.29E12 O.000 1.30E+09 (continued) MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT .10B05 2.8967 VOLTAGE SOURCE CURRENTS NAME CURRENT .103 2.000 1.000 1.' Figure 5.00D12 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.3 147 .000 DEG C **** BIPOLAR JUNCTION TRANSISTORS Q1 QMOD 2.72E12 1.23E+03 O.10E03 0.
19.1012 1 rad s / = 0. 7T .AC DEC 10 10MEG lOG Last. The frequency range of interest can be estimated roughly by locating the pole of the current gain at r (C 7T 7T w{3 = 1 7T + C.4. 5. limit the gain bandwidth of the transistor. Fourth. connected to the collector in parallel with Re is equivalent to a short at high frequencies and an open circuit at DC.. 27T Hz = 4.3.10 9 rad s / (5. Second. which are omitted in this example. In the OPERATING POINT INFORMATION (OPI). A dummy voltage source. 10• Third. section note that the values CPI and CMU have been modified using the actual junction voltages VEE and VEC according to Eqs.4. A decoupling capacitor. for the AC input amplitude proves useful when the output of a circuit needs to be calibrated at 1 V. Also listed in this section is the value of the unitygain frequency. The input circuit with the bias point information is listed in Figure 5. This value is very close to the one computed in Eq. because VBe is negative. the AC component of the output current 10 must be separated from the DC component and measured.148 5 AC ANALYSIS or V.14. 3. C has increased.3 GHz (5. 027. is two orders of magnitude higher: 7T iT = {3F/[3 = 100.6) The frequency interval of interest is therefore between 10 MHz and 10 GHz: . the output control statement must be added: . or 0 dB. the zerobias junction capacitance values must be added to the •MODEL statement of the npn transistor. The unitygain frequency iT. because VEE is positive. and the Bode plot is shown in Figure 5.3.27.18. iT. Eq.5) The value of r has been taken from the bias point computation in Figure 4. defined in Eq. CSHUNT. 5.6. and the zerobias junction capacitances values have been used for C and CIL" This pole corresponds to a 3dB frequency of 43 MHz.J = 1. These capacitances together with the diffusion capacitances. 3. VMEAS must be added in series with CSHUNT to measure the output current. an AC control statement is needed.. and 3. 3. and CJL has decreased.23.6 is very useful for adding AC input signals or for purposely introducing an open circuit in DC without SPICE2 flagging the error LESS THAN TWO ELEMENTS CONNECTED AT NODEx.PLOT AC IDB(VMEAS) IP(VMEAS) It produces a Bode plot of the magnitude in decibels and phase in degrees of the current transfer function.109 . The zeroDC offset current source connected above and in Example 4.4.20.103.
The phase of the current gain at /r3 is 45°. (These accurate values are obtained with a • PRINT AC statement.NOISE ANALYSIS 149 45 IDB (VMEAS) 40 0 al ""0 ""0 35 20 "1J III (J) :T al "c Ol •• (lj 30 40 . This frequency is between 3. Noise characterization of a circuit can be performed by adding to each SPICE component a noise generator. f{3.98 GHz and 5 GHz. From the AC plot the midfrequency magnitude of the current gain is 39. Semiconductor devices produce shot noise. The magnitude drops to 37.4 Bode plot for the onetransistor currentgain circuit. Both /r3 and iT derived from the AC plot confirm the above hand calculations. 5.C1> CC1> <0 :2: m C1> (J) 25 60 20 80 15 10 Frequency. and burst noise (Gray and Meyer 1993). flicker noise.) The unitygain frequency is located where the magnitude curve crosses the OdB mark. Noise generation has a random character and can be due to a number of phenomena. MHz 100 Figure 5.81 MHz. The next step is to check the values of f{3 and iT in the AC plot.3 dB below the midfrequency magnitude of f3F. is located where (5.7) which translated into decibels is equal to . which is approximately equal to the value of f3F = 100. This limit is imposed by the noise that is generated in electronic components.3 NOISE ANALYSIS There is a lower limit to the amplitude of a signal that can be processed by electronic circuits.93 dB. The pole position.28 dB and the phase to 40° at 39. The most common is the thermal noise generated in resistors. A common .
. Capacitors. of the measurement.62. equal to 8. and controlled sources are noisefree.f is the frequency bandwidth G . whereas other types are greater at one end of the spectrum than at the other. A useful measure is the spectral density. is Boltzman's constant. some types cover the entire frequency spectrum uniformly and are also known as white noise.f.150 5 AC ANALYSIS origin of the noise phenomenon is the conduction of electric current by individual carriers. in semiconductor circuits. The noise current or noise voltage generators associated with different elements are characterized by a meansquare value. The theoretical mean square of the noise voltage source in series with the noisefree resistor (see Figure 5. inductors. The various types of noise have different frequency behaviors.2 IR Figure 5. Tis the absolute temperature. SPICE models noise in resistors and all semiconductor devices. The total effect of all the noise sources at the output of the circuit is obtained by adding all the meansquare values of the noisy elements reflected at the output: n V~ut = ~ i=1 vt (5. Noise source .9) where k. v2/ I::. A meansquare value is used for noise sources because the phenomena underlying the chargeflow mechanism are random. respectively.f.5) is given by Vk = 4kTR/1f (5.5 of a resistor. I::. of the noise source. and I::. measured in degrees Kelvin. The noise generators of the different elements in a circuit are uncorrelated. electrons and holes. The spectral density is measured in V2/Hz or A2/Hz. {i or v2.8) Noisesource values are proportional to the frequency bandwidth.. R is the resistance.. The best known noise behavior of an electronic component is the generation of thermal noise in a resistor..f or {i/ I::.105 eV/K.
is shown in Figure 5.AC request.NOISE V (nl<. respectively. Additionally. depending on whether the circuit input is defined by a voltage or current source. .11) (5.6. SPICE computes the output noise voltage at a specified output and an equivalent input noise voltage or current. Vth. The noise analysis is performed by SPICE in conjunction with an . The equivalent input noise is obtained by dividing the output noise by the transfer function of the circuit and represents the measure of all noise sources concentrated in a single noise source at the input. and therefore the analysis can be performed on the linear equivalent of a nonlinear circuit.10) with G = 1/ R. i~. a report on each noise source's contribution can be generated by SPICE2 at specified frequencies. The general form of the • NOISE control statement is . and i~. defines the output port as a voltage between nodes nl and n2. Another way of representing the noise contribution current generator in parallel with meansquare value is to connect a i2 . V(nl <.AC and the •NOISE control statements must be present in the input file. If only one node B + Ii r" Figure 5. both the .5. The meansquare value of each source is proportional to the corresponding DC current. The latter approach is used in SPICE because of the ease of adding the contribution of current generators in nodal equations.12) G= The meansquare values of the noise sources are small compared to the thermal voltage.6 Noise sources of the onetransistor amplifier.NOISE ANALYSIS 151 of the measurement.n2» V/Iname nums n2» which defines the twoport connections of the circuit for the noise computation. IB or Ie: i~ = 2qIBtif 2qIetif (5.4kTGtif R (5. The smallsignal equivalent model of a BIT with the shot noise sources of the base and collector currents. as shown in Figure 5. The major source of noise in semiconductor devices is associated with the flow of DC current and is known as shot noise. This report can produce a large amount of printout.
at the output nodes defined in the • NOISE statement. in addition. the value 10 is missing from the • NOISE statement. If.PLOT NOISE ONOISE to the above two statements causes SPICE2 to produce a lineprinter plot of the total rootmeansquare (rms) value of the output voltage noise at node 11. M. At least one resulting noise value must appear on a • PRINT or • PLOT NOISE statement. the frequency interval specified in the . then SPICE2 does not generate any output related to the two statements. No output is generated in the absence of a • PRINT or • PLOT statement for ACor NOISE.PLOT NOISE > <INOISE«MtDB»> ONOISE represents the total noise voltage.152 5 AC ANALYSIS is specified. one for each decade. DB. The general form of the output request is • PRINT NOISE ONOISE < (MtDB) > <INOISE ONOISE«MtDB) < (MtDB) > > . The results of a noise analysis can be requested in tabular form with a • PRINT statement or as a lineprinter plot with a • PLOT statement. n2». the output is between it and ground. which is the default. The optional qualifiers differentiate between magnitude.4 . .The output noise and the input noise are computed at all frequencies betweenfstart andfstop. as specified in the •AC statement. at Viiname.NOISE V(ll) VIN1 10 The above two statements define the frequency interval. V(nl <. and decibels. VII name. The number of noisesource summaries for a DEC interval with numpts frequency points per decade and a number of frequency decades in the intervalfstart tofstop equal to decades is equal to decades' numptsj nums + 1. and INOISE is the equivalent input noise. voltage or current. EXAMPLE 5.AC DEC 10 1K 100MEG . The input of the twoport circuit is identified by an input source. define the twoport circuit. of which the input is VINl and the output is node 11.AC statement. The addition of the statement . and request six noisesource summaries. which can be a voltage or current source and must be present in the circuit description. also defined by the . a summary of each noise source value is listed in the result file once every nums frequency points in the intervalfstart to fstop. SPICE2 can list the individual contribution of each noise generator at given frequencies. A zero or the absence of a value for nums disables the individual noisesource report.NOISE line. from fstart = 1 kHz to fstop = 100 MHz.
6.2 without the VMEAS.1.10 24 22 A /Hz A /Hz 2 2 = 2. 1020. Solution The noise sources are shown in the smallsignal equivalent circuit of the onetransistor amplifier in Figure 5. Eqs.72. is The contribution of the noise sources connected to the collector is obtained by multiplying i~c and i~ by the square of the output resistance. All contributions to the output noise voltage are spectral densities of the meansquare values.6.2. 105 y2/Hz = 3.4.72 .1016 y2/Hz = 6. the contributions of the two BJT noise currents are evaluated: 72R2 l~f = 6. The values of all noise sources can be computed using the definitions ofthermal and shot noise. = 4kTRc . First.6. 1015 y /Hz 2 ~R. 1019 .2.1 .12: ~ R} a 2 = 4kTRB = 1. The value of the transfer function at midfrequency. the total output noise. The contribution of the noise sources connected at the base of the transistor can be obtained by multiplying the meansquare values of i~b and i~ by the square of the transfer function Ii.72. as defined Vol in Sec.2.2 = 1. 103 A2/Hz = 6.72.1.1019. CSHUNT net.1014 y2/Hz ~A2 l~/ .1. Check your results with SPICE2. 1017 y /HZ A2/Hz 2 ~f = 2qIB = 2.6. 103 y2/Hz = 1.9 to 5.NOISE ANALYSIS 153 EXAMPLE 5.6.5 Compute the contribution of each noise source to the output voltage noise.2. 10 The contribution of each of the above sources to the output noise voltage is calculated next. 5. 4.105 ~f = 2qIc '2 = 6. and the equivalent input noise for the onetransistor amplifier in Figure 5. 1020.6.
The input circuit. and RE. TRANSFER FUNCTION VALUE: V(2l/II .7 Hz or 2. The following two statements must be added to the SPICE2 input used in the AC sweep (Example 5. FN. the summary report printed by SPICE2 of the noise analysis at 100 kHz. and the frequency variation of the rms values of va/ !J. A frequency sweep of the total output noise voltage and equivalent input noise current is also requested. The RESISTOR SQUARED NOISE VOLTAGES are in agreement with the hand calculations. Below the NOISE ANALYSIS header are the meansquare values of all individual noise sources computed at the output.j and iieq/ !J. The FREQUENCY precedes each such report. For this reason lownoise amplifiers often use PETs in the input stage.7.j  I 4 ""2 . 107 Y/ Jlh. which is described in more detail in the reference text by Gray and Meyer (1993). All noise sources associated with a BJT and their values are listed under TRANSISTOR SQUARED NOISE VOLTAGES. RC.PLOT NOISE ONOISE INOISE The element lines VMEAS and CSHUNT must be deleted since an output voltage must be sampled.j The total meansquare output noise voltage v~ is the sum of the meansquare values of all contributions. generate thermal noise. resulting in 2 Va _ !J.154 5 AC ANALYSIS The noise contributed by the base current at the output is significant because the current amplification available in BITs is high.NOISE V(2) II 10 . which is equal to zero in this case because no parasitic resistances have been specified in the •MODEL statement. One summary report of each noise source is computed for each frequency decade.j computed from 100 kHz to 10 GHz are listed in Figure 5. expressed as an rms value.6 9'1014y2/ !J. the noise seen at the output due to Rc and RB is: Va3 2 !J. The • NOISE statement defines node 2 as the noise output and current source I I as the noise input. is the flicker noise component.j ~ Von . Second. The shot noise contributions from IB and IC are in agreement with the hand calculations. in order to have a noise analysis performed: .3). Each NOISE ANALYSIS summary ends with the meansquare and rms values of TOTAL OUTPUT NOISE VOLTAGE. RB. The last noise source of a BIT. The parasitic terminal resistors.6.
693D16 O.762D14 SQ V/HZ 2.904D+04 2.000D+05 SQUARED HZ VOLTAGES (SQ V/HZ) **** TOTAL RESISTOR NOISE RC 1.000 DEG C **** NOISE *********************************************************************** FREQUENCY = 1.130D16 NOISE VOLTAGES (SQ V/HZ) **** RB RC RE IB IC FN SQUARED TOTAL Q1 O.NOISE ANALYSIS 155 *******02/03/89 ONETRANSISTOR ******** CIRCUIT LISTING SPICE 2G.OOOD+OO O.600D07 V/RT HZ **** TOTAL TRANSFER FUNCTION VALUE: V(2)/II EQUIVALENT INPUT NOISE AT II 9. 5.OOOD+OO 6. .OOOD+OO 6.OP .679D14 OUTPUT NOISE VOLTAGE 6.OOOD+OO O.lMEG lOG .646D17 TRANSISTOR RB 8.625D12 /RT HZ (continued on next page) Figure 5.2) TEMPERATURE = 27.6 3/15/83 ********11:40:54***** (FIG.MODEL * .000 DEG C **** INPUT *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 II * * 0 1 AC 1 QMOD NPN CJE=lP CJC=2P * .END *******02/03/89 ******** ONETRANSISTOR CIRCUIT ANALYSIS * . 5.AC DEC 10 O.PLOT SPICE 2G.NOISE V(2) II 10 NOISE ONOISE INOISE .612D14 6.2) TEMPERATURE = 27.7 Results of onetransistor amplifier noise analysis.WIDTH OUT=80 .6 3/15/83 ********11:40:54***** (FIG.
* * *..968D08 1. 1.587D07 2.675D10 5.162D+07 3.259D+06 1.6 3/15/83 ********11:40:54***** ONETRANSISTOR CIRCUIT (FIG. * * * * +.892D08 3.+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .. + *.123.512D+09 3.259D+08 1.310D+08 7.574D07 2.. * * * * * * * * * *  .000D09 1.069D09 9.585D+09 1..512D+05 3.'995D+09 2.000 DEG C **** INPUT LISTING *********************************************************************** LEGEND: *: ONOISE +: INOISE FREQ ONOISE *)1.*******02/03/89 ******** SPICE 2G.388D10 7..855D10 7.162D+08 3.162D12 1. +..310D+07 7.523D07 2.943D+06 1.  ..995D+05 2.278D09 5.162D+06 3. 943D+07.+)1.564D10 8.473D08 1.245D08 7.943D+09 1.000Dll 3.590D10 7.000D08 1.230D10 7..585D+07 1.774D10 8. ..000D+07 1.000D+08 1.310D+09 7.995D+07 2. .585D+06 1.175D07 2.512D+07 3.* * * * * * * * * * ...245D08 9.521D10 6.105D08 2.012D+09 6.003D07 1.209D09 2.2) TEMPERATURE = 27.111D10 4.585D+05 1.7 (continued) 156 ..000D+05 1.012D+06 6....259D+07 1.012D+05 6.574D07 1.512D+08 3.981D+05 5..309D07 2..485D10 .520D08 6.028D10 6.905D09 7.554D07 2.211D10 7.981D+07 5...310D+05 7.799D07 1.943D+05 1.226D09 1.807D10 6.102D09 1.000D07 1... 2.D07 9.000D12  .067D08 4. 002D09 3.000D06 .000D+06 1.595D07 2.000D+10 1.162D+05 3..259D+05 1. 3..000D10 1.995D+06 2.441D09 1..162Dll .012D+07 6.000D10 * * * * * * * * * * * * * * .512D+06 3.007D09 4.587D09 2.981D+06 5. .943D+08 1. + *..981D+08 5.600D07 2.566D08 1. 5.259D+09 1..310D+06 7.868D08 3.981D+09 5.1. Figure 5. * * * + * +* *+ * + + *.727D09 1.995D+08 2..343D07 1.000D+09 1.476D07 2.883D09 6.147D10 5.. + + + + + + + + + + ..162D+09 3.585D+08 1.407D07 2.012D+08 6.
13) where ai.. Si = SI COSWjt + S2cosw2t (5. increases starting at 158 MHz. 100 MHz. . 5. These terms are called sum and difference secondorder intermodulation .3. can be expressed as a power series of the input signal. is seen to fall off above 1 MHz. and the EQUIVALENT INPUT NOISE AT II. In the frequency plot entitled AC ANALYSIS. The output signal. these summaries have been omitted from Figure 5.W2) are generated as well.4 DISTORTION ANALYSIS The signal applied to an active circuit is distorted because of a number of causes such as nonlinear elements and limiting. and the . and the increase in equivalent input noise. such as When Si is replaced by SI coswltin Eg. and the equivalent input noise. 10 MHz. a3.. The distortion measures derived below are computed for nearly linear circuits. signals of frequencies 2Wl and 3Wl (and higher) are generated. a voltage or a current. This analysis is not available in PSpice.7. the output noise voltage. The falloff of the output noise voltage is due to the 3 dB/octave rolloff of the transfer function.3dB frequency obtained in the AC frequency sweep. 5.~~ DISTORTION ANALYSIS 157 at the corresponding frequency. are constants. I GHz. Exercise Explain the difference between the . where capacitances and inductances can be neglected.3dB frequency obtained in the above analysis.14) intermodulation distortion terms of frequencies (WI + W2) and (WI . Avi. When a second signal is also present in the input signal. and 10 GHz. proportional to /2. is due to the frequency dependence of the current gain. representing the second and third harmonic distortion terms.13. operating at the bias point and at midfrequency. INOI SE. Harmonic distortion is generated in the circuit when one or more sinusoidal signals are applied at the input.. (3(jw). So. SPICE2 and SPICE3 compute several harmonic distortion characteristics using AC smallsignal analysis. Example 5. One such summary is printed also for I MHz. ONOISE. al is the transfer function at midfrequency computed by SPICE2 as part of the • TF or •AC analysis. For small signals the cause of small distortions is the nonlinear IV characteristic of semiconductor devices. a2. Si: (5.
HD2 is the fractional secondharmonic distortion.AC statement. and amplitude. Each distortion contribution is computed as distortion power in a designated load resistor. The expressions hi II and 8z define the frequency.13 by 8] cosw]t and ordering the terms of the fundamental and the harmonics. 5. A resistor with the same name must be present in the input file. 5. The general form of the distortion control statement is .16) The last distortion measure computed by SPICE2 is DIM3. 8z. the frequency interval specified in the •AC statement. The following quantities are computed by SPICE2 as a measure of the different distortion components. The secondorder sum and difference intermodulation components. both an •AC and a • DISTO statement must be present in the input file. The number of summaries can be related to the type of frequency interval. HD3.DISTO RLname <nums <hi II <Pre! <8z»» RLname is the name of the load resistor for computing the power contribution of the distortion. is computed similarly. decades' numptsl nums + 1 summaries are printed.wz). and decades decades in the interval from fstart to fstop. A summary of each distortion source in the circuit is listed in the result file once every nums frequency points in the interval from fstart to fstop. and is equal to HD2 = amplitude of secondharmonic distortion signal amplitude of fundamental (5. 5. the normalized thirdorder intermodulation component of frequency (2w] .14 for the evaluation of the intermodulation distortion terms. A zero or the absence of a value for nums disables the report on individual distortion sources. respectively. of the second input signal. in Eq. The small distortions measures defined above are computed by SPICE2 in conjunction with an AC smallsignal analysis. the total harmonic distortion of a given order is obtained by summing up all individual contributions.13 produces thirdorder intermodulation terms at frequencies (2wz :t wd and (2w] :t wz). of frequency 2w] in the absence of the second signal. 81M2 and DIM2. for a DEC interval with numpts frequency points per decade. The thirdorder term in the power series of Eq. is the frequency being swept in . The frequency of the first signal. are computed from the following equation and under the assumption that two signals are present at the input: 1M2 = amplitude of secondorder intermodulation amplitude of fundamental component (5. h.15) The expression of HD2 as a function of the power series coefficients is derived by replacing 8i in Eq. specified in the . The normalized thirdharmonic distortion magnitude. f]. using the amplitude of the thirdharmonic distortion signal.158 5 AC ANALYSIS components. 8z coswzt. Associated with each component of the smallsignal equivalent model of a transistor is a distortion contribution at the output of the circuit.
7 provides more insight into the derivation of the distortion components of the onetransistor amplifier. SIM2. and DB. which serve as reference for deriving the distortion measures HD2. 100 kHz. according to Eqs.DISTORTION ANALYSIS 159 the AC analysis.95 1M 0. for real. and . SIM2.17) By default SPICE2 uses 1 mW for P ref. The variable P ref is the power used as reference in the computation of the distortionpower terms in resistor RLname. Pret..16. M.15 and 5. At least one distortion term must appear on a • PRINT or • PLOT DISTO statement. The frequency of the second signal 12 is set to 0.DISTO ROUT 20 0. The output produced by SPICE2 will consist of three summaries of all distortion sources and the total distortion terms HD2.95fl. If fl is not specified. HD3. EXAMPLE 5. and DIM3 at 1 kHz. Va. . The rest of the data in the • DISTO statement define the second signal and reference output power level. for phase. The value 20 in the • DISTO statement establishes the summary to be printed once every 20 frequency points resulting in the three summary frequencies mentioned above.6 . and DIM3 have the meanings defined above. measured in the load resistor RL is hi hi (5. DIM2.PLOT DISTO HD2«x) > HD3«x» > HD2.5 The above two statements request the computation of the small distortion measures in the load resistor ROUT over a frequency interval from 1 kHz to 100 MHz.. 5. The frequency sweep of the distortion components can be requested in tabular form with a • PRINT statement or as a lineprinter plot with a • PLOT statement.PRINT DISTO HD2«x) > HD3«x)> SIM2«x) > DIM2«x) > SIM2«x) > DIM2«x) > + + DIM3«x) > DIM3< (x) .AC DEC 10 1K 100MEG . For a given value of RL both the amplitude Va and 51 can be calculated. and 10 MHz. DIM2. HD3. HD3. according to the . I for imaginary. for magnitude.AC statement specification there are 10 frequency points per decade. The power of the output signal. which is the default. The distortion terms are computed at all frequencies betweenfstart andfstop as specified in the . The general form of the output request is . Example 5.9 is used by SPICE2 and 52 defaults to 1. P. a value of It = 0. and x stands for any of R.AC statement. for logarithmic representation.
It should be noted that referencing distortion to the output power level uniquely determines the amplitude of the input signal producing that distortion. The onetransistor circuit is simplified.7 Compute all distortion measures introduced above for the onetransistor ure 4. and replacement of it by a bias source of value VBE = 0.160 5 AC ANALYSIS the amplitude is 0. for all computed frequency points between 1 kHz and 100 MHz. as shown in Figure 5.7934.18) . equal to the BE voltage obtained with the base resistor such that the quiescent collector current. Pref is used to scale the distortion terms that the output voltage amplitude of the fundamental is equal to If Pref = I mW. by removal of the bias base resistor. The resulting distortion components reflect the actual input amplitude corresponding to P ref. RB. If only the total distortion is of interest. which is usually I V. EXAMPLE 5. DIM2. The computation of the distortion terms is presented in more detail in the following example.3) and check the results using SPICE2.1 rnA. the logarithmic values of the distortion components can be expressed in terms of dBm. The results of the •AC and • DISTO statements are detailed summaries of all distortion sources in the circuit. The value of P ref can contradict the AC amplitude of the input source. a unit often used in telecommunications: dBm distortion = 20logHD where 1 m W corresponds to 0 dBm. nums is set to zero in the • DISTO statement and a • PRINT or • PLOT DISTO statement is added. VBE. This simplification is necessary because distortion is a strong function of the input source resistance. is preserved. such as .8. HD2. Ie = 2. The total voltage applied at the base of Ql. can be expressed as VBE = VBE + Vbe = VBE + Vbel coswt (5.PRINT DISTO HD2 HD2(P) DIM2 DIM2(P) which lists the magnitude and phase of the second harmonic distortion. and the second intermodulation difference distortion.5. Solution amplifier (Fig Expressions for the different distortion terms can be derived based on the exponential IV characteristic of the BIT. A voltage signal source of amplitude Vbel is also connected at the input.
from Eqs.21: Ie = ie . ie.. .DISTORTION ANALYSIS 161 (1 V) COS rot 5V =+ Vee VBE =+ 0.20 can be expanded in a power series: " . .2 V + . + '2 V2 I Ie th Vi 2 +"6 V3 1 Ie th Vi 3 + . Vi 1<:: := Ie 1 + .~e follows'. VBE.21) . Ie. Because of the assumption of small nonlinearities. ] (5. Ie: ie = Ie + Iecoswt (5. has a DC component... 5. and an AC component. the exponential in Eq.19) The total collector curren~. The resulting total collector current.Ie = V Vi th Ie .19 and 5.20) where VBE has been replaced by the sum of its components.equal to Vbel. where Vi is tlleinput s~gnal.' Vth IVi IVi ( th )2 + 6 ()3 Vth [ +. (5. ie.794 V I FigureS.. 5.S Simplified onetransistor circuit for distortion analysis. is an exponential function of the total baseemitter voltage.
22a) or.24) . 5. using the relation So = ajSi. Vi or Ie must be calculated.4 rnA Vi = aj = gm = 0.162 5 AC ANALYSIS The coefficients ai ofthe power series in Eq. . Both values result from the equation of the output power in Re Po Vo = V ut: = 2 I i.333 Vth (5.Re = Pre! = 1 mW 1. assuming that Si = Vi and So = Ie..22b) In order to evaluate the above expressions. Ie 2 ai 0 4 Ie (5..= 0.018 Ie 2 Ie (5. HD2 e The remaining distortion terms can be derived similarly: HD3 = 24' 1 ( Vth Vi )2 = 2 24' 1 (Ie )2 = 0.4 __ 0 16 .22b.13 can be set equal to the coefficients in the above power series. 5. = .1i' for either Vi or Ie in Eq.22a or Eq. respectively: 1 = . The distortion terms follow naturally: (5.23) 1 Vi 1 Ie SIM2 = DIM2 = . 4 2.! The amplitude of the input signal Vi is 1.4 rnA Ie Ie 1.Ie = 4I _1. a2 S = ~ . HD2 can be rewritten as HD2 = ~ .4 V = = J2RePre! = = Ie J2~. 1.081 mho = 17mV The secondharmonic distortion is obtained by substituting 5.
447E+01 TEMPERATURE SIM2 (DB) 9.PRINT DISTO HD2 (DB) HD3 (DB) SIM2 (DB) DIM2 (DB) DIM3 (DB) . 548E+01 HD3 (DB) 3.683E01 HD3 1.OP .000 DEG C DIM3 5.054 (5. .8 and the distortion measures at 1 kHz computed by SPICE2 are listed in Figure 5.PRINT DISTO HD2 HD3 SIM2 DIM2 DIM3 .AC statement have been set equal since only *******03/06/89 ******** SPICE 2G.000 DEG C *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K *RB 1 3 200K * VCC 3 0 5 VEE 4 0 793.9 SPICE2 distortion analysis results.DISTO RC * .6 (FIG.4M VEE1 1 4 AC 1 * * .WIDTH OUT=80 . (Vi)2 Vth = 1 8".668E02 DEG C **** DIM2 3. Note that/start and/stop in the .25) The input statements for the distortion analysis of the onetransistor amplifier of Figure 5.455E+00 DIM3 (DB) 2.000 DIM2 (DB) 9.MODEL QMOD NPN *+ CJE=lP CJC=2P * .000E+03 HD2 1.000E+03 HD2 (DB) 1.455E+00 27. (Ie)2 Ie = 0.9. 5.8) 3/15/83 ********11:10:26***** ONETRANSISTOR CIRCUIT **** INPUT LISTING TEMPERATURE = 27.493E+01 Figure 5.AC LIN 1 1K 1K .END AC ANALYSIS FREQ 1.DISTORTION ANALYSIS 163 DIM3 = 1 8".367E01 = 27.367E01 = **** AC ANALYSIS FREQ 1.889E02 TEMPERATURE SIM2 3.
One of the three keywords must be present. The polezero analysis is very useful for relatively small circuits.. The last field specifies whether the poles (POL).PI)(S . such as filters or feedback circuits. zeros (ZER). 5. In many applications. One of the keywords must be present. The output for this analysis is always a voltage.5 POLEZERO ANALYSIS The frequency sweep. introduced above yields the frequency response of circuits in the form of a graph. which can be either a current or a voltage. The results are stored in the output file if the following line is added to the input circuit: . such as SpicePLUS and HSPICE. PRINT PZ ALL The same command without the leading period can be issued in interactive mode.25. CUR for current input and VOL for voltage input.22 through 5. •AC. whereas in the latter case a separate analysis must be performed each time the twoport representation is redefined. (s . for circuits containing more than 20 charge storage elements the results must be interpreted carefully. The locations of poles and zeros can in general be inferred from a Bode plot. V 0 is the output voltage. and Sj is the input signal. The polezero analysis computes the transfer function of the circuit represented as a twoport circuit: H(s) = Vo(s) Sj(s) = a (szd(szz)"'(sZn) (s .Pm) (5. provide a polezero analysis.pz) . 5.164 5 AC ANALYSIS the total distortion terms at midfrequency are of interest. The distortion terms in dBm are listed in the SPICE2 output as well. or both poles and zeros (PZ).. the succession of several poles and zeros makes reading their locations from a frequency plot difficult and makes it necessary to obtain the actual values. A noteworthy difference between the frequency sweep and the polezero analysis is that in the former case one analysis computes the transfer function from input to any node in the circuit. The general form of the polezero statement in SPICE3 is • PZ ni I ni2 no 1 no2 CURNOL POL/ZERIPZ where nil and ni2 are the input nodes and nol and no2 are the output nodes of the twoport representation. should be computed. . In interactive mode the same command with the omission of the leading period must be typed at the SPICE3 shell prompt.26) where s = j w. The field following the node specification defines the type of the input. The distortion terms computed by SPICE2 are in good agreement with the values calculated by hand according to Eqs. SPICE3 and highend SPICE versions.
SUMMARY
165
The bridgeT circuit, which has exemplified the .AC frequency sweep, is used below for finding the poles and zeros and double checking the Bode plots.
EXAMPLES.8 Use SPICE3 to compute the poles and zeros of the bridge T filter; compare the results with the hand calculations in Example 5.2 and the Bode plot produced by SPICE.
Solution
The SPICE3 input and results for the polezero analysis are shown in Figure 5.10 on page 166. Note that the • AC statement has been replaced by a • PZ line defining the input of the twoport representation between nodes 1 and 0 and the output between nodes 3 and O. Furthermore, the input is defined as a voltage. The output signal is always assumed to be a voltage. The output contains the two real poles and zeros of the transfer function, which are identical to the hand calculations carried out in Example 5.2. Note that the polezero algorithm usually runs into difficulties when the transfer function is complex and has multiple poles or zeros.
5.6
SUMMARY
This chapter has described the analyses performed by SPICE in the AC mode. The control statements for each analysis have been introduced as well as the specifications of output variables and resultprocessing requests. Several examples have been used to show how to apply the various AC analyses to practical circuit problems. The implications of smallsignal analysis for nonlinear circuits in the AC mode has been addressed in the examples. The AC analysis types, frequency sweep, noise and distortion analysis, and polezero computations are specified by the following control lines:
• AC Interval numpts fstart fstop •NOISE V(nI<,n2»
V/Iname nums
.DISTO RLname <nums <hl!J
<Pre! <52»» . PZ ni 1 ni2 no 1 no2 CURNOL POL/ZERIPZ (SPICE3)
Noise and distortion are frequencydomain analyses; therefore these statements must be used in conjunction with an • AC line. With the exception of the PZ analysis, results are stored in the output file only for specified circuit variables, AC_OULvar, which can be complex voltages or currents: Vx (nodeI <,node2» Ix (Vname)
166
5
AC ANALYSIS
BRID3E VI Cl C2 R3 R4
T FILTER 12 AC 1 1U 1U lK lK
*
1 1 2 2 1
0 2 3 0 3
*
.OP .PZ 1 0 3 0 VOL PZ .PRINT PZ ALL
* END •
Circuit: BRID3E T FILTER
Circuit: BRID3E T FILTER Date: Fri Apr 19 14:55:55 Operating Node
V(3)
1991
point
information:
Voltage 1.000000e+Ol O.OOOOOOe+OO 1.000000e+Ol Current O.OOOOOOe+OO bridge T filter polezero analysis
V(2) V(l)
Source vl#branch
Fri Apr 19 14:55:55
1991
Index
pole(l) 2.618034e+03, O.OOOOOOe+OO
pole(2) 3.819660e+02, O.OOOOOOe+OO
o
bridge T filter polezero analysis Index zero(l) 1.000000e+03, O.OOOOOOe+OO zero(2)
Fri Apr 19 14:55:55
1991
o
1.000000e+03,
O.OOOOOOe+OO
Figure 5.10
Input and results for polezero analysis of bridgeT circuit.
SUMMARY
167
where x defines the output format of the complex variable; accepted formats are Rand I, for real and imaginary part, respectively; Mand P, for magnitude and phase, respectively; and DB, for the decibel value of the magnitude. The output variables of a frequencydomain analysis can be saved either in tabular or linepeinterplot format using the • PRINT or . PLOT control statement, respectively. The general format of the output request is .PRINT/PLOT AC ACOUT_varl <AC_OULvar2 ...
> <ploLlimits>
REFERENCES
Dorf, R. C., 1989. Introduction to Electric Circuits. New York: John Wi1~y&: Sons. Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits, 3d ed. New York: John Wiley & Sons. ' .
"
J
,.
..• I
':r,
Six
TIMEDOMAIN
ANALYSIS
6.1
ANALYSIS DESCRIPTION The transient analysis of SPICE2 computes the time response of a circuit. This analysis mode takes into account all nonlinearities of the circuit. The input signals applied to the circuit can be any of the timedependent functions described in Chap. 2: pulse, exponential, sinusoidal, piecewise linear, and singlefrequency FM. In contrast, in AC analysis only sinusoidal signals with small amplitudes, for which circuits can be considered linear, are used. Timedomain analysis computes, in addition to voltages and currents of timeinvariant elements, the variation of charges, q, and fluxes, e/>, associated with capacitors and inductors. These are described by the branchconstitutive equations (BCEs) for capacitors and inductors defined in Sees. 2.2.3 and 2.2.5: ic VL
= =
dq dt
=
Cdvc dt
(6.1) (6.2)
de/> = L diL dt dt
where ic and Vc are the current and voltage of capacitor C and iL and VL are the current and voltage of inductor L. The BCE for resistors, Ohm's law, is timeinvariant. Two analysis types are supported in SPICE for the timedomain solution:
TRAN
FOUR
Computes the voltage and current waveforms over a given time interval Computes the Fourier coefficients, or spectral components, of periodic signals
168
TRANSIENT ANALYSIS
169
An additional utility for transient analysis, • IC (initial conditions), is used for specifying the initial voltages at selected or all nodes. An INITIAL TRANSIENT SOLUTION (ITS) precedes a timedomain analysis unless it is specifically disabled. It is a DC solution at t = O.
6.2
TRANSIENT ANALYSIS
The following statement is required by SPICE to perform a transient analysis:
. TRAN TSTEP TSTOP <TSTART <TMAX> > <UIC>
The analysis is performed over the time interval from 0 to TSTOp' but results can be output starting from a userdefined time, TSTART, to TSTOP; TSTARTis assumed to be o if it is not specified. TSTEP is the time interval used for printing or plotting the results requested by a • PRINT or a • PLOT. Note that SPICE2 and most programs derived from it use a different internal time step for solving the circuit equations, which is automatically adjusted by the program for accuracy. By default the internal time step is bound by the smaller of (TSTOPTSTART)/50 or 2. TSTEP. Although in most cases the SPICE internal timestep selection algorithm is accurate enough, there are situations when for better accuracy a user may want to restrict the maximum time step. This can be achieved by specifying the value of the maximum allowed internal time step TMAX. The data on a • TRAN statement are ordersensiti ve, and a value for TSTART must always precede TMAX. The timedomain solution is preceded by a DC solution, the ITS, which computes the initial values of voltages and currents necessary for the integration of the BCEs, Eqs. 6.1 and 6.2, or Eqs. 2.5 and 2.10. A user can avoid the initial transient, DC, solution by concluding the. TRAN statement with the keyword UIC (use initial conditions). In this case the initial value of every voltage and current is 0 except those voltages and currents initialized with the IC keyword in the element definition lines or the • IC statement. One scenario where UIC is useful is the computation of the steadystate solution without the transient response leading to it. For a correct solution the user must define the correct initial values for all chargestorage elements in the circuit.
EXAMPLE 6.1
Explain the meaning of the following transient analysis statements:
.TRAN In lOOn .TRAN O.lu 100u 90u .TRAN 100u 1m 0 lOu .TRAN IOn lu mc .PRINT TRAN V(6) I (VCC) .PLOT TRAN V(6) V(2,1) (0,5)
170
6
TIMEDOMAIN
ANALYSIS
Solution
The first statement specifies that a timedomain analysis is to be performed from time to 100 ns and that the results are to be output at a lns interval. The second statement requests that the analysis be performed to 100 Jls and that the results between 90 JlSand 100 Jls be output at a 0.1 JlSinterval. The third statement requests a long analysis to lms with results output every 100Jls but limits the internal time step to lOJls. Finally, the fourth. THAN statement requires SPICE to omit the initial transient, or DC, solution by concluding the statement with the Ule keyword. The desired voltages and currents resulting from a transient analysis are identified in a • PRINT or • PLOT statement. The keyword THAN must be present to identify the analysis type. The time interval and time step for the prints and plots are those specified on the • THAN statement. At least one • PRINT or • PLOT statement must be present in the input file for the analysis to be performed. In this example the values of V ( 6) and the current through voltage source vee are printed and V ( 6) and V ( 2 , 1) are plotted with a common voltage scale with values from 0 to 5 V at the output.
o
EXAMPLE
6.2
Compute the timedomain response of an RLC parallel circuit that at t = 0 is connected to a constant current source as shown in Figure 6.1. Verify the solution with SPICE.
Solution
The KCL applied to node 1 yields the following equation:
Cdvc + dt
.
lL
+ If
Vc
=
I
S
(6.3)
The BCE of the inductor, Eq. 6.2, yields a substitution for iL : diL Ldt leading after differentiation ential equation in vc:
=
Vc
(6.4)
with respect to time to the following secondorder
differ
(6.5)
The solution of this equation is of the form vc(t)
=
Aept
(6.6)
TRANSIENT ANALYSIS
171
t= 0
R 10kQ
Figure 6.1
Parallel RLC circuit.
which put in the differential equation above leads to the characteristic
equation: (6.7)
pZ
where a
+ 2a p + w5
=
0
=
_1_
2RC 1
=
5. 104SI
106 rad/s (6.8)
Wo
= 
jLC
=
The solution of the quadratic equation is
PI,
Z =
a::!:: JaZ

W5
=
a::!:: J(W5
 aZ)
=
a::!:: jWd
(6.9)
which is put in Eq. 6.6 to obtain vdt):
(6.10) a is the damping/actor, and Wd is the damped radian/requency (Nilsson 1990). Coefficients A I and Az are found from the initial conditions; at t = 0, vdO) = 0 and therefore Az = AI. Al is obtained by putting vdO) in Eq. 6.3:
172
6
TIMEDOMAIN ANALYSIS
The timedependent
function vc(t) is 1 . cIse at.sm Wdt Wd
Vc (t ) =
(6.11)
The angular frequency, w, is close to Wo because a is negligible by comparison; therefore the period is T
= 
27r Wo
=
6.28/Ls
(6.12)
PARALLEL
RLC CIRCUIT
IS 0 1 PWL 0 0 IN 1M 1 1M L 101M
*
C lOIN RIO 10K
* .TRAN
. END
lU 1000 .PLOT TRAN V(l)
The SPICE input file for this circuit entitled, PARALLEL RLC CIRCUIT, is shown above. A transient analysis for 100 /Ls is requested corresponding to approximately 16 periods according to the above calculations. The waveform computed by SPICE2 is shown in Figure 6.2 and has the damped sinusoidal shape predicted by Eq. 6.11. The complex algorithms in SPIcI~2 (see Sec. 9.4) can be verified to predict waveforms in agreement with the above handderived solution for this simple problem. According to Eq. 6.11, the amplitude of the oscillation at wot = 7r/2 (for example, at t = 7r/2 /LS for Wo = 106 rad/s) is
After solving for vc(t), one can put Vc of Eq. 6.4 in Eq. 6.3 to obtain a secondorder differential equation in iL(t):
(6.13)
This equation differs from Eq. 6.5 for vc(t) in that the righthand side is nonzero. The solution consists of the damped sinusoidal term, which is the natural solution, and an
which is equal to the input current of 1 rnA. A few comments can be made at this point.0 0. JlS 60 80 Figure 6. The natural solution. In order to observe the oscillations in a circuit.5 > G .. represents the transient response. therefore.TRANSIENT ANALYSIS 173 1. This second approach is equivalent to applying a step function at t = 0+ since all currents and voltages at t = 0 are zero. whereas the forced solution is the steadystate response. we use a step function at t = 0+ described as a PWL current source.5 1.2 The waveform vc(t) computed by SPICE.0 0. 0.3.5 1. The example also outlined the . Explain the result.14) The SPICE waveform for iL(t) is shown in Figure 6.0 20 Time. It can be seen that once the oscillations die out the inductor current assumes the forced solution. An alternate way to achieve the same result is to use a DC current source at the input and to omit an INITIAL TRANSIENT SOLUTION by specifying the ure option in the • TRAN statement. additional forced solution: (6. ure keyword is The previous example demonstrated the use of the transient analysis in SPICE for computing the response of a linear RLC circuit. Exercise: Show that no oscillation can be observed in the SPICE solution if the not used when Is is a DC source.
3 Verify the oscillation condition and find the amplitude and frequency of the Colpitts . of a gain block. The importance of the different analysis parameters is exemplified best by oscillators.5 « E . In the frequency domain the overall transfer function.f.2 cannot sustain oscillations. connected in a feedback loop.7 is positive. Oscillations can be sustained only if the real part of the natural frequencies computed from Eq.3 The waveformh(t) computedby SPICE. This can be achieved with a gain block connected in a feedback con~ figuration (Pederson and Mayaram 1990). Solution The passive RLC circuit in Example 6. connection between the equations describing the electrical circuit and the analysis parameters and solution computed by SPICE.5 Time. the circuit has righthandplane poles. The following example demonstrates the use of SPICE for computing the response of a Colpitts oscillator. or in other words. a(s) (where s = (T + jw is the complex frequency).4 using SPICE._~ 1. oscillator shown in Figure 6. A(s).0 0. I!S Figure 6. which is shown in Figure 6. EXAMPLE 6.15) . which are damped by the factor eat.5 is equal to the following (Gray and Meyer 1993): a(s) 1 + a(s)f (6. 6.174 6 TIMEDOMAIN ANALYSIS 1.
where T(s) = a(s)f.5 Feedback amplifier.4 Vee 10V Colpitts oscillator. 0) in the complex frequency plane as shown in Figure oscillate.16) where n can be referred to as the capacitive turns ratio and is equal to the inverse of the feedback factor. QI connected in a feedback loop. f: I n= f 10 (6. T(s).17) s. The signal fed back to the input is must encircle the point (1. commonbase (CB) transistor network consists of capacitors (6. I I I I I Als) L I S" f ~ I I Figure 6. and C2. CD RE RB RL • L C2 o VEE 10 V o Figure 6.6 in order for the circuit to diagram.6 is known as the Nyquist The Colpitts oscillator shown in Figure 6. The plot in Figure 6.TRANSIENT ANALYSIS 175 0 i(' ie v" 0 if= ie + C. 6. The loop gain of the system.4 has the amplifier. The feedback C. .
19) where Wo is the resonant frequency of the tank circuit in the collector of transistor QI : 1 1 Wo = JLC .18) The circuit is unstable. which is less than gm.450.::====== J5' rad/ s = 21. When oscillations build up. (6.22) . the smallsignal approximation is no longer valid and the equivalent largesignal Gm must be considered.176 6 TIMEDOMAIN ANALYSIS 1m T(joo) T(joo) =a (joo)J= _ gm2L(j (0) n 00=0 Re T(joo) n Figure 6.1 . and oscillations are initiated when the loop gain is T(jwo) a(jwo)f = =  gmRL n = 1 (6.6 Nyquist diagram.20) 1012 with (6.36 MHz. 106 rad/ s 106. A good approach to ensuring steadystate oscillations (Meyer 1979) is to dimension RL so that the initial loop gain is (6. The smallsignal gain a( s) of the CB transistor is (6.21) This corresponds to an oscillation frequency fo = 3.
The analysis of oscillators with SPICE can be tricky for certain circuits because a large number of periods must be simulated before oscillations can be observed. this can be achieved by setting the emitter current. using a negative supply. 6.26) Putting Q in Eq. The above equation is very important for understanding at what rate the oscillations build up. ex = _1 (1_ gmRL) 2RC n (6.27) where K is a constant dependent on the actual oscillator configuration. RE: VEE = lOV . the longer it takes to reach steadystate oscillations. the predicted solution. in this example.24. defined by Q = R woL = woCR (6. Q. of a parallel tuned circuit. is a growing sinusoid that reaches a steadystate amplitude constrained by circuit biasing and loading. and a resistor.7. In order to complete the circuit specification. VEE. 6. Eq.27 is also valid for series resonant circuits with the appropriate change in the definition of Q. The oscillation buildup can be related to the quality factor. corresponding to complex poles in the right halfplane. The above expression shows that the higher the Q of the tuned circuit. It has a pair of complex poles leading to a timedomain solution. we need to bias the circuit.TRANSIENT ANALYSIS 177 The gain of the circuit including feedback is (6.24 leads to the following expression of the circuit response: vo(t) IX eKwot/Q sinwot (6.23) The denominator can be compared with the characteristic equation of the parallel RLC circuit. Eq. Eq. If gmRd n > 1.24) where. hE. of the form (6. Eq.11.25) and represents the damping factor. 6. 6. 6.
8) V . It is always desirable to kick the circuit in order for the program to find the oscillatory solution.VBE = RE = adEE 099(10 . Note that for the graphical output of Nutmeg or Probe.178 6 TIMEDOMAIN ANALYSIS RE gm Ie = = 4. of QI. The value chosen for RL is 750 n.VEE . to 3 f. 6.LS.TRAN 20N 3U . COLPITTS OSCILLATOR RB101 Q1 9 1 3 Mom VC1 2 9 0 VCC 4 0 10 RL 4 2 750 C1 2 3 500P C2 4 3 4.7. .MODEL Mom NPN RC=10 * .0.65K VEE 6 0 10 PULSE 15 10 0 0 0 1 * * . note that the negative supply is implemented as a step function using the PULSE source. The simulation is carried out for ten periods. The step function used in simulation is similar to the real situation of connecting a circuit to a supply before proper operation can be observed. or V ( 2) in SPICE.96mA With the above values the minimum value of RL for which. the collector voltage.076 A/V = aF .PLOT TRAN V(2) I (VC1) .OPTIONS LIMPTS=5000 ITL5=0 ACCT • END The results of the simulation. vo.5N L 4 2 5U RE 3 6 4.22. with results to be printed in the output file every 20 ns. according to Eq. Vo. are shown in graphical form in Figure 6. 103 n l. the circuit oscillates is The SPICE input COLPITTS OSCILLATOR is listed below. the time step is used only to set a default upper bound on the internal integration time interval.65 kO 0. 4. The amplitude of oscillations at the collector.65.
is a function of b = Vt/Vth and is equal to 0.7 Colpitts oscillator: collector voltage. 103 V = 2.5 Figure 6.8 and can be observed to be much smoother.TRAN 20N 3D 0 lON The new waveform resulting after replacement of the initial.89.28) The incremental part of the collector current. of QI. vo.2.95 for Vt/Vth > 6. Ie.9. .5 Time.54 V (6. is approximated by a Fourier series (Pederson and Mayaram 1990) in which the ratio of the modified Bessel functions. IlS 2.750. 1. TRAN line with the above line is shown in Figure 6. can be verified at wo: = 0.7. the maximum integration time step used by SPICE must be limited. A powerseries representation cannot be used because of the large value of Vi compared to Vth' The amplitude of Va derived above is in good agreement with the waveform in Figure 6. Iii 10. The waveform can be seen to be a piecewise linear approximation of a sinusoid. The points actually computed by SPICE are apparent on the graph. This is achieved by specifying the TMAX parameter on the • TRAN statement: . In order to obtain a smoother sinusoid.TRANSIENT ANALYSIS 179 13 12 11 > } 10 9 8 7 0.
8 Colpitts oscillator: more time points used for V ( 2 ) .. n.2. First. which computes the initial conditions.6. Exercise Verify that oscillations can be observed for RL = 395 n but not for RL = 100 exercise should prove the validity of the oscillation condition derived above. Most SPICE programs support two types of userspecified initial conditions. 4. The steadystate timedomain solution of more complex circuits is reached faster if the user initializes voltages across capacitors. Similarly.IlS Figure 6.3 INITIAL CONDITIONS The solution of the time response of electric circuits starts with the timezero values." 10 9 8 7 Time. and node voltages.180 6 TIMEDOMAIN ANALYSIS 13 12 11 > . semiconductordevice junction voltages. Note that unlike voltages initialized by . and so on.. the •NODESET statement helps the DC solution to be found faster.Ie v (node]) =value] <V(node2) =value2 . > This command sets the timezero voltage at node] to value]. that at node2 to value2. or initial conditions. A transient analysis in SPICE is preceded by an INITIAL TRANSIENT SOLUTION. userdefined initial conditions enhance the accuracy and offer quicker access to the desired solution. Initial values of charges on capacitors and semiconductor devices are also computed based on these initial voltages. as shown in Example 6. This 6. As described in Sec. currents through inductors.. initial values for node voltages can be set with the following statement: .
1. uses devicebased IC first.OP request. on the circuit solution. which in the presence of UIC has the effect of a step function. If UIC is specified on the • TRAN line. which is the result of an . a devicebased IC effects the solution only when UIC is present in the • TRAN statement. all initial values are zero No ITS. The effect of the • IC statement differs depending on whether the UIC parameter is present on the. namely. TRAN line. and the UIC keyword. Therefore the SPICE input file in Example 6. the devicebased Ie.1 summarizes the.1 UIC no no no no yes yes yes yes . uses devicebased IC. all the values in the timezero solution except the initialized node voltages are zero.4 Use a devicebased IC to set the initial current iL(O) the parallel RLC circuit in Figure 6. which are used only as initial guesses for the iterative process and then released to converge to a final solution. controlled sources. IC next. devicebased ICs have no influence No ITS.1. The third modification in the RLC description listed below is the replacement of the PWL source used for Is with a DC current.INITIAL CONDITIONS 181 • NODESET. is different from SSBS ITS uses . These values are used only in conjunction with UIC and have no effect on the INITIAL TRANSIENT SOLUTION. Table 6. In the absence of UIC an INITIAL TRANSIENT SOLUTION for the entire circuit is computed with the initialized nodes kept at the specified voltages. uses . In this table ITS stands for initial transient solution. rest of initial values are zero No ITS. and seIl1iconductor devices can b.2 is modified as shown below. Second. initial conditions for capacitors. the • IC statement. devicebased ICS have no influence ITS uses •IC voltages. As many node voltages should be initialized as possible when the UIC parameter is set. transmission lines. is different from SSBS. IC. inductors. When initial values are specified both on devices and in an • IC stateme~t. = 1 rnA through the inductor of Solution According to Table 6. the devicebased values take precedence: Table 6. effect of the different combinations of initial conditions. voltages defined by the • IC statement do not change in the final INITIAL TRANSIENT SOLUTION. which is different from the smallsignal bias solution (SSBS).e set on a devicebydevice basis using the IC keyword. . EXAMPLE 6.IC no no yes yes no no yes yes Effects o( IC Combinations SPICE2/3 Initialization ITS is equivalent to SSBS ITS is equivalent to SSBS. IC voltages. rest of initial values are zero No ITS. rest of initial values are zero Devicebased IC no yes no yes no yes no yes .
pwr TRAN V(l) .1. fXAMPLf6.27). LAMBDA = 0. KP = 40 j. The above example demonstrates the use of the devicebased rc and its applicability for finding the steadystate response.Lm. Note that omission of the keyword urc from the • TRAN statement results in damped oscillations.5 Use SPICE to simulate the behavior of the threestage enhancementdepletion (ED) MOS ring oscillator shown in Figure 6.TRAN 1US 100US UIC . This constitutes a very important observation: The fastest way to find the steadystate response of a circuit is to initialize as many elements as possible in the state they are expected to reach. VTO = 1.182 6 TIMEDOMAIN ANALYSIS PARALLEL RLC CIRCUIT IS 0 1 1MA L 101MB IC=lMA C101NF R 1 0 10K .Lm. VTO = . 6. Depletion NMOS: W = 5 j.9. the longer this phase lasts.Lm.LA/y2.8 Y. The explanation for this result is that the specified initial condition corresponds to the steadystate solution. according to Eq.Lm. L = 10 j.001 yI.2. LAMBDA = 0.3 y. The enhancement and depletion transistors have the following device and model parameters: Enhancement NMOS: W = 40 j. because devicebased rcs have no effect.001 yI. The next example will demonstrate the use of • rc for the correct initialization of a ring oscillator. as shown in Table 6.LA/y2. KP = 40 j. Solution Following is the SPICE input for this circuit: RING OSCILLATOR VDD 11 0 5 MOS * M1 1 3 0 0 ENH L=10U w=40U M2 2 1 0 0 ENH L=10U w=40U M3 3 2 0 0 ENH L=10U w=40U .END WI INITIAL CONDITION The SPICE analysis results in a constant current iL(t) = 1 rnA without the damped oscillations observed in Example 6. CGSO = 20 pF/m. L = 10 j. In the analysis of oscillators initial conditions must be used in order to shorten the simulation time during the buildup phase (the higher the Q of the circuit.
4E4 . the outputs of the three inverters. because initial conditions are set up in SPICE by connecting a Thevenin equivalent with a voltage .OOl KP=.0lU .2.5) If the circuit is analyzed as is.OOl KP=. no oscillations are observed.IC V(1)=5 V(2)=0 Resimulation of the circuit including the above line produces the waveforms shown in the graph of Figure 6.TRAN • END DEP NMOS LEVEL=l VTO=3 LAMBDA=.5 V.PLOT TRAN V(l) V(2) V(3) (0. M4 11 1 1 0 DEP L=10U W=5U M5 11 2 2 0 DEP L=10U W=5U M6 11 3 3 0 DEP L=10U W=5U * .INITIAL CONDITIONS 183 ~ ~ VDD 5V Figure 6. 5 V or 0 V.8 CGS0=20N LAMBDA=.4E4 .9 NMOS ring oscillator.MODEL * .5U . with an • IC line: . this can be achieved by initializing the outputs of the inverters at high or low values.MODEL ENH NMOS LEVEL=l VTO=1.10. The values in the initial solution are not always identical to the values in the • IC statement. Note that the data in the • IC statement are used to compute the INITIAL TRANSIENT SOLUTION in the absence of the UIC parameter. nodes 1. settle at 2. An initial imbalance is necessary for oscillations to build up. and 3.
10 Waveforms at the outputs of the inverters in the ring oscillator. The Thevenin equivalent nets are removed only at the first time point in the transient analysis.30) ak = T 2 2 ft+T t bk = T ft+T t . 6.4 FOURIER ANALYSIS A periodic signal can be decomposed into a number of sinusoidal components of frequencies that are multiples of the fundamental frequency. In other words. ns 300 400 Figure 6.29) where !ao is the DC component and the coefficients ah bk of the series are defined by ao = T 2 ft+T t v(t)dt v(t) cos(kwt)dt v(t) sin(kwt)dt (6.184 6 TIMEDOMAIN ANALYSIS 200 Time. a periodic signal can be represented by a Fourier series (Nilsson 1990): 1 v(t) = 2ao + L(ak k=! n coskwt + bk sinkwt) (6. equal to the initial value and a 10 resistor to the initialized node. These components of the signal are also referred to as spectral or harmonic components.
. The Fourier coefficients defined in Eqs. thus for good accuracy the maximum time step must be limited. or the kth harmonic component. Because of the assumption of periodicity. that is for the interval (TSTOPl/freq. A few remarks are necessary about the accuracy of the Fourier analysis in SPICE. The frequencies of the harmonics are multiples of the fundamental frequency of 1 MHz.~Ak k=l cos(kwt . is used for the Fourier series: 1 v(t) = n "2ao +.FOURIER ANALYSIS 185 The coefficients ak and bk give the magnitude of the signal of frequency kw. Only a singletone sinusoid has a single spectral component. Ab and the phase. Example ..31) where the amplitude. TSTOP). the Fourier coefficients defined above are computed based on the values of OULvar during the last period.cPk) (6. SPICE3 allows the user to define the number of harmonics to be computed. of a given signal if the following line is present along 'with the • TRAN statement: • FOUR freq OUT_varl <OULvar2 . having only one periodic component. cPb are given by (6. > In the above statementfreq is the fundamental frequency and OULvarl. In electrical engineering a different formulation. . magnitude and phase. For an accurate spectral analysis enough periods must be simulated that the circuit reaches the steady state. SPICE2 and PSpice compute the first nine spectral components for each of the signals listed on the • FOUR line. are voltages and currents the spectral components of which are to be computed.. . using TMAX on the • TRAN line.30 are evaluated based on the values for OULvar computed at discrete time points. Only one • FOUR line can be used during an analysis.. 6.32) In the timedomain mode SPICE can compute the spectral components. o ULvar2.FOUR lMeg V(3) I (VDD) This line added to a SPICE deck causes the computation of the spectral components of the voltage at node 3 and of the current through the voltage source VDD. which is at the oscillation frequency.
CGBO = 2 nF/m. = L = 5 /Lm.. CGSO = CGDO = 0.2 nF/m. 5 /Lm. The following line requests the computation of the harmonics for the output signal V ( 2 ) : .FOUR 20MEG V(2) o {.186 6 TIME.DOMAIN ANALYSIS EXAMPLE 6. L 40 /Lm.11 CMOS inverter. Ml: W M2: = W = 20 /Lm. The two transistors are described by the following model and device parameters: NMOS: PMOS: VTO = 1 V. KP = 20 /LAJV2. CGBO = 2 nF/m. Solution Because the CMOS inverter is nonlinear. CGSO= CGDO=0.topeak amplitude of 5 V and a frequency of 20 MHz.2 nF/m. VTO= 1 V.6 Verify the spectral values computed by SPICE2 for the output signal of the CMOS squarewave clock generator shown in Figure 6. A sinusoidal voltage source is applied at the input with a peak.\ VDD 5V Figure 6. . KP= 10 /LAJV2. the output signal contains harmonics of the 20MHz input sinusoid.11.
2N . V (2 ).OPTION RELTOL = 1E4 in order to obtain the waveform in Figure 6.12. and the phases. simulation of two periods is sufficient for this circuit because no oscillations need to settle. END The output waveform. Note that if the above deck were used the output voltage would display some ringing. The results of the Fourier analysis are listed in Figure 6. as showI1 in Figure 6.2 and 9. the amplitude of the fundamental is 3. The DC component computed by SPICE2 is 2. Ak> are listed under FOURIER COMPONENT. The SPICE deck . and all the even harmonics are negligible. This problem can be corrected by SPICE2 analysis option parameters.FOURIER ANALYSIS 187 The period of the output signal is 50 ns. cPk> appear in the PHASE (DEG) column. 2N CGSO=.15 V. The results of the Fourier analysis are listed according to the formulation in Eq.29 and 6. A l.5 20MEG VTO=l VTO=l KP=20U KP=10U .MODEL NMOS NMOS LEVEL=l * + + CGID=. The output signal. the magnitudes of the spectral components. shown in Figure 6. For this circuit it is necessary to add the line . is a square wave. 2N CGB0=2N 1N lOON (1.MODEL PMOS PMOS LEVEL=l .31. PLOT TRAN I (VDD) .12 can be expressed as follows: vo(t) = 0 for 0 < t < 2 T for 2 :5 T t <T .OP . until 100 ns.5. 2N CGBO=2N CGID=.FOUR 20MEG V(2) . and the analysis is requested for two periods.13.30. 6.4.12. of the fundamental.for this ex'ample is CMOS INVERTER M1 2 1 0 0 NMOS W=20U L=5U M2 2 1 3 3 PMOS W=40U L=5U VDD 3 0 5 VIN 1 0 SIN 2.5 V.5 2. vo(t) (V (2) ).CGSO=.5) . In the Fourier analysis output two additional columns list the amplitudes of the spectral components normalized to the amplitude. 6.PLOT TRAN V(2) V(l) . and the phases normalized to cPl' The Fourier series coefficients can be easily checked with Eqs. described in Sees 9.TRAN . which is due to numerical inaccuracy.
613225E+01 PHASE (DEG) 1. I.249E02 2.791E+02 1. J I .061E02 3.503637E+00 FOURIER COMPONENT 3. .694E+01 2.74SE+00 . 593E+02 1. \.561E03 3.000 DEG C FOURIER COMPONENTS OF TRANSIENT 2. I .S9SE01 3.946E01 1.188 6 TIMEDOMAIN ANALYSIS 5 '\ 4 r '\ > 3 g > 2 o \. I.055E01 3. 7S2E+02 PERCENT NORMALIZED PHASE (DEG) O.962E+01 2. .009E+01 4.13 Fourier analysis results for the squarewave voltage V ( 2 ) .907E01 DISTORTION RESPONSE V (2) DC COMPONENT HARMONIC NO 1 2 3 4 5 6 7 S 9 = FREQUENCY (HZ) 2.970E03 9.362E02 4.000E+07 1..945E03 4.000E+07 4. 80 . ns . .555E02 1. 40 Time.400E+OS 1.941E03 6.000E+00 2.692E01 2. 791E+02 1.000E+07 S.160E03 1.576E+02  . .7.3.573E01 3. 19SE+02 1. SOOE+OS NORMALIZED COMPONENT 1.951E01 1.600E+OS 1.797E01 . 20 60 Figure 6. I J .OOOE+OO 5.12 Squarewave signal V ( 2) at the output of the CMOS inverter.147E+00 S. 716E+02 1. **** FOURIER ANALYSIS TEMPERATURE = 27.000E+07 6.799E+02 1.612E01 9.05SE03 9.200E+OS 1. TOTAL HARMONIC = Figure 6.000E+OS 1. 425E+02 1. 794E+02 1.
A useful application of the Fourier analysis is the evaluation of largesignal distortion.33) In the design of many circuits the THD must be kept below a specified limit. that is. and b3. The TOTAL HARMONIC DISTORTION (THD) computed by SPICE is equal to (6. J(t) =  J(t . are derived by solving the integral in Eqs.12: 2 bi = l' Jo 2 (T vo(t) sin(wt)dt T = 1'VDD TI2 t 10 2 Jo (T12 sin(wt)dt 2.30 for the two values of vo(t) corresponding to the halfperiods of the waveform in Figure 6.T /2) making all coefficients bk with even k equal to zero (Nilsson 1990). is Ao = 2ao = l' 1 1 Jo (T vo(t)dt = 25 V 1 = 2. Ao.FOURIER ANALYSIS 189 The DC component. The small discrepancies with the SPICE2 Fourier coefficients can be attributed to the imperfection of the square wave V ( 2 ) .06 V The above coefficients scaled by the appropriate DC value are generally valid for any square wave.5 = 1" 2'1T VDDCOS T b2 b3 = (2'1T) = . 6. bl> b2. vo(t) also possesses halfwave symmetry.V = 3. The first three harmonics.5 V Before deriving the coefficients of the harmonics.. note that the function is of odd symmetry: J(t) = J(t) Thus all coefficients ak are zero.18 V 0 2VDD 3'1T = = 1. The second and third NORMALIZED COMPONENTS listed among the Fourier analysis results .
190
6
TIMEDOMAIN ANALYSIS
correspond to HD2 and HD3 in the AC smallsignal distortion analysis presented in Chapter 5. If the results of the two analyses are compared, the Fourier components should be scaled by the reference power, Pref, in the load resistor to match the values of HD2 and HD3. More detail on the two types of distortion analysis can be found in Chapter 8. Sinusoidal oscillators for various applications must have a small content of harmonics. It is instructive to compute the harmonic content in the output voltage of the Colpitts oscillator.
EXAMPLE 6.7
Use Fourier analysis to find the total harmonic distortion of the output signal of the Colpitts oscillator in Figure 6.4.
Solution
For an accurate estimate of the harmonics, the circuit needs to be simulated for more than the 10 periods used in Example 6.3. We will perform a transient analysis for 10 JLS corresponding to 33 periods; the • TRAN line in the input file is replaced by the following line:
.TRAN 15N lOU 9.3U 15N
The waveform is saved for displaying only the last two periods, and limiting TMAX to 15 ns ensures that at least 20 time points are used in each period to evaluate the response. The following statement defines the frequency of the fundamental and the output variable for which the spectral components are desired:
.FOUR 3.36MEG V(2)
The frequency of the fundamental must be specified as accurately as possible, because an error as small as 1% can make a difference in the values of the Fourier coefficients. The output ofthe Fourier analysis from SPICE2 is listed in Figure 6.14. Note that the amplitude of the fundamental found by the Fourier analysis agrees with the value computed by hand in Example 6.3, Eq. 6.28. The THD of the sinusoidal signal produced is 8.25%.
A few comments are necessary regarding the implementation of Fourier analysis in SPICE3. Although the limit of only nine harmonics imposed by SPICE2 and most other SPICE versions is not a problem for most circuits, this limitation can become an impediment in finding the intermodulation (1M) terms for such circuits as mixers. In
SUMMARY
191
****
FOURIER ANALYSIS
TEMPERATURE
=
27.000 DEG C
FOURIER COMPONENTS OF TRANSIENT RESPONSE V (2) DC COMPONENT HARMONIC NO
1
=
1.000407E+00l FOURIER NORMALIZED COMPONENT COMPONENT 2.523E+000 1.890E00l 7.725E002 3.532E002 1.602E002 7.680E003 4.226E003 2.962E003 2.516E003
=
FREQUENCY (HZ) 3.360E+006 6.720E+006 1.008E+007 1.344E+007 1.680E+007 2.016E+007 2.352E+007 2.688E+007 3.024E+007
PHASE (DEG) 8.683E+00I 1.545E+002 1.471E+002 1.374E+002 1.257E+002 1.111E+002 9.404E+00I 7.896E+00I 6.880E+00I
NORMALIZED PHASE (DEG) O.OOOE+OOO 6.769E+00I 6.027E+00I 5.054E+00I 3.886E+00I 2.426E+00I 7.206E+000 7.869E+000 1.803E+00l
2 3 4 5 6
7
8 9
1.000E+000 7.490E002 3.062E002 1.400E002 6.420E003 3.044E003 1.675E003 1.174E003 9.971E004
TOTAL HARMONIC DISTORTION
8.245843E+000 PERCENT
Figure 6.14 Fourieranalysisof the Colpittsoscillator.
SPICE3 the user can define the number of harmonics to be computed by issuing the following set command in the SPICE3 shell: spice3> set nfreqs=n where nfreqs is the keyword and n is the desired number of harmonics. The default for n is 9. Another variable that can be set by the user in SPICE3 is the degree of the polynomial used to interpolate the waveform. In order to request polynomial interpolation of higher degree, the following command must be issued at the SPICE3 shell prompt: spice3> set polydegree=n where polydegree is the keyword and n is the degree.
6.5
SUMMARY
This chapter presented the analyses performed by SPICE in the time domain. The control statements for each analysis were introduced as well as the specifications of output variables and resultprocessing requests. Emphasis was placed on exemplifying the transient and steadystate responses of both a linear and a nonlinear circuit and comparing the manual derivation with SPICE simulations.
192
6
TIMEDOMAIN
ANALYSIS
SPICE supports two analysis types in the time domain, transient and Fourier analysis, which are specified by the following control lines: . TRAN TSTEP TSTOP <TSTART <TMAX> > <UIC> .FOUR
freq OULvar] <OULvar2 ... >
The. IC (initial conditions) statement is a third control statement introduced in this chapter used for specifying the known node voltages at time t = 0: . IC V (node] )=valuel <V (node2) =value2 ...
>
Initial conditions can also be defined for individual elements; terminal voltages and initial currents can be used to initialize chargestorage and nonlinear elements. Elementbased initial conditions are taken into account only in conjunction with the UIC (use initial conditions) option in the • TRAN statement. Table 6.1 summarizes the ways of setting initial conditions. The waveforms of voltages and currents computed in a transient analysis must be saved by use of the. PRINT or • PLOT control statement, in tabular or lineprinterplot format, respectively. The general format of the output request that must accompany a • TRAN line is . PRINT/PLOT TRAN OUT_var] <OULvar2 ...
> <ploLlimits>
The seven detailed examples in this chapter also highlighted the relation between largesignal timedomain analysis and smallsignal AC analysis.
REFERENCES
Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits, 3d. ed. New York: John Wiley & Sons. Meyer, R. G. 1979. Nonlinear integrated circuits. In EE 240 Class Notes. Berkeley: University of California. Nilsson, 1. W. 1990. Electric Circuits, 3d ed. Reading, MA: AddisonWesley. Pederson, D.O., and K. Mayaram. 1990. Integrated Circuits for Communication. Boston: Kluwer Academic Publishers.
Seven
FUNCTIONAL AND HIERARCHICAL SIMULATION
7.1
HIGHLEVEL CIRCUIT DESCRIPTION
The example circuits presented in previous chapters use circuit elements, such as resistors, capacitors, and transistors, that have a onetoone correspondence with components on electronic circuit boards or ICs. Such a description is generally referred to as a structural representation of the circuit. The simulation of a structural circuit produces very accurate results, but may take a long time. The analysis time grows proportionally to the number of components and is dominated by semiconductor elements, which are described by complex nonlinear equations. The analysis time sets a limit on the size of circuits that can be simulated at the structural level. Although circuits with several hundred to a few thousand components can be analyzed with SPICE on current PCs and engineering workstations, alternate ways of modeling circuits can increase design productivity. The most common approach is to group several components in a block according to the function performed. According to this criterion, we can distinguish gain blocks, oscillators, integrators, differentiators, NAND and NOR blocks, adder blocks, and so on. Then, the SPICE description needs to be an equivalent circuit that achieves the same function as the componentlevel implementation. This functional model can be built with fewer components and with special SPICE elements, such as controlled sources. Simulation times for circuits with functional models are considerably shorter than those for detailed circuits.
193
194
7
FUNCTIONAL
AND HIERARCHICAL SIMULATION
SPICE provides a subcircuit capability, which allows a user to define a subnet or a block and then instantiate it repeatedly in the overall circuit. For example, the functional, or transistorlevel, schematic of a NAND gate can be defined once and then instantiated repeatedly to form complex digital or mixed analog/digital circuits. This SPICE feature and its application for large circuits is described in Sec. 7.2. When the SPICE input of large circuits is prepared, the netlist description can be very long and difficult to understand. A hierarchical approach to describing large circuits is recommended; with this approach a designer can quickly recognize the toplevel block diagram of the circuit from the SPICE description. The subcircuit definition capability of the SPICE input language provides the means for hierarchical descriptions. An example of SPICE hierarchical definition is described in Sec. 7.2. In a hierarchical description various blocks can be described at different levels of accuracy. The simplest representation of the function of a given block is an ideal model. Ideal functional blocks are introduced in Sec. 7.3 for both analog and digital circuits. Ideal blocks are very simple and result in short simulation times but may not provide sufficient accuracy or adequate SPICE convergence, as described in Chap. 10. More complex models for SPICE simulation can be developed, which reproduce detailed characteristics of the circuit, such as limited output swing, finite bandwidth, and other range restrictions. These models combine SPICE primitives (Chap. 2) and arbitrary functions (Sec. 7.4.1) to formjunctional models. A few examples of functional models are presented in Sec. 7.4. All details of the operation of circuit blocks or entire ICs can be built into SPICE primitives. The macromodel can incorporate all or a part of the first and secondorder effects of a circuit with a considerably smaller number of elements, resulting in significantly shorter simulation times. An operational amplifier macromodel commonly used by many suppliers of SPICE models for standard parts is described in Sec. 7.5.
7.2
7.2.1
SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY
.SUBCKT Definition A circuit block that appears more than once in the overall circuit and consists of SPICE primitives can be defined as a subcircuit (Vladimirescu, Zhang, Newton, Pederson, and SangiovanniVincentelli 1981). The block can then be referenced as a single component, the subcircuit instance, and connected throughout the circuit. There is a similarity between the. SUBCKT definition and the .MODEL definition. Whereas a .MODEL statement defines a set of parameters to be collectively used by a number of devices, the • SUBCKTdefinition represents a circuit topology, which can be connected through its external pins or nodes anywhere in the circuit. The elements that form the sub circuit block are preceded by the following control statement: . SUBCKT SUBname node} <node2 ...
>
SPICE SUBCIRCUIT
AND CIRCUIT
HIERARCHY
195
where SUBname uniquely identifies the subcircuit and nodel, node2, ... are the external nodes that can be connected to the external circuit. There is no limit to the number of external nodes. The rest of the nodes in the subcircuit definition are referred to as internal nodes. The internal nodes cannot be connected or referenced in the toplevel circuit. The ground node, node 0, is global from the top circuit through all subcircuits. The completion of the subcircuit definition is marked by the following line:
. ENDS
<SUBname>
Repetition of SUBname is not required, except for nested subcircuit definitions, but is recommended for the ease of checking the correctness of the circuit description. In addition to SPICE elements, a number of control statements can be used within a subcircuit definition. Local •MODEL lines introduce models that can be referenced only by elements that belong to the subcircuit. Other • SUBCKT definitions can be nested inside a subcircuit; nested subcircuits can only be referenced from the subcircuit in which they are defined. No other control lines, that is, analysis, print/plot, or initialization requests, are allowed in a subcircuit definition. One difficulty created by this restriction is related to initializing node voltages. Although device initial conditions can be defined for elements inside a subcircuit, no • NODESET or . IC statement can be used to set the starting voltages on internal nodes. This limitation is overcome by declaring all nodes that require initialization as external nodes on the • SUBCKT line.
7.2.2
Subcircuit Instance
A subcircuit block is placed in the circuit by an Xelement call, or subcircuit call, defined by the following line:
Xname xnodel <xnode2 ... > SUBname
The letter X must appear in the first column to identify a subcircuit instance; the number of nodes must be equal to those on the corresponding subcircuit definition, SUBname. xnode l, xnode2, ... , are the numbers or names of the nodes that are to correspond with the nodes nodel, node2, ... of the. SUBCKT line, at the circuit level where SUBname is instantiated. Subcircuit definition and calls can be exemplified by a hierarchical description of the threestage ring oscillator in the previous chapter, Example 6.5. The new SPICE description, using inverters rather than the detailed schematic of the circuit as in Figure 6.9 is listed in Figure 7.1. The corresponding circuit diagram is shown in Figure 7.2.
7.2.3
Circuit Hierarchy
The SPICE subcircuit capability offers the designer the ability to describe a complex circuit in a hierarchical fashion. Any number of hierarchical levels can be defined. The
196
7
FUNCTIONAL
AND HIERARCHICAL SIMULATION
RING OSCILLATOR WI MOS INVERTERS Xl 1 2 5 INVERTER X2 2 3 5 INVERTER X3 3 1 5 INVERTER VDD 5 0 5
*
*
* .SUBCKT INVERTER 1 2 3 * NODES: VIN, VOUT, VDD
M1 2 1 0 0 ENH L=10U W=40U M2 3 2 2 0 DEP L=10U W=5U
*
.MODEL DEP NMOS LEVEL=l VTO=3 LAMBDA=.OOl KP=.4E4 .MODEL ENH NMOS LEVEL=l VTO=l.8 CGS0=20N LAMBDA=.OOl KP=.4E4 INVERTER
* .ENDS
*
.IC V(l)=5 V(2)=0 .TRAN .0lD .5U .PLOT TRAN V(l) V(2) V(3) (0, 5) .WIDTH OUT=80 .END SPICE input for ring oscillator with MOS inverters using
.SUBCKT.
Figure 7.1
hierarchical description of an adder built from NAND gates is presented in this section as an example of the proper application of the SPICE • SUBCKT statement.
EXAMPLE 7.1 Use sub circuits and hierarchy to create the SPICE input of the 4bit adder built with TIL NAND gates that is shown in Figure 7.3 (Vladimirescu 1982). Partition the adder at the following levels: NAND gate, Ibit adder, and 4bit adder. Run SPICE to find the DC operating point of the Ibit adder and interpret the results.
Solution
The first step is to write the SPICE netlist of the TIL NAND gate in Figure 7.3.a. This description is listed between the . SUBCKT NAND and . ENDS NAND lines. The external nodes, or terminals, of the NAND gate are the two inputs INl and IN2, the output, OUT, and the supply connection, VCC. These are the only pins needed for connecting a NAND gate in an external circuit and correspond to the pins available in a 7400series TILle.
SPICE SUBClRCUIT AND CIRCUIT HIERARCHY
197
Figure 7.2
Ring oscillator with MOS inverters.
Next, a description of the Ibit adder is created by specifying how the nine NAND gates in the schematic in Figure 7.3.b are connected. The NAND gates are instantiated in the Ibit description using the X element. This new circuit is labeled as subcircuit ONEBIT and is used at the next level of the hierarchy to define the 4bit adder. The external nodes of ONEBIT are the two inputs, A and B, the carryin bit, CIN, the output, OUT, and carryout bit, COUT, as well as the supply, vee. When digital circuits are described in the following sections of this chapter, node names are uppercase, such as A and OUT, the voltages or analog signals at these nodes are indicated by an uppercase V, as in VA and VOUT, and the boolean (digital) variables associated with the terminals are lowercase, such as a and out. Four ONEBIT subcircuits are connected according to Figure 7.3.c to form the 4bit adder. Four instances (X) of ONEBIT are needed to define the FOURBIT subcircuit. The hierarchical SPICE definitions of the 4bit and Ibit adders and the NAND gate are listed in Figure 7.4. All the toplevel input and output pins of the 4bit adder are
198 7 FUNCTIONAL AND HIERARCHICAL SIMULATION IN1 I~ ~OUT IN2 OUT IN2 (a) .. GOUT A B . . (c) 4bit adder.0 GINOUT A OUT B GOUT (b) ri I I RITO BITI GIN GOUT BITO A BOUT BIT1 BIT2 GIN GOUT A BOUT  FOURRIT BITJ I GIN GOUT I BIT2 A B I BIT3 OUT I  ~ (c) Figure 7. (b) Ibit adder with symbol.3 Hierarchy of 4bit adder: (a) TTL NAND gate.
BlTO(2) / BIT1(2) / BIT2(2) / BIT3(2) .SUBCKT ONEBIT 1 2 3 4 5 6 NODES: A B CIN OUT COUT VCC Xl 1 2 7 6 NAND X2 1 7 8 6 NAND X3 2 7 9 6 NAND X4 8 9 10 6 NAND X5 3 10 11 6 NAND X6 3 11 12 6 NAND X7 10 11 13 6 NAND X8 12 13 4 6 NAND X9 11 7 5 6 NAND . * OUTPUT . CARRYIN.SUBCKT * Figure 7.4 Hierarchical SPICE definition of a 4bit adder.BITO / BIT1 / BIT2 / BIT3. . 6K Q3 6 9 8 QMOD R2 8 0 1K RC 4 7 130 Q4 7 6 10 QMOD DVBEDROP 10 3 DMOD Q5 3 8 0 QMOD . The DC operating point of the Ibit adder can be found by running the SPICE deck shown in Figure 7.4 BIT ALLNANDGATE BINARY ADDER .SUBCKT NAND 1 2 3 4 NODES: IN1 IN2 OUT VCC Q1 9 5 1 QMOD D1CLAMP 0 1 DMOD Q2 9 5 2 QMOD D2CLAMP 0 2 DMOD RB 4 5 4K R1 4 6 1. The SPICE2 output in Figure 7.4 for NAND and ONEBIT.ENDS ONEBIT * * FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NODES: INPUT . CARRYOUT. VCC Xl 1 2 13 9 16 15 ONEBIT X2 3 4 16 10 17 15 ONEBIT X3 5 6 17 11 18 15 ONEBIT X4 7 8 18 12 14 15 ONEBIT .ENDS FOURBIT (continued on next page) * . respectively.SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 199 connected to signal sources or resistors.5 with the subcircuit definitions listed in Figure 7. The 4bit adder circuit defined in Figure 7.ENDS NAND * * .4 has three levels of hierarchy.5 seems confusing at first. A long list of node ADDER .
SUBCKT NAND 1 2 3 4 NODES: IN1.6 3/15/83 ******** 17:44:45 ******* ADDER . 200 .ENDS NAND Figure 7. OUT.0 1 DMOD Q2 9 5 2 QMOD D2CLAMP 0 2 DMOD RB 4 5 4K R1 4 6 1.MODEL .*** *** DEFINE NOMINAL CIRCUIT *** Xl 1 2 3 4 5 6 7 8 9 10 11 RBITO 9 0 1K RBIT1 10 0 1K RBIT2 11 0 1K RBIT3 12 0 1K RCOUT 13 0 1K VCC 99 0 DC 5V VIN1A 1 0 PULSE(O 3 0 10NS VIN1B 2 0 PULSE(O 3 0 10NS VIN2A 3 0 PULSE(O 3 0 10NS VIN2B 4 0 PULSE(O 3 0 10NS VIN3A 5 0 PULSE(O 3 0 10NS VIN3B 6 0 PULSE(O 3 0 10NS VIN4A 7 0 PULSE(O 3 0 10NS VIN4B 8 0 PULSE(O 3 0 10NS 12 0 13 99 FOURBIT 10NS 10NS 10NS 10NS 10NS 10NS 10NS 10NS 10NS SONS) 20NS lOONS) 40NS 200NS) 80NS 400NS) 160NS 800NS) 320NS 1600NS) 640NS 3200NS) 1280NS 6400NS) * .4 (continued) ******* 02/24/92 ***** SPICE 2G. Q3 6 9 8 QMOD * R2 8 0 1K RC 4 7 130 Q4 7 6 10 QMOD DVBEDROP 10 3 DMOD Q5 3 8 0 QMOD .OPT ACCT .000 DEG C *************************************************************************** .OP DMOD D .5 SPICE2 output for Ibit adder. VCC Q1 9 5 1 QMOD D1CLAMP . IN2.6K.MODEL QMOD NPN(BF=75 RB=100 CJE=lPF CJC=3PF) .1 BIT ALLNANDGATE BINARY ADDER **** INPUT LISTING TEMPERATURE 27.END Figure 7.
X1 RB.X9. Xl.X9.OPT ACCT NODE .X1 Q1.X1 D2CLAMP* Q1.X1 VCC Q2.X6. COUT. OUT.X1 Q5.X1 Rl.X1 RC. VCC Xl 1 2 7 6 NAND X2 1 7 8 6 NAND X3 2 7 9 6 NAND X4 8 9 10 6 NAND x5 3 10 11 6 NAND X6 3 11 12 6 NAND X7 10 11 13 6 NAND X8 12 13 4 6 NAND X9 11 7 5 6 NAND .X3.X7.X1 RB.X1 Q5.X8.X1 Q1.X8.X1 Q2.X9.X2. CIN..X4.X1.X1 Figure 7.5 .MODEL DMOD D .X7.6 3/15/83 ******** 17:44:45 **** .X1 RB.X1 RC.X7.X1 RC.X2.X1 RC.X1 R1.X1.ENDS ONEBIT *** *** DEFINE NOMINAL CIRCUIT *** Xl 1 2 9 0 13 99 ONEBIT RBITO 9 0 1K RCOUT 13 0 1K .WIDTH OUT=80 .X1 D2CLAMP* Q5.SUBCKT ONEBIT 1 2 3 4 5 6 * NODES: A.X1 Q1.X1 Q1.X3.X1.X1 Q1.X1 Rl.X6.X1 Rl.X1 RB.X2.000 DEG C *************************************************************************** 1 2 9 13 99 VIN1A VIN1B RBITO RCOUT RB.X2.X2.X1.X2.X4.X1 R1.END ******* ADDER **** 02/24/92 ******** SPICE 2G.X1 RC.X3.X1 RB.X4.X1 Q2.X1 D2CLAMP* D1CLAMP* D2CLAMP* DlCLAMP* DlCLAMP* DlCLAMP* Q5.X5.X1 R1.X1 DVBEDRO* Q2.X6.X1 RC. B.X6.X1 RB.X1 DVBEDRO* DVBEDRO* (continued) ')1\1 100 101 102 DlCLAMP* D2CLAMh DlCLAMh DVBEDRO* Rl.MODEL QMOD NPN(BF=75 RB=100 CJE=lPF CJC=3PF) VCC 99 0 DC 5V VIN1A 1 0 PULSE(O 3 0 10NS 10NS 10NS 50NS) VIN1B 2 0 PULSE(O 3 0 10NS 10NS 20NS lOONS) * * .X1 RC.X1 R1.X8.X1 RB. Xl RC.X1 Q2.X5.X9.OP .X5.X4.X4.X3.X1 Rl.X3.X1 RB.Xl.X5.1 BIT ALLNANDGATE ELEMENT NODE TABLE BINARY ADDER TEMPERATURE = 27 .X3.X9.X1 RC.
X1 Q4.X7.X1.X8.X3.X1 R1.X5.X1 Q1.X1 Q4.X1 Q3.X1 (continued) D2CLAMP* D1CLAMP* Q5.X7.X1 Q3.X3.X1 R1.X7.X4.X3.X1 Q4.X1 D2CLAMP* D2CLAMP* D1CLAMP* Q5.X1 RB.X7.5 202 .X1 Q2.X1 Q1.X4.X1 R2.X6.X1 Q3.X1 DVBEDRO* Q1.X5.X1.X1 Q5.X1 R1.X5.X2.X2.X1 R1.X7.X1 DVBEDRO* Q1.X1 Q4.X7.X3.X4.X4.X3.X1 Q1.X1 DVBEDRO* Q1.X1 RB.X1 R2.X1 Q2.X6.X1 Q3.X7.X1 Q3.X1 Q2.X5.X2.X4.X3.X1.X1 Q4.X6.X6.X1 Q4.X1 Q1.X6.X1 Q2.X1 Q5.X4.X1 Q5.X6.X1 R2.XB.X2.X5.X1 RB.X2.X6.X1 Q4.X1 Q2.X1 Q4.X7.X1 Q5.X3.X1.X1 RB.X1 Q3.X6.X6.X6.X5.X5.X4.X6.X1 Q1.X2.X2.X1 Q5.X5.X1 Q2.X3.X6.X1 Q1.X1 Q4.XB.X3.X3.X7.X1 Q4.X3.X2.X1.X3.X1 Q2.X1 RC.X5.X1 Q4.X1 RC.X1.X1 Q4.X1 Q2.X1 RC.X1 Q3.X1.X1.X1 Q2.X5.X7.X2.X1 Q2.X2.X1 DVBEDRO* Q1.X1 R1.X1 RB.X2.X1 Q4.X5.X7.X1 Q3.X7.X5.X2.X5.X1 DVBEDRO* Q1.X1 Figure 7.XB.X1 Q5.X1 Q1.X7.X6.X1 DVBEDRO* DVBEDRO* Q1.X1 Q5.X1 Q2.X1 Q4.X1 R2.X4.X7.X9.X1.X1 RB.X2.X3.X6.X1 Q3.X1 Q3.X1 DVBEDRO* Q1.X1 Q5.X7.X2.X1 Q3.X1 Q2.X1 Q3.X1 Q2.X1.X1 Q3.X6.X1 RB.X1 Q3.X1 Q4.X3.X1 Q4.X1 Q3.X4.X8.X1 RB.X1 Q4.X4.X1 Q3.X1.X5.X7.X1.X4.X1 Q4.X4.X3.X7.X1 Q1.X1 Q2.X7.X8.X1 Q2.X6.X6.XB.X1 Q4.X1 R2.X4.X1 R1.X1 Q2.X1 Q1.X1 Q4.X4.X1 DVBEDRO* Q1.X1 Q5.X8.X5.X1 Q3.X2.X1 R1.X1 Q3.X1.X1 RC.X5.103 104 105 106 107 lOB 109 110 111 112 113 114 115 116 117 11B 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 14B 149 150 DVBEDRO* DVBEDRO* Q1.X1 D1CLAMP* D2CLAMP* Q2.X1 Q3.X5.X1 RC.X1 Q4.X1 Q1.X1 R2.X1.X1.X4.X1 Q2.X1 RC.X1 RC.X1 Q3.X4.X1 R2.X1 Q2.X1 Q3.X1 Q2.X1 Q3.
000 DEG C *************************************************************************** NODE 1) ( 99) (103) (107) (111) (115) (119) (123) (127) (131) (135) (139) (143) (147) (151) (155) (159) VOLTAGE 0.X1 RC.9763 4.X1 RB.9998 1.5339 0.8752 4.X1 Q5.X8.X1 Q5.8448 4.X9.5919 4.1152 0.9639 1.0642 2) (100) (104) (108) (112) (116) (120) (124) (128) (132) (136) (140) (144) (148) (152) (156) (160) VOLTAGE SOURCE CURRENTS NAME VCC VIN1A VIN1B CURRENT 1.X1 Q3.1899 0.X1 02/24/92 ******** Q4.0870 0.9642 4.X8.1122 0.1 BIT ALLNANDGATE BINARY ADDER **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.X8.6308 3.5122 0.X1 Q2.9998 NODE ( VOLTAGE 0.0000 2.7590 0.0178 3.2526 1.0179 4.7979 4.9745 0.X9.X8.9998 4.X8.X1 Q1.9941 1.X9.8448 4.6 3/15/83 ******** 17:44:45 **** ADDER .9724 0.X1 Q3.X1 SPICE 2G.0000 0.0877 1.X9.X8.9897 4.8752 4.4845 1.0000 0.X8.X1 Q1.X1 Q2.X9.X1 Q4.0000 1.0363 4.4928 4.0745 0.SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 203 151 152 153 154 155 156 157 158 159 160 ******* R1.7685 0.X1 Q4.X1 Q4.0000 0.0309 0.0363 4.075003 2.0672 4.2529 1.X1 Q3.0000 3.8268 4.8444 4.7616 3.X9.X1 R1.9941 1.38002 WATTS TOTAL POWER DISSIPATION Figure 7.X9.9639 4.0000 2.X8.9642 1.X9.X9.2529 0.8567 0.1940 0.7459 0.X9.0672 4.X1 R2.0000 5.X1 Q3.X1 DVBEDRO* Q4.X1 Q3.X1 RC.5278 3.6303 0.X1 DVBEDRO* Q4.X9.0500 2.X9.X9.X8.9994 4.X9.075003 9.876002 2.5005 NODE ( 9) (101) (105) (109) (113) (117) (121) (125) (129) (133) (137) (141) (145) (149) (153) (157) VOLTAGE 0.8320 4.1020 NODE ( 13) (102) (106) (110) (114) (118) (122) (126) (130) (134) (138) (142) (146) (150) (154) (158) VOLTAGE 0.X9.5 (continued) .9941 0.6308 3.X1 R2.
In order to understand the.3 IDEAL MODELS Ideal models are the simplest and computationally most efficient. The composite name starts with the component name followed by the subcircuit instance names that call it. a designer can choose among several levels of detail and accuracy for each hierarchical block. The following sections present several approaches to defining SPICE models for more complex blocks. Because the detailed design of an opamp is complex. The ELEMENT NODE TABLE generated by SPICE2 is also part ofthe output listed in Figure 7. 9.meaning of these newly created node numbers the user must request the NODE option on an • OPTION line: . In the adder example the last node number is 99. PSpice uses the composite node names in the SSBS printout. As described in the following sections. therefore all threedigit numbers are introduced due to subcircuit expansion and the meaning of each node can be derived from the ELEMENT NODE TABLE. but it may not be economical. The operational amplifier. the names at different levels of hierarchy are separated by periods. Once a hierarchy of a circuit is established. macromodel or as a detailed model. This process is similar to using simpler or more complex transistor models by selectively specifying values of model parameters representing certain secondorder effects. X2 . A practice that distinguishes the toplevel circuit nodes from those generated by the program due to subcircuit expansion is to make the last node number in the toplevel circuit easy to identify. for example. Xl is the resistor RB of the X2 NAND instance that is part of the Ibit adder Xl. functional. for both analog and digital circuits an ideal model provides only the single most relevant function of a device. OPTION NODE For more detail on SPICE options see Chap.5. an opamp is a gain block and . Describing a block by the detailed structural schematic is always straightforward if the schematic is known.204 7 FUNCTIONAL AND HIERARCHICAL SIMULATION numbers appears in the SMALLSIGNAL BIAS SOLUTION (SSBS) section. including from 20 to 50 transistors. both analog and digital. in this case the NAND gate definition level. making it difficult to trace the hierarchy path of elements having long names. which is widely used in many designs and is considered a basic circuit element due to its availability in IC implementation can be described as an ideal. Component RB. 7. The composite names are limited to eight characters in SPICE2.5. it is advisable to select the representation with only those characteristics that are relevant for a given design. 9. The name of an element connected at a node is formed by concatenating the names of the X calls at every level of hierarchy to the element name of a SPICE primitive appearing at the bottom of the hierarchy. especially the summary in Sec.
7 by replacing Zf with a capacitor Cf and Zi with a resistor Ri.6 Idealopamp. 7. as shown in Figure 7. The correct operation as an integrator can be checked with SPICE both in the time domain and the frequency domain. and amplifiers. Although very efficient in simulation ideal models can cause problems in SPICE analyses due to the ideality. and low output resistance.6. The output voltage in the frequency domain is given by (7. . An ideal opamp can be reduced to a gain block with infinite input resistance and zero output resistance. Oldham and Schwartz 1987.3. very high input resistance.7.IDEAL MODELS 205 a transistor is a switch.1 Operational Amplifiers The main characteristics of an opamp are very high gain.2) This feedback connection is often used to implement integrators.1) A commonly used circuit configuration of the opamp is shown in Figure 7. The principle of the virtual short can be applied in the analysis of circuits with ideal opamps (Dorf 1989. Figure 7. filters. Paul 1989. differentiators. An ideal integrator can be built with the circuit in Figure 7. Sedra and Smith 1990). This assumption consists of Vid = 0 (7.
as shown in Figure 7. .8 Bandpass filter. C = I nF.6.8. Note that the ideal opamp is defined as a subcircuit (.Rf = 10 ko'. BANDPASS FILTER WI IDEAL OPAMP XOP1 0 1 2 OPAMP RI 3 4 100 CI 1 3 1N RF 1 2 10K CF 1 2 1N VID40AC1 * * Figure 7. Use the ideal opamp description with av = 105 and the following values for the resistors and capacitors: Ri = 100 0.206 7 FUNCTIONAL AND HIERARCHICAL SIMULATION Figure 7. Solution The SPICE input is listed below.2 Check the operation as a bandpass filter of the circuit shown in Figure 7. Cf = I nF. SUBCKT) that contains just a voltagecontrolled voltage source.7 Opamp in feedback configuration. EXAMPLE 7..
AC DEC 10 10 1G . where 1/ (RfCf) « w « 1/ (RiCi).Q.3) In the passband.WIDTH OUT=80 .SUBCKT OPAMP 1 2 3 EGAIN 3 0 1 2 1E5 .IDEAL MODELS 207 . Va versus Vid.59 MHz.9 kHz to 1.2: H(jw) = Vo Vid = _ Rf . that is. as shown by the transfer characteristic. The output voltage of the openloop ideal opamp model. 7. The Bode plot produced by SPICE is in agreement with the behavior predicted by Eqs. can rise to thousands of volts.10.END The transfer function of this active filter is obtained through substitution of the expressions for Zi and Zf in Eq.ENDS . which limits the excursion of the output signal. 7.PRINT AC VDB(2) VP(2) . the passband extends from 15.9. possibly causing simulation problems depending on the circuit. A very important nonideality factor to consider in largesignal analyses is the supply voltage. The desired largesignal transfer characteristic can be achieved by adding a voltage limiter to the output stage. the transfer function becomes (7.5) The magnitude and phase resulting from the SPICE frequency analysis are plotted in Figure 7. .37. The ideal opamp model presented above is a useful concept for instructional purposes and quick hand calculations. however. in Figure 7. Its use in SPICE simulations should be limited due to the potential numerical problems that can be caused by the approximations involved.5.4) The limits of the passband for this active filter are defined by the two poles: PI P2 = RiCi 107 rad/s (7. R i jw RfCf ~w ( + RfCf 1)( jw + Riq 1) (7.
(c) opamp symbol. Vid transfer characteristic. g. vee Vo Ro 1 Ve Vo + Vid + + Vid R.9 Magnitude and phase of Va of bandpass filter.10 Nonideal operational amplifier: (a) Va versus (b) opamp model.208 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o lD 0 100 200 300 400 "'C Dl c 25 50 75 100 ::T g ~ g' :a: ai ~ co 0CD m CD en 102 103 104 105 Frequency. Hz 106 107 108 Figure 7.d t Ree Ce Vd °dVd (a) Vee (b)  VEE r D2 Vid Vo VEE (c) Figure 7.v. .
OR. The corresponding SPICE sub circuit description using typical values is listed below .ENDS * 7.11.7 D1 8 4 DMOD D2 5 9 DMOD . . and the revised symbol is in Figure 7. Rill and Ro.2 Logic Gates and Digital Circuits Many circuits simulated with SPICE have both analog and digital functions.b. The ideal models ofthe NAND. NOR. A simple but nonideal opamp model that includes the above properties is presented in Figure 7. 59E2 * OUTPUT STAGE EGAIN 7 0 6 0 1E5 RO 7 3 100 VC 8 3 0. which corresponds to a value Ce = 1.IO. The pole is defined by the intermediate stage at 10 Hz. These ideal models of logic gates can be used to simulate circuits in SPICE3 and PSpice but not in SPICE2.IO. . In this case simplified versions of the logic blocks can be used. and XOR gates using voltagecontrolled switches and positive logic are shown in Figure 7.7 VE 3 9 0. Vee and VEE. 102 F and Re = 1 O. The simplest and computationally most efficient are the ideal models.59. Ideal logic gate models can be easily derived from the NMOS implementation (Hodges and Jackson 1983).c.SUBCKT OPAMP 1 2 3 4 5 TERMINALS: IN+ IN. AND. If the analog blocks are required to be characterized with very high accuracy. in reality the bandwidth of the opamp is finite and is defined by an internal compensation capacitor.OUT VCC VEE RIN 1 2 1MEG * GAIN STAGE GI 0 6 1 2 1 RCC 6 0 1 CC 6 0 1. the digital functions might not be critical to the performance of the circuit but might need to be included for verifying the correct operation of the overall circuit. which include the two power supplies.IDEAL MODELS 209 Two additional nonideality factors that should be added to the opamp model in order to avoid very high currents are input and output resistances.MODEL DMOD D RS=l . Ideal models oflogic gates can be implemented with switches. The MOS transistor in this implementation acts as a voltagecontrolled switch. An intermediate stage has been added to this model to include the singlepole rolloff of the frequency characteristic.3. Note that the simple nonideal opamp model has five terminals. The ideal opamp also assumes that the frequency bandwidth is infinite.
7. whereas that of the allNAND implementation is 146 s.4.12.14. compare the results and the run time with those obtained with the detailed model of Figure 7. the SPICE input of which is listed in Fig. In PSpice on an IBM PSI280 with a 386 processor at 16 MHz the run times 37. b. These models are presented in Sec.9 sand Vo NAND AND NOR OR XOR Figure 7.b) using the ideal gates shown in Figure 7.210 7 FUNCTIONAL AND HIERARCHICAL SIMULATION Computationally efficient models for logic gates accepted by SPICE2 can be implemented as functional models using controlled sources. EXAMPLE 7. Compute the response to signals a.13 and the corresponding SPICE3 input is given in Figure 7.5) are displayed with the input signals on the same graph in Figure 7. .5. 7. and Ci in Figure 7.3. using SPICE. The analysis time for the ideal circuit in SPICE3 on a SUN 4/110 workstation is 1. Solution The Boolean function. implemented Co.b (7. s. The computed waveforms s and Co for both the ideal and the detailed implementations (see listing in Figure 7.3 Derive the most efficient implementation of the Ibit adder (Figure 7. for convenient verification of correct operation.11.2 s (no hysteresis).3.b.6) The logic diagram of the adder is drawn in Figure 7.12.11 Ideal logic gates. is by the Ibit adder with carryin Ci and carryout s Co = a + b + Ci = (a + b)ci + a .
G.13 Logic diagram of the Ibit adder.12 Ibit adder simulation: input signals and full models. ns 150 Figure 7.IDEAL MODELS 211 a b s (ideal) Co (ideal) s (full) Co (full) 50 100 Time. . respectively. b. The difference between the operations of the two circuits can be traced to the instantaneous switching of the ideal version after each change in input. compared to the delayed response of the transistorlevel version: the ideal circuit lacks of charge a b o o Figure 7. Note that the waveforms obtained with the two representations are different. and Cj and output s and Co for ideal 617 s. than the detailed circuit. s and Co. the ideal model predicts more changes in the output signals.
ENDS AND * .14 212 .1BIT ADDER WITH SWITCHES * . 5 2N 200N SPICE3 description of IBit adder.ENDS OR * .ENDS ONEBIT 1 2 3 4 5 6 B CIN OUT COUT VCC * * MAIN * Xl 1 2 CIRCUIT ONEBIT 3 9 13 99 RINA 1 0 1K RINB 2 0 1K RCIN 3 0 1K RBITO 9 0 1K RCOUT 13 0 1K VCC 99 0 5 VINA 1 0 PULSE 0 VINB 2 0 PULSE 0 VCIN 3 0 PULSE 0 3 0 10N 10N 10N 50N 3 0 10N 10N 20N lOON 3 lOON 10N 10N lOON 200N * . 5 VOFF=2.SUBCKT XOR * TERMINALS RL 3 0 1K 1 2 3 4 A B OUT VCC Sl 4 3 1 2 SW S2 4 3 2 1 SW .TRAN .MODEL SW VSWITCH RON=l ROFF=lMEG VON=2. * .SUBCKT OR 1 2 3 4 * TERMINALS A B OUT RL 3 0 1K VCC Sl 3 4 1 0 SW S2 3 4 2 0 SW .ENDS XOR * .SUBCKT ONEBIT * TERMINALS: A Xl 1 2 7 6 XOR X2 1 2 8 6 AND X3 7 3 4 6 XOR X4 3 7 9 6 AND X5 8 9 5 6 OR .END Figure 7.SUBCKT AND * TERMINALS RL 3 0 1K 1 2 3 4 A B OUT VCC Sl 4 5 1 0 SW S2 5 3 2 0 SW .
such as controlled sources.be inappropriate for some analyses. These subcircuits are built with just a few SPICE primitives. respectively.:>vn . This sec. is supported in SPICE3.4 F~NCTIONAL MODELS Several ideal subcircuit definitions were introduced in the p~eyious 'section that perform the main function of the circuit blocks they model in a SPICE analysis. This section describes how the function of a circuit bl~ck c~mbe modeled using controlled sources that are nonlinear or of arbitrary functional form. and name can be an arbitrary long string. This app~oach was exemplified above for a full adder~mplemented with ideal gates rather than the allNAND TTL transistorlevel implementation used in Example 7. ideal circuit models can also lead to an analysis failure in SPICE. In a departure from the above circuit models.1. which covers all possible cases.4. On the other hand. as ~an any element name in SPICE3. 7. The variable expr is an arbitrary function of the node voltages and currents in the circllit_ All common ~l~m~ntm. and other components. The savings in simulation time are very important. functional models achieve the same operation as the blocks they represent with just a few controlled soUrces connected in a network having no resemblance to the original one. In the following subsections a few examples of functional models are provided that are developed based on the different capabilities of the controlled sources available in the versions of SPICE under consideration. Linear sources are treated in the same way as in SPICE2. ofthesesubcircuits is similar to that of the transistorlevel implementation. as pointed out by the shortcomings of the ideal opamp. 7. it is possibleto have one description of the toplevel circuit and use different levels of detail in the component building blocks or subcircuits. The circuit structure. or topology. The controlled source is connected between nodes node} and node2 and is either a voltage or a current source depending on whether the character at the left of the equal sign is V or I. ideal models can.v flm~tiom: ~~n h~ 1I~~cl in pynr' tr~n~rpntlpnt~l .1 Nonlinear (ArbitraryFunction) Controlled Sources in SPICE3 A single type of nonlinear controlled source. switches. the equivalent of a gain block. which are structural.tion has introduced the concept of ideal elements. With the hierarchical specification features of SPICE input language. Besides predicting incorrect behavior. The general format for nonlinear controlled sources is Bname node} node2 V/I=expr B in the first column identifies the controlled source as nonlinear.FUNCTIONAL MODELS 213 storage.
It is important to understand that the SPICE algorithms require nonlinear functions to be continuous and bound. is controlled by an input voltage. Eqs. tanh. sinh. can cause an arithmetic exception. 7. such as 1/ x. Vc: Wose(t) = Wo + Kvc(t) = Wo (1 + K'vc(t)) (7. Controlled sources described by arbitrary functions enable the user to define functional or behavioral models. acosh.4. asin. and atanh. trigonometric. nonlinear controlled sources equivalent to those in SPICE3 and identified as G or E sources depending on whether the output is current or voltage.8) ()ose = J: Wose dt = wot +K J: Vc dt = Wo I: (1 + K'vc)dt (7. in addition to polynomial sources. EXAMPLE 7.2. acos. ramps up from 0 V to 1 V in the first half of the time interval and then decreases back to 0 V in the second half of the interval. These sources are described in the "Analog Behavioral Modeling" section in the PSpice manual (Microsim Corporation 1991). oscillator (VCO) in SPICE3 using B Solution A VCO generates a signal whose frequency.7) where K is the VCO gain in rad. Wose. Rapidly growing functions. tan.214 7 FUNCTIONAL AND HIERARCHICAL SIMULATION log. and atan. for a VCO this function is vose where = Vose sin ()ose (7. respectively.15). such as exp(x) and tan(x). V1s1 and Wo is the signal frequency of the freerunning oscillator when the controlling voltage is zero. The function for the B source must express the instantaneous value at any time point. therefore.13 to 7.9) Assume that the controlling voltage. and sqrt. cosh. The following example describes how a voltagecontrolled oscillator can be modeled in SPICE3 using Btype controlled sources. in the frequency domain the source assumes a constant voltage or current value equal to the smallsignal value in the DC operating point (see Sec. PSpice supports. sin. and hyperbolie. ln. Vc is implemented as an independent PWL source whose value must be integrated to obtain . A sound approach is to check that the variables of the functions are in a safe range. 7. vc. can cause convergence problems.4 Define a functional model of a voltagecontrolled sources. The nonlinear function applies only to the time domain. asinh. cos. and discontinuous functions.
which varies linearly with time. Vase V (3). Under the assumption that fa = 10 kHz and K' = I VI.3. the SPICE3 input circuit is listed below: VCO FUNCTIONAL MODEL FOR SPICE3 * * CONTROL VOLTAGE VC 1 0 PWL 0 0 0. subtraction. rather than digital. and division (Epler 1987). Vc = V (1) . The SPICE3 Bsource expression does not allow explicit time dependence. Addition and multiplication can be achieved with the following polynomial.PLOT TRAN V(3) V(2) . The model introduced in this example for a VCO is known as afunctional. The waveforms of the controlling voltage.2 Analog Function Blocks The circuits presented in these sections implement the desired function with the polynomial controlled source (introduced in Chap.1 and 7. Note that the results of these operations are analog. 7.FUNCTIONAL MODELS 215 the second term of Eq.4.5 1 1 0 RIN 1 0 1 * * * * V(2) IS INTEGRAL IN EQ. or binary. 2) in SPICE2 and the arbitraryfunction controlled source in SPICE3 and PSpice. model. can be used. and the VCO output. are shown in Figure 7. The nonlinear controlled source can be used to implement a number of arithmetic functions.TRAN 0. VCVS: EADD 3 0 POLY (2) 1 0 2 0 0 1 1 EMULT 3 0 POLY (2) 1 0 2 0 0 0 0 0 1 . 7.9). a PWL voltage source. as was the case in Examples 7.9 BINT 0 2 I=l+V(l) CINT 2 0 1 BVCO 3 0 V=5*SIN(2*PI*10*V(2)) ROUT 3 0 1 * * .01 102M UIC .9. 7. multiplication.END Note that V ( 2) in the expression of BVCO equals the integral of the current through capacitor CINT and represents the time integral of (1 + K'vc) (see Eq. or behavioral.15. such as addition. 7.
A divider is slightly more complex and requires two poly sources.For details on the POLY coefficient specification see Sec. 4 If\ vase " II /I II f\ 2 > "C ai :E Ci E a 2 ve «  4 . . as shown in Figure 7.I 800 V 200 400 Time. V I V I I I V V V I .I.216 7 FUNCTIONAL AND HIERARCHICAL SIMULATION . . The SPICE specification ofthe two VCCSs needed is GV130101 GV2V3 0 3 POLY (2) 2 0 3 0 0 0 0 0 1 +0 CD (2) + v.16 Divider circuit.2.I V I V . V . V2. .. referenced to ground.15 Waveforms Vase and Vc for veo functional model.16. .2 and 3. 0 +0 v2 0 Figure 7. ms 600 Figure 7.I .10) (7.3. The functions implemented by the two elements are V3 V3 = = VI + V2 (7. 2. which is node O. and V3 are the voltages at nodes 1.11) VI V2 where VI.
3.g to (7. The derivative offis computed in DC biaspoint analysis in a way similar to the evaluation of smallsignal conductances of semiconductor devices (see Secs. V3." .J in sinaU~signalanalysis is a linear function given by . A controlled source with two arguments. The setup is shown in Figure 7. is performed only in a DC or timedomain largesignal analysis but not in a smallsignal AC analysis. .XI + D.X2 +'XID.' D.2). VDD. .13) Therefore.XI X2D. is the quotient VI/V2 because of the equality of the currents of the two.3. D.. The value of the function expressed by a nonlinear controlled source f (x + ax) when a small signal ax is added to the quiescent value of the controlling signal x is (7.5.=D.4. which would otherwise flag the two controlled current sources in series as an error. Another useful function that can be implemented with polynomial sources is a meterfor the instantaneous and cumulative power over the time interval of transient analysis.2. " I. the controlled source function tJ. and V4 is the cumulative .FUNCTIONAL MODELS 217 The resulting output voltage. such as multiplication or division. into a voltage with the correct sign and a VCVS to obtain the product iDD VDD. The voltage V3 represents the instantaneous power. Xl and X2.VCCSs imposed by the KCL: (7. "dx . df" .2.fs D.X2 (7.14) . is evaluated in AC analysis accordip. An important observation regarding the use of nonlinear controlled sources is that the desired function.17 and uses a CCCS to transform the current of the bias source. 3.fM = = D. which 'uses the differential of a nonlinear function in the DC operating point and not the function itself. The addition and multiplication functions implemented with polynomial controlled sources are evaluated according to the following equalitie~ in AC analysis: fs == Xl + X2.12) Note that the large output resistor is needed to satisfy the SPICE topology checker.15) fM = XIX2. The cause of this is the smallsignal nature of AC analysis. and 3. 3. . ..j.x .
by the current time. 7.18 is similar to that of a differential amplifier (Gray and Meyer 1993) and is expressed by Vo = Vee tanh V avvid ee (7. The output characteristic shown in Figure 7.0 :0.5 ° 0.0 ° 10 20 1.0 Figure 7. power from 0 to the current time: (7.18 Output of tanh x limiter functional block. A good example is the limiter circuit that was used in the previous section at the output of a nonideal opamp block. . The ease of defining functional models is greatly enhanced by the arbitrary controlled sources available in SPICE3 and PSpice.5 1. which can be measured by a PWL voltage source whose value increases proportionally with the analysis time.17 Powermeasuring circuit.218 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o lQ lQ 0 IF Figure 7.16) The average power at any time point can be obtained by dividing V4 as given in Eg.16.17) 20 10 > ".
and Rc is the collector resistance. . The behavior of arctan x is similar to that of tanh x. that is. for small values of the argument it can be approximated by the value of the argument. because the derivative of the arctangent is .21) where The functional limiter for SPICE2 is shown in Figure 7. and for large values of the argument it is limited to a constant value... for small values of the argument it is approximately equal to the argument. according to the series expansion: tanhx I x .20 and then integrating it to obtain Vo = 2Vcc 7r (f Jo 1 + u2 _U_'_dT _ ~) 2 (7. 7. The limiter built with the arbitrary controlled source defined by Eq. The functional description of a differential amplifier built with an emittercoupled pair (Gray and Meyer 1993) is as follows: Vo = exRchE tanh (  2~th V"d) (7.18) Its absolute value is limited at 1 for large values of the argument. A functional limiter can be built also for SPICE2. but it takes more components (Mateescu 1991). 7. (7.20) Therefore the limiter can be built by implementing the righthand side of Eq.19) where hE is the sum of the emitter currents.FUNCTIONAL MODELS 219 In general the function tanhx is ideally suited to implementing a limiter. which is equal for the two input transistors of a differential pair. ex is the CB gain factor.17 allows the output voltage Vo to follow the input voltage Vid amplified by av as long as avvid is smaller than the supply voltage and then limits Vo to the supply when avvid surpasses the supply voltage. The behavior of arctan x is identical to that of tanh x.arctanu = dt d u' 1 + u2 (7.19.x 3 3 2 + x 5 = 15 . and it can be represented by conventional polynomial sources.. assuming values between 0 and 7r when x varies from 00 to 00.
Another important point is to initialize differentiators and integra .21. 5. The differentiator is built with an ideal opamp. 7. and 9 are given in the following equations. V2 = U = '7T avVid 2 Vee V9 = u' u' V6 = I t o 1+ u u' dT 2 V7  _ 2Vee 7T (It 0  u' 1 + u2 dT _  7T) 2 Each section in Figure 7. differentiation.19 performs a specific function. 6. and the limiting output function are plotted in Figure 7. toward the realization of Eq. The voltages at nodes 2.19 Circuit diagram of arctan x limiter. such as division.220 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o CD Figure 7. or integration. its arguments.21. The voltages representing the values ofthe integral. Each section is also identified by comments in the SPICE2 input listed in Figure 7. Functional models must be used with care to avoid arithmetic exceptions such as division by zero. 7.20.
Figure 7.54 R7 7 0 1 * * * LEVELSHIFT AND SCALE * .21 GV 0 2 1 0 lE5 G2 2 0 2 0 9. The capacitor of the differentiator.FUNCTIONAL MODELS 221 ARCTAN (X) LIMITER VIN 1 0 PWL 0 1M 2 1M RIN 1 0 lMEG * * * * COMPUTE THE ARGUMENT U.PRINT TRAN V(5) V(6) V(7) . EQ.48 lE12 004 lE3 9 1 lE12 A * * COMPUTE U'/(I+U 2) GVP05901 G5 5 0 POLY (2) 2 0 5 0 0 0 1 0 0 0 0 1 R5 5 0 lE12 * * G6 0 6 5 0 1 R6 6 0 lE12 C6 6 0 1 * * INTEGRATION CKT. . used in the arctan x function is initialized with the appropriate voltage at t = 0 in order to prevent a convergence failure due to a large voltage at the input of the ideal opamp.54 R2 2 0 lE12 E3 3 C3 3 R3 4 EDIF RDIF RO 9 * * * DIFFERENTIATION CKT TO COMPUTE U' 0 4 0 9 4 0 201 1 1('=10. 7. COMPUTES INTEGRAL OF V (5) E7 7 0 POLY (1) 6 0 15 9.TRAN . C3.01 2 0 UIC .END SPICE deck for arctanx limiter.20 tors in the expected initial states in order to avoid convergence failures.
2 by the following transfer function: Ls LCs2 + Ls/R + 1 (7.21 Simulation results of SPICE2limiter. Some proprietary SPICE simulators. Both a frequency. support a frequencydomain transfer function. With an arbitrary frequencydomain transfer function block one could define the parallel RLC circuit of Example 6. such as PSpice and SpicePLUS (Valid Logic Systems 1991).22) The PSpice input specification for this block is . A functional block that proves very useful in many simulations is a frequencydomain transfer function. such as the adder.. and the differentiator.PARAM L=lMH C=lNF R=10K EFILTR 1 0 LAPLACE {I(VIN)}={L*s/(L*C*s*s+L/R*s+l)} This block can replace the RLC lumpedelement representation in Example 6.5 1.2. ."" 0 5 10 15 1.0 0.0 Figure 7.d= 0 V(1) .5 V.222 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 5 > . the integrator.mV 0. With this capability a variety of filters can be described by the locations of poles and zeros. these can be saved in a library and then used in any circuit where such blocks are needed. So far we have defined a number of functional blocks. the multiplier.and a timedomain analysis can be performed with this block.
The operation of this model is based on the correspondence of the logical AND operation to multiplication.2 so that the output voltage VOUT is 5 V when both inputs are at a logical 1.4. logic levels 0 and 1 are expressed in voltages corresponding to positive logic. In order to model the OR function.22 Universal gate functional model. 7. The elements presented below implement the analog operation of digital circuits. 7. The structure of a universal gate is shown in Figure 7.22.Jj vc (7.3 Digital Function Blocks In Sec. such as switches. .23) 3. on ideal building blocks. the product must be scaled by 0.12 kQ OUT A B + E 1GQ 1GQ 100Q Figure 7. that is.12 kQ 3. which can be implemented as above: a+b=ii. The AND function is implemented by the VCVS EAND. The supply and input resistors are chosen to model the behavior of a TTL gate.2 Assuming that VA and VB take values between 0 and 5 V.3.FUNCTIONAL MODELS 223 Exercise Show that the timedomain response of the above block to a current step function calculated by PSpice is identical to the response of the lumped RLC circuit in Figure 6.2. which contains only the term VA VB: EAND OUT 0 POLY (2) A 0 BOO 0 0 0 0. All digital gates can be described at a functional level with polynomial sources (Sitkowski 1990). DeMorgan's theorem (Mano 1976) is applied to transform the OR function into an AND function. digital gates were implemented with simple circuits that are structurally similar to actual implementations but use ideal elements.
hydraulic. the inversion of the output function.2 The order of the coefficients follows the rule introduced in Sec. the OR function becomes EaR 0 OUT POLY(2) A VC B VC 5 0 0 0 0. are described by complex nonlinear differential equations. and the NOR function needs only the inputs inverted. is achieved by inverting the polarity of the controlled source and subtracting 5 V from the result.2(Vee .24) a E9 b = iib + ab These functions need four variables. that is. 7. . ii.224 7 FUNCTIONAL AND HIERARCHICAL SIMULATION The inversion of the input signals is achieved by referencing the two input signals. the NAND function. and electromechanical systems.VAWB + O.2 0 0 0 0 0 0 0.2 0 0 0 0 0 0 0. respectively. 7.4 Equation Solution The operation of electrical systems as well as nonelectric systems. a. b.VBWA The two terms require the definition of coefficients P6 and P13 for both XOR and XNOR. Note that for SPICE2 the node names used above must be replaced by numbers: i 7. with respect to the AND function.4. In order to simulate these devices with SPICE it is necessary to create a model or. and b. The XNOR function is implemented by switching the polarity of the VCVS. ab. According to Eq. to cast the component equation in a form that the program can understand and solve. VA an9 VB. and therefore a fourdimensional polynomial is used.2 A 0 VC B 5 0 0 0 0 0 0. input a is VA and input ii is Vee . EXOR OUT 0 POLY(4) VC ABO EXNOR 0 OUT POLY (4) VC ABO A 0 VC BOO 0 0 0 0 0. and the product of variables 3 and 4. leading to the following expression of the XOR function VOUT = O.2(Vee . equivalently.2 A VC B VC 0 0 0 0 0. Each variable and its inverse introduce two controlling voltages. The functional models defined above can be combined in creative ways to solve most complex equations describing not only electrical but also other physical systems. such as mechanical. to Vee rather than to ground. according to Eq.2 The XOR and XNOR functions are implemented according to the definition (7. The only terms of the polynomial used in both functions are the product of variables I and 2.VA' The SPICE definitions of the VCVS for the XOR and XNOR functions are.23: ENAND 0 OUT POLY(2) ENNOR OUT 0 POLY(2) A 0 B 0 5 0 0 0 0.3.2. iib.23. 2.2 The NAND function needs only to have the output inverted.
and d. The lamp is represented by a nonlinear controlled current source.23. Note that for PSpice the definitions of G and of the arbitrary controlled sources BRHS and BLAMP need to be changed to the following syntax: ERHS 6 0 VALUE={2.2)S. such as multipliers and dividers.= ~ aI2 + bIV + c V2 + d (I V )3 + e (I.7*(I(VA)!V(2))} GLAMP 4 5 VALUE={ V(Gl) W(IN) } . The circuit is shown in Figure 7. c.FUNCTIONAL MODELS 225 EXAMPLE 7. BRHS.!)' V where G(V. After designing the complete model defined by Eq. A SPICE2 model can be developed using functional blocks. V..25.422*PWR(I(VA). b. and the voltage. I) is the voltage at node G 1. The relationship between the current. f = 271. equal zero.7 The rest of parameters. equal to the integral of the righthand side of Eq.25. Create a model for both an arbitrary controlled source as well as a polynomial controlled source implementation.25 and corresponds to the operation known from text books.25.186E4*PWR((I(VA)/V(2)) + +271. it can be implemented as a nonlinear controlled voltage source. 7. The result is integrated to obtain V(G 1).25) where G is the conductance of the lamp. which implement the terms of the righthand side of Eq.)2 + f I V V (7. of the lamp is defined by the following equation: dG . The corresponding SPICE3 description is shown in Figure 7.24. 7. Solution The main part of the model is the defining equation of the conductance G.25. which sums the terms on the righthand side of Eq. . Eq. simulate the turnon characteristic for a lamp with the following parameters: a = 2. I.25. which are then added. 7.2) The IV characteristic of the lamp obtained from SPICE3 is plotted in Figure 7. 7. 7. BLAMP. the current of which is I = GO'.5 With the functional blocks defined above develop a circuit that can be used in SPICE to model the turnon IV characteristic of a fluorescent discharge lamp.422.
.7*(I(VA)!V(2)) R8 7 4 978M R7 5 4 10MEG R6 0 IN 1K BLAMP 4 5 I=V(G1)*V(IN) EV5IN0451 L3 0 3.1 100 ) C10 4 5 lOOP BRHS 6 0 V=2.226 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 0 vB Ra CD J 1 @ + BLAMP 1= VGl VIN R7 10MQ ClO 100 pF VA + EVS R6 +  0 @)  BRHS Figure 7.24 SPICE3 input for the fluorescent lamp functional model.2E02 0 ) VB 7 8 PWL ( 0 0 0.IC V(G1)=1 V(IN)=201 .ENDS INTEG VI 5 3 0.1 0 .01E+02 2E+02 6E+01 1.0 .5M UIC .186E04*((I(VA)!V(2))A2)+271.SUBCKT INTEG 1 2 RIN1 1 4 2 RIN2 1 4 2 G1 2 0 4 0 1 R1 2 0 1E12 C1 2 0 1 .END Figure 7.55.23 Fluorescent lamp functional model.TRAN 0. FLUORESCENT LAMP VA 8 0 DC 201 SIN ( 2.005 .422*(I(VA)A2)5. 7M XF2 6 G1 INT1M .
The components used to model specific characteristics are identified. opamps have been widely used in such circuits as active filters. Macromodels combine functional elements with accurate nonlinear models for some elements. and their evaluation from the data sheet is highlighted. The approaches have varied from structural simplifications of the circuit using ideal elements to pure functional blocks. and the development of macromodels that implement all or part of the databook characteristics of a given opamp is crucial. Since the introduction in IC realization in the late 1960s. such as transistors and diodes.5 MACROMODELS A number of concepts have been introduced so far in this chapter on higherlevel modeling. A SPICE simulation of a circuit with morethan a couple of opamps can be very expensive.MACROMODELS 227 V1N. 7. and control systems. which synthesize the input/output relationship of the circuit. in order to obtain the behavior of the original circuit from a simplified circuit that can be simulated several times faster. This concept was first applied to opamps (Boyle. called macromodeling. and Solomon 1974). which contain ten to a hundred transistors in a detailed representation. Cohn. . phaselocked loops. The next section describes a common opamp macromodel. This section introduces the most general and powerful modeling concept.V Figure 7. Pederson.25 1V characteristic of fluorescent lamp.
and accurate largesignal characteristics. equal to Iez.5. and frequency rolloff. and four diodes are used in the output stage for limiting the voltage excursion and the shortcircuit current.228 7. 7.1. Is! and IS2. The macromodel ofthe JLA 741 opamp is divided into three distinct stages. The gain factor. (1974).27) f3F1 and f3F2 are derived from Eqs. and slew rate. the input offset voltage. voltage swing. is due to an inequality in the two saturation currents. and output stages.I B IBI + IBos 2' (7. The gain stage is built with linear elements. These characteristics are presented in Table 7. The macromodel derivation for the JLA741 is outlined below according to Boyle et al.1 7 FUNCTIONAL AND HIERARCHICAL SIMULATION The Opamp MacroModel The macromodel developed by Boyle et al. the three stages are modeled separately to implement all the datasheet characteristics. The element values and model parameters of Q! and Qz must be derived from the opamp data sheet.1. . At the conclusion of this section the switching and frequencydomain characteristics of the macromodel compared with those of the detailed circuit are shown in Figures 7. of the two transistors. shortcircuit current limiting. and compensation capacitor Cz: S. The schematic ofthe macromodel is shown in Figure 7. Table 7. such as offset. is shown in Figure 7.3.1. (7.26) IB of Q! and Qz is taken from the data sheet. ICl. is derived from the DC offset and the slew rate.31 and 7. gain. and an imbalance is introduced to account for the offset input current. model parameter BF. f3F. Unlike the ideal opamp described in Sec. The number of transistors in the macromodel has been reduced to only two. 7. The detailed circuit. is established by the positivegoing slew rate.33. according to the following equation: (7. IBos: . input and output characteristics. which are necessary to model the correct input characteristics.26.27. (1974) is described in this section. Vos.28) which leads to the values of the model parameter IS of Q! and Qz. the macromodel attempts to provide an accurate representation of differential and commonmode gain versus frequency characteristics. containing 26 BJTs.27. slew rate. The input stage must be designed to reproduce characteristics such as DC offset. the input.26 and 7. The approach described below can be applied to model a broad class of opamps.
26 Detailed JLA741 circuit.0 ~ ~ Biasing reference network Input stage Intermediate stage Output stage Figure 7.+Vcc @ @ B 1 A @ Qg 39kn<Rs Cf @ R4 R1 R3 @ VEE 1. .
=.A741 macromodel.= r y~) (V \. .27 p.W Q ~ o (Vee! Ve = Rc2 0 Rp Vb D3 @ C2 . y)\.=. GbVb I L1EE r D1 D2 D4 H@ Gevs @ c. 1 (VEE) y~) \. GemVe I I GaVa 1 I 0(+) \{2. Inputstage Interstage Outputstage Figure 7..! 0 (~ 11 1 1'1 f =. VC @ Ral Vs CD R2 v.
30) Rei and Rc2 can be derived from the equality 1 Rei = Rc2 = 2 7TJOdB r.3 106 566 76.67 0.2 14.(V) The emitter resistor. The frequency response is established by resistors Rei and Rc2 in the input stage and components of the gain stage.7 S.7 Data Sheet 30 0.103 16. set by the compensation capacitor C2 and by Ga = I/ReI.8 106 566 76. of 200 V: (7.9 0.283 4.899 0.9 25.9 14.31) 2 .265 4.5 25.62 80 20 1 2.72 256 0.16.105 103 20 90 75 MacroModel 30 0. is given by (7.2 12.MACROMODELS 231 Table 7.219.17.105 1.718 255 <1 0.1 Parameter Cz (pF) fLA741 Performance Characteristics DeviceLevel Model 30 0. RE is chosen so that it matches the output resistance of a transistor with an Early voltage.103 16.8 25 25 14 13.7 0.217. C (7.105 1.8 26.29) where hE is the sum of the collector and base currents of QI and Q2. f3dB.2 26. The frequency of the dominant pole. VAF.2 12. (V/fLs) Si (V/fLS) IB (nA) IBos (nA) Vos (mV) avd avd (l kHz) !1c/J(degrees) CMRR(dB) Rout (n) Roose (n) Is~ (rnA) Is~ (rnA) V+(V) V.
Gem = (7. rolloff of 6dB/octave by fOdB can be approximated for a (7.34) With the phase shift !i. DM.ThevalueofGemisbasedonthecommonmode rejection ratio.32) There are two more capacitors in the input stage. CM.<jJ given in the data sheet. .36) (7. CMRR = ayd/ aye.33) by introducing a second pole at (7.38) Transconductance Gb defines the correct openloop DM gain. and is equal to 1 (CMRR)Rcl ayd.39) where Ro2 is approximately equal to the DC output resistance given in the data sheet. CE and C1• The first is included to model a smaller negativegoing slew rate Sii according to the following equality: \ C1 models the excess phase at fOdB (7. gains. and is given by (7. aYd and aye.232 7 FUNCTIONAL AND HIERARCHICAL SIMULATION where fOdB is the OdB frequency from the data sheet. This is achieved by a correct sizing of the transconductances Gem and Gb' The two gains. C 1 results as (7.37) aye = GemR2 whereR2 = lOOk!1andGa = l/Rcl.35) The gain stage is designed to provide the correct differential mode. are defined by the following equalities: aYd =  R2 Rcl (7. and common mode.
26 and the macromodel in Figure 7.1016 8. Table 7. EXAMPLE 7.1986 5034.363 229.233 The design of the output stage of the macromodel requires the dimensioning of diodes D1 and D2 and resistor Ra1 for current limiting and diodes D3 and D4 and bias sources Vc and VE for proper output voltage limiting. reproduced from Boyle et a1. and the SPICE input is shown in Figure 7.3 1. The offset voltages Vas corresponding to each model are applied as DC biases at the inputs of the two opamps.29. and for the macromodel. listed in Figure 7. called subcircuit UA 741. are used in order to compare the output voltages. The complete list of the parameters of the macromodel is provided in Table 7.2 Parameter lSI (A) p.9 7.5 V to 5 V is applied to the positive input ports of both opamps. V3 and V6. Both subcircuits have five external terminals. Note that two unconnected voltage followers.p.512 4352 2391.6042 3.A741.A741 MacroModel Value Parameters Parameter Rp(kO) Ga({. Xl is represented by the macromodel. the output. The circuit for the slewrate performance is shown in Figure 7.28. write the SPICE netlist for the detailed p.5 4. Solution First.LA) Rei (0) Rei (0) RE (MO) (pF) CI (pF) Rz (KO) Cz (pF) CE 8.774 1.27 with the component values from Table 7.7962 27.28. (1974). for the two opamp models.1516 37. A 20.0978 76.5288 100 30 Gb(mho) Rol(O) Roz(O) Ism (A) Ism (A) Rc(mO) Gc (mho) Vc (V) VE (V) .MACROMODELS . UA 7 41MAC.2. UA 741.1016 52.30. and X2 is described by the complete circuit.6726 52. The two subcircuit definitions are listed in Figure 7. for the detailed derivation of this model see that paper.8218 .31 and can be seen to match very well.2 3.A741 circuit shown in Figure 7.1O3Z 8. and the two supplies.Lmho) Gem(nmho) Value 15.2696 7.1042 b(A) (31 (3z leE ({.0925. called UA 7 41MAC. Xl and X2. the two inputs.6 Compare the voltagefollower slewrate performance and the openloop f~equency response to fOdB between the complete p.s pulse from . The two waveforms of VOUT are plotted in Figure 7.2.8 489. 1016 0.
SUBCKT UA741 1 2 24 27 26 NODES: 1m.65P CJC=0.6 C2=1653 IK=1.15N TR=405N + CJE=0.33 PC=0.IN.45 MC=0. .36P IS=1.5 RB=670 RC=300 CCS=1.234 7 FUNCTIONAL AND HIERARCHICAL SIMULATION ************************************* * * DETAILED CIRCUIT FROM BOYLE PAPER * ************************************* .OUT VCC VEE R1 10 26 1K R2 9 26 50K R3 11 26 1K R4 12 26 3K R5 15 17 39K R6 23 24 50 R7 24 25 25 R8 18 26 100 R9 14 26 50K R10 21 20 40K R11 13 26 50K CaMP 22 8 30PF Q1 3 1 4 BNP1 Q2 3 2 5 BNP1 Q3 7 6 4 BPN1 Q4 8 6 5 BPN1 Q5 7 9 10 BNP1 Q6 8 9 11 BNP1 Q7 27 7 9 BNP1 Q8 3 3 27 BPN1 Q9 6 3 27 BPN1 Q10 6 15 12 BNP1 Q11 15 15 26 BNP1 Q12 17 17 27 BPN1 Q13A 28 17 27 BPN3 Q13B 22 17 27 BPN4 Q14 27 28 23 BNP2 Q15 28 23 24 BNP1 Q16 27 8 14 BNP1 Q17 22 14 18 BNP1 Q18 28 21 20 BNP1 Q19 28 28 21 BNP1 Q20 26 20 25 BPN2 Q21 13 25 24 BPN1 Q22 8 13 26 BNP1 Q23A 26 22 20 BPN5 Q23B 26 22 8 BPN6 Q24 13 13 26 BNP1 * .611M NE=2 PE=0.26E15 VA=178.417P TF=1.6 + ME=0.MODEL BNP1 NPN BF=209 BR=2.28 Detailed description and macromodel of the JLA741 opamp.33 Figure 7.
33 .40P lS=0.55P lS=0.MODEL BPN4 PNP BF=14.80P lS=17.455P TF=0.2 R01 13 6 76.6E15 VA=57.25E15 VA=83.45 + ME=0.1516N GA 12 0 8 9 229.25 PC=0.79E15 VA=79.15E15 VA=55.259P TF=27.90P lS=2.33 PC=0.395E15 VA=267 C2=1543 lK=10M NE=2 PE=0.4 lK=590.55U NE=2 PE=0. 4N TR=55N + CJE=0.76N TR=243N CJE=2.49K lK=80.94 C2=478.45 C2=1219 lK=80.7U NE=2 PE=0.55U NE=2 PE=0.MACROMODELS 235 .33 .6 MC=0.4N TR=2540N + CJE=4. 8 BR=1.MODEL BPN5 PNP BF=80 BR=1.6 + ME=0.126P TF=27.25 .OUT VCC VEE Q1 8 2 10 QMODl Q2 9 3 11 QMOD2 RC1 7 8 4352 RC2 7 9 4352 RE1 1 10 2391.63E17 VA=167.774U R2 12 0 lOOK C2 12 13 30P GB 13 0 12 0 37.512U C1 8 9 4.25 PC=0.8P CJC=1.5 RB=1100 RC=170 TF=26.10P CJC=2.45 + ME=0.8U NE=2 PE=0.363K GCM 0 12 1 0 1.25E15 VA=83. 9 RE 1 0 7.MODEL BPN2 PNP BF=117 BR=4.MODEL BPN1 PNP BF=75 BR=3.6 MC=0.0 RB=650 RC=100 TF=26.33 .8 BR=1.4N TR=2540N + CJE=0.37K lK=171.45 MC=0.SUBCKT UA741MAC 3 2 6 7 4 NODES: IN+ IN.55 C2=84.6 + ME=0.33 PC=0.ENDS * * UA741 ********************* UA741 MACROMODEL * ********************* .05P CJC=2.6 MC=0.8 RB=500 RC=150 CCS=2.33 PC=0. 4 RB=100 RC=80 CCS=2 .28 (continued) .3P lS=2.25 + + * .40P lS=0. 9 RE2 1 11 2391.10P CJC=0.25 PC=0.27MEG CE 1 07.45 MC=0.MODEL BPN6 PNP BF=19 BR=1.45 + ME=0.5N TR=9550N + CJE=0.0978 R02 13 0 489.MODEL BPN3 PNP BF=13.11 C2=1764 lK=270U NE=2 PE=0.33 PC=0.45 MC=0.45 MC=0.1 RB=185 RC=15 CCS=3.5N TR=2120N + CJE=1.10P CJC=0.MODEL BNP2 NPN BF=400 BR=6.05P lS=3.126P TF=27.1 C2=57.55 C2=84.4N TR=220N + CJE=0.33 .5P lEE 1 4 27.25 .90P CJC=2.37K lK=5M NE=2 PE=0.5 RB=160 RC=120 CCS=2.5288P RP 7 4 15.8 RB=80 RC=156 TF=27.6 ME=0.10P CJC=1.6 + ME=0.8 Dl 13 14 DMODl Figure 7.
ENDS (continued) Figure 7. UA741 SLEW RATE * MACROMODEL Xl 1 3 3 4 5 UA741MAC * FULL MODEL X2 2 6 6 4 5 UA741 VIN1 10 0 DC . Figure 7.MODEL DMOD1 D IS=3.1042 * .OPTIONS ACCT .1986M D3 6 15 DMOD3 D4 16 6 DMOD3 VC 7 15 1.TRAN .28 Figure 7.6042 VE 16 4 3.2765M PULSE 5 SOlON VIN2 11 0 DC .7962 .6726 .MODEL QMOD1 NPN IS=8E16 BF=52.8218E32 .MODEL QMOD2 NPN IS=8.25U SOU .29 Voltage follower configuration for slewrate comparison.3 RC 14 0 0.30 .0925E16 BF=52.MODEL DMOD3 D IS=8E16 .2834M PULSE 5 SOlON RIN1 10 1 100 RIN2 11 2 100 VCC 4 0 15 VEE 5 0 15 * 10N 20U 100U AC 1 10N 20U 100U AC 1 * .END SPICE input for voltagefollower configuration for slewrate comparison.236 7 FUNCTIONAL AND HIERARCHICAL SIMULATION D2 14 13 DMODl *EC 0 14 6 0 1 GC 0 14 6 0 5034.
Figure 7. so that the two opamps. are in an openloop configuration. lIS 30 40 Figure 7.0 s 0 2 4 10 20 Time. as shown in Figure 7.33. The two models track UA741 FREQUENCY RESPONSE MACROMODEL Xl 1 0 3 4 5 UA741MAC * FULL MODEL X2 2 0 6 4 5 UA741 VIN1 1 0 DC .. END VIN1 .MACROMODELS 237 4 2 > . and the frequency range is set from below the dominant pole defined by the compensation capacitor to six orders of magnitude above that value.2765M AC 1 VIN2 2 0 DC . The SPICE input for the frequency response is modified.31 Slewrate results for opamp models.32 . Xl and X2.32.AC DEC 10 . The magnitudes ofthe two output signals are plotted in Figure 7. the pulse is replaced by an AC source.TF V(6) VIN2 .2834M AC 1 VCC 4 0 15 VEE 5 0 15 * * * * * V(3) .TF .1 1G SPICE input for openloop frequency response comparison.
after which secondary poles and zeros come into play.17 sand 21 iterations for the complete . Separate runs for individual opamps show that the complete circuit has 79 nodes and 38 components. Hz Figure 7. versus 16 nodes and 26 elements for the macromodel. a performance gain of 11. The gains in analysis time become significant for the transient analysis. The performance gain is achieved in the analysis of the macromodel circuit partly because fewer time points and iterations are required by this solution. each other very well up to 1 MHz. The simpler circuit takes only half the number of iterations used by the full opamp circuit. see Chap. . because in SPICE the transistor is the most timeconsuming component to evaluate. an IBM PS/2 Model 80 equipped with a 16 MHz 386 processor requires 209 s for the complete circuit versus 14 s for the macromodel. offers detailed information on the two circuits. where the complete circuit requires 56 s versus only 5 s for the macromodel.1). 9 for more details.uA741 circuit and 0. This ratio is very important. ACCT (see Sec. versus only 2 for the macromodel.238 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 100 50 OJ "0 "0 :J <Ii '2 Ol ::2: t1l 0 50 100 Frequency. The same analysis performed by PSpice 01). The above characterization is useful for identifying the range of the macromodel's validity for different applications. The accounting information option of SPICE. the complete circuit has 26 BITs. These results were obtained from SPICE2 running on a SUN 4/110 workstation.25 sand 32 iterations for the macromodel. The reductions in circuit complexity and simulation time are important advantages for macromodels. In addition.5. This option also shows that the run time for the openloop DC operating point is 1. 9.33 Openloop frequency response comparison.
7. a nearly ideal model of an opamp can run up to two orders of magnitude faster. For the opamp macromodel varying degrees of accuracy can be implemented. The first step in defining circuit representational levels is to identify a hierarchy when describing a more complex circuit. > circuit elements • ENDS Xname xnodel <xnode2 .. With the reduction in complexity. > SUBname These statements can be nested to create several levels in a hierarchical circuit description. the savings in run time are of major significance. Ideal opamps can be used in active filters. which are applicable as well to nonelectrical physical systems. and ideal logic gates save analysis time in mixed analog/digital circuits.. The subcircuit definition. . A number of useful functional blocks can be defined using the polynomial controlled sources available in all SPICE simulators... Macromodels can achieve the accuracy of a detailed circuit with important savings in analysis time by combining structural elements. SpicePLUSlProfile. Functional models implement complex analytical currentvoltage expressions with one or more nonlinear controlled sources. such as transistors and capacitors.6 to the complex macromodel of Figure 7. This approach to modeling and simulation is known as highlevel. as exemplified by several digital building blocks.. It is up to the user to decide which behavior of a circuit block is important and needs to be modeled for the correct operation of an entire circuit. from the ideal model in Figure 7. and phaselocked loops with just a few components. Highlevel circuit representations have been presented in three categories depending on the level of accuracy.1991) make it possible to model circuit blocks such as limiters. a global statement. The arbitrary controlled source introduced in SPICE3 and the equivalent or more powerful capabilities in PSpice. voltagecontrolled oscillators. Whereas the detailed macromodel can save up to an order of magnitude in run time. Ideal models describe the single most relevant function of a device and can be used for computational efficiency in circuits where the ideal blocks are not critical for the circuit performance. and the subcircuit instance are defined by the following syntax: • SUBCKT SUBname nodel <node2 . Devices described by complex equations.27.SUMMARY 239 An important conclusion to the modeling practices described in this chapter is that SPICE can accommodate different levels of accuracy in the representations of circuits. or behavioral. 1991) and Saber (Analogy Inc. The SPICE language provides constructs for identifying subcircuits and instantiating them in the circuit description. can also be simulated using arbitrary controlled sources. HSPICE (MetaSoftware Inc. which need not be electrical.6 SUMMARY This chapter has introduced several concepts pertaining to modeling and simulating electric circuits and systems. in contrast to the structural representation common to circuit schematics.
and lOA. New York: John Wiley & Sons. ERL Memo UCBIERL M82175 (October). 1992. Microelectronic Circuits. Personal communication. Solomon. K. Berkeley (August). 1990. Mano. as well as in Secs. Epler. O. Vladimirescu. Campbell. Sitkowski. Berkeley. Jackson. R. Circuit Analysis Users Guide. Computer System Architecture. R. and Schwartz. Valid Logic Systems. Newton. M.. IEEE Circuits and Devices Magazine 6 (September). PSpice. R. SPICE2 application notes for dependent sources. Zhang.2. 2. 1987. 3d ed.. of California. 1987. and K. Sedra. Analysis and Design of Digital Integrated Circuits. and H. Univ. 1993. IEEE Circuits and Devices Magazine 3 (September). San Jose. Smith.240 7 FUNCTIONAL AND HIERARCHICAL SIMULATION with functional blocks implemented with controlled sources. 1982. Oldham.Vincentelli. 1974. D. of California. B. CA: Author. Vladimirescu. 1989. R. HSPICE Users Guide. B. C. 10. New York: McGrawHill. A cautionary note at the conclusion of this chapter regarding the accuracy of the results using highlevel representations: the analysis is only as accurate as the models used! Erroneous operation as well as analysis difficulties can result from using idealized models. REFERENCES Boyle. Meyer. M. M. 1991. SPICE version 2G User's Guide. 1981. A. Saunders. O. and 1. Version 5. Irvine. A. as shown in one ofthe examples. MetaSoftware Inc. Welldesigned macromodels can be simulated up to an order of magnitude faster than the detailed model with little if any loss in accuracy. Paul. L. OR: Author.. Analog Workbench Reference. S. Philadelphia: W. Hodges. Englewood Cliffs. New York: John Wiley & Sons. A. M. 10. G. Simulation and modelingThe macromodeling of logic functions for the SPICE simulator. of Electrical Engineering and Computer Science.0. Univ. Introduction to Electric Circuits. Introduction to Electronics. D. A. P. New York: McGrawHill. Macromodeling of integrated circuit operational amplifiers. 1990.. 1983. Both analog and digital circuit examples have been presented in this chapter to highlight the diverse approaches to highlevel modeling. G.2.. Analogy Inc. D. Beaverton. CA: Author. Saber Users Guide. C. Dept. G. Gray. G. Mateescu.0. IEEE Journal of SolidState Circuits (December). 1991. Vol. B. NJ: Prentice Hall. CA: Author. Pederson. A. Cohn. R. Analysis of Linear Circuits. Microsim Corporation. 1989. Analysis and Design of Analog Integrated Circuits. and R.3. E. and A. Release 3. LSI circuit simulation on Vector computers. Pederson. A. Sangiovanni. 1976. C. . 1991. Dorf.. New York: McGrawHill. 1990. W.
2. 8. 241 . The signal amplitude is often larger than the limit for small signals. 5 the distortion measures were derived for a nearly linear frequencyindependent circuit.4. The main features of the smallsignal distortion analysis were presented in Sec. The distortion analysis presented in Chap. A more rigorous analysis of distortion components for a singletransistor amplifier and a mixer circuit is carried out in this chapter. 8. 5. which is a powerful tool for designing electronic circuits and ICs. 8. it is important to understand how to use largesignal timedomain analysis to derive the same distortion measures computed by the smallsignal analysis. 5. in Sec. SPICE2 provides more distortion information about a circuit than shown in Chap.3 describes the application of Fourier analysis for verifying the results of the onetransistor amplifier and for deriving the intermodulation component for a mixer. In this section the effect of frequencydependent circuit elements is considered in the derivation of the distortion measures.2 SMALLSIGNAL DISTORTION ANALYSIS In Chap. 5 was limited to frequencyindependent circuits. Emphasis is placed on the smallsignal distortion analysis in SPICE2. Therefore. The total distortion measures are broken down in the SPICE2 output into contributions for each nonlinearity of each diode or BJT in the circuit as exemplified in Sec.2.Eight DISTORTION ANALYSIS 8.1 DISTORTION IN SEMICONDUCTOR CIRCUITS This chapter describes in detail the evaluation of distortion in electronic circuits with SPICE.2. Sec. 8.
Soa.1 HighFrequency Distortion In the absence of frequencydependent elements.1 two frequencydependent linear circuit blocks. respectively. The approach consists of expressing the transfer function of a circuit containing both small nonlinearities and frequencydependent elements (Meyer 1979. Sia: (8. a power series is used to express the highorder terms of the signal at the output of a nonlinear circuit. So. The higherorder terms in the output signal.242 8 DISTORTION ANALYSIS The SPICE2 capability of reporting individual distortion sources is explained and the additional feature of the AC analysis that provides a frequency sweep of the distortion coefficients is exemplified. are added to the nonlinear gain block A. . is a power series of the input to A. 0.4) F(jOJ) J( jOJ) Figure 8.1 Nonlinear gain block with input and output filters. of the nonlinear gain block. The output. A more general series expansion of a signal is derived below for computing the distortion terms. Si. are obtained by taking into account all three transfer functions. Pederson and Mayaram 1990). The two linear filters have transfer functions F(j w) and J(jw).2. A new operator is introduced. both filters. 8. In Figure 8. Si through F(jw) to get = SI cosw1t + S2cosw2t (8.2) . to simplify the above expression of Sia to Sia = F(jW)oSi (8. where IF(j w)1 is the magnitude and cPw is the phase of the transfer function.1) Sia is the result of passing the input signal. A.
. The signal at the output of the nonlinear gain block is a power series of the input signal. and We. The above power series expansion of the output signal is also known as a Volterra series (Narayanan 1967). jWb) + a3F(jWa)F(jWb)F(jwe)J(jwa. Wa. 8. limited to three terms and up to three signal frequencies.ad + COS(2a2 + a])] + cos(2a] . Wb. is obtained by including the contribution of the second frequencydependent block. 0 Sf jWb. jwe) 0 Sf (8.(2)]} + 3cos(2)] + 3cosad + IF(jW2)13Si(cos3a2 + 3!F(jwdIS]IF(jW2)12Si[2cosa] + 3IF(jw])!2SrIF(jW2)IS2[2cosa2 In the above equations a] and a2 represent a] a2 = = + COS(2a2 .8) The argument of J in Eq. and Saa3. J(jw): So = a]F(jwa)J(jwa) 0 Si + a2F(jwa)F(jWb)J(jWa.5) The detailed expressions of Saa]. We. Wb.6) + 2IF(jwdIIF(jW2)IS]S2[ a Saa3 = .(2) + cos(2a] + (2)]} + cf>w] W2t + cf>w2 WIt (8. W] and W2. Saa2.SMALLSIGNAL DISTORTION ANALYSIS 243 The meaning of applying F through the operator 0 on the input signal Si is to multiply the amplitude Sn of each frequency component in Si by IF(jwn)1 and shift its phase by cf>wn.{[IF(jw])13Sr(COS3a] + (2) + cos(a] .7) The signal at the output. which are listed below for an input signal with two frequencies. are useful for deriving the distortion components in the following section: Saa] =a][IF(jw])IS] Saa2 cosa] + IF(jW2)IS2 cosa2] + 1) + IF(jW2)12Si(cos2a2 cos(a] = ~{[IF(jw])12Sr(COS2a] + 1)] (8. the output becomes Saa = Saa] + Saa2 + Saa3 = a]F(jwa) 0 Si + a2F(jwa)F(jWb) 0 Sf + a3F(jWa)F(jWb)F(jWe) 0 Sf (8.8 is the frequency of a given spectral component which in tum is a linear combination of the input frequencies Wa. The above result is generally valid for circuits with memoryless nonlinearities and linear frequencydependent elements. So.
Transfer functions of first.8) TEMPERATURE = 27.8 and by an appropriate assignment of ::tWl and ::tW2 to Wa.MODEL + + QMOD NPN RB=100 CJE=lP CJC=2P . Wb.PRINT DISTO HD2 HD3 SIM2 DIM2 DIM3 . 8.4M VI 1 4 AC 1 * * . 8. and third order can be isolated to compute the distortions of corresponding order.or thirdorder terms in Eqs.2.000 DEG C INPUT LISTING ************************************************************************* Q1 2 1 0 QMOD RL 2 3 1K * VCC 3 0 5 VEE 4 0 793.AC LIN 1 1MEG 1MEG .END Figure 8. as listed in Figure 8.DISTO RL 1 * . and We.244 8 DISTORTION ANALYSIS The different distortion measures introduced in Chap. The DC bias solution and the smallsignal parameters of Ql are recomputed and the results are in Figure 8.6 3/15/83******** 16:14:42 ***** ONETRANSISTOR ***** CIRCUIT (Figure 5. The linear equivalent of the onetransistor ******* 04/07/89 ******** SPICE 2G.2 Distortion in a OneTransistor Amplifier Consider the onetransistor amplifier of Figure 5. of 100 n and junction capacitances CJE and CJC added to the •MODEL statement. second. In conclusion.2.OPTION NOPAGE . the distortion terms of a signal at the output of a frequencydependent circuit with small nonlinearities can be found by writing the overall transfer function and replacing the nonlinear signals by series expansions. . RB.8 with a series base resistance. The following section exemplifies the use of this approach.2 Onetransistor amplifier input and DC bias point.2. 5 can be derived as ratios of the second.WIDTH OUT=80 .OP .
000 100.000 FT 4.948D03 1. 000 1.052 BETADC 100.2 (continued) 245 .26E12 CBX O.000 DEG C VOLTAGE NAME VCC VBE VI SOURCE CURRENTS CURRENT 1.948D05 1.0522 TEMPERATURE = 27.OOE+OO BETAAC 100.33E+03 RX 1.000 8M 7.00E+12 CPI 1.00D12 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.02E+09 Figure 8.00D12 2.**** TYPE IS BF NF BR NR RB CJE CJC BIT MODEL PARAMETERS QMOD NPN 1.259 VCE 3.7934 NODE ( 2) VOLTAGE 3.000 1.75D03 WATTS TEMPERATURE = 27.000 1.0000 = 27.OOE+OO CCS O.000 TOTAL POWER DISSIPATION **** **** OPERATING POINT INFORMATION TRANSISTORS DEG C BIPOLAR JUNCTION Q1 MODEL QMOD IE 1.793 VBC 2.948D05 9. 95E05 IC 1.72E12 CMU 1.53E02 RPI 1.00E+02 RO 1. 000 1.000 DEG C **** NODE 1) TEMPERATURE NODE ( 3) VOLTAGE 5.00D16 100. 95E03 VBE 0.
Each group starts with a header identifying the type of distortion. The distortion summary computed by SPICE2 at 1 MHz is listed in Figure 8. and QBe. as compared to the results obtained at 1 kHz in Sec.21 for an approximation of ie.14. see Sec. QBE.3.19 through 5. The contribution of each second or third derivative in the Taylor series to the output distortion is listed in the corresponding column of the SPICE2 printout. and the fundamental frequency. in the same manner as derived in Eqs.2. as defined in Eqs. Note that the current equations for Ie and IB in distortion analysis use not the GummelPoon formulation given in Appendix A. QBE. SIM2 and DIM2. 5. but the more simple EbersMoll . FREQ1. 5. The BJT DISTORTION COMPONENTS are due to the nonlinear voltage dependencies of Ie. 5. Ie and IB. such as 2ND HARMONIC DISTORTION.3 associated with a nonlinearity of the transistor.4 (Figure 5. and CJL in the linear equivalent in Figure 8. 3. The distortion contribution in the load resistor is computed for every element in Figure 8. as described in Chap. go. is specified in the. The DISTORTION ANALYSIS summary report lists five groups of BJT DISTORTION COMPONENTS. The elements g1T' gJL' gm. Note that the addition of the base resistance and the two charge nonlinearities do not significantly affect the absolute values of the second. C1T. for one input signal or FREQl and FREQ2 for two input signals. The total currents. HD2 and HD3. 5.4. can be expressed as Taylor series around the DC operating values. Ie. More detail than just the total distortion figures is obtained from SPICE2 when a summary interval.10 through 3. IB.3   l ~ Smallsignal equivalent of the onetransistor amplifier.4. and QBe in the firstorder terms of the corresponding Taylor expansions. the DISTORT I ON FREQUENCY and MAG and PHS of the transfer functions for the input signals are listed on the following line. equal to 1 in the deck shown in Figure 8.and thirdorder distortion terms. amplifier is shown in Figure 8.246 8 DISTORTION ANALYSIS rr~l : RB Q1 B' e~ c I~ I I I io + n r en IVb'  o r ! I I I I I I I Figure 8.9).3 represent the partial derivatives of IB. The higherorder terms of this series constitute distortion sources. which are listed under the AC ANALYS I S header. ie and iB. DISTO statement. and the secondorder intermodulation terms.
543D03 75.00 CJC 5.10 GM023 4.989D+Ol BJT DISTORTION COMPONENTS NAME GM GPI GO GMU GM02 Ql MAG 1.00 CJC 9.02 14.22 GM02 7.31 0.992D+Ol PHS 176.061D04 89.604DOl PHS 166.000D20 0.00 HD3 MAGNITUDE 1.98 75.261D02 1.30 GMU 1.92 CB CBR MAG 1.75 120.356D08 1.842D02 120.016D03 1.32 CBR 1.4 SPICE2.63 BJT DISTORTION COMPONENTS NAME GM GPI Ql MAG 3.00 3.000D20 PHS 0.63 COMPONENTS GPI 2.352DOl HZ MAG 6.989D+Ol GO 2.70 CB CBR MAG 1.735D08 0.00D+06 PHS HZ 176.61 PHASE 2ND ORDER INTERMODULATION DIFFERENCE FREQ2 = 9.56 TOTAL 3.989D+Ol BJT DISTORTION COMPONENTS NAME GM GPI Ql MAG 1.253D03 PHS 132.00 IM2D MAGNITUDE 3.90D+06 PHS 176.26 BJT DISTORTION NAME Ql GM MAG 3.544D02 PHS 179.209DI0 13.789D02 1.524D02 13.26 9.00D+05 HZ DISTORTION FREQUENCY 1.22 9.678D07 55.25 179.000D20 4.27 0. DISTO summary for the onetransistor amplifier. 247 .989D+Ol PHS 176.00 CJE 8.000D20 0.00D+06 HZ MAG = 0.000D20 0.00D+06 PHS HZ 176.00 0.**** DISTORTION 2ND HARMONIC DISTORTION ANALYSIS TEMPERATURE 27.71 TOTAL 3.69 DB TOTAL 1.000D20 PHS 0.000D20 0.598Dll 38.19 14.264DI0 0.800DOl 1.512D07 89.000D20 3.871D09 21.10 164.00 0.00D+05 HZ SUM COMPONENT 1.842D02 GO 1.00 IM2S MAGNITUDE GO 2.473D06 5.352DOl 165.600DI0 PHS 166.26 DISTORTION FREQUENCY 2.68 GM203 6.00D+06 HZ MAG 6.674DOl PHS 75.26 GM02 7. 674DOl PHASE 164.26 3RD HARMONIC DISTORTION DISTORTION FREQUENCY 1.84 165.000D20 1.61 GM02 5.267D07 22.50 DB PHASE (continued on next page) Figure 8.714D08 14.019D03 62.000D20 1.00 14.00 CB CBR CJE CJC TOTAL MAG 1.64 GMU 1.468Dll 21.73 0.377DOl COMPONENT MAG FREQI = 1.40 47.26 6.00D+06 PHS 6.30 CJE 3.632DOl 2.992D+Ol INTERMODULATION 9.56 34.00D+05 HZ MAG 6.53 FREQI 3.49 15.000 FREQI = DEG C 1.000D20 1.00 DB HZ 176.00 CJC 4.509D06 76.88 CB MAG 1.43 FREQI = PHASE DB HZ 2ND ORDER FREQ2 = DISTORTION 6.000D20 PHS 0.00D+06 MAG FREQUENCY 1.377DOl 179.74 CJE 4.68 GMU 1.49 HD2 MAGNITUDE 1.
377E01 14.26 GM02 GMU GM GPI GO MAG 5. For completeness the equations of Ic and IB used in SPICE2 for computing distortion are included here: = Ic (lcc .352E01 DIM2 3. Also.883E02 Figure 8. The total currents and voltages. The base and collector currents are functions of two variables.000D20 1.842E02 1.01 26.388D07 4.4 formulation including the Early effect from Eqs.10) .25 17.00 1M3 MAGNITUDE 4.867D07 1.000D20 1.01 79.22 GM023 TOTAL GM203 CBR CJE CJC CB MAG 1. the emission coefficients NF and NR are set equal to 1. VBE and VBC.24 0.95 157.883D02 PHASE 157.248 8 DISTORTION ANALYSIS 3RD ORDER INTERMODULATION DIFFERENCE COMPONENT FREQ2 = 9.674E01 (continued) H03 1.100+06 MAG 6.82 DB DB **** 27.844D01 6. such as VBE.616D03 3. such as Vbe: (8.973D10 1. IBC.10 through 3.00 0.515D03 1. 3.39 PHS 0.9890+01 176.68 23. 3.486D08 4.and highlevel injection have been neglected in order to simplify the derivation of higherorder terms and focus the results on the main nonlinear distortion sources.00 PHS 162.10 and 3. and an incremental component. and IBE have the same meanings as in Eqs.ICE) (1  :1~) )(1  IBC = Is (ev8dVth IB .86 8.9) = IBE + IBC where Icc. because of model simplicity at the time of the implementation.440002 TEMPERATURE = SIM2 3. The current components for low. ICE.000D20 2. are made up of a DC component.11.eV8c1vth :1~) %R (eV8c1Vth  1) (8.63 BJT DISTORTION COMPONENTS NAME Q1 HZ FREQ1 = 1.9920+01 PHS 176.000+06 PHS HZ MAG 6.883D02 7. such as VBE.12.000E+06 HD2 1.000+05 HZ DISTORTION FREQUENCY 1.000 DEG C DIM3 4.78 66.685D10 14.164D02 3.97 7.23 DB APPROXIMATE CROSS MODULATION COMPONENTS CMA CMP MAGNITUDE MAGNITUDE AC ANALYSIS FREQ 1.
SMALLSIGNAL DISTORTION ANALYSIS 249 Similarly. The values listed under GPI and GMUin the HD2 group represent the contributions to the total distortion due to the secondorder terms g7T2 and gIJ2 in ib. alc V Vbe a BE alc Vbe BC 1 (a lc 2vbe a V BE 2 Ie = + av + 2 2 + 2 av a lc av VbeVbe BE BC 2 + 2vbe a lc a V BC 2 2) (8... The incremental component ib has the following Taylor series expansion: ib = ig7T + igIJ = g7TVbe + g7T2v~e + g7T3vbe + . the input and output voltages of the transistor equivalent network shown in Figure 8. respectively.. however. In the same way distortion contributions can be associated with the Taylor coefficients of the expansion of ic: . (8. (8. Note that a value of 1020 represents zero distortion contribution.14) where iP) and i~2)represent the first.. of the ic series. are Vbe and Vee.3. + gIJVbe 2 3 + gIJ2Vbe + gIJ3Vbe + .15) .12) where alB aVBE alB avBC I a2lB g7T2 g7T = 1 dlcc {3FdVBE I dIcE {3RdVBC 1 d2lBC (8.and secondorder terms.13) gIJ 2av~E 2 dV~E 1 d2lBE 2dV~c gIJ2 = 1 a2lB 2av~c and so on.9. respectively. A change of variable (8. 8.11) where IB is defined by Eqs. Note that Vbe and Vbe are the independent variables in the above equation.
and GM02 in the SPICE2 output represent the secondorder distortions (8.19) . 3.2 and 3.GO. The current through a nonlinear capacitance can be expressed in a power series: (8. (8.4.17) respectively.and secondorder components of ic: (8. Next consider the distortion due to the charge components.16) where + alcT aVBE alcT aVBC go alc aVBE alcT aVBC = g f.L alc aVBC GM. The nonlinear charge formulations are described by Eqs.250 8 DISTORTION ANALYSIS leads to the following expression for the first.18) Here C(V) has two possible formulations.
IBE.13 and 8. defined by Eqs. ga2 CJE and CJC represent the distortion contributions due to the junction capacitances. namely. and Vl is the junction voltage.1 to find the transfer function of the frequencydependent and nonlinear blocks of Figure 8. The distortion in the load resistor.22. Start out by writing the transfer function for the smallsignal circuit in Figure 8. due to each nonlinearity is evaluated by considering only one distortion source at a time. IBc. ID represents the diffusion current.21) = Cdc2 TR. A source of small distortion can be associated with each nonlinear term (Chisholm and Nagel 1973) in Eqs. ICE and the different charge terms in Eqs. 8.17.(Vl + Vj)/ cPl]Ml (8. The approach used in Sec. 3. 11T = 0 (8.L  . Note that the circuit distortion is additive in a vector sense. In the smallsignal equivalent C1T and Cf. 8.L include both types of capacitances. 3. defined by Eqs.23) ia igm  if. Kirchhoff's current law (KCL) is applied at nodes B' and C to yield Vi  RB Vb' +  . that is. RL. It is instructive to derive by hand the different distortion components for the onetransistor amplifier in order to understand the meaning of the SPICE2 distortion summary report.22) respectively.l8: Cde2 = = a2QDE aV~E a2QDc av~c = TF.14: Cje2 Cjc2 = = dClE dVBE dClc dVBc (8. the printout of the distortion components separates them. The total distortion at the output of the linear circuit is obtained by superposition of all individual contributions. CB and CBR represent the contributions due to CDE and CDC.2. 8.20) for the junction capacitances.3.21 and 8. gm2 (8. two distortion generators of equal magnitude and opposing phase cancel each other.SMALLSIGNAL DISTORTION ANALYSIS 251 for the diffusion capacitances defined by Eq. Icc or ICE.3. respectively. however.L = 0 . Icc.3 and Co J ClO [1 . 1f.1 is used in this derivation.
8.23) for first. which must be satisfied for the terms of different orders in the Taylor series expansion of the currents and voltages.24) The derivation is simplified by splitting the circuit in Figure 8. from the output to the internal base. The input equivalent of gIL' CIL. 8. In the following derivation secondorder distortion figures are computed first. Each distortion source contribution derived below has a onetoone correspondence with a distortion component in the SPICE2 summary. has a nonlinear component. 8. and a linear component. and thirdorder terms. The current i1T. 8. gIL is very small and can be neglected.252 8 DISTORTION ANALYSIS These are general equations. represented by ig1T in Eq.2 the input signal. ig1T (Eqs.12).72pF = = C1T . The coefficients of the above series are derived by satisfying the KCL (Eqs.3 into two disconnected subnetworks.5.12.23 yields from which the following expression for al can be obtained: (8. Vi: (8. is multiplied by the voltage gain. iC1T: (8. 7. Vi.25) Because ig1T is nonlinear Vb' can be expressed as a power series of the input signal. in Eqs.27) It is calculated by substituting the following circuit component values: RB = g1T 1000.26) where al represents the transfer function from the input to the internal base. shown in Figure 8. consists of two sinusoids of frequencies WI and W2 and amplitudes Vii and Vi2: (8. 8. B'. second. Similarly to Si in Eq. the distortion contribution of which appears in the GPI column in the printout. Consider the nonlinearity due to IBc. Substitution of the firstorder terms in Eqs.5 X 104 mho l. avl. 8.23.
26 pF avi = gmRL = 0. The contribution at the output. (2) 1 Vag'1T Va HD2g'1T = 2 2Van (8.8 evaluated for a2( jWI. respectively. and different combinations of the two must be used depending on which distortion measure is evaluated.075 X 103 = 75 Next. a2( jWI. j(2). can be obtained by multiplying the secondorder component in the vb' series by the gain: (8.j(2).L = 1. 8.30) . + + I ~ Figure 8.28) where a2 is a function of WI and W2.SMALLSIGNAL DISTORTION ANALYSIS 253 r. due to g'1T'result from the secondorder terms in Eqs. B Q1 I I I I I I I I I I I I I L RB B' C I I~ . and DIM2. The values of a2 represent the secondorder distortion at the internal base due to g'1T'that is. a2 can be expressed from the above g'1T2RBal(jwI)al (jW2) 1 + g'1TRB+ j(WI + (2)RB(C'1T + avi CJ.5 Smallsignal equivalent using Miller's theorem. CJ.29) The expressions of HD2. . the first of Eqs.6 and 8. SIM2. anda2( jWI.23 is written for the secondorder terms of the currents and voltages: Note that equation: Vi has no terms of second or higher order. 8. in resistor RL.L) (8. jwd. the IBe nonlinearity.
jwl) .075 + j6. vogrr.72 + 75.053)2 1.93 . jW2).16: (2) .9 .254 8 DISTORTION ANALYSIS where Vo is the gain referenced to the input for an input signal of amplitude IV. ') 1 vogrr( jWl. corresponding to 1. 8. a2(jwl. for SIM2 evaluate .053)2 . =  0.3 . jW2) .92 where grr2 1 = .45(0.28 .9wl.075 + j6.106). and Von is the normalized output voltage corresponding to 1 mW power in RL.72 + 75.0256 13° . 102 .26)1012 = a2(jwbjwd where WI + W2 = 1. The distortion signal at the output. 106) 1. a2(jwl. jW2 2 Vo SIM2grr = 2 Von (8. =  1.102(1.31) The magnitude and phase of SIM2 are ISIM2grr1 LSIM2grr = = 0. = 0. (1.jO.212) = 1.30 yields the amplitude and phase of HD2grr: IHD2grr1 = 0. (2. 1.1. The secondorder intermodu1ation components are calculated similarly.9 MHz.26)1012 jO.28 . jWl) is . and its value is substituted into the definition of SIM2 ofEq.0126 These values are in excellent agreement with the values computed by SPICE2 in the GPI column ofthe 2ND HARMONIC DISTORTION category.93 . 102(0. a2(jwl.jO. (1.3 .0145 A/ V2 2 Vth Substitution in Eq.0145 .24(0. 5.grr. is calculated for a2(jwl.
3.SMALLSIGNAL DISTORTION ANALYSIS 255 The difference intermodulation component is derived similarly by substituting 1. to find b1 and bz: Va are used in the KCL. and GM02.23. where WI  Wz is 27Tx 0.17. gmRL 1 + jWICfoLRL (8. The magnitude and phase of DIM2 are IDIM2g1T LDIM2g1T 1 = 0. IOz(1.106). the second harmonic component due to the gm distortion source.jO. 8.053)(0.jO.93 . HD2 as predicted in the frequencyindependent case in Example 5.7° Note that the 1M2 components agree with the SPICE2 results and the magnitudes are equal to 2. 8.45(0.and secondorder terms of ic and 8. the second of Eqs. GO.012) in Eq. Eq. The harmonic distortion due to the nonlinearity of Ie is summarized in the SPICE2 output in the columns GM. The following equations are used to derive HD2gm.33) with The first.26)1O1Z 1.34) gmZRL 1 + j(WI + wz)CfoLRL .29.075 + j6. 8.1 MHz.72 + 75.28' (0.93 .047) 1. ic is expressed as a power series of Vb': (8. 1.93 + jO.7.32) and Va is a power series of Vb': (8.1.25(0. based on the Taylor series expansion of ie around the operating point/c. The equivalent distortion sources generating these three contributions to the second harmonic are defined in Eqs.0255 = 0.14.
2.35) resulting in the following values: IHD2gmi LHD2gm = = 0.17: 1 gm 2V gm2 = = / 2 1.1).36 X 108.23) at the output node and using only the go terms of the ic series: (8. which now represents the distortion at the output due to go: (8. The second harmonic contribution is found in the GO column of the SPICE2 output and is equal to 1. equal by default to 1012 mho. 8. 10.36) A new value is obtained for h2. 8.181 166 0 At first glance the distortion due to go should be zero since no value has been specified for the Early voltage.256 8 DISTORTION ANALYSIS where gm2 is computed according to the Taylor series coefficients.45 A V th h2 represents the contribution of gm to the second harmonic in the output voltage: Vogm (2) _ h 2 2Vb' The distortion at the output is computed according to Eq. The resulting value can be verified replacing the secondorder terms in the KCL (Eq. This result can be explained by the conductance GMIN added in parallel to each junction (see Sec. VAF.37) where the go term has been neglected and .29: 1 vogm Vo (2) HD2gm 22Von (8. Eqs. 8.
.20 and the series  112 (l + x)" = 1 + ax + 2!a(a . 8.\ccording to Eq. are evaluated next. and therefore the nonlinearity in C1/"or C IL can be expressed in the single power series (8. . irl.crE jel VJE(l = MJE . with VBE > FC. and Cj2 in Eq. Only the junction capacitanc~s CJE anq CJC are defined for transistor Ql in this example. The derivatives of Eq. 10. that is.40) The values of C1/"O. and C1/"2.4l) described in Sec.2.16. follows: IHD2goi = 1.38) based on Eqs.39) (8. 8. are the first and second derivatives of Cj with respect to VJ. which were used in calculating the distortion contributions of g1/"' remain valid. but Eqs. Eq.38 because the BE junction is forward biased.26. 8.l)x + .4 can be verified through the above approach.2.3. 8. The coefficients Cjl and Cj2 in the power series of Cj.42) C1/"2 = Cje2 0 . The distortion components due to QBE and QBC. is nonzero'because of the GMIN conductance. The value listed under GM02 in Figure 8. VJE)(MJE+l) (8.23 and 8.C .40: C 1/"1 .FC. the graphical interpretation of the above approximation is shown in Figure 10. and SPICE uses the following approximation: CJE [MJE C1/"O= Cje = (l :: FC)MJE 1 + VJE(l ] _ FC) (VBE . 8. HD2go.which correspond to CjO. For the evaluation of the distortion contribution of Cje.4 x 108 The distortion contribution due to the secondorder crossterm gmo2 in the ic series.25.SMALLSIGNAL DISTORTION ANALYSIS 257 The second harmonic distortion coefficient.. 8. 8. 8.7. Eqs.18 and 8. respectively. VJE) (8.41 lead to the coefficients for Eq. expressing currents ig1/" andic1/"' must be changed to (8. represented by C1/"and CIL in Figure 8.38. Eq.12 and 8.. no TF or TR parameters are specified.38. VJE. 8.FC. C are not computed. Cjl.
IRB (l + jWl C". HD2c"... 8.oRBl j(WI The amplitude and phase of the secondorder distortion.. The firstorder equation and.43) = 4. 106 = 77° which are in excellent agreement with the SPICE2 values.40 are used to compute the values of the coefficients aI.26: of secondorder = Cjcl Cjc2 BC = = 3CJL1 VIC 2 1 +MIC .5.23 and 8.44) where Vo has been replaced by avlvb" C JLO equal to Cjc. 8. as shown in Figure 8. 3 dv~. 8.oRB)[l + j(WI + w2)C".ORB)(l + jW2C". calculate the distortion due to CJLi.23 yields the following value for in (8.8.[t av V dv~.. and a3 of the Vb' series.23 is used with i JL expressed by the following series due to the nonlinearity in the junction capacitance C JL: _ dVb' 2 i JL . the capacitance of the reversebiased is following derivatives Cjcl and Cjc2: 1 MIC "2.cJLOVIC ....VBc a2 terms in Eqs..[t + CJL1av 1 (if + CJL2 1 . (8. due to C". First. The secondorder terms inserted into the first of Eqs. therefore..1 LHD2c". Eq. al are the same as for g". and has the CJLl CJL2 Substitution Eq.46) The secondorder distortion component HD2cJLi has the following magnitude: .IV~' + j(WI + W2 + w3)CJL2a~lv~.V BC junction. The distortion contribution due to CJL will be derived next. The first of Eqs.. 8. = jWICJLOavIVb' + j(WI + W2)CJLla.5 .. are (8.26. the reflection of CJL to the input circuit.258 8 DISTORTION ANALYSIS Eqs. 8.CJLOa 1 . IHD2c". a2.23 yield the following expression for a2: + W2)C".
]V~ + j(W] + Wz + W3)CIJ. 8. 5 and equal 2 X HD2.4 in the CJC column.25 and 8.OVo The assumption that the input circuit is linear represents an approximation made in order to avoid the more complex solution.47 after inserting the value of bz from Eq.167 is very close to the value of HD2 obtained in Sec.4 for the transistor with no frequencydependent elements.5. The magnitude 0.48) (8. at the output is the sum of the two coefficients This value is in agreement with the value found in the SPICE listing of Figure 8. 8.49: The contribution due to CIJ.and secondorder terms in Eqs.47) = jW]CIJ. and C is negligible compared to the nonlinear resistive contributions. which involves the power series of both vb' and Vo simultaneously. The nonlinearity of ilJ. is evaluated from the output circuit in Figure 8. component connected at the output node is obtained from Eqs. = b]Vb' + bzv~.674D01 PHASE 164. the derivation is more difficult and prone to errors due to some approximations made in hand calculations.23 yields the following values of the coefficients b] and bz: (8. 8. 7T . Because 1 MHz is a relatively low frequency. which is a power series of Vb': Vo ilJ.49 = 15. 8.ZV~ (8. the total secondorder intermodulation sum and difference components track the values of Chap. + b3V~. The thirdorder distortion can be computed following the same steps as above.23.26 into KCL. The thirdorder distortion due to the IBe component of the base current can be computed by replacing the thirdorder terms of Eqs. 5. is assumed to be due only to vo. Eqs. + j(W] + WZ)CIJ. The section 2ND HARMONIC DISTORTION is concluded by the line HD2 MAGNITUDE 1. the distortion due to the nonlinear capacitances CIJ.49) The secondorder distortion due to the CIJ. gm and g7T' Similarly.53 DB. 8. Because the number of terms involved is higher.SMALLSIGNAL DISTORTION ANALYSIS 259 The second part of the distortion due to CIJ. which gives the total secondharmonic distortion in the load resistor obtained by adding all the complex numbers representing the individual distortion components. Substitution of the first.
for the output section of the transistor model. The thirdorder distortion component due to gm is computed similarly. by the insertion of the thirdorder terms in Eqs. jW2.52) The magnitude of this distortion yields which is in agreement with the SPICE2 value for GPI in the 3RD HARMONIC DISTORTION section.33 into KCL.55) which translates into the following magnitude for HD3: IHD3gmi = 2. results: a3( jWl.54) The thirdorder distortion contribution due to gm in the output voltage is (8. Eq.22 X 102 . jW2) CJL) I + g71"RB + j(Wl + W2 + w3)RB(C71" + avl (8.23. jW3) .32 and 8. 8.260 8 DISTORTION ANALYSIS Coefficient a3 in the Vb' series.51) and the thirdorder distortion due to g71"is given by (8.2g71"2RBal (jwl)a2( jWl. Eq. The HD3 contribution is obtained by multiplying a3 by the gain avl: at the output (8. 8.53) where W3 can be :tWl or :tW2 depending on the distortion component to be derived.26. 8.g71"3RBal (jwl)al (jw2)al (jw3) . The thirdorder coefficient in the power series for Va results: (8. and (8.50) where the possible values of W3 are :tWl or :tW2.
6 the following crossmodulation term is generated: (8. Two additional distortion components. which represents the spectral component at 2Wl . Cross modulation (Meyer. the carrier signal.57) The total third"order distortion HD3 is the magnitude of the vector sum of all components. amplitude modulation is transferred to the signal WI.2 is modulated in amplitude and the other is not: (8.58 with 52 equal to 1 if not otherwise specified on the • DrSTO line.W2 = 21T X 1.59) where m is the modulation index. The term with this frequency in Eqs. and the value 1M3 = 4. 8. 8. 8. Because of the nonlinearities in the circuit. In our example this assumption is generally valid. An important distortion measure is the thirdorder intermodulation.88 X 102 computed by SPICE relates to HD3 approximately according to Eq. and Eschenbach 1972) occurs when one of the two input signals in Eq. The last distortion category computed by SPICE as part of the summary is that of the APPROXIMATE CROSS MODULATION COMPONENTS. 8.6 represents the 1M3 component.60) .84 X 102. In the thirdorder term in Eqs. equal to 1.SMALLSIGNAL DISTORTION ANALYSIS 261 HD3gm is evaluated according to Eq. the 1M3 distortion can be related to HD3 as follows: (8. for the thirdorder distortion it is harder to separate in hand calculations the different distortion components contributed by Ie.56) gmo23 aVBEaV~e (8. 5 for the circuit with pure resistive nonlinearities and without parasitic base resistance. and is very close to the value obtained in Chap.79 X 102 predicted by SPICE. denoted 1M3. 8. Shensha. can be noticed in the summary report for thirdorder distortion. Assuming that F( jWl) F( jW2). They represent the distortion due to the following partial derivatives in the Taylor series expansion of ie: VO' a31e gm203 aV~EaVBe a31e (8. GM2 03 and GM02 3.1 MHz.52 where the gm contribution replac'es that of g1T in This value is larger than the 1.58) as long as frequencydependent effects are not important.
nonlinearities only. CMA. corresponds to CM at low frequencies (defined by Eq.j(2) is the thirdorder transfer function for the modulated w! component (see Eqs. amplitude (8. 8. .63) A phase crossmodulation factor. or resistive. 8.58. is defined as the ratio of the transferred modulation to the original fractional modulation. CMF: (8. At high frequencies the amplitude crossmodulation. .61) for equal amplitudes of the two input signals.6 and 8.62 and the definition of 1M3.65) and phase cross The above equality is used in SPICE2 to compute the amplitude modulation terms: CMA CMP = 411M31 COS(<PIM3.8). From comparison of Eq.62) where H3( jw!. For frequencydependent nonlinear circuits the phase shifts of the different transfer functions must be considered in defining a frequencydomain crossmodulation factor.67) = 411M31 sin(<pIM3.61) and is equal to CMA where = CMF.262 8 DISTORTION ANALYSIS The cross modulation index. can be defined as the ratio of the transferred phase modulation to the original fractional amplitude modulation: CMP = CMFsin<p (8. CM.IM3 (8. Vi] = Vi2. 8. 8.64) The values computed by SPICE2 are based on the relation between CMF and the thirdorder intermodulation distortion. Eq.66) (8. CMP. the following equality results: CMF = 4. cos<p (8.<Po) where <PIM3and <Poare the phase of 1M3 and the phase of the signal at the output. jW2. respectively.<Po) (8. This definition is valid for memoryless. 1M3.
corresponding to this specification is (8. the Fourier analysis does not offer the evaluation of intermodulation distortion in the presence of two input signals and the distortion contribution by type of nonlinearity available with the smallsignal . Largesignal analysis provides more accurate results than AC smallsignal analysis because of the removal of the linearity. The most important issue is to scale the amplitude of the sinusoidal input signal properly so that the circuit dissipates the same power in the load resistor as specified in the • nrSTO statement.LARGESIGNAL DISTORTION ANALYSIS 263 8.4) is av = ~ = 69. or 0 dBm.2mV (8. nrSTO analysis.9 which leads to an input amplitude of Vi = Vo av = 20. 6.3 LARGESIGNAL DISTORTION ANALYSIS A good approach for estimating the total harmonic distortion is to run a largesignal timedomain analysis and then use the • FOUR analysis introduced in Sec. can introduce errors due to the approximation of the waveform based on the values stored for the discrete timepoints used in the transient analysis. 8. The Fourier analysis computes the first 10 spectral components in SPICE2 and a userspecified number of harmonics in SPICE3. The computation of the spectral components. however. nrSTO for the onetransistor amplifier in the above section.8) Ql 2 1 0 QMOD RL 2 3 lK * vce 3 0 5 . Also. Vo.1 OneTransistor Amplifier Distortion It is a useful exercise to check the distortion measures computed by SPICE2 using .4. or smallsignal. The amplitude of the output voltage.3. The distortion components for the above circuit were computed for 1 m W power in RL.68) The gain predicted by the AC analysis for this circuit (see the results in Figure 8. assumption.69) ONETRANSISTOR CIRCUIT (Figure 5.
69 leads to the following value of Vi: Vi = 19. and a frequency of IMHz. the thermal voltage.MODEL QMOD NPN + RB=lOO + CJE=lP + CJC=2P . one needs to doublecheck that the value of the gain computed in the AC analysis is accurate.OPT NOPAGE REL'IOL=lE4 ITL5=O LIMPTS=5000 • END The SPICE input is shown above.TRAN IN 2U 0 IN . the circuit has the sinusoidal input signal Vi with a DC offset. Before checking the results of the Fourier analysis.6.2M lMEG AC 1 * * . that is. The measurements show that this value is 1. the amplitude of Vo should be 1.0162 which are close to but slightly less than the values obtained from the • DISTO analysis.OP *.PLOT TRAN V(2) . This value points to a gain of 72.AC LIN 1 lMEG lMEG * . where the accuracy of the linear approximation declines. The results of the analysis with Vi = 19.4mV . The discrepancy in the value of the gain can be explained by the fact that the input voltage is very close to the value of Vth. an amplitude of 20.4M VI 1 4 SIN 0 20. as well as the value of TMAX. TRAN line. which must be 1. First check the value of the first spectral component at 1 MHz. 8. . The second.154 0. of 793.FOURIER lMEG V(2) . which inserted into Eq.DIS'IO RL 1 * * .and thirdorder harmonic distortions are HD2 HD3 = = 0.41 V.41 V for proper calibration of the spectral components.264 8 DISTORTION ANALYSIS VEE 4 0 793. Note the large number of time steps specified on the .4 m V necessary to bias the circuit.7. VBE.46 V.2 mY.WIDTH OUT=80 . 2000.4 mV are shown in Figure 8. the maximum time step the program is allowed to use in order to estimate the spectral components over the last period.
388 127.976 69.976003 0.000Dt06 2. The radio signal. Wi!.179001 0. and generates the local oscillator signal (LO). The difference frequency is called the intermediate frequency.477 103.241004 0.000Dt06 1. which rejects the sum and other frequency components.062005 0.7.288002 0.484004 0.715 102. Q].000 71.000Dt06 1. ws.LARGESIGNAL DISTORTION ANALYSIS 265 **** FOURIER ANALYSIS TEMPERATURE = 27. and Vs is defined as the input signal (5): The two signals add up to an input voltage Vi consisting of two frequencies: (8.000Dt06 2.831003 0.263 306.453 0.004232 5 5. in parallel form a bandpass filter at the output of the mixer.000105 8 8.935 245. Two voltage sources are connected at the input: Vw sets the bias at the base of transistor.000029 9 9. Wlo.520066 PHASE NORMALIZED (DEG) PHASE (DEG) 175.466 PERCENT Figure 8.000Dt06 1.299 146.70) . R]. and a local signal generated in the receiver.001296 6 6.055005 0.000Dt06 1.000D+06 4.044 48. C].412DtOO 1.000Dt06 5.846 197.000008 TOTAL HARMONIC DISTORTION = 15.505 21.831DtOO HARMONIC FREQUENCY FOURIER NORMALIZED NO (HZ) COMPONENT COMPONENT 1 1. L]. The mixer operates as an analog multiplier by generating spectral components of frequencies Wlo :t ws' The mixer is followed by a bandpass filter tuned to the difference frequency.409 4.154288 3 3. 8.947 72.2 SingleDevice Mixer Analysis Mixer circuits are commonly used in radio receivers. A typical singletransistor mixer circuit is shown in Figure 8. The local oscillator frequency is tunable so that the difference between the two signal frequencies is approximately constant.000000 2 2. are fed to a mixer circuit.000371 7 7.682 131. and the load resistor.016205 4 4.013 321.6 Fourier analysis results.3.229 179.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V(2) IX:COMPONENT = 2.000Dt06 5.
71) where leis the quiescent DC value of the collector current..2.. A differencefrequency component is present in the output current.. Singletransistor The transfer characteristic of the BIT is approximately equal to (8.266 8 DISTORTION ANALYSIS Figure 8.21 and in the above sections a power series was used under the assumption of a small signal. 5. namely v. according to the smallsignal derivation of Sec.1: = Ie [1 + . + az Vlo Vs COS(Wlo  ws)t + . 8.72) . In Eq. ] (8.. ie.j Vth < < 1. There are two possible series expansions for an exponential.7 mixer.
1] (s)1](l) COS(Wlo . 8.75) IcIo(s)Io(l) is the dynamic average value of the collector current. ] (8.. is generated as well as other components not included above.. obtained from smallsignal analysis..75 are identical. If the amplitude of an input sinusoid is not small with respect to Vth.. the IF component.74 into Eq. This 1M2 component represents the IF signal. 8.ws)t = IDe [ 1 + .. + 2 Io(s)Io(l) where IDe = + .ws).1 MHz.. After substitution ofthe series ofEq. The IF component in Eq. 8. 8. and fs = I MHz. the output collector current is ie = IcIo(s)Io(l) + . A differencefrequency spectral component (Wlo .LARGESIGNAL DISTORTION ANALYSIS 267 where Vi is the total input signal for the mixer circuit. 8. which is the output of interest in a mixer: (8.71 and use of trigonometric identities.75 derived through a Fourier series expansion is more general than the expression in Eq.73) In the case of a mixer or a multiplier the smallsignal assumption is not always true.ws)t + . (8.72 and 8.73. all spectral components except the IF component must be rejected by the output filter. Vs = 1 m V. + 21] (l) cos wlot + .74) where s I = = and In (x) are modified Bessel functions of order n.. For small signals Eqs.. which can be found in mathematical tables. flo = 1. + 2Ie1] (s)1] (I) COS(Wlo .72 or that in 8. the exponential can be expanded in a Fourier series with Bessel function coefficients (Pederson and Mayaram 1990): exp(Vs cos wst/Vth) exp(Vlo cos wlot/ Vth) = = Io(s) fo(l) + 21] (s) cos wst + . Assume the following values for the amplitudes and frequencies of the two signals: Vlo = 100 m V. Vlo is a large signal and .
Vs' The Q of the parallel RLC filter must be dimensioned so that the rejection. 8. Re j (w). is much larger than the radio signal.75 must be used to calculate the IF component. s 1 Vs lo(s) 2 2 Vth The difference component of the collector current becomes iCij = 0. ICla = h(l) 21Dc lo(l) COSwiat (8.268 8 DISTORTION ANALYSIS therefore Eq. From the Fourier series.26.76) The correct design of a mixer requires that the amplitude of the IF output voltage be much larger than any other voltage.951Dc Vs th vCOSWijt (8. Rej.77) arid using iCij as given in Eq. for a singletuned parallel RLC filter is given by (8. The selection of this value is made difficult by the fact that the amplitude of the local oscillator.78) which in this example is over 50. The ratios of Bessel coefficients are found in math tables: h(l) fo(l) h(s) = 095 . at Wla is sufficient to boost the IF component.79) where = 1 Wa jLC is the resonant frequency and Q is the quality factor defined in Eq. 6. . Via.76 the ratio of the LO component to the IF component is given by iCla iCij = 2 Vth Vs (8. 8. The rejection of a given frequency component. Vij .
FOUR lOOK V(3) .2U 620U 600U 45N .( e] Volo Vs ) (8. There is a limit of only nine harmonics printed by SPICE2 including the fundamental.lM V(3) .TRAN . The first set of input commands is If Q = Rej = .WIDTH OUT=80 . leading to an IF voltage component 8.49 times larger than the amplitude of the local oscillator at the output Volo' The SPICE circuit description and the resulting DC operating point are shown in Figure 8. In order to have SPICE2 compute the amplitudes of both the IF and LO components.PLOT TRAN V(3) *******12/13/90 ******** SPICE 2G. the rejection of the LO component is 440. The IF and LO frequency components can be checked by requesting a • FOUR analysis.8.80)  Wlo 40 for the tuned circuit of Figure 8.8 SPICE2 input and DC bias point for mixer circuit. * .000 DEG C *********************************************************************** Q1 3 2 R1 3 4 C1 3 4 L1 3 4 .LARGESIGNAL DISTORTION ANALYSIS 269 The ratio of interest between the voltage amplitudes of the IF and LO components is Voil _ 2 VthR.lMEG AC 1 .244NF 596. SIGNAL AND LOCAL OSCILLATOR VCC 4 0 10 VS 2 1 0 SIN 0 1MV 1MEG VLO 1 0 0 SIN 0.8U 600U 45N *.MODEL 0 Mom 15K 4.6 3/15/83 ********18:44:38***** ONE TRANSISTOR MIXER CIRCUIT **** INPUT LISTING TEMPERATURE = 27.7.83UH Mom NPN * * * SUPPLY.END Figure 8.TRAN .TRAN 45N 601.PLOT TRAN V(3) .OPTIONS RELTOL=lE4 ITL5=0 .FOURIER 1.2U 620U 600U 45N .78 100MV 1. two separate runs must be performed.FOURIER lOOK V(3) *.
25E05 1.70E+17 (continued) Figure 8.000 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.000 1.OOE+OO O.000 DEG C **** NODE 2) TEMPERATURE NODE 4) VOLTAGE 10.220 10.25E03 0.270 8 DISTORTION ANALYSIS **** TYPE IS BF NF BR NR BIT MODEL PARAMETERS MODl NPN 1.251D03 1.25D02 WATTS TEMPERATURE = TOTAL POWER DISSIPATION **** **** OPERATING POINT INFORMATION 27.000 DEG C BIPOLAR JUNCTION TRANSISTORS Q1 MODEL IE IC VEE VEC VCE BETADC 8M RPI RX RO CPI CMU CBX CCS BETAAC FT MODl 1.00E+12 O.07E+03 O.000 1.000 4.00D16 100.84E02 2.8 .780 9.OOE+OO 1.000 7.251D05 1.000 DEG C VOLTAGE NAME VCC VLO SOURCE CURRENTS CURRENT 1.7800 NODE 3) VOLTAGE 10.0000 TEMPERATURE = 27.000 1.0000 = 27.000 100.OOE+OO O.OOE+OO O.OOE+OO 100.
10 Fourier coefficients of the IF component.000242 0.607D04 1.000256 0.714 PERCENT NORMALIZED PHASE (DEG) 0.062 109.240 14.027 61.000Dt05 5.000903 0.000 95.330 42.000Dt05 9.280 132. which request SPICE2 to plot the waveform of V ( 3).347D03 1.888 19. The .us) after 60 cycles have been computed to assure that the circuit has reached steady state.077 28.348 62. for the last two periods (Tij = lO. .929 100.LARGESIGNAL DISTORTION ANALYSIS 271 15 > 8 :> 10 605 Time.059D03 1.000Dt05 3.106690 PHASE (DEG) 89. FOUR statement requests the harmonics of the 100kHz spectral component. ~s Figure 8.593D03 1.211 157.000216 0.000169 0. 000Dt01 DC COMPONENT = FOURIER NORMALIZED HARMONIC FREQUENCY COMPONENT (HZ) COMPONENT NO 1 2 3 4 5 6 7 8 9 1.624D03 1.000Dt05 2.225DtOO 5.298 152.879 190.9 IF component waveform.000292 0.236 TOTAL HARMONIC = Figure 8.819D03 DISTORTION 1.509D03 5.950 5.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V(3) 1. The IF waveforms modulated by the LO signal TEMPERATURE = **** FOURIER ANALYSIS 27.161 67.290 75.000Dt05 7.000090 0.000Dt05 6. the collector voltage.000Dt05 8.000Dt05 6.054D03 1.000Dt05 4.000000 0.000170 0.
0 Time. and fo(l) = 10.025815 .272 8 DISTORTION ANALYSIS are shown in Figure 8.FOUR 1.9 V (8. The • TRAN and • FOUR statements for the next run must be changed in order to observe the 1.25 .090U 45N .1MHz LO signal waveform are shown in Figure 8. from tables of Bessel functions.76: Voif = IcifRi = 0.225 V. 102 A with Ie given by SPICE2. 8. the last two periods of the 1.ingEq.Is 610.5 610.25 . 103 A) .5 Figure 8.10. 103 n 6. the Fourier analysis results are listed in Figure 8.lMEG V(3) As in the IF signal plot.95IDe v th Ri = Vs = 103 0.9.TRAN 45N 610.This value can be verified by hand uS. The amplitude of Voif computed by SPICE2 is 6.95 . ).11 Waveform of the LO signal. (1. the resulting Fourier coefficients for the WZo signal are listed > '* :> 609. . 102 A) 0.81) where IDe = Iefo(s)Io(l) = (1.909U 609.25.IMHz LO spectral component: . and Io(s) = 1. 10 = 1.11.
800Dt06 9.12. Pederson.700Dt06 8.80: 1.900Dt06 8.300Dt06 4.5 predicted above.038 151.885 0. and Sangiovanni. Newton.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V (3) DC COMPONENT = 4.095D02 3.867 142. It is necessary to provide at least 20 points for one period of a sine wave for the calculation of the Fourier coefficients to be accurate. . 0. The results of the SPICE3 Fourier analysis are listed in Figure 8. Since Vlo is not much larger than Vth.TRAN analyses were run with a maximum internal time step TMAX = 45 ns. SPICE3 allows a user to define the number of Fourier components computed.337 257.000 111. The SPICE3 Fourier analysis verifies the ratio VOitiVolo = 8.Vincentelli 1992). it is **** FOURIER ANALYSIS TEMPERATURE = 27. 8.151106 0.200Dt06 3.89 V.344D01 9.168D02 5. is larger than that predicted by Eq.100Dt06 2.051932 0.618D02 4.342 280. which represents 1I20th of the highestfrequency component of interest in the signal.82) The approach of finding the highfrequency component of a modulated signal from a Fourier analysis with this component as fundamental is very inaccurate. 102 440 • 15 .085574 0.451 146.LARGESIGNAL DISTORTION ANALYSIS 273 in Figure 8. 103 V = 0.923 262.881368 PHASE (DEG) 110.600Dt06 7. 1.069368 0. The value computed by SPICE2 for Volo.533 156.763D02 6. The amplitude of the IF component can vary by 100% depending on which time interval of the IF signal's period the computation is performed.184 251.456 169.752 253.058822 0.13. in this example both the IF and the LO magnitudes result from a single analysis as the fundamental and the eleventh harmonic.099DtOO HARMONIC FREQUENCY FOURIER NORMALIZED NO (HZ) COMPONENT COMPONENT 1 2 3 4 5 6 7 8 9 1.418 266.400Dt06 5.609D02 1.892D01 7.12 = Fourier components of the LO signal.510 276.041623 23.056 TOTAL HARMONIC DISTORTION Figure 8. Better accuracy can be obtained from a program that can compute more than nine harmonics.624 165.500Dt06 6. More details about Fourier and distortion analysis in SPICE3 can be found in the latest user's guide (Johnson. Note that the above .81 V (8.701D02 1.171 PERCENT NORMALIZED PHASE (DEG) 0. Quarles.23ID02 4.109789 0.298 140.25 . The same result can be arrived at by using the • DISTO smallsignal analysis as long as the circuit behaves fairly linearly.000000 0.9.046057 0.
16 79.311 84.000165179 0.131 0 1 2 3 4 5 6 7 8 9 10 11 0 1 0.993 11.4 161.1et06 9.17 71.103 mW = 175 mW (8.732933 0 0 101.1382 Norm. Gridsize: 200.00115581 0.274 8 DISTORTION ANALYSIS 1> spice3d2 Spice 1 > source 1xtor_mixer.425 180. Interpolation Degree: 1 Harmonic Frequency  Magnitude Phase 0 89. instructive to verify the results of the. Phase 0 100000 200000 300000 400000 500000 600000 700000 800000 900000 1et06 1.00663444 0. Mag  Norm.00106634 0.0181946 0.224 0.296 9.13 Fourier components computed by SPICE3 for the mixer circuit. the reference power is calculated for an input amplitude Vlo = 100 m V Pre! = :i~Rl = "2 1 1( 4.0029233 0.83) where with 8m = 4.491 78.4975 168.00102807 0.84. .000225968 0.84 X 102 mho as computed by SPICE in Figure 8.176 18. It is important to provide the correct information in the • DISTO statement.163 10.117759 Spice 5 > quit Spice3d2 done Figure 8.06029 100. THO: 11.000356766 0.00026973 0. Harmonics: 12.6825 174.00222051 0.0534 190.4065 71. DISTO analysis.00106594 0.00015316 0.ckt Circuit: one transistor mixer circuit Spice 2 > run Spice 3 > set nfreqs=12 Spice 4 > fourier lOOk v(3) Fourier analysis for v(3) : No.4315 90.99887 6.103 )2 15.00095327 0.14.742 158. The SPICE2 input and the results of the. The IF component is the DIM2 secondorder difference intermodulation component.8.000171327 0. DISTO analyses are listed in Figure 8.000185701 0.00140642 0.7802 %.6968 99. AC and.0016788 0. First.735 68.
121E+03 4. 530E+04 2. 000E+05 2.484E04 4.155E+03 2.388E+01 1.000E+05 1.312E+00 2.882E+01 7.000 DEG C FREQ 1.83UH . SIGNAL AND LOCAL OSCILLATOR VCC 4 0 10 *VS 2 1 0 SIN 0 75. TEMPERATURE = 27. HD2 1.MODEL Mom NPN * * * SUPPLY.218E+04 3.259E+02 1.645E+00 2.675E+03 3.lMBG ' .000E+05 9.551E+00 1.000E+05 4.563E+00 3.026E+04 2.PRINT DISTO DIM2 SIM2 HD2 HD3 DIM3 .?44NF .906E+02 3. 1.103E+02 1. 275 .502E+02.986E+01 1. 27.040E+01 3.01 :AC LIN 11 'lOOK 1.618E+00 4. 281E+03 1.14 distortion analysis results for mixer.000 DEG C **** INPUT LISTING *********************************************************************** Q1 3 2 0 MODI R1 3 4 15K C1 3 4 4.PRINT AC VM(3) . 609E02 2.OPTIONS RELTOL=lE4 ITL5=0 .891E01 1.END ACANALYSIS **** .589E+04 3.976E+00 4.647E03 '5'.803E+02 6.268E01 1.78 100MV 1.256E+02 9.000E+05 5.000E+05 9.931E+02 3. 507E+02 3.778E03 5.6 3/15/83 ********18:44~38***** ONE TRANSISTOR MIXER CIRCUIT TEMPERATURE = 27. L1 34 '596.209E+01 6.100E+06 HD3 5.WIDTH OUT=80 .000E+05 2.019E+01 2.317E+01 4.000E+05 1.386E+00 .249E+03 Figure 8.779E+00 3.90909 175M .DISTO R1 0 .700E+02 1.361E+03 1.914E+04 DIM3 2. 303E+02 1.000E+06 1.000E+05 8.000E+05 4.000E+05 5.676E+03 Smallsignal FREQ 1.099E+04 1.753E+02 2.000E+05 3.733E+00 3.100E+06 **** VM(3) 7.897E+02 2.1MEG AC 1 * .000E+05 3.837E+00 3.000E+06 1.802E+00 4.000E+05 7.041E+00 1. 691E+03 2. 6.895E+01 8.399E+03 7.707E+01 6.000E+05 6.109E+00 2.*******12/13/90 ******** SPICE 2G.303E+00 2.000E+05 7.255E+02 '1.832E+00 '1.000E+05. 841E+01 1.887E01 9.093E+02 = .885E+00 2.000 DEG C AC ANALYSIS DIM2 4.149E+00 3.424E05 3.5UV 1MEG VLO 2 5 SIN 0.000E+05 8.663E+00 TEMPERATURE SIM2 3.447E+00 1.
34: (8. the amplitude Vs is .1 MHz it is found in the AC ANALYSIS listing for VM ( 3) equal to 1.73. FOUR lines. First. and Van is the normalized voltage amplitude at the output: (8. and 8. Via. and at 1. which can be applied with any SPICE program.1 = 8. the •AC and • DISTO lines replace the • TRAN and. 8. 8.5 (8. The following changes must be made to the SPICE2 input used by the previous analyses (see Figure 8. SPICE2 computes DIM2 according to (8.14. .8). see the INPUT LISTING in Figure 8. 8.80. 103 1. is commented out. It is advantageous to use the • DISTO analysis whenever the circuit behaves linearly because the • DISTO and •AC analyses are much faster than the • TRAN and • FOUR analyses. The results obtained using • DISTO are correct for this example because the only distortion of the signal is due to the transistor nonlinearities.87) which is the same as the result obtained from largesignal Fourier analysis and hand calculations.4 SUMMARY This chapter has described in detail how to evaluate distortion in electronic circuits using both smallsignal AC and largesignal Fourier analysis in SPICE.68x 103. since only one AC source. a2 is the secondorder coefficient in the power series.66 . From Eqs.23 and Eqs. is needed to run the AC analysis.4 Via 72. the input signal source. 8.86) The value of DIM2 computed by SPICE2 is 3. Second.66. a2 can be evaluated by solving equations similar to Eqs.1 MHz.909 Wla. Vi.84 the ratio of the IF to the LO signal at the output can be derived: a2 ViaVs a] = DIM2a] Via = Van 3. regardless of whether the program supports smallsignal distortion analysis.01 Via and the frequency Ws is 0. The purpose has been to familiarize the user with the methodology of evaluating distortion. 0.276 8 DISTORTION ANALYSIS For the • DISTO specification the radio signal S is defined with respect to the LO signal.84) where a] is the gain.85) The gain a] is frequencydependent.68. 8.32 through 8. The ratio Vail /Vala can be obtained from the value of DIM2 computed by SPICE at 1.
H. and A. S. D.. The summary option of . and K. that is. DISTO was exercised in SPICE2 and the meanings of all the results were explained. B. O. 1967. In Nonlinear Analog Circuits EECS 240 Class Notes. J. 1992 (April). Univ. 5 have been presented here. R. Integrated Circuits for Communication. 1979. Commonly used distortion measures were related to the results obtained from SPICE2 for a singletransistor amplifier. of California. 1973. Eschenbach. 1972. Mayaram. S. SPICE3 Version 3f User's Manual. DISTO analysis over the. of Electrical Engineering and Computer Science. Efficient computer simulation of distortion in Electronic circuits. Special consideration must be given to the accuracy of the • FOUR analysis. The relationship between smallsignal and largesignal analysis results was exemplified for a singletransistor mixer.O. . Cross modulation and intermodulation in amplifiers at high frequencies. SangiovanniVincentelli. A. Quarles. R. and R. G.. Boston: Kluwer Academic. Berkeley: Dept. to the number of time points computed by the simulator during the last period of the signal. Frequencydependent elements were included in the general derivation of the spectral component calculation.. of California. This example also pointed to the advantages of the smallsignal. Meyer. In the second part of the chapter largesignal timedomain analysis and • FOUR analysis were applied to evaluate the same distortion measures derived with smallsignal analysis. of Electrical Engineering and Computer Science. IEEE Journal of SolidState Circuits SC7 (February). Narayanan. W. Bell System Technical Journal (MayJune). D. Newton. Berkeley: Dept. Transistor distortion analysis using Volterra series representation. R. 1990. REFERENCES Chisholm. The Fourier components computed by SPICE correspond to the distortion components of the same order. Univ. Meyer. FOUR analysis for circuits with two nearly linear input signals.. M. IEEE Transactions on Circuit Theory (November). Distortion analysis of solidstate circuits. and L. T. G. Shensa.REFERENCES 277 All the capabilities of the smallsignal • DISTO analysis of SPICE2 introduced in Chap. Johnson. Nagel. Pederson. Pederson.
3.2 and 9. 278 . The iterative process is represented by the inner loop in Figure 9. The solution starts with an initial guess of the operating point. 9. The timedomain solution. respectively. The timedomain analysis is replaced by a sequence of quasistatic solutions. 9.Nine SPICE ALGORITHMS AND OPTIONS . The various types of BCEs for electrical elements were described in Chaps. uses numerical integration to transform the set of ODEs into a set of nonlinear equations. Generally the program first solves for a stable DC operating point. with nonlinear BCEs. 4 and 6. respectively. 2 and 3. The solution process implemented in SPICE for the timedomain solution is shown in Figure 9. which must be solved in the time domain. The iterative process is repeated for every time point at which the circuit equations are solved in transient analysis. The solution the iterative process converges to represents either the smallsignal bias solution (SSBS) or the initial transient solution (ITS). The most general equations have been shown to be ordinary differential equations. see Chaps. The algorithms used in SPICE for the DC solutions of linear and nonlinear circuits are presented in Secs. These techniques are described in Sec. which is represented as the outer loop in Figure 9.4. 9. which is followed by iterations for solving the DC nonlinear equations. ODE.1 OVERVIEW OF ALGORITHMS A number of algorithms have proven well suited for the solution of the equations of electrical circuits and are implemented not only in SPICE simulators but in most circuit simulators in existence today.1.1. This is the time zero solution.1.
1 SPICEsolutionalgorithm. linearization of these through a modified NewtonRaphson iterative algorithm. and their derivatives.OVERVIEW OF ALGORITHMS 279 Initial trial operating point Linearize semiconductor device around trial operating point Discretize differential equations in time Load linear conductances in circuit matrix Define new trial operating point Solve linear equations No Convergence? Yes Increment time No End of time interval? Yes Stop Figure 9. an implicit numerical integration method that transforms the nonlinear differential equations into nonlinear algebraic equations. The choice of algorithms and tolerances is based on a large set of examples. SPICE should not be treated as a black box that always provides the right answer to no matter what circuit. SPICE3. Simulators using these techniques. These algorithms are described in detail by McCalla (1988) and Nagel (1975) and in overview papers. are known as thirdgeneration circuit simulators. such as those by McCalla and Pederson (1971) and Hachtel and SangiovanniVincentelli (1981). The solution approach implemented in these simulators is also referred to as direct methods. which enable the user to select among several numerical methods and analysis tolerances. A circuit simulator is defined by the following sequence of specific algorithms. . such as SPICE2. and finally Gaussian elimination and sparse matrix techniques that solve the linear equations. An important characteristic of SPICE is the analysis options.
Two important issues are detailed there: the reordering of equations for accuracy and sparsity and the SPICE options available to the user for controlling the linear solution process. to VI. The analysis options introduced throughout this chapter are summarized at the end.2.2 DC SOLUTION OF LINEAR CIRCUITS This section describes the circuit equation formulation as well as the solution algorithms for linear systems. Namel. The general form of the option statement is . and iteration limits can be found in most versions. 9. its sparsity.2. or a number.. vall..2... An important characteristic of the circuit admittance matrix.1 the DC solution of the bridgeT circuit (Figure 1. the LV factorization. The option is followed either by a name. 9.280 9 SPICE ALGORITHMS AND OPTIONS and the majority of the circuits run well using the default settings. Thus only two nodal equations in two unknowns must be solved.. A good understanding of this chapter is important for overcoming the analysis failures commonly referred to as convergence problems. The most important options control the solution algorithms and tolerances and are introduced in this chapter. and the AC equations use complex numbers. In the evaluation of the node voltages. VB/AS. The linearequation solution algorithms described here are used for the DC solution of linear circuits and for the the AC solution. This chapter is intended to relate the analysis options accessible to the user with the solution algorithms. . OPTl. The matrix formulation for connectivity and nodal equations in SPICE is presented in Sec. was assigned. .1 Circuit Equation Formulation: Modified Nodal Equations In Example 1. Name2.1 together with the solution algorithm. Gaussian elimination and the associated factorization into lower triangular and upper triangular matrices. are implemented in SPICE for the solution of a linear system of simultaneous equations. OPT2. which always involves linear circuits. The DC equations are formulated with real numbers. Paul 1989). are options recognized by the SPICE program.. OPTIONS OPTl=Namel/vall <OPT2=Name2/val2> . Nilsson 1990. An extended version of nodal analysis (Dort 1989. 1. the voltage at node 1.1) is derived from the nodal equations written for each node.. These pitfalls are detailed in Sec. by inspection. is used in SPICE to represent the circuit.. 9. val2. Eqs. .2.1 . the value of the grounded voltage source. Certain characteristics of the MNA formulation and Gaussian elimination associated with computer limitations of the representation of real numbers can lead to a loss of accuracy and a wrong solution. 9. tolerances. and its impact on the analysis is also described in this section. called modified nodal analysis (MNA). but the fundamental options for algorithms. Each version of SPICE has a few options that differ from the ones in SPICE2.
and Brennan 1975). One problem in formulating the conductance matrix. and I is the righthandside (RHS) current vector. Ho. V2 +(G3 G3 .1) Eq. VA.2 are reproduced here: node2: node3: GI .2.2 Modified bridgeT circuit. and its current is unknown. This approach. VI +(GI + G2 + G3)V2 G4 . which contains an additional voltage source.2) where G is the conductance matrix of the circuit. 9. The problem is exemplified by the modified bridge.DC SOLUTION OF LINEAR CIRCUITS 281 and 1. This problem led the developers of SPICE to extend the set of nodal equations to include voltagesource equations represented by currents in the unknown vector and by voltages in the RHS vector. is that a voltage source cannot easily be included in the set of nodal equations: the conductance of an ideal voltage source is infinite.T circuit shown in Figure 9. 0 R4 + 14 VA 0 R3 VB CD R2 Figure 9. in series with R4. G. is therefore an extension of nodal analysis in that the node voltage equations are augmented by current equations for the voltagedefined elements (Nagel and Rohrer 1971. is easily set up by adding all conductances incident into a node to each diagonal term and subtracting the conductances connecting two nodes from the corresponding offdiagonal terms. A voltage source connected between two circuit nodes complicates this issue even more and raises the need for a consistent formulation suited for programming. Representation by matrices and vectors is well suited for programming and therefore is the methodology of choice in SPICE. . G.1 can be expressed as a matrix equation: GV = I (9. modified nodal analysis. Ruehli. The conductance matrix. V3 + G4)V3 = 0 = 0 (9. VI G3 . V is the unknown node voltage vector.
3) +G4V4 +/4 =0 = VB = VA 0 G3 G3 G4: 1 0 G4 1 0 0 0 0 0 1 :0 G4 :0 0 1 0 0 :0 I 0 0 1 1 VI V2 V3 V4 II 14 0 0 0 0 VB VA (9. So far the discussion has treated only voltage sources as being difficult to include into a set of nodal equations. also .2. because it is a short in DC. and therefore the voltage across it is zero and the conductance is infinite. The inductor is also a voltagedefined element in SPICE and is included as a current equation in the MNA formulation. which is a transconductance.4) ~0 :0 :0 0 0 The above MNA equations can be rewritten in abbreviated form: where C and E are the vectors of the current and voltage sources. The total number of equations. and nz is the number of inductors.282 9 SPICE ALGORITHMS AND OPTIONS The complete set of equations can now be written for the bridge. N. Note that all controlled sources except the voltagecontrolled current source (VCCS). respectively. including the voltage sources: node 1: node 2: node 3: node 4: VB: VA: In partitioned matrix form the equations become GJ +G4 GJ GI GI + G2 + G3 G3 G4VI" VI V3 +V4 (GI + G4)VI GIVI GIV2 +(GI + G2 + G3)V2 G3V2 G3V3 +G3 V3 /4 G4V4 +II =0 =0 =0 (9. nv is the number of independent voltage sources. used to represent a circuit in SPICE is (9. Another circuit element that presents the same problem is the inductor.5) where n is the number of circuit nodes excluding ground.T circuit in Figure 9.
The solution can then be found by computing each element of vector x in reverse order (the backsubstitution phase). Eq. The Gaussian elimination procedure uses scaling of each equation followed by subtraction from the remaining equations in order to eliminate unknowns one by one until A is reduced to an upper triangular matrix. a(O) 21 a(O) 31 a(O) 12 a(O) 22 a(O) 32 (9.8) Second. First. (O). X2 is eliminated from e~l) by subtracting ei1) multiplied by aWl aW from e~1): (9. both in the equation designators and the matrix elements. represent the step of the elimination process. The equations are designated by e\O). For complete details on the MNA matrix representation of different elements consult McCalla's book (1988).. and Gaussian elimination (Forsythe and Moler 1967) is preferred for numerical solutions. For a 3 X 3 system of linear equations.9) . XI can be eliminated from e(O) and e(O) by subtracting e(O) multiplied by a(O)/a(O) from /0) and subtracting e(O) 2 3 I 21 11 2 I multiplied by a(O)/a(O) from / 3 J.4. e(O) .7) the steps leading to the solution are outlined as follows. can be expressed as a matrix equation: Ax = b (9. and e~O). 9. can be computed by inverting matrix A. This approach is very timeconsuming. [ a(O) I. 11 (O). e 2.6) The solution vector. x. 31 11 ° e(l) I e(l) 2 e(l) 3 . e 3.DC SOLUTION OF LINEAR CIRCUITS 283 introduce current equations.e(O) I /0) _ (a(O)/a(O))/O) 2 21 11 I e(O) 3 (a(O)/a(O))e(O) 31 11 I (9. eiO). The superscripts. The MNA set of equations that needs to be solved.
r 11 a(O) 12 a(O) a(l) 22 13 a(O) a(l) 23 a(2) 33 [ XI ] X2 X3 = r I b(O) b(l) 2 b(2) 3 1 (9. backsubstitution leads to the following solution: (9. e(2). which for the thirdorder (9.15) Note that inverting Land U is trivial because they are triangular. Equation 9. L. 3 .11) A variant of Gaussian elimination is LV factorization. e(2) .6 can be rewritten as LUx = b The first step of the method is to factorize A into Land system become (9. which results in a new RHS: (9. x: (9. and an upper.12) U.10) 0 0 0 Third. which computes the elements of the unknown vector.284 9 SPICE ALGORITHMS AND OPTIONS which yields an upper triangular equation system: I' e(2) . 2 .14) The last step is backsubstitution.13) where U is the result of Gaussian elimination and L stores the scale factors at each elimination step. The second phase of the solution is the forward substitution. The advantage of LU factorization over Gaussian elimination is that the circuit can be solved repeatedly for . triangular matrix. U. This procedure transforms the circuit matrix A into a lower.
4. has 20 zero elements of a total of 36 elements in the matrix. This additional topological reordering scheme is. could not correct this problem. Yang. in other words the conductance matrix is sparse. which used only topological reordering. In the conductance matrix of a circuit having a few tens of nodes. Earlier versions of SPICE2. 9. differs from the above number because SPICE includes the ground node in the computation. The simple explanation of this is that offdiagonal terms are generated by conductances connected between pairs of nodes. The sparsity of the matrix can be defined as number of elements equal to zero total number of elements in matrix sparsity =  (9. The zeroelement count in SPICE is taken after reordering. and Trick 1981) that finds an equation sequence free of topological problems. up to version F. and Brennan 1975). An important observation about the conductance matrix G (Eq.4). 9. A second problem. not necessary once the numerical reordering known as pivoting is used. The voltagedefined elements. raising the total number of elements to 49.6% in this example. only two or three out of a few tens of offdiagonal terms are nonzero. This problem can be corrected in the setup phase based on a topological reordering.16) The sparsity is 55.2 Accuracy and SPICE Options Accuracy problems in the solution of a linear circuit can be classified as either topological or numerical. In SPICE the row in the MNA matrix corresponding to the current equation of a voltage source is swapped with the node voltage equation corresponding to the positive terminal of the same voltage source (Cohen 1981). and distortion analyses. however. The MNA matrix of the bridgeT circuit. . where many diagonal elements are also zero. 9. such as sensitivity. generate zero diagonal elements linked to the current equation (Ho. The sparsity is maintained in the currentequation submatrix R (Eq. option ACCT (Sec. which can be exploited for reducing data storage and computation. A reordering algorithm has been proposed (Hajj. is a cut set of voltagedefined elements. This property is useful in certain SPICE analyses. Eq. such as voltage sources and inductors. This issue is addressed in the following section on accuracy. 9.4) is that it is diagonally dominant and many offdiagonal terms are zero. Sparsity is a very useful feature.2.DC SOLUTION OF LINEAR CIRCUITS 285 different excitation vectors. All SPICE2 version G releases use pivoting in the sparse matrix solution (Boyle 1978. different righthand sides. noise. which is also topological in nature. also referred to as preordering. that is. Vladimirescu 1978). The number obtained from SPICE for the sparsity of this circuit in the accounting summary.5). This leads to a cancellation of a diagonal element value during the factorization process. 9. The next section explains the need for careful reordering of the equations for maintaining accuracy and sparsity at the same time. and usually a node is connected to only two or three neighboring nodes. Ruehli.
This example shows the need of a reordering scheme based on the matrix entries at each step of the LV decomposition.286 9 SPICEALGORITHMS AND OPTIONS A circuit that cannot be solved only through preordering The MNA matrix of the circuit is is shown in Figure 9. described below.17) After preordering. the circuit matrix becomes 1 1/2 0 0 0 1 0 0 0 0 0 0 0 0 1/5 1/5 0 0 1/5 1/5 0 0 0 0 0 1/2 0 0 1/2 0 1 1 0 '1 1/2 1 Matrix equations 3 and 4 form a diagonal block [ G] G] G] ] G] where G] = during the LV factorization a zero is created on the diagonal at row 4. and reordering to maintain sparsity. !. G) R1 CD 50 • L1 1H 0 R2 0 Iv ~ 20 IL t 3V VA Figure 9. 1/5 1/5 0 0 0 0 1/5 1/5 0 0 0 0 0 0 0 1 0 1/2 1/2 1 0 1/2 1/2 0 1 1 0 0 0 0 0 0 1 0 0 V] V2 V3 V4 h I 1 Iv 0 0 0 0 3 (9.3 Circuit exemplifying diagonal cancellation. which swaps row h with node 2 and row Iv with node 4.  .3.
000 a zero is created on the values of infinity for VI computer and cannot be is singular. can be caused by the circuit in Figure due to the fourdigit limitation. [1] The hypothetical computer in this case.19) 1Q 10 kQ Figure 9. It is easy to imagine that having a switch element (see Chap. The simple circuit (Freret 1976) shown in Figure 9. in IEEE floatingpoint format. however. can lead to the loss of significance of a matrix term relative to another during the solution of the linear equations. rounds off element Qzz to (9. of digits.4 Circuit exemplifying limited floatingpoint range. Another problem is that computers only have finite precision. The limit of the number of digits in the mantissa of a floatingpoint number. The equations of the circuit are 1 1] V 0 [ 1 1.gl VI + gz Vz = I + Gz Vz = 0 (9. The conductance matrix of the circuit Another accuracy problem.5.DC SOLUTION OF LINEAR CIRCUITS 287 Not all problems associated with the solution of theMNA matrix are topological. 12 orders of magnitude. diagonal during Gaussian'elimination. This problem is due to the insufficient accuracy of the corrected by reordering. up to 15 decimal digits for a doubleprecision. resulting in erroneous and Vz.4 demonstrates this point.S Circuit exemplifying rounding error.0001 [VI]z . 2) A circuit can have resistors with a range from i mn to 1 Gn. This case is exemplified 9. real number. also due to the limited number by the Gaussian elimination process. The nodal equations for this circuit are GI VI . Figure 9. It is assumed that the computer can represent only four digits of floating~point accuracy. As in the previous example. Or 64bit. . that is..18) a22 = GI + Gz = 1. however.
288 9 SPICE ALGORITHMS AND OPTIONS Substitution of the values of the conductances.9999 VI = 0. GI and G2.9999 V2 This type of accuracy loss can also be observed in the case of a series of highgain stages conne. the system of equations becomes with the more realistic solution The accuracy of this solution is still affected by the limited number of digits. The exact solution is = 0.6. which grow as a powerlaw function of the gain factors during factorization and can eventually swamp out the diagonal term. A ring oscillator similar to that in Figure 6.cted in a feedback loop. Replacement of the transistors with a linearized model during each iteration. as . for the available number representation. the solution is correct. If the rows of the equation are swapped before factorization in order to bring the largest element onto the diagonal. the offdiagonal elements are transconductances.9 but implemented with bipolar transistors is shown in Figure 9. and the transconductances. however. such as a ring oscillator. gl and g2. yields the following system of equations: After one elimination step the system becomes with the following solution on a computer with fourdigit accuracy: which is obviously incorrect.
with the ratio between the largest value in the remainder matrix and the largest value in the initial matrix being of more orders of magnitude than can be represented by the computer. because the selfconductance of each node. A parameter. and Ieq = 2.6 BJT ring oscillator exemplifying rounding error. is used in SPICE that defines the lowest threshold for accepting an element as a diagonal element. Another numerical problem occurs when the matrix entries at a certain step of the elimination process become very small.20) [Ieql] o + g1T1 V3 The solutions of the node voltages. and V3. PIVTOL. should be identical. leads to the following system of equations: G [ + g1T2 gm2 0 G + g1T3 gm3 gml o G ][VI]V 2 = Ieq2 Ieq3 (9. V2. Carry out the Gaussian elimination steps to find the solution for VI. described in Sec.3. but they differ if the above system is solved as is. V2. Exercise Assume that gm = 3. g1T = 3.607 X 102 mho. PIVTOL = 1013. loses its contribution during the elimination process. VI. or a pivot. The default for this parameter. If an element larger than this value is not found in the remainder matrix at any step.607 X 104 mho.192 X 102 A. then the matrix is declared singular and SPICE aborts the analysis.DC SOLUTION OF LINEAR CIRCUITS 289 R R 10 kn 10 kn t I Figure 9. 9. and V3 with fourdigit accuracy. or diagonal term. was chosen under the assumption that for typical circuits the maximum conductance is 1 mho and that. at least 13 digits of accuracy are used by computers to store the matrix . R = 10 kO.
Pivoting is performed on the diagonal elements. if no pivot can be found on the diagonal the rest of the submatrix is searched. or a full pivoting strategy. the largest element is found in the remainder matrix. The second constraint mentioned in the previous section is preservation of the sparsity of the matrix. the one that introduces the fewest jillin terms. among a number of acceptable pivots. Fillins are the matrix terms that are zero at the beginning of the factorization process and become nonzero during LV decomposition. An increase of PIVREL forces a better . because of the accumulation of rounding error in the solution process. and then the diagonal element with the best Markowitz number is checked as to whether it satisfies the following magnitude test: aii ::::: PIVREL.290 9 SPICE ALGORITHMS AND OPTIONS entries. The numerical reordering is based on two criteria: partial pivoting for accuracy and the Markowitz algorithm for minimum fillin. the best element to be picked as the next pivot is the one that has the minimum number of offdiagonal entries in the row and column as measured by m = (r . very high ratios of conductance values. which selects the largest element in the remainder of the matrix. Therefore SPICE accepts as pivot the element that introduces the fewest fillins as long as it is not PIVREL orders of magnitude smaller than the largest element at that elimination step. is essential for an accurate solution to a set of equations if the original values can be altered significantly by the factorization process. the more important pivoting becomes. which defaults to 103. The larger the circuit. In SPICE2 the topological aspects are considered in the setup phase when the sparsematrix pointers are defined. Sometimes it is even necessary to reorder during the iterative process. which picks the largest element in the column or row. A detailed presentation of numerical accuracy issues can also be found in the thesis by Cohen (1981). and so on. The Markowitz algorithm is used in SPICE to select.1)(c  1) (9. Note that SPICE lists the value of the largest element in the remainder matrix in the *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP number value IS LESS THAN PIVTOL message (see Appendix B for error messages). but the user must doublecheck the circuit for possible highimpedance nodes. First. aiMax (9. Reordering is performed at the very first iteration after the actual MNA values have been loaded. called pivoting. respectively. As part of numerical reordering. If this value is nonzero. According to the Markowitz algorithm. can be chosen. The solution obtained afterward can be correct.21) where rand c are the numbers of nonzero entries of a row and a column. a partial pivoting strategy. The selection of a pivot in SPICE proceeds as follows. Reordering based on selecting the largest element for the diagonal.22) where aiMax is the maximum entry at the ith elimination step and PIVREL is a SPICE option parameter. The above examples demonstrate that a topological reordering is not sufficient and that the order of the MNA sparse matrix has to be based on actual values generated by the circuit as well. PIVTOL can be reset using the • OPTION statement to accommodate it.
shown in Figure 9.7a. PIVREL is the other option parameter that a user can modify if SPICE aborts because of singular matrix problems.3. until the solutions of two consecutive iterations are the same. one should carefully check the circuit first. one conductance. lD = Is(ev/Vth GV  1) (9.1 NewtonRaphson Iteration The NewtonRaphson algorithm for the solution of the equations of nonlinear circuits is introduced with the simple circuit consisting of one diode. In order to modify one or both linear equation option parameters. Controlled sources can also be described by nonlinear BCEs that are limited to polynomials in SPICE2 but can be any arbitrary function in SPICE3 and other commercial versions. The iterative solution process continues until the values of the unknown voltages and currents converge. two option parameters control the linear equation solution in SPICE. 9. In summary.23b) IG = . If the largest entry is zero.DC SOLUTION OF NONLINEAR CIRCUITS 291 conditioned matrix at the expense of introducing fillin terms. or in other words. This algorithm is described in Sec. The modified nodal equations for a circuit with transistors are a set of nonlinear simultaneous equations. and one current source. In this case pivoting on the fly is performed for the remainder of the matrix.3 DC SOLUTION OF NONLINEAR CIRCUITS In Chap.1. lA.2. G. 3 semiconductor devices were shown to be described by nonlinear IV characteristics that are exponential or quadratic functions. The graphical representation ofthe BCEs for the two elements. 9. PIVREL and PIVTOL. or skip the DC solution and run a transient analysis with the Ule flag on. Once an optimal order has been found.1 for the DC solution of nonlinear equations is implemented in SPICE using the NewtonRaphson algorithm.3. 9. it is used throughout the analysis unless at some point a diagonal element is less than PIVTOL. possibly leading to a wellconditioned matrix.3. try increasing PIVREL. 9. The user is not advised to modify these parameters unless SPICE cannot find a solution because of a singular matrix problem.23a) (9. The criteria for convergence and the options available to the user to control convergence are presented in Sec. The iterative loop marked in Figure 9. The timedomain admittance matrix adds the contributions of the charge storage elements. one adds the following line to the SPICE input file: • OPTIONS PIVTOL=valuel PIVREL=value2 PlVTOL should be reset to a smaller value than the maximum entry listed in the SPICE message as long as the value is nonzero.
with new values for GD and IDN at each iteration (i + 1).25 represents the linearized BCE of the diode around a trial operating point. 9.25 is substituted into Eq.26 is solved repeatedly. which must satisfy Kirchhoff's current law. VDo: ID = IDo + dV ~I (VD .7 ~ Diode circuit: (a) circuit diagram.24) Nonlinear equations of this type are generally solved through an iterative approach. is shown in Figure 9. (9. which are based on the voltage at the previous iteration .26) The solution of the above equation is VDl.VDO) = IDo + GDO(VD  VDO) = IDNo + GDOVD D Voo ' (9. The current ID in Eq.24. which becomes the new trial operating point for the diode. 9. also known as the tangent method (Ortega and Rheinholdt 1970).25) where only the firstorder term is considered. such as Newton's method. the nodal equation for this circuit becomes (G + GDo)V = IA  IDNo (9. Equation 9. Equation 9.The diode can therefore be represented by a companion model.292 9 SPICE ALGORITHMS AND OPTIONS + v ~ Figure 9. or operating point. The new circuit and the graphical representation of the linearized BCE of the diode are shown in Figure 9. the solution VD is located at the intersection of the two functions ID and IG. VDO. 9. (b) graphical solution.8.23a can be approximated by a Taylor series expansion around a trial solution. a Norton equivalent with current IDNo and conductance Goo.7 b. or iteratively. After Eq.
I I I I IDN I v L I I I I .25. called the Jacobian.9.9. (b) graphical solution. These values form the conductance contribution of the nonlinear BeEs to the MNA of the circuit.28) where for tpe diode equation g(x) and at the solution X.. according to Eq.8 Linearized companion model of the diode circuit: (a) circuit diagram. The general Newton iteration applied to a nonlinear function g(x) of a single variable is (9. = ID(V) = Is(ev/Vth .27) which represents for this simple case the Newton iteration. Intersection of the linearized diode'conductance with the load line G define the values VDi at successive iterations.1) Ig+ 1) = Ig).I ~ ~ Figure9. For an arbitrary circuit the set of all nonlinear equations is replaced at each iteration by the following set of linear equations: (9.DC SOLUTION OF NONLINEAR CIRCUITS 293 r. V. J. The graphical representatiqn of the iterative process for this circuit is given in Figure 9.nonlinear equations g(x) = 0 consists in computing the partial derivatives with respect to the controlling voltages. This process converges to the solution.29) . The generalized linearization approach for a set of.. (i). The iterative process is described by the nodal equation (9.
31. As exemplified by the diode characteristic in Figure 9. 9.28. This algorithm is known as a limiting algorithm and determines .g(x(i») (9. respectively. sources in the circuit. At each iteration the circuit is described as a linear system. and 9. G and C.6. 9.31 includes the contributions of the linear elements and independent current .1. An algorithm that controls the changes in the state variables of the nonlinear elements from iteration to iteration is very important if the simulated circuit is to converge to the correct solution.8.9 Newton iteration for the diode circuit. which is solved using the LU factorization described in Sec. x(i) . The nonlinear IV characteristics of semiconductor devices are exponential or quadratic functions. where J(x(i») is the Jacobian computed with xU). 9. 9.294 9 SPICEALGORITHMS AND OPTIONS v Figure 9. An important question is whether the above equations converge to a solution and how many iterations it takes. the iterative scheme can fail to converge. Eqs. With the limited range of floatingpoint numbers available on a computer and the unboundedness of solutions provided by the Newton algorithm according to Eq. the solution at the previous iteration.30.31) Equation 9.2. the equivalent conductance can vary from 0 in the reverse region to infinity in the forward bias region.30) = J(x(i») . The conductance matrix A and RHS b for a nonlinear circuit have the following matrix representation: A b = J(x(i») +G +C (9.
I. 9.10 limiting. The scheme proposed by Colon is successfully used in SPICE and its derivatives to limit the new junction voltage on diodes and BITs. At each iteration the new solution of the junction voltage. VI.DC SOLUTION OF NONLINEAR CIRCUITS 295 the convergence features of the simulator.. If VI is smaller than Va. V. Equation 9. Va. VI. limits it by correcting the new value of the Newton iteration (Calahan 1972) from Eq.28 to the following: (9. based on the last linearization of the diode characteristic. A practical implementation of the above modified NewtonRaphson iteration. 9. This parameter assumes a different value at each iteration and for each device. NewtonRaphson iteration with current . if larger than the previous value. which is tailored to the different nonlinear characteristics of each semiconductor device. is used to derive a new current. becomes the new trial operating point for the diode in the current iteration. when large changes in the value of the nonlinear function would occur. v Figure 9.32 defines the NewtonRaphson iterative algorithm.10. it is accepted directly I. which is smaller than the original solution. is shown in Figure 9.32. Eq. A limiting algorithm selectively accepts the solution unchanged or. The voltage corresponding to on the nonlinear diode characteristic is V.. The choice of ex is implemented through the limiting algorithm.32) The parameter ex(O < ex ::s 1) indicates that only a fraction of the change is accepted at each iteration.
Yo in Figure 9. the iterative process is finished when the following two conditions are met: 1. to prevent zerovalued conductances from being loaded into the circuit admittance matrix when these junctions are reverse biased. The default values are set to RELTOL YNTOL = 103 = 1 J. is formed from a relati ve term and an absolute term.3. The values of the nonlinear functions and those of the linear approximations are within a prescribed tolerance. 9. Therefore.296 9 SPICE ALGORITHMS AND OPTIONS as the new trial operating point because there is no danger of a runaway solution. which cannot be corrected in subsequent iterations. An additional protection built into SPICE is a parallel minimum conductance. and the process fails to converge. SPICE2 initializes the semiconductor devices in a starting operating point such that nonzero conductances can be loaded into the MNA circuit matrix at the first iteration. Each tolerance. connected in parallel to every pn junction.32 defines the NewtonRaphson iteration. such as BE and BC for BITs and BD and BS for MOSFETs.10. GMIN. The NewtonRaphson algorithm has quadratic convergence properties if the initial guess. The voltage tolerance for node n. EVn. it is important in a circuit simulator to provide an initial guess as a set either of node voltages or of terminal voltages for the nonlinear semiconductor devices. is close to the solution. Equation 9. respectively.L V .33) The values of node voltages at two consecutive iterations have to satisfy the following inequality for convergence: !y(i+1) n  y(i)l n :=. with a default value of 1012 mho. All the voltages and currents of the unknown vector are within a prescribed tolerance for two consecutive iterations. Circuit simulators start out usually with all unknowns set to zero.2 Convergence and SPICE Options This section addresses the issues of how and when convergence is achieved. the tolerances used in SPICE to establish convergence are introduced. 2. for voltage or current variables. E Vn (9. is defined as (9.34) RELTOL and VNTOL are SPICE option parameters representing the relative and the absolute voltage tolerance. Next. The danger in the absence of any limiting is that a trial solution can generate very large values of the exponential function.
voltages are accurate to 1 part in 1000 down to 1 /LV of resolution. ITIA defaults to 10.37. ID) + ABSTOL (9.IDI :5 Ej (9. For each time point only ITL4 iterations are allowed before a failure of convergence is decreed. This means that a node with 100 V is accurate to 100 m V and a voltage of 10 /LV is accurate to only 1 /Lv.36) and the iteration process converges when liD . When SPICE computes DC transfer curves. with the SPICE defaults.34. for example. In the following derivation the nonlinear function will be referred to for simplicity as a current. evaluated for the last junction voltage solution vji) and the linear approximation iD. Convergence failure can also occur during a transient analysis. In the case of semiconductor devices. If the inequalities ofEqs. SPICE2 prints the message * ERROR*: NO CONVERGENCE IN DC ANALYSIS and the last node voltages. ID.DC SOLUTION OF NONLINEAR CIRCUITS 297 The absolute tolerance defines the minimum value for which a given variable is still accurate. 9. ID for a diode. as the test for convergence: ID ID The tolerance is defined as El A = = GDVJ (i+1)  IDN  Is (evji)/vth 1) (9. The advantage of subsequent analyses is that the unknown vector is initialized with the values from the last point. which consists of quasistatic iterative solutions at a discrete set of time points. whose operation is controlled by the gate voltage and for which IDs is in most applications 1 /LA and higher.38) IVJ+1)  VJ)I :5 EVJ ABSTOL is the absolute current tolerance and defaults to 1012 A in SPICE2 and SPICE3. max (iD. such as FETs. There is a limit to the number of iterations computed by SPICE. VY+I). the nonlinear functions are the currents.37) (9. which defaults to 50. In transient analysis failure to converge at a time does not result in the abortion of thf' :m::llv~i~hnt r::ln~f'~ ::lrf'ihwtion of thf' timf' ~tf'n ::l~f'xnl::linf'n in Sf'r CJ 4 . and 9. This limit is set by the option parameter ITL1. This default is very accurate for the base current of BITs but may be too restrictive for other devices. Convergence is based not only on the circuit variables but also on the values of the nonlinear functions that define the BCEs of the nonlinear elements. which defaults to 100. Ie and IB for a BIT. and IDs for all FETs. using the present voltage solution.38 are not satisfied in ITLl iterations.35) = RELTOL . 9. SPICE defines the difference between the nonlinear expression. the number of allowed iterations is ITLl only for the first value of the sweeping variable and then is reduced to ITL2.
Source ramping can be viewed as a variation of the general modified NewtonRaphson solution algorithm. however. . thesis (1975). as shown graphically in the flowchart of Figure 9.298 9 SPICE ALGORITHMS AND OPTIONS When SPICE fails to find a DC solution.1. 9. SPICE2 does not automatically use source ramping if it fails to converge. an additional option can be used to achieve convergence. such as the ones representing the BCEs of capacitors and inductors. Option parameter ITL6 must be set to the number of iterations to be performed for each stepped value of the source. The bypass operation results for a majority of circuits in analysis time savings without affecting the end result. cases when bypass can cause nonconvergence at a later time point. a new linearized model is not computed for this device. Nagel's Ph. This is a very timeconsuming process and may not always be necessary. the accuracy of these algorithms is analyzed along with the options available to the user regarding numerical methods and error bounds. called source ramping. All ITLx options can be reset by the user. 9.OP analysis using a • DC transfer curve approach. The presentation of the numerical methods is simplified for the purpose of providing the SPICE user with insight into the workings of the program. During the solution process the linear equivalent of each nonlinear element must be evaluated. during the iterations performed at anyone time point each nonlinear element is checked for a change in the terminal voltages and the output current from the last time point. This method consists in finding the DC solution by ramping all independent voltage and current sources from zero to the actual values. although this should be rarely necessary. This check can limit the devices being bypassed by reducing the tolerances. In timedomain analysis. A more detailed presentation of convergence problems along with examples and solutions can be found in Chap.37 and 9. 9. it is bypassed. however. In other words. There are.1). The specific implementation in SPICE is described here.D. into a set of algebraic equations. 10. transient analysis is divided into a sequence of quasistatic solutions. similar to ITL2 for DC transfer curves. because it involves all the algorithms presented so far in this chapter. If the controlling variables and resulting function of a device have not changed. The check for bypassing a device is based on Eqs. SPICE3 and PSpice perform source ramping automatically when the regular iterative process fails to converge. this reduction can negatively affect the convergence test for the overall circuit. As described in the introductory overview of algorithms (Sec. This section outlines the numerical techniques used in SPICE to transform a set of differential equations.4 TIMEDOMAIN SOLUTION The timedomain solution is the most complex analysis in a circuit simulator. A detailed presentation on the situations requiring the change of these options is provided in the following chapter. This is equivalent to an . a rigorous description of the integration algorithm can be found in the book by Chua and Lin (1975) and L. the linearized conductances obtained at the previous time point are used again in the circuit matrix.38. furthermore.
vcCt). at t = 0 a voltage step of magnitude Vi is applied at the input. Find the voltage.15 Figure 9.1 Consider the series RC circuit shown in Figure 9. across the resistor and the voltage.0 1. (b) plots of solutions VR(t) and vc(t).TIMEDOMAIN SOLUTION 299 9. VR(t).5 1. (b) 1.11a. Vi (a) 'j 0. .4. across the capacitor over time.11 RC circuit: (a) circuit diagram. • EXAMPLE 9.5 Time.1 Numerical Integration The different numerical integration algorithms and their properties are best introduced with an example.
assumed equal for all time points for simplicity. can be expressed by a Taylor series expansion around Xn+! Xn: = Xn + hXn (9. 6.43) where h is the time step.et/T). Substitution of Eqs. (9.41) The solutions VR(t) and vcCt) are VR(t) vcCt) and are presented in Figure 9.300 9 SPICE ALGORITHMS AND OPTIONS Solution From the BCEs of the resistor and capacitor the following equation is obtained: (9. Xn+!. This is identical to the finitedifference approximation of the derivative of x and represents the forwardEuler (FE) integration formula. = Viet/T Vi(l . 9.2) is performed at a number of discrete time points.42) = In SPICE the solution of the above equation in the interval 0 to TSTOP (see also Sec.41 into 9.43 yields the following recursive solution for Vc at tn+!: (9. where the differential equation is replaced by an algebraic equation. let x be the time function to be solved for and Xn the values at the discrete time points tn: The solution at tn+!.39) KVL applied to the circuit allows the following substitution of Vc: vcCt) = Vi  VR(t) (9.44) .40) yielding the following differential equations for VR(t) and vcCt): (9. For simplicity.11b.
An important measure of the accuracy of a numerical integration method is the local truncation error. LTE. evaluated at each time point. Because Eq.44. because higherorder terms are neglected in the series.TIMEDOMAIN SOLUTION 301 This is represented graphically in Figure 9. The trapezoidal integration is a secondorder method that can be derived based on the observation that a more accurate solution VC(tn+ 1) can be obtained if in Eqs. 9. Based on the above definition of LTE. A rather sizeable error can be noticed for VC(tn+l) computed with Eq.13. this formula is known as an implicit method. xnl (9. whereas the FE is an explicit method.48) . The two methods introduced so far are known as firstorder methods.45 the average of the slopes at tn and tn+ 1 are used as compared to either one or the other: (9.45) This represents the backwardEuler (BE) integration formula. 9.47 with a Taylor expansion: (9. For the FE and BE methods LTE can be approximated by the first discarded term in the Taylor expansion: h2 Xn+l = Xn + hXn + TXn = Ih.43 and 9.46) LTE Algorithms for automatic timestep control such as the one used in SPICE are based on checking whether the LTE of each timedependent BCE is within prescribed bounds.47) The higher accuracy ofthis method is obvious from the graphical solution of Vc (tn + 1) shown in Figure 9. It can be seen that Vn+l as given by the BE formula is less sensitive to the size ofthe time step h than that given by the FE formula. Xn+l = Xn + hXn+l (9. The LTE of the trapezoidal integration formula can be derived by first substituting Xn+l in Eq.45 must be solved simultaneously for x as well as for its derivative. 9. 9. 9.43 xn+ 1 is expressed in terms of the derivative at tn+ 1> Xn+ 1.12a. A different solution is obtained for Vc if in Eq. it can be thought that using higherorder terms of the series in the solution of xn+ 1 can lead to smaller LTE.12b. The actual algorithm is detailed in the following section. The graphical interpretation of this solution is shown in Figure 9.
Solutions of vdt) between tn and tn+ 1: (a) FE solution.13 Trapezoidal solution of vdt) between tn and tn+l. (b) Figure 9.12 BE solution. .302 9 SPICE ALGORITHMS AND OPTIONS (a) (b) Figure 9.
Eq..2 Apply the trapezoidal integration method to the BCE of a capacitor. 9.52) formula.4 and 2. 2C( + h Vn+l : Vn ) (9. (9. from the exact solution given by the first three terms of the Taylor series: (9.54) or . . can be rewritten for a nodal interpretation: L The trapezoidal results in integration In+l idt = r Cdvc (9.47. 9.49 and then subtracting the resulting equation in xn+ 1 from Eq. = In .47.53) Equation 9.50) The LTE for n+ 1 is obtained by first substituting xn+ 1 in Eq. Use the result to develop a companion model of the capacitor to be used in nodal equations. Eq. 9.48: x (9.51) EXAMPLE 9.47 byEq.5. is applied to the above equation and .49) The resulting LTE of the trapezoidal integration method for xn+ is 1 LTE = 3 Ih12 xn .TIMEDOMAIN SOLUTION 303 and then subtracting the trapezoidal solution. 2.53 can be rewritten as a nodal equation at tn+ 1: (9. Solution The BCE of a capacitor.. 9. 9. Eqs.
h.42. Eqs. Whereas the LTE is a local measure of accuracy at each time point. The BE solution. 9.54 is updated at each time point and the contributions are loaded into the circuit matrix and RHS vector. The integration methods used to solve such systems must be stiffly stable. An interesting result is offered by the TR method. decreases to zero as does the exact solution VR(t) in Eqs. A quantitative analysis of the stability of the integration methods introduced so far can be performed for the RC circuit in Figure 9.11. can be compared with the FE. 9. and TR solutions computed after n time steps: (FE) (BE) (TR) Vi(l .h/rt Vi (1 VI (9. In SPICE Eq. these methods . stability is a global measure of how the solution computed by a given method approaches the exact solution as time proceeds to infinity. the equations representing these circuits constitute stiff systems.56) (9.304 9 SPICE ALGORITHMS AND OPTIONS + G 'q = 2C h Figure 9. BE.h/2r)n (l + h/2r)n The FE solution can be seen to lead to the wrong solution if the stepsize.55) (9. in other words. Electronic circuits have time constants that can differ by several orders of magnitude. 9.14 Companion model for a capacitor. An important property of an integration method is its stability or convergence feature. which converges toward zero but does so in an oscillatory manner if h > 2r. This behavior of the TR method can be observed in SPICE especially when the solution goes through discontinuities. Stability is also a function of the specific circuit. by contrast. The exact solution for VR(t). is greater than 2r. The companion model of the capacitor for nodal analysis is shown in Figure 9. The companion model for an inductor can be derived similarly. It is formed of the parallel combination of the equivalent conductance Geq and the equivalent current source Ieq.57) + h/r)n (l .14.42 as time increases.
1~A t 1~1 Figure 9. EXAMPLE 9. SPICE3. The TR method converges to a solution in an oscillatory manner (Eq.SPICE2 or . Additional integration formulas have been developed that fall in the general category of polynomial integration methods defined by Xn+l = 2: n i=O aiXni + i=1 2: n bixni (9. the method is explicit. BE and TR. are not. The Gear integration (Gear 1967) formulas of order 2 to 6 have proven to have good stability properties. the two have different characteristics. which leads to a damped response.a circuit can differ depending on the integration method used. if running. PSpice uses only the Gear algorithms. . the latter with a MAXORD of 2. are stiffly stable. This difference between the two methods is demonstrated by the following example. . The TR and BE integration methods are the default in the majority of SPICE versions.algorithm if i > 1. 9. SPICE3. Use both the TRAP and the GEAR options. The time~domain response of.57) when the time step is larger than a certain limit. The algorithm'is a multistep . but explicit methods.58) If b1is zero. that is. and if b1 is nonzero. .TIMEDOMAIN SOLUTION 305 must provide the correct solution without constraining the time step to the smallest time constant in the circuit. The Gear formulas of varying order for xn+ 1 are listed in Appendix D. if more than one time point from the past is needed to compute Xn+ 1. the method is implicit.15 LC circuit. such as the FE method. The Gear formula of order 2 has an opposite behavior. and compare the results. The implicit methods introduced so far. The Gear integration formulas'order 2 to 6 are implemented in SPICE2.3 Find the time response oftl1eLC circuit shown in Figure. Although in the vast majority of cases both the TR and the Gear methods lead to the same solution. and most commercial SPICE versions as an alternative to the default TR method. 9.15 assuming that at t = 0 the switch is opened.
must be taken into account by setting the appropriate initial condition for the inductor current. or 159 kHz. The inclusion of the • OPTIONS statement by removal of the asterisk at the beginning of the line leads to the solutions computation by the Gear formula. In order to start the analysis from the initial condition at the time the switch is opened. which is wrong. Trapezoidal 1V 0 1V > 1V 0 1V 50 100 150 200 Time.16 LC circuit response computed with trapezoidal and Gear 2 algorithms. the Ule keyword must be specified in the • TRAN statement. Note that the current source must not appear in the circuit description. .PWT • END 1U 400U TRAN V(l) The SPICE input is listed above.16 to be a decaying oscillation. The result of trapezoidal integration is free oscillations with an amplitude of 1 V at the resonant frequency of 106 radls. its effect. which is valid for t 2': 0. Recent versions of PSpice produce the decaying waveform.16. OPTION METHOD=GEAR MAXORD=2 0 UIC * .lls 250 300 350 Figure 9.306 9 SPICE ALGORITHMS AND OPTIONS LC CIRCUIT L1 101M C1 1 0 1N * IC=lM * * . as seen in the upper trace of Figure 9. The result is shown in the lower trace of Figure 9.TRAN . probably because the Gear 2 method is used as default. however.
Accuracy. but a user can select the Gear algorithm with the optiOhsMETHOD MAXORD. As mentioned above. A higherorder method has a smaller LTE. ' Solution .OPTIONS line to {he SPICE circuit description: . f. order methods.TIMEDOMAIN SOLUTION 307 The stability of integration methods is presentedinrriore detail in the works by McCalla (1988) and by Nagel (1975). and Options This section describes the implementation in SPICE of the integration algorithms introduced in the previous section and the options available to the user to improve the accuracy of a solution.OPTIONS METHOD=GEAR MAXORD=3 The variableorder algorithm in SPICE selects at each time point the order that allows for the maximum time step.' Second. caution must be exercjsed with higher orders because inaccuracy is introduced in the computation of the LTE and of the resulting time step. . as shown in the previous section. the equations of electronic circuits must be solved by stiffly stable integration methods for which the t~me step is determined by LTE and not by stability constraints. the LTE of a numerical method diminishes for higher.4 Change the SPICE2 default integration method to Gear and limit the order of the integration formula'to 3. Several conclusions can be drawn based on the firstorder analysis presented in this section and the more thorough analysis found in the . by contrast.2 Integration Algorithms iii SPICE. the stability deteriorates as the order of the method increases. most SPICE programs support two integration algorithms. enabling the variable time step algorithm in SPICE to select a larger time step. 9. multistep method. First.and for MAXORD a number between 2 and 6 is required.references. MAXORD limits the order of the integration formula used for the variableorder Gear method and is therefore relevant only when METHOD=GEAR.be achieved by adding the following . EXAMPLE 9. choices and The for METHOD are TRAP or GEAR. SPICE implements the Gear algorithm as a variableorder.4. However.' This can . The default method is trapezoidal. secondorder trapezoidal and Gear order 2 to 6.
33 and 9. CHGTOL.308 9 SPICE ALGORITHMS AND OPTIONS The truncationerrorbased timestep control algorithm is described next for trapezoidal integration. d3 dt3.62) (9. = RELTOL.60) . This error is similar to the one defined for nonlinear equations (Eqs. Ixnl. the next time step. The exact SPICE implementation of the truncation errors is Ex Eqa. An upper bound is calculated for the truncation error at each time point based on the computation of charges or currents of capacitors and fluxes or voltages of inductors.GTOL)/hn The default value for CHGTOL is 1014 C. It is important to get an accurate estimate of the third derivative of the charge. CH. Ixnl) + ABSTOL (9. is introduced for the absolute charge or flux error. Eq. RELTOL. in the above inequality. . SPICE defines also a charge or flux error: . 9. 9. max(lxn+ll. This algorithm is common to most SPICE programs. Based on the upper bound E for the LTE at each time point. (9. the LTE at each time point is taken as the maximum of the two errors: (9.36) and consists of a relative and an absolute error: (9.51. is given by the following inequality: 6E Iddt3n I which results from the definition of the LTE of the trapezoidal method for Xn+l.63) Ex = max(lxn+ll. hn+1.59) Xn+ 1 in the above equation represents the current of capacitors or the voltage across inductors. The highorder derivatives are approximated in SPICE 3x (9.61) A new SPICE option.64) x/ .
Eg.E (9. 9. which scales down the divided difference and therefore the LTE. Eg. 9. With the new factor the predicted time step becomes TRTOL. The recursive formula for divided differences is DD k = DDkl(tn+[) k . Comparisons between the exact LTE for the circuit in Figure 9. . and the one approximated by divided differences have shown that the divided difference overestimates the LTE several times (Nagel 1975).68) ) max (DD 12.67) A value for the maximum time step given by Eg.11. This observation has led to the conclusion that a larger time step can be used than the one defined by Eg.68 for all capaciWrs and inductors in the circuit.DDkl(tn) hn+li (9. 9. becomes (9. .65) which sets the relation between the kth derivative. TRTOL.67.67 is computed for every linear or nonlinear charge.or fluxdefined element in the circuit. 9. DDk. The SPICE timeselection algorithm is outlined below. The automatic timestep control algorithm in SPICE selects hn+ 1 based on the minimum value resulted from evaluating Eg.€a 3 The default value of 7 for TRTOL has proven to provide a good compromise between accuracy and speed for a large number of circuits. 9.64.TIMEDOMAIN SOLUTION 309 by divided differences using the following definition: (9. An option parameter has been introduced in SPICE. and the divided difference of order k.50. dkx/ dtk. the time step computation in SPICE.66) L i=1 DD1 is the numerical approximation of the derivative of x between tn and tn+ I: With these formulas for divided differences.
hn+l is allowed only to double at each time point. TMAX) proceed with tn+2 else reject tn+l hn = hn/8 reduce integration order to I (BE) if (hn > h min) then recompute at new tn+! else TIME STEP TOO SMALL. 9. hn) then reject tn+l hn = hn+! recompute at new tn+! else accept tn+l hn+l = min(hn+I. 6).51. If the new hn is not larger than hmin. The solution at the newly defined tn+ 1 is performed with the firstorder BE method. 9. First.abort Assume that the solution at tn has been accepted and hn has been selected as the new time step. After removing the time dependency at tn+ 1 using transformations of the type given by Eq.9hn which implies that the LTE is within bounds. hn+l is computed based on the prescribed LTE. a new value is defined for hn that is of the previous value. the time step can only increase up to the lesser . TSTEP (see Chap. Also. If a solution could not be obtained in ITIA iterations. which is approximately eight orders of magnitude smaller than the print step.2. The method is changed back to the secondorder TR only if the new tn+ 1 is accepted. If the solution at tn+l is obtained in less than ITL4 iterations. The value of hn+l is accepted if it is at least 0. hmin.310 9 SPICE ALGORITHMS AND OPTIONS tn+! = tn + hn solve at tn+ 1 if iter J1um < ITIA compute hn+l = f( LTE) if (hn+l < 0.53. l new tn+ 1 = tn + 8 hn and the solution is repeated. Eg.9. a new tn+! is defined. where ITL4 is an option parameter defaulting to 10. SPICE aborts the analysis and issues the message *ERROR*: INTERNAL TIMESTEP TOO SMALL IN TRANSIENT ANALYSIS followed by the value of tn and hn. hn. If this value for the time step is larger than the minimum acceptable time step. the program checks whether the nonlinear solution has converged in less than ITIA iterations.3. if larger than hn. the set of nonlinear equations is solved as described in Sec. 9.
if LVLTIM = 1. 9. The approximation of the truncation error is therefore based on an often untrue assumption that x(t) is continuously differentiable to order k in the time interval of interest. A third implementation detail is the bypass option. such as Ie. which represents the LTEbased algorithm. The timestep selection algorithm is defined by the LVLTIM option. At every new time point after the first iteration the nonlinear branch voltages.9hn.38). such as VBE and VBe of a BIT. is used to solve for the time point immediately following the breakpoint. which in tum is a function of the divided difference approximation of the derivative of a voltage or current waveform. there are certain time points. In SPICE2 and other commercial SPICE programs there is an alternate timestep controlling mechanism. The iteration timestep control proves more .TIMEDOMAIN SOLUTION 311 of2.51 is less than 0. If they have not changed more than the tolerance errors EV and Ej (Eqs. If hn+1 evaluated according to Eq. the solution at tn+ 1 is rejected and the smaller value obtained for the time step is assigned to hn. 9. A second accuracyenhancing technique is the prediction of the circuitvariable values for a new time point. are compared to the corresponding values at the previous time point. based on the NewtonRaphson iteration count used at each time point. the iterationcount timestep algorithm is used. the computation of the linear equivalent is bypassed and the conductance values from the last time point are used. called breakpoints. RELTOL. There are a few additional details in the integration implementation that a knowledgeable user should be aware of. which doubles the time step for any time point where a solution is obtained in less than ITL3 iterations and reduces the time step by 8 when more than ITL4 iterations are required. The LTE of the firstorder method is used at the new time point to minimize the error of the approximation. the backward Euler method. TSTEP or TMAX. The method applied at the first time point following a breakpoint is known as a startup method. In SPICE2 and PSpice the only way to reduce bypassing is to tighten the relative error.37 and 9. The default value is 2. First. but it also can cause convergence problems for slowly moving variables that are within the prescribed tolerances compared to the last time point but may differ more than the error tolerance if compared to k time points previously. and the resulting nonlinear function. which defines in tum the new tn+l. The timestep control algorithm is based on an estimate of the LTE. Breakpoints are important for an accurate solution because they prevent the evaluation of the LTE based on time points preceding the discontinuity. Bypassing the reevaluation of certain devices can result in 20% savings in analysis time. which is a time point where an abrupt change in the waveform is anticipated based on the shape of independent source signals. At a breakpoint a solution of the circuit differential equations is enforced and a firstorder method. that are treated differently. In the first iteration of a new time point SPICE employs a linear prediction step for the voltages and charges of nonlinear branches. Large inaccuracies are avoided by introducing the concept of a breakpoint. This must be done carefully since it can have the adverse effect of nonconvergence depending on the nonlinear equations. SPICE3 provides an option at compile time that prohibits bypass.
Nagel (1975) has found that for a set of benchmarks using the default tolerances. The list starts with circuit statistics. because of the overhead of computing the coefficients of the method at each time step (Nagel 1975). A sample output of the information printed by the ACCT request in SPICE2 is shown in Figure 9. This summary covers most common SPICE options. the information is for the slewrate transient analysis of the complete /LA 741 circuit. an order change is performed.05 times larger than the value obtained for the current order.5.1 Analysis Summary Before reviewing the analysis options it is instructive to introduce a SPICE option that provides insight into the analysis: the accounting option. In general it has been found that most problems where Gear is beneficial. This section summarizes the • OPTIONS parameters by function. As mentioned previously. NUNODS is the number of nodes defined at the top . if there is any. The timestep is also controlled by the LTE in the same manner as described above.and sixthorder Gear algorithms is that the divided difference introduces a sizable error. This timestep control algorithm is not available in SPICE3 or PSpice. 9.5 SUMMARY OF OPTIONS The various options available to a user for controlling solution algorithms and tolerances have been introduced throughout this chapter. and k + 1. If the value of hn+ 1 for higher or lower order method is 1. whose SPICE input is listed in Figure 7. the majority of the options introduced in this text can be found in most versions. for a complete list of options available in a specific SPICE version the reader is advised to consult the corresponding user's guide.312 9 SPICE ALGORITHMS AND OPTIONS conservative but more foolproof for cases when no charge storage parameters are specified in the model definition of a nonlinear device or when the default error bounds are not suitable.17. So far the timestep control mechanism has been presented only for the TR method.29. The order leading to the largest time step within the prescribed LTE is chosen.1. Although use of the Gear method can result in a reduction of computed time points and iterations. The highest order of the Gear method to be used is limited by MAXORD and the number of previous time points available since the last breakpoint. k. ACCT. the savings in execution time over the TR method is small. The problem with the fifth. 9. Only for tolerances reduced by 2 to 3 orders of magnitude are the higherorder Gear algorithms being exercised.28 and whose schematic is shown in Figure 7. a MAXORD of 2 or 3 is sufficient. the Gear algorithms order 2 to 6 are also implemented in SPICE. The time step following a time point where the method of order k has been used is evaluated for orders k . such as where there is numerical ringing or convergence problems. An additional feature for the Gear method is that the order of the method can also be modified dynamically. Although options differ among SPICE versions. the Gear algorithm used order 2 most of the time.
READIN SETUP TRCURV DCAN DCDCMP DCSOL ACAN TRANAN OUTPUT LOAD CODGEN CODEXC MACINS OVERHEAD TOTAL JOB TIME Figure 9.00 3.783 4. I CVFLG is the requested points in a DC transfer curve. 7.00 51. SPICE statistics for the JLA741slewrate analysis in Sec.000 0. NUMEL 42 JACFLG 0 DIODES 0 INOISE 0 BJTS 26 IDIST 0 JFETS 0 NOGO 0 MFETS 0 IFILL 102. These numbers can be verified from the data in Chap.000 DEG C *********************************************************************** NUNODS 6 NUMTEM 1 NSTOP 82.5. NCNODS 27 ICVFLG 0 NTTBR 370.45 35.43 O.02 56.68 9.53 0. and NUMNOD is the number of nodes after adding the internal nodes generated because of the parasitic series resistances of semiconductor devices. NCNODS is the number of the actual circuit nodes resulting after expansion of subcircuits. O. 1231. the total number of elements. level of the circuit.60 0. NUMRTP 56.17 0.283 0. O. NUMNOD 79 JTRFLG 201 NTTAR 472. NUMTTP 284. 7. NUMNIT 1231.067 0.980 COPYKNT 41543. 84. which is broken down into the different types of semiconductor devices.000 0.15 0. NUMTEM is the number of temperatures.6 3/15/83 ******** 17:55:34 ***** UA741 FULLMODEL SLEW RATE **** JOB STATISTICS SUMMARY TEMPERATURE = 27.SUMMARY OF OPTIONS 313 ******* 03/23/92 ******** SPICE 2G.000 0. These numbers are followed by NUMEL. The second set of data summarizes the analyses requested. MEMUSE 15484 PERSPA 92. 3. JTRFLG is . MAXMEM 400000 IOPS 1059.
JACFLG is the number of frequency points in the AC analysis. NTTAR is the total number of nonzero terms after reordering. NSTOP is the number of MNA equations. The fourth set summarizes information about the transient solution and memory use. The default is 103. PIVREL=value (SPICE2 and SPICE3) represents the ratio between the smallest acceptable pivot and the maximum entry in the respective column. Only increasing GMIN can lead in some cases to better convergence. NTTBR is the total number of nonzero terms before reordering. If no entry is larger than value at any LU decomposition step.314 9 SPICE ALGORITHMS AND OPTIONS the number of transient print/plot points. or TRUE. if the analysis has finished. Note that the outputs produced by different SPICE versions for this option vary but relate some of the same statistics. . MAXMEMis the amount of memory available. These options should not be modified unless convergence failure is caused by singular matrix problems. The default is 1013. if the analysis has been aborted because of an error. but it may be of interest to users who want to relate the knowledge about algorithms acquired in this chapter to a specific circuit as well as to learn about the ease or difficulty of convergence and timedomain solution. None of the above information has any bearing on the actual solution. a larger value for this option can lead to a betterconditioned matrix at the expense of more fillins. PIVTOL=value (SPICE2 and SPICE3) sets the smallest MNA matrix entry that can be accepted as a pivot. and I. The third set of data contains the linear system matrix statistics. IFILL is the number of fillins created during the LU decomposition process and is equal to NTTARNTTBR. the circuit matrix is declared singular. and PERS PA is the sparsity of the MNA matrix expressed as a percentage. which is 0. MEMUSE is the memory used by the present circuit. and NUMNIT is the total number of iterations performed for the transient analysis. and INOISE and IDIST indicate whether a smallsignal noise or distortion analysis has been performed. NUMRTP is the number of rejected time points. and CPYKNT is the number of memory transfers. 9.2 Linear Equation Options The following options are related to the linear equation solution: GMIN=value defines the minimum conductance connected in parallel to a pn junction. Last in the analysis category is the variable NOGO. or FALSE. the default is 1012 mho. lOPS is the number of floatingpoint multiplications and divisions required for each solution of the linear system. NUMTTP is the number of time points at which the circuit has been solved. The last part of the summary lists the times in seconds for the different analyses and solutions and the number of iterations. where the time step hn+ 1 had to be rejected and the analysis restarted at tn.5.
this is also the number of iterations used for a first solution in the timedomain when UlC is present on the . VNTOL=value is the absolute voltage tolerance defined by Eq.33. it defaults to 5000. The default is 103. DC transfer curve analysis. The default is 100. which defaults to 1012 A.SUMMARY OF OPTIONS 315 9. 9. 9. This option is a protection against very long simulations and can be turned off by setting value to zero.36. the default is 10. lTL3=value is meaningful only in SPICE2. in connection with the LVLTIM=l option where it defines the lower iteration limit at a time point. A higher value may lead to a solution. and bypass. These options are the following: lTL1=value sets the maximum number of iterations used for the DC solution.5. 9. This option can have direct impact on convergence. In PSpice value is also used as the maximum number of iterations at each source value during source ramping.4 Numerical Integration The options for the timedomain solution can set integration methods as well as tolerances specific to this analysis. timestep control. The smallest current that can be monitored is equal to value.33 and 9. It represents the smallest observable voltage and defaults to 106 V. lTL2=value sets the number of iterations allowed for any new source value in a .36. TRAN line. ABSTOL=value represents the absolute current tolerance as defined by Eq. lTL5=value is the total number of iterations allowed in a transient analysis. lTL6=value (SPICE2 and SPICE3) represents both a flag for source ramping in a DC solution and the maximum number of iterations allowed for each stepped value of the supplies.3 Nonlinear Solution Options The options that control the NewtonRaphson solution can be grouped as convergence tolerances and iteration count limits. 9. . lTL4=value sets an upper limit to the number of iterations performed at a time point before it is rejected and the time step reduced by 8. the time step is doubled when the circuit converges in fewer iterations. The convergence tolerances are the following: RELTOL=value defines the relative error tolerance within which voltages and device currents are required to converge as set forth by Eqs. A few options control the number of iterations allowed in the nonlinear equation solution. The default is 50.5.
47.316 9 SPICE ALGORITHMS AND OPTIONS A user can select from two integration methods. the default is 2. TRAP. MAXORD=value (SPICE2 and SPICE3) sets the maximum order of the Gear method when selected by the METHOD option.1. several integration formula orders. Note that this option effects the analysis results at temperatures specified in the . parameters are printed. by default the model NOMOD suppresses the listing of device model parameters. LTE. 9. is the absolute charge tolerance at any time point according to Eq. SPICE implements variableorder Gear integration formula contained in Appendix D. at which all device parameters are assumed to be measured. global device properties. and two timestep control mechanisms as follows: METHOD=TRAP /GEAR (SPICE2 and SPICE3) selects the numerical integration formula. OPTS . the default is NONODE. The default value is 2.5.5 Miscellaneous Options A number of options in SPICE control the analysis environment. rather than a command line as in SPICE2 and PSpice. causes a complete list of all options parameter settings. TEMP=value. the default is the secondorder trapezoidal method. The following option modifies the analysis environment: TNOM=value sets the reference temperature the analysis time.67. TEMP statement.62. requests the output of a node table. the default is 27°e. LVLTIM=value a (SPICE2) selects whether the timestep is controlled by the local truncation error. NOPAGE NODE suppresses new pages for different analyses and header printing. as defined by Eq.3. the default is NOLIST. The information and its format saved by SPICE in the output file is controlled by the following options: LIST generates a comprehensive summary of all elements in the circuit with connectivity and values. The tolerances that can be modified in the transient analysis are the following: TRTOL=value CHGTOL=value is a scale factor for LTE as defined in Eq. 9. 4. and which information is output. 9. 9. In SPICE3 the analysis temperature is also an option. it defaults to 7. it defaults to 1014 e. of the method (value = 2) or by the iteration count needed at each time point for convergence (value = 1). which lists the elements connected at every node. see Sec.
and P. The source area. drain area. DEFAS=value sets the global. Global geometric dimensions can be defined for MOSFETs as option parameters: DEFW=value sets the global. REFERENCES Boyle. M Lin. 3) overrides the DEFAS value. There is an additional command belonging in the options category that controls the line length in the SPICE2 output file: •WIDTH OUT=value where value equals the number of characters per line. 3) overrides the DEFW value. on the device line (see Chap. PLOT. of California. More than 4 digits may be meaningless unless RELTOL is reduced. DEFAD=value sets the global. PRINT or a . W. The channel length. New York: McGrawHill. the SPICE builtin default is 1 meter. or default. Performance limits of integrated circuit simulation on a dedicated minicomputer system. the SPICE builtin default is 1m2• The drain area. Univ. on the device line (see Chap. AD. device channel length. it defaults to 201.REFERENCES 317 NUMDGT=value selects the number of digits to be for results. . Note that this option does not affect the computation of the results but only how many digits are printed. R. Chua. ERL Memo UCBIERL M81/29 (May). AD. A. value must be larger than the number of data points resulting from the analysis. Personal communication. 0. value is an integer number between printed after the decimal point 0 and 8 and defaults to 4. AS. The channel width. Cohen. source area. or default. 1972. D. AS. L. the SPICE builtin default is 1 m2. W. By default the SPICE2 output line is 120 characters long. E. 1981. DEFL=value sets the global. ComputerAided Network Design. on the device line (see Chap. 1978. ComputerAided Analysis of Electronic Circuits: Algorithms and Computational Techniques. 1975. L. PSpice and specific implementations of SPICE2 allow the user to limit the analysis time through the following options parameter: CPTIME=value sets the maximum CPU time for the analysis. the SPICE builtin default is 1 meter. or default. 3) overrides the DEFAD value. or default. Berkeley. on the device line (see Chap. L. NJ: Prentice Hall. Englewood Cliffs. Calahan.. 3) overrides the DEFL value. G. device channel width. LIMPTS=value sets the number of points to be saved for a .
J. of Illinois.. Freret. R. w. Avoiding zero pivots in the modified nodal approach. and C. Computer Solution of Linear Algebraic Systems. and D. Univ.. Electric Circuits. IEEE Proceedings 69 (October). Nagel. NJ: Prentice Hall. Nagel. Moler. Iterative Solution of NonLinear Equations in Several Variables. C. R. R. Technical Report No. 1990. 1989. 1975. Numerical integration of stiff ordinary equations. Hachtel. 1967. N. Gear. J..318 9 SPICE ALGORITHMS AND OPTIONS Dorf. A. SPICE2: A computer program to simulate semiconductor circuits. Berkeley. of California. 1978. Computer analysis of nonlinear circuits. W. Univ. IEEE Transactions on Circuit Theory CT18 (January). W. 3d ed. and T. Dept. Stanford Univ. G. P. L. New York: John Wiley & Sons. C. P. Rheinholdt. 1971. of Computer Science. A. McCalla. N. Reading. Paul. MA: AddisonWesley. (May). 1970. W. A.Vincentelli. The modified nodal approach to network analysis. M. Ortega. Introduction to Electric Circuits. Rohrer.. 1988. IEEE Transactions on Circuits and Systems CAS22 (June): 504509. Yang. and R. IEEE Transactions on Circuits and Systems CAS28 (April): 271278. Englewood Cliffs. Elements of computeraided circuit analysis. Forsythe. and A. W. Trick. 1975. L.. C. 1967. 1989. J."Sparse Matrix Solution with Pivoting in SPICE2.. W. O. Ruehli. Vladimirescu. 1971. Stanford. J. J. McCalla. Boston: Kluwer Academic. of California. Ho. Hajj. I. E. C. ERL Memo ERL M520 (May). Minicomputer Calculation of the DC Operating Point of Bipolar Circuits. New York: Academic Press. IEEE Journal of SolidState Circuits SC6 (August): 166182. Urbana. Analysis of Linear Circuits. L. Univ. New York: McGrawHill. G. 1976. 1981. Pederson. Fundamentals of ComputerAided Circuit Simulation. 50151. Sangiovanni.. and W. Berkeley. Brennan.. CA. Report 221. and P. Nilsson. A survey of thirdgeneration simulation techniques. E. excluding radiation (CANCER)." EECS 290H project. . 1981. W.. B. Stanford Electronics Labs.
or the numerical integration. either its specification or its inoperability. A convergence problem can be categorized as either failure to compute a DC operating point or abortion of the transient analysis because of the reduction of the time step below a certain limit without finding a solution.1 INTRODUCTION Generally. SPICE finds a solution to most circuit problems. The two most common messages that SPICE2 prints when it fails to find a solution are *ERROR*: NO CONVERGENCE IN OC ANALYSIS and *ERROR*: INTERNAL TIME STEP TOO SMALL IN TRANSIENT ANALYSIS This chapter describes the most common causes of convergence failure and the appropriate remedies. because of the nonlinearity of the circuit equations and a few imperfections in the analytical device models a solution is not always guaranteed when the circuit and its specification are otherwise correct. the NewtonRaphson iteration.Ten CONVERGENCE ADVICE 10. failure to find a solution can occur at the level of the linear equation. In the majority of the cases when a solution failure occurs it is due to a circuit problem. However. From the perspective of the previous chapter. Rather than present the convergence issues based on the algorithm causing 319 .
tolerances. options. different computers may use different floatingpoint representations and different mathematical libraries of elementary functions. and DC operating point solution with a different analysis. Section 10. Thus. Section 10. the problems and their remedies are the same as for the smaller circuits described in this chapter.4 describes some of the problems and several approaches that can lead to a solution in these cases. Specific procedures can be followed when SPICE fails to find a DC solution of the circuit. Timedomain analysis can provide an inaccurate solution or fail because of a number of reasons related either to the integration method and associated timestep control or the iterative solution of nonlinear equations.2 10. An overview of circuitspecific analyses and issues is provided in Sec. oscillators require certain initializations not necessary for amplifiers.320 10 CONVERGENCE ADVICE the problem.2. Although convergence failure is more common for large circuits. Note that the convergence problems described are specific to the simulators mentioned in the text.2 contains the most common remedies for SPICE solution failure. Because of differences between SPICE simulators. All convergence issues described in this chapter are illustrated by small circuits that can be easily understood by a new user. 10.1 COMMON CAUSES OF SOLUTION FAILURE Circuit Description The first thing a user should do after a convergence error occurs is to check the circuit description carefully. the SPICE input should be compared to the schematic for correct connectivity. it has been deemed beneficial to describe the causes for failure from a user's perspective.3. . Sometimes the same simulator can succeed or fail to converge depending on the platform. Knowledge of the specifics of different types of electronic circuits can assist the user in finding an accurate solution by specifying appropriate analysis modes. the problems presented below can be duplicated only in the specified simulator. A list of every node and the elements connected to it can be obtained by adding the NODE option to the input description: •OPTIONS NODE The user should specifically look for and identify nodes that are floating or undefined in DC. The results presented in this chapter are obtained from SPICE2 and SPICE3 running on SUN workstations and PSpice running on 386/486 PCs.5. and suitable model parameters. 10. 10. Additional SPICE information can be helpful for this verification. These approaches are presented and exemplified in Sec. use of builtin convergenceenhancing algorithms. and bipolar circuits may need different convergence tolerances than do MOS circuits. The prescribed remedies include redefinition of analysis options.
or bulk. source. Although SPICE identifies and reports most topology errors. As described in the previous chapter. inductors are equivalent to zerovalued voltage sources in DC analysis and therefore cannot form a mesh or loop with voltage sources or other inductors. The gate terminal of a MOSFET. Common error messages related to circuit topology are *ERROR*: *ERROR*: *ERROR*: Vname LESS THAN 2 CONNECTIONS AT NODEnumber NO DC PATH TO GROUND FROM NODEnu~ber INDUCTOR/VOLTAGE SOURCE LOOP FOUND. has no DC connection to the other terminals of the device (Grove 1967). One such example is the gate terminals of MOSFETs which need to be connected properly for DC biasing. unlike the base of a BJT. defined in the SPICE deck listed in Figure 10. The second message points to the nodes that are floating in DC and cannot be solved. The following example illustrates an analysis failure due to the improper connection of a MOSFET which goes undetected by SPICE. drain. Most often such nodes are connected to ground through capacitors. The third error message records a violation of Kirchhoff's voltage law. C1 r& =V 1 Figure 10. which are open circuits in DC. CONTAINING The first message identifies any node that has only one terminal of one element connected to it. some evade the scrutiny.COMMON CAUSES OF SOLUTION FAILURE 321 SPICE checks every circuit for topological and component value correctness. EXAMPLE 10.2. Floatinggate MOS .1 Find the time response of the circuit shown in Figure 10.1 circuit. and therefore must be properly biased outside the device.1 to the input signals VA and VB.
000 DEG C PARAMETERS *********************************************************************** NMOS NMOS 1. .WIDTH OUT=80 .0000 NODE (3) VOLTAGE 0.1.6 3/15/83 ********11:48:25***** GATE OF MOSFET MOSFET MODEL ERROR TEMPERATURE = 27.3 * .000 DEG C **** *********************************************************************** M1 C1 VA VB V1 * 2 4 4 3 2 1 1 3 0 0 0 0 NMOS L=100U W=100U lOP IC=O PULSE 0 5 70U 2N 2N lOU 100U PULSE 0 5 lOU 20U 20U lOU 100U 6 NMOS NMOS VTO=1.000 DEG C *********************************************************************** o VB 1 C1 2 V1 3 VA 4 C1 *******01/16/92 FLOATING **** V1 M1 M1 VB M1 M1 VA ******** SPICE 2G.00D05 LESS THAN PIVTOL TYPE LEVEL VTO KP *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 2(0.TRAN 1U 100U 0 .6 3/15/83********11:48:25***** **** TABLE TEMPERATURE = 27.PRINT TRAN I(V1) I (VA) I(VB) .0000 ***** JOB ABORTED Figure 10.6 3/15/83********11:48:25***** GATE OF MOSFET INPUT LISTING ERROR TEMPERATURE = 27.000 1.322 10 CONVERGENCE ADVICE *******01/16/92 FLOATING ******** SPICE 2G.0000 NODE (2) VOLTAGE 0. 300 2.MODEL * .2 SPICE2 input and output with node table for circuit in Figure 10.0000 NODE ( 5) VOLTAGE 0.000000D+00)IS *ERROR*: NO CONVERGENCE IN DC ANALYSIS LAST NODE VOLTAGES: NODE ( 1) VOLTAGE 0.END *******01/16/92 ******** SPICE FLOATING GATE OF MOSFET ELEMENT NODE ERROR 2G.OPTIONS NODE .
6 and 5. by setting the emitter current supplied by the current . Alternatively. There are several remedies once the cause of this type of failure is understood. THAN statement. as described in Example 10. which connects the signals VA and VB during the transient response.COMMON CAUSES OF SOLUTION FAILURE 323 Solution The SPICE2 output. but care must be exercised.2. proper biasing should be provided to the gate. if a DC solution is needed. The node table for this circuit. If the singular matrix problem occurs but the value of the maximum element at a certain elimination step is nonzero. which is printed by SPICE when the NODE option is set (see Figure 10. including the input circuit.2). that is. The initial transient solution. PIVTOL can then be lowered to a value less than the maximum entry and the analysis rerun.2. the information about which terminal of M] is connected at a given node is not provided. the following singular matrix message is printed by SPICE2: *ERROR*: MAXIMUM PIVI'OL ENTRY IN THIS COLUMN AT STEP 2 (D. is shown in Figure 10.2 The setup in Figure 10. the capacitor.3.DDDED) IS LESS THAN The submatrix at the second elimination step is singular because the circuit is open at node 1. the DC analysis. The current source in this case is an open circuit. the actual value is listed in parentheses in the error message. leaves the gate terminal floating in DC. shows that only C] and M] are connected at node 1. Another element that can cause singular matrix problems is a current source that voluntarily or involuntarily is set to zero. the DC solution should be bypassed by specifying the UIC keyword in the. If only the timedomain response is of interest. This problem goes undetected by the SPICE topology checker. It is left as an exercise for the reader to experiment with the suggested workarounds to find whether they result in the completion of the analysis. and it is up to the user to understand the problem.3 can be used to measure the collector cutoff current. EXAMPLE 10. fails with *ERROR*: NO CONVERGENCE IN IX: ANALYSIS A closer look at the output file reveals that the circuit matrix is singular within the SPICE tolerances. a common data sheet parameter. Unfortunately. as described in Examples 4. ICBO. It can be used to defeat the topology checker.
source Ie to zero and measuring Ie of the transistor. The default is P IVT 0L = 1013• . This problem can be overcome by lowering the value of PIVTOL. Solution The input is listed in Figure lOA' together with the SPICE analysis results for Ie = O.OPTIONS PIVTOL=lE14 causes SPICE2 to finish the analysis.3 Cutoff current measurement circuit. The same message of a singular matrix is printed as in Example 10. lowering PIVTOL below the value of the maximum entry can cure the problem when a singular matrix is encountered. 5.324 10 CONVERGENCE ADVICE + Figure 10. This is equivalent to leaving the emitter of QI open. .77 X 1014. the problem remains that random numbers are generated during the solution process for VE' Note that for Ie =? 0 SPICE might not find a solution because of the erroneous circuit setup: QI cannot conduct the driving current. Although PSpice finds a solution without flagging a singular matrix. see also Sec. can be set to any value. VE = VI. which is not permitted in SPICE. The following • OPTIONS line added to the circuit description in Figure lOA. Lowering of PIVTOL allows SPICE to accept smaller values as pivots in the linear equation solution.2. 9.1 but the maximum entry is a finite number. In the case of correctly defined circuits. The cause for this error is that the circuit equations that SPICE solves constitute an underdetermined system and the emitter voltage.
8M PTF=O + CJS=O MJS=O VJS=750M XCJC=l XTB=l.38 IKR=2.5 V+ 2 0 15 VC 2 3 0. 5 IS=6.OPTION PIVTOL=1.WIDTH OUT=80 .526 + VJE=757.9P RE=741. 038 MJE=O.OPT ACCT .COMMON CAUSES OF SOLUTION FAILURE 325 *******01/16/92 COLLECTOR **** CUTOFF ******** CURRENT SPICE 2G.5P RC=696.8M VJC=800M NC=1. 25 + VAR=10 CJE=5.773160D14) IS LESS THAN PIVTOL *ERROR*: NO CONVERGENCE IN DC ANALYSIS LAST NODE VOLTAGES: NODE ( 1) VOLTAGE 0.3.7M + TF=610 52P VTF=1.8M MJC=0.ll ISE=23.1474 NODE (2) VOLTAGE 15. 534F + IRB=100U RB=O RBM=O XTI=3 ISC=100P EG=l. END PIVOT CHANGE ON FLY: N= 7 NXTI= 7 NXTJ= 7 ITERNO= 23 TIME= O.2 AF=1 KF=O FC=0. 31N XTF=100 ITF=317. lowering PIVTOL below the smallest matrix entry indicated in the error message enables SPICE to compute the solution.4M CJC=3.6 3/15/83********11:41:02***** CIRCUIT TEMPERATURE = 27.4 SPICE2 input and outputfor circuit in Figure 10. 9 NR=1.188K TR=29. .42F + IKF=113.0000 ***** JOB ABORTED Figure 10. The conclusion of this example is that a singular matrix message can be caused by an error in the circuit specification and that if the circuit is correct and no floating nodes are found. 3 VAF=49.MODEL M2N2501 NPN + BF=166.0E14 .OP .000 DEG C MEASUREMENT INPUT LISTING *********************************************************************** Q1 3 0 1 M2N2501 AREA=l .0 IE 0 1 0 * * * *.0000 NODE (3) VOLTAGE 15.1M NE=1.294 NF=1 BR=744.OOOOOD+OO *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 8 (5.
an alternate way is to use the • NODESET command to initialize the voltages at these nodes. GMIN prevents the occurrence of floating nodes in a transistor circuit. Ideal elements and unrealistic component values and semiconductor device model parameters can lead to voltages and currents that combined with transcendental equations generate numbers outside the computer range. connected in parallel.1. and JFETs have a very small conductance. which can be set as an option. GMIN. The semiconductor model parameters are printed by default in the output file obtained from SPICE2 and PSpice. A highimpedance node can result in the same failure mode as above.326 10 CONVERGENCE ADVICE c GMIN D GMIN B G1 GMIN E S GMIN B Figure 10. MOSFETs. BJTs.5 GMIN conductance across pnjunctions for BJT and MOSFET. smaller than l/GMIN.2 Component Values In the case of an analysis failure or erroneous results. 10.2. . EXAMPLE 10. The simple example presented below leads to a solution failure or erroneous result depending on which SPICE version is used.6. The LIST option can be introduced in the SPICE input to obtain a comprehensive summary of all elements and their values. As protection against this problem the internal SPICE models of the pn junctions in diodes. because numerically it can become an open circuit. can be added to highimpedance nodes if they do not disturb the operation.3 Use SPICE to find the operating point and the timedomain response of the halfwave diode rectifier shown in Figure 10. the component values and model parameters should be doublechecked. The schematics for the BJT and the MOSFET including GMIN are shown in Figure 105 Large resistances. after the topology has been verified. similar to the gate node of transistor M1 in Example 10.
7 SPICE descriptionof halfwavediode rectifier. limit the value of the exponent to 80 in the internal computation which combined with automatic source ramping leads to a solution. however.OP .7. this solution is wrong. such as older PSpice releases.   Solution An uninformed user may try to simulate this circuit with the default diode model parameters. In the absence of an external resistor the role of the diode parasitic series resistance is to provide current limiting in the halfwave rectifier circuit. Some versions of SPICE.WIDTH OUI'=80 • END Figure 10.6 Halfwave dioderectifiercircuit. that can be represented in double precision. . The simulation fails because the absence of current limiting leads to numerical range error in computing the value of (10. that is. In reality the DIODE CIRCUIT WITHOUT CURRENT LIMITING VIN 1 0 20 Dl 1 0 DMOD . 10308.COMMON CAUSES OF SOLUTION FAILURE 327 CD D1 + V1N 20V ID ~ VD Figure 10. because the current is limited at The error in this example is due to the lack of a parasitic resistance in the diode model. with an ideal diode according to the SPICE input listed in Figure 10. For smaller values of the voltage source VIN SPICE may find a solution as long as ID is in the range of floatingpoint numbers.1) This number is greater than the largest value.MODEL DMOD D * .
Vi: Vx = FC. as well as Fe.3 SPICE o Figure 10. Other model parameters that can cause numerical problems for bipolar devices are the emission coefficients. For an accurate solution it is important to observe certain limits on the element values. Eg. NF and NR for a BJT (see Chapter 3). Eq.2) The approximation is shown graphically in Figure 10.8 bias.. The value of C] increases toward infinity as the junction voltage VD approaches the builtin voltage VJ according to Eg. 3. Power electronics is the one area where resistances Simple theory. which approximates the junction capacitance.8.2). such as N for a diode. C]. In SPICE the characteristic described by Eg. that is. for a forwardbiasedjunction.2. respectively.3. Fe. It was shown above that the smallest conductance used by SPICE is GM IN = 1012. 3.5. VJ VJ Junction capacitance approximation in forward . Vi where 0:5 FC < 1. The default for FC is 0.3 is replaced by the tangent to the curve it describes when the junction voltage reaches half the value of the builtin voltage.3 is replaced for pn junctions in all semiconductor models with the tangent to the curve at a junction voltage determined by FC and the builtin voltage. This error can also occur for JFETs and MOSFETs when improperly biased because of the presence of an ideal pn junction between gate and drain or source or between bulk and drain or source.328 10 CONVERGENCE ADVICE pn junction of the diode would melt if no proper currentlimiting resistor is added in the circuit. 9. The maximum conductance cannot be more than 14 to 15 orders of magnitude larger than the smallest conductance in order to satisfy the constraint set by the limited accuracy of number representation in a computer (see Sec. (10. 3. This constraint limits the smallest resistance to 1 mD.3.
This approach is exemplified by the BiCMOS voltage reference circuit in the following section. as described in Sec. the lower the chance for such an occurrence. as explained in Sec. the presence of VAF in a BIT model results in a finite output conductance of the transistor. when a very complex model is used for a device and the simulation of the circuit fails. to 6 in SPICE3 (Sheu. 10.3. Convergence problems also occur when the most elementary or ideal models are used. Therefore. but the lower limit defined above should still be observed. 3. Also.4. on convergence improvement in DC and transient analysis. For a specific combination of arguments the function describing the conductances can become discontinuous. parameters RBM and IRB. which can go to 3 in SPICE2 (Vladimirescu and Liu 1981). The presence of a parameter causes the inclusion of a specific physical effect in the behavior of a semiconductor device. the smallest values are dictated by semiconductor models and are of the order of femtofarads (l015 F).5. a nonzero value for LAMBDA in a FET model introduces a finite output conductance in the saturation region. For example. and to 4 in PSpice.3. The higherlevel models include such secondorder effects as subthreshold current. The value of "theequivalent conductance for these elements is also a function of the integration time step. The simpler the model. as demonstrated by Example 10. In this situation the user is advised to add those parameters that increase accuracy to the simulation. . in a BIT (Appendix A) or smallsize effects in a MOSFET. As explained in Sec. whereas the absence of the parameter eliminates modeling of the corresponding effect. more than six orders of magnitude apart as long as they are virtual shorts and open circuits by comparison with the other conductances in the circuit. 1 JLF. can help convergence. As mentioned earlier. the equations implemented in various versions of SPICE are not perfect. a selective omission of secondorder effects.COMMON CAUSES OF SOLUTION FAILURE 329 smaller than 1 n need to be modeled. Convergence is related not only to specific values of model parameters but also to the complexity of the models. Once a first solution is obtained. Once all the above guidelines on circuit correctness and component values limits have been observed and SPICE still does not converge. The use of ideal switches also leads to extreme values for the ON and OFF resistances. it is necessary to use initialization of critical nodes and adjust some options parameters. subthreshold conduction in a MOSFET can help convergence. 9. The OFF resistance need not be as large as lIGMIN The same rules on the ratio between the largest and smallest values of a component must be observed also for capacitors and inductors.3.2. Scharfetter. and Ko 1985). such as baseresistance modulation. 2. similarly. These two issues are exemplified in the following two sections. it is not necessary to set these two parameters. RON and ROFF. For practical circuits the largest capacitances should not surpass . MOSFETs can be described by more complex and accurate models than the SchichmanHodges model presented in Chap. convergence with "theinitial. and smallsize effects. such as finite output conductance and charge storage. velocitylimited saturation. these models are accessed by the LEVEL parameter. . more complex model can be achieved by initializing key nodes of the circuit.
35EIO CGDO=3.330 10. among the three versions used in this text.9 using SPICE2. ITLl defaults to 100 in SPICE2 and SPICE3 and to 40 in PSpice. listed in Figure 10.89EIO CJ=3. and the results are as listed in Figure 10.4 Solution The circuit is a conventional threestage CMOS operational amplifier (Gray and Meyer 1985) in a closedloop unitygain feedback configuration. SPICE2.11.75E4 MJ=O.76 GAMMA=0. The analysis of this circuit produces a DC convergence error in SPICE2.29 TOX=225EIO NSUB=3.OPTION ITL1=300 to the input file. and the user must specifically request the sourceramping convergence algorithm by specifying the ITL6 option.10.The function of the various transistors is documented in the input file.5E16 U0=411 LAMBDA=0. Thus. Note that various SPICE versions handle nonconvergence in different ways.71 GAMMA=0. .4 PMOS: VTO=0. PSpice and the latest versions of SPICE3 automatically run a builtin convergenceenhancing algorithm after failing to find a solution in the first ITLl iterations. This circuit does not converge in PSpice or SPICE3.02 CGS0=2. The following LEVEL=2 model parameters should be used for the two types of MOS transistors: NMOS: VTO=O.3 10 CONVERGENCE ADVICE DC CONVERGENCE This section describes several approaches that can be followed when a circuit that has passed the scrutiny of the previous section fails to converge in DC analysis. It is questionable whether it makes sense to use a higher ITLl in PSpice. especially for large circuits.6 TOX=225EIO NSUB=1.6E16 UO=139 LAMBDA=O.89EIO CGDO=2.4 Compute the operating point of the CMOS operational amplifier shown in Figure 10. however. It definitely makes sense in SPICE2. The iteration count is increased by adding the line . which may need more than 100 iterations to converge.2E6 CGS0=3. which use automatic ramping algorithms. EXAMPLE 10. which automatically ramps the supplies after ITLl iterations and may find a solution faster through this approach. the DC operating point is found by SPICE2 in 108 iterations. The first step to be taken after a convergence failure is to rerun the circuit for more than the default ITLl iterations. This circuit is extracted from the collection of circuits with convergence problems in SPICE prepared by the Microelectronics Center of North Carolina.02 XJ=O. aborts the run if no convergence is reached in ITLI iterations.35EIO CJ=4.74E4 MJ=0.
G) 5V 100n RF ~ ~ Figure 10. .9 CMOS opamp circuit diagram..• .
5 * *. L=10U L=10U * DIFFERENTIAL * * MI0 36 33 32 1 AMPLIFIER STAGE L=2U L=2U L=3U L=3U L=2U AD=24P AD=24P AD=136P AD=136P AD=24P AS=24P AS=24P AS=136P AS=136P AS=24P PCH W=11U M20 3 34 32 1 PCH W=11U M30 36 36 o 0 NCH W=6U M40 3 36 o 0 NCH W=6U M50 32 7 1 1 PCH W=14U * * * FOLDED CASCODE STAGE WITH COMPENSATION W=80U L=2U AD=24P AS=24P W=24U L=2U AD=136P AS=136P W=46U L=2U AD=136P AS=136P W=4U L=3U M2 6 7 1 1 PCH M3 6 5 4 0 NCH M4 4 3 0 0 NCH M80 11 5 3 0 NCH CC 6 11 .22PF * COMMON DRAIN OUTPUT STAGE * M7 1 6 12 12 NCH W=100U L=2U M8 12 9 0 0 NCH W=63U Figure 10.5 0 lE9 lE9 50E9 100E9 ) VIN 99 0 DC 2. internally compensated.332 10 CONVERGENCE ADVICE CMOS OPAMP * * * * * * * This opamp is a conventional 3stage.10 * AD=136P AS=136P L=2U AD=136P AS=136P SPICE input for CMOS opamp.5U W=71U W=69U W=35U W=12U L=40U L=10U L=10U. CMOS opamp from the MCNC SPICE test circuits. ANALOG * * M65 M64 M63 M62 M61 0 7 5 5 9 0 7 7 5 9 INPUT * BIAS CIRCUIT * 7 1 1 9 0 1 1 1 0 0 PCH PCH PCH NCH NCH W=4. . The simulation file is set up for closed loop (unitygain feedback) analysis of transient and ac performance. SUPPLY VOLTAGES VDD 1 0 DC 5 VAP 34 99 PULSE ( 0.0 0.
OPTIONS ACCT ITL1=300 .02 * ANALYSES * .6 3/15/83********15:44:54***** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.6E16 + XJ=0.29 * .0207 NODE 3) 7) 32) 99) VOLTAGE 1.000 DEG C *********************************************************************** NODE ( 1) ( 6) (12) (36) VOLTAGE 5.74E4 MJ=0.OOODtOO TOTAL POWER DISSIPATION 1.11 CMOS opamp DC solution.0208 2.4 TOX=225E10 NSUB=1.35E10 + CGDO=3.6 CGS0=3.END Figure 10.7841 2.250D04 O.62003 WATrS Figure 10.2190 2.75E4 MJ=0.10 (continued) *******01/21/92 CMOS OPAMP **** ******** SPICE 2G.8663 3. 333 .3756 1.0000 3.6144 2.5000 NODE 4) 9) 33) VOLTAGE 1.5E16 + U0=411 LAMBDA=O.89E10 CJ=3.5000 NODE 5) 11) 34) VOLTAGE 2.MODEL NCR * .4 TOX=225E10 NSUB=3.* LOAD CL 12 0 10PF FEEDBACK CONNECTION RF 12 33 100 * * * * * MOSFET PROCESS MODELS NMOS LEVEL=2 CGS0=2.2E6 UO=139 LAMBDA=O.MODEL * + CGDO=2.89E10 VTO=O.1081 1. 02 PCR PMOS LEVEL=2 VTO=0.71 GAMMA=0.5000 VOLTAGE SOURCE CURRENTS NAME VDD VAP VIN CURRENT 3.OOODtOO O.76 GAMMA=0.OP .0208 3.5000 1.35E10 CJ=4.
000 0.OOE+OO O.706 0.376 2.84E13 7.01E14 3.63E15 5.10E07 5.OOE+OO M2 M50 M40 PCH PCH NCH 5.OOE+OO O.OOE+OO M4 M80 NCH NCH 6.062 0.OOE+OO O.OOE+OO O.6 3/15/83********15:44:54***** OPERATING POINT INFORMATION TEMPERATURE = 27.88E15 7.44E05 3.21E06 4.OOE+OO O.47E05 5.000 1.94E15 O.30E06 3.000 1.33E06 3.216 0.10E07 5.000 0.000 0.134 1.91E14 O.389 3.OOE+OO O.OOE+OO O.854 0.134 1.88E15 3.OOE+OO O.47E15 3.021 0.OOE+OO O.33E14 1.66E14 5.79E07 2.216 1.06E13 3.134 3.37E06 8.OOE+OO o .021 0.05E06 5.68E15 1.OOE+OO O.16E15 1.386 1.36E05 7.108 0.31E14 1.23E12 1.41E14 5.OOE+OO O.216 1.763 2.OOE+OO O.63E06 8.108 1.OOE+OO 1.69E15 2.19E05 1.88E15 O.OOE+OO O.09E14 O.24E07 1.49E06 1.OOE+OO O.OOE+OO O.707 0.~  *******01/21/92 CMOS OPAMP **** ******** SPICE 2G.463 4.355 1.68E15 3.36E07 2.OOE+OO O.134 2.68E14 O.47E05 1.134 0.33E14 1.865 0.84E14 2.99E04 1.OOE+OO O.OOE+OO 5.52E05 4.444 0.OOE+OO 4.07E06 5.89E07 2.OOE+OO O.OOE+OO 1.269 0.11 (continued) 334 .OOE+OO 5.OOE+OO O.08E06 5.284 1.15E15 O.29E05 6.55E05 5.021 1.OOE+OO O.38E14 2.72E06 1.59E14 6.710 0.92E04 1.42E05 1.73E15 4.157 1.51E15 2.99E05 3.OOE+OO O.021 1.292 0.59E14 O.OOE+OO O.14E14 1.23E13 2.021 0.86E14 1.OOE+OO 2.48E07 3.92E07 5.68E14 1.271 0.763 1.68E15 O.OOE+OO O.OOE+OO O.19E05 1.134 1.26E13 7.57E14 3.73E:"15 O.844 0.66E14 7.157 1.09E14 1.01E14 3.31E14 1.OOE+OO O.25E14 O.OOE+OO O.72E06 5.49E06 1.000 0.OOE+OO O.OOE+OO 9.506 1.750 1.62E06 8.14E05 3.965 0.OOE+OO O.07E05 2.84E14 O.37E06 1.267 2.965 0.021 0.07E05 6.866 2.284 1.OOE+OO O.51E15 2.94E15 6.64E13 O.OOE+OO M3 NCH 6.332 0.58E15 O.866 1.68E15 1.38E14 2.269 0.00E04 3.OOE+OO O.OOE+OO 1.219 1.OOE+OO MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGOOVL CGBOVL CGS CGD CGB MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGOOVL CGOOVL CGS CGD CGB Figure 10.98E06 5.710 0.27E06 4.03E05 2.25E12 1.265 0.19E05 1.25E14 1.09E14 1.73E15 4.73E15 1.58E13 1.72E06 8.269 3.69E15 2.37E05 6.37E06 5.16E14 O.219 0.92E07 1.OOE+OO O.OOE+OO M30 NCH 5.000 DEG C *********************************************************************** **** MOSFETS M20 M61 M10 M62 M64 M63 M65 PCH NCH PCH NCH PCH PCH PCH 8.OOE+OO 1.OOE+OO O.58E15 7.OOE+OO 7.47E15 3.710 0.80E05 3.OOE+OO O.OOE+OO O.624 3.710 0.16E15 O.219 1.748 0.37E05 2.37E06 1.000 1.14E14 1.OOE+OO O.OOE+OO O.OOE+OO O.293 2.331 3.79E07 1.51E13 3.42E05 5.271 0.000 0.33E06 1.000 0.
The next .500 0. When the above options do not lead to a solution. ITLl. If the ramping methods fail.6 and Sec. the relative convergence tolerance.710 0.76E04 2.OOE+OO O.12 using SPICE2.82E14 O.OOE+OO 2.09E14 1. The external output formed of two emitterfollower stages built for higher current capability with transistors 2N2222 for Q21 and 2N3055 for Q22. 6.114 2.89E14 2.DC CONVERGENCE 335 MODEL ID VGS VDS VBS VTH VDSAT GM GDS 8MB CBD CBS CGSOVL CGDOvL CGBOvL CGS CGD CGB M7 NCH 2.95E06 1.17E03 4.11 ..82E14 1.OOE+OO Figure 10.OOE+OO O. The next step in overcoming a convergence error is to relax the two. the absolute'curr~nttolerance.89E14 5.05E13 O.3) or by identifying cutoff devices with the OFF keyword (see Chap. 3).89E14 M8 NCH 2.13.5 Find the DC bias point of the .500 0.35E04 1.uA74l operational amplifier with an external follower circuit shown in Figure 10.NODESET and.key tolerances which defaults to I pA.28E04 4. EXAMPLE 10.OOE+OO O.35E04 1.000 0. and the steps that lead to a solution will be outlined.9E14 8 5. Solution emitterstage is discrete a unity The simulation of this circuit results in a convergence failure.29E13 O. and RELTOL.444 9.. (continued) ABSTOl. 4. Neither a higher number of iterations. which defaults to 103. Ie (see Sec. nor looser tolerances help the solution of this circuit. The opamp is connected in feedback loop.352 1. it is recommended to use initialization either by setting the values of key nodes with . Especially for MOS circuits the default ABSTOL can be too small.219 2. Next an operational amplifier that fails DC convergence will be considered.710 0. or some of the iteration options must be changed in PSpice and SPICE3.37E04 2 .95E06 1.000 0. the sourceramping mechanism must be invoked in SPICE2.OOE+OO 1.09E14 2. The SPICE input file is listed in Figure 10.
A741 opamp with highcurrent output stage.S soon R. .w W Q'I Vs 1SV VT Qg NPNL R.12 p. SOkn R2 1kn RlO son Vs 1SV Figure 10.
DC CONVERGENCE 337 UA 741 W / POWER OUTPUT STAGE Ql 18 5 24 NPNL AREA=l Q2 18 19 25 NPNL AREA=1 Q3 23 3 25 PNPL AREA=4 Q4 4 3 24 PNPL AREA=4 Q5 3 18 9 PNPL AREA=5 Q6 18 18 9 PNPL AREA=5 Q7 23 21 22 NPNL AREA=l Q8 4 21 20 NPNL AREA=l Q9 9 23 21 NPNL AREA=0. . 5K 6 12 7.5K 1 7 25 8 1 50 29 14 50 29 15 50K 0 2 500 0 5 300M 30 0 3K 9 30 12K (continued on next page) Figure 10.5 Q10 17 17 29 NPN AREA=2 Q11 3 17 16 NPNL AREA=2 Q12 29 6 8 PNP AREA=120 Q13 11 13 9 PNP AREA=30 Q14 13 13 9 PNP AREA=12 Q15 9 11 7 NPN AREA=60 Q16 11 7 1 NPN AREA=3 OFF * Q16 11 7 1 NPN AREA=3 Q17 11 12 6 NPN AREA=7 Q18 6 15 14 NPN AREA=7 Q19 6 4 15 NPNL AREA=5 Q20 4 14 29 NPN AREA=4 OFF * Q20 4 14 29 NPN AREA=4 Q21 9 1 2 2N2222 AREA=l Q22 10 2 5 2N3055 AREA=1 Rl R2 R3 R4 R5 R6 R7 R8 R9 RIO R11 R15 R16 R17 R18 * * * THIS CKT FAILS OC CONVERGENCE * 29 21 50K 29 20 lK 29 22 1K 17 13 30K 29 16 5K 12 11 4.13 SPICE input file for circuit of Figure 10.12.
7 MJS=O.07 VAR=500 IKR=O ISC=O NC=l RB=36 + IRB=O RBM=36 RE=500M RC=l CJE=910F VJE=661M + MJE=294M TF=112P XTF=120 VTF=O ITF=O PTF=O + CJC=835F VJC=l MJC=280M XCJC=0.02167 VAF=50 IKF=3 ISE= + 500P NE=2 BR=8.7 EG=l.11 XTI=3 KF=O AF=1 FC=O.074 VAF=78 IKF=500M + ISE=3.155 BR=4.5 .3 EG=l.11 XTI=3 KF=O AF=1 FC=0.5 .83 ITF=216.37P VJC=1.3P BF=120 NF=1.155 BR=4. 92N + CJS=O VJS=700M MJS=O. 5 XTB=1.MODEL NPN NPN IS=4.07 VAF=260 IKF=100M + ISE=347.074 VAR=500 IKR=O + ISC=O NC=l RB=676M IRB=O RBM=676M RE=100M RC=654M + CJE=22. 5 + XTB=2.5 CJE=6.1 EG=l.471P NE=3.WIDI'H OUT=80 .8 + IRB=80M RBM=100M RE=5M RC=50M CJE=711P VJE=530M MJE=530M + TF=20N XTF=5 VTF=10 ITF=10 PTF=O CJC=650P VJC=580M MJC=400M + XCJC=O.92P NE=1. 8M TF=361.221 VAF=150 IKF= + 150M ISE=2.78F BF=150 NF=1.MODEL * . 7 ITF= + 260M PTF=O CJC=6.MODEL PNP PNP IS=218. 5N CJS=O VJS=O.13 (continued) 338 . 5 * . 5 XTB=l.68 NR=1.5 .67 MJC=406.479F BF=260 NF=1.MODEL PNPL PNP IS=218. 5 .479F BF=260 NF=1.1P NE=3.5 CJE=6. 8M TF=361.3M PTF=O CJC=8. 72P XTF=21 VTF=4. 7 ITF= .92N +CJS=O VJS=700M MJS=O.25P + VJE=916M MJE=389. 5 TR=117.11 XTI=3 + KF=O AF=1 FC=0.333 + MJC=O.25P VJE=1.88F BF=150 NF=1.68 NR=1.394 NR=1. 518 XCJC=O.MODEL 2N2222 NPN IS=166.66 BR=l NR=1.24 VTF=4.5 TR=19.OP *.5 XTB=2. 5 XTB=2.88F BF=150 NF=1.5M XCJC=O.OPT ITL6=40 ACCT .07 VAF=260 IKF=lM + ISE=3.5 TR=lN + CJS=O VJS=700M MJS=0.5 XTB=2.07 VAR=500 IKR=O ISC=O NC=l RB=36 + IRB=O RBM=36 RE=500M RC=l CJE=910F VJE=661M + MJE=294M TF=112P XTF=120M VTF=O ITF=O PTF=O + CJC=835F VJC=l MJC=280M XCJC=O.522 TF=454. 5 TR=400N CJS=O VJS=O.4P + XTF=13.MODEL NPNL NPN IS=4.50M ISE=23.5 .+ 260M PTF=O CJC=6. 5M XCJC=O. 67 MJC=406.34 EG=1.0 29 0 15 9 0 15 2N3055 NPN IS=10.221 VAF=150 IKF= + 1.6P VJC=1.221 VAR=500 IKR=O + ISC=O NC=l RB=12 IRB=O RBM=12 RE=100M RC=1.11 XTI=3 KF=O AF=1 FC=O.C1 11 4 30P VY VT V6 V5 * * 19 30 9 10 0.25P + VJE=916M MJE=389.l1 XTI=3 KF=O AF=1 FC=O.364P NE=2.END Figure 10. 5 TR=19.66 BR=l NR=1. 7 MJS=O. 7 EG=l.221 VAR=500 IKR=O + ISC=O NC=l RB=12 IRB=O RBM=12 RE=100M RC=1.776 BR=2.333 MJE=0.02167 VAR=500 IKR=l ISC=O NC=2 RB=1.3 EG=1. 72P XTF=21 VTF=4.1 NR=1.5 TR=lN + CJS=O VJS=700M MJS=0.11 XTI=3 KF=O AF=1 FC=0.64F NE=2. 6P VJC=l.
9773 4. at 3 V.4726 14. A quick inspection of the operating point of the devices shows that the current through the external transistor Q22 is higher than the current in the class AB output stage of the opamp.8792 14.4057 24) 4. Another way of finding the bias point of this circuit is by understanding the role of each transistor.DC CONVERGENCE 339 step is to use the builtin sourceramping algorithm.526D03 1.000 DEG C *********************************************************************** NODE VOLTAGE NODE 2) 6) 10) 14) 18) 22) 29) VOLTAGE 3. For source ramping the function of IT.0000 14. the positive input of the opamp.14 SPICE DC solution for the circuit of Figure 10. in such a situation it is suggested that the user change ITL2.OPI'IONSITL6=40 The simulation results using this approach are shown in Figure 10.9999 13.4054 25) VOLTAGE SOURCE CURRENTS NAME VY VT V6 V5 CURRENT 3.8958 4.0000 13) 14. Q12 and Q15' The source ramping that is invoked automatically in PSpice fails to find a solution for this circuit.9999 ( ( ( ( ( ( NODE VOLTAGE 4) 13.3784 17) 14.7767 2.9902 15.859D08 9.7862 8) 12) 5.3947 2. .12.50Dt02 WA'ITS (continued on next page) TOTAL POWER DISSIPATION Figure 10.Q19 and the output *******01/21/92 ******** SPICE 2G.753DtOO 3. As can be verified. which is the number of iterations taken at each source value.0097 16) 14.8498 5. As a result of this inspection one can see that transistors Q20 and Q16 have the role oflimiting the current through the gain stage Q18 .8930 20) 14.9902 2.6 UA741 W/ POWER OUTPUT STAGE **** SMALL SIGNAL BIAS SOLUTION 3/15/83********11:58:49***** TEMPERATURE = 27.6087 4.14. which is node 5 and the emitter of Q22.L2 in PSpice is similar to that of !TL6 in SPICE2. the results are correct because of the correct biasing ofthe output.0000 NODE 3) 7) 11) 15) 19) 23) 30) VOLTAGE 1.2969 21) 14.3167 15.0004 9) 15. close to the value of node 19.1871 2.7906 1) 5) 3. This convergence method is exercised by adding the following line to the above circuit file: .00IDtOl 1.4823 14.
896 0. 80E+01 2.104 160.527 0.17E12 3.60E+01 2.32E07 2.595 0.85E06 0.672 12.703 0.62E04 2.733 6.06E13 2.618 28.40E+05 2.92E06 0. 99E+06 1. 29E+07 1.42E10 3.646 8.213 245.40E+05 2.07E14 8.56E04 7.46E03 9.786 1. 65Ell O.87E06 9.622 8.OOE+OO 274. OOE+OO 6.210 126.68Ell 3.43Ell 2.527 147.81E06 0.50E05 0.90E12 6.504 16. 28E+06 Q7 NPNL 3.137 6.14E12 3.703 196.66E+06 4.00E+00 1.000 9.31E+03 4.642 68.777 29.10E12 O.02E+07 (continued) Q10 NPN 4.67E+07 3.222 113.51E04 7.341 7.067 16.829 162.96Ell O.10E08 9.400 6.786 260.14E04 5.623 47.76E+06 3.OOE+OO 148.OOE+OO 266.60E+01 3.94E02 1.OOE+OO 134.18E08 1.90E12 O.06E13 O. 68E+07 6.470 16.23E10 4. 73E+03 4.80E+01 1.000 0.882 4.35E13 O.518 0.60E+01 2.18E06 2.00E+00 2.596 0.50E+05 2.000 0.595 11.881 3.510 15.OOE+OO 262.42E08 1.12E12 O.13E12 3.13E05 8.20E12 2.219 163.93E10 3.00E01 1.52E12 8.78E02 2.36Ell 1.16E+06 Q2 Q3 NPNL PNPL 3.OOE+OO 262.17E04 2.55E+06 1.594 0. 88E+03 1.622 120.10E+08 MODEL IE IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT Qll Q12 NPNL PNP 8.53E04 3.104 1.46E+04 1.17E+05 3.81E06 0.473 15.65E13 O.07E14 O.08E+07 2.10E12 2.73E+07 6.047 1.014 162.193 19.577 13. 65Ell 1.865 3.06E13 5.OOE+OO 251.000 DEG C *********************************************************************** **** BIPOLAR JUNCTION TRANSISTORS Q4 PNPL 6.38E+07 6.36E+05 Q13 Q14 PNP PNP 2.394 3.75E+07 1.69E04 2.OOE+OO 251.11E04 7.85E+06 Q6 PNPL 1.85E06 9.37E+05 3.6 3/15/83********11:58:49***** UA741 W/ POWER OUTPUT STAGE OPERATING POINT INFORMATION **** TEMPERATURE = 27.789 19.06E13 5.12E12 5.65E+07 6.51E04 7.20E+01 2.86E08 6.42E02 6.622 0.472 12.40E+00 7.510 11.595 0.29E04 6.067 255.77E13 1.OOE+OO O. 61E+05 3.73E+05 7. 14E+06 MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT Q1 NPNL 3.809 8.OOE+OO 163.182 255.14 . 66E+06 4.80E06 2.26E12 8.05E08 9.68Ell 3.55E13 O.395 274.89E08 9.OOE+OO 160.95E05 0.OOE+OO 235.873 3.796 8.77E13 1.60E+01 2.55E13 3.381 245.99E08 9.~_.445 1.96Ell 4.26E+05 3.203 8.99E08 9. 12E+06 Q5 PNPL 1.12E05 0.08E10 1. 31Ell 9.691 3.527 12.21E+05 3. 17E+05 3.722 3.65E+07 6.04E05 8.52E04 0.42E+05 5.489 7.32E+07 Figure 10.94E06 0.43Ell 5.OOE+OO O.40E+00 7.42E10 O.476 1.OOE+OO O.38E+05 7.618 1.69E03 3.706 3.35E13 8.36Ell 6._ 340 10 CONVERGENCE ADVICE *******01/21/92 ******** SPICE 2G.32E07 1.317 16.11E+06 Q9 NPNL 4.00E01 1.65E13 3.56E+04 1.28E04 0.21E05 0. 56E+06 Q8 NPNL 3.611 8.
633 9.04E+03 6.518 10.28E+06 Q16 NPN 9.96E+00 1.16E13 O.20E+00 9.84E05 0.81E+08 Q19 NPNL 1.71E+11 3. Adding the keyword OFF at the end of the lines corresponding to these transistors and commenting out the line defining ITL6 result in the quick convergence of the circuit.97E11 O.37E02 2. 27E12 1.33E03 0. 05E+08 MODEL IB IC VEE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETMC FT Q15 NPN 2.109 8.74E+11 2.28E03 2. 20E+01 9.166 184.58E09 4.76E+03 5.23E+06 Q20 NPN 3.150 92. 25E+00 MODEL IB IC VEE VEC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETMC FT Figure 10.55E11 1.46E02 2.000 39.40E03 0.10E12 0. 33E12 O.91E11 9.00E01 1.07E01 6.75E+00 0.26E05 2.121 1. 16E+05 2.04E10 1. Another circuit that demonstrates the need . 391 0.45E12 0.16E13 9.692 0.615 8.DC CONVERGENCE 341 Q21 2N2222 2.47E+02 1.797 2.54E01 0. In normal operation these two transistors should be turned off.002 4.648 1.633 0.13E+02 1.14E+00 1.OOE+OO 22. 14E+00 1.OOE+OO 0.OOE+OO 86. 31E01 Q17 NPN 1.48E01 9.745 1.11E12 4. 30E11 O. 12E+05 2.513 8.08E11 2. The above example has illustrated how both source ramping and the OFF initialization of transistors can lead to a solution. 86E+07 1.00E+00 9. 11E+08 Q22 2N3055 2.07E11 9.38E12 1.344 2.76E+06 2.000 1.977 11.OOE+OO 268.406 1. 15E+05 9.691 7.81E01 6.02E03 2.925 18.63E+05 7. 11E11 1.34E03 0.059 0. respectively. 05E08 1.813 10.OOE+OO 246.504 256. 24E+01 6.14 (continued) transistor Q15.81E12 1.90E+07 9.38E12 O.473 1.11E07 2.27E12 O. in only 11 iterations in SPICE2.693 0.271 1.09E12 1.76E01 3.62E12 O.215 5.OOE+OO 172.30E11 1.023 12.53E05 2.22E+00 1. 84E+03 5.186 6.196 195.001 1.209 11.12E11 1.001 5.692 18.09E12 O. PSpice and SPICE3 also converge easily to a solution.62E12 2.OOE+OO 0.86E12 1.578 17.797 5.023 111.49E05 9. 11E+08 Q18 NPN 1.65E02 2.23E05 2.504 19.OOE+OO 230.33E12 1.
16.15 Bistable circuit with /LA 741 opamps. implemented with two J. including source ramping.LA741 opamps as the gain stages. given in Sec. This circuit. EXAMPLE 10. may fail to lead to a solution for this circuit depending on the model used for the opamp. All the approaches mentioned above.28).15 prior to computing the response to a sawtooth input voltage VA. containing highgain stages and highimpedance nodes.15.1 (Figure 7.6 Find a DC solution to the bistable circuit shown in Fig. The subcircuit definition of UA741MAC has to be copied from Figure 7.28 into the deck of Figure 10. @ CD R2 Rs 10kQ D4 @ 100 kQ 0  @ R4 10kQ Da  Ra 10kQ I 0 Rs 15 kQ ems VEE=15V 0 Figure 10. 7.342 10 CONVERGENCE ADVICE of initialization is the bistable circuit in Figure 10. The macromodel UA741MAC. Solution The input description of the circuit is listed in Figure 10. is one that requires +Vcc=15V CD D.LA741.5.16. . 10. D2 R7 15kQ @ +vcc 0 R. is used for the J.
7~2S * * .OPTIONS ACCT .11 XTI=3 KF=O AF=1 FC=O.END SPICE input for bistable circuit with JLA741 opamps.BISTABLE CIRCUIT WI UA741 OPAMPS *VA 3 0 15 VA 3 0 DC .5M 0 * 15 13 M1M1N914 AREA=l 13 15 M1M1N914 AREA=l 9 16 M1M1N914 AREA=l 16 11 M1M1N914 AREA=l * .6 *.55 TT=5N CJO=l.TRAN .ENDS .S5P + VJ=650M M=lS0M EG=1.PLOT TRAN V(3) V(15) V(13) V(S) V(4) * * * INITIALIZATION FOR VIN=15 .OUT VCC VEE * INSERT UA741 MACROMODEL DEFINITION FROM FIG. Figure 10.OP .SUBCKT UA741MAC 3 2 6 7 4 * NODES: INt IN.OPTIONS ITL1=300 ABSTOL=lU .WIDTH OUT=SO .NODESET V(4)=15 'V(13)=.MODEL M1M1N914 D IS=lN RS=500M N=1.16 343 .15 PWL 0 151M VCC 1 0 15 VEE 2 0 15 D1 D2 D3 D4 * 152M 15 2.5 BV=120 IBV=l ' R7 R6 R5 R4 R2 R1 * 1 11 15K 11 4 10K 9 2 15K 4 9 10K S 13 lOOK 15 3 10K RESISTOR * *'FEEDBACK R3 4 15 10K * CNS S 0 1P CN15 15 0 1P XOPA1 0 15 13 1 2 UA741MAC XOPA2 0 S 4 1 2 UA741MAC * * * * .6 V(l5)=O V(S)=.OlM 2M 0 .
0 Figure 10.6V and 0.5 2. The highimpedance opamp input.0003 0.NODESET V(15)=O V(13)=O. As described in Example 4. for an NMOS flipflop SPICE finds the metastable state as solution.17. node 13. one of the states of this circuit can be specified with the following • NODESET statement: o . > oj ~ g 0.344 10 CONVERGENCE ADVICE the initialization mentioned in the previous section.0 Time.17 Transient response of V ( 4) to triangular input V ( 3 ) .16 the following refineo v (15) V ( 13 ) V(B) = 0. Therefore. ms 1. nodes 8 and 15. as well as the opamp output. This state corresponds to all inputs and outputs of the opamps being at V. must be initialized.5 1.8.6 V. The waveform at node 4 together with the triangular input voltage is shown in Figure 10. nodes 4 and 13.6 V(8)=O.6 V(4)=15 With this line added to the circuit description solution is obtained: of Figure 10. with the input at a very low value.5964 = = = 0. . is limited by the two diodes D1 and Dz to between 0.6983 V(4) Note that a DC solution is a prerequisite for a transient analysis unless the UIC keyword is used on the • TRAN line. The output of XOPAl.5452 12. in this case an • IC line should be used to define the initial state of the circuit in order to avoid a convergence failure at the first time point.
18. . Highimpedance nodes are common in CMOS and BiCMOS circuits using cascode configurations. A good example for a difficult convergence case is the BiCMOS reference circuit shown in Figure 10.18 BiCMOS bias reference circuit. NPN NPN 9kO o @ Vss Fi~ure 10.DC CONVERGENCE 345 Circuits with highimpedance nodes are often difficult convergence cases for circuit simulators. initialization and variations in model parameters and complexity can help convergence. For such circuits a combination of ramping methods.
set by parameter NFS. therefore we expect the current in the left branch to be approximately five times the current in the right branch. represented by parameters VMAXand NEFF. represented by parameters UCRIT and UEXP. For more details on the semiconductor device physics see the works by Muller and Kamins (1977) and by Sze (1981). and mobility modulation by the gate voltage.3) Because of the cascode currentsource configuration the drain connections between transistors M3 and Ms and between M4 and M6 are highimpedance nodes. represented by parameter DELTA. A first approximation is to neglect for all MOSFETs the smallsize effects. The complete model equations for LEVEL=2 can be found in Appendix A or in the text by Antognetti and Massobrio (1988). respectively. such as narrowwidth modulation of the threshold voltage.346 10 CONVERGENCE ADVICE EXAMPLE 10. current source Solution The areas of the MOS transistors in the left branch are five times the areas of the MOSFETs in the right branch of the circuit. and velocitylimited saturation.18. Deletion ofVMAX and NEFF as well leads to a SPICE2 solution in only 25 iterations. The LEVEL=2 model includes such secondorder effects as subthreshold conduction. namely. The second approach recommended in convergence cases of circuits using complex models is to eliminate some of the secondorder effects. The currents in the right and left branches are 4.7 Find the currents in the two branches of the thermalvoltagereferenced in Figure 10. set the ITL6 option in SPICE2 to invoke the sourceramping method. Note that a model of higher accuracy is used for the MOSFETs than the one described in Chap. PSpice finds a solution after source ramping. First. which make convergence to the DC solution difficult. and SPICE2 requires ITL6 to be set to 40 for convergence.19. represented by parameters VMAXand NEFF. The solution to the SPICE input of Figure 10. 3.3 /LA.20. as five transistors connected in parallel.19 is the DC operating point shown in Figure 10. Two approaches are suggested for solving this convergence problem. which can be estimated from the VBE difference of the two identical BJTs (Gray and Meyer 1985): Vth 1= Rln5 = 4. consistent with our estimates. This is achieved by deleting the DELTA parameter from the •MODEL statement. The transistors with the larger area are modeled as they are implemented on the layout.6 /LA (10. For the input specification of this circuit shown in Figure 10. saturation due to carrier velocity limitation.66 /LA and 23. A rerun of the circuit results in the desired solution in SPICE2 in 96 iterations without the need of ramping. .
WIDTH OUT=80 .5E6 LD=.OPTION ABSTOL=lN .5E6 LD=.8E4 UEXP=0.5 NFS=3E11 * * * + IKR=lE3 .l + VMAX=5E4 NEFF=4 DELTA=4 NFS=4E11 .5E6 U0=220 UCRIT=5.8 TOX=500E10 NSUB=2E15 + XJ=0.MODEL P PMOS LEVEL=2 + VTO=0. 347 .8 TOX=500E10 NSUB=1.MODEL NPNMOD NPN IS=2E17 BR=.3E16 + XJ=0.OPTION ACCT DEFL=10U *.MODEL N NMOS LEVEL=2 + VTO=O.BIOMOS BIAS REFERENCE Q1 10 10 3 NPNMOD 400 Q2 10 10 1 NPNMOD 400 R1 1 2 9K M1A 8 12 11 11 N M1B 8 12 11 11 N M1C 8 12 11 11 N M1D 8 12 11 11 N M1E 8 12 11 11 N M2 12 12 11 11 N M3A 6 13 8 11 N M3B 6 13 8 11 N M3C 6 13 8 11 N M3D 6 13 8 11 N M3E 6 13 8 11 N M4 13 13 12 11 N M5A 6 6 4 10 P W=60U M5B 6 6 4 10 P W=60U M5C 6 6 4 10 P W=60U M5D 6 6 4 10 P W=60U M5E 6 6 4 10 P W=60U M6 13 6 5 10 P W=60U M7A 4 4 3 10 P W=60U M7B 4 4 3 10 P W=60U M7C 4 4 3 10 P W=60U M7D 4 4 3 10 P W=60U M7E 4 4 3 10 P W=60U M8 5 4 2 10 P W=60U VDD 10 0 5 VSS 11 0 5 .5E6 U0=640 UCRIT=6E4 UEXP=O.19 SPICE description of BiCMOS bias reference circuit.OP .4 BF=100 ISE=6E17 ISC=26E17 IKF=3E3 + VAF=100 VAR=30 RC=100K RB=200K RE=lK .18 + VMAX=3E4 NEFF=3.END * DEFW=20U Figure 10.5 DELTA=2.
01E07 1.248 2.152 1.841 0.51E05 2.841 0.51E05 1. 01E07 1.000 0.139 5.25E05 M3A N 4.248 2.66E06 1.000 DEG C **** *********************************************************************** NODE 1) 5) 11) VOLTAGE 4.248 2.000 0.2169 5.165 0.4778 3.248 0.60E08 1.165 0.318 1.564 0.66E06 1.66E06 1.25E05 M2 M1E N N 4.4359 1.54E05 5.000 0.01E07 1.78E04 4. 25E05 M1C N 4.66E06 1.25E05 M1B N 4.8484 NODE 3) 8) 13) VOLTAGE 4.165 0.51E05 1.90E04 9.000 0.2322 5.152 1.841 0.841 0.522 0.248 2.25E05 1.60E06 0.000 0.0000 SOURCE NODE 2) 6) 12) CURRENTS VOLTAGE 4.14E+07 **** MOSFETS M1A N 4.51E05 1.4360 3.000 0.6 WATTS 3/15/83********15:57:31***** TOTAL POWER *******02/11/92 BICMOS BIAS REFERENCE OPERATING POINT INFORMATION TEMPERATURE = **** 27. 01E07 1.66E06 1.66E06 4.8354 2.01E07 1.522 72.20 DC operating point of BiCMOS reference circuit.798D05 2.152 1.25E05 M1D N 4.000 DEG C *********************************************************************** **** BIPOLAR JUNCTION TRANSISTORS MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO Q1 NPNMOD 2.8759 3.6 3/15/83********15:57:31***** BIAS REFERENCE SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.841 0.51E05 1.30E05 0.152 1.711 0.84E07 2.80D04 ******** SPICE 2G.51E05 1.67E+04 5.152 1.00E+02 2.66E06 1.833 0.000 0.6967 NODE 4) 10) VOLTAGE 3.152 1.248 2.36E08 4.564 81.152 1.165 0.46E+05 5. .000 0.841 0.798D05 DISSIPATION 2.246 2.348 10 CONVERGENCE ADVICE *******02/11/92 BICMOS ******** SPICE 2G.26E05 MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB Figure 10.0000 VOLTAGE NAME VDD VSS CURRENT 2.26E+06 Q2 NPNMOD 6.165 0.116 8.00E+02 4.01E07 1.000 0.
60E08 1.204 1.29E06 4.60E. .29E07 4.275 0.711 0.270 .60E08 1.152 1.98E05 1.29E06 3.66E06 1.000 0':833 0. 4. 097 1.204 0.097 1.98E05 2.152 0.66E06 1.58E06 M7E M8 P P 4.204 1.66E06 1..564 0.58E06 4.29£06 M7C P 4.711 0.98E05 1..58E06 MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB M5C P 4.841 0.66E06 1.04E05 1.204 1.768 1.58E06 p.270 0.29E07 4.66E06 1.54E05 5.270 2. 0.2.66E06 1.66E06 4. The advantage of timedomain analysis for solving circuits with positive feedback and high loop gain resides in the presence of charge storage elements..29E07 1. 4. 5.219 0.270 2.204 0.139 5.54E05 5.66E06 4.29E06 3.356 5.097 1. 783 0.000 0.564 0.98E05 2.54E05 5.66E06 .14E05 1.66E06 1.98E05 1. 31E07 1.356 1 :356 1.204 1..51E05 1.564 1.i75 0.246 2.711 0.204 1.':1'.139 . Another approach to 'finding the DC bias point of a circuit is to ramp up the supplies in a transi~nt analysis.31E07 3.26£05 M5A M5B P P. .000 0.54E05 5.341 1.246 2.000 0. initialization of critical nodes can be used to obtain convergence of the circuit using the complex models and default tolerances.29E'06 .939 0. 01E07 1. which do not allow instantaneous switching to take place.356 1.356 1.08 1.26E'05 4.06 4.P P P P 4.711 0.356 1. 31E07 1.939 0.DC CONVERGENCE 349 M3B MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB N N M3C N M3D N M3E N M4 4. 29E07 4.939 0.939 0..246 2.270 0.66E06 4.31E07 1. Another possible' approach is to increase the values of ABSTOL and RELTOL.204 1.58E06 Figure 10.37E~06 3.275 3.248 2. 00E07 1.275 0. which displays very abrupt switching at the two thresholds.139 5.29E07 3.04E05 3.58E06 4.356 1.091 0.26E05 ..267 0.29E07 1. This method is applied in the next example to obtain the hysteresis curve of a CMOS Schmitt trigger.275 3.768 1.246 2.914 1.833 0.939 0.66E06 1:356 1.66E06 1.939 0.270 2. MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB M7D P 4. M5E M6 M7A M7B . 356 1.204 ~1.564 0. 768 1. 768 1.139 5.20 ( continlfed) This example shows that both source ramping and selective deletion of some secondorder effects can lead to convergence for CMOS and BiCMOS circuits. 768 1..04E05 3. 097 .04E05 1.31E07 3.564 .097 0.04E05 3.26E05 M5D 4.204 1.60E08 1.25E05 4.564 0.0.204 1.66E.833 0.66E06 4.833 0. Once a solution is obtained.000 0.356 1.66E06 4.66E06 1.98E05 3.
presented in Sec. Vo can be computed while Vi first increases from 0 to Vee and then decreases from Vee to O.21 CMOS Schmitt trigger circuit. All transistors have the same geometry.8 Compute the hysteresis characteristic of the CMOS Schmitt trigger (Jorgensen 1976) shown in Figure 10. Solution The most appropriate analysis for computing the transfer characteristic is • DC. The n. Compare the results from PSpice and SPICE2. The positive and negative thresholds of the hysteresis curve are set by the voltages at nodes 5 Figure 10. use LAMBDA 0. .350 10 CONVERGENCE ADVICE EXAMPLE 10. The output voltage.05 VI for both transistors.3.and pchannel transistors have the following LEVEL=l model parameters: NMOS: VTO=2 PMOS: VTO=2 KP=20U KP=lOU RD=lOO RD=lOO CGSO=lP CGSO=lP If a finite output conductance in saturation needs to be modeled. the DC sweep analysis.21. 4. with W = 10 /Lm and L = 10 /Lm.
Ms turns on and the voltage at o node 5 is set to approximately ~ Vee.DC CONVERGENCE 351 and 3.5) CMOS SCHMITT TRIGGER * * THIS CIRCUIT DIES IN . This value of V biases M3 off and M6 on. pchannel transistors Ml and M2 are turned on and nchannel transistors M4 and Ms are off. DC AROUND VT+ AND vr.TRAN CAN PROVIDE * FOR IMPROVED CONVERGENCE LAMBDA > 0.TRAN 1N 200N .\VTOP\ (10.PROBE •END 0 CGsa=lP RD=100 RD=100 Figure 10.MODEL N NMOS VTO=2 KP=20U *+ LAMBDA=0. M1 2 1 3 2 P * M2 3 1 4 2 P M3 043 2 P M4 4 1 5 0 N M5 5 1 0 0 N M6 2 4 5 0 N . When Vi == Vs + VTOn. CAPS IN MODEL. ONLY A .OPTION ABSTOL=100N *. When Vi == VTOn. respectively. This point is the positive switching threshold. which define the two thresholds. . The transistors M2 and M4 form a comparator. * PSPICE SOURCE RAMPING CANNar SAVE IT.05 VCC 2 0 12 VI100 *VI 1 0 6 PWL 0 0 lOON 12 200N . M4 starts turning on. while the pchannel transistor pair MIM3 and the nchannel transistor pair MsM6 are voltage dividers.OPTION DEFL=10U DEFW=10U . When Vi is 0.22 SPICE input for CMOS Schmitt trigger.1 *. triggering regenerative switching and resulting in Vo going to 0 V and transistors M2 and M6 turning off. 05 CGsa=lP .DC VI 0 12 0. except that the switching point occurs at Vi == Vst == Vee 2 . or 2 V. THE HYSTERESIS.MODEL P PMOS VTO=2 KP=10U *+ LAMBDA=O. Vst+ of the Schmitt trigger and is equal to Vst+ == 2 + VTOn Vee (10A) The same process takes place when Vi is varied from Vee to 0. with Vo at Vee.
After the addition of LAMBDA. In order to demonstrate the importance of the charge storage in the circuit it is left for the reader as an exercise to remove CGSO from both •MODEL definitions in Figure 10. The analysis of this circuit fails both in SPICE2 and PSpice. VI must be changed in the input circuit to include the ramping in time. 12 10 8 > 6 ~ 6 4 2 o .22.I . finite output conductance is modeled when a value is specified for LAMBDA in the •MODEL statement. any SPICE simulator can fail to converge in DC analysis when strong regenerative feedback is present in the circuit. and the • TRAN line must be added in Figure 10. In the basic LEVEL=l model. The two switching points agree between the two programs and analyses.I . In general. and specifying LAMBDA is necessary only when the internal value must be overridden. The approach to curing this problem is to find a timedomain solution rather than a DC solution. The hysteresis of the Schmitt trigger is shown in Figure 10. with Vi rising to Vee at 100 ns and falling back to 0 at the end of the analysis interval.I I I I I I o Figure 10. A basic rule when simulating stacked CMOS transistors is to provide a finite output conductance in saturation for all transistors.I .I ' I . at 200 ns.I 2 . SPICE2 completes the DC transfer characteristic. . Vst+.23 4 VI' V 6 8 10 12 Hysteresis curve of the Schmitt trigger.22: VI 1 0 0 PWL 0 0 lOON 12 200N 0 .352 10 CONVERGENCE ADVICE The SPICE input circuit is listed in Figure 10. PSpice however fails to converge when Vi reaches the positive switching threshold. Models of higher LEVEL compute a finite conductance internally from process parameters.23: it is the plot of Vo as a function of Vi.22 and observe the result of the analysis.TRAN 1N 200N The solution is obtained over 200 ns. by sweeping Vi over time from 0 V to Vee and then back to 0 V. Every SPICE program can complete this analysis.
iterations. whereas PSpice does not offer this choice. SPICE2 differs from SPICE3 by offering the user the choice of the timestep control method through the LVLTIM option. If LVLTIM = 1. The most important causes for convergence failure are incomplete semiconductor model descriptions and lack of charge storage elements. are addressed. By default the time step is controlled by the truncation error in both programs. the three SPICE versions used in this text differ slightly in the implementation of the integration algorithms and the control a user can exert on the timedomain solution. models described only by the default parameters are often the cause of a transient analysis failure. Figure 10.TIMEDOMAIN CONVERGENCE 353 10. .24 Diode rectifier circuit. corresponding to LVLTIM = 2 in SPICE2. Then perform a second analysis including the breakdown voltage for the two diodes. In addition.9 Use SPICE to compute the timedomain response of the circuit shown in Figure 10. EXAMPLE 10. convergence failure and accuracy. As in the case of DC analysis.24. an iterationcount timestep control is used in SPICE2. The model parameters of the diodes are IS = 1014 A and CiO = 10 pF. and PSpice exclusively uses the Gear algorithm. that is. Ideal representations of semiconductor devices. Through the METHOD option SPICE2 and SPICE3 offer the user the choice between trapezoidal and Gear variableorder integration. SPICE2 and SPICE3 use trapezoidal integration by default. equal to 10. which doubles the time step at any time point when the program does not need more than 3 iterations to converge. In the following examples both potential traps of timedomain solution. BV = 100Y. and cuts it by 8 when convergence is not reached within ITL4. The following example illustrates a TIME STEP TOO SMALL (TSTS) failure due to an incomplete model used to represent a diode in a fullwave rectifier circuit.4 TIMEDOMAIN CONVERGENCE This section addresses the convergence problems that can occur during a transient analysis and the ways to overcome these problems.
which is followed by an RLC lowpass filter. ms Figure 10.26. driven by the two sinusoidal sources represent a fullwave rectifier.24 the two diodes.26 Rectifier waveforms for no BV. which is the peak value and is reached when the voltage at node 3 reaches its lowest point.MODEL DIO D IS=1. 8 > € > 0 ~ > 70V 0 10 20 30 40 50 60 Time. and the voltage waveforms at nodes 3 and 4 are plotted in Figure 10.0 R2 4 0 10K C2 4 0 2UF IC=80 .OPT ACCT .354 10 CONVERGENCE ADVICE CHOKE CKT .WIDTH OUT=80 • END Figure 10. .TRAN 0. The . SPICE input file for this circuit is listed in Figure 10. The output voltage on capacitor C2 is initialized at 80 V. Solution In the circuit of Figure 10. D1 and D2.FULL WAVE CHOKE INPUT VIN1 1 0 SIN(O 100 50) VIN2 2 0 SIN(O 100 50) Dl 1 3 DIO D2 2 3 DIO R1 3 0 10K L1 3 4 5.25.2MS 200MS UIC .PLOT TRAN V(1) V(2) V(3) V(4) .25 SPICE input for diode rectifier.0E14 CJO=10PF .
TIMEDOMAIN CONVERGENCE 355 100V ~ > 100 100V 100 50V g > ff > 0 50V 0 10 20 30 40 Time. In reality a careful sizing of the series resistors is necessary in order to limit the reverse current to the maximum value prescribed in the data book and avoid destruction of the diode. .. D2 breaks down when V ( 1) reaches 50 V and V ( 2) reaches .. ms ~ > 50 60 70 Figure 10. Note that because of the diode reverse conduction the voltage at node 3 is clamped at 50 V. . and the two diodes could be destroyed in reality.. a current path exists from one signal source to the other through the series combination of the two backtoback diodes. the value of parameter BV is added to the • MODEL line. The addition of series resistance for limiting the current solved the problem. Resimulation of the circuit with RS=l 00 added to the. The solution to this problem is to add a parasitic series resistance. This example has illustrated a failure condition that can develop during the transient analysis because of an ideal model and improper circuit design. Resimulation of the circuit results in a TSTS error in PSpice and a numerical exception in SPICE2. Because of the ideality of the diodes in the previous analysis only one is conducting at anyone time and proper current limiting is provided by the load circuit.50 V.27 Rectifier waveforms for BV = 100.27. Analysis failure can also occur because of insufficient charge storage in a circuit. to the diode model. When a breakdown characteristic is added to the diodes at 100 V. This issue is presented in the following example. which does not happen in reality and cannot be handled by the existing solution algorithms. MODEL line in Figure 10.25 results in the waveforms V (3) and V (4) shown in Figure 10. RS. In order to model the breakdown characteristic of the diode in the reverse region. In the absence of charge storage elements a circuit tends to switch in zero time. which limits the current when Dr or D2 operate in the breakdown region.
LS. The model parameters for the enhancement and depletion transistors are LEVELF=l V'IO=O.356 10 CONVERGENCE ADVICE EXAMPLE 10. .4 ms. MODl and MOD2. 01 transistor) (depletion transistor) Solution The input description for SPICE is listed in Figure 10.10 Simulate the behavior of the NMOS relaxation oscillator shown in Figure 10.Lsto 1800 J. h. The transient response is requested to be displayed only from 1400 J. 7 LEVELF=l V'IO=O. CGSO. MODEL statement.28 (Kelessaglou and Pederson 1989) using SPICE. to the two models.23 J. It is necessary to correct the ideality of the MOSFET models by adding a gatesource capacitance.29. is used only to kickstart the oscillations. The period and pulse width can be verified by hand using the GDS values printed in the operating point information for depletion devices Ms and Mg. Note that the current source. SPICE computes the waveA form starting from 0 but saves only the results after t = 1.2.30.28 NMOS relaxation oscillator. In SPICE2 the analysis fails at t = 46. Also note that the substrates of all transistors are connected at VEE = 9 V. hen the time step is reduced below w a minimum value set by the program to be 109 of the smaller of2 X TSTEP or TMAX. the transient analysis finishes successfully. the resulting waveforms are shown in Figure 10. 6. KP=30U 7 KP=30U (enhancement LAMBDA=O.LS. After CGSO=l P is included in the. s pointed out in Sec. The first observation is that the MOS transistors do not have any capacitances given in the • MODEL statement. Figure 10.
5 Figure 10.MODEL MOD2 NMOS VTO=O. and V (5) for the NMOS relaxation oscillator.30 Waveforms V (1) .29 SPICE input for NMOS relaxation oscillator.END Figure 10.OPTION NOPAGE NOMOD LIMPTS=1001 ITL5=O . ms 1.TRAN 2U 1800U 1400U . 7 KP=30U *+ CGSO==lP . ~ > 0 > 5 ~ > 0 0. .MODEL MOm NMOS V'I'CPtO. V (4) .OPTION ACCT ABSTOL=lN .WIDI'H OUT=80 .7 KP=30U LAMBDA=O. V (2) .Ol *+ CGSO==lP .OP .5 Time.0 1.PLOT TRAN V(5) V(l) V(4) .TIMEDOMAIN CONVERGENCE 357 MOS RELAXATION OSCILLATOR M1 2 1 0 6 MOD1 W=100U L=5U M2 4 5 0 6 MOD1 W=100U L=5U M3 3 2 2 6 MOD2 W=20U L=5U M4 3 4 4 6 MOD2 W=20U L=5U M5 3 1 1 6 MOD2 W=20U L=5U M6 1 0 0 6 MOD2 W=20U L=5U M7 3 5 5 6 MOD2 W=20U L=5U M8 5 0 0 6 MOD2 W=20U L=5U C1 2 5 lOOP C2 4 1 200P VEE 6 0 9 VDD 3 0 5 11 5 0 PULSE lOU 0 0 0 0 1 .
the effect of this parameter is that when a diode is switched off it takes a finite time to eliminate the carriers from the neutral region.1N 50N lOON .MODEL DMOD D RS=lOO + TI'=40N *+ CJO=lOP . This numerical oscillation can be avoided by selecting the Gear algorithm or controlling the tolerances for a tighter control of the truncation error. the integration method should be changed to the secondorder Gear . The waveform of the diode current resulting from the SPICE simulation is plotted in Figure 10.358 10 CONVERGENCE ADVICE The above examples have focused on the main causes for the failure of transient analysis and on how to overcome them.OPTION METHOD=GEAR MAXORD=2 . The following example illustrates ringing around the solution. The trapezoidal method was seen to oscillate around the solution for values of the time step that are larger than a limit related to the time constant of the circuit. Another important issue is the accuracy of the solution computed by the transient analysis. Current ringing around the value of zero can be noticed following the storage time.31.11 Find the waveform of the current flowing through the diode D] in Figure 10. Several observations were made in the previous chapter on the stability of numerical integration algorithms. Solution DIODE SWITCHING D1 1 a DMOD VIN 1 0 PULSE 5 5 50N .6 when a voltage step from 5 V to 5 V is applied to the circuit.PLOT TRAN I (VIN) * . This behavior can be noticed in the computed response of a circuit.1N .WIDTH OUT=80 • END * The SPICE input description is listed above. For the first analysis use the default model for the diode with the following two additional parameters: RS=100 TT=40N The parameter TT is a finite transit time of the carriers in the neutral region of the diode.5N lOON . and during this time the diode conducts in reverse direction. EXAMPLE 10. which results in a smaller time step. especially when the circuit switches. This result can be explained only by the oscillatory nature of the trapezoidal integration method. Whenever the simulated response of circuits displays oscillations that are not anticipated by design. during which the diode conducts in reverse.'IRAN .
a gradual decay of the current is expected with a time constant equal to CjRs. RS. Numerical ringing can . After the. The charge storage of the diode is incomplete without the depletion region charge (see Sec. This last observation leads to the conclusion that the more complete the model. and series resistance.31. 6. addition of the above line to the input. TT. It can be noticed that the current returns to zero with minimal numerical ringing. If this charge is modeled by specifying a value for the parameter CJO on the •MODEL line. a few comments are necessary about the impact of transient analysis parameters TSTEP and TMAX on the accuracy of the result. In Sec. A new simulation with CJO added and the default trapezoidal integration yields the third current waveform shown in Figure 10. The latter can also be caused by imperfections in the builtin analytical models in SPICE in addition to the absence of certain model parameters. repeating the simulation yields the second waveform shown in Figure 10. A common cause for numerical oscillation is sudden changes in a circuit variable or in the model equations. which controls the number of points evaluated for a signal each period.2). 3. Next.31. The model of the diode used in this example is ideal except for the finite transit time.4 the accuracy of the Fourier coefficients calculation was shown to depend on the value of TMAX. method by adding the following line to the SPICE input: •OPTION METHOD=GEAR MAXORD=2 The secondorder Gear method is characterized by numerical damping. the more accurate and stable is the solution. ns Figure 10. which exhibits the expected behavior.31 Diode current computed with trapezoidal and Gear 2 integration methods and C].TIMEDOMAIN CONVERGENCE 359 BOmA z ~ 0 40 BOmA TRAP z ~ 0 40 BOmA GEAR 2 z ~ 0 CJO+ TRAP 40 Time.
the more time points are computed. also be avoided by selecting smaller values for TMAX or reducing the relative tolerance In general.33.32 CMOS in verter circuit diagram. The graphical solution of the inverter current in Figure 10. The SPICE input description and model parameters are listed in Figure 10. incorrectly displays ringing of 10 /LA after reaching the peak value. computed with the default trapezoidal method. An alternate way to obtain the correct solution is to limit the maximum time step the program takes during the trapezoidal integration. + Figure 10. EXAMPLE 10. The same current computed with the Gear 2 method is smooth and overlaps the trapezoidal solution in Figure 10. A value of 50 ns added to the • TRAN line in Figure 10. the more accurate the results. Modeling the subthreshold current with parameter NFS added to the device specification has an effect on the result similar to that of the Gear integration. Solution Current flows through the inverter only for values of VIN from 1 V to 9 V. The input voltage is ramped from 0 V to 10 V over 10 /LS. . that is.33 also leads to a smooth waveform.34.360 10 CONVERGENCE ADVICE RELTOL.12 Simulate the current flowing through the CMOS inverter shown in Figure 10. Sometimes the maximum time step must be set by the user in order to obtain an accurate solution.32. a smooth current waveform.34.
TRAN 200N lOU .66E9 MJSW=.4E+S NEFF=3 KF=.l + VMAX=1.7U LD=.WIDTH OUT=80 .4E3 MJ=.28E9 CGBO=.34 methods.4E+4 UEXP=.69 PB=.49 CJSW=.6 PB=.46 CJSW=.6E9 MJSW=.TRAN 200N lOU 0 SON .8 CGSO=.33 SPICE description of CMOS inverter.2SE9 + CJ=.28E9 CGDO=.6SE+16 NSS=lE+11 + TPG=l XJ=.9 GAMMA=.END * M1 * * * Figure 10.26 TOX=.38E6 UO=610 UCRIT=S.28E9 CGDO=.SE16 NSS=lE11 + TPG=l XJ=.8 GAMMA=.2E+4 UEXP=.2SE9 + CJ=.24 TOX=.18 + VMAX=.MODEL PMOS PMOS + LEVEL=2 VTO=. ~ ~ 300 100 o Time.0E32 AF=1.SE7 NSUB=.0 + NFS=lEll .2E+S NEFF=3 KF=1.SE7 NSUB=.8 CGSO=.0 + NFS=lEll *.S2U UO=230 UCRIT=S.TIMEDOMAIN CONVERGENCE 361 CMOS INVERTER 2 1 0 0 NMOS + L=10U W=20U AD=160P AS=160P PD=36U PS=36U VM 21 2 M2 21 1 3 3 PMOS + L=10U W=40U AD=1600P AS=1600P PD=216U PS=216U VIN 1 0 PWL 0 0 lOU 10 VDD 3 0 10 . ~s Figure 10.PLOT TRAN I(VM) .28E9 CGBO=.MODEL NMOS NMOS + LEVEL=2 VTO=.2E32 AF=1.SE6 LD=. CMOS inverter current computed with trapezoidal and Gear 2 integration .3E3 MJ=. '3.
02 An attempt to run the circuit as is or using a startup pulse does not produce the expected oscillations. The crystal has . EXAMPLE 10. the default in SPICE2 and SPICE3. An important aid for initiating oscillations in a simulator is either a single pulse at the input of the amplifier block or the initialization of the charge storage elements close to the steadystate values reached during oscillations.8 H Rs = 600 n Co = 7 pF Use the following model parameters for the n. common equivalent circuit parameters: Cx = 2. Therefore. Solution A first approach for simulating this circuit is to replace the crystal with an equivalent circuit with a reduced Q that allows for a rapid buildup of oscillations.35 using includes the equivalent schematic of the crysresonant frequency of 3. the maximum allowed integration step. and Rs.and pchannel MOSFETs: NMOS: VTO=l PMOS: VTO=l KP=20U KP=lOU LAMBDA=O. Because of the high Q.47 fF Lx = 0. In the previous chapter and in the previous section it was shown that the Gear integration method has a damping effect on oscillations. Co. the number of periods for oscillations to build up is inversely proportional to the quality factor of the resonant circuit. 02 LAMBDA=0. and has the following crystal oscillator shown in Figure 10. in order to control the accuracy of the trapezoidal method. 10.362 10 CONVERGENCE ADVICE PSpice does not provide a choice in integration methods. It may be necessary to set a value of TMAX. trapezoidal integration. of the order of tens of thousands. which points to the Gear method. Q. Lx.1 CIRCUITSPECIFIC CONVERGENCE Oscillators The analysis of oscillators can represent a challenge for the user of circuit simulation.5795 MHz. Cx. The results of PSpice simulations for the above circuits show a certain level of damping. but seemingly not in PSpice. The following example provides insight into the analysis of a Pierce crystal oscillator. Another possible difficulty in simulating oscillators is related to the numerical integration methods.3. should always be used when simulating oscillators. The crystal has a in color television. it would theoretically take a number of periods on the same order of magnitude to reach steady state.5 10.13 Verify the behavior of the CMOS Pierce SPICE2 and PSpice. The circuit drawing tal.5. The most representative example for the difficulty encountered in simulating oscillators is a crystal oscillator. As described in Example 6. It is impractical to simulate a circuit for so many cycles.
and Co can be substituted by an effective inductance. respectively.w}Cl Cz/ (Cl + Cz) = 0. At frequencies below of the crystal is capacitive. The oscillation frequency. ws. Leff.18 mH (10.6) This frequency. whereas above Is the reactance is inductive and Lx. Is and Ip.CIRCUITSPECIFIC CONVERGENCE 363 Figure 10. is very close to the crystal resonant frequency. leading to the following value for Leff: L _1 eff . wo. of the equivalent circuit is given by Is the reactance Wo = (10. Cx.35 oscillator.7) . r Pierce CMOS crystal a series and a parallel resonant frequency. wo.
1N .3.36. it is necessary to initialize the charge storage elements as close as possible to the steadystate values. Co.TRAN 10N 50U 45U 10N .75 V across the crystal with a period of 280 ns.1N . 6.1 ns pulse for triggering the oscillations. As shown in Sec. that is. the circuit can be simulated with the real crystal.ENDS XTAL * * KICKING * VKICK 70 * .* XTAL Xl 3 5 XTAL . which provides a 0.02 .END Resimulation of the circuit results in the waveforms V (2) and V (3) shown in Figure 10.364 10 CONVERGENCE ADVICE The new equivalent resonant circuit has Q = 7. which is considerably smaller than the original value. The SPICE input description is listed below.MODEL * SOURCE PULSE 0 10M .MODEL PMOS PMOS VTO=l KP=10U LAMBDA=0.1N 1 1 NMOS NMOS VTO=l KP=20U LAMBDA=O. node 2.75 V at the output of the gain block.OP .PLOT TRAN V(2) V(3) . after approximately 150 cycles. 02 . when the steady state should have been reached. Assume that at t = 0+ both V (3) and V (5) are at 2. . corresponding to the resonant frequency. VKICK. Once the correct operatiori of the circuit has been verified. and 0. a • SUBCKT block represents the crystal. the previous results can help in this task. The • TRAN line requests the results to be saved only after 45 fJS.5 V.SUBCKT XTAL 1 2 LEFF 1 3 . PIERCE XTAL OSCILLATOR WI CMOS . Lx. The circuit sustains oscillations centered around 2. The crystal equivalent circuit.18M RS 3 2 600 RP 1 2 22MEG . The same results are obtained with both SPICE2 and PSpice.5 V with an amplitude of 1. woo Note that the SPICE circuit description includes a voltage source.OPTION LIMPTS=10000 ITL5=0 M1 M2 RL C1 C2 VDD * 2 2 2 5 3 0 0 NMOS W=40U 1 1 PMOS W=80U 10K 22P 22P 1 0 5 3 3 5 0 7 L=10U L=10U * * . must be replaced by Left. Cx.
. such as Lx. M1 M2 RL C1 C2 VDD 1 0 5 * * * XTAL . PIERCE XTAL OSCILLATOR WI CMOS ONLY PSPICE ITL5=0 L=10U . Therefore.lLS Figure 10.CIRCUITSPECIFIC CONVERGENCE 365 > E g ai Time.36 Waveforms V (2) and V ( 3) for oscillator with reduced Q. L=10U 3.5 IC=2. The results of the simulation using the equivalent inductor.02 (OLD) BECAUSE IT USES TRAP * * * * THIS CKT OSCILLATES . the initial current through Lx and Co should approximate the value of the current amplitude through the equivalent crystal.. in order to achieve steadystate oscillations in the solution. For a rigorous derivation of the oscillation amplitude consult the text by Pederson and Mayaram (1990). Note that it is important to initialize the state of one of the crystal components. Lejf. Lejf.5 .OPTION LIMPT8=10000 2 2 2 5 3 3 3 5 0 0 0 0 1 1 10K 22P 22P NMOS w=40U PMOS W=80U IC=2. instead of the crystal can be used for guidance. which corresponds to the maximum current in the inductor Lx.
18M LX 1 3 0. .366 10 CONVERGENCE ADVICE Xl 3 5 XTAL .END The new SPICE input is shown above.SUBeKT XTAL 1 2 * LEFF 3 6 .8 IC=0. 02 .47FF eo 1 2 7PF RS 4 2 600 RP 1 2 220K . l!S Figure 10.TRAN ION sou 45U ION Ule .37 and are identical to the previous solution. The estimated steady state is verified by the analysis performed in SPICE2 or SPICE3.MODEL PMOS PMOS VTO=l KP=10U LAMBDA=0.37 Waveforms V ( 2) and V ( 3) for oscillator with crystal.MODEL NMOS NMOS VTO=l KP=20U LAMBDA=O. The results are shown in Figure 10. and the oscillations are sustained for the 200 cycles simulated. The result > ai ~ g Time.6M ex 3 4 2.02 * .OP . note that the initial pulse is omitted and the keyword UIC is used in the • TRAN statement in order to start the analysis at steady state.PLOT TRAN V(2) V(3) .ENDS XTAL * .
Whereas.Poon formulation for the BJT transistor applies to all regions of operation. whicJ. MOSFETs are initialized with Vcs = VTO. and subsequently to the failure of SPICE to find a solution. are initially in the conduction state. in contrast with digital circuits. and the difficulty with MOSFETs is that the actual threshold voltage"VTH.n. often leading to illconditioned circuit matrices. and Ko 1985. Sheu. selfconductance of the gate)s therefore zero in DC.1. An important difference between BJTs and MOSFETs in the first iteration is that by default the former are initialized conducting whereas. By contrast. the EbersMoll or Gummel. decaying. The explanation can be found in the mode of operation of analog circuits. that is. The default initi~lization oLtransistors has a different impact on convergence depending on the operation of the circuit. Only MOSFET devices with subthreshold current. it is an open circuit in DC. Tbe continuity of the conductance.1.arid leads to"a sol~ti(:m without source ramping. There are differences in the operating points in which the program initializes the two types of devices and in the way new operating points. the MOSFETmodels combine different ~quations t~describe distinct regions of operations and various secondorder effects.icontinuous current flows in or out of the base terminal of a bipolar transistor. This secondorder effect is supported only by the higherlevel models. model parameterNFS. which is the first deriv'ative of the funttion. is usually increased by backgate bias to a higher value than the zerobias threshold'voltage.2 BJT versus MOSFET Specifics MOSFET circuits have more convergence problems than bipolar circuits because of a number of differences between the two devices types. the generality of analytical models used in SPICE to describe the two devices is not the same. This is one example where convergence can be improved by changing model parameters. as demonstrated by Example 10. t". independently of region of operation and analysis.4 demonstrated thatthe initialization of two protective devices as OFF improves the convergence . First.CIRCUITSPECIFIC CONVERGENCE 367 of a PSpice analysis for this circuit shows the oscillations explained by the use 'of Gear integration. The gate terminal of a MOSFET is insulated. Example 10..5. summarized}n Appendix A and described in more detail in the references (Antognetti and Massobrio 1988. Experiments in the SPICE code that initialized all MOSFETs in the conduction state have proven to . ave an important percentage of the 'devices turned h off.. is Important for the convergence of the iterative process.. the ilpplementation details in SPICE also affect convergence. A smaller number of iterations has been noticed for analog (linear) bipolar circuits as compared to digital (logic) bipolar circuits because BJTs are initialized 'as' cond~cting in SPICE. which have the majority of the transistors turned on. The differel}r fo. The. the physical structures of the two devices are different.mode. generally. Third. Second.MOSFETs are initialized turned off. VTO. Vladimirescu and Liu 1981).nulations have different levels of continuity for the equivalent conductance at the tran~i!ion points. Scharfetter. are selected at each iteration. which could be 10.
39 fails in SPICE2 but succeeds in PSpice and SPICE3 after source ramping. especially those with highimpedance nodes. and M6M7' Based on the knowledge acquired in Chap. IS LESS THAN PIVTOL can be found in the output file. Solution This circuit is a differential amplifier in a unityfeedback loop. If the supplies are ramped for part of the time interval.. often present in cascode loads. can be exemplified by a CMOS differential amplifier (Senderowicz 1991). encounters problems in the matrix solution: the messages PIVOT CHANGE ON THE FLY and *ERROR*: MAXIMUM ENTRY .368 10 CONVERGENCE ADVICE speed up the convergence of analog circuits. The importance of initialization and device specifics for the convergence of MOS analog circuits. VBSO. nodes 3 and 4 have very high impedances because of the cascode connection. a first approach is to tighten the pivot selection criterion . It is important to note that SPICE2.39 is performed when the • THAN and • PRINT lines are activated. IC = VDSO..14 Find the DC operating point of the circuit shown in Figure 10.38 using the LEVEL=2 parameters given in the SPICE description. the conversion from double. Based on the observation of the condition of the circuit matrix. 10. and the load transistor pairs M3M4. the DC value should be preserved for the rest of the timedomain analysis in order to allow the circuit to settle. the differential pair transistor M2. which are activated only in transient analysis in conjunction with the UIC option. Vcso. and at the limit between saturation and linear region. When ramping methods fail for this type of difficult circuit. A DC solution is avoided by using the UIC keyword on the • THAN line. Transient ramping of the CMOS differential amplifier in Fig. on one hand. A transient analysis also fails in SPICE2 for this circuit. running a transient analysis while ramping the supplies from 0 to the DC value or leaving them unchanged may lead to a solution. Addition of the option ITL6=40 to the SPICE2 input does not help for this circuit. The attempt to find the DC operating point of the circuit as it is represented by the input description in Figure 10. This approach to biasing is common in analog CMOS circuits.to singleended output is achieved by PMOS transistors M6 through M9. on the other hand. one can see the difficulty associated with solving the modified nodal equations when a number of nodes are of very low conductance. and additionally. A timedomain analysis of an MOS circuit has the additional advantage of a wellconditioned matrix because charge storage elements provide finite conductance at the gates of MOSFETs. which provides more feedback related to a solution failure. EXAMPLE 10. 9. The user can access initialization through the device initial conditions. Several options can be modified for this circuit. The state of this circuit is set by connecting the appropriate bias transistors Mll through M14 to the gates of the transistor Ms. all transistors are biased very close to the threshold voltage.
W Q'I I.C .Voo CD ~ )17 ~ )16 ~ )Is @ o o o ~ } /10 ~ CD Vss Figure 10.38 CMOS differential amplifier with cascode load.
2U AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U ARE SUPPLIED BY L=4.0 0 100U ION 100U 200U) VSS 2 0 0.WIDTH * * + + + + + + N_CHANNEL TRANSISTOR.O 2.8 JS=100.000 TOX=25.OPT PIVREL=lE2 *.l + XJ=lE10 PB=0. M12 AND M11 * W=120U 10 1 1 P M11 10 W=120U 2 2 N M12 8 8 2 2 N W=120U M13 6 6 2 N W=120U 7 7 2 M14 200U 110 10 2 1 8 200U 18 200U 16 1 6 17 1 7 400U L=1.OP .000 TOX=25.OPT ABSTOL=lU *.0E6 RSH=200 + NFS=100E+9 VMAX=20.0E6 RSH=100 NFS=200E+9 VMAX=60E+3 NEFF=2.2U AD=2N AD=2N AD=2N AD=2N AS=2N AS=2N AS=2N AS=2N PD=12U PD=12U PD=12U PD=12U PS=12U PS=12U PS=12U PS=12U VDD 1 0 5.2U L=1.9 DELTA=l + CJ=400E6 MJ=300E3 CJSW=2.0E10 CGDO=2.MODEL N NMOS LEVEL=2 U0=600 VTO=700E3 TPG=1.6U L=4.TRAN IUS 200US UIC *.2U L=1.2U L=1.0 *+ PULSE(O.8 JS=100.00E9 MJSW=1.39 SPICE input for CMOS differential amplifier with cascode load.0E10 CGDO=2.0E10 CGBO=3.0E10 CGB0=3.5 DELTA=3 CJ=400E6 MJ=300E3 CJSW=2.0 + CGS0=2.0E9 + NSUB=2. M14.OPT ITL4=100 *.0 CGS0=2.2U L=1.OPT ACCT *. SANITIZED MODELS * .0 0 100U ION 100U 200U) OUT=80 .8U L=1. .5 P_CHANNEL TRANSISTOR * * * .5 * .l XJ=lE10 LD=100E9 PB=0.OPT ITL6=40 *.END 370 Figure 10.MODEL P PMOS LEVEL=2 + U0=200 VTO=700E3 TPG=1.PRINT TRAN V(12) V(13) V(14) * * * .AMPLIFIER CMOS DIFFERENTIAL * W=120U 2 N M1 11 5 9 2 N W=120U M2 12 6 9 W=120U M3 8 11 2 N 3 12 2 N W=120U M4 4 8 7 2 N W=240U M5 9 2 w=120U 10 13 1 P M6 3 W=120U 14 1 P M7 4 10 W=120U M8 13 4 1 1 P W=120U 1 1 P M9 14 4 * * BIAS CIRCUIT * VOLTAGES AT NODES 6.0E+16 UCRIT=2E+4 UEXP=O.PRINT TRAN V(7) V(8) V(9) V(10) V(ll) *.0EIO FC=0.0E10 FC=0.PRINT TRAN V(2) V(3) V(4) V(5) V(6) *.O 5.00E+3 NEFF=.2U L=1.2U L=1.2U L=1.0E9 NSUB=5.0 VFF 3 5 2. 8 AND 10 * M13. 7.0 *+ PULSE(O.0E+16 UCRIT=2E+4 UEXP=O.8U L=9.2U L=1.00E9'MJSW=1.
the DC operating point is obtained for this circuit in only 8 iterations.and geometryadjusted values of the zerobias threshold voltages. The voltages at the circuit nodes are listed for the last 10 time points in Figure 10. can be raised: .28 = 1.39 = 4.71 = 1.54 = 0.64 + + + + + V(8) V(9) V(10) V(ll) V(12) V(13) V(14) When the node voltages are initialized.19 = 3.29 = 1. the node voltages obtained from the openloop circuit can be used in a • NODESET statement to initialize the closedloop amplifier. The openloop solution for this circuit is nontrivial. An alternate way to find a solution for this circuit and for amplifiers in general is to cut the feedback loop and find a DC solution of the openloop amplifier. One can verify the bias point of the transistors in this circuit and understand that the convergence difficulty is caused by the proximity of the operating points to the limits of the subthreshold conduction.1 = 1.OPTIONS PIVREL=lE2 Second.41.NODESET + + V(4) + V(5) + V(6) + + + V(7) V(3) = 3. VTO. the absolute current tolerance.OPTIONS ABS'IOL=1U These two options contribute to a successful timedomain solution in SPICE2. an average value is chosen to initialize the node voltages with a •NODESET statement.63 = 4. ABSTOL.32 = 0. MOS analog circuits are biased with VGS close to VTO for maximum gain and at the edge of saturation for maximum output signal swing (Gray & Meyer 1985). specified in the •MODEL statement.29 = 3.CIRCUITSPECIFIC CONVERGENCE 371 by increasing the value of PIVREL by including the following statement: . because of the possible operation near threshold of some transistors. linear and saturation regions. Then. VTH represents the bias.40. The solution and the operating point information are listed in Figure 10. . .39 = 0.
287E+00 3.883E01 3.906E01 3.920E04 1.980E04 1.824E01 3.284E+00 1.970E04 1.631E+00 4. Figure 10.000 DEG C *********************************************************************** TIME 1.540E+00 1.876E01 3.910E04 1.970E04 1.626E+00 V(lO) 3.289E+00 1. .642E+00 4.904E01 V(13) 4.939E01 3.286E+00 1.909E01 V(8) 1.629E+00 4.283E+00 1.940E04 1..287E+00 1.711E+00 3.876E01 1.542E+00 1.877E01 1.866E01 1.316E+00 3.883E01 1.903E01 1.950E.817E0l 3.930E04 1.920E04 1.6 3/15/83********20:18:56***** CMOS DIFFERENTIAL AMPLIFIER **** TRANSIENT ANALYSIS TEMPERATURE = 27.645E+00 4.288E+00 1.102E+00 1.546E+00 1.102E+00 V(ll) 3.710E+00 3.821E01 3.323E+00 3.626E+00 4.102E+00 1.960E04 1.313E+00 3.930E04 1.920E04 1..638E+00 4.286E+00 TIME 1.286E+00 3.630E+00 4.914E01 3.288E+00 3.712E+00 V(5) 1.896E01 1.930E04 1.950E04 1.990E04 2.852E01 3.285E+00 1.288E+00 1.317E+00 3.890E01 1.708E+00 3.990E04 2.708E+00 3.636E+00 4.980E04 1.874E01 3.534E+00 1.533E+00 1.323E+00 3.970E04 1.372 10 CONVERGENCE ADVICE *******03/07/93 ******** SPICE 2G.640E+00 4.897E01 3.649E+00 4.709E+00 3.529E+00 1.315E+00 3.102E+00 1.940E04 1.910E04 1.882E01 3.850E01 3.893E01 1.000E04 V(3) 3.950E04 1.320E+00 3.639E+00 4.288E+00 1.282E+00 1.000E04 TIME 1.942E01 V(9) 1.853E01 3.290E+00 V(4) 3.546E+00 V(12) 3.281E+00 1.000E04 .290E+00 V(6) 1.285E+00 3.632E+00 4.867E01 3.639E+00 4.642E+00 4.940E04 1.541E+00 1.907E01 3.04 1.791E01 3.287E+00 3.312E+00 V(14) 4.538E+00 1.102E+00 1.102E+00 1.288E+00 3.980E04 1.633E+00 4.283E+00 1.102E+00 1.960E04 1.102E+00 1.707E+00 3.990E04 2.710E+00 3.635E+00 4.40 V(7) 1.635E+00 Transient solution of CMOS differential amplifier.645E+00 4.537E+00 1.319E+00 3.287E+00 1.286E+00 3.285E+00 1.712E+OO 3.327E+00 3.886E01 1.960E04 1.102E+00 1.635E+00 4.844E01 3.286E+00 1.288E+00 3.284E+00 1.282E+00 1.102E+00 1.289E+00 3.711E+00 3.910E04 1.285E+00 1.
1019 0. A large circuit usually consists of a number of individual functional blocks.3 CONVERGENCE OF LARGE CIRCUITS The larger a circuit. 7 should be used for this purpose. which perform different functions. linear or nonlinear.2872 0. Before the entire circuit is stimulated. or cells.3878 VOLTAGE SOURCE CURRENTS NAME VDD VSS VFF CURRENT 1.467D03 1. Because of the size of the circuit. ITLl should be increased to 300 to 500 but not *******03/08/93 ******** SPICE 2G. The difficulty of finding a solution is directly related to the number of nonlinear elements.1884 4.000 DEG C *********************************************************************** NODE 1) 5) 9) 13) VOLTAGE 5.6327 NODE 2) 6) 10) 14) VOLTAGE 0. The . Specifying the state of transistors that are OFF also helps. SPICE requires considerable more iterations than for a few transistors. The large number of transistors operate in very different conditions depending on the functions of the blocks.5372 0.CONVERGENCE OF LARGE CIRCUITS 373 10.5.OOODtOO 3. the component functional blocks should be characterized individually.6421 NODE 3) 7) 11) VOLTAGE 3.2831 3.67D03 WATTS (continued on next page) TOTAL POWER DISSIPATION Figure 10. It is a good practice to describe a large circuit hierarchically. SUBCKT definition capability of SPKE introduced in Chap. This is necessary since • NODESET and • IC cannot initialize nodes internal to a subcircuit. . Key nodes can be expressed as interface nodes and initialized. With no prior knowledge of the expected function. the more complex is its behavior.2872 1. For most common purposes a circuit with more than 100 semiconductor devices can be considered a large circuit. the 100 iterations of the default ITLl are often insufficient for finding a DC solution.467D03 O. and some digital. some analog.6 3/15/83********21:30:55***** CMOS DIFFERENTIAL AMPLIFIER **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.0000 1.0000 1.41 DC operating point computed after initialization.7093 1.3848 NODE 4) 8) 12) VOLTAGE 3.3196 4.
40E13 8.OOE+OO Figure 10.188 0.172 1.202 1.OOE+OO O.40E14 2.40E14 2.358 0.314 0.40E14 2.188 0.37E03 9.90E13 6.87E14 O.29E13 3.00E04 2.40E14 2.680 0.154 0.20E14 O.765 0.08E04 4.00E16 3.348 5.OOE+OO O.46E06 1.04E12 5.OOE+OO O.OOE+OO O.OOE+OO M7 M6 M5 P P N 4.40E14 2.04E03 6.23E13 7.932 0.65E13 2.00E16 1.102 1.099 0.40E14 3.32E04 1.26E04 5.33E13 1.00E16 3.OOE+OO O.537 1.367 0.152 3.845 0.08E13 4.207 2.30E05 4.40E14 2.OOE+OO O.31E13 8.47E04 2.13E04 2.13E13 O.06E05 6.35E04 2.40E14 2.00E04 1.84E04 5.76E04 6.13E06 2.322 1.37E04 5.60E16 1.38E15 1.59E04 1.24E13 4.46E04 7.OOE+OO O.25E04 4.188 0.21E15 O.680 1.*******03/08/93 ******** SPICE 2G.OOE+OO O.358 0.23E04 7.14E06 8.44E15 2.361 0.35E04 2.89E04 6.751 0.09E13 8.11E13 O.00E16 1.000 0.36E04 7.98E04 1.40E14 3.80E14 2.16E03 2.OOE+OO VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGDOVL CGBOVL CGS CGD CGB P 2.095 1.OOE+OO O.170 0.70E04 9.385 0.81E13 7.537 1.67E04 2.000 0.48E04 4.32E13 7.102 0.156 1.09E13 2.35E04 2.306 0.OOE+OO O.65E13 7.OOE+OO O.291 0.11E13 2.388 0.08E04 4.933 1.367 0.00E04 1.000 0.69E04 6.42E13 5.000 0.OOE+OO O.32E04 1.41 (continued) 374 .14E04 3.29E13 5.82E15 1.000 0.53E04 7.64E04 7.196 0.82E13 5.02E03 3.33E13 1.13E13 8.31E13 7.79E13 6.11E13 8.40E14 2.03E06 1.756 0.18E13 2.931 0.10E13 1.OOE+OO M13 M12 Mll M9 N N P P 2.19E03 1.859 0.346 0.00E04 2.32E04 1.82E03 1.11E13 O.60E16 2.40E14 3.30E13 1.283 1.000 DEG C *********************************************************************** **** MOSFETS M2 M1 N N 2.52E06 7.40E14 2.OOE+OO O.96E13 4.40E14 2.60E16 1.000 0.01E13 1.149 1.40E14 2.845 0.32E04 2.857 0.291 1.35E04 1.40E14 3.348 5.18E13 8.00E16 1.40E14 2.22E13 2.313 1.751 0.762 0.55E05 1.23E04 6.88E04 2.20E14 9.00E16 3.40E14 3.757 0.11E13 1.82E03 9.40E14 2.22E13 7.80E14 2.199 0.677 0.60E16 3.40E14 3.OOE+OO M8 MODEL 10 MODEL 10 VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGDOVL CGBOVL CGS CGD CGB M4 M3 N N 2.000 0.23E03 7.102 0.11E13 8.OOE+OO O.10E13 1.540 0.40E14 2.40E14 2.322 2.09E13 7.6 3/15/83********21:30:55***** CMOS DIFFERENTIAL AMPLIFIER **** OPERATING POINT INFORMATION TEMPERATURE = 27.40E14 4.751 0.283 1.OOE+OO O.80E13 5.40E14 2.OOE+OO M14 N 4.902 0.40E14 2.
2. '[he r:esults can then be used either to find an 0p. for example. The next step toward finding a solution is to add or delete certain physical effects of the model. element values. Initialization of node voltages and cutoff semiconductor devices can be of help in finding a solution. and ABSTOL c. the NODE. number is low.themaxiIhum number of iterations allowed for anyone set of source values. In other situations a simpler model can lead to better convergence.6 SUMMARY Based on the information on the solution algorithms of the previous chapter. it can be used for initialization and the tolerances can be tightened back for more rigorous results. however. 4. LIST and MODEL options provide useful information on connectivity. PSpice and SPICE3 automatically exercise the ramping methods if the main iterative process fails.SUMMARY 375 beyond. Note that only tlie MODEL option is turned on by default in most SPICE versions. Carefully check the circuit connectivity and elem~nt values for possible specification errors and typographical errors. Once a solution is available. Another approach that may help large circuits converge is . For large circuits it can be useful'to initialize all nodes once a solution'is available and reduce the time for subsequent DC solutions. the probability for a circuit to converge beyond this.!te values. needs to be directed to ~pply source ramping by setting ITL6 to a value of 20 to 1OO. a number of approaches and simulator option parameters for overcoming convergence failure have been presented in this chapter.to relax the tolerances RELTOL and ABSTOL. increase ITL2 in PSpice from the default of 20to 40 or more.iterations. The following is the sequence of actions to undertake when SPICE fails to find the DC solution.transient analysis. 1. try first increasing the maximum number of iterations ITLI to 300 to 500.?rating point or to initialize another. Source ramping offers a better chance of success than increasing ITLl above the limit of 500 . The time interval should be chosen so that elements with the slowest time constants can settle to steadyst. If automatic convergence algorithms fail.anbe made as high as six orders of magnitude below the highest current of a single device in the circuit. the number of iterations taken at each step should be increased. RELTOL can be increased to 5 X 10. . If the circuit specification is correct and SPICE does not converge. a transient analysis with ure and all supplies ramped up from zero should help. If all the above attempts fail.7. see Example 10. 10. and model parameters. respectively. SPICE2. Examples in this chapter have demonstrated the importance of finite output conductance in saturation and subthreshold conduction for MOS circuits.3 . 3.
such as 103. as a . 7. Reduce. this luxury. RELTOL.2. rather than relax.NODESET initialization to the simulator of choice. The time step in this situation is controlled by the iteration count. 6. 1. If more than one SPICE simulator is available. SPICE2 grants the option of setting LVLTlM=l. Reduce the maximum allowed time step. such as FC. ABSTOL should not be more than 9 orders of magnitude smaller than the largest current of a nonlinear device. Convergence failure can occur not only in a DC analysis but also in the timedomain solution. 7. which is equivalent to setting TRTOL to a very large value. Once a solution is available. can also lead to a solution. A very reliable method for finding a DC solution is to run a transient analysis with the UlC option. 2. The protective parallel junction conductance. 8. 4. Also check the circuit for an abnormally high range of values for a single component type. . 9. Bypass is sometimes the culprit in a failed timedomain analysis. Disable control of truncation error by setting TRTOL to a large value.2 for the underlying explanation. 5.2). See Sec. The following steps should be taken. can be increased 2 or 3 6. however. which insures a finite transition time from state to state. which graphical postprocessing package for documentation purposes. ITIA. 3. All supplies should be ramped from zero to the final value for part of the interval and then held constant for the nodes to settle. to try to solve a difit can be transferred is usually linked to a Not many users have METHOD=GEAR with 8. Check model parameters that can produce unrealistic conductance values. GMIN. Increase the number of iterations.376 10 CONVERGENCE ADVICE 5. allowed at each time point to 40 or higher from the default of 10. it is useful ficult circuit with another version. Relaxation of the convergence tolerances. Use a different integration method if available. The solution of largegain blocks connected in a feedback loop can be found by opening the loop and then using the results to initialize the closedloop circuit. Check the circuit for charge storage. Relax the tolerances ABSTOL and RELTOL. 9. MAXORD=2orMAXORD=3 is recommended. In general. ABSTOL can easily be raised to 1 nA for MOSFETs.3. RELTOL and ABSTOL. TMAX. orders of magnitude. a value of 104 or smaller can force a smaller time step and avoid the bypass of a seemingly inactive device (see Sec. the ratio of the largest to the smallest value of a component type should preferably be within nine orders of magnitude.
S. R. T. Pederson. and S. Gray. The simulation of MOS integrated circuits using SPICE2. New York: McGrawHill. K. G. Univ. Berkeley.. O. Pederson. Scharfetter. Analysis and Design of Analog Integrated Circuits. 1989. A.. Sze. New York: John Wiley & Sons. Semiconductor Device Modeling with SPICE. and R. Device Electronics for Integrated Circuits. Physics of Semiconductor Devices. Meyer. 1981. S. IEEE Journal of SolidState Circuits. (October 5). 1991. S.. J. SPICE2 implementation of BSIM. Muller. Univ. New York: John Wiley & Sons.. M. ERL Memo UCB/ERL M85/42 (May). Senderowicz. New York: John Wiley & Sons. NECTARA knowledgebased environment to enhance SPICE. R. Patent 3. 1977. P. Mayaram. and K.O. Integrated Circuits for Communications. U. S. Physics and Technology of Semiconductor Devices. Personal communication. D. . ERL Memo UCB/ERL M8017 (March). 1967. P.. and D. Berkeley. 1981. CMOS Schmitt Trigger. L. and T. of California. J. Kelessoglou. SC24 (April) 452457. Grove. and P. New York: John Wiley & Sons. Jorgensen. 1976. of California. 1988.703. D. B. Liu. and G. 1990. Kamins. Vladimirescu.984. Ko 1985.SUMMARY 377 REFERENCES Antognetti.. Sheu. D. Boston: Kluwer Academic. 1985. M. I. A. Massobrio.
IN 2P 0.11 3 V A 00 Example lE16 1.69 Sbd 0.33 1.5 100 O.67 Ge 3 pn 2Sbd 40 lOU Seale Factor area l/area area EG XTI BV IBV FC KF Saturation current Emission coefficient Ohmic resistance Transit time Zerobias junction capacitance Junction potential Grading coefficient Activation energy Is temperature exponent n s F V eV AF Breakdown voltage Current at breakdown voltage Coefficient for forwardbiased depletion capacitance formula Flicker noise coefficient Flicker noise exponent 1 X 103 0.6 0.5 1.11 Si 0.5 0 1 area 378 .l Name IS N RS TT CJO VJ M Diode Model Parameters Parameter Units A Default 1 x 1014 1 0 0 0 1 0.APPENDIX A SEMICONDUCTORDEVICE MODELS A.1 DIODE Table A.
l DC. C](T) and Eg(T): (A3) (A 4) 4 2 E (T) g = E (0) _ (7.5) C](T2) = C](Td { 1 + M [400 1O6(T2  T1)  <PAT ~]ZT ~](Td ]) (A 6) Model parameters are assumed to be specified at the reference temperature. <p](T). VI. TNOM can be modified with a • OPTIONS statement.02 X 10.1) + VDGMIN ID = for VD 2: NkT 5q (Al) IS + VDGMIN IS(eq(Bv+vD)/kT .l.VD/VIO)M CD = ~ V FC VI lor D < . . { dID TT dVD + (1 _ CIO FC)I+M [1 _ FC(1 + M ) + MVD] VI ~ V FC lor D 2: .5q for VD < BV TTdID + CIO dVD (1 . IS(eqVD/NkT .2 Temperature Effects Model parameters IS.l. VI (A2) A. Transient. Is(T). equal to TNOM. T1. CIO.1) . and AC Models All SPICE2 and SPICE3 model parameters are listed in Table A. and EG vary with temperature according to the following functions of temperature. which defaults to 300 K.eV /K)T g (1108 K) + T X (A.DIODE 379 A.I.IBV NkT for BV < VD .
VBe) starts Excess phase at f = 1/ (2nTF) Reverse transit time BE zerobias junction capacitance BE builtin potential BE grading coefficient BC zerobias junction capacitance BC builtin potential BC grading coefficient 1016 0 1.f+fI KFl~F t::.2 qD t::.6 0.1 lE13 2 200 2 100 10 0. and the shot and flicker noise of the pn junction: '2 lRS = 4kTt::.f ld  A.75 0.5 1 1 00 00 area area V A A n n n n A s V A degrees s F V F V 0 1.5 250 0.3 Noise Model The three noise contributions are due to the parasitic series resistance.5 0 0 0 RB 00 area area l/area I/area l/area l/area area 0 0 00 0 0 0 0 0.1 IN Scale Factor area Saturation current Forward current gain Forward emission coefficient Forward Early voltage {3F highcurrent rolloff comer BE junction leakage current BE junction leakage emission coefficient Reverse current gain Reverse emission coefficient Reverse Early voltage (3R highcurrent rolloff comer BC junction leakage current BC junction leakage emission coefficient Collector resistance Emitter resistance Zerobias base resistance Minimum base resistance at high current Current where base resistance falls nalfway to its minimum value Forward transit time Coefficient for bias dependence of TF Voltage for TF dependence on VBC Current where TF = f(lc. RS.6 0.33 area lOON 2P 0.2 Name IS BF NF VAF IKF ISE NE BR NR VAR IKR ISC NC RC RE RB RBM IRB TF XTF VTF ITF PTF TR CJE VJE MJE CJC VJC MJC TRANSISTOR BJT Model Parameters Parameter Units A V A A Default 1x 100 1 00 00 Example lE16 80 2 100 0.380 APPENDIX A SEMICONDUCTORDEVICE MODELS A.33 2P 0.1 lE13 2 3 1.f RS (A.75 0.2 BIPOLAR JUNCTION Table A.33 0 0.5 area area .l .7) ~ .
IS .11 3 0 0. q 2 ( 1 _ VBC _ VBE )' 1) + IKR IS (eqVBclNRkT  (A 10) = IS (eqVBdNFkT _ IKF 1) Older versions of SPICE use parameters C2 and C4.5 Scale Factor F V eV XTI XTB FC KF AF 0 0.ISC(eqVBclNCkT  1) 1) (A 8) IB = ~~ (eqVBdNFkT  1) + ~~ (eqVBclNRkT .75 0 1.11 Si A.6 0.5 1. IS C4.1) + ISC(eqVBclNCkT  1) (A9) where qb is defined by qb = ~' (1 + Jl VAF + 4q2) VAR _ q.1 DC Model Ic ~~ (eqVBdNFkT _ eqVBclNRkT) _ ~~ (eqVBclNRkT . which correspond to the junction leakage currents ISE and ISC: ISE ISC = = C2.5 0 1 2P area 0.2.BIPOLAR JUNCTION TRANSISTOR 381 Table A.1) + ISE(eqVBdNEkT .2 Name XCIC CIS VIS MIS EG (continued) Parameter Fraction of CJC connected at internal base node B' CS zerobias junction capacitance CS builtin potential CS grading coefficient Activation energy Is temperature exponent {3F and {3R temperature exponent Coefficient for forwardbiased depletion capacitance formula Flicker noise coefficient Flicker noise exponent Units Default Example 0.
is RBM RBB.382 APPENDIX A SEMICONDUCTORDEVICE MODELS The effective series base resistance.44VTF ( Icc Icc + ITF )2] (A 14) Junction capacitances are defined by (AI5) .2.=== 1 + J1 + 1.44IB/ 24/ 'TT2 'TT2IRB JIB/IRB A.RBM qb if IRB is not specified (All) ztan2 z if IRB is specified { RBM + 3(RB . RBB.RBM) tan z .z where z = .2 Transient and AC Models CBE CBC CCS Diffusion capacitances = CDE + CJE CDC + CJB.c CJS as (AI2) = = are implemented CDE C DC = _J_ [T/ JVBE S qb (eQV8dNFkT  1)] (A13) = TR qIS eQV8c1NRkT NRkT where TF and = TF[l + XTFeV8c11. = + RB .
A. TF (A 17) This effect is also present in the timedomain expression of ie(t).I8) (A 19) (A.4 Noise Model Noise is modeled as thermal noise for the parasitic series resistances flicker noise for i C and iB: i~ and as shot and = 4kTtlf R (A2l) .6. of Eg.3 Temperature Effects The following quantities are adjusted for temperature variation: (A.XJC)CIC (A 16) a phase shift equal to () = is applied to the phasor Ie: wPTF.C CIBC At high frequencies = XJC. AA to A.BIPOLAR JUNCTION TRANSISTOR 383 The Be junction capacitance has two components.2. one to the internal base node: one connected to the external and CIB. CIC = (l .20) The temperature dependence mined by Eqs.2. and CI for the diode is implemented as deter A. cPI.
3 Name LEYEL YTO KP GAMMA PHI LAMBDA RD RS RSH CBD CBS CJ MJ CJSW MJSW PB IS JS CGDO CGSO CGBO NSUB NSS NFS TOX TPG Example 1.33 I I x 1014 0 0 0 0 0 0 0 00 Table A.0EI6 I.3 2q IB 11/ 2q1cl1/ + KF.23) MOSFET MOSFET Model Parameters Parameter Model index Threshold voltage Transconductance parameter Bulk threshold parameter Surface potential Channel length modulation parameter Drain ohmic resistance Source ohmic resistance D and S diffusion sheet resistance Zerobias BD junction capacitance Zerobias BS junction capacitance Zerobias bulk junction bottom capacitance Bulk junction grading coefficient Zerobias bulk junction sidewall capacitance Bulk junction grading coefficient Bulk junction potential Bulk junction saturation current Bulkjunction saturation current per junction area GD overlap capacitance per unit channel width GS overlap capacitance per unit channel width GB overlap capacitance per unit channel length Substrate doping Surface state density Fast surface state density Thinoxide thickness Type of gate material + 1opposite to substrate 1 same as substrate Al gate Metallurgical junction depth Lateral diffusion Surface mobility Units Y A/y2 yl/2 Y yI Default I 0 2 X 105 0 0.5U O.OEI5 1.6 0 0 0 0 0 0 0 0./ IY 11/ (A.6 1.0E4 0.lU Scale Factor n n n F F F/m2 NRD NRS AD AS PD PS F/m Y A Nm2 F/m F/m F/m cm3 cm2 cm2 m AD AS W W L o XJ LD .0ElO O.384 APPENDIX A SEMICONDUCTORDEVICE MODELS :z lb :z = lc A.OEII 2.5 1.25 0.0E1O 4.0E4 10 10 10 5P IP 2.5 0 0.7 1.2U 700 .0E9 0.0ElO 1. s 0 0 600 O.OE8 4.0 1.0E3 0.OEII 4.5 0.UO m m cm2N.22) (A.
these two models together with the LEVEL==l model. described in Chap.24) and mobility factors are defined by f3 IJ.27) .26) The builtin voltage including smallsize effects is VBIN == VFB + PHI + DELTA 4 Cox~(PHI 7TES' .2.(PHI .== VO == IJsCox Lejf w  ilL UEXP (A.1 DC Model The LEVEL parameter differentiates and sets the analytical models describing the behavior ofa MOSFET.VBS) (A.VTRA. There are 3 levels in SPICE2 and 6 in SPICE3.VBS)3/2]) (A.VBIN . are available in all SPICE versions. LEVEL==2: 1]VDS) f3 { ( l:'CS ." Cox(Vcs . VDS) ] (A.A.VTH . . 3.25) [ VCRITEs.3. Only the equations for LEVEL==2 and LEVEL==3 are listed.VBS)3/2 .VDS IDs == ~YS where the transconductance [(PHI + VDS .
JPHI) (A.VBS . LD.VBS .as .29) VTO where = VFB + PHI .31) (A.1) Ws = Xd JPHI . 33) (A.30) D .GAMMA JPHI ')Is = GAMMA(l .1) Xl aD = 2£ lXl(J 1 + 2 Xl W (A. 34) .32) Ll _ { LAMBDA .2LD if LAMBDA is specified if LAMBDA is not specified (A. and channel shortening in saturation: Left = L . L.386 APPENDIX A SEMICONDUCTORDEVICE MODELS The adjusted and zerobias threshold voltages are VTH = VBlN + ')Is ( JPHI .aD) as = IXl 2£ (J 1 + 2 Ws .NSUB The geometric channel length. VDS f(VDSAT) L  The pinchoff saturation voltage is defined by V DSAT ..28) (A. 2ESi q.(VGS . is adjusted due to lateral diffusion. .VBIN)  YJ (A.
VBIN .VBS)3/2]) eq(VGSVoN)/nkT (A.39) = aQB aVBS = d ( Ys dV ~ J PHI ays .VTH .X d [ (XdVMAX)2 2 JJs L.'l7VDSAT . 36) Qchan = Cox [VGS .40) (A.VBS)3/2 . NFS Cd Cd Cox (A. 35) (A.(PHI . W.MOSFET 387 The velocitysaturationbased tions: model derives VDSAT and ilL from the following equa IDSAT .VBIN ~YS [(PHI where 'l7~DS )VDS + VDS .VBS .VMAX.VDSAT) + 2.Ys(PHI .av ~ J PHI .VBS 7TESi + DELTA 4C ) Cox mW LEVEL=3: IDS where 1+ FB = f3 (VGS .2VDS )V DS (A. 37) Subthreshold conduction is modeled when NFS is present: IDS =f3 {(VON .41) . 38) VON = VTH +Cis Cox nkT q n=l++Cis = q .] JJs (A.VBS AL . Qchan(L) = 0 + VDSAT)'/2 ] (A.l XdVMAX + (V DS .
d2 = 0.VTH)2 1 +FB + (VMAX.Xl (A.47) (A.VTH) (A.50) Xd [ + KAPPA(VDS .01110777 The saturation model is based on velocitylimited carrier flow: VDSAT = VGS .44) where a = ETA + We Xl 8.45) CoxLejf Wp/Xl 1 .VDSAT) .46) FN = DELTA 'TTESi 2CoxW (A. Lejf JLs EPXd)2 ( 2 (VGS .42) (A.0631353.VTH 1 +FB ilL = + VMAX. Lejf VDs The threshold voltage is defined by (A.43) JLejf 1+ JLs JL VMAl.15 X 1022 3 (A.EPXd] 2 (A.49) do = 0.8013292.48) (A. d] = 0.51) where Ep=  IDSAT GDSATLejf .388 APPENDIX A SEMICONDUCTORDEVICE MODELS va JLs = 1 + THETA(VGS = . JLs Lejf)2 (A.( 1 + Wp/Xl Fs = 1 _ Xl [LD )2 Lejf LD] .
see the University of California at Berkeley research reports (Jeng 1990. VGS > VTH CGB CGS + VDS. VGS ::s. CGD. and CGB.52) CGSO.VON VON) _ V ( 1 . Sheu. + CGDO' W (A 54) W CGD Cox [ 2(VGS _ Cox DS where = Cox W . CGDO.VDS . CGS. LEVEL=4 and LEVEL=5 in SPICE3. Leff (A. A. In saturation. V TH.17. shown graphically as a function of VGS in Figure 3. Leff €ox€O C ox = TOX The charge conservation model derives asymmetrical capacitances according to the following definitions: Qchan = QD + Qs = (QG + QB) (A55) . = = = CGBO' Cox Leff VGS . the expressions are = CGBO' 3CoX CGDO' Leff = = 2 + CGSO. W W (A53) In linear operation. and Ko 1985).MOSFET 389 For the BSIM and BSIM2 models.[ 2(VGS _ ( 1 ]2) ]2) + CGSO. are listed below for the three main regions of operation of a MOSFET. VTH < VGS ::s. VTH CGB CGS CGD + VDs.VON VON) _ V DS VGS .3.2 Transient and AC Models The gate capacitances defined by the Meyer model. Scharfetter. In the cutoff region. all three capacitances are constant: CGB CGS CGD = = = Cox + CGBO W W .
. and C] which have the temperature dependence described for the diode.¥.3.Cyx avy avx A.f + KF. University of California.Sheu.45 X jL(T) = jL(300) 300)1. K. I~~ D. Ko. M. B.. D.C. . £g)] 2k 300 (A58) 1. the intrinsic concentration ni and the mobility are adjusted for temperature: ni(T) ni(300) _ = ni(300) (T)1.. J. University of California. Scharfetter.5 300 1010 m3 exp [Q(1. ERL Memo UCBIERL M85/42 (May). Berkeley. Design and modeling of deepsubmicrometer MOSFETs.T. SPICE2 implementation of BSIM 'model.390 APPENDIX A SEMICONDUCTORDEVICE MODELS QD = XQC' Qchan (A56) (A5?) _ aQx aQy_ Cxy . and P.16eV K . cf>].3. L.5 (T (A59) A. 1990. Berkeley.4 Noise Model The noise contributed by the drainsource current is j2 = 8kTgm D. 1985. ERL Memo UCBIERL M90/90 (October).f ds 3 fC ox L2 eff (A.3 Temperature Model In addition to Is.60) REFERENCES Jeng.
but the wording may differ. *ERROR*: NEGATIVE NODE NUMBER FOUND This statement is printed immediately following an input statement that contains a negative node number. It is an added protection that ensures that additional element types are implemented correctly at future times. This error is fatal. This error is fatal. *ERROR*: ELEMENT TYPE NOT YET IMPLEMENTED This error message should hardly ever occur.1 GENERAL SYNTAX ERRORS *ERROR*: UNRECOGNIZABLE DATA CARD This message follows an input statement that starts with a number in the first field. B. 391 . is omitted in the first column of a continuation statement. *ERROR*: UNKNOWN DATA CARD: Name Name. does not start with any of the accepted key characters in the first column. This error may arise when the continuation character. that is. This error is fatal. +. This error is fatal. since it duplicates the previous message.APPENDIX B ERROR MESSAGES A large percentage of aborted simulation runs are due to erroneous input specifications. This section enumerates all the SPICE2 error and warning messages related to input specifications. the first field of the statement. An example is the occurrence of two title statements in the same circuit specification. Other SPICE programs flag the same problems as the ones listed below.
or the frequency. F. *ERROR*: . specified. 8. 8. This error is fatal. This A value must be specified for the characteristic error is fatal. for transient . This error is fatal. for example. the fourth node must be defined for a MOSFET. This error message would occur if.0 A coupling coefficient in excess of 1 must have been specified in the above statement.3 SOURCE SPECIFICATION ERRORS *ERROR*: VOLTAGE SOURCE NOT FOUND ON ABOVE LINE A currentcontrolled source requires the name of the voltage source through which the controlling current flows to be specified. *ERROR*: EITHER TD OR F MUST BE SPECIFIED A value must be specified for either the delay time. Check the types and abbreviations source functions.2 MULTITERMINAL ELEMENT ERRORS *ERROR*: MUTUAL INDUCTANCE REFERENCES ARE MISSING A mutual inductance name must be followed by two inductor names starting with the letter L. even if all bulk terminals are connected to ground.END CARD MISSING *ERROR*: ILLEGAL NUMBERSCAN STOPPED AT COLUMN number A number with an absolute value outside the interval from 1035 to 1035 has been. *ERROR*: UNKNOWN SOURCE FUNCTION: sourcefunction A transient source function is specified. The analysis continues with a coupling coefficient of 1. This error is fatal. *ERROR*: ZO MUST BE SPECIFIED impedance of a transmission line.392 APPENDIX B ERROR MESSAGES *ERROR*: NODE NUMBERS ARE MISSING This error message is printed immediately following an input statement that does not contain the correct number of nodes for a particular element type. of a transmission line. TD. WARNING: COEFFICIENT OF COUPLING RESET TO 1. This error is fatal. This error is fatal. The voltage source name must follow the node numbers of the source. only three nodes are specified for a MOSFET.
*ERROR*: MODEL NAME IS MISSING A model name is expected to follow the node specification on diode. The number of values in the above line exceeds the maximum number of parameter values. PD. For convergence reasons it is not advisable to use resistor values less than 1 mf!. SEMICONDUCTORDEVICE. *ERROR*: UNKNOWN PARAMETER: Name A parameter name used in an element statement is not valid. Check element statement for valid parameter names. such as area. *ERROR*: VALUE IS ZERO This message follows a zerovalued resistor. This error is fatal. This error is fatal. capacitors. l¥. and NRS. AD. The following elements belong in this category: resistors. *ERROR*: UNKNOWN MODEL PARAMETER: Name The above parameter name is not supported by the model. . which lead to infinite conductances. AS. *ERROR*: UNKNOWN MODEL TYPE: modeltype A model type was specified in the above statement that is not one of the eight types recognized by SPICE2. 8. This error is fatal.ELEMENT. mutual inductors. inductors. or L. *ERROR*: MODEL TYPE IS MISSING Every • MODEL statement must contain a model type. This error is fatal. which are assigned in order to L. This error is fatal. Up to eight values can follow the model name. and MOSFET statements. This error is fatal. JFET. This message may be encountered also following a semiconductor device definition statement that contains negative geometry parameters. AND MODEL ERRORS 393 *ERROR*: ELEMENT Name PIECEWISE LINEAR SOURCE TABLE NOT INCREASING IN TIME The time values of the (ti. *ERROR*: VALUE IS MISSING AND MODEL ERRORS NONPOSITIVE OR IS This error message can follow an element definition statement that is expected to contain a value. This error is fatal. *ERROR*: EXTRA NUMERICAL DATA ON MOSFET CARD A MOSFET can have up to eight device parameters. NRD. l¥. PS. SEMICONDUCTORDEVICE. This error is fatal. The solution of nodal circuit equations in SPICE precludes the use of zerovalued resistors. BJT. and controlled sources. Each of these elements must be accompanied by a positive value. Vi) coordinates must be in increasing order.4 ELEMENT.
*ERROR*: SUBCIRCUIT NAME MISSING A name starting with a character must follow the word. MODname. *ERROR*: NO DC PATH TO GROUND FROM NODE number From every node there must be a path to ground in order to find a DC solution. *ERROR*: NONPOSITlVE DEFINITION NODE NUMBER FOUND IN SUBCIRCUIT All node numbers must be positive numbers. subcircuit instantiation. SUBCKT on a subcircuit definition line or the node numbers on an X element. . CONTAINING voltage law.394 APPENDIX B ERROR MESSAGES WARNING: MINIMUM BASE RESISTANCE (RBM) IS LESS THAN TOTAL (RB)FOR MODEL MODname RBM SET EQUAL TO RB WARNING: THE VALUE OF LAMBDA FOR MOSFET MODEL.5 CIRCUIT TOPOLOGY ERRORS *ERROR*: CIRCUIT HAS NO NODES The circuit needs to contain at least one other node than ground. Such a loop would contradict Kirchhoff's WARNING: ATTEMPT TO REFERENCE RESET TO 0 UNDEFINED NODE numberNODE 8. BV = value AND IBV = value 8. line.6 SU8C1RCUIT DEFINITION ERRORS *ERROR*: SUBCIRCUIT DEFINITION DUPLICATES NODE number Two terminals (nodes) on the subcircuit definition line have the same number. *ERROR*: Vname INDUCTOR/VOLTAGE SOURCE LOOP FOUND. IS UNUSUALLY LARGE AND MIGHT CAUSE NONCONVERGENCE WARNING: IN DIODE MODEL MODname IBV INCREASED TO value TO RESOLVE INCOMPATIBILITY WITH SPECIFIED IS WARNING: UNABLE TO MATCH FORWARD AND REVERSE DIODE REGIONS. *ERROR*: LESS THAN 2 CONNECTIONS AT NODE number At least two elements must be connected at any node.
WARNING: ABOVE LINE NOT ALLOWEDWITHIN SUBCIRCUIT. *ERROR*: NO CONVERGENCEIN DC ANALYSIS.7 ANALYSIS ERRORS *ERROR*: MAXIMUMENTRY IN THIS COLUMNAT STEP LESS THAN PIVTOL number value IS Circuit matrix is singular. in SPICE2 increase ITL2 and consult Example 10. *ERROR*: UNKNOWNSUBCIRCUIT NAME: SUBname A • SUBCKT definition for SUBname referenced by an X element cannot be found in the circuit deck. 9 and 10 for more insight. *ERROR*: . *ERROR*: INTERNAL TIMESTEP TOO SMALL IN TRANSIENT ANALYSIS The smallest acceptable time step has been reached after repetitively cutting the time step without converging to a solution. every subcircuit definition must be completed with an • ENDS line.IGNORED WARNING: NO SUBCIRCUIT DEFINITION KNOWNLINE IGNORED 8. . list LAST NODE VOLTAGES: Failure to find a DC solution. see Chaps. has been encountered before all • SUBCKT lines have been matched by • ENDS lines. • END line. 10 for advice on overcoming convergence problems. *ERROR*: NO CONVERGENCEIN DC TRANSFER CURVES AT Name = value LAST NODE VOLTAGES: list Solution failure during a • DC analysis at a specific value of the variable Name.. see Chap.8. *ERROR*: Xname HAS DIFFERENT NUMBER OF NODES THAN SUBname The number of nodes on an X line must match the number of nodes on the subcircuit definition line it references. see Sec. *ERROR*: SUBCIRCUIT SUBname IS DEFINED RECURSIVELY A subcircuit definition contains an X element that references the subcircuit being defined.ENDS CARD MISSING The end of the circuit deck. 10.ANALYSIS ERRORS 395 *ERROR*: SUBCIRCUIT NODES MISSING Node numbers are expected to follow the subcircuit name on a SPICE2 subcircuit definition line.1 for detailed examples.2.
or .PLOT or • PRINT request. Use the LIMPTS options parameter to override this limit. or . WARNING: MORE THAN number POINTS FOR Name ANALYSIS.AC analysis. WARNING: TOO FEW POINTS FOR PLOTTING Too few points have been computed or requested. floatingpoint arithmetic computation may continue after an underflow condition leading to the creation and proliferation of outofrange or NaNs (notanumber).AC analysis must be accompanied by a . WARNING: NO Name OUTPUTS SPECIFIED ••• ANALYSIS OMITTED In SPICE2 a • DC. CHANGE THE ORDER AND RE. *ERROR*: MEMORY REQUIREMENT EXCEEDS MACHINE CAPACITY MEMORY NEEDS EXCEED value]. and when interactivity is available. •AC. • TRAN.TRAN. THIS LIMIT MAY BE OVERRIDDEN USING THE LIMPTS PARAMETER ON THE . set ITL5 = 0 to remove this limit. quantities. ANALYSIS OMITTED. . such as in SPICE3.EXECUTE In a •DC statement the temperature variable must always be the second variable if another sweep variable is specified. value2 The analysis of the circuit requires more internal memory than available. the lineprinter plot has been omitted. SPICE has trapped and minimized the effect of the problem.OPTION CARD Some SPICE programs limit the number of print/plot points that can be output by • DC. *ERROR*: TEMPERATURE SWEEP SHOULD BE THE SECOND SWEEP SOURCE. or • DISTO analysis. note that in IEEE format. equal to 5000 in SPICE2. . the user can monitor the correctness of the solution. to give the user the opportunity to judge the correctness of results and whether analysis should be continued.396 APPENDIX B ERROR MESSAGES *ERROR*: TRANSIENT ANALYSIS ITERATIONS EXCEED LIMIT OF number THIS LIMIT MAY BE OVERRIDDEN USING THE ITL5 PARAMETER ON THE . WARNING: UNDERFLOW OCCURREDnumberTIME(S) WARNING: UNDERFLOWnumberTIME(S) jreq HZ IN AC ANALYSIS AT FREQ WARNING: UNDERFLOWnumberTIME(S) FREQjreq HZ IN DISTORTION ANALYSIS AT A smaller number than can be represented on the computer was generated during a •DC • TRAN.OPTION CARD The transient analysis is stopped after a preset number of iterations. Many SPICE programs do not have this builtin limit.
WARNING: UNRECOGNIZABLE OUTPUT VARIABLE ON ABOVE LINE Incorrect output variable specification on a plot or print statement. see Chap.TSTART) is less than the period of the fundamental specified on the • FOUR line. ANALYSIS OMITTED WARNING: UNKNOWNFREQUENCY FUNCTION: Name ••• ANALYSIS Frequency variation is limited to LIN. WARNING: OUTPUT VARIABLE UNRECOGNIZABLE ••• Incorrect sensitivity analysis output specification. . WARNING: DISTORTION WARNING: DISTORTION OMITTED WARNING: FOURIER LOAD RESISTOR ANALYSIS ANALYSIS OMITTED OMITTED MISSING ••• ANALYSIS ANALYSIS OMITTED PARAMETERS INCORRECT ••• PARAMETERS INCORRECT ••• ANALYSIS OMITTED WARNING: FOURIER ANALYSIS FUNDAMENTAL FREQUENCY IS INCOMPATIBLE WITH TRANSIENT ANALYSIS PRINT INTERVAL ••• FOURIER ANALYSIS OMITTED Transient analysis interval (TSTOP . AC.. OCT. WARNING: FREQUENCY PARAMETERS INCORRECT ••• ANALYSIS WARNING: START FREQ > STOP FREQ ••• ANALYSIS OMITTED OMITTED OMITTED WARNING: TIME PARAMETERS INCORRECT ••• ANALYSIS WARNING: START TIME> STOP TIME ••• ANALYSIS OMITTED OMITTED OMITTED WARNING: ILLEGAL OUTPUT VARIABLE ••• ANALYSIS Incorrect output variable specification in • TF analysis.. LINE IGNORED The analysis type on a plot or print statement must be one of DC.ANALYSIS ERRORS 397 WARNING: MISSING PARAMETER(S) ••• Incorrect • DC specification. or DEC. 5. WARNING: INVALID INPUT SOURCE ••• Incorrect input noise source specification. NOISE or DISTO. TRAN. WARNING: VOLTAGE OUTPUT UNRECOGNIZABLE ••• Incorrect noise analysis output specification. ANALYSIS OMITTED WARNING: UNKNOWNANALYSIS MODE: Name .
MAXIMUM VALUE ASSUMED WARNING: UNKNOWN OPTION: Name WARNING: ••• IGNORED FOR OPTION: Name ••• IGNORED ILLEGAL VALUE SPECIFIED The following warnings are issued for an incorrect •NODE SET or • IC line..398 B..8 APPENDIX B ERROR MESSAGES MISCELLANEOUS ERRORS *ERROR*: CPU TIME LIMIT EXCEEDED . ANALYSIS STOPPED Some SPICE programs allow the user to set a limit on how long an analysis can run. WARNING: WARNING: OUTOFPLACE INITIAL NONNUMERIC FIELD Name SKIPPED VALUE MISSING FOR NODE number CONDITION FOR GROUND WARNING: ATTEMPT TO SPECIFY IGNORED INITIAL . WARNING: NUMDGT MAY NOT EXCEED number.
.l ELEMENT STATEMENTS Rname nodel node2 rvalue < TC=tc1<tc2> > Rname nodel node2 <rvalue><Mname><L=L><W=W> Cname nodel node2 lvalue <IC=vco > [SPICE3] Cname nodel node2 POLY Co CI < C2 .phase»> + <TRANjunction <valuel <value2 . ><IC= iLO> Vname node1 node2 «DC>devalue><AC <acJnag <ac........ ><IC=vco > Cname nodel node2 <cvalue><Mname><L=L><W=W><IC=vco [SPICE3] Lname nodel node2 lvalue <IC=iLO> Lname nodel node2 POLY 10 II < 12 . »> Iname nodel node2 «DC> devalue><AC <acJnag <ac.phase»> + <TRANjunction <valuel <value2 . C.. Statements followed by [SPICE3] appear only in SPICE3. »> TRAN Junction can be one of the following: V2 <TD <TR <TF<PW<PER»»» SIN(VO VA <FREQ <TD <THETA»» SFFM (VO VA <Fe <MDI <FS> > > ) PULSE(Vl > 399 ..APPENDIX C SPICE STATEMENTS This appendix lists all the SPICE statements introduced in this text.
..ncl.vcso > [SPICE3] > SUBname C.nc+ nc + nc1 < nc2+ nc2> .VCEO> < IC=VDSO. > <POLY (ndim) > Vnamel <Vname2 ..ncZ. » Diode model npn BJT model .ncZ. > [SPICE3] [SPICE3] [SPICE3] Hname n + n . > Po < PI + + < pz .nc+ nc.Model <ON/OFF> Wname n+ n. > ii.. > Po < PI < Pz .MODname Jname nd ng ns MODname nz n3 n4 ZO=zO <TD=td> <F=freq <NL=nl <area><OFF><IC=VDO <area><OFF> »<IC=VIlI. i(Vname2) ... i(Vname2) ..Vname Model <ON/OFF> Tnamenl Dname n+ n.Vname hvalue Hname n+ n » + <IC=i(Vnamel). > > ) Lname2 k gvalue <POLY (ndim) > nc1 evalue Kname Lnamel Gname n+ n Gname n+ n..... > iz Qname nc nb ne <ns> MODname Mname nd ng ns nb MODname <area> <OFF> < IC=VBEO. < IC=VDSO... » <IC=Vncl+.. VBSO> <area><OFF> Zname nd ng ns MODname Xname xnodel <xnode2 . > Po < PI + < pz .....'" Ename n+ n.. vcso.. VIl3..2 GLOBAL STATEMENTS • MODEL MODname MODtype <PARAM1=valuel MODtype can be one of the following: D NPN <PARAM2=value2 .400 C SPICE STATEMENTS EXP(Vl V2 <TDl TAW TD2 <TAU2») PWL (tI VI < tz Vz < t3V3 ..nc+ ncEname n+ n <POLY (ndim) > nc1 + nc1 < nc2+ nc2 .IlZ.vcso > «L=>L>«W=>W><AD=AD><AS=AS> + + <PD=PD> <PS=PS> < NRD=NRD > <NRS=NRS> <OFF> <IC=VDSO. » <IC=Vncl+.. > Po < PI < pz .Vname fvalue Fname n+ n<POLY (ndim) > Vname1 <Vname2 .. vncZ+.1l4. > Fname n + n .... Bname nodel node2 <VII> =expr Sname n+ n.vllcZ+.llcl... » < IC=i(Vname1 ).
> C.. ><ploLlimits> Analysis_TYPE can be one of the following: DC.OP • DC V/Iname] start] stop] step] <V/Iname2 start2 stop2 step2> ....TF OUT_varV/Iname • SENS OUTvar] <OUT_var2 ..DISTO . > • TEMP temp] <temp2 ..n2» V/Iname nums ...NOISE.NOISE V( n]<..AC. > <V(node2)=value2 .NODESET V(nodel)=value] • IC V(nodel)=valuel • ENDS <SUBname> • END <V(node2)=value2 .DISTORLname [SPICE3] <nums <f2/fl < Pre! < S2 »» node_out2 <CUR/VOL><POL/ZERlPZ> • PZ node_in] node_in2 node_outl ....AC DEC/OCTILIN numptsfstartfstop .TRAN.3 CONTROL STATEMENTS .TRAN TSTEP TSTOP < TSTART <TMAX»<UIC> •FOURfreq OUT_var] <OUT_var2 ...CONTROL STATEMENTS 401 PNP NJF PJF NMOS pnp BJT model nchannel JFET model pchannel JFET model nchannel MOSFET model pchannel MOSFET model Diffused resistor model Diffused capacitor model [SPICE3] [SPICE3] [SPICE3] [SPICE3] [SPICE3] PMOS R C URC Uniformdistributed RC model Voltagecontrolled switch model Currentcontrolled switch model nchannel MESFET model pchannel MESFET model SW CSW NMF PMF [SPICE3] [SPICE3] • SUBCKT SUBname node] <node2 . > . > • PRINT/PLOT AnalysisTYPE OUT_varl <OUT_var2 . > .
 . (~) 18 9 TIxn .  lOh6 d6x 137 dt6 Xn+l = 147xn .3Xn1 + 3Xn+1 = 9 2h3 d3x dt3 6h.125 dt5 12 (~) 300 300 137xn .22 + 16 3 25xn2 .APPENDIX D GEAR INTEGRATION FORMULAS Gear 1: Gear 2: Gear 3: Gear 4: Gear 5: Xn+l =Xn 4 Xn+l Xn+l Xn+l Xn+l + hXn+l .25xn1 + TIXn2 . 3h5 d5x 25 Xn+l .25xn3 200 75 2 3h4d4x dt4 (~) = = + 12h.TIXnl 48 36 25xn .137xn3 + 137xn4 (~) + 137xn+1 Gear 6: 60h .TIXn+l .147xn3 + 147xn4 + 147xn+1 60h .137xn1 + 137xn2 .2 dt2 (~) 1 2h .147xn1 + 147xn2 .  360 450 400 225 72  10 147xn5 180h6 d7 X 3087 dt7 (~) 402 . h2 d2x = 3xn .
1 SMEG) AC 1 * * * * CIRCUIT ELEMENT DESCRIPTION STATEMENTS * * GLOBAL STATEMENTS CCS=2P TF=0. DIFFPAIR CIRCUIT . Most types of statements and analyses are used.3N TR=6N * * * + .APPENDIX E SPICE INPUT DECK This is an example SPICE input for a differential amplifier from the University of California.MODEL QNL NPN BF=80 RB=100 CJE=3P CJC=2P VAF=SO ANALYSIS REQUESTS 403 . Berkeley.SIMPLE DIFFERENTIAL AMPLIFIER Ql 4 2 6 QNL Q2 5 3 6QNL Q3 6 7 9 QNL Q4 7 7 9QNL RSI 1 2 lK RS2 3 o lK RCI 4 8 10K RC2 5 8 10K RBIAS 7 8 20K VCC 8 o 12 VEE 9 o 12 VIN 1 o SIN( o 0. SPICE benchmarks.
4) .pwr * END • DC V(5) .AC DEC 10 1 10GHZ .TF V(5) VIN .25 0.005 .OP .pwr TRAN V(5.25 0.404 E SPICE INPUT DECK * .DC VIN 0.pwr AC \!M(5) VP(5) .TRAN 5N SOON * * OUTPUT REQUESTS * .
349. 149157 operating (bias) point. 335. 157164. BR. 1920. 196204. 284 pivoting. 279 linear equation solution: Gaussian elimination. 2226. 299312. 7986. 296297. 291296 numeric integration. 285291 Markowitz. 210213. 297. 346349 transient ramping. 381384 parameters. 169180 Approximations. 290291 reordering. 133136 smallsignal transfer function.148 polezero. 244262. 117125.2426. 238. 125129. 371 . 5. 290 sparse matrix. 151. 380381 405 . 2426. 114140 timedomain. 129132 transient. 1617. 368372 direct methods. See also Numeric integration Amplifier. 184191 noise. 291298 limiting. 312314 Accurac~ 285291. 145149. 164166 sensitivity. 2933. 116117 types: AC frequency sweep. 253284 LV factorization. 294295 NewtonRaphson. 164. 241277 Fourier. 2933. 280283 nonlinear equation solution. 285 modified nodal analysis. 142 ACCT. 215216 Algorithms: convergence enhancing: source ramping. 350352 distortion. current Bias point. 1617. 9394. 298. 246 DC transfer curves. 380384 device. 3436. 114115 parameters. 308. 315. 122 B B (nonlinear controlled source) element. 8696. see Gain. 3. 168192 overview. 213216 BF. 142149. 159164 Analysis: modes: AC. 1417. 14. 1517. 130132. 119121.INDEX A ABSTOL. see Analysis Bipolar junction transistor (BIT). 153157. 39.119121. 285. 141167 DC. 308312 Adder circuit.AC. 4748. 7896. 7879 model: equations.
401 Conventions. 1922 Continuation line. 379380 parameters. 378 Distortion: crossmodulation. 189190. 311312. 61.319377 Crossmodulation distortion. 68. 368374 inverter. 7677. 6465 Current source: controlled. 57. 45. 126127. 44 nonlinear. 350352 thermalvoltage referenced source.DC statement. 18. 79. 205. 14. 76. 75 model: equations. 5865.99 MESFET. 82. 227240 subcircuit. 330335 Schmitt trigger. 4245 CHGTOL. 159. 254255 . 143145. 221. 360362 opamp. 7677. 9395. 102103. III D DC analysis. 275276 DIM3 output variable. 87. 75. 7576 Device initial conditions (IC). 280. 4142. 186189. 163. semiconductor. see Adder circuit logic functions. 261. 353355 c Capacitance. 114140 DC bias. see Semiconductor device model Capacitor: linear. 362367 Differentiator. 4243. 194204 CMOS circuit: differential amplifier. 296298. 381382 diode. 180184. 213227 ideal. 391 Controlled source. universal. 6365. 378 JFET. 18.385389 . 209213 TTL gate. 5658 Comment line. see Analysis Default values: BJT.406 INDEX Bistable circuit. 7983. 6567 voltage source (CCVS). 275276 Diode: device. 291. 78. 213216 linear. see Distortion Current controlled: current source (CCCS). 19. 73. 6165 nonlinear. 345349 Coefficient of coupling k. 46 Convergence. 213216 polynomial. 45. 97 BV breakdown voltage.110 MOSFET. 16. 158. 223224 DIM2 output variable. 6165. 2933. 163. 384385 D (diode) element. 379 JFET.9697 MESFET. 149 Branchconstitutive equations (BCE). 38. 220221 Digital circuit: adder. 133136 independent. 22. 5965 Control statement. 3839. 44 semiconductor. 6162. III MOSFET. 96. 109. 342344 Bode plot. 261262 harmonic. 380381 diode. 148. see Analysis DC model: BJT. 226227 Curtice model. 159. 125127 DC transfer curves. 78. 6364 current mirror. 4243 model. 78. 323325 Currentvoltage characteristics. 76. 77.314315. 12. 157158. 69. 39. 4445 C (capacitor) element. 87. 137138. 204213 macromodel.252254 intermodulation. 316 Circuitblock models: functional. 4656 zerovalued. 6364 switch.
4. 187189 .38 GummelPoon model. 180184 Initial transient solution. 66. 96. 116. 143. 81. 194195. 5354 GMIN option. 400401 . 169. 298. 316 G (VCCS) element.NODESET). 399400 . 1822 Element statement. 6465 Hybrid parameters. 256257. 163. 22 Error messages. 263274 smallsignal. 163. 241262 total harmonic.ENDS statement. 329. 184189 HD2 output variable. 391398 Euler integration. 381382 H Harmonics. 195 . 158159 Divider. 159. 16. 5658 polynomial. 174177 feedback factor. 180181. 131. see Circuitblock models I (current source) element. 173. 278 INOISE output variable. 175 loop gain. 1920. 4647 Independent source: current. 315 F FC parameter. 314. 297298. 2122. 275 HD3 output variable. VAR. 180181. 328 Feedback circuit. 205. 216217 E Early voltage. see Analysis Functional model.END statement. see Bistable circuit Floatingpoint accuracy.INDEX 407 largesignal. 137139. 152 Input language (SPICE). 1822 Input resistance.IC). 184185. see Device initial conditions node voltages: DC (. see Algorithms Gear integration. see Device initial conditions . 3134 Flip. see Current source voltage. see Transfer function Integration. 326. 8183. 220221. see Voltage source Inductor: linear. 13.FOUR statement. 121.IC statement. 19. 145 voltage. see Numeric integration GEAR option. 8792.DISTO statement. 2229. 136139. 46 Initial conditions: IC keyword (device line). 275 H (CCVS) element. see Numeric integration Integrator. 287290 Fourier series. 305307. 6263 Electric circuit. 157164. 189 . 175176 F (CCCS) element. see Distortion Inverter. 93 EbersMoll model. 344 timedomain (. 376 Ground. 6364 File input/output. 195197 ITL options. 335 Initialization: devices (IC).flop circuit. 169. 93 I Ideal models. 205 Gaussian elimination. 19. 185 Frequency sweep. 164. 84. 22. 6162 Global statement. 159. 7983 E (VCVS) element. 137139. see Circuitblock models G Gain: current. 45 mutual. 3. VAF. see Numeric integration EXP signal source. 225226 Intermodulation distortion. 181183.
303304 linearization. 42. 307. 280282 . 385390 parameters. 74. see Distortion L (inductor) element. 225227 Largesignal: analysis. JFET. 196204. 126128 parameters. MESFET.382383 Junction field effect transistor (JFET): device. 10911 0 model: equations. 44. 5658 Kirchhoff's laws. Capacitor. . 292293.143. 75 Models: capacitor. see ShichmanHodges model semiconductor devices. see Algorithms MAXORD option. 15. 151. 148149 Matrix. 307. 8796. 9798 parameters. 39. 12. 289291. 279. 4546 Limiter circuit. 4142. 379. 14 Linearization.39. 99101 K K (coupled inductors) element. 96 Junction capacitance: forward bias. see Model linearization LIST option. 141. 346 Nodal analysis. 328. 323325. 77. 394 L Lamp. 257. 44. 86. 74. 100101.408 INDEX J J (JFET) element. see Feedback circuit L (length) parameter. 384385 Metalsemiconductor field effect transistor (MESFET): device. 2122. 326 Loop gain.MODEL statement. 379. see Inductor N NAND circuit. 292293 parameter extraction. see EbersMoll model GummelPoon. 265276 Model: companion. see Circuitblock models Magnitude. 316 M (MOSFET) element. 316 Mixer circuit. see Algorithms NFS parameter. 2. 314. 4. Resistor types. 382383 reverse bias. 395 sparse. 215216 Mutual inductance. see PIVTOL option reordering. 8486. discharge. 14 distortion. 115. see GummelPoon model Raytheon. 287. 1216. see Algorithms Multiplier. 102103 M Macromodel. 110111 parameters. 108109. 210212 NewtonRaphson. 68. MOSFET. see Raytheon model resistor. 141142. 101102 model: equations. 99. 316. see Capacitor EbersMoll. 97. III METHOD option. 77. circuit: PIVREL option.300. see Resistor ShichmanHodges. 83. 101102 Metaloxidesemlconductor field effect transistor (MOSFET): device. see PIVREL option PIVTOL option. Diode. 289. AC response. 102107. see Algorithms Linear circuit. 108. see Bipolar junction transistor. 321. 14. 7475 . see Algorithms singular. 143145. 96 model: equations. 129130. 105106. 218222 Limiting. III Modified nodal analysis (MNA).
Quality factor Q relaxation. see Ground numbering. 300305 Gear. 117125 Option parameters: ABSTOL.317. see VNTOL option Oscillator: Colpitts. see PIVREL option PIVTOL. 323325 Operating point information.375 LIMPTS. 155156 Opamp: CMOS. 102.NODESET statement. 220221 macromodel.75. 109110. 102. 129. 305307. 136.RELTOL TNOM. 256257 Output variables.317 OPTS. 375 ITL3. 115116. 229238. 308312 stability. 297. 96. 339. 152.321323 zerovalued current source. 159.317 DEFAS. 330. ONOISE output variable. 316.. 150151 . 356358 ring. 21. 151152 NOR circuit. 171 quality factor Q. 312. 204207. see MAXORD option METHOD. 383384 diode. 357 NOPAGE. 322323 Nodevoltage method. 175176 o OFF initialization. 315.351 DEFW.347. 335338 Open circuit: DC. 315.7879. 169170.335. 145148. 300305 forwardEuler. 288289 startup. 66 . ~15316. 339. 310311.347. 375 ITL2. localtruncation error. 316. seeCHGTOL DEFAD. 204 NODE option.INDEX 409 Node: connection. 150151 Noise models: BIT.317 LIST. see TNOM option TRAP. 380 MOSFET. 210212 Number fields. 20 Numeric integration: backwardEuler. . see Analysis . 297. 368. 102. 341. 330335 functional model. 301303. see NODE option NOMOD. 152. see ACCT CHGTOL.see GMIN option ITLl. 297298.OP statement.364 Output resistance. see ABSTOL ACCT. 315. 131. 304305. 335. 311. 177178.357 NUMDGT. 376 ITL5. 150151. 298. 102. 181:182. 185 . 190191 crystal. 315 ITL4. 373. 317 . 315. 93. see Nodal analysis . 228239 iLA741. 133.317. 326. see PIVTOL option RELTOL. see. 343344. see GEAR option GMIN. 321 ground. 128:129 meansquare value. 281282.351 GEAR. 182184. 151. 204. 362367 damping factor. 117119. H 9. 154157 output.86. 315 ITL6. 353. 316 PIVREL. 174180. 316. see. 155157 margins. see LIST option LVLTIM. 101102. see TRTOL option VNTOL.NOISE statement. 74. 207209 ideal model. 337341 ON initialization. 353 MAXORD. see TRAP option TRTOL. 1921. 307 trapezoidal. see METHOD option NODE. 301306 Nyquist diagram. 346. 330. 137.' DEFL. 371 Noise: input. 311. 151152 source. 143. 66.390 resistor.
see Analysis. 4142 thermal noise.PLOT statement. 141. 2937. 104105. 358359 R (resistor) element. 2836. 109. 170 Plotting results: Nutmeg. 96. see Diode hybrid. 350352 Schottky barrier diode. 109 Schematic. 86. 2021. 4344 controlled sources. 77.SENS statement. 102. 127. 7879 Quality factor Q. 97. 2937. 326328. 164 parasitic. 102. 7678. 182. 41 input. 143145.410 INDEX p Phase. 170 . 290291. 143144. AC response. 382 junction. 159160. see Bipolar junction transistor data sheet. 9495. types Smallsignal bias solution. 78. 111 Resistor: model. 368 . 127 xgraph.152. circuit. see Junction capacitance metaloxidesemiconductor (MOS). 289291. 4850 PWL signal source. see Junction field effect transistor MESFET. 322325.152. 144 PULSE signal source. 33 Probe. see Analysis .PZ statement. see Metaloxidesemiconductor fieldeffect transistor Sensitivity analysis. 296297. 75. 217218 total dissipation. 78 S (voltagecontrolled switch) element. 143. 62 semiconductor. 2325. see Transfer function . 66 Semiconductor device model: capacitance: diffusion. 371 PIVTOL option. 4G42 RELTOL. 16. 133 SFFM (singlefrequency frequencymodulated) signal source. 117. parameter extraction diode. 353355 halfwave. 314. 75. 18 Schmitt trigger. 148149 PIVREL option. 159160. 5965 inductor. 87. 103 Scale factors. 143144. 164165 Polynomial functions: capacitance. 87. 148. 375376 Resistance: function of temperature. see Transfer function output. 362 R Raytheon model. zeroes. operating (bias) point Q Q (BJT) element. 13. circuit. 4556 Power: measuring circuit. 97. 95. 177. 315. 5456 . 4142 nonlinear. 379. 99. 125 . 20. see Hybrid parameters JFET. 5153 ShichmanHodges model. 311. see Analysis. 115116. 164.PRINT statement. 3436. see Noise models Result processing. 115116. 79. 389390 parameters: BJT. 3435 Poles. 99.154156. 110 Rectifier: fullwave. 5052 Smallsignal analysis. 81. see Metalsemiconductor field effect transistor MOSFET. 349. 278279 SIN (sinusoidal) signal source. see Oscillator s Saturation current IS. 8384. 115116 Ring oscillator. 149. 3536. 314.PROBE statement. 88. 207 Polezero analysis. see Model. 308. 102103 Simulator.
see Input language SPICE programs: HSPICE. 164. 169170. 145.215. 7475. 352. see Analysis. 33. 5. 379 MOSFET. 309. 219221 SPICE3. 86. see Analysis transient. 278280 smallsignal bias. 145. 119 Transfer function.221. 77. 182. 195204 definition. 6869 Temperature analysis: BJT. see Convergence initial transient. 345349 Timedomain analysis: spectral (Fourier). 177. 316. 6667 . 86.390 resistor. 110. 316. 148. 362 Subcircuit: call (instance). 20. see Accuracy bypass. 84. 394 Total harmonic distortion. 379 Topology: circuit. 20. ideal. 79. operating (bias) point stability. 116. 125 v V (voltage source) element. 28.239 SpicePlus. 174177. 153. 194195 . 15 errors.205207 gain. 164. 58 Transient ramping. 1. 27. 344. 226. 239 IsSpice. 169 TRAP option. 76 Thermal voltage referenced bias. 316 TRTOL option. 173. 354. 106107. 4. Metaloxidesemiconductor field effect transistor. 18. 298. see Numeric integration tolerances. 34. 198199.169. 222. 98. 23. types. 6265. 305. 18.TF statement.383 diode. 308312. 194195 Switch: element. 223224 u VIC (Use Initial Conditions) keyword. see Initial transient solution overview. 239 SPICE2. 27 PSpice. 143. 102. 296297. 291. 375 T T (transmission line) element. 131. 298 Spectral analysis. 45. 98. 143. see Analysis Timestep control. Fourier SPICE input language. 6566 model. 43. 93.TEMP statement. 116 . see Analysis. 368. 173. 18. 21. 67. 27. 8486. 107 Solution: accuracy. 23. 376 TTL gate. 306. 14.~eep. 321. 90. 96. 116117 . 3334. 164. 296297. 4647 VNTOL option. Metalsemiconductor field effect transistor Transit time. 41. 21. 37. 21. 164. 83. 185. 20. 315. 13. 289291. 323. 368 Transistors. 131"132. 77. 131 Transformer. 29. 129130 Thermal voltage. 382383 Transmission line. 2628. Junction field effect transistor. 239 Steadystate solution. 315 .SUBCKT statement. Vth. 366. 311 convergence. 314316 Source ramping.INDEX 411 Smallsignal parameters. 69. 181183. 58.205 input resistance.TRAN statement. see Distortion Transconductance. 7. 222223. 6871 . see Bipolar junction transistor. 309311 TNOM option. 131 output resistance.
99100. see SIN signal source W (currentcontrolled switch) element.412 INDEX Voltage: breakdown. 6265 independent.l\. 6162 switch. 386388 threshold. 110. see PWL signal source SFFM. 281.. 317 W (width) parameter. 44. 100. 103. x X (subcircuit call) element. 195 '. 66 . 99100 saturation. . BV. see EXP signal source PULSE. 4656 Volterra series. 9697. 97. see PULSE signal source PWL. Result processing EXP.WIDTH option. 6263 Voltagedefined element. VTO. see SFFM signal source SIN. 285286 Voltage source: controlled. 4142. 110111 Voltagecontrolled: current source (VCCS). see BV breakdown voltage pinchoff. 243 w Waveforms: display. see Plotting results. 6567 voltage source (VCVS). 102103 '.