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Andrei Vladimirescu
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John Wiley & Sons, Inc.
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ACQUISITIONS EDITOR Steven Elliot MARKETING MANAGER Susan Elbe PRODUCTION SUPERVISOR Richard Blander DESIGNER Kevin Murphy MANUFACTURING MANAGER Inez Pettis ILLUSTRATION COORDINATOR Anna Melhorn This book was set in Times Roman by Publication Services and printed and bound by Malloy Lithographing. The cover was printed by Phoenix Color Corp. The paper in this book was manufactured by a mill whose forest management programs include sustained yield harvesting of its timberlands. Sustained yield harvesting principles ensure that the number of trees cut each year does not exceed the amount of new growth. Copyright @ 1994, by John Wiley & Sons, Inc. Published simultaneously in Canada.
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Library of Congress Cataloging in Publication Data:
Vladimirescu, Andrei. The spice book / Andrei Vladimirescu. p. cm. Includes bibliographical references. ISBN 0471609269 1. SPICE (Computer file) 2. Electric circuit analysisData processing. S. Electronic circuit designData processing. I. Title. TK 454.V58 1994 621.319'2'028553dc20
9333667 CIP
Printed in the United States of America 10 9 8 7 6 5 4 3 2 1
PREFACE
This book is written for electrical engineering students and professionals who use one of the many versions of the SPICE program to analyze and design circuits. The topics presented in this book are universally valid for SPICE users no matter which version they use. This point is reinforced in the text by using the most popular SPICE versions to run the examples developed in the chapters. SPICE has become the standard computer program for electrical simulation, with over 40,000 copies in use worldwide. The name SPICE stands for Simulation Program with Integrated Circuit Emphasis and was inspired by the application to integrated circuit (IC) design, which made computer simulation mandatory. Today, SPICE in its many versions is used not only for IC design but also for analog printed circuit boards, power electronics, and other applications. The majority of the commercial SPICE packages are based on and support the functionality of SPICE2, version G6, from the University of California at Berkeley. The current circuit simulation development at the University of California at Berkeley is devoted to the SPICE3 program. Few commercial products are based on SPICE3, but a number of these programs support SPICE3 functionality that is not available in SPICE2. A commercial version of SPICE that has gained popularity in universities is PSpice, from the MicroSim Corporation. PSpice, which was first introduced as a Personal Computer Program, has become very popular because of the wide use of PCs. The material in this book was developed based on the SPICE2 program, whose functionality and syntax are supported by all other SPICE simulators. The SPICE netlist standard is defined by SPICE2, and all derivatives of the program accept a SPICE2 input file; functionality specific to a certain SPICE program and not available in SPICE2 is introduced as an extension to the SPICE language and is documented in the respective user's guide. Examples throughout this book are simulated alternatively on SPICE2, SPICE3, or PSpice. Functionality available only in SPICE3 is documented, and useful features proprietary to PSpice are mentioned. This book combines in a natural progression a tutorial approach on how to advance from hand solutions of typical electrical and electronic circuit problems to using SPICE, with some reference information on the program necessary for the more advanced user.
VII
viii
PREFACE
The text should be useful to the SPICE novice as well as to the experienced user. The reader is assumed to have a basic electrical engineering background and be able to use a computer. The approach in this book emphasizes that SPICE is not a substitute for knowledge of circuit operation, but a complement. The SPICE Book is different from previously published books on this subject in the approach of solving circuit problems with a computer. The solution to most circuit examples is sketched out by hand first and followed by a SPICE verification. For more complex circuits it is not feasible to find the solution by hand, but the approach stresses the need for the SPICE user to understand the results. Although the program can detect basic circuit specification errors, it cannot flag conceptual errors. It is up to the user to question the program through the various analysis modes in order to get insight into what is wrong with the circuit. Briefly stated, the results of SPICE are only as accurate as the circuit description and the component models used. The first six chapters provide information about SPICE relevant to the analysis of both linear passive circuits and electronic circuits. Each of these chapters starts out with a linear example accessible to any new user of SPICE and proceeds with nonlinear transistor circuits. The latter part of the book goes into more detail on such issues as functional and hierarchical models, distortion models and analysis, basic algorithms in SPICE, analysis option parameters, and how to direct SPICE to find a solution when it fails. This book is ideally suited as a supplement to a wide range of circuits and electronics courses and textbooks. It is of special interest in junior, senior, and graduate courses, from introductory courses on electric circuits up to analog and digital integrated circuits courses. The subject of computeraided circuit simulation is put in a historical perspective in the Introduction to this book. The milestones of the research in the late 1960s and early 1970s that led to the SPICE program are presented first. The proliferation of SPICE versions and the salient features of the most popular programs are described. The Introduction follows the evolution of the SPICE effort at the University of California at Berkeley from the beginning to the present day. This historical perspective concludes with the current research in the area of electrical computer simulation and the possible future SPICE developments in the 1990s. Chapter 1 is an introduction to the computer simulation of electrical circuits and the program SPICE. The approach used in SPICE to solve electrical problems is described in simple terms of the Kirchhoff voltage law, the Kirchhoff current law, and branch constitutive equations. A linear RLC circuit is used to exemplify the workings of SPICE. The reader is also introduced to the SPICE input language, the network specification, the analysis commands, and the types of result output available. The sequence of events for simulating a circuit is completed by examples on how to run SPICE on the most common computers. Chapter 2 presents in detail the circuit specification in terms of elements, models, and the conventions used. The SPICE syntax is detailed for twoterminal elements, such as resistors, capacitors, inductors, and voltage and current sources, and multi terminal elements, such as controlled sources, switches, and transmission lines.
PREFACE
ix
Chapter 3 introduces the semiconductor device elements and models available in SPICE. The dual specification as device and model is explained for semiconductor elements. Only the firstorder models are described in this chapter for devices represented by several levels of complexity. The model parameters are related to the branchconstitutive equations of the device as well as to electrical characteristics. The most important physical effects and corresponding parameters are described for the five semiconductor devices supported: diodes, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), metaloxidesemiconductor field effect transistors (MOSFETs), and metalsemiconductor field effect transistors (MESFETs). This chapter does not cover the details of each model but provides references dedicated to the subject. Chapter 4 contains an overview of the analysis modes of SPICE and a detailed description of DC analysis. In the DC mode SPICE can perform an operating point analysis, compute DC transfer curves, estimate the value of the transfer function, and perform sensitivity calculations. Chapter 5 describes the SPICE functionality in the smallsignal frequency domain. The AC mode analysis types, such as the frequency sweep, noise, and distortion analyses, are introduced by means of both linear and nonlinear circuit examples. Chapter 6 presents the timedomain, or transient, simulation. In the timedomain analysis mode SPICE computes the transient response of a circuit and the harmonics of a signal. At least one workedout circuit example is included for each analysis type. The reader acquires the basic knowledge of using SPICE by the end of this chapter. Chapter 7 introduces the concept of functional simulation. Higherlevel abstractions and hierarchy can be modeled in SPICE using controlled sources and subcircuit blocks. Logic gates and operational amplifiers can be described using the macromodeling approach. Examples demonstrate the compactness and efficiency of macromodeling for opamp circuits. The last three chapters of the book, Chaps. 8 to 10, are intended for the more advanced user. The material presented in the first part should be sufficient for solving most circuit problems encountered in undergraduate and graduate courses. There are three main topics in the second half, which can be be studied independently of each other. Chapter 8 covers in some detail distortion analysis, Chap. 9 contains an explanation of the solution techniques built into SPICE and the analysis options that may be necessary for solving complex circuits, and Chap. 10 uses the information in the previous chapter to steer the user on how to ensure the convergence of SPICE. Chapter 8 offers an indepth look at distortion analysis. The details of smallsignal and largesignal distortion analysis are described with the help of several examples. A brief overview of the algorithms and numerical methods used in SPICE is presented in Chap. 9. The purpose of this chapter is to offer some insight into the internal workings of SPICE for the user interested in taking advantage of all the available analysis controls or options, which are also described in this chapter. The main topics are solution of sparse linear equations, iterative solution of nonlinear equations and convergence, and numerical integration. Chapter 10, which concludes this book, is a primer on convergence and the actions a user can take to overcome DC and timedomain convergence problems. Solutions to
X
PREFACE
convergence problems are offered using initialization, analysis options, and nonlinear model parameters. The importance of understanding the operation of the circuit and the limitations of the models used is emphasized for obtaining accurate results. Five appendixes are included at the end of the book. The first contains the complete equations for the semiconductor devices and the full list of model parameters. The second appendix lists the most common error messages of SPICE2 and provides guidance on corrective action. The error messages included are common to most SPICE versions, although the exact wording may differ. Appendix C summarizes all the SPICE statements introduced in this book. Appendix D contains the Gear integration formulas of orders 2 to 6. The last Appendix contains a sample SPICE deck of a circuit that requests most analyses supported by SPICE2. This book is a result of my association with Professor D. O. Pederson, who has guided me during my academic studies as well as during my professional activity. I acknowledge Judy Lee for the graphic design and the presentation of the schematics and the simulation results. I also acknowledge the review and comments contributed by Dr. Constantin Bulucea in addition to the valuable comments made by the following reviewers for John Wiley and Sons: Kenneth Martin, UCLA; Richard Dort, University of California at Davis; Ron Rohrer, Carnegie Mellon University; Norb Malik, University of Iowa; Bruce Wooley, Stanford University; Darrell L. Vines, Texas Tech University; James R. Roland, University of Kansas; David Drury, University of Wisconsin, Platteville; Robert Strattan, University of Oklahoma; John O'Malley, University of Florida, Gainesville; Gordon L. Carpenter, California State University, Long Beach; and Elliot Slutsky, Cal Poly, Pomona. Together with colleagues and customers of Daisy Systems, Analog Design Tools, Valid, and Cadence, as well as University of CaliforniaBerkeley students, they have contributed to the material covered in this book. October 1993 Andrei Vladimirescu
CONTENTS
Introduction
SPICETHE THIRD DECADE
1 1
~,', I
1.1 THE EARLY DAYS OF SPICE 1.2" SPICE IN THE 19705 i.3 SPICE IN THE 19805 1.4 SPICE IN THE 19905 1.5 CONCLUSION REFERENCES
2 4 7 8 9
I.
Chapter One
INTRODUCTION SIMULATION
1.1 1.2 1.3
TO ELECTRICAL COMPUTER
12
PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS WHAT IS SPICE? USER INTERACTION WITH SPICE AND THE COMPUTER
1.3.1 1.3.2 1.3.3 Electric Circuit SpecificationThe SPICE Input SPICE Simulation, DC Analysis . SPICE Results for AC and TRAN Analyses
12 14 17 18
22
28
36
1.4 SUMMARY REFERENCES
37
XI
xii
CONTENTS
Chapter Two
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
2.1 2.2 ELEMENTS, MODELS, NODES, AND CONVENTIONS TWOTERMINAL ELEMENTS
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Resistors Semiconductor Resistors (SPICE3) Capacitors Semiconductor Capacitor (SPICE3) Inductors Independent Bias and Signal Sources 2.2.6.1 Pulse Function 2.2.6.2 Sinusoidal Function 2.2.6.3 FrequencyModulated Sinusoidal Function 2.2.6.4 Exponential Function 2.2.6.5 Piecewise Linear Function Coupled (Mutual) Inductors Dependent (Controlled) Sources 2.3.2.1 VoltageControlled Current 2.3.2.2 VoltageControlled Voltage 2.3.2.3 CurrentControlled Current 2.3.2.4 CurrentControlled Voltage Switches Transmission Lines
38 38
39
40 41 42 44 45 46 48 50 51 53 54 56 56 58 61 62 63 64 65 68 71 72
2.3
MULTITERMINAL ELEMENTS
2.3.1 2.3.2
Source Source Source Source
(VCCS) (VCVS) (CCCS) (CCVS)
2.3.3 2.3.4
2.4
SUMMARY
REFERENCES
Chapter Three
SEMICONDUCTORDEVICE
3.1 3.2 3.3 INTRODUCTION DIODES BIPOLAR JUNCTION TRANSISTORS
3.3.1 3.3.2 3.3.3 DC Model Dynamic and SmallSignal Models Model Parameters
ELEMENTS
73 73 75 78 79 83 86 96 101 102 103
108
3.4 3.5
JUNCTION FIELD EFFECTTRANSISTORS (JFETs) METALOXIDESEMICONDUCTOR
3.5.1 3.5.2 3.5.3
FIELD EFFECTTRANSISTORS (MOSFETs)
DC Model Dynamic and SmallSignal Models Model Parameters
2 5.169 ANALYSIS DESCRIPTION TRANSIENT ANALYSIS .7 OPERATING (BIAS) POINT DC TRANSFER CURVES SMALLSIGNAL TRANSFER FUNCTION SENSITIVITY ANALYSIS NODE VOLTAGE INITIALIZATION SUMMARY REFERENCES Chapter Five AC ANALYSIS 5.3 4.1.7 METALSEMICONDUCTOR SUMMARY FIELD EFFECTTRANSISTORS (MESFETs) REFERENCES Chapter Four DC ANALYSIS 4.142 149 157 164 165 167 REFERENCES Chapter Six TIMEDOMAIN 6.1 ANALYSIS OVERVIEW 4.1.4 5.6 4.CONTENTS xiii 109 112 113 3.2 ANALYSIS168 168 .4 4.3 5.5 5.3 4.5 4.1 6.2 Simulation Modes and Analysis Types Result Processing and Output Variables Analysis Parameters: Temperature 114 114 114 115 116 117 125 129 133 136 139 140 4.6 3.1 4.1 5.6 INTRODUCTION AC FREQUENCY SWEEP NOISE ANALYSIS DISTORTION ANALYSIS POLEZERO ANALYSIS SUMMARY 141 141 .1.2 4.
2 7.4 FUNCTIONAL MODElS 704.5 CONTENTS INITIAL CONDITIONS FOURIER ANALYSIS SUMMARY 180 184 REFERENCES 191 192 Chapter Seven FUNCTIONAL 7.2 241 241 241 242 244 263 263 265 276 277 DISTORTION ANALYSIS HighFrequency Distortion Distortion in a OneTransistor Amplifier OneTransistor Amplifier Distortion SingleDevice Mixer Analysis 8.1 8.1 7.5.2.2.2.6 MACROMODElS 7.3.3.xiv 6.3 IDEAL MODElS 7.1 7.3 70404 7.1 7.1 SUMMARY REFERENCES 239 240 Chapter fight DISTORTION ANALYSIS 8.2.3 LARGESIGNAL DISTORTION ANALYSIS 8.2. SUBCKT Definition Subcircuit Instance Circuit Hierarchy Operational Ampl ifiers Logic Gates and Digital Circuits Nonlinear (ArbitraryFunction) Analog Function Blocks Digital Function Blocks Equation Solution The Opamp MacroModel Controlled Sources in SPICE3 7.1 704.5 7.2 7.4 SUMMARY REFERENCES .1 8.3.2 704.2 DISTORTION IN SEMICONDUCTOR CIRCUITS SMAllSIGNAL 8.3 .1 8.3 6.3.2 AND HIERARCHICAL SIMULATION 193 193 194 194 195 195 204 205 209 213 213 215 223 224 227 228 HIGHLEVEl CIRCUIT DESCRIPTION SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 7.2 8.4 6.
1 NewtonRaphson Iteration 9.1 Circuit Description 10.4 Numerical Integration 9.1 Circuit Equation Formulation: Modified Nodal Equations 9. 312 314 315 315 316 317 OVERVIEW OF ALGORITHMS DC SOLUTION OF LINEAR CIRCUITS 9.2 Component Values DC CONVERGENCE TIMEDOMAIN CONVERGENCE CIRCUITSPECIFIC CONVERGENCE 10. Accuracy.3 9.5 SUMMARY OF OPTIONS 9.4 9.5 10.2. and Options 9.2 INTRODUCTION COMMON CAUSES OF SOLUTION FAILURE 319 319 320 320 326 330 353 362 362 367 373 375 377 10.6 REFERENCES .2 AND OPTIONS 278 278 280 280 285 291 291 296 298 299 307 312.5.3 Convergence of Large Circuits SUMMARY 10.3.5.3 Nonlinear Solution Options 9.4.2 Linear Equation Options 9.2 8JT versus MOSFET Specifics 10.5.2.5 Miscellaneous Options REFERENCES Chapter Ten CONVERGENCE ADVICE 10.2.4.2 Accuracy and SPICE Options DC SOLUTION OF NONLINEAR CIRCUITS 9.2 Numerical Integration Integration Algorithms in SPICE.2 Convergence and SPICE Options TIMEDOMAIN SOLUTION 9.1 10.2.5.3 10.1 9.1 Analysis Summary 9.5.1 Oscillators 10.5.1 9.5.5.4 10.3.CONTENTS XV Chapter Nine SPICE ALGORITHMS 9.
l B.2 A.2. Transient.2 C.3.3.1 A. and AC Models Temperature Effects Noise Model DC Model Transient and AC Models Temperature Effects Noise Model DC Model Transient and AC Models Temperature Model Noise Model MODELS 378 378 379 379 380 380 381 382 383 383 384 385 389 390 390 390 A.2.1 A.4 A.4 B.2.l C.2 A.1 A.2.7 B.l DIODE A.3.3. CIRCUIT TOPOLOGY ERRORS SUBCIRCUIT DEFINITION ERRORS ANALYSIS ERRORS MISCELLANEOUS ERRORS AND MODEL ERRORS 391 391 392 392 393 394 394 395 398 APPENDIXC SPICE STATEMENTS C.5 B.2 B.3 A.2 A.8 GENERAL SYNTAX ERRORS MULTITERMINAL ELEMENT ERRORS SOURCE SPECIFICATION ERRORS ELEMENT.1.3 DC. SEMICONDUCTORDEVICE.1.3 MOSFET A.XVI CONTENTS APPENDIX A SEMICONDUCTORDEVICE A.1.3 B.6 B.3 A.3 ELEMENT STATEMENTS GLOBAL STATEMENTS CONTROL STATEMENTS 399 399 400 401 .2 BIPOLAR JUNCTION TRANSISTOR A.4 REFERENCES APPENDIX B ERROR MESSAGES B.
CONTENTS xvii APPENDIX D GEAR INTEGRATION APPENDIX E SPICE INPUT DECK INDEX 403 FORMULAS 402 405 .
.
The current trends in electricalcircuit simulation and the role of SPICE in its third decade are presented in the last part. Rohrer. That this program was written by engineering students for engineers explains the simple and computationally efficient approach chosen for the network equations and the builtin semiconductordevice models. which in its various versions enjoys 1 .1 THE EARLY DAYS OF SPICE SPICE in its different versions has been the main computeraided analysis program used in analog design for over 20 years. under the guidance ofD. Nagel 1975). and intended areas of application is provided first.Introduction SPICETHE THIRD DECADE This introduction is a review of the evolution of SPICE from the initial research project at the University of California at Berkeley in the late 1960s. The relation between solution algorithms. who had a mandate to produce the best computer program for the simulation of practical integrated circuits. Pederson and R. and into the 1990s. analysis modes. and circuits to be characterized is explored in order to clarify the merits and limits of this program. semiconductordevice models. A general description of SPICE techniques. ICs. SPICE is the result of the work of a number of talented graduate students in the Department of Electrical Engineering and Computer Science at the University of California at Berkeley. through the 1970s and 1980s. 1. SPICE2 (Cohen 1975. The program known as SPICE today was first released under the name CANCER (Nagel and Rohrer 1971) in 1970 and acquired the name SPICEI (Nagel and Pederson 1973) in 1972.
Jenkins. a program for the nonlinear DC solution of bipolar circuits. integration algorithms. called the new version SPICE. input language. 1968) at Autonetics. The most important addition to this program was in the area of semiconductor device models. techniques. Nagel. limiting techniques. and transistors. BIAS3 (McCalla and Howard 1971). Simulation Program with IntegratedCircuit Emphasis. sparsematrix solutions.2 INTRODUCTION SPICETHE THIRD DECADE the largest use worldwide today.2 SPICE IN THE 19705 In the early 1970s L. nonlinear equation solution. 1. and CIRPAC (Shichman 1969) at Bell Labs. Pederson (1984). In the design oflinear ICs such as the /LA 741. and the program was developed and initially used on a CDC 6400. was developed. The algorithmic research carried out during the development of these programs converged to the use of the NewtonRaphson solution of nonlinear equations. A better model for bipolar transistors. was released in 1975. The main goal of the SPICE project has been to provide an efficient computer tool for the design of the emerging ICs in the late 1960s and early 1970s. implicit integration methods using fixed time steps. the integral chargecontrol model . continuing to develop the CANCER type of program. a division of Rockwell Corporation. The universal acceptance is due not only to its robustness and ease of use but also to its free distribution by DC Berkeley. These efforts were continued through the 1970s with the MSINC program at Stanford and MTIME. and reordering schemes for sparse matrices. which is still in use at Motorola. It is important to note that the early years of the SPICE development were dedicated to the investigation of the most accurate and efficient numerical methods for circuit representation. An excellent review of the algorithms. diodes. and milestones in circuit simulation evolution can be found in the paper by D. The emphasis on linear IC design using bipolar technology explains the priority given the implementation of bipolar device models. and up to 100 nodes. checking the bias point and performing a smallsignal analysis were essential. it was later included in SUC (Idleman. First. The algorithms of TRAC evolved into the programs TIME (Jenkins and Fan 1971) at Motorola and SINC at Berkeley. McCalla. and nonlinear semiconductordevice modeling. and Pederson 1971) to address the analysis of linear bipolar ICs. The circuit decks were submitted on punched cards. with only 100 transistors and diodes. A number of related programs originated from this research. The need for accurate largesignal timedomain simulation for the characterization of highly nonlinear circuits such as oscillators fueled the research for numerical integration and the development of the programs TRAC (Johnson et al. CANCER (Nagel and Rohrer 1971) implemented the EbersMoll model (Ebers and Moll 1954) for the bipolar transistor described by 18 parameters. The choice of the nodal admittance representation is based on the relative ease of setting up the circuit matrix and the quick access to the DC operating point. The circuit size was limited to 400 components. In May 1972 SPICEl was distributed for the first time in the public domain (Nagel and Pederson 1973).
was introduced at this time to overcome the long run times required by the use of detailed transistorlevel schematics. which are simulated much faster. Independent research on circuit simulation conducted at IBM. ASTAP and SPICE2 used implicit. Mehta.SPICE IN THE 19705 3 of H. was introduced in 1970. A new circuit representation. which allowed access to all desired circuit state variables at the cost of run time and memory. Cohen. ASTAP used a different circuit representation. The accuracy and speed of the analysis were improved by the addition of a timestep control mechanism and the stiffly stable multipleorder integration method of Gear (1967). and these circuits used mostly nchannel MOS devices. The first macromodels were developed for operational amplifiers by replacing many transistors through functionally equivalent controlled sources. The next major release of the program. Macromodels are to this day the main approach to representing SPICE equivalent circuits for a variety of complex ICs. led to the ASTAP program (Weeks. the first commercially supported version. and Solomon 1974). and Scott 1973). Gurnmel and C. A new push was initiated by industry to improve the SPICE2 device models to keep up with technology. Idleman et al. known as macromodeling (Boyle. SPICE2 (Nagel 1975). This new representation added support for voltagedefined elements. Poon (1971). In the late 1970s all semiconductor companies used circuit simulation and most adhered to SPICE. known as sparse tableau. such as voltage sources and inductors. noise. such as drain and source . Mahoney. and Brennan 1975. This trend of commercial SPICE derivatives grew considerably in the 1980s. Models for two other semiconductor devices were added to SPICE1: the junction field effect transistor (JFET) and the metaloxidesemiconductor field effect transistor (MOSFET). A noteworthy event that took place in the second half of the 1970s was the introduction by NCSS of ISPICE (Interactive SPICE). It was important to add device geometry information. In this first implementation the two models were very similar and were based on the firstorder quadratic model of H. A new approach to IC modeling. and represented a major advancement over the EbersMoll model. Quassemzadeh. This capability addressed the need to design larger ICs. because by the mid1970s ICs had grown in complexity and the component limit of SPICE1 had become a serious limitation. replaced the old nodal analysis. A memory management package was developed in SPICE2 (Cohen 1975). such as highlevel injection and lowlevel recombination. Jimenez. Hodges (1968). leading to their classification as thirdgeneration circuit simulators (Hachtel and SangiovanniVincentelli 1981). Ruehli. known as modified nodal analysis (MNA) (Ho. 1971). available in SPICE1. included secondorder effects. and distortion. This model. Shichman and D. the adjoint network. It allowed the program to allocate dynamically the entire available memory to the solution of the circuit. IC technology had advanced the complexity of circuits to largescale integration. A novel circuittheoretical concept. was introduced by Director and Rohrer (1969) in the late 1960s and added to SPICE very efficient computation of sensitivity. LSI. was completed in 1975 and offered significant improvements over SPICEl. which had introduced ECAP in 1965. The representation of MOSFETs in SPICE2 was significantly overhauled at this time. Pederson. variableorder integration and the NewtonRaphson nonlinear solution.
Algorithmic innovation in timing simulation (Newton and Sangiovanni. and Newton 1983). and transittime modeling were added to the GummelPoon model. 1984.Vincentelli 1984) led to the waveform relaxation technique. used in the SPLICE simulators (Kleckner. Although fast. and engineers were able to view the results of the simulation on their terminals as soon as the analysis had been completed. Improvements such as base pushout. and Kozak 1975). perimeters. exemplified by the RELAX2 program (White and SangiovanniVincentelli 1983). Examples include HSPICE from MetaSoftware (1991). had little help when using publicdomain programs such as SPICE. and shortand narrowchannel effects (Vladimirescu and Liu 1980). substrate capacitance. led the way to a number of programs that took advantage of MOSFET characteristics. and the absence of feedback. it became obvious that support for SPICE users was lacking. Bipolar transistor geometries were also shrinking and the frequency of operation rising. and SPICE saw a tremendous increase in use. 1. .4 INTRODUCTION SPICETHE THIRD DECADE areas. or MOS Timing Simulator (Chawla. Kleckner. and number of squares. the infrequency of events in digital circuits. This need was the driving force of new businesses with the charter to upgrade and support publicdomain SPICE2. Gummel. In addition to the simple squarelaw MOSFET model available in 1976. two more complex models were added. that described such effects as subthreshold conduction. Timing simulators such as MOTIS. With the proliferation of the number of users. The increase in circuit size also brought about the need for increasing the accuracy of the sparsematrix solution by allowing for runtime pivoting to correct any singularity that may occur during a long transient simulation.3 SPICE IN TH E 19805 At the beginning of the 1980s. Small engineering firms. the introduction of the minicomputer gave engineering groups easier access to computer resources. split basecollector capacitance. A number of approaches for speeding up electrical simulation by relaxing the accuracy or limiting the class of circuits to which it can be applied were used in several programs. however. carrier velocitylimited saturation. This class of electrical simulators achieved speedups in excess of an order of magnitude compared to SPICE for MOS digital circuits. The need to measure subpicocoulomb charges in memory cells also led to the implementation of a chargebased MOS model (Ward and Dutton 1978) in addition to the existing piecewise linear Meyer capacitance model (Meyer 1971). The attempt to use these programs to characterize analog circuits required the implementation of the more accurate and timeconsuming SPICE device models and often resulted in longer run times than SPICE. Newton 1978. LSI chips required electricalsimulation speeds in excess of an order of magnitude faster than SPICE. Large companies had internal CAD groups dedicated to support and enhancement of software packages for their engineers. which was first introduced in the midl 970s. and iterated timing analysis. timing simulators did not have the accuracy needed in the design of sophisticated microprocessor and memory chips. The VAX 11/780 quickly became the platform of choice for running SPICE. Saleh.
e. DIANA frQm the University of Leuven (DeMan et al. DSPICE.. All three addressed the most lucrative aspect of digital design first. due to either insufficient performance or inflexibility . Danuwidjaja. and the graphic display of results on the same screen/workstation had become obvious . often the result of layout extractors.. Ng. SPICE IN THE 19805 5 o i A differertt approach to faster simulation of complex ICs is the mixedmode. . whereas digital blocks can be evaluated using logic simulation. Niraj. Early efforts in this category include SPLICE from UC Berkeley. and Valid. Program SLATE (Yang.. In spite of these first programs. Flatcircuit netlists. An alternate way to more speed has been to bui'ld dedicated hardware accelerators for circuitsimulation algorithms (Vladimirescu.. These accelerators did not make it beyond a prototype. where individual blocks can be evaluated depending on the perforined function. which in 19811982 introduced integrated software packages for electronic design using microprocessorpowered engineering workstatio~s. was available on the IBM PCXT. SPICE received an additional boost from the three companies Daisy. A major development by the mid1980s was the proliferation of the personal computer in the engineering field. of SIMUCAD Corporation for multipleinstruction multipledata (MIMD) computers.. PCbased SPICE programs have attracted many new users and considerably expanded the popularity of this electric simulator. One possible explanation is that the need for customization of mixedmode simulators for specific applications goes. and SAMSON from Carnegie Mellon University (Sakallah and Director 1980). Speedups of up to an order of magnitude were achieved for circuits having a regular hierarchical structure. such as the Sequent or Alliant machines. The lack of impressive speed returns. which was developed at UC Berkeley for C~AY vector computers. decoupled the analysis of circuit blocks and took advantage of latency to ~peed up the timedomain simulation. • Yet another approach for speeding up electrical simulation was to tailor the directmethod algorithms of SPICE2 to various panHlel computer architectures... which belong to the class of singleinstruction multipledata (SIMD) machines. the de facto reference for SPICE throughput. Weiss. White 1986). .. or hybrid. The field they developed is called computeraided engineering.g. and Lass 1987. simulation. 1980). Mentor. simulation. only analog blocks need electrical characterization. could be :simulated only a few times faster. and the emergence of RISC workstations with everincreasing processing speeds doomed these efforts in the late 1980s. . . Daisy took the lead in electrical simulation devel9pment by supporting an improved SPICE2 version. The need for an integrated analog simulation tool that would cover design entry. DMV realized this need and linked its schematic capture to a SPICE version and developed waveform display tools.against the desire of software tool companies to develop universal tools. Haji. By early 1984 PSPICE (MicroSim 1991). the customization needed for the various parallel architectures. based on the MSPLICE project at UC Berkeley. also referred to as DMV. and PACSIM (Deutsch and Newton 1984). Although eight times slower than I ! on a VAX 11/780. and Trick 1980). good commercial mixedmode simulators are lacking. Examples include CLASSIE (Vladimirescu 1982). as part of its analog :. which emerged from research at the University of Illinois at Urbana. the first pC ver'sion of SPICE.
This feature was first available in ASTAP and then expanded in the SABER simulator (Analogy Inc. and HP SPICE. promoted the behavioral representation of entire circuit blocks by timedomain or frequencydomain equations. Most of these groups had provided output display tools on graphic terminals in the second half of the 1970s. ADVICE at Bell Labs. Tektronix. the goal of which was to rewrite and improve SPICE2 version 2G6 (Vladimirescu. During the 1980s the effort was directed toward robust convergence. easily understood. Newton. The use of continuation methods and education of users contributed toward reliable DC analysis. the widespread use of UNIX in the university research environment offered increased interaction between user and program. University research made new contributions to SPICE technology during this decade. Texas Instruments. Analog Design Tools (ADT). Improved models and techniques for handling discontinuities resulted in robust timedomain simulation as well. initially developed as a piecewise linear electrical simulator addressed to the simulation of analog systems. These limitations led to the SPICE3 project at UC Berkeley (Quarles 1989a). At the beginning of the 1980s. was a FORTRAN batch program and was difficult to modify and limited in its potential use of Cshell utilities. such as TI SPICE. . HewlettPackard.6 INTRODUCTION SPICETHE THIRD DECADE Virtual Lab software. The SPICE technology was also advanced by the contributions of talented CAD groups at Bell Labs. 1987) from Analogy. SPICE2.and boardlevel analog designer and to add new functionality and models to the program to serve the needs of those applications. an Apple Macintoshlike user interface called the Analog Workbench. Zhang. Pederson. who historically had been reluctant to use computers.Vincentelli 1981) using the C language to produce an interactive. Both ADT and Daisy developed analog component libraries needed by analog system designers. such as ADICE from Analog Devices and TekSPICE from Tektronix. SABER. Analog Devices. An important achievement of the concurrent SPICE work in this decade was the elimination to a large degree of convergence problems. accurate semiconductor device modeling. An interesting concept that gained support toward the end of the 1980s was to provide the user the capability of describing the functions that govern the operation of devices used in the simulation. SPICE3 (Quarles 1989b) was released in the public domain in March 1985. A new company. however. and additional functionality and userfriendly features. structured program with a graphic tool for the display of results. The major achievement of these CAE companies was to extend the use of SPICE to the system. Modeling entire circuit blocks at a functionallevel rather than transistor level speeds up the simulation and enables a designer to evaluate an entire analog board or system. modular. which extended electric simulation to boardlevel analog engineers and powersupply designers. emerged in 1985 with a wellintegrated analog CAE product. ideas and results of this parallel research work eventually found their way into publicdomain or commercial software. Although these proprietary developments were not available to the user at large. and National Semiconductor. Harris Semiconductor. while the other two offered a user interface with SPICE2 or deferred the choice of the simulator to the end user. and Sangiovanni.
Input signals are defined and checked in a Function Generator tool. such as switching power supplies. which solves the above problem in the time domain. The major CAE companiesCadence and Mentoroffer a proprietary SPICE version as part of their analog CAE products: Analog Workbench and Analog Artist from Cadence and Accusim from Mentor. no reliable program is available today. Viewlogic. Intusoft. This trend of developing specific functionality for given applications not well suited to traditional SPICE analysis will continue in this decade. an envelopefollowing method is used in NITSWIT (Kundert. Every major supplier of analog CAD/CAE software offers a wellsupported and enhanced version of SPICE2 or SPICE3. Specialized programs such as SWITCAP (Fang and Tsividis 1980) have been developed to fill this need. as well as with physical design tools. Modeling technology is an important aspect of circuit simulation and is instrumental in defining the capabilities and the accuracy of a program . such as printed circuit boards and integrated circuit layout. Although research on this topic took place in the 1970s (Aprille and Trick 1972). This approach is not very efficient for nonlinear transistor circuits.Vincentelli 1986) a nonlinear frequencydomain analysis program developed at DC Berkeley. An example of a stateoftheart analog CAE product is the Analog Workbench II (1990) from Cadence. White. This mode is particularly important for circuits with long settling times. higherlevel modeling. Intergraph. • . One extension is exemplified by Harmonica (Kundert and Sangiovanni. a schematic replaces the SPICE deck. Similar analog CAE packages are available today from Microsim. Timedomain simulation is controlled by popup menus. In order to simulate a differential amplifier.SPICE IN THE 19905 7 1. and component libraries. Current research is under way at MIT and DC Berkeley. and tighter integration with schematic capture. Mentor. such as filter design in general and switched capacitor filters in particular. and the resulting waveforms can be viewed and measured in an Oscilloscope tool. SPICE also lacks capabilities for specific applications. display tools. Solution in the frequency domain is especially useful for finding the steadystate response of circuits with distributed elements and highQ resonators. Analogy. beyond nonlinear DC and timedomain analysis and smallsignal frequencydomain analysis.4 SPICE IN THE 19905 Today SPICE is synonymous with analog computeraided simulation. All information needed for simulation is entered in graphical form and through menus. Another direction of research is steadystate analysis. The main emphasis for the near future is on increased functionality. A number of interesting developments started in this direction at the end of the 1980s. and others. and SangiovanniVincentelli 1988). that is. introduced by Analog Design Tools in 1985. and SSPICE (Ashar 1989) is a vehicle for studying various troubleshooting techniques for the steadystate solution. The circuit is entered as an electric schematic. Significant research will be dedicated to extending the functionality of electrical simulation beyond the established analysis modes of SPICE. a similar setup with a Frequency Sweeper and a Network Analyzer tool is used to control and view the results of an AC smallsignal analysis.
OASYS (Harjani. SPICE will continue to be the main electrical simulator. and 1000 gigabytes of disk storage. is under development under the guidance of the IEEE Standards Coordinating Committee 30. more support will be developed for the behavioral/structural description of entire circuit blocks. according to Bill Joy's forecast at the 1990 Design Automation Conference (Joy 1990).5 CONCLUSION The new developments in circuit simulation do not make SPICE obsolete but rather complement it. Analog Hardware Descriptive Language (Kurker et al. by supporting blocks described by integrodifferential or algebraic equations.000transistor circuit simulation capability. Research work in the area of analog synthesis has been reported by groups at Carnegie Mellon University. In a recent report on PCbased analog simulation published in the magazine EDN (Kerridge 1990). During the next decade analog synthesis tools will evolve to facilitate the design of complex analog and mixed analogdigital systems. which is reported to describe quasisaturation and highfrequency effects better than the current GummelPoon model and which could be a useful addition to SPICE. Rutenbar.8 INTRODUCTION SPICETHE THIRD DECADE At the top level of circuit representation. in order to keep up with evershrinking semiconductor devices. SPICE will probably evolve to an open architecture that would enable CAD groups of IC manufacturers to implement better device models or upgrade the default ones. Sequin. and Gray 1987). Also. and the University of California at Berkeley. In conjunction with other software modules. 1000 megabytes of memory. and OPASYN (Koh. a description language for analog behavior. such as operational amplifiers. Centre Suisse d'Electronique et de Microelectronique (CSEM). Advances in computer technology will also increase the applicability of circuit simulation. can be used to design welldefined circuit blocks. At the transistor level of representation. the author concludes that "for the foreseeable future nothing will supplant SPICE as the industry standard for analog simulation. in this decade more emphasis will be put on the design aspect. and Carley 1989). 1. 1987). SPICE will form the analytic core of analog optimization and synthesis software tools. respectively. from a collection of analog cells available in the knowledge base. IDAC (Degrauwe et al. Over the next few years the power of engineering workstations will increase to 1000 MIPS." SPICE will probably add a number of analysis modes. This translates into a 50. Whereas for the last two decades circuit simulation has been used mostly for analyzing fullyspecified circuits. 1990). the synthesis tools these groups have developed. The ability to represent entire circuit blocks by an equation or a set of equations will make simulation of complete analog systems possible. Improved transistor models have been reported in technical journals during the last decade with little impact on the various SPICE releases. Such functionality creates the need for powerful modelgeneration software capable of automating the process. such as nonlinear frequencydomain analysis and higherlevel modeling capabilities. One important up . Examples include the MEXTRAM model (de Graaf and Klosterman 1986) for bipolar transistors. because it solves the fundamental equations of an electrical system.
Ebers. G." Univ. NY (October): 356360.P. Poon. 1975. Tokyo: 287290. "A Multiprocessor Implementation of Accurate Electrical Simulation. J. B. 1987 (December). "MOTISAn MOS Timing Simulator. "Modified Nodal Analysis with Improved Numerical Methods for Switched Capacitive Networks. Degrauwe.." High Peiformance Systems 11 (March). "The Generalized Adjoint Network and Network Sensitivities. "SteadyState Analysis of Nonlinear Circuits with Periodic Inputs.. and W." IEEE Journal of SolidState Circuits SC9 (December): 353363. Rohrer. Gummel. "Implementation of Algorithms for the Periodic SteadyState Analysis of Nonlinear Circuits. "Compact Bipolar Transistor Model for CACD. R.. J. of California. E. "Macromodeling of Integrated Circuit Operational Amplifiers. S. Gummel. 1984. E. D.. "Program Reference for SPICE2. ERL Memo No. 1974. Saber: A Design Tool for Analog Systems. B. DeMan. Aprille. O. and R A. "Numerical Integration of Stiff Ordinary Differential Equations. H. L.. Rye Brook." Univ. Boyle. Klosterman. of Computer Science. C. P. and H." Report 221. 1969. REFERENCES "Analog Workbench II Adds Framework Features. . N. et aI. 1980. Cohen. 1975. Solomon. 1986. Berkeley." Proceedings IRE 42 (December): 17611772.. Deutsch. of California. Urbana. 1989. et aI. and Y. Cohen. and A. and J. Ashar. de Graaff. H. and T." IEEE Journal of SolidState Circuits SC22 (December): 11061116. K. 1954. J. C. Dept. C. Kozak. T... Analogy. M. "An Integral ChargeControl Model of Bipolar Transistors.. N. Univ. K. 1980. J. Pederson." Proceedings Ext. c. 1967. M. "IDAC: An Interactive Design Tool for Analog CMOS Circuits. Tsividis. Newton. Pederson for the inspiring discussions and suggestions that helped identify the various trends and the chronology of circuit simulation over the past three decades. 1972. UCBIERL M75/520 (May).. Berkeley. Chawla. of Illinois.REFERENCES 9 grade needed in SPICE to make such a large simulation a reality is the decoupling of the analysis of circuit blocks at the level of the differential or nonlinear equations. Director. Research Memo (March). W. Gear. R. T. "Large Signal Behavior of Bipolar Transistors. Moll.. "DIANA: Mixed Mode Simulator with a Hardware Description Language for Hierarchical Design of VLSI. Inc. H. OR: Author. with Accurate Description of Collector Behavior. and J." 21st ACM/IEEE DAC Conference Proceedings. Albuquerque." Proceedings of the IEEE 60: 108116. S." IEEE Transactions on Circuit Theory CT16 (August): 318323. 1987." IEEE Transactions on Circuits and Systems CAS22 (December): 901909. Conference on SolidState Devices and Materials. J. W." IEEE ISCAS Conference Proceedings: 977980. H. 1970. ACKNOWLEDGMENT The author would like to thank D." Bell System Technical Journal 49 (May): 827852. R." IEEE ICCC '80 Conference Proceedings. Trick. Fang. and P. Beaverton.
1989. FL (June). Berkeley. Santa Clara. A. B. of California. 1973." Keynote address at the 27th ACM/IEEE Design Automation Conference. McCalla. . ERL Memo No. Sequin. E. Anaheim. M. Y. L. CA: Author. Kundert. "An EnvelopeFollowing Method for the Efficient Transient Simulation of Switching Power and Filter Circuits. 1. J.. "MOS Models and Circuit Simulation. 1991. Excluding Radiation (CANCER). MetaSoftware. J. Campbell. F. P. Santa Clara. and A. "Analog Circuit Synthesis for Performance in OASYS. 1971.. CAD5 (October): 521535.. Rutenbar. Carley. L.0.. A. of California. E. Pederson. Howard. D. "A Survey of ThirdGeneration Simulation Techniques. W. A..1984. Autonetics Div. D. "RelaxationBased Electrical Simulation. MicroSim. Newton.. C. E." IEEE Journal of SolidState Circuits SC6 (August): 182188." EDN (June): 168180. 1987. and W. ERL M382 (April). CA (November): 446449." IEEE ICCAD Conference Proceedings. and P. "Engineering the Future. and D. ERL Memo No. Kundert. O. Idleman. E.. Berkeley. CA (November): 502505. Pederson. McCalla." RCA Review 32 (March): 4263. SC6 (August): 166182. and A. S. Meyer. S. 1988.. L. and P. et aI. Ruehli. T." Proceedings of the IEEE 69 (October): 12641280. SangiovanniVincentelli. J. and L. Pederson. SangiovanniVincentelli. Orlando. L.10 INTRODUCTION SPICETHE THIRD DECADE Hachtel.. CA: Author. J. "PCBased Analog Simulation. 0. G. ERL Memo No. C. Jenkins. Sangiovanni. CA. R. Kurker.. w. Joy. "Development of an Analog Hardware Description Language. "SLICA Simulator for Linear Integrated Circuits. R. and A. of California. 1971. A. A. Version 5. S. "BlAS3: A Program for the Nonlinear DC Analysis of Bipolar Transistor Circuits. F. E. K." IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. and D. "The Modified Nodal Approach to Network Analysis. Irvine. North American Rockwell Corp.. Newton." IEEE Transactions on Circuits and Systems CAS22 (June): 504509. Brennan. and S. "The Simulation of Large Scale Integrated Circuits. Kleckner. K." IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. 1990. 1971. UCB/ERL M78/52 (July)." IEEE Transactions on Circuits and Systems CAS31 (January): 103111. Rohrer. 1971. "SPICE2: A Computer Program to Simulate Semiconductor Circuits. R. Nagel.4. Jenkins." IEEE ICCAD Conference Proceedings. 1984. W. 1990. 1990. 1975.. PSpice. Jr. D. Kerridge. S. and R." Univ. 1975. 1968 (June). 1971. Harjani. L. UCB/ERL M75/520 (May). SangiovanniVincentelli. H. W. 1978. ERL Memo No. Fan." Univ. of California. "Advanced MixedMode Simulation Techniques. Circuit Analysis User's Guide. R. Johnson." Univ. "Transient Radiation Analysis by Computer Program (TRAC)." Univ. W. O.. HSPICE User's Guide. R. Nagel.. "TIMEA Nonlinear DC and TimeDomain Circuit Simulation Program. Santa Clara. H. 1991. CA (November): 492495." Proceedings of the IEEE 1990 CICCoBoston (May): paper 5. "Simulation of Nonlinear Circuits in the Frequency Domain. UCB/ERL M84/48 (June). White.. Nagel. "Automatic Synthesis of Operational Amplifiers Based on Analytic Circuit Models.. Berkeley." IEEE Journal of SolidState Circuits." IEEE ICCAD Conference Proceedings. C. "SPICE (Simulation Program with Integrated Circuit Emphasis). Berkeley. 1981. Ho. S. "Computer Analysis of Nonlinear Circuits. et ai. CAD3 (October): 308331. A.. W. Gray. 1986. "A Historical Review of Circuit Simulation. Koh." IEEE Journal of SolidState Circuits SC6 (February): 1419. 1984." Technical Report issued by Harry Diamond Labs. G." IEEE Journal of SolidState Circuits SC6 (August): 188204. and A.Vincentelli. S. R.
" Univ. L. 1. ERL Memo No." In ICCAD '83 Digest. Vladimirescu. "An ActivityDirected Circuit Simulation Algorithm. "A ChargeOriented Model for MOS Transistor Capacitances.. UCBIERL M89/46 (April). . W." ProceedingsIEEE International Sympo~ium on Circuits and Systems." Univ. K.. Sakallah. G. J. "Iterated Timing Analysis and SPLICE1. W. O. and A. A. 1983. R. ERL Memo No. T. 1983. N.~ . T. Pederson. H. Newport Beach." IEEE Journal of SolidState Circuits SC3: 285289.1973.. Director. UCBIERL M80/7 (February). 1980. S.rd. of California. L. Berkeley. 1989b. W. 1980. 1989a. SangiovanniVincentelli. W. "Computation of DC Solutions for Bipolar Transistor Networks. H. K." IEEE ICCD '86 Conference Proceedings. Mehta. NY (October). Vl~dimirescu. Newton.. Jimenez. YaAg. 1. 1. A. A. 11981." IEEE Journal of SolidState Circuits SC13 (October): 703707. of California. T. 1980. Trick. "SPICE Version 2G User's Guide." Univ. Santa Clara. Shichman.. L. Dutton. 1968. "Algorithms for ASTAPA Network Analysis Program. N. P. NY (October) . A. D. CA. C. "Parallelizing Circuit SimulationA Combined Algorithmic and Specialized Hardware Approach. Hodges. Quassemzadeh." IEEE Transactions on Circuit Theory CT16 (November): 460466. A. White.REFERENCES 11 Quarles. Mahoney. 1969. of California." IEEE ICCC '80 Conference Proceedings. Zhang. K. Berkeley. Weiss. Quarles. Rye Brook. R. and A. Liu. Rye Brook. Danuwidjaja. "A Vector Hardware Accelerator with Circuit Simulation Emphasis. Vladimirescu. 1982. and T.. and A. J. K. of California. ERL 'Memo No. 1987. D. and S." IEEE Transactions on Circuit Theory CT20: 628634. Berkeley. Saleh. NY (October): 10321035. and R. Hajj.D. of Electrical Engineering and Computer :Science. Kleckner. 1978. "Analysis of Performance and Convergence Issues for Circuit SimulIation. CA (May). "SLATE: A Circuit Simulation Program with Latency Exploitation and Node Tearing. ERL Memo No. Niraj. White. SangiovanniVincentelli. and D. Miami (June). of California. "RELAX2: A New Waveform Relaxation ~pproach for the Analysis of LSI MOS Circuits.. UCBIERL M82/75 (October)." Univ.. Newton. W~eks. E. Ng. A. R. R. . Vladimirescu. Univ. and S. Rye Brook. Shichman. Scott. E. Berkeley (August)." IEEE ICCC '80 Conference Proceedings.. A. Lass.. I. D. "LSI Circuit Simulation on Vector Computers.." 24th ACM/IEEE DAC Conference Proceedings. A. 1986. Berkeley. and T.. "Modeling and Simulation of InsulatedGate FieldEffect Transistor Switching Circuits. Wa. L. UCBIERL M89/42 (April). H. "The Simulation of MOS Integrated Circuits Using SPICE2." Dept. "SPICE3 Version 3Cl User's Guide.
described by linear branch voltagecurrent dependencies. Another level of complexity is added when one has to predict the behavior in time or frequency of ~n electrical circuit. Engineers learn in electronics courses to make certain approximations in order to predict the DC operation of small circuits by hand. The nonlinear equations become integrodifferential 12 . KCL. requiring the solution of the nonlinear branch equations simultaneously with the equations based on Kirchhoff's laws. For larger linear circuits the DC solution and especially the frequencydomain or timedomain solutions are very complex.One INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION 1. which requires one to solve a set of equations deriv.ed/from Kirchhoff's voltage law. Only small circuits can be solved by hand calculations. The easiest problem is that of finding the DC operating point of a linear circuit. For a small circuit with linear elements. and current law. the exact DC solution is readily available through hand calculations. BCE. which yield only approximate results.1 PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS Knowledge of the behavior of electrical circuits requires the simultaneous solution of a number of equations. KVL. and the'branch constitutive equations. The analysis of circuits that contain elements described by a nonlinear relation between current and voltage adds another level of complexity.
The efforts of two decades ago have crystallized in the two circuit simulators now most often used. Lunde. The firstgeneration programs. defined both the need and the tool for automating the design process of electronic circuits. This could be produced on a digital computer by means of an electricalanalysis or simulation program. photomicrographic plates used at each step during fabrication to obtain the desired circuit equivalent in silicon are produced from the layout. Hogsett. KVL. with mean time between failures (MTBF) drastically improved over the previous generation. finally. after which the electrical design is carried out and a circuit layout generated. and BCE equations are called circuit simulators. Since the electrical design engineer did not have the luxury of a trialanderror approach in silicon to verify the correctness of the design. a process needs to be defined. The fabrication of ICs on silicon wafers was and still is an expensive process both in cost and time. were introduced offering capabilities similar to those of presentday computers. a virtual breadboard was needed. but so did circuit elements in ICs differ from their discrete equivalents. a transistor became the standard load device in an IC as opposed to a resistor on a breadboard. a hybrid technology using silicon semiconductor diodes and transistors and a precursor of monolithic ICs. and their scope was fairly limited. initially named CANCER (Nagel and Rohrer 1971). ICs and powerful computers. such as SPICEl. which can be solved by hand only under such approximations as smallsignal approximation or other limiting restrictions. and ECAP II (Branin. such as ECAP I in 1965 (IBM 1965) could only solve piecewise linear networks. Generalpurpose computers. Not only did transistors integrated on the same silicon chip behave differently from discrete transistors on a breadboard. The fabrication of an IC requires several stages: first. A number of researchers started studying the best techniques and algorithms for automating the prediction of the behavior of electric circuits (Pederson 1984). But the breadboarding approach became inadequate with the breakthrough of integratedcircuit fabrication and associated novel circuit techniques in the years 19641965. A . A number of socalled third generation circuit simulation programs available today have their roots in the above secondgeneration nonlinear programs. 1973). SPICE2 (Nagel 1971) and ASTAP (Weeks et al. Another important factor contributing to the development of computer programs for the analysis of electrical circuits was the advance in digital computers that occurred in the same years. The CDC 6400/6600 scientific computer was also introduced at that time. Advances in numerical techniques led in the late 1960s to the development of nonlinear analysis programs. the wafers are tested for correct operation. For many years designers working with discrete components have used breadboards to analyze and test the behavior of electronic circuits. for example. currently called ASX. based on solidlogic technology (SLT). and Kugel 1971). and. These two technological factors.PURPOSE OF COMPUTER SIMULATION OF ELECTRICAL CIRCUITS 13 equations. Programs intended for the electrical analysis of networks without taking any shortcuts in the solution of the KCL. To this day there are designers who use this approach for building analog circuits. with architectural innovations that preceded the principles of today's supercomputers. such as the IBM 360 series. This costly fabrication flow required a correct electrical design the first time through.
from switching power supplies to RAM cells and sense amplifiers. mutual inductors.1 Calculate the node voltages in the resistive bridge. associated with the above three basic simulation modes. or 80. capacitors. KCL. this type of analysis requires the smallsignal assumption. Paul 1989) in the same manner as one writes the KVL. such as transistor circuits. and linear AC analysis. Circuits can contain resistors. The DC analysis part of the program computes the bias point of the circuit with capacitors disconnected and inductors shortcircuited.2 WHAT IS SPICE? SPICE is a generalpurpose circuitsimulation program for nonlinear DC. . the amplitude of the excitation sources are assumed to be small compared to the thermal voltage (Vth = kT / q = 25. inductors. metaloxidesemiconductor field effect transistors (MOSFETs). In the first example the DC solution of a linear resistive network is calculated by hand by an approach similar to the SPICE solution. nonlinearities are due mainly to the nonlinear currentvoltage (IV) characteristics of semiconductor devices. The transient analysis mode computes the voltage waveforms at each node of the circuit as a function of time.T circuit shown in Figure 1.6°F). SPICE uses iterations to solve the nonlinear network equations. dependent voltage and current sources. and BCE equations for a circuit and solves them. and metalsemiconductor FETs (MESFETs). are available in SPICE. The best way to understand how SPICE works is to solve a circuit by hand. nonlinear transient. 4 through 6. independent voltage and current sources. bipolar junction transistors (BITs). can be simulated with equal accuracy by SPICE. Thus the nonlinear characteristics of semiconductor devices are taken into account.1 and find the current flowing through the bias voltage source. They are described in Chaps. SPICE sets up and solves the circuit equations using the nodal equations (Dort 1989. VBlAS' Use the source and resistor values given in the figure. and the most common semiconductor devices. EXAMPLE 1. This is a largesignal analysis: no restriction is put on the amplitude of the input signal. junction field effect transistors (JFETs). TheAC analysis mode computes the complex values of the node voltages of a linear circuit as a function of the frequency of a sinusoidal signal applied at the input.14 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION detailed overview of the evolution of circuit simulation in general and SPICE in particular is presented in the Introduction. The program is equally suited to solve linear as well as nonlinear electrical circuits. Circuits for various applications.8 mV at 27°C. it solves the network equations for the node voltages. More types of analysis. diodes. transmission lines. Only under this assumption can the nonlinear circuit be replaced by its linearized equivalent around the DC bias point. Nilsson 1990. For nonlinear circuits. As outlined above. 1. that is.
•. ~. to IR2: '.T circuit..2V2 + OAV3 = 204 OAV2 .2 the results derived by hand in this example are compared with those obtained from SPICE..G3._.0.G3 V2 + (G3 + G4)V3 whereG].andG4aretheconductancesofresistorsR] throughR4: G] = G2 = 0.oj •••.1 and 1.••_. 1.~ ..G] V] .2 mho.3.WHAT IS SPICE? 15 5n R4 CD + VB/AS 10n R1 0 10n R2 5n R3 12V Figure 1. ..2 0. . This is a system oftwo equations and two unknowns that can easily be solved for V2 and V3: = 1.G3 V3 = = 0 0 (Ll) (1. In Section 1.. or 12 V....' node 2 : node 3: . a nonlinear circuit.2 are formulated from a graph of the circuit topology and are solved using Gaussian elimination (see Chap.. The hand derivation offers some insight on how SPICE automates the solution of the bias point for a nonlinear circuit. the voltages at nodes 2 and 3 are found by writing the corresponding nodal equations: .1 Bridge. ' In SPICE. The current through the bias source is equal .••. Eqs.. is described in the following example.G2. ..2V3 The solution is V2 = 8 V and V3 = 10 V. The analysis of a onetransistor amplifier. 9). Solution The voltage at node 1 is equal to VB1AS.2) .1 mho and G3 = G4 = 0.G4 V] + (G] + G2 + G3)V2 .
6) + 5V =vee Figure 1. 1. VBE is valid only as > 0.4) which is derived from the BCEs of the transistor.3) The most commonly used relation for the bipolar transistor equates the collector current Ie to the base current IB: (1.16 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION EXAMPLE 1.5 V and VBe <0V (1.2.2 Find the operating point of the onetransistor circuit of Figure 1. VBE and VBe.4: the BCE that defines the currentvoltage relation between Ie and VBE: (1. that is. The two sets of equations needed for this solution are KVL and the BCEs of the bipolar transistor. the bipolar transistor has a current gain f3F = 100 and a saturation currentIs = 1016 A. The KVL equation is RBIB + VBE = Vee (1.3 and 1. Ie and IB. and the junction voltages. Solution The bias point of the transistor is defined by the collector and base currents.2 Onetransistor circuit.5) One more equation is needed in addition to Eqs. . This approximation long as the transistor operates in the forward active region.
31. IB.4: Ie = 100IB = 2. the circuit schematic must be cast in a format that can be understood by SPICE. The complete BCEs of a BIT (see Chap. 1. however. the SPICE input language.3) V = 2. 1. Then Ie follows from Eq. VBe is calculated from the KVL equation for the BC jl.7 V and replace it in Eq. On a computer. . 1.6 based on the value of Ie and then refined.4 is no longer valid. repeating.0. 1. is presented in Chap.3 to yield the following value for IB: 5 . is trivial. 1. start with the assumption that VBE = 0. or converge.15 .6. or iterating. Ie.15 rnA The assumption for VBE should be verified in Eq. Obviously. namely.4. 1. It is obvious that writing and solving by hand the KVL and BCE equations for a circuit with a few transistors is tedious. Eq. The basic information on BIT equations and parameters.3 USER INTERACTION WITH SPICE AND THE COMPUTER This section describes the steps a user must follow for performing a SPICE analysis. In the next section the SPICE input file for this circuit is listed and is followed by the computer simulation and verification of the hand results.RBIB = (2. For a description of this step.USER INTERACTION WITH SPICE AND THE COMPUTER 17 At this point two linear equations and one nonlinear equation must be solved to find the values defining the operating point of the transistor. VBe = Rele .5. 1.15 V and indeed it satisfies Eq.7 V 200 kO IB = = 0. no one would ever go to that much trouble for hand calculations. 3) are coded in SPICE. 3. guaranteeing correct analysis regardless of t?e operation region. however. One more detail must be checked before the above solution can be accepted: VBe must satisfy the condition in Eq. and the complete set of equations and parameters of the SPICE BIT model are listed in Appendix A. 1. First.lnction mesh. If. To solve Eqs. the type of information . the transistor is saturated and the two BCEs must be modified. the above solution until all data agree. or model. and VBE.0215 rnA . The above example has described in a nutshell the iterative procedure used in SPICE to solve a nonlinear circuit. Re = 2 kil.5 for forward linear operation.
The two circuits from the previous section are used to acquaint the user with SPICE. . and the user is advised to consult the users' guide of the specific version for the extra features.T circuit in Figure 1. AccuSim from Mentor. 1. but SPICE accepts multiline statements. As long as one uses the functionality described in this text. the input file is customarily named with the name of the circuit followed by a suffix. Pederson. Highend SPICE products support a schematiclevel specification. Most statements are a single line long. The SPICE input language is free format and consists of a succession of statements. and Design Center with PSpice from MicroSim. Zhang. save the output in a file. spi for SPICE. A statement contains a number of fields separated by delimiter characters. Second. batch or interactive. Newton. that is. cir for a circuit. several commands must be issued to the host computer to run the simulator. Sangiovanni.T circuit of Figure 1. In order to identify files easily. with the exception of the SPJQ2 (Quarles 1989) or PSpice (MicroSim 1991) extensions. a comma.Vincentelli 1981). a user must create an ASCII file containing two kinds of information: the circuit description and the analysis requests. the input files should be readable by a variety of SPICE versions. . This file is referred to as the SPICE input file. the SPICE2 syntax (Vladimirescu.3 Write the SPICE input for the bridge. which can be . Examples include the Analog Workbench and Analog Artist from Cadence. EXAMPLE 1. in for input.2.18 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION contained in the SPICE input file is examined in more detail by formulating the SPICE description for the bridge. Newer and proprietary versions of SPICE have additional functionality. and inspect the results graphically or in ASCII format. which are a blank. Although the SPICE input file can have any name.3.T circuit in Figure 1. ckt or . a continuation line must start with a + in the first column.1 Electric Circuit SpecificationThe SPICE Input Before running SPICE on any computer. SpiceNet from Intusoft. extra blanks are ignored. and so on. the above naming convention is recommended: circuit~ame. .suffix The user can create the file with the editor of choice.1 and the onetransistor amplifier of Figure 1.1 and the onetransistor amplifier in Figure 1. The elements of the SPICE language can be introduced naturally by creating the SPICE decks for the bridge. an equal sign (=). or a left or right parenthesis.2. A most important common feature of the various SPICE versions is that all accept the basic SPICE input language.2.1 and the onetransistor circuit in Figure 1. or SPICE deck.
we transcribe the information from Figure 1. The first character for a BJT is Q. element name. can be specified with the same format used in the above deck. with the name first followed by nodes and values. The circuit description consists of the element statements on lines 3 through 7. ckt. This input description is also known as a SPICE deck from the time that punched cards were used. These two lines must always be the first and the last. The SPICE specification is componentoriented. A new element not present in the BRIDGET CIRCUIT deck is the BJT. a bipolar transistor. and the.2. 1. three nodes must be specified. which requests the DC operating point analysis. an . Some details on how to run a SPICE simulation are presented in the next section. and a voltage source. The resistors Re and RB and the voltage source. in order to describe the circuit in Figure 1. which is always the same. which is used as input to SPICE.1 and 1. base. as shown below. END line. Another type of statement needed in a SPICE input file is the control statement. respectively. these are comment statements and are used to document the circuit description and analysis requests. that is. for the collector. Next consider the onetransistor circuit of Figure 1.1. respectively. and each element can be easily identified from Figure 1. two comment lines. a .2 are set up internally in SPICE and solved as a linear system. such as a resistor. and value.2 into the format required by SPICE: one element per line. to a text file.1 one needs to transfer the information in the figure. The circuit contains resistors. • END.USER INTERACTION WITH SPICE AND THE COMPUTER 19 Solution Any SPICE input file must start with a title statement. The circuit description is read by SPICE and compiled into an internal representation. Nodal equations identical to Eqs. Vee. A number of lines start with an asterisk in the first column. Instead of a single value. BRIDGET CIRCUIT VEIAS 1 0 12 R1 1 2 10 R2 2 0 10 R3235 R4 1 3 5 * * . connectivity. which identifies the circuit. Other lines in the SPICE input file are the title. Control statements contain a period in the first column and define the types of analysis to be performed and the output variables to be stored.oP line is required. and must conclude with an end statement. In order to verify the hand calculation of the bias point of the circuit. so the name is Ql. Therefore. which must always conclude a circuit and analysis description.OP • END The above circuit description is saved in the file bridget. identifying the circuit as BRIDGET CIRCUIT. and emitter. Following the approach used above. starting with an asterisk in the first column.
The values of resistors Rc and RB in the above example. 103. such as or QMOD. ONETRANSISTOR Q1 RC RB VCC CIRCUIT (FIG. and the values of the parameters that Ql. 10. or either an integer or a floatingpoint number followed by one of the following scale/actors recognized by SPICE: T= lEl2. The model parameters for transistor QI. G= lE9. 20MHZ is not 20 megahertz but 20 millihertz.65E5. but some versions of SPICE for specific computers may require that the input file be uppercase. the circuit nodes to which the element is connected. SPICE distinguishes between name fields and number fields. 10. Ql through VCC in the above example. a letter that immediately follows a scale factor or that immediately follows a number and is not a scale factor is ignored. Another common mistake is to confuse M. and MIL. such as 5 or 123. In a number field.1 millimeter but 2. MSEC. the forward gain {3F.END ". or 1 OUM. 10VOLTS. K= lE3. such as 3. These are all valid specifications as long as the physical unit is not confused with the scale factor. After all the statements described so far are typed in an editor of choice. We save the circuit in a file called bj t .54 microns. MMHOS represent the same scale factor. IMIL is not 0.M= lE3. 1. SPICE3. P = lE12. 10V. The circuit description consists of a number of element statements. ckt. MIL= 25. a floatingpoint number in engineering notation. A number field can contain an integer.MODEL * .N= lE9.20 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION BJT is characterized by a number of parameters defined by a • MODEL statement. MEG = lE6. A name field. for example. U= lE6. 4E6. the SPICE . IF in SPICE is 1015 and not 1 farad. . as in 10V. andF = lE15. are expressed in kiloohms using the scale factor K. Each element statement contains the element name. SPICE2. The transistor is of type NPNand the SPICE parameter names for {3F and Is are BF and IS. RB. respectively. and 0 . MEG. MA. such as 1E16 or 2. and the saturation current. and 10HZ represent the same number. and M.2) * 2 1 0 QMOD 2 3 1K 3 1 200K 3 0 5 QMOD NPN IS=lE16 BF=100 * .OP . Hence. respectively.14159. This name replaces the value field on a transistor line.input specification looks as listed below. Is. and PSpice are case insensitive. a floatingpoint number. 1 PF. Many users like to append the units to the number fields. assume that the name of the model that describes QI is QMOD. are specified in the global • MODEL statement for QMOD. must start with a letter (AZ) followed by additional letters or numbers. lK and 20 OK.
these elements reference the name of the model definition that contains the parameters.. Model QMOD defines only two parameters. The •MODEL statement belongs to a different category of statements. and BF. PARAM2.. the parameters of all transistors with the same geometry integrated on one silicon chip. For each MODELname referenced. must be one of the accepted keywords for the model type. Each element must be characterized by at least one valuel. the saturation current. such as R for resistor. and most commercial SPICE versions allow node names as well. The fields enclosed in angle bracket are optional or need to be present depending on type. .. as defined in Chaps. The period in the first column differentiates global and control statements from element statements. Q for BJT. Each of PARAMl. <node3 . for missing value fields. This number field is shown as optional because SPICE provides defaults such as 0 or 1. the global statements.USER INTERACTION WITH SPICE AND THE COMPUTER 21 determine the electrical characteristics statement is of the element. SPICE2 restricts the name to eight characters. and V for voltage source. MODELname uniquely identifies one set of parameters common to one or more elements. The model statement allows one to specify only once a set of parameters common to a number of elements. some elements. depending on context.. called the model statement. From zero up to the maximum number of model parameters supported for a specific model type can be specified. whereas SPICE3. PSpice.. The name of the model that defines the parameters of QI in the example is QMOD. and those whose names are lowercase are number fields. Transistor QI in Example 1. the forward current gain. fields whose names are uppercase or start with an uppercase character are name fields.. . The following fields.1. Note that either a value or a model name should end an element line. >. respectively. for example. IS. the circuit specification must contain a •MODEL statement. node2. SPICE2 accepts only numbers fornodes. nodel. Alternatively. which are grouped on a separate line. 2 and 3 and Appendix A. and MODELtype is one of the seven or eleven types of models supported by SPICE2 or SPICE3.. Throughout this text.. are lowercase to identify them as number fields. the rest of the element name can contain both characters and numbers. ><MODELname><valuel . The general format of an element Aname nodel node2 <node3 . MODELname. SPICE3 and PSpice do not.. Except for the first letter. Bold characters are used in this book to identify key words and parameter names that are part of the SPICE language. > The first field always contains the name of the element. they represent the node numbers at which the element is connected. A comprehensive list of all conventions used in this text can be found in Section 2. Instead of referencing a value field. one of the two MODELtypes supported in SPICE for BJTs. are characterized by several values. such as transistors..3 is an NPN transistor. which must start with the letter that identifies the element type. for QI in the onetransistor circuit. The general format of a •MODEL statement is «» • MODEL MODELname MODELtype PARAMl=valuel PARAM2=value2 .
In summary. EXAMPLE 1.ckt > bjt. and this section does not enumerate all possibilities but is limited to the computers most often used by students and professionals. bridget. The redirection signs.out assuming that the executable program is called spice2 and that it is located in a directory that is in the search path of the user. Thus an element that references a •MODEL statement may require some values that are specific to it. the different channel widths.4 Print the result files bridget. out and bj t. every SPICE input file has the following general structure: Title statement * Comment statements Element statements Global statements Control statements . of MOSFETs are defined in element statements. L. grouped in the •MODEL statement. W. ckt or bj t . UNIX is the operating system of choice in universities. respectively.3. < and>. All control statements start with a dot in the first column. such as transistors. or printing it.1 and 1.3 can be accomplished in UNIX by typing % spice2 < bjt.3 the DC bias point is requested by the • OP line. DC Analysis The next step is to run the simulation. define the file where the input data reside and the file where the results are stored. For example. 4 through 6 describe in detail all control statements. are characterized by both device parameters. and lengths. Control statements specify the analyses to be performed by SPICE as well as define initial states. and model parameters. SPICE2 is available on a variety of computers and operating systems worldwide. out and compare the results with the hand calculations of Examples 1. it is presently available on a variety of computers ranging from the Personal Computer to the Cray. defined on the element line. such as threshold voltage and thinoxide thickness.2 SPICE Simulation. Upon completion of the simulation. complex elements. ckt created in Example 1. .22 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION MOSFETs of different geometric sizes can be characterized by the same model parameters. The simulation of bridget. END (end statement) 1.2. Chaps. out can be inspected by having it typed on the screen. Therefore. out and bj t. In Example 1. The last category of statements necessary in a SPICE deck is the control statement. viewing itthrough an editor.
3 SPICE2 results for DC operating point. It is important to note that SPICE2 and PSpice always echo back the circuit description received. and the solution can be verified to be identical to the.000E01 9. The contents of bj t.6 BRIDGET CIRCUIT CIRCUIT DESCRIPTION ********* **** *************************************************************************** VBIAS 1 0 12 R1 1 2 10 R2 2 0 10 R3 2 3 5 * R4 1 3 5 * .OP . . 9/21/84 ********* 06:47:36 ******* 03/19/91 ********* SPICE2G. out are shown in Figure 1. the BJT MODEL PARAMETERS defined in a . Many errors can be identified by carefully comparing the circuit description output by SPICE with the original s.000 DEG C *************************************************************************** NODE 1) VOLTAGE NAME VBIAS VOLTAGE 12.6 BRIDGET CIRCUIT 9/21/84 ********* 06:47:36 ******** **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.MODEL " .chematic.hand calculation.3.END ******* 03/19/91 ********* SPICE 2G.4. The SPICE2 output contains several sections. First. the CIRCUIT DESCRIPTION is echoed so that the user can check for potential errors.USER INTERACTION WITH SPICE AND THE COMPUTER 23 . 60E+00 WATTS TOTAL POWER DISSIPATION Figure 1. Next. Solution The output bridget.0000 NODE VOLTAGE SOURCE CURRENTS CURRENT 8.0000 NODE 2) VOLTAGE 8. out produced by SPICE2 is listed in Figure 1.0000 NODE 3) VOLTAGE 10.
VBE. in this case the source Vcc.3.MODEL QMOD NPN . Ic. The difference. and smallsignal characteristics computed by SPICE2 are listed. 1.4 File bj t . Finally. 1.6 (FIG.6 (FIG. consisting of IB. and the TOTAL POWER DISSIPATION are also listed in this section.7 V in the hand calculations.OP • END * * ******* 03/25/91 ******* CIRCUIT SPICE 2G. the voltages.4. out: DC analysis results. 1. The OPERATING POINT INFORMATION of transistor QI. According to these values. and VCE.24 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION . is due to the assumption that VBE = 0. power consumption. of the order of tens of millivolts. statement are printed. VBC. The node voltages listed as part of the SMALL SIGNAL BIAS SOLUTION agree with the ones obtained through hand calculations in Example 1.2) 9/21/84 ******* 23:07:40 ********* ONETRANSISTOR **** BJT MODEL PARAMETERS *************************************************************************** QMOD NPN IS 1. . Although SPICE2 computes a first solution with a similar assumption. defines the region of operation. The VOLTAGE SOURCE CURRENTS. 00E16 BF 100 NFl BR 1 NR 1 Figure 1. and 1.2.6 are satisfied. it continues to iterate until Eqs.2) 9/21/84 ******* 23:07:40 ************ ONETRANSISTOR **** CIRCUIT DESCRIPTION *************************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * * . QI is ******* 03/25/91 ******* CIRCUIT SPICE 2G. 1.
900 100.2) POINT INFORMATION TEMPERATURE = 27.OOE+OO O. 1.124E03 1. 29E+18 (continued) IC VBE I VBC VCE BETADC GM RPI RX RO CBE CBC CBX CJS BETAAC FT Figure 1.000 DEG C *************************************************************************** NODE 1) VOLTAGE NAME VCC VOLTAGE .OOE+OO O.2) __. 00E+12 O. 1.OOE+OO 1.000 8.7934 NODE VOLTAGE NODE 3) VOLTAGE 5.0000 NODE VOLTAGE 2) 2.8967 SOURCE CURRENTS CURRENT 2.OOE+OO 100.13E02 1.793 2.000 **** OPERATING DEG C *************************************************************************** **** NAME MODEL IB BIPOLAR JUNCTION TRANSISTORS Q1 QMOD 2. 9/2. ******* CIRCUIT SPICE 2G.10E03 0.4 .USER INTERACTION WITH SPICE AND THE COMPUTER 25 ******* 03/25/9.1/84 ******* 23:07:40 ************ ONETRANSISTOR **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.23E+03 O.10E05 2.06E02 SPICE 2G.OOE+OO O.6 WATTS 9/21/84 TOTAL POWER DISSIPATION ******* 03/25/91 ******* ******* 23:07:40 ********* ONETRANSISTOR CIRCUIT _(FIG.100 2.6 (FIG.000 1.
SPICE2 is a batch program. source. At this point the user needs a few additional commands not available in SPICE2 in order to communicate with the program. the same information found under the SMALL SIGNAL BIAS SOLUTION header in SPICE2. A value of {3F. Note that the print command does not provide the OPERATING POINT INFORMATION of SPICE2. If a circuit element must be changed or an output request has been omitted. the third. The first command. type quit to exit SPICE3. the previous steps must be repeated. namely. lists the input file for verification. which are displayed before the program exits. In this and the following chapters all supported elements and analysis modes are described. is computed that takes into account the Ie and 18 for each transistor. defines the input file. The resulting information listed on the screen is much more verbose. is interactive. print all. editing the input file. While one circuit is active. ckt. op. each command is followed by the results displayed on the screen by the program. and in release 3d2 this information can be accessed only on a devicebydevice basis by using the show ql command. 3. BETADC. but print or plot only selected ones. The rest of the data represent the values of the elements in the linear equivalent model of the transistor and are described in more detail in Chap. Figure 1. The results of the different runs have been saved in temporary files.5 is the transcript of an interactive SPICE3 session of the same simulation as performed above for bj t. and the fourth. the results of various analyses can be either viewed graphically on the screen or printed out. running the simulation. as predicted by hand calculations. and the user has a last chance to save any desired results. the second. Input files can be edited and repeated simulations can be performed from within the SPICE3 shell. runs the DC operating point.out . The above examples are intended to show a new user of computer simulation how natural the SPICE input language is and how straightforward is the output information provided by the program for a simple DC analysis. listing. that is. lists all node voltages and currents through voltage sources. and the user is transferred inside a spice shell upon invocation of the program: Spice 1 > SPICE3 commands must be entered at the prompt. As can be seen. SPICE3 can also be run in batch mode through the command % spice3 b bjt. however. and viewing the output file. SPICE3. When you have finished. SPICE3 saves all node voltages of all simulations performed during the same SPICE3 session and provides for the interactive display of selected waveforms while the simulation is running.ckt > bjt.26 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION biased in the forward active region. For larger circuits it is useful to display all available output variables. as well as the best approaches for using SPICE to solve electrical circuits.
12431e03 Spice 7 > quit Warning: the following plot hasn't been saved: op2 ONETRANSISTOR CIRCUIT (FIG.r flag is used._w_. 4 rc 2 3 lk 5 rb 1 3 200k 6 vcc 3 0 5 9 .. the models supported range from the AT to the 486.'•• . Although SPICE2 is not available from DC Berkeley for the PC." ..end Spice 3 > op Spice 4 > print all v(l) = 7. Some packages offer DOS shells.__ _ _~ __ . the display data are stored in a file called rawspice. ~~ ._ Spice 1 > source bjt. 1.ckt Circuit: ONETRANSISTOR CIRCUIT (FIG.••• ~_ •.••. This is a sarrplenew. such as PSpice from MicroSim.5 Transcriptof interactiveSPICE3 analysi'sof bj t .model qrnodnpn is=le16 bf=100 15 .iJJ . and . the command to simulate may differ from package to package.USER INTERACTION WITH SPICE ANDTHE COMPUTER 27 . __ " ro ••_ n.~"'. • The most common platform for running SPICE has becomy the IBM PC and PC clones.!il~_~stYJ..s .934384eOl v(2) = 2. raw. SPICE3 is distributed by DC Berkeley for the PC. operating point Are you sure you want to quit (yes)? yes Spice. 1.••_ •.. 1.•.b~_P.•••••. which facilitate the simulation sequence of creating or modifying the input circuit. IsSpice from Intusoft.000000e+OO vcc#branch = 2. and HSPICE from Meta Software.••. If no filename is specified.2) 1 : onetransistor circuit (fig. At completion bj t .2) 3 ql'2 1 0 qrnod'" . _ . Although the sequence of operations remains the same. The companion postprocessor for the SPICE3 rawfiles is called Nutmeg. a number of commercial offerings.. run under DOS or Windows.. ckt. . .896719e+OO v(3) = 5. 1. out contains information similar to but in a different format from what is produced by SPICE2. SPICE3 also produces a raw/tie containing data to be displayed graphically when the .•_ .2) Spice 2 > listing ONETRANSISTOR CIRCUIT (FIG.3d2 done Figure 1.r::!pt~~ whenever spice or nutmeg is started. .2) . running SPICE.
SPICE2 and SPICE3 run in batch mode on a variety of mainframe computers. as is MacSpice.. for several computers and operating systems. the jobs submitted to such computers contain job control statements in addition to the SPICE circuit description. Although in Windowsbased packages most operations can be performed from menus. what types of statements are available. which runs BSPICE. computer resources. SPICE3 transfers to its shell. OUT as saved by PSPICE is similar in format to that saved by SPICE2. First.28 . Berkeley. Job control statements define the user identification. and how to interpret the results of a DC analysis in the output file. has . the input and output file names follow the program name as command arguments: C > PSPICE BJT. SPICE is also available on the Apple Macintosh. The name of the output file must not be specified unless a different suffix than . When the input file is ready. 1. Only one control statement. it is still useful to follow filenaming conventions similar to those introduced above for circuit identification. SPICE3 is run in batch mode. and the program to be run.. Both SPICE2 and SPICE3 are distributed by the University of California. SPICE3 and Nutmeg can be run similarly on a Pc. Although not as common as on the PC. and Cray. • OP.3. and then runs Nutmeg on the result file RAWSPICE. Note that BJT . SPICE3 .sm.~e. input and output units. (The two commands can be saved in a . BAT file. the same steps as in UNIX must be followed for simulating circuits. how to run the analysis on the most common computers. the name of batch SPICE3 on a PC. RAW created by BSPICE. INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION '*' viewing the results.3 SPICE Results for AC and TRAN Analyses So far we have learned how to write a SPICE circuit file.OUT The output file from PSpice is of the same format and contains the same information as that from SPICE2. For the VMS operating system on DEC computers. BAT. then Nutmeg is run to view the results.. type $ run spice SPICE2 will prompt for an input file and then for an output file. The Electronics Research Laboratory at UC Berkeley tells where users can get a copy of SPICE for a specific mainframe computer. CDC. from Deutsch Engineering. When one runs PSpice from DOS.CKT BJT. OUT is desired. time limit. Typically.) More on displaying results is presented in the following two sections. which is specifically tailored for the Macintosh interface.£oSim and SpiceNet frQillTutusoftallow the circuit specificati~entered grap!!'[ ically rather than through the. The schematic capture available in the Design Center from Mi. PSpice and IsSpice are offered on the Macintosh. where the same commands as in UNIX are valid. such as IBM.
or AC.• PRINT and • PLOT define only the results saved in the output file. LI = 90° Z R1 = Vin = Vin 5'. closely follow the input signal: . 1/ I + l/iwC1 III = 0.verify the results derived from hand calculation. Solution First.AC control line. invoked by the . so will the size of the output files. Thus the • PRINT and • PLOT control statements define the node voltages of interest or.31 rnA. EXAMPLE 1.2.j16 '= jO. various versions of SPICE have additional control lines or interactive commands that let the user access results that have been saved in binary files and display them in graphical mode with the help. the solution for the network is obtained using phasor calculations. vary the frequency of the input signal Vi~ from 1 Hz to 10 kHz and obtain the Bode plot of the magnitud~ and the phase of the voltage across the capacitor C1. w C 1.1 and 1. Vin = 5 cos 27T1Ot Write the SPICE deck and run the program to . 7) The voltages at nodes 2 and 3. Then. making the results of interest more difficult to find.103 0. The interpretation of the results of SPICE simulations is best understood if exernc plified for typical applications. the resistanceR1 and the inductorreactancewL1 can be neglected compared to the reactance of the capacitor.ANDTHE COMPUTER 29 been introduced so far.5 Compute the node voltages and the current for the series RLC circuit shown in Figure 1. Of postprocessing programs. more generally. These analyses result in large amounts of data.2. and a timedomain analysis. bridget. Forsmall circuits such as the ones in Examples 1. SPICE also performs a steadystate sinusoidal analysis. V2 and V3.USER INTERACTION WITH sPICE. 10 3 (1. the desired output variables . this was sufficient for obtaining all computed node voltages in the output files.31 . V3. out and bj t . analysis and how to display the results as a Bode plot. TRAN line. this may not bea problem.out. In addition to a DC analysis.6 assuming the following periodic input signal: . due to the fact that each node voltage is computed for all frequencies or times.) l . In calculating the current. The following example introduces the SPICE frequency. The crihent is ". But as the circuits grow. invoked by the.
AC voltages and currents are phasor quantities and can be expressed in terms of either real and imaginary parts. The first statement represents a request for a steadystate frequencydomain analysis and defines the type of frequency variation.072E+01 5.125 Cl 3 0 10 R1 1 2 200 . 5 and 4. The following results are computed by SPICE for the desired phasors at 10Hz: FREQ 1M (VIN) IP(VIN) VM(2) VP(2) VM(3) VP(3) 1.002E+00 7. For AC variables the character V (for voltage) or I (for current) must be followed by one or more additional characters specifying whether polar or rectangular values are desired. and circuit variables to be saved in the output file. therefore.203E01 5. The SPICE deck for this circuit.000E+00 7.AC LIN 1 10 10 . SERIES RLC CIRCUIT VIN 1 0 AC 5 0 L1 2 3 0. These two statements are described in detail in Chaps.000E+01 3. • OP. PRINT keyword must be followed by the type of analysis. 1. is necessary if the user wants the results of the analysis to be written into the output file. a current requested on a • PRINT line must always have as argument a voltage source name. and the starting and ending frequencies. ckt. The second statement. The . only the currents flowing through voltage sources can be measured.6 Series RLC circuit.PRINT AC 1M (VIN) IP(VIN) VM(2) VP(2) VM(3) VP(3) • END * Two new control statements are used. • PRINT. for the other analyses the user must specify which data are to be saved in the output file. where SPICE automatically prints the results in the output file. In most SPICE versions. as in VR (2 ) and VI (2 ) . rIc. is based on the previous examples. including SPICE2 and SPICE3. •AC and • PRINT.203E01 . Unlike the case of the DC operating point analysis. respectively. 10Hz. the number of frequencies. which in this case are the same. LIN. as in VM( 2) and VP ( 2 ) .143E04 9. AC in this case. or a magnitude and a phase.125mH Figure 1.30 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION o .
ACstatement.7. 0 ******* 09/08/92 SERIES RLC CIRCUIT AC ANALYSIS ******** SPICE 2G. We also change the amplitude of Vin to 1 V in order to obtain the transfer function V3/ Vin' For the frequency variation a logarithmic scale is desirable. the decade. and we will use it for obtaining the Bode plot. The resulting Bode plot. For the desired Bode plot the requesting statement is . The new •AC line and the above • PLOT line should replace the existing •AC and • PRINT lines in the SPICE input file rlc. The only two statements that need to be changed are the. is negative because the direction of flow is assumed in SPICE to be from the positive to the negative terminal through the voltage source.AC DEC 10 1 10K This statement requests an AC solution of the RLC circuit at 10 frequencies per decade in the interval from 1 Hz to 10kHz. plot.USER INTERACTION WITH SPICE AND THE COMPUTER 31 If the amplitude of the input signal were 1 V. is taken from the SPICE output file. PRINT capability. or lineprinter. The next part of this example is to obtain the Bode plot of the magnitude and phase of the voltage across the capacitor for the frequency range from 1 Hz to 10 kHz. because it provides an even number of analysis points in all ranges. and the phase changes by 180 because of the two complex poles (see also Chap. The new .PLOT AC VDB(3) VP(3) Note that the magnitude ofthe voltage is requested in decibels as specified by the suffix DB. . au t. OCT.AC line is . SPICE offers two choices of logarithmic intervals. the voltage at each node computed by SPICE would represent the transfer function at that node referred to the input. SPICE supports a • PLOT command. 6). I P (VIN) .The most commonly used frequency interval is the decade. The phase of the current. The information entered on the • PLOT line is identical to that entered on a • PRINT line. which produces an ASCII character. and the octave. the resonant frequency of the circuit.ckt.000 DEG C *********************************************************************** LEGEND: *: VDB(3) +: VP(3) Figure 1. In addition to the. shown in Figure 1.7 SPICE2 ASCII plot of VDB (3) and VP (3) .6 3/15/83 ******** 19:45:56 ******** **** TEMPERATURE = 27. DEC. rIc. and the output request line. The amplitude peaks at 450 Hz. to reflect the desired frequency range.
.
ckt > rlc. Bode plot ofVDB (3) and VP (3) from . on the command line: spice2 r rlc_sp2.ro o 20 eO e1 e2 e3 e4 Figure 1. SPICE 2G6 and SPICE3. PLOT commands of SPICE2 and most other commercial SPICE programs.8.raw < rlc. which can then be directly loaded and viewed in Nutmeg. 20  VDB(3) VP(3) . which translates the file to the SPICE3/Nutmeg raw file format: sconvert 0 rlccsp2.. .r f i 1ename.USER INTERACTION WITH SPICEAND THE COMPUTER 33 There are ways to obtain SPICE plots with highquality graphics on a computer screen or printer.raw rlc.out Before a rawfile created by SPICE2 can be opened in Nutmeg. The rawfile created by SPICE3 can be assigned any name with the r filename option on the command line.3. SPICE2 plots can be viewed or printed in Nutmeg on a UNIX system by setting the rawfile option. raw.raw a rlc_sp3.raw The Bode plot of the capacitor voltage magnitude and phase produced by Nutmeg from a SPICE2 rawfile is shown in Figure 1. as in the following: spice3 b r rlc. the graphic postprocessor is Nutmeg.out Note that SPICE3 does not support the • PRINT and.2. For the UC Berkeley releases.8 Nutmeg. I( SPICE3 is used for simulation.ckt > rlc. If SPICE3 is run in batch mode. the plot of any desired circuit variable can be obtained while running the program interactively from the spice3 shell. as shown in Section 1. it creates by default a binary result file called rawfile. the sconvert utility must be run.
In order to generate the graphics file PROBE. a few headers are added. The complete SPICE deck for the transient analysis is listed below. best takes advantage of PC graphics.125 C1 3 0 lU R1 1 2 50 . First. Solution Two new items must be introduced in the SPICE deck of the RLC circuit in order to perform a transient analysis.2M 50M .01M L1 2 3 0. analysis. • PROBE. CGA. IntuScope. and the results can then be viewed or printed in the xgraph tool. The rest of this section is dedicated to introducing the third major analysis mode of SPICE. the postprocessor for IsSpice. or transient. VGA. which identifies a piecewise linear . EGA. the user can view the results of the simulation in graphic mode. including SVGA. The following example describes how to obtain the SPICE timedomain solution for the above RLC circuit. Find the waveform of V3(t) between 0 and 50 ms. the control line • THAN must be included. which defines the time interval for the analysis. The data produced by the • PRINT command are extracted from the SPICE output file. Besides using the regular output file. MicroSim offers Probe. On Macintosh computers tabular output created by the • PRINT command on a Macintosh or another computer can be viewed and printed using plotting programs such as Cricket Graph or Kaleidograph. SERIES RLC CIRCUIT 0 VIN 1 0 PWL 0 0 10N 5 25M 5 25.. timedomain.PRINT TRAN V(3) V(l) • END * The first difference from the input file used in the AC analysis is found on the VIN line: the two nodes are followed by the keyword PWL.34 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION Another graphics package available on UNIX machines that run XWindows is xgraph. consult the manual page of xgraph for the details. Use R] = 500.6 Use SPICE to compute the timedomain response of the series RLC circuit of Figure 1.TRAN . which can display and perform arithmetic operations on waveforms. The tabular output created by the SPICE2 • PRINT command can be used as input to xgraph. a pulse with the defined characteristics must be assigned to the voltage source VIN. a control statement. Commercial PC SPICE packages offer postprocessing for all popular PC graphics. must be added to the PSpice input file.6 to a pulse with an amplitude of 5 V applied at the input at time 0 for 25 ms. and Hercules. DAT. Second. EXAMPLE 1.
ms Figure 1.10.0000 20.00 <Ii ~ E a. Two waveforms are requested.0000 30. If PSpice is used for this analysis and the line • PROBE is included in the deck. Other waveform functions can be generated by a source. which is the interval at which values are printed or plotted by a • PRINT or . the value on the.7 and 1. The tabular output saved in r 1 C • au t is used in this case as input for xgraph. complete information on independent sources is in Section 2.USER INTERACTION WITH SPICEAND THE COMPUTER 35 function generated by the input source. and V ( 3 ) . SPICE uses an internally adjusted.2. The values following the keyword represent pairs of timevoltage values. This behavior corresponds to the peaked frequency characteristic displayed by the circuit. the input. Note that both the AC and transient analyses can be made part of a single SPICE run by the addition of the PWL specification to the AC characteristics on the VIN line and the inclusion of the •AC and • TRAN lines together with the relevant output request lines in the same input file. the final time. 6 and 9). « 0.0000 50. 6. which produces the plot of Figure 1.00 V(1) V(3) > "0 4. . TRAN. and the starting time.00 2. A • PRINT statement followed by an analysis type. the voltage across the capacitor.00 2.0000 Time. which enables the results to be viewed on the screen or a hardcopy to be produced as shown in Figure 1.8.00 0.9 xgraph plot of transient waveform V ( 3 ) .9. see Figures 1. All the details on specifying a timedomain analysis can be found in Chap. variable time step for solving the circuit equations (see also Chaps. TRAN line is used only for result output purposes. upon completion of the SPICE run the user is transferred into the Probe program. The voltage across capacitor C1 displays an overshoot.00 4.0000 10. PLOT command. V ( 1 ) . Rle 8. is also present in the deck. which takes almost the entire pulse width to settle.0000 40.00 6. The • TRAN control line contains three values: the time step.6.
0 > "C 5 ai E :E c.. such as transistors. the plots in the rest of the book are produced using the Oscilloscope and Network Analyzer tools of the Analog Workbench because of their superior graphic quality. engineering workstations.4 SUMMARY This chapter introduced the basic capabilities of the electrical simulation program SPICE. the list of graphics packages available on computers.10 Probe plot of transient waveform V ( 3 ) . > . The solution process of SPICE was linked to the knowledge of electric circuits necessary for using the simulation. For uniformity. and save the results in a output file or create a plot. 1. All the elements used so far can be specified in SPICE according to the following format: Aname nodel node2 <node3> . « 0 5 o 10 20 Time. Alternatives for obtaining graphs of the results have been presented. The main analysis modes of SPICE as well as how to display the results of the analyses have been covered in this section.36 1 INTRODUCTION TO ELECTRICAL COMPUTER SIMULATION RLC Daterrime 10 run: 09/16/92 16:43:41 Temperature: 27. is the global statement • MODEL.. <MODELname> <value> Associated with complex elements. which defines the parameters for a number of elements: • MODEL MODELname MODELtype <PARAM1=valuel PARAM2=value2 .. ms 30 40 50 o v(3) Figure 1. run the basic analyses. You should be able to write a SPICE input deck for a simple linear circuit. and personal computers is intended not to be complete but only to exemplify an approach for obtaining highquality plots from SPICE • PRINT data..
• PLOT ANALYSIS OULvarI OUT_var2 . SPICE3 version 3Cl user's guide. SPICE version 2G user's guide. A. Irvine.. J. Introduction to Electric Circuits. 1973. R. IEEE Transactions on Circuits and Systems CAS31 (January): 103111. UCBIERL Memo M89/46 (April). IEEE Journal of SolidState Circuits SC6 (August): 166182. of California. 1971. K. Pederson. Kugel. R. Algorithms for ASTAPA network analysis program. PSpice: Circuit Analysis Users Guide Version 5. New York: McGrawHill. SangiovanniVincentelli. Rohrer. J. Nagel. Lunde. The plots in the following chapters of this book are all created using the display tools of the Analog Workbench. H. Analysis of Linear Circuits.0. D. A. Electric Circuits. 1989. D. W. New York: John Wiley & Sons. excluding radiation (CANCER). . R. Dept. Reading. of Electrical Engineering and Computer Science. MicroSim. or timedomain analysis. Hogsett. Berkeley. such as Nutmeg. 1965. Scott. TRAN TSTEP TSTOP <TSTART> for performing a DC. Mahoney. . ERL Memo UCBIERL M75/520 (May). The general structure of SPICE deck is shown on page 22. W. and L. Dorf. 1971. . Nilsson. ECAP IIA new electronic circuit analysis program. 1620 electronic circuit analysis program [ECAP]. E. Weeks. 1990. Univ. 1989. A historical review of circuit simulation. Berkeley. C.REFERENCES 37 The following analysis control statements are defined: . Mehta. Computer analysis of nonlinear circuits. L. [l620EE02X] User's Manual.. Jimeniz. 1984. Univ. Paul. and Probe. Newton. L. R. Quassenizadeh. . SPICE2: A computer program to simulate semiconductor circuits. REFERENCES Branin. xgraph. frequencydomain. D. A. 1975. O.. T. W. IBM Application Program File H2001701. and R. Vladimirescu. Zhang. F.. R. 3d ed. L. and T. CA: Author. L. G. 1989. MA: AddisonWesley. IBM. . and A. SPICE results are requested with the following control statements: • PRINT ANALYSIS OULvarI OUT_var2 . G. Univ. IEEE Transactions on Circuit Theory CT20 (November): 620634. IEEE Journal of SolidState Circuits SC6 (August): 146165. T. all SPICE circuit descriptions must start with a title line and end with an • END line. L. Nagel. 1991. respectively. of California. 1981 (August). O. of California.op • AC INTERVAL numpts fstart fstop . Berkeley. H. ' Quarles. Pederson. A. Examples of several plotting tools were presented. C. R.
either explicitly or by reference to a model name. and Sangiovanni. Sec: G 38 . SPICE3 (Johnson. SPICE elements areclassified in threecategories:. presented in Chap. Model statements are necessary for defining the parameters of complex elements. described in Sec.3. 3. A circuit must always contain a ground node.1~ ELEMENTS.'and semiconductor devices. SPICE2 supports models only for semiconductor devices. these model types. AND CONVENTIONS Element statements and model statements represent the core of the circuit description. and the nodes of unterminated transmission lines. have extended model support to most elements.1. which must always be number O. 2. the only exceptions are the substrate node in MOSFETs.Vincentelli 1981). Every element type accepted by SPICE2 and SPICE3 is presented in this and the following chapter. Quarles. NODES. Pederson. 1. Pederson. The circuit nodes need not be numbered sequentially. are described in Chap.Two CIRCUIT ELEMENT AND NETWORK DESCRIPTION 2. but not all implement the newer element types of SPICE3. All commercial SPICE versions support the elements available in SPICE2. Newton. as shown in Sec. and SangiovanniVincentelli 1991). however. Zhang. multiterminanlemenfs. Newton. SPICE3 and PSpice.2. which has internal connections to the drain and to the source. common to all SPICE versions. The following conventions must be observed in the SPICE2 (Vladimirescu.3. An element statement contains connectivity information and. MODELS. 3. presented in 2. and PSpice (MicroSim 1991) circuit definitions. the values of the defined element. The circuit nodes must always be positive integers in SPICE2 or positive integers and names in SPICE3.two::tertniiial elements. Every node in the circuit must have at least two elements connected to it.
tc2 • Exception: when a parameter name is followed by its value. model and analysis types. Because SPICE2 uses modified nodal analysis (Ho. In the statement format definition the characters or keywords that must be present in an actual statement are boldface. Monotype is used for: • Computer (program) input and output • References made in the text to names. Any violation of the above restrictions results in an error message and termination of the SPICE program. The IV . for which the program cannot find a bias point. in uppercase. the value may be denoted by the same characters as the name. parameter names. for example the parameter name is L and the variable is L • Highlighting new concepts 4. and the latter due to Kirchhoff's current law. The former is disallowed due to Kirchhoff's voltage law. Boldface monotype is used for: • Command names. and optional keywords or values appear between angle brackets. and characters that are keywords for the program. McCalla 1988. The possible error messages and corrective actions are described in Appendix B. KCL. but italic type 2. Italic type is used for: • Variable names (subscripted characters as well) • Names of fields in SPICE statement definitions • Reference to the value of a program parameter with the same name. such as MODELname • Variables in lowercase denote a numeric field in a statement as in TC= tel. the same type is used whether these keywords appear in a statement definition or are referred to in the text 3. 1.TWOTERMINAL ELEMENTS 39 Every node in the circuit must have a DC path to ground. KVL. The following description summarizes the conventions for different typesets. Uppercase versus lowercase in SPICE statement definitions: • Variables in uppercase or starting with uppercase in statement definitions denote a character field. 9) to solve for both node voltages and currents of voltagedefined elements. This requirement prevents the occurrence of floating nodes. titles. and Brennan 1975. In DC. Several conventions are observed in the following sections in the presentation of element statements. see Chap. The semiconductor diode is presented together with multiterminal semiconductor devices in Chap 3. and it cannot contain a cutset of current sources or capacitors. such as voltage sources and inductors. Ruehli. < >.2 TWOTERMINAL ELEMENTS This section describes both the syntax and the branchconstitutive equations (BCEs) of all twoterminal elements except the semiconductor diode. two restrictions must be observed: the circuit cannot contain a loop of voltage sources or inductors. capacitors represent open circuits and inductors represent shorts. or variables appearing in a computer input or output 2.
node}. 2.1 Resistors The general form of the resistor statement is Rname node} node2 rvalue <TC = tc1<. . Only the first 7 characters in name are used by SPICE2 to identify this resistor. These special elements have an associated.1. is positive. On any twoterminal element statement the first node. capacitors. node2. are described by simple BCEs. which can be specified by geometric and process parameters. SPICE3 supports the following model types introduced in this chapter: R C URC SW CSW Diffused resistor model Diffused capacitor model Uniformly distributed RC model Voltagecontrolled Currentcontrolled switch model switch model JCSpice also supports modeLstatem. as shown in Figure 2. SPICE3 does not restrict the length of name.ents for resistors.40 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION relations of semiconductor elements an~ expressed by complex which require many parameters. MODEL statement for the process parameters. SPICE supports the following twoterminal elements: Resistors (linear) Capacitors (linear and nonlinear) Inductors (linear and nonlinear) Independent Independent voltage sources (linear) current sources (linear) analytic equations.2. All twoterminal elements supported by SPICE2. The branch voltage across any element is computed as Ve1em = Vnodel Vnode2 and the current is assumed to flow from node node} to node node2. except the diode. Diodes (nonlinear) The type of IV branchconstitutive equation implemented in the program for each element listed above is specified in parentheses. and switches for all elements except for sources. and have no associated model statements. nonlinear magnetic cores. SPICE3 supports semiconductor resistors and capacitors. require only one or a few parameters. and the second node. inductors.tc2» R in the first column identifies a resistor labeled Rname. is negative. connected between nodes node} and node2 of the circuit.
TWOTERMINAL
ELEMENTS
41
niJde1 I __
R
rvalue' Rname. VR
node2
~
Figure 2.1
Resistor model.'
The BCE of a resistor is
(2.1)
where the proportionality constant rvalue is the resistance measured in ohms, VR the ,voltage across the resistor in volts, and IR t1).e current in amperes. The resistance may be positive or negative but cannot be zero. SPICE models the temperature variation of the resistance by a secondorder polynomial: rvalue(TEMP)
=
rvalue(TNOM)[l
+ tel(TEMP  TNOM) + te2(TEMP  TNOM)2]
(2.2)
The keyword TC must be present if one or both temperature coefficients are specified; tel and te2 are the first and secondorder temperature coefficients of the resistor specified in parts per °C or eq2, respectively. TNOM is the nominal temperature, 27°C, assumed in SPICE2, and TEMP is a different simulation temperature specified in a • TEMP statement. Note that SPICE3 and PSpice require the temperature coefficients to be specified onthe resistor. MODEL line. PSpice also supports a second temperature dependence, described by an exponential function. Examples
R1 2 45 100 Rci 12 17 1K TC=O.001,0.015 (SPICE2) RC1 12 17 RMOD 1K (SPICE3,PSpice) .MODEL RMOD R TC1=0.001 TC2=0.015
2.2:2
Semiconductor
Resistors (SPICE3)
SPICE3 supports an extension of the general resistor element that allows a convenient description of a diffused resistor from geometric and process information. The general form of a semiconductor resistor statement is Rname nodel node2 <rvalue><Mname><L'=L><W= W>
If rvalue is specified, this statement is equivalent to 'the ge~eral resisto~ statement and any information following the value is discarded. Note that SPICE3 does not support temperature coefficients on the resistor statement. A model statement with the general format described in Sec. 1.3.1 must be used in order to define the parameters listed in Table 2.1 for a model of type R.
42
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
Table 2.1
Semiconductor
Resistor Model Parameters Parameter Units lIoC lI("C2) flIsq. m m Default 0.0 0.0 0.0 106 0.0 Example 5E3 20E6 50 2E6 lE7
Name TCl TC2 RSH DEFW NARROW
Firstorder temperature coefficient Secondorder temperature coefficient Sheet resistance Default width Narrowing due to side etching
The resistance is computed from the length L and width W of the diffusion specified in the resistor statement and the values RSH and NARROW of the model statement:
rvalue
=
RSH.
LNARROW W  NARROW
(2.3)
The temperature behavior is modeled the same way as for regular resistors (see Eq. 2.2). Note that the program provides default values only for Wand DEFW, and not for L, because the width of most diffused resistors on a chip is equal to the minimum feature size; a default value for DEFW also prevents division by zero in Eq. 2.3 when W is omitted.
EXAMPLE 2.1
RDIFFl 1 2 RMODl L=50U W=5U .MODEL RMODl R RSH=lOO NARROW=.25U
The above statements define a resistor of resistance rvalue
=
100. 50  0.25 5  0.25
n=
1047
n
2.2.3
Capacitors
The general form of a capacitor statement is Cname node] node2 cvalue <IC
=
Veo
>
The C in the first column identifies a capacitor labeled Cname and connected between nodes node] and node2 of the circuit, as shown in Figure 2.2. The BeE of a capacitor is
Ie
.
=
eva ue .
I
dve ;It
(2.4)
TWOTERMINAL
ELEMENTS
43
nog_e1_<I •...__ I
IC~ Cname Vc
cvalue
n(oge2
Figure 2.2
Capacitor model.
where cvalue is'the capacitance in farads and represents the proportionality constant between the current through the capacitor, ic, and the rate of change of the voltage across the capaCitor, Ve. The integral variant of Eg. 2.4 is used in SPICE to model the capacitor:
,
.
Ve
=
1 .lcva ue
It iedt + Veo
0
(2.5)
IC is optional and is used to input Veo, the initial value (time t = 0) of the capacitor voltage. This value is used at t = 0 only when UlC (use initial conditions) is specified in the. TRAN statement (see Chap. 6).
Examples
C2 2 0 lOP CGS1 12 14 50F
CLOAD 310 20P IC=5
The above SPI and PS "linear polynomial The general
statement ice a 0 function form of a
describes a linear capacitor with constant capacitance. su ort nonlinear capacitors whose capacitance is a nonof the termina vo age Ve. nonlinear cap~citor statement is
Cname node] node2 POLY cO c1 <c2 ... ><IC
= Veo >
The keyword POLY identifies the capacitor Cname as nonlinear, and the values cO, c1,." are the coefficients of the corresponding powers ofve. The value of this capaCitor is computed at each time point as
cvalue
=
cO + c1 . Ve
+ c2
. v~
+ . ,:
(2.6)
The BCE for the nonlinear capaCitor becomes.
Ie
,
dq d. = 'dt = d/cvalue'
vc)
d = dt (' cO.
Ve
+,.c1 . Ve
2
+ c2.
Ve
3
+ ... )
(2.7)
Thus the coefficients cO,c1, c2, ... should not be mistaken for a polynomial representation of the charge q. .
44
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
EXAMPLE 2.2
CI 3 5 POLY IN 75P 200F
The value of C 1 is evaluated for every new value of Vc across the capacitor according to Eq. 2.6: cvalue
=
109
+ 75
. 1O12vC
+ 200.
1O15v~
+ ...
farad
2.2.4
Semiconductor Capacitor (SPICE3)
SPICE3 supports an extension of the general capacitor element to allow for a convenient description of the capacitance of a planar diffused region from geometric and process information. The general form of a semiconductor capacitor statement is Cname node} node2 <cvalue><Mname><L=L><W= W><IC
= Vco >
If cvalue is specified, this statement is equivalent to the general capacitor statement and any information following the value is discarded except the initial value. If Mname is specified, the capacitance is calculated from the process information in model Mname and the given length, L, and width, W. Note that if cvalue is not specified, Mname and L must be provided; W assumes the default value in the model if not specified. Also note that either cvalue or Mname, L, and W may be specified, but not both. A model type C statement must be used in order to define the parameters listed in Table 2.2. The capacitance is'computed as follows: cvalue
=
CJ(L  NARROW)(W
 NARROW) (2.8)
+ 2 . CJSW(L + W
EXAMPLE 2.3
CDIFF PDIFF, 0 PCAP L=5U W=5U .MODEL PCAP C CJ=IOOU CJSW=IN
 2 . NARROW)
Table 2.2 Name CJ CJSW DEFW NARROW
Semiconductor Capacitor Model Parameters Parameter Junction bottom capacitance Junction sidewall capacitance Default device width Narrowing due to side etching Units Fm2 Fm1 m m Default Example 5E5 2Ell 2E6 lE7
106 0.0
TWOTERMINAL
ELEMENTS
45 and node
The above statements define a diffused capacitor between node 0, with a value computed according to Eq. 2.8:
cvalue
=
PDIFF
104. 5 . 106 . 5 . 106 F + 2 . 109 . (5 + 5) . 106 F
=
22.5 iF
Note that node names are accepted in SPICE3.
2.2.5
Inductors The general form of an inductor statement is
Lname node] node2 lvalue <IC = iLO
>
The L in the first column identifies an inductor labeled Lname and connected between nodes node] and node2 of the circuit, as shown in Figure 2.3. The BCE of an inductor is
VL =
lvalue'
dt
diL
(2.9)
lvalue is the inductance in henries and represents the proportionality constant between the voltage across the inductor and the rate of change of the current through the inductor. The integral variant of Eq. 2.9 is used in SPICE to model the inductor: .
lL
=
II1 
It
0
va ue
VL
d
t
. + lLO
(2.10)
IC is optional and is used to input the initial (time t = 0) inductor current, iLO' This value is used at t = 0 only when UIC is specified in the • TRAN statement, as described in Chap. 6.
Examples
LXTAL 5 6 0.8 LSHUNT 23 51 lOU IC=15.7M
The statements presented so far describe linear inductors characterized by the constant inductance lvalue. SPICE2 also supports nonlinear inductors the inductance of
no~e2 lL~ Lname VL
Figure 2.3
Inductor model.
46
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
which is a nonlinear polynomial function of the current iL. The general form of a nonlinear inductor statement is Lname node] node2 POLY ZOII < 12 ... > <IC The keyword
= iLO>
and the values ZO,
POLY identifies the inductor Lname as nonlinear
ll, ... as the coefficients of the corresponding powers of iL. At least one other coefficient must be specified besides ZO. The value of this inductor is computed at each time
point as lvalue
=
to + II . iL + 12 . if + ...
(2.11)
The BCE for the nonlinear inductor becomes VL
= ~~ =
:t(lvalue'iL)
=
:t(ZO'iL+ll'if+12'it+
... )
(2.12)
The coefficients to, ll, 12, ... are the coefficients for a polynomial representation not of the magnetic flux <p but of the inductance.
EXAMPLE
2.4
LPAR 21 0 POLY 0 5M 1
The BCE for inductor LPAR is obtained from Eq. 2.12: VL which is solved at each time point. :t (0.005 . if
=
+ it)
2.2.6
Independent Bias and Signal Sources
Voltage and current sources that are independent of any circuit variables are defined by the following general statements: Vname node] node2 < <DC> devalue> <AC <ac...mag <aephase> >>
+ <TRAN_junction + <TRAN_junction
<value] <value]
<value2 ... devalue> <value2 ...
»> »>
Iname node] node2 «DC>
<AC <ac...mag <aephase»>
The V and the I in the first column identify a voltage source and a current source, respectively, connected between nodes node] and node2. The polarity conventions are shown in Figure 2.4. The devalue is the voltage difference between nodes node1 and
TWOTERMINAL
ELEMENTS
47
Vname
Iname
Figure 2.4
Independent
voltage and current sources.
node2 for a voltage source and the current flowing from node nodel to node node2 through the source for a current source. The voltage across the terminals of a voltage source is independent of the current flowing through it. Likewise, the current Bowing through a current source is independent of the voltage across its terminals. Independent sources are used to describe biases and signals for the three analytic modes of SPICE: DC, transient (timedomain), and smallsignal AC.1f a source definition contains no other information except the name and the nodes, the program assumes a DC source of value O. . .
EXAMPLE 2.5 vee
10 0 DC 5 IE 0 1 lOU IBl 1 0 'lOU VMEAS 4 5
All four statements define DC sources. The keyword DC is not necessary for defining the DC value of vee and is used mostly for clarity when a lot of information is present on the source line. The current IB flows from ground into node 1 of source lB. I B 1 is identical to I B since both the order of the nodes and the sign of the current have been changed. VMEAS is a zerovalue.voltage source used in SPICE to measure currents (see also Chapter 4). The DC value of a source remains constant during a transient analysis if no other information is provided.
acmag and acphase are the magnitude and phase in degrees of an AC smallsignal voltage or current. These values must be preceded by the keyword AC and are used only in conjunction with an AC analysis request, described in Chapter 5. If the keyword AC is alone, a magnitude of 1 and a phase of 0 are assumed by the program. The value of the transfer function at any point in the circuit referred to the input can be obtained by monitoring an AC voltage or current. The input Vin(jw) is defined by the AC source. The output variables computed by the program, such as Vout(j w), are
48
2
CIRCUIT ELEMENT AND NETWORK DESCRIPTION
identical to the transfer function, T(jw), phase of 0: Vout(jw) since Vin(jw)
if the input signal has a magnitude of 1 and
=
T(jw)Vin(jw)
=
T(jw)
(2.13)
= acmag'
exp(j . acphase)
=
1
(2.14)
For the largesignal timedomain analysis, SPICE supports five types of timedependent signals: pulse, exponential, sinusoidal, piecewise linear, and singlefrequency frequency modulated. The TRAN function specification in a source statement contains a keyword that identifies one of the five functions and a set of parameters. In the following description of the five functions, the parameters and their defaults are specified.
2.2.6.1 Pulse Function
The general format of the TRAN function specification of the source statement is PULSE (Vi V2 <TD <TR <TF <PW <PER»»» where the seven parameters have the meanings shown in Figure 2.5 and described in Table 2.3. The order of the values following the TRAN_function is essential for the correct specification of the signal characteristics. The parameters must be input in the given order. The initial and pulsed values, Vi and V2, must be specified. If no values follow the function name, SPICE2 and SPICE3 perform the simulation and do not flag an error; PSpice, however, announces an error and aborts the analysis. The rest of the values, TD through PER, need not be input, but all values preceding the last nonzero parameter must be specified. The default values listed in Table 2.3 are used for unspecified parameters and are related to TSTEP and TSTOP of the transient analysis introduced in Chap. 1 and described in detail in Chap. 6; TSTEP is the output resolution of the waveforms, or time step, and TSTOP is the end of the time interval.
Amplitude,
V or A
Time, S
PER
Figure 2.5
SPICE PULSE source function.
0 s s s TF PW PER s 0. however. such as VD. .0V 0 > 1.1U) The waveforms generated by the four statements are shown in Figure 2. such as VIN and VSAW.:> ~ 1. For a step function neither PW nor PER need to be specified.lU 20. IlS Figure 2. The DC value of each of the above sources is equal to the initial value of the pulse.0mA 52 OmA 5.TWOTERMINAL ELEMENTS 49 Table 2. a single pulse. VIN is a rectangular signal.3 Name VI V2 TD TR Pulse Source Parameters Parameter Initial value Pulsed value Delay time Rise time Fall time Pulse width Period Units VorA VorA s Default 0.0 TSTEP TSTEP TSTOP TSTOP EXAMPLE 2. The PULSE source can describe a step function. or a periodic signal. and for a single pulse PER must not be specified. SPICE3.0V ov 5 10 Time.0V <. such as IKICK.0 0. Neither SPICE2 nor PSpice accepts a DC value different from the first value of the PULSE function. and VSAW a sawtooth.0V z :> ~ « en > ov 1. allows the user to define a DC value different from 1.6 VD 3 0 PULSE (1 1 1U) IKICK 0 2 PULSE (0 1M 1U 0 0 2U) VIN 1 0 PULSE (0 5 0 IN IN 99N 200N) VSAW 3 4 PULSE (0 1 0 IOU IOU O.6.6 Sample PULSE source functions.
Thus a value one or two orders of magnitude smaller than TR and TF needs to be specified. SPICE uses the defaults of TSTEP for the fall time and TSTOP.2 Sinusoidal Function The general format of the sinusoidal function in the source statement is SIN(VO VA <FREQ <TD <THETA»» where the five parameters are illustrated in Figure 2. does not accept a zero value for PW and replaces it by the default value. a voltage or current change in zero time can cause the solution not to converge. The single pulse IKICK defines a pulse of 2 fJs width and zero TR and TF. the pulse width.15) Amplitude. Therefore. should be zero. Due to the numerical integration algorithm used by SPICE. a warning message is output stating that the time zero value is used for DC.4.TD))eTHETA(tTD) (2. The source assumes the offset value VO for times from t = 0 to t = TD and behaves according to the following function for t > T D: f(t) = VO + VA sin(27TFREQ(t . the other values are optional.7 and described in Table 2. 9. . but the faster rise and fall times cannot be seen on the lineprinter plot. the program substitutes the default value. The offset and the amplitude must always be specified. The step function described by VD does not need any additional information besides the initial and pulsed values and the delay time of the step. however. For the sawtooth voltage source. TSTEP for TR and TF. 2.7 SPICE SIN source "function. PW. Values smaller than TSTEP can be specified for TR and TF. TSTOP. VSAW.2. explained in more detail in Chap. V or A T VA 1/FREQ t VA 1 1/THETA Time. the end of the transient analysis.50 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION the starting value VI of the PULSE function.6. s Figure 2. In the absence of devalue. SPICE. for the pulse width.
73. equal to 2.0 0. the period is equal to the time interval of the analysis. SPICE3 and PSpice allow a negative delay.3 FrequencyModulated Sinusoidal Function The general format for a singlefrequency frequencymodulated (SFFM) transient function on a source statement is SFFM (VO VA <Fe <MDI <FS»» The five parameters are defined in Table 2. The last source. in other words.5U) The first example describes a sinusoidal signal of 1 V amplitude. and 1 for veas.0 Parameter VA FREQ TD THETA Offset Amplitude Frequency Delay Dampingfactor VorA VorA Hz s SI 0.0 EXAMPLE 2. The number of signal periods depends on TSTOP. in SPICE2 the signal veas would be a sine wave. indeed. Therefore. the SIN and SFFM functions produce identical waveforms.2 rnA amplitude.5. over 10 periods.0 VTSTOP 0. The waveforms produced by the three sources are plotted in Figure 2. Note that an SFFM function does not contain any delay. implements a cosine signal by specifying a negative delay equal to 2. in one case defining damping characteristics and in the other.5 fLs.7 VSIN 33 34 SIN(O 1 1MEG) I2 2 0 SIN (1M . The SFFM source is a special case of a sinusoidal source. and 10 MHz frequency that is delayed by 1 fLs and decays by a factor of e. The second example is a current source that supplies a sinusoidal signal of 1 rnA DC current.6. . and 1 MHz frequency.TWOTERMINAL ELEMENTS 51 Table 2. The default for FREQ according to the parameter table is lITSTOP. zero DC offset.4 Name VO Sinusoidal Source Parameters Units Default 0. The number of periods that can be viewed for this interval are 10 for VSIN. but not SPICE2. the length of the time interval for the transient analysis. modulation. The last two parameters differ between the two functions. or a quarter of a period. 2.8 over a time interval of 10 fL s.2M 10MEG 1U 1MEG) veas 5 6 SIN (0 5 lOOK 2. 90 for 12. A singleperiod sinusoid independent of the transient analysis interval can be specified by omitting the frequency.2. 0. veas. if only the first three parameters are defined and if they are identical.
52 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION 1V z ii5 > 1 V (J) 5. A signal described by an SFFM function has the following time behavior: f(t) = va + VAsin(27TFC' t + MDlsin(27TFS' t)) (2.2 mA C\l O.8mA 2 4 Time.5 Name VO FrequencyModulated Sinusoidal Source Parameters Parameter Offset Amplitude Carrier frequency Modulation index Signal frequency Units VorA VorA Hz Default 0. > Table 2. ~s 6 8 Figure 2.16) EXAMPLE 2.9.8 VIN 3 0 SFFM (0 1 lMEG 2 250K) The above source produces a 1 MHz sinusoid of 1 V amplitude modulated at 250 kHz. It is shown in Figure 2.0 0.0V 0 C> > 5.8 Example SIN source functions.0V 1.0 l/TSTOP 0.0 l/TSTOP VA FC MDI FS Hz .
10 SPICE EXP source function. and the other parameters need not be specified. Jls 6 8 Figure 2. 2.6.6.4 Exponential Function The general format of the EXP TRAN_function in the source statement is EXP (Vi V2 <TDi TAW TD2 <TAU2») where the six parameters are as illustrated in Figure 2.10 and are described in Table 2. S TD1 TD2 Figure 2. Vi and V2. . must be specified.2. the defaults listed in the table are used for any missing parameter values. The initial and pulsed values.TWOTERMINAL ELEMENTS 53 1V z :> 2 4 Time.9 SPICE SFFM source function. The time behavior of an exponential source is described by the following functions of time t: Amplitude. V or A Time.
otherwise the current may start increasing before the end of the analysis interval TSTOP. This is why after a short decay with a time constant equal to TSTEP. The second source. The three waveforms are plotted in Figure 2. by default the value of VEXP would start to fall after TSTEP seconds.V2) e(tTDl)/TAUI) eUTD2)/TAU2) (1  for 0 ::5 t::5 TDi for TDi < t ::5 TD2 for TD2 < t ::5 TSTOP (2.0 TSTEP TDI + TSTEP TSTEP v(t) = Vi VI(t) { V2(t) + (V2 = VI (t) + (Vi = Vi Vl)(1 . 1.1 JLS.0 0.0 0. V2. Vi.5 Piecewise Linear Function The general format of a piecewise linear function on a source statement is PWL (tl VI < t2 V2 < t3 V3 . where TSTEP = 0. ») . must be specified for TD2. and TD2 and TAU2 become the rise delay and time constant. represents an exponential signal that rises from 0 to 5 V with a time constant of 1 JLs. respectively.9 VEXP 1 0 EXP (0 5 0 1U 1) IDEC1 3 1 EXP (1M 0 0 0 0 1U) The first source. the correct definition of a decaying current is the following: IDEC2 3 1 EXP 1M 0 0 1U 1 Note that a large value. until TD2 = TSTEP. IDEC1.Note that since the initial value.6. the current resumes increasing back towards 1 rnA with a time constant equal to 1 JLs... VEXP. the meanings of rise and fall are reversed.17) EXAMPLE 2.54 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Table 2. is intended to be a current that exponentially decays from 1 rnA to 0 with a time constant of 1 JLs.11. 1 second. TDi and TAUl become the fall delay and time constant. of IDECl is larger than the pulsed value.6 Name VI V2 TDl TAUl TD2 TAU2 Exponential Source Parameters Parameter Initial value Pulsed value Rise delay time Rise time constant Fall delay time Fall time constant Units VorA VorA s s s s Default 0. on the VEXP line is necessary for defining T the delay TD2 before the source starts decaying.2.Thus. that is. respectively. he last value. 2.
If tl > 0. is greater than TSTOP.tnI .1 JLS through TSTOP. the first coordinate pair assumed by SPICE is (0. J.tnI tn .2U 5 3U 5 3. 0. tn.TWOTERMINAL ELEMENTS 55 4V a x U. Both IBITl and VDATA are specified with finite rise and fall times.12.J 9 OmA Time. at TSTOP in SPICE2. Vn.10 IBITl 1 0 PWL (0 0 lU 0 1. VI).2U 0 6U 0 6. from 8.11 Example EXP source functions. . equal to 10 JLS.Vnd EXAMPLE 2. Vi). IBITl preserves its last specified value.1U 1M 8U 1M 8.2U 5) + The two waveforms are shown in Figure 2. note that SPICE does not accept more than one PWL source value for a given time point.1U 0 4U 0 4. There is no limit to the number of coordinate pairs specified. The parameters for this function are timevalue coordinates. 0 and TSTOP.1U 0 7U 0 7.Is Figure 2. The signal described by a PWL statement is formed of straight lines that connect the pairs of coordinates (ti. Neither tl nor the last defined time needs to coincide with the transient analysis limits. if the time of the last coordinate pair. SPICE3 and PSpice interpolate the source value at TSTOP: V(TSTOP) = VnI + (Vn TSTOP .1U 1M 5U 1M 5.lU 1M 2U 1M 2. the source assumes the last value. This type of function is useful for describing sequences of pulses.J > OV 1 mA () U.1U 0) VDATA 21 0 PWL (0 0 0.
12 PWL functions. . This section covers multi terminal elements with the exception of semiconductor elements. 3. which must be greater than 0 and less than or equal to 1. generally.3. require only simple specifications.0V > OV 1. The elements presented in this section. See Figure 2. !is Figure 2. defined somewhere else in the input file. 2.13. SPICE3 contains models for: Switches Uniformly distributed RC lines Lossy transmission lines In PSpice the switch and the lossy transmission line are also supported.0mA f ~ OmA Time. k is the coefficient of coupling.1 Coupled (Mutual) Inductors The general format of a coupled inductors statement is Kname Lnamel Lname2 k K in the first column identifies a mutual inductance specification between the two inductors Lnamel and Lname2.3 MULTITERMINAL ELEMENTS elements: SPICE2 supports the following types of multiterminal Mutual inductors (linear and nonlinear) Controlled sources (linear and nonlinear) Transmission lines (linear) Bipolar and field effect transistors (nonlinear) In addition to the above element types. 2. which are treated separately in Chap.56 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION « « 0 f 5.
The above equations must be modified accordingly to include all mutual inductances and terminal pairs.99 The polarity of coupling between the two inductors is defined by the position of the dots as shown in the schematic representation in Figure 2.d to two and can be extended to a multitude of inductor pairs.13.. .MULTITERMINAL ELEMENTS 57 EXAMPLE 2. . Kname Figure 2. must be defined first on the inductor statement. The value of the mutual inductance M is computed as M = kJL]L2 (2.18) where k is the coupling coefficient and L] and ~ are the inductances. .13 Coupled inductors. containing the dot.99 mHo The BCEs of coupled inductors in SPICE are (2. Note that the positive inductor node. The mutual inductance of the coupled inductors is M = .19) Systems of coupled inductors are not limitt.11 The SPICE specification of two coupled inductors L1 and L2 is L1 121M L2 4 3 1M KL1L2 L1 L2 .
with N1 turns. Additionally. a voltagecontrolled current source. VCVS. the primary. supply voltages or currents that are functions of voltages or currents in other parts of the circuit. Dependent sources are useful for implementing a variety of largesignal input/output transfer functions (Epler 1987). and the voltages and currents obey the following relations: (2. CCCS. VCCS. such as SpicePLUS.2 Dependent (Controlled) Sources Dependent sources.3. SPICE supports four types of dependent sources. CCVS. also known as controlled sources.20) (2. implement a nonlinear magnetic core model.21) EXAMPLE 2. a currentcontrolled current source. and a currentcontrolled voltage source. and the secondary. An ideal transformer has two pairs of terminals. a voltagecontrolled voltage source.22) The coupling coefficient for an ideal transformer is 1. . with N2 turns.58 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Coupled inductors can be used to model an ideal transformer in SPICE. 2. PSpice and other commercial SPICE versions.12 Write the SPICE2 input for a transformer that has turns ratio NdN1 primary has selfinductance L1 = 1 mHo = 5 and whose Solution First calculate the inductance of the secondary knowing that the inductance is proportional to the square of the turns: L2 = N2)2 ( N1 Ll = 25 mH (2. and therefore the SPICE2 input specification for the transformer is the following: LPRIM 121M LSEC 3 4 25M KXFRMR LPRIM LSEC 1 '¥ ~ G ote that PSpice restricts the value of k to less than 1.
. F..4. The sequence of values in the dependent source statement is a function of the number of dimensions of the polynomial. see Sec. SPICE3 and PSpice accept an arbitrary nonlinear function of both voltages and currents in the circuit. and the output is equal to the input. CTRLname/ sources or a voltage source name that measures the controlling current for currentcontrolled sources.4. A nonlinear controlled source is limited to a polynomial function of an arbitrary number of circuit variables in SPICE2. with all optional fields deleted and only one coefficient given. Let Po.14. Xl. A linear controlled source has two ports. The onedimensional polynomial (ndim = 1) is the default in SPICE2. on the dependent source statement denote polynomial coefficients. are coefficients for the polynomial description. and neither the keyword POLY nor ndim needs to be specified. a linear controlled source statement is a special case of the general POLY statement. Only SPICE2 and PSpice recognize the POLY specification. .MULTITERMINAL ELEMENTS 59 SPICE supports both linear and nonlinear dependent sources. In this case that value becomes the coefficient of the linear term. Thus. Xl . or controlling variable. » nodes is a pair of nodes for voltagecontrolled For a linear source only the information outside the brackets is specified...4. Pz.23) An exception to the above assignment of coefficients is made when only one value appears on the source statement. or H. 7.<POLY(ndim» CTRLname/nodes Po < PI < pz . . x3 be three controlling variables. The four types of dependent sources are as follows: VCCS VCVS CCCS CCVS G E F H = = VE = VE = IF = IF = VH = VH = Ie Ie GVe g(Vc) EVe e(Vc) FIe f(lc) HIe h(lc) linear nonlinear linear nonlinear linear nonlinear linear nonlinear The different types listed next to the four kinds of controlled sources represent the identification character on an element statement. PI. In SPICE3 only linear controlled sources are identified by G.1 and Sec. The general format of dependent sources is CSname node+ node. The input values represent the following coefficients: (2. E. . Xz. PI. pz.. A nonlinear source can depend on more than one current or voltage. Po. 7.. all types of nonlinear controlled sources have B as the first character of the element name. and f (x) be the dependent polynomial function. the symbols and controlling elements are shown in Figure 2. times a proportionality constant.
2.60 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION nc+~+ 11 nc+o. of a current of 1 rnA flowing from mode 3 through the source to node 2 and controlled by the voltage. The second statement is rejected by SPICE3.nr llCO  11+ nce>.4)} (PSpice) The first two statements represent the same VCCS. The third example.E 11 G + 11 + 11+ F H Figure 2. EXAMPLE 2. VI. 7.4.14 Dependent sources.13 G1 3 2 1 2 1E3 G1 3 2 POLY(l) 1 2 1E3 G2 5 6 3 4 10M 1M (SPICE2) G2 5 6 VALUE = (O. 82 must be described by a B statement in SPICE3 (see Sec. the third statement is accepted by PSpice ifthe keyword POLY (1) is included.Ol+lE3*V(3. The fourth statement represents the preferred syntax for PSpice. 82. is interpreted like a regular polynomial source in SPICE2 but causes an error in PSpice.+ 11+ Vnc+.1). or transconductance. because in this way the general nonlinear dependent source statement takes the particular form of a linear controlled source for ndim = 1. nc Vnc+. between nodes 1 and 2: The above discrepancy in the meaning of Po has been deliberately chosen for onedimensional polynomial sources. The value of 82 is evaluated according to the following equation: .
. The second difference is that for each additional controlling voltage a pair of controlling nodes.nc (2.. ndim is the number of controlling voltages. Vnc2+.26) where gvalue is the transconductance in mhos. operational amplifiers.1 VoltageControlled Current Source (VCCS) The general format of a linear VCCS is Gnamen+ n.nc+ nc. The BCE of a VCCS is Ie = gvalue .<POLY( ndim) > nc1 + nc1 < nc2+ nc2.(see Figure 2. Controlled sources are useful for emulating analog and digital circuit blocks..gvalue A G in the first column followed by up to seven characters and digits define the unique name of a VCCS. nc2. X3) = Po + PIX] + P2X2 + P3X3 + P4XI + P5X]X2 + P6X]X3 + P7X2 + P8X2X3 + P9X3 + PIOX] + PllX]X2 2 2 3 2 + P12XIX3 + P13X]X~ + P]4X]X2X3 + P]5X]X~ (2.. nc2+..3.are the terminals of the first controlling voltage.nc2. with current flowing from the positive node.. The linear VCCS is only a special case of the more general nonlinear VCCS. which can be present only when a nonlinear VCCS is specified. . take the meaning described above depending on the number of controlling variables. P2.nc.. PI.is the controlling variable.are the nodes between which the current source is connected. through the source to the negative node. > > <Ie = Vnc1 +..25) + p]6Xi + P17X~X3 + P]8X2X~ + P]9X~ + . n+. must be specified. > + Po < p] < P2 . > The first difference between this statement and that of a linear VCCS is the keyword POLY. X2) + PIX] + P2X2 + P3XI + P4X]X2 + P5X223223 X] + P7X]X2 + P8X]X2 + P9X2 + P6 (2.. n+ and n. The . . X2. Vnc+.MULTITERMINAL ELEMENTS 61 A twodimensional polynomial function is expressed as = Po f (x]. and many others.2. converters... 2. The coefficients Po. respectively.24) A threedimensional polynomial function assigns the values on the source statement to coefficients in the following order: f(x]. the voltage difference Vnc+. n.nc1. The positive and negative controlling nodes are nc+ and nc. The general format of a nonlinear VCCS is Gnamen+ n. such as gain stages.14). and nc 1 + and nc 1.
because the re keyword and initial value are present on the GRPOLY line. at t =0 the terminal voltage.nc (2. respectively.2 + 3.are the positive and negative controlling nodes.1.27) where evalue is the voltage gain. Note that the keyword POLY is needed in PSpice for a onedimensional source. n+ and n.3 V.3.2.14 GRPOLY 17 3 POLY (1) 17 301M 1.nc+ nc. nc+ and nc. when the ure flag is on). or equal to the resulting value from the DC bias point otherwise.evalue An E in the first column followed by up to seven characters and digits defines the unique name of a VCVS. The BeE of a VCVS is VE = evalue' Vnc+.S + 0.2 VoltageControlled Voltage Source (VCVS) The general format of a linear VCVS is Ename n+ n. These values are used only in conjunction with the ure option in the • TRAN statement to initialize the controlled source at the first time point.is the controlling variable.are the positive and negative nodes of the voltage source. The second example is a twodimensional nonlinear VCCS of value Ie = 0. the voltage difference Vnc+. The BCE of the nonlinear conductance GRPOLY is Ie = 0.001.017.5. because the terminal nodes of the controlled current source are identical with the nodes of the controlling voltage. VI.5U IC=2. 6 for 2. the controlling voltages are assumed to be zero. .62 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION third difference from the statement for a linear VCCS is that initial conditions can be defined for the controlling voltages.3 The first example represents a nonlinear conductance. If no initial values are present. V3.nc. 1O6Vts In a transient analysis that starts from initial conditions (that is.001.14. 5M IC=2 G2DIM 23 17 POLY (2) 3 5 1 201M 17M 3. to 2. The linear VCVS is only a special case of the more general nonlinear VCVS.5 .0015 . as shown in Figure 2. Ve + 0.5 V and 1. the two controlling voltages are initialized details. EXAMPLE 2. Ve is 2 V. V~ In a transient analysis. respectively. but not in SPICE2. if the ure option is chosen. see Chap.
0. For an explanation of the result. 2.llc2.2.. E 1. n+ and n.Ilcl..5 + 2. and V3. or equal to the resulting value from the DC bias point otherwise. > Po < PI < P2 .3 The first example. Use different values for VI. EXAMPLE 2.o. ne2 . and V3.0. 5 and 7.2. must be specified. Vname is the voltage source through which the controlling current flows.1 1.are the positive and negative nodes of the current source. if the UIC option is chosen. If no initial values are present.MULTITERMINAL ELEMENTS 63 The general format of a nonlinear VCVS is Ename n+ n..5 2. Exercise Run an AC analysis of the voltage summer ESUM using SPICE and verify if this VCCS still performs the add function. V21.17+ 1. PI. Vllc2+. take the meaning described above depending on the number of controlling variables.14). V2. for each additional controlling voltage. IC is optional and defines the initial values of the controlling voltages.. a pair of controlling nodes.are the terminals of the first controlling voltage.<POLY (ndim) > nel + ne1+ <ne2+ ne2 .75 ESUM 17 0 POLY(3) 1 0 2 0 3 0 0 1 1 1 1C=1. defines a nonlinear voltage gain function VE = 10. ne2 +. The coefficients Po. the controlling voltages are assumed to be zero. V2.0.. and current flows from the positive node through the source to the negative node (see Figure 2... > > <IC= vllcl +.. P2. these values are used only in conjunction with the UIC option in the • TRAN statement to initialize the controlled source at the first time point. 15 E1 3 4 POLY (1) 21 17 10. > The keyword POLY must be present when a nonlinear VCVS is specified. ndim is the number of controlling voltages. .0. since the value of the controlled source ESUM is the sum of Vl..O.1. .3. ncl + and ncl.75. Vh17 The second example represents a voltage summer.Vname fvalue An F in the first column followed by up to seven characters and digits defines the unique name of a CCCS.3 CurrentControlled Current Source (CCCS) The general format of a linear CCCS is Fname n + n . see Chaps.
28) where fvalue is the current gain... 2.2 with a CCCS connected from collector to emitter having value fvalue = Ih = 100 and controlled by the current iRB. 1. i(Vname2) ..64 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION I(Vname) is the controlling variable.001 1E4 1E5 F2 2 3 POLY (2) VCON1 VCON2 0 0 0 0 1 FeON defines a current that is a quadratic function of the current flowing through the voltage source ve 1: . ndim is the number of controlling currents. If no initial values are present. The current of F2 is equal to the product of the currents flowing through voltage sources . > Po <PI <P2 . or equal to the resulting value from the DC bias point otherwise. these values are used only in conjunction with the UIC option in the •TRAN statement to initialize the controlled source at the first time point. PI.. The general format of a nonlinear CCCS is Fname n+n<POLY (ndim» Vname1 <Vname2 .. IC is optional and defines the initial values of the controlling currents. Explain the difference and modify the circuit to obtain the same answer. Exercise Replace transistor QI in Example 1.3. veONl and veON2. > The keyword POLY must be present when a nonlinear CCCS is specified.Vname hvalue . the controlling currents are assumed to be zero if the UIC option is chosen.. P2. Vnamel is the voltage source measuring the first controlling current.2. and show that the bias point obtained by SPICE is close to the one obtained in Chap. take the meaning described above depending on the number of controlling variables.4 '~ CurrentControlled Voltage Source (CCVS) Th~ general format of a linear CCVS is •Hname n + n . » + <IC = i(Vnamel). for each additional controlling current a voltage source must be specified. . The BCE of a CCCS is h = fvalue 'I(Vname) (2.16 FCON 13 4 POLY (1) VC1 0. The linear CCCS is only a special case of the more general nonlinear CCCS... EXAMPLE 2. The coefficients Po.
or equal to the resulting value from the DC bias point otherwise. the controlling currents are assumed to be zero if the OIC option is chosen. depending on a controlling voltage or current.MULTITERMINAL ELEMENTS 65 An Hin the first column followed by up to seven characters and digits defines the unique name of a CCVS. The coefficients Po. pz. ndim is the number of controlling currents.. and a very large value... > » The keyword POLY can be present only when a nonlinear CCVS is specified. as shown in Figure 2.3. The BCE of a CCVS is VH = hvalue' I(Vname) (2. > Po <PI <pz .17 HRNL 1 2 POLY (1) V12 0 0 1 HXY 13 20 POLY(2) V1N1 V1N2 0 0 0 1 2 1 10=0. Vname is the voltage source through which the controlling current flows.3 The voltage between nodes 1 and 2 of HRNL is equal to the square of the current flowing through V12.1. respectively. and the value of HXYis equal to the square of the difference of the currents through voltage sources VINl and VIN2. IC is optional and defines the initial values of the controlling currents.. Vnamel is the voltage source measuring the first controlling current.. An ideal switch has zero ON resistance and infinite OFF resistance. If no initial values are present..<POLY (ndim) > Vnamel <Vname2 . for each additional controlling current a voltage source must be specified.. n + and n . I(Vname) is the controlling variable.are the positive and negative nodes of the voltage source. The linear CCVS is only a special case of the more general nonlinear CCVS. take the meaning described above depending on the number of controlling variables. The switch is therefore a resistor that toggles between a very small value.29) where hvalue is the transresistance in ohms. The general format of a nonlinear CCVS is Hname n+ n. PI. . the OFF resistance.14. + <IC = i(Vnamel). these values are used only in conjunction with the OIC option in the • TRAN statement to initialize the controlled source at the first time point.5.. the ON resistance. 2. i(Vname2) .3 Switches SPICE3 and PSpice support a nearly ideal switch model. . than the other resistances in the circuit. EXAMPLE 2. This behavior can be approximated satisfactorily with ON and OFF resistances that are significantly smaller or larger.
GMIN in the table is a minimum conductance.0 0. SW. The switch is connected between nodes n + and n . their use in a circuit can lead to convergence problems.and is controlled either by the voltage between nodes nc+ and nc. It is strongly recommended that ROFF < 1012 RON (2. the currentcontrolled switch. Because switches are highly nonlinear. switching at Vcontrol = VT when Vcontrol is rising and at VT . There are two types of switch models. in order to avoid the situation in which the time step is too small (see Chap.0 0.7. In order to prevent the failure of the timedomain analysis.0 1. Each model type defines four parameters. Model is the name of the model statement that contains the parameters of the switch.or by the current flowing from the positive node to the negative node of the voltage source Vname. 9.Model <ON/OFF> Wname n+ n.66 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION Voltage. a W identifies a currentcontrolled switch. for other uses of GMIN see Chap. and CSW. the voltagecontrolled switch.7 Name VT IT VH IH RON ROFF Switch Model Parameters Parameter Threshold voltage Threshold current Hysteresis voltage Hysteresis current ON resistance OFF resistance Units V A V A Default 0.0 lIGMIN Model n n.0 0.CSW SW. and for modifying it see Chap. shown in Table 2. 9). The interval between the two variables is used to provide for a smooth transition between RON and ROFF. and the flag ON/OFF specifies the initial state of the switch.15. which prevent sudden changes in the controlling variables. 3. that is. The switch in SPICE3 displays hysteresis.CSW . The parameters VT and VH are replaced by VON and VOFF for an S switch.and currentcontrolled switches have the following general formats: Sname n+ n. Table 2. The resistance of the switch as a function of the controlling variable is shown in Figure 2.nc+ nc.VH when Vcontrol is falling.30) ~ Another remedy for convergence failure of circuits with switches is the addition of capacitors across the controlling voltage and inductors in series with the controlling current. used in SPICE to protect against an illconditioned set of nodal equations. Note that the PSpice switch does not have hysteresis. and IT and IH are replaced by ION and IOFF for a Wswitch. SW CSW SW CSW SW. RON should be negligible compared to the smallest resistance and ROFF should be large enough not to affect the total value when connected in parallel to the largest resistor.Vname Model <ON/OFF> where an S in the first column identifies a voltagecontrolled switch.
. EXAMPLE 2.16 NOR gate implemented with switches.18 Use switches to model a NOR gate in SPICE3. The values are RON = 1 0" ROFF = 1 Mo'. The value of the load resistor is 1 ko'. Solution A straightforward implementation is shown in Figure 2. o Vee. Rs V'l"  ~1' R4 V4   Figure 2.16.MULTITERMINAL ELEMENTS 67 Rswitch ROFF RON VT Vcontrol Figure 2. respectively. RON and ROFF are selected such that they are much smaller and much larger. For best results in SPICE.15 Switch resistance as a function of controlling voltage. the circuit is equivalent to the MOS implementation of a NOR gate with the transistors replaced by switches and a load resistor connected to 5 V. than 1 ko'.
ii.01U 5 V4 4 0 PWL 0 0 2U 0 2. model type ISWITCH.01U 5 2U 5 2.01U 5 0 3U 0 3. Vn3. SPICE3 and PSPICE support also lossy transmission lines. Only lossless lines are supported in SPICE2.2. and n3 and n4 are the nodes at port 2. and ION and IOFF must be specified. i2 > A T in the first column identifies a transmission line element. 2.n4.68 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION The SPICE3 input description is listed below. The two input signals are a sequence of logic 0 and 1 described as PWL voltage sources.PLOT .3:4 Transmission Lines The general form of a transmission line statement is Tname nl n2 n3 n4 ZO=ZO <TD=TD><F=freq <NL=NL» + <IC=Vnl. VH. as well as for different values of RON and ROFF. See also Chap.MODEL * . ZO is the characteristic impedance of the line. nl and n2 are the nodes at port 1. END SW SW RON=l .01U * .TRAN . represent the two inputs of the NOR gate. PSpice users must replace VT and VHwith VON and VOFF and the model type byVSWITCH. one additional characteristic . The controlling terminals. NOR GATE WITH SWITCHES * * NORGATE * RL 2 1 1K Sl 1 0 3 0 SW S2 1 0 4 0 SW vee 2 0 5 * * INPUT SIGNALS * 3 0 PWL 0 0 V3 R3 3 0 1 R4 4 0 1 1U 0 1.6. 2.n2. nodes 3 and 4. A transmission line together with the SPICE equivalent model is shown in Figure 2.5. 7 for more details on this subject.17. introduced in Sec.for currentcontrolled switches.02U 4U V(3) ROFF=lMEG VT=1 VH=O TRAN V(l) V(4) Exercise Run this circuit in SPICE3 and study the impact of various values for the hysteresis width.
TD) Vnl. iz(t .Jreq is the quarterwave frequency. The BCEs of the transmission line are expressed as the following functional forms of the voltage sources VI (t) and vz(t) in the equivalent model (Branin 1967) of Figure 2.n2(t . These values are used only in conjunction with the UIC option on the • TRAN statement. If only a frequency is specified andNLis omitted.n4(t . IC. must be specified about the line.25. which can be either the line delay. that is. The three parameters are described by the following equation: TD where NL I = NL jreq (2. NLdefaults to 0. TD.TD) The two equations represent the incident and reflected waves along a lossless transmission line.34) + 20.MULTITERMINAL ELEMENTS 69 n1 n2 0_0 0>0 Tname n3 n4 n1 n2 Figure 2.TD) + 20 .17 Transmission line and equivalent model. . or the normalized electrical line length. Initial Conditions.31) = A (2. at a given frequency jreq. expressed in wavelength units. NL.32) with I the physical length of the line and A the wavelength.33) (2.TD) (2. iI(t .17: VI (t) VZ(t) = = Vn3. are optional and consist of the currents and voltages at the terminals of the two ports.
The SPICE input is listed below: TRANSMISSION LINE EXAMPLE VIN 1 0 PULSE 0 5 0 0.33 RL=100n :.N 0 2. .18 Transmission line response for RL = 50 nand RL = 100 n. 2. Tl 1 0 2 0 ZO=50 TD=10N T1 1 0 2 0 ZO=50 F=100MEG NL=1 T1 1 0 2 0 ZO=50 F=25MEG A coaxial cable is described by two transmission lines. . I . 20 Time. .25N SON .5N TEXT 2 0 4 0 ZO=100 TD=1N Study the difference in the response ofline TLINE to a pulse when terminated with a load resistor RL of 50 nand 100 n. 30 .32. 0 .5 cry RL= 50n :. .1N 5N SON RIN 1 2 50 TLINE 2 0 3 0 ZO=50 TD=10N RL 3 0 50 . . 40 . . the first representing the inner conductor with respect to the shield.5 N :.PLOT TRAN V(2) V(3) * 2. see Eq..0 2.31 and 2.TRAN .10 . ns Figure 2.70 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION EXAMPLE 2.cry 0 3. and the second the shield with respect to the outside world: TINT 1 2 3 4 ZO=50 TD=1.1N 0. I .5 :.19 The following three definitions ofline Tl are equivalent. .
. RL. and ZOo 2.4 SUMMARY This chapter describes all the elements supported in SPICE with the exception of the semiconductor devices. type E. switches. <acJ11ag <acphase»> + <TRAN_function »> where TRANfunction can be one of the following: PULSE (VI V2 <TD <TR <TF <PW <PER»»» SIN (Va VA <FREQ <TD <THETA»» SFFM (va VA <Fe <MDI <FS> >» EXP (VI V2 <TDI <TAW <TD2 <TAU2»») PWL (tl VI <t2 V2 <t3 V3 .. type G.PRINT TRAN V(2) .SUMMARY 71 . a voltagecontrolled current source. Coupled inductors have the following syntax: Kname Lname I Lname2 k Four types of controlled sources are supported in SPICE. controlled (dependent) sources. were defined. <tc2» Cname nodeI node2 cvalue <IC Lname nodeI node2 lvalue <IC = = Vco > ho > Capacitors and inductors can be also defined as nonlinear. The difference is that a matched line with Rin = RL = ZO delays the input pulse by TD while the unmatched line reflects the pulse between input and output with an attenuation corresponding to the values of Rin. resistor.. respectively. Independent voltage and current bias and signal sources can be specified using the following generic SPICE statement: V/Iname nodeI node2 «DC> <valueI dc_value><AC <value2 . Multiterminal elements supported in SPICE include coupled inductors. the twoterminal passive elements. a voltagecontrolled voltage source. L. and inductor. END V(3) The waveforms at the input and output of TLINE for the two values of the load resistor RL are shown in Figure 2.18. First. polynomial expressions of voltage and current. C. a currentcontrolled .. ») For each of the optional parameters SPICE provides default values. Both the syntax and the relation between the branchconstitutive equations and SPICE statement parameters were explained and exemplified. capacitor. and transmission lines. R. T~ese elements use the following SPICE syntax: Rname nodeI node2 rvalue <TC= tcl.
Vname Model <ON/OFF> One or more switch elements reference a . Newton. C. Boston: Kluwer Academic. Version 5. F. and a currentcontrolled dent source has the following syntax: voltage source. PSpice. Berkeley: Univ.nc+ nc. A.POLY(ndim) Vname/ncnodes Po PI + <P2 <P3 . T. Johnson. Berkely.MODEL statement that defines the necessary parameters. The modified nodal approach to network analysis. Ruehli. H. i2 = TD> <F =freq <NL = NL> > devices. MicroSim. + < Ie = VnI.. Pederson. B. Newton. REFERENCES Branin. 1991.n2. McCalla. Pederson. 1991.0. D. (April). A. The last element introduced in this chapter is the ideal transmission line defined by the following statement: Tname nl n2 n3 n4 Zo = ZO <TD iI.72 2 CIRCUIT ELEMENT AND NETWORK DESCRIPTION current source. Irvine. of California. and P. J. SPICE3 Version 3E User's Manual.Model <ON/OFF> Wname n+ n. the operation of the switch can be controlled by a voltage (type S) or a current (type W). 1967. O.nc+ nc. 1975. L. Sangiovanni. Ho. IEEE Transactions on Circuits and Systems. > This chapter has detailed all SPICE circuit elements except semiconductor which are the subject of the following chapter. and A. Nonlinear polynomial controlled sources use the following general syntax: G/E/FlHnamenode+ node. O. 1988. Circuit Analysis User's Guide. W.. CA: Author.. Univ. SPICE2 application notes for dependent sources. D. Zhang. A. Transient analysis oflossless transmission lines. Fundamentals of ComputerAided Circuit Simulation. L.Vname value Vname is the name of the voltage source used to measure the controlling current.value F/Hname node+ node. w. R. SangiovanniVincentelli. Department of Electrical Engineering and Computer Science. Quarles. SPICE Version 2G User's Guide. type F. The syntax for the two types of switches is Sname n+ n. Vn3. IEEE 55: 20122013. » More complex nonlinear dependent sources supported in SPICE3 and PSpice are defined in Chap. . CAS22 (June): 504509.. 1981 (August). of California. A.. 1987. Proc. Vladimirescu. R. K. Brennan. A. IEEE Circuits and Devices Magazine 3 (September): 3644. Epler. type H. 7. A nearly ideal switch is implemented in SPICE3 and PSpice.n4.Vincentelli. B. A linear depen G/Ename node+ node. and A. E.
respectively. Q. > MODname <value] <. Up to seven characters can follow to identify the element..1 INTRODUCTION Semiconductor elements are presented together as a group because they have a common specification methodology. SPICE2 was initially developed for integrated circuits (ICs).. These parameters are specified in a • MODEL statement.. and metaloxidesemiconductor field effect transistor (MOSFET). diode.. 2. SPICE2 supports four different semiconductordevice models.. J.junction field effect transistor (JFET). The element statement for any semiconductor device has the following general format: DEVname node] node2 <node3 . As mentioned in the beginning of Chap. and M corresponding to the four kinds of semiconductor elements accepted by SPICE2.of . bipolar transistor (BJT). 2. Two to four node numbers specify the connection of the semiconductor element terminals. and SPICE3 and PSpice accept five different semiconductor devices. Unlike the elements described in Chap. and the 73 .earameters. is identified by a Z in SPICE3 and a B in PSpice. > + <OFF> <IC=v]<..v2. » The device name DEVname starts with one of four characters D.Three SEMICONDUCTORDEVICE ELEMENTS 3. semiconductor elements are defined by complex nonlinear BCEs characterized by a large number. the metalsemiconductor field effect transistor (MESFET). .value2>. . The additional semiconductor device supported in SPICE3 and PSpice. MODname is the name of a model statement that contains the parameter values. one or more semiconductor devices can reference the same model.
and PSpice support the following model types: D Diode model npn BJT model pnp BJT model nchannel JFET model pchannel JFET model nchannel MOSFET model pchannel MOSFET model model types: NPN PNP NJF PJF NMOS PMOS SPICE3 supports the following additional semiconductor R Diffused resistor model Diffused capacitor model c . to scale their geometry with respect to a unit device. This name is referenced by the device statements. SPICE3. such as channel dimensions and areas. valuel. This specification is used only in conjunction with a transient analysis.. In all other circumstances these values are ignored. » MODname is a unique eightcharacter name in SPICE2 and a name of arbitrary length in SPICE3 associated with the parameter values defined in this statement. 6.. at which point the constraint is removed and iterations continue until the first converged solution is confirmed or a new solution is found. The values defined as part of the IC option are used only when the UIC option is specified in the •TRAN statement. that are unique and differentiate it from other devices having the same model parameters. More complete geometric information is available for MOSFETs because of the importance of this device type in LSI and VLSI circuits. which precludes the computation of a DC bias solution. and MESFETs use only one parameter. MODtype is one of seven recognized device types in SPICE2 and one of twelve in SPICE3. each semiconductor device has certain geometric characteristics. JFETs. MOSFETs require more detailed geometric information. see Chap. Besides the process parameters. value2. BJTs. which are general model parameters. These initial conditions are optional and are seldom used. OFF devices are held in the cutoff state until convergence is reached. The OFF flag is a toggle that initializes the device in the nonconducting state for the DC solution. In other words. The rest of the information in a semiconductor element statement specifies the initial state of the device. The companion model statement for semiconductorelement statements has the following general format: • MODEL MODname MOD type <PARAMl=valuel <PARAM2=value2 .74 3 SEMICONDUCTORDEVICE ELEMENTS commonality of model parameters can be traced back to the common process parameters. The optional IC specification defines the values of the terminal voltages of a semiconductor device at time zero. area. SPICE2. Diodes. a device initially assumed to be OFF may tum out to be conducting at the completion of the SPICE DC solution. The iterative DC solution process assumes that at the start all semiconductor elements are either conducting or on the verge of conduction. and so on.
For details on the semiconductordevice physics underlying the models described in this chapter.1) (3. K. called an LPNP. or cathode. More than one model type can share the same parameters. the keyword OFF initializes the diode in the cutoff region. and nis the negative node. and an additional BJT model type for a lateral pnp. D identifies a diode and can be followed by up to seven characters in SPICE2. and T is the temperature in degrees Kelvin. The following sections describe the supported semiconductor elements. otherwise diodes are initialized at the limit of tumon. The descriptions of both the element and the companion model are presented. q and k are the electron charge and Boltzmann's . Muller and Kamins 1977. several reference texts (Grove 1967. In this chapter each element is described together with its model parameters. or nonideality coefficient. VDO is used as initial value only when the UIC option is present in the • TRAN statement.6 V.MODname <area> <OFF> < IC=VDO > The letter D must be the first character in Dname. for the DC solution. The parameters and supporting equations for the firstorder models are introduced. The BCE of the diode in DC is described by an exponential function: ID = IS(eqVD/NkT . The schematic symbol of a diode is presented together with its pnjunction SPICE implementation in Figure 3. Four sets of semiconductor parameter names occur in SPICE2. for example. N is the emission. For the initial iterations of the DC bias solution. 3. A model statement with no values assigns the defaults of the specific type to that model name.1. area defaults to 1. The keyword IC defines the voltage VDO at time t = 0 for a time domain analysis. M 0Dname is the name of the model defining the parameters for this diode element. called a GASFET. Only those parameter names must appear on the model statement that are assigned different values from the defaults built into the program. eight in SPICE3. with VD = 0.DIODES 75 URe NMF Uniformly distributed RC model nchannel MESFET model pchannel MESFET model PMF PSpice also has a builtin model for an nchannel galliumarsenide FET. The complete equations and list of parameters for semiconductor devices are contained in Appendix A and in more detail in Semiconductor Device Modeling with SPICE (Antognetti and Massobrio 1988). npn and pnp bipolar transistors.1) where IS is the saturation current. The variable area is a scale factor equal to the number of identical diodes connected in parallel. or anode. Sze 1981) are suggested. and five in PSpice. n+ is the positive node.2 DIODES The general format of a diode element statement is Dname n + n.
is defined. can be easily derived as the slope and the intercept at the origin of the log ID versus VD plot.2.2 1V characteristics of a diode: (a) ID versus VD.1 is shown in Figure 3. 106 108 1010 1012 IS . that is. The breakdown current occurring when the diode is reversebiased is also modeled if the value of the breakdown voltage parameter.1 nDiode element. of a semilogarithmic plot of Eq.76 3 SEMICONDUCTORDEVICE ELEMENTS n+ Figure 3. The two model parameters./ .1. (h) Figure 3. The variation in time of the diode current of a shortbase diode (Muller and Kamins 1977) is controlled by the two types of charge storage in a semiconductor pn junction. the diffusion charge and the depletion charge. Vth = kT / q. 3. The IV characteristic of the diode described by Eq. see Appendix A for complete equations . respectively. BV. equal to 1. (b) log ID versus YD. . IS and N. The current at the breakdown voltage is set to the value of parameter IBV. constant. these two constants and the diode temperature define the thermal voltage. 3.38x 1022 JK1. .6x 1019 C and 1.
where TT is the average transit time of minority carriers through the narrow region of a shortbase diode. DIN' 0 1 DMOD OFF . In the smallsignal AC analysis. The depletion charge Q] at the pn junction is stored in a voltagedependent junction capacitanc~.DIODES 77 The diffusion charge QD is defined by QD = TT. C]: CJO VD/VJ)M (3.6) CD = TT. gd . and grading coefficient. other semiconductor junctions. and Schottky diodes..1 Following are the SPICE descriptions for two diodes..3) C] = (l  (3. » Table 3. such as silicon pnjunction diodes. EG.4) CJO. and M are the zerobias junction capacitance. VJ. The general format 'of the diode model statement is . EXAMPLE 3.1 summarizes the diode model parameters introduced so far along with the default values assigned by SPICE2.2) .5) (3. respectively. ID (3. RS. The scale'factor column indicates whether and how the parameter is scaled by the factor area appearing in the device statement. the diode is modeled as the conductance in the operating point gd and two capacitances CD and C] corresponding to the two charges.MODEL DMOD D . respectively. The latter is used to differentiate between different types of diodes. builtin voltage. two additional parameters needea for a' firstorder definition onhe diode model afetl'ie""parasiticseries resistance. and the energy gap. 1 dID dVD (3.MODELMODnameD <IS=IS <N=N .
also note that TT = 0.69 The above two statements define a Schottkybarrier diode. because of the absence of minority carriers.6 0. DSBD 11 17 DS1 IC=O. VCEO > The letter Q must be the first character in Qname.MODEL DS1 D IS=lP CJO=O. The junction is initialized at 0. the value ofthe voltage drop when conducting. NPN and PNP. Only default parameters are used to model DIN. area defaults to 1. Two BIT device types are supported. The schematic symbols for the two types of BITs are shown in Figure 3.11 Example IE16 1.11 Si 0.7 M=O.3 BIPOLAR JUNCTION TRANSISTORS The general form of a bipolar junction transistor (BIT) statement is Qname nc nb ne <ns> MODname <area> <OFF><IC= VBEO.3. is the substrate node. ns.33 1. 3. and its specification is optional.5 EG=O. The keyword OFF initializes the transistor in the cutoff . and ne specify the collector. The value of EG corresponds to an aluminumsilicon contact.69 Sbd 0. nc. MODname is the name of the model defining the parameter values for this transistor. the substrate is assumed to be connected to ground. The fourth number.5 100 O.4 .4 V. respectively.IN 2P 0.5 1.78 3 SEMICONDUCTORDEVICE ELEMENTS Table 3. The scale factor area is equal to the number of identical transistors connected in parallel. If ns is not present.1 Name IS N RS TT CJO VJ M Diode Model Parameters Parameter Saturation current Emission coefficient Ohmic resistance Transit time Zerobias junction capacitance Junction potential Grading coefficient Activation energy Breakdown voltage Current at breakdown voltage Units A Default 1014 I 0 0 0 I 0. Q identifies a BJT and can be followed by up to seven characters in SPICE2. nb.2P VJ=O.67 Ge 40 IOU Scale Factor area l/area area n s F V eV V A EG BV lEV 00 103 area DIN describes a protective diode at the input of another device that is normally off. base. and emitter nodes.
of the commonbase (CB) connected BJT: Ic IE Is = = cxFIF .7) where the emission coefficients (see Eq. VSEO and VCEO are used as initial values only when the UIC option is present in the • TRAN statement. These two currents satisfy the reciprocity equation (3.5. which uses diode currents IF and IR as reference: (3. The keyword IC defines the values of the junction voltages.1 DC Model The basic DC model used in SPICE to describe the BCEs of a bipolar transistor is the EbersMoll model (Muller and Kamins 1977). is the saturation current of the transistor.0 V for the DC solution.IR IF + cxRIR + (1 . with VSE = 0. a SPICE BJT model parameter.kT .10) ICE = IS(eQV8c1NR.BIPOLAR JUNCTION TRANSISTORS 79 region for the initial iterations of the DC bias solution. By default.4 is the injection version of the EbersMoll model.3. IE. CXF and CXR.cxR)IR (3. BJTs are initialized in the forward active region.1) have been assumed to equall. The currents flowing through the two sources. The injection version is commonly documented in textbooks and has been repeated above for comparison with the transport version.cxF)IF IEs and Ics are the saturation currents of the BE and BC junctions. respectively. The SPICE implementation of the EbersMoll model is a variant known as the transport version and is shown in Figure 3. 3. The three terminal currents of the transistor. VSEO and VCEOat time t = 0 for the transient analysis. The model shown in Figure 3. are chosen as reference: Icc = IS(eQV8e1NF'kT .1) . 3. and Is can be expressed as functions of the two reference currents and the forward and reverse current gains. which represent the transistor effect of the two backtoback pn junctions.6 V and Vsc = 1.1) (3. Ic.9) where IS.8) = (1 .
3 elements.80 3 SEMICONDUCTORDEVICE ELEMENTS nc (C) nc (C) !I C tIc tIE ne (E) npn tIE ne (E) pnp Figure 3.5 EbersMoll transport model of an npn transistor.4 EbersMoll injection model of an npn transistor. npn and pnp bipolar transistor C Ic vEC IE~ B IR a~R + VEE IF a~F Figure 3. . VEC IEB ICE f3R C Ic leT + + VEE Icc f3F ~ Figure 3.
and RE. The IV characteristics described by Eqs.BIPOLAR JUNCTION TRANSISTORS 81 The three terminal currents assume the following expressions: Ic = Icc .VBC' The reverse Early voltage. .6 for positive values of VBE and V CE. these resistances are modeled by parameters RC.11) IB where = f3F Icc + f3R ICE = 1 IBC + IBE ICT = Icc . has a similar interpretation for the reverse region. SPICE parameters BF and BR. of a bipolar transistor in the commonemitter (CE) configuration. Depending on the values ofthe two controlling voltages. base. This geometric interpretation of the Early effect and its SPICE implementation is shown in Figure 3. or linear.Icc f3F + 1 f3F 1 = ICT 1 . The suffixes F and R in many SPICE parameter names indicate the region of operation. VBc) plane where the extrapolations of the linear portions of all Ic characteristics meet. the transistor can operate in the following four modes: Forward active Reverse active Saturation Cutoff VBE VBE VBE VBE > 0 and VBC < 0 < 0 and VBC > 0 > 0 and VBc > 0 < 0 and VBC < 0 In most applications the transistor is operated in the forward active. For most practical applications VAF is important and VAR can be neglected. VAF and VAR.ICE f3F and f3R in the above equations are the forward and reverse current gains.11 are shown in Figure 3. RB. The finite output conductance of a BJT is modeled in SPICE by the Early effect (Muller and Kamins 1977) implemented by two parameters. ignoring the effects of finite output conductance in the forward and reverse regions and the parasitic series resistances associated with the collector. The Early voltage is the point on the VBC axis in the (Ic.ICE 1 f3R Ie = ICE .Icc f3F (3. and in some situations in the saturation region. 3. region.ICE f3R + 1 f3R = ICT . respectively. VAR.7 for the Ic = !(VCE) characteristics: VCE = VBE . These characteristics are ideal. and emitter regions. VBE and VBC.
2mA « E 200 .1mA 300 la= 2. .7 Early voltage parameter.3mA la= 400 JlA 100 o 200 400 VeE' mV 600 800 1000 Figure 3.0 mA 400 la=3...82 3 SEMICONDUCTORDEVICE ELEMENTS 500 la= 4. .. ' VAF ••I Figure 3.• () la= 1.6 BJT IV characteristics described by the EbersMoll model. VAF.
the builtin potential. X stands for E. respectively. CJ. 3. C. which defines the charge QJ. the grading coefficient. These are the diffusion charges represented by the current sources Icc and ICE in the EbersMoll model.IBc VBC VBE) I (3. are associated with the mobile carriers.8.VAF . respectively.12) 3. Eq. collector. 3.VAR . QJC.VBclVJC)MJC (3.VcS/VJS)MJS Each junction can be characterized in SPICE by up to three parameters: CJX. The other three charges model the fixed charges in the depletion regions of the three junctions: baseemitter. the zerobias junction capacitance. and MJX. VJX.ICE) ( 1 . modeled by . denoting the emitter.{3/CE = ICT .13) = TR. or substrate junction. Ic and ICT in Eqs. QDE and QDC. The diffusion charges are modeled by the following equations in the largesignal transient analysis: QDE QDC = TF. and Qcs. QJs. The nonlinear BIT model in SPICE including charge storage and parasitic terminal resistances is depicted in Figure 3. Icc (3. QJE. 3.4. which includes QDE and QJE.14) CJS (l . QBC.VBdVJE)MJE CJC (l .11 are modified as follows: Ic = (Icc . The depletion charges can be derived using the nonlinear equation that defines the depletion capacitance. which includes QDC and QJC.2 Dynamic and SmallSignal Models The dynamic behavior of a BIT is modeled by five different charges.3. The SPICE largesignal implementation of the three depletion charges is according to Eq. ICE TF and TR are the forward and reverse transit times. and collectorsubstrate. of the injected minority carriers through the neutral base. or S. The three voltagedependent junction capacitances are described by the following functions: CJE (l . of a pnjunction.BIPOLAR JUNCTION TRANSISTORS 83 With the addition of the Early voltage. Two charges.3. The five charges are consolidated into three: QBE. basecollector.
aVBC . The complete equations and model parameters are summarized in Appendix A.5 are replaced by the following linear resistances (conductances) and transconductances: gn giL gmF gmR gm 1 = Tn 1 TiL alCT aVBE go alB aVBE alB aVBC 1 dlcc f3F dVBE 1 dIcE f3R dVBc (3.8 is a firstorder representation of the complete GummelPoon BJT model available in SPICE and is sufficiently accurate for many applications.gmR alc aVBE .giL gmF . such as f3F and 'TF dependency on Ie.go nc (C) Re RB nb(B) B' VB'C' + QBe C' + VB'E' ~ IB QBE ~ Ie E' ns (8) f" RE ne (E) Figure 3.15) = = = = =  1 To alCT aVBC = alB aVBC alc . the collectorsubstrate capacitance. The nonlinear diodes and the current generator lCT in Figure 3. also known as the hybrid1T model. Figure 3. .8 Largesignal SPICE BJT model. The complete model includes secondorder effects. is shown in Figure 3.84 3 SEMICONDUCTORDEVICE ELEMENTS Ccs.9. The linearized smallsignal model of a BJT. and temperature effects. base pushout.
Vee in the second term.~ ro. can be expressed from Eqs.9 Smallsignal SPICE BJT model. ~F gm glJ. .BIPOLAR JUNCTION TRANSISTORS 85 C~ . 3.= = NF.kT (3.15 and the hybrid7T model (see Figure 3. gmFvbe qIc gm = gmF = ~Fg~ r~ =rlJ.12 and 3.= 0 VAF VAF gmVth 1 go Ie .9) as (3. terminal voltages VB'E' and VB'creplace VBEand VBC' ' The smallsignal AC collector current ie.17) 1 g~ 00. RE. The above smallsignal parameters have been derived assuming no parasitic terminal resistances Re. In the forward active region the smallsignal equations assume the more commonly known expressions (Gray and Meyer 1993): ie = gm Vbe :.' C' Re ne (C) B' nb (B) r~ C~ gmvb'e' ~ ro I • E' fa ns (8) ne (E) Figure 3.16) f where Vbe has been replaced by Vbe . andRE. if these resistances are present.
. corresponding to QBE and QBC.MODEL MODname NPNIPNP <IS=IS <BF=BF . 3..19) CM = CDC + CJc An important characteristic of a BJT is the cutoff frequency. indicating the transistor type.14.86 3 SEMICONDUCTORDEVICE ELEMENTS In smallsignal AC analysis chargestorage effects are modeled by nonlinear capacitances. fr. where the current gain drops to unity. fr can be expressed as a function of the smallsignal parameters: (3. » In every model one of the keywords NPN or PNP. (3. must be specified. QX12 14 15 21 QMOD IC = 0.9) the two types of capacitances for the BE and BC regions are consolidated in C7r and CM.MODEL QMOD NPN BF=200 RB=100 CJC=5P TF=10N .0 . Table 3.3. EXAMPLE 3. The diffusion charges are modeled by two diffusion capacitors. respectively.18) CDC = dQDC dVBC = alcT TRaVBC = TR'gmR where gmF and gmR are the forward and reverse transconductances of the BJT (Eqs.2 summarizes the model parameters introduced in this section together with the default values assigned by SPICE2.2 The following are two BJT specifications. The junction capacitances are defined by Eqs.6. 3.20) 3.3 Model Parameters The general form of the BJT model statement is . CDE and CDC: (3.5.15). In the smallsignal BJT model (Figure 3.
Defaults are used for the remaining parameters. its switching time is governed by the BC junction capacitance and the forward transit time. The measurement techniques leading to the SPICE parameters of bipolar transistors are presented in detail by Getreu (1976).6 0.5 100 250 200 2 100 IN lOON 2P 0.6 V and VCEO = 5. QFF2 is specified OFF in order to speed up the solution of the DC bias point. see Example 4.5 Scale Factor area Saturation current Forward current gain Reverse current gain Forward emission coefficient Reverse emission coefficient Forward Early voltage Reverse Early voltage Collector resistance Emitter resistance Base resistance Forward transit time Reverse transit time BE zerobias junction capacitance BE builtin potential BE grading coefficient BC zerobias junction capacitance BC builtin potential BC grading coefficient CS zerobias junction capacitance CS builtin potential CS grading coefficient V V 11 11 11 s s F V F V F V 0 0 0 0 0 0 0. The same measurements can be used to characterize discrete transistors if lab equipment and the transistor of interest are available. model parameters must be derived. A different approach is necessary for discrete .MODEL QQ PNP IS=lP BF=50 CJE=lP CJC=2P QFFl and QFF2 are the two transistors of a flipflop. For more detail on flipflop initialization. This topic is addressed in the following pages. The characteristics of IC transistors are derived from a test structure built on the same wafer. Generally.8.5 2P 0. QFFl 1 3 0 QQ QFF2 2 4 0 QQ OFF .33 0 0.6 0.75 0. 6). and how the SPICE parameters can be derived for physical transistors becomes an important question.BIPOLAR JUNCTION TRANSISTORS 87 Table 3. For some standard parts SPICE parameters are available from semiconductor manufacturers because of the widespread use of SPICE simulation in circuit design. however.2 Name IS BF BR NF NR VAF VAR RC RE RB TF TR CJE VJE MJE CJC VJC MJC CJS VJS MJS BJT Model Parameters Parameter Units A Default 1016 100 I I I 00 00 Example lEI6 80 3 2 1.33 0 0.75 0 I/area I/area I/area area area area QX12 is initialized at VBEO = 0.75 0.33 2P 0.0 V in a transient analysis (see Chap.6 0.
3. ON. and switching characteristics. Is. under electrical characteristics. provided as minimum or maximum values.015. Choose hFE1 = 150 at Ie = 1 rnA hFE2 = = 200 at Ie 240 at Ie = = 10 rnA 100 rnA = hFE3 The average of these three values results in BF 190. Eqs.3 Derive the SPICE DC model parameters for the MPS2222 npn transistor. When graphs are available. VSEsat. IS. and VSEsat by substituting the current ICE from the Is equation into the Ie equation.14. Choose Ie = 150 rnA and the resulting VSEsat = 0. as a function of Ie for a set ratio lei Is. . an average value should be chosen for hFE over the Ie range that the transistor is expected to operate. we obtain the BE voltage in saturation. the current gain factor. 1015 A (3.should be used as primary sources of characteristic data. In addition to these data. equal to 10 for this transistor. EXAMPLE 3.2). Because BF is a constant and because hFE dependence on Ie is not supported in the firstorder model. similar to a 2N2222. This can be obtained from the plot of the DC current gain. 3. we derive a value for BF. hFE. because the graphs represent a typical device. From the graph entitled ON Voltages. Figure 3. many transistor data sheets contain graphs of several electrical quantities.5. This approximation is of no consequence unless the transistor is operated in the reverse region most of the time. or BR = 1. Simulate the Ie = f(VeE. Obtain from Eqs.10.88 3 SEMICONDUCTORDEVICE ELEMENTS transistors when the only information available is a data sheet. Next. The first parameter to be extracted is the saturation current. namely the OFF.11 a relation between Ie. The extraction of the main parameters from a data sheet is outlined in the following example. Solution The information needed for extracting the model parameters is found in the MPS2222 data sheet. as a function of Ie.0258 = 1. Several categories of characteristics are included. they .21) Is In the above calculation it has been assumed that CXR = 0.10 are then used with N F = 1 to obtain the following expression for IS: IS = Is (Ie + _l_)eVBEsat/Vth 1CXR = 0. which is the default value in SPICE (see Table 3. Use the Motorola Semiconductors Data Book (Motorola Inc. smallsignal. 1988) for electrical characteristics. Is) characteristics with SPICE.85 V. 12eO.85/0.
1 2 CASE 2904.0 Vde. 'E = 0) (VCB = 50 Vde.10 MPS2222 data sheet.4 0. TA = 55'C) (lC = 150 mAde.A. Figure 3.) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS CollectorEmitter Breakdown Voltage (lC = 10 mAde. IE = 0) EmitterBase Breakdown Voltage (IE = 10 ~de. VCE = 10 Vde)(1) (lC = 150 mAde. Tstg MPS2222 MPS2222A 30 60 5. VCE = 10 Vde) (lC = 1. VCE = 10 Vde. IE = 0. A* CollectorEmitter Voltage CollectorBase Voltage EmitterBase Voltage Collector Current  Total Device Dissipation @TA = 25'C Derate above 25'C Tota' Device Dissipation @ TC = 25'C Derate above 25'C Operating and Storage Junction Temperature Range THERMAL CHARACTERISTICS Characteristic Thermal Resistance. VEBloffl ON CHARACTERISTICS = =   125'C) 125'C)  0. 89 . VEB(offl V(BR)CEO MPS2222 MPS2222A V(BR)CBO MPS2222 MPS2222A V(BR)EBO MPS2222 MPS2222A ICEX 3.01 0. Junction to Ambient 'c . IE = 0.0 6. IC = 0) Collector Cutoff Current (VCE = 60 Vde. IE = 0) (VCB = 60 Vde. VCE = 10 Vdel (lC = 10 mAde. 'B = 0) CollectorBase Breakdown Voltage (lC = 10 ~de. IC = 0) Base Cutoff Current (VCE = 60 Vde.0 60 75 30 40   Vde 10 Vde Vde =  nAde ~de Collector Cutoff Current (VCB = 50 Vde. VCE = 1.0 Vde) MPS2222A 5.:~"=' 1 Emitter 3 Symbol ReJC ReJA Max 83.0 600 625 5. VCE = 10 Vde)(1) CollectorEmitter Saturation Voltage(1) (lC = 150 mAde.0 1.3 200 Unit GENERAL PURPOSE TRANSISTORS NPN SIUCON 'c/w 'c/w ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted.0 Unit Vde Vde Vde mAde mW mWrC Watts mWrC MPS2222. IB = 15 mAde) hFE 35 50 75 35 100 50 30 40 VCE(sat) MPS2222 MPS2222A MPS2222 MPS2222A MPS2222A only    300 MPS2222 MPS2222A Vde 0.0  (lC = 500 mAde.5 12 55 to + 150 40 75 6. Junction to Case Thermal Resistance.0 Vde)(1) (lC = 500 mAde. 'B = 50 mAde)  • Also available as a PN2222. VCE = 10 Vde) (lC = 10 mAde.1 mAde.0 mAde.3 1.0 Vde) MPS2222A ICBO MPS2222 MPS2222A MPS2222 MPS2222A lEBO MPS2222A IBL 3. STYLE 1 TO92 (TO226AA) . TA (VCB = 50 Vde.01 10 10 10 20 nAde nAde =  DC Current Gain (lC = 0. TA Emitter Cutoff Current (VEB = 3.6 1.MAXIMUM RATINGS Rating Symbol VCEO VCBO VEBO Continuous IC Po Po TJ.
6 2. +30 DUTY v 200 CYCLE"'2% _l_ T:Cs. IC = 150 mAde. IC 8.25 8. .TURNON TIME +30 200. f = 1. lk lN914 .0 kHz) (lC = 10 mAde.0 kO.0 mAde. VCE = 10 Vde. <20n5 :Cs.0 kHz) Collector Base TIme Constant (IE = 20 mAde.0 kHz) (lC = 10 mAde.S. (2) IT is defined as the frequency at which Ihfel extrapolates to unity. TIME EQUIVALENT TEST CIRCUITS FIGURE 2 . f = 100 MHz) Output Capacitance (VCB = 10 Vde.0 30 25 MHz  pF pF = = 0.3 1. f = 1. VCE = 10 Vde.TURNQFF TIME v _I 1+16V~ 0 1.0 0. VCE = 20 Vde. VCB = 20 Vdc.0 1. IB = 15 mAde) 0. f = 1. VCE = 10 Vde. f = 1.6  (lC = 500 mAde.90 (continued) . f = 1.Duty Cycle'" 2.0 ps dB 50 75 300 375 ILmhos 2. SWITCHING FIGURE 1 .5 Vde. VCE = 10 Vde.0 kHz) Voltage Feedback Ratio (lC = 1.4 V . VCE = 10 Vde. ___J < 10 pF Scope < 4 ns Total . RS = 1.0 kHz) SWITCHING CHARACTERISTICS MPS2222A only Delay TIme Rise Time Storage Time Fall Time k{}     (VCC = 30 Vde.0 Unit Vde BaseEmitter Saturation Voltage(1) (lC = 150 mAde.5 Vde.". IB = 50 mAde) IT SMAllSIGNAL CHARACTERISTICS MPS2222 MPS2222A Cobo 250 300 CurrentGain .ELECTRICAL CHARACTERISTICS (continued) (TA Characteristic = 25°C unless otherwise noted. f = 1. f = 1. f = 31. f= 1.0 4.hunt capacitance of test connectors. IB1 = IB2 = 15 mAde) (Figure 2) td tr ts tf 10 25 225 60 ns ns ns ns (1) Pulse Test: Pulse Width'" 300 /LS.0 kHz) Output Admittance (lC = 1. .0 kHz) SmallSignal Current Gain (IC = 1. IB1 = 15 mMe) (Figure I) (VCC = 30 Vde. f = 1.0 0.25 X 104 8. VCE = 10 Vde. VBE(off) = 0. Figure 3.0 mAde. and oscilloscope. .Bandwidth Produet(2) (lC = 20 mAde.2 2.8 MHz) Noise Figure (lC = 100 !LAde. VCE = 10 Vde. IE Input Capacitance (VEB = 0. VCE = 10 Vde.0 mAde. IC = 150 mAde.10 .0 kHz) (lC = 10 mAde.0 MHz)   Input Impedance (lC = 1.0 MHz) Cibo MPS2222 MPS2222A hie MPS2222A MPS2222A hre MPS2222A MPS2222A hfe MPS2222A MPS2222A hoe MPS2222A MPS2222A rb'Ce MPS2222A NF MPS2222A 5.0 kHz) (lC = 10 mAde.) Symbol VBE(sat) MPS2222 MPS2222A MPS2222 MPS2222A Min Max 1.0 mAde.0 25 35 200 150 4.0 to 100 . f = 1. f = 1.0%. ___ J _L_ < 10pF Rise Time 14 V  I jig. VCE = 10 Vde.
0 5.0 10 20 30 50 70 100 200 300 500 IC.. 20 3.0 k IC.• '" .....0 10 20 30 50 IS.05 0..:: •.. COLLECTOR CURRENT (mAl FIGURE 4 .•..11/S If If): ~~~c 1"'_ g w 30 20 10 7..••..0 V_ 'd@lVES(off) = 0 100 c w FIGURE 6 . 200 10 ..5 0....~50C ..0 10 20 30 50 70 100 .S 0. IC.. I  ~ c ~ I I .1 i"...01  \ I' 0.4 1\ \ \ 500 rnA \ \ \ 0.0 2. SASE CURRENT (mAl FIGURE 200 5 .0V VCE=10V I I I I III 7.0 5..0 5..... 300 500 7..0 5...3 0..0 7..2 o 0..•.•. ..0 . COLLECTOR CURRENT (rnA) ... COLLECTOR CURRENT (rnA) Figure 3..••.....COLLECTOR SATURATION REGION TJ = 25°C 1.. 2...l 25°C 3 .:: II .. .0 3..MPS2222.3 0..1 I '.03 0.. I •.10 (continued) 91 ...0 2.0 5.0 1\ ....0 rnA lOrnA 150mA 0...... .7 1. " I •••••• 70 50 30 '" .TURN'()N TIME ICIIS = 10 TJ = 25°C 500 300 200 '.••• "'7'" 0..6 l IC = 1.TURN'()FF TIME VCC = 30 V IC/IS = 10 100 70 50 t'.2 0.0 VCE=1..DC CURRENT GAIN •• •..0 3.2 0.005 0..5 1. A FIGURE 1000 700 500 TJ=1250C I .02 0..0 5.... ..0 O. .1 0.!" .0 7.0 10 20 30 50 70 100 200 300 500 700 1....@l VCC = 30 V 'd@lVESloffl = 2.. '" '" B u z 300 200 100 70 50 30 20 10 0..I.•..
SOURCE RESISTANCE 10HMS) FIGURE 9 .0 7. .01 0.0 FIGURE 12 .0 II . V8Elon)@VCE = 10 V ~ .: w 1\ l/ )' ~ 50 100 500 ..0 10 II 20 50 100 200 500 0. 10 7. 0.0 3.1 11111 0.0 5.0 :> <. A FIGURE 7 .0 RIN8forV8E .0 2.0 V 0..0 10 20 50 100 200 500 1.0 10 20 50 100 I.2 VCElsat) r./ 10k 20k 50k 100. '' .A '" .A 1. c5 .0 2.: ~ o 4.•.5 2.0 V / 1/ J J / I I I j IC=50.0 5.0 10 20 30 50 70 100 IC.0 2. COLLECTOR CURRENT ImA) FIGURE 11 .b + I t. 3: z '/ " .0 2. 200 500 1.1.0 I I 10 20 30 REVERSE VOLTAGE (VOLTS) 50 1.5 1.. > >' . 0. rr C. COLLECTOR CURRENT (mA) IC.0 w ~ <..2 0.0 5.0 3...0k 5.5 1. FREQUENCY 1kHz) RS.0 .05 0. ~ w <.GAIN BANDWIDTH PRODUCT ~ I I .. . '' 0. :> VCE = 20 V TJ.. .0 2.0 0 z ~..0k 2.0 1..10 (continued) 92 .TEMPERATURE COEFFICIENTS +0.0k .0 ~H~ I III II 1111 8. 0..1 0.0 'IOO.t'1J.2 0. .. ~ w 8.1 0..0 5..5 1. z 2.250C 300 200 I I ~ ~ w Z g g: or :.02 o a 0.0 5.2 0.MPS2222. COLLECTOR CURRENT (mAl Figure 3..CAPACITANCES 30 20 FIGURE 1Q .0 Ccb r.5 III I RINCfor VCElsatll ~ ~ ~ Il 0.3 0.::.o IC/18' 10 2.A 6.6 ~ E :.0 k IC..0 1/ ".::.0 0.0mA I '" 4.•• .2 0. '' ~ .4 f:: w c I.5 1.CURRENT.0 ./ / 100 1/ 70 ~ / '" ~ '" '" B ~ 50 3.FREQUENCY EFFECTS 10 10 FIGURE 8 .. z 2.SOURCE RESISTANCE EFFECTS II 1111111 t.0 z ~.0 5..0 2.5 1. c z .8 '" ':.5 o 0."ON" VOLTAGES 1.1 0.0 ~ 6.
V CE curves intersect at V CE = . Then VAF is computed from geometric considerations.V CE curve at the measured Ic and V CEo Ideally the extrapolations of the two tangents to the Ic. Both a minimum and a maximum value are listed for two values of Ic. We have now obtained the main BJT SPICE parameters for simulating the DC behavior of transistor MPS2222.OP . or hybrid parameters. VAF.PRINT DC I (VCl . which are given as h parameters.VCE = 102• 106 mho . h fe. A reasonable estimate for VAF is obtained by first choosing a value between Min and Max for hoe at the higher current.25E14 BF=190 VAF=100 RC=3. For a transistor in a CE configuration.4 RB=37 . and hoe.075M VC 2 0 10 * * * * * * PARAMETERS DERIVED BY HAND WI TYPICAL VALUES FROM GRAPHS *. The smallsignal value of hoe is the slope of the Ic. VAF = hoe . The setup is shown in Figure 3. The corresponding SPICE input follows: IV CHARACTERISTICS OF 2N2222 Q1 2 1 0 Q2N2222 IE 0 1 . The hybrid model is based on a twoport representation of the transistor with iin and Vo as the independent variables. we can describe a measurement setup for displaying the I c. hre. if this current is not outside the range of the application.DC VC 0 10 0. 1 rnA and 10 rnA.9M .10 V Ic 102 A = 100 V The data for hoe are measured at V CE = 10 V. as in Figure 3.14F BF=190 VAF=100 * WI MAX VALUES.7. With the information presented so far about SPICE.END . Vin and io relate to iin and Vo through the hybrid parameters hie. This parameter can be calculated from the smallsignal characteristics.11.MODEL Q2N2222 NPN IS=1.4M 4M 0.22) hoe is the data sheet parameter used for evaluating VAF.BIPOLAR JUNCTION TRANSISTORS 93 The next parameter to be evaluated is the Early voltage for forward operation.VAF.V CE characteristics of the BIT.MODEL Q2N2222 NPN IS=5.7. A transistor can therefore be described by the following hybrid equations: Vin + hrevo io = hfeiin + hoevo = hieiin (3. as shown in Figure 3. NO GRAPHS .5 IB 0.
A slightly different approach must be followed if no graphs are available and all parameters must be derived from the electrical characteristics data. Note that the different curves are equally spaced in the firstorder model based on a constant value of h FE. the difference in VBEsat can be attributed in large part to the voltage drop across the parasitic base resistance. this statement is described in detail in the following chapter.23) Similarly. These values are too high for following the extraction procedure outlined above. The plot of the Ic = f(VCE. RB.4M 4M 0. RC. the validity of the model can be verified for a few operating points given in the data sheet.DC VC 0 10 0.2 V 0. The two maximum values.35 A = 3.3 V 0. I B) characteristic is available from the data sheet for comparison with the above simulated curves.40 (3. IB) characteristics simulated by SPICE with the above parameters is shown in Figure 3.11 Measurement setup for !c. resulting in a resistor value RB = VBEsatMl IBI  VBEsatM2 IB2 1.24) The approximation of attributing the VBEsatM difference to an ohmic voltage drop is supported by the fact that it takes approximately only VBE = Vth = 26 mV to increase IB from 15 rnA to 50 rnA.12. The difference in VCEsatM for the two values of Ic can be attributed to the ohmic collector resistance.5 IB 0.9M which defines the range over which the VC supply and the base current source IB are swept. the value of which is RC = V CEsatMl  V CEsatM2 ICl .IC2 1. .035 A r\ = 37 H (3. are obtained from the saturation characteristics. VCEsatM and VBEsatM.VCE characteristics. No I C = f (V CE.94 3 SEMICONDUCTORDEVICE ELEMENTS Figure 3. equal to BF. The only statement that has not been defined so far is .
1013 A 5. The three characteristic parameters of a junction capacitance. Choose hFEI in the range between Min and Max. BF can be estimated from the ON characteristics table. is estimated from the latter. I (VCE.1014 A In the absence of the DC current gain plots. The junction capacitances. are derived from the former characteristics. RC' IBI ICI = 0. In) characteristics of the MPS2222 npn transistor simulated Now IS can be derived from Eqs. Calculate hFE2 and hFE3 at two other values of Ic such that they represent the same multiple of the corresponding minimum values as hFEI• BF results as the average of the three midrange values of hFE: BF = 110.0 IB = 2.5.10 and 3.12 by SPICE.25.69 V = = VCEsatMI = = = ICleVBEsatM/Vth 0. .0 IB=1.0 IB=400~A 200.. which lists the minimum values of hFE for several values of Ic.3mA •.15.0mA IB=3.1mA 600. The chargestorage characteristics can be derived from the plots of capacitances versus reverse voltage and switching characteristics.74 V 0. the highest.BIPOLAR JUNCTION TRANSISTORS 95 IB=4. Usually both a minimum and a maximum hFE value are given for a single Ic value.0 o Ic = 10 Figure 3. The extraction ofVAF is the same as the above. CJC and CJE. 3.3. closer to the minimum.• v 200.11 and the corrected values of and V CEsatM: VBEsatM VBEsatM VCEsatM IS = VBEsatMI  RB. and the transit time.2mA 4: E 400. TF.
MlX. J identifies a JFET and can be followed by up to seven characters in SPICE2. VDSOand VGSOare used as initial values only when the UIC option is present in the • TRAN statement. Two JFET models are supported. The schematic representations of the two types of JFETs are shown in Figure 3. ng.14. see Eqs. area is a scale factor equal to the number of identical transistors connected in parallel.. from MicroSim Corp. Another parameter extraction package. gate. nchannel (NJF) and pchannel (PJF). from Symmetry Design Systems (1992).3333 FC=.03 ON * W/ VALUES FROM GRAPHS OR AVERAGED * . Parts finds the following DC parameters using typical data: * Q2N2222 MODEL CREATED USING PARTS VERSION 4.and highcurrent behavior. 3.2 are present in the above. with VGS = VTO and VDS = 0. 78P IKF=3. 837 VJC=.3333 VJE=. nd.4 JUNCTION FIELD EFFECT TRANSISTORS (JFETS) The general form of a junction field effect transistor (JFET) statement is Jname nd ng ns MODname <area> <OFF> <IC= vDSO. The package Parts. respectively. The keyword IC defines the values of the terminal voltages.MODEL Q2N2222 NPN(IS=15. which is a straight line. VDSO and VGSO. MODEL statement because Parts uses the complete GummelPoon model in the extraction.01F XTI=3 EG=1.348 IKR=O RC=O CJC=2P TR=10N TF=1N XTB=l. and source nodes.12. area defaults to 1. and ns are the drain. computes SPICE parameters for all the supported semiconductor devices from data book characteristics. MODname is the name of the model that defines the parameter values for this transistor. should be evaluated from a plot of log Cj versus I (Vj).11 VAF=90. t time t = 0 in a timedomain a analysis.75 A number of parameters that are not in Table 3.75 MJC=. For transistor MPS2222.13.96 3 SEMICONDUCTORDEVICE ELEMENTS ClX.0 for the DC solution. MODPEX.7 NE=2. ' The above parameter extraction approach can be automated by writing a small program for repeated use. can scan a data sheet and generate SPICE parameters. The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution.vGso> The letter J must be the first character in lname. = I (VCE. 5 BR=1 NC=2 ISC=O MJE=. . Secondorder effects can be added. JFETs are initialized at the threshold voltage. such as low. By default. ~" ~ Exercise Verify that the parameters from Parts result in Ic to those in Figure 3.5 CJE=5P ITF=O VTF=O XTF=O) 08/02/91 AT 13:59 BF=223. and VlX. IB) characteristics similar 3.7 + + + ISE=70.
respectively. Note that LAMBDA is measured in VI and is equivalent to the inverse of the Early voltage for the BJT. the transconfactor.VGD/PB)O.26) VTO. OD. ductance CGS (l . The drainsource current. introduced in Sec. and output conductance factor in saturation. and linear. is defined by the following three equations for the three regions of operations. respectively: a for V GS ::::.3. The dynamic behavior of a JFET is modeled by two charges associated with the gatedrain. The gate pn junctions are reverse biased. cutoff. VT 0 I_BETA DS  { BETA. characterized by the saturation current IS. VDS VDs(2(VGS . The current IDs flows in the opposite direction. saturation. The quadratic ShichmanHodges model (Shichman and Hodges 1968) is used in SPICE to solve the BCEs. IDs. VGS is replaced by VGD. These charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eq. There is an additional current component due to the pn junction current.5 (3. junctions. VDS) fora < VDS < VGS . BETA. VDS) fora < VGS .13 n. OS.VTO (3.1. (VGS .25) are the threshold.VTO)2(l + LAMBDA.VTO::::.VDs)(l + LAMBDA.5 . If VDS changes sign. and VDS is replaced by its absolute value in the above equations.JUNCTION FIELD EFFECT TRANSISTORS (JFETS) 97 nd(D) t ng (G) IDS + ns (8) nchannel ns (8) pchannel Figure 3. respectively. 3.VGs/PB)O. voltage. and therefore the pn junction current is negligible. the behavior of the JFET is symmetrical.VTO) . or pinchoff. the drain and the source swapping roles. and gatesource. and LAMBDA CGD (l .and pchannel JFETs. The above equations are valid for VDS > O.3. 3.
26.98 3 SEMICONDUCTORDEVICE ELEMENTS CGS.15.14 and the smallsignal model in Figure 3.14 Largesignal nchannel JFET model. and PB are the zerobias gatesource capacitance.s' must be used in Eqs. 3. These capacitances are used in the smallsignal analysis. In the largesignal timedomain analysis the gate charges are computed from Eq. 3.o the region of operation (Eqs.27) dIDs dVDs gds VGS and VD. CGD.26. and builtin gate junction potential. 3. The transconductance gm and the drainsource resistance rds of the smallsignal model are defined as follows: gm = = dIDs dVGS 1 rds (3.27 when RD and RS are nonzero.25. nd(D) ns (8) Figure 3.25) must be used when deriving gm and rds' Note that in nOmlal operation the GD and GS diodes are reverse biased and the corresponding smallsignal conductances can be neglected.4 using Eqs. The expression of IDS appropriate t. and 3. zerobias gatedrain capacitance. The largesignal JFET model is shown in Figure 3. . 3. 3. respectively.
with the corresponding default values assigned by SPICE2. voltage. in other words.15 Smallsignal JFET model. Table 3. must be specified.6 1. This discrepancy is present in SPICE3 as well as PSpice. the sign of VTO for a depletion pchannel JFET should be entered as negative. indicting the transistor type.0E4 100 100 5P IP 0. The general form of the JFET model statement is •MODEL MODname NJF/PJF <VTO=VTO <BETA=BETA ..0 104 0 0 0 0 0 1 1014 Example 2. VTO. is signsensitive.0E3 1. VTO for a pchannel JFET is defined with the same sign as for an nchannel JFET.16 Scale Factor area l/area l/area area area area n n F F Y A .3 summarizes the model parameters introduced so far. however. they are normally on.. Therefore VTO is negative for nchannel devices (NJF) and should be positive for pchannel devices (PJF). or pinchoff.3 Name YTO BETA LAMBDA RD RS CGS CGD PB IS JFET Model Parameters Parameter Threshold (pinchoff) voltage Transconductance parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zerobias GS junction capacitance Zerobias GD junction capacitance Gate junction potential Gate junction saturation current Units Y AYZ yI Default 2. Because of a bug in all recent versions of SPICE2.5 1. » In every model statement one of the keywords NJF or PJF. The threshold. Table 3. that is.JUNCTION FIELD EFFECT TRANSISTORS (JFETS) 99 D' nd(D) ns (S) Figure 3.0E. JFETs operate in depletion mode.
the commonsource output admittance in the data sheet: gds = BETA . The threshold. 3. and therefore the transistor is saturated.27. A normallyon pchannel JFET that conducts the same current as Jl in similar bias conditions is described by the following MODEL statement: .VTO = 3. BETA is computed as a function of !DSS' BETA = .100 3 SEMICONDUCTORDEVICE ELEMENTS EXAMPLE 3. !DSS (VGS .VTO)2 = Yos (3. VGS(off).4 J1 20 1 21 Mom . according to Eqs. For the 2N4221 this value. !DSS' The measurement in the data book is taken at VDS = 15 V.28) . the value is VTO = VGS(off) = 3.327 rnA V !DSS has been set at 4 rnA.VTO)2 4mA (3. the smallsignal DS conductance. the channel modulation parameter. or pinchoff. is readily available from the commonsource transfer characteristics plot. 3. MODEL Mom NJF VTO=. This value is obtained from equating the expression of gds.3 RD=20 RS=20 Jl is a normallyon nchannel JFET with parasitic series drain and source resistances.25: VGS . is referred to as the gate source cutoff voltage.5 V)2 2 = 0. .The last parameter of importance for DC is LAMBDA.LAMBDA(VGS .5 Derive from the Motorola semiconductor for the 2N4221 nchannel JFET. data book the SPICE DC model parameters Solution As in Example 3. which measures the output conductance in saturation.3.25.MODEL Mom PJF VTO=3 RD=20 RS=20 EXAMPLE 3. to Yos.5 V < VDS From Eqs. which is the average between the minimum and maximum values provided by the data sheet. The transconductance parameter BETA can be obtained from the zerogatevoltage drain current. we choose to derive the SPICE parameters from graphical data if such graphs are available. VTO.5 V. voltage. in the data book. 3. defined by Eqs.
and bulk nodes. 3.6. M identifies a MOSFET and can be followed by up to seven characters in SPICE2. 103 A 5 = IDss 25. ns. for computing the f(VDS.16. MODname is the name of the model that defines the parameters for this transistor.4. in the following chapter. vcso. the bulk terminal is often nd(D) t nd(D) IDS t nd(D) IDS nd(D) iDS + VDS ng(G)~ Vcs ng(G)~ Vcs + VDS nb (8) ng(G)~ Vcs t + + ns (5) t ng(G)~ Vcs iDS VDS VDS nb (8) + + ns (5) ns (5) nchannel ns (5) pchannel Figure 3. and nb are four numbers that specify the drain. . Note that a MOSFET can be represented either as a fourterminal or threeterminal device. respectively.16 n. 103 . nd. Mname nd ng ns nb MODname «L=>L> «W=>W> <AD=AD> <AS=AS> + + <PD=PD> <PS=PS> <NRD=NRD> <NRS=NRS> <OFF> <IC=VDSO. The schematic representations for the two types of MOSFETs are shown in Figure 3.15 for JFETs. ng. gate. VI ID These values are used in Example 4. The details of the MESFET models can be found in Sec. VBSO> The letter M must be the first character in Mname. 3. = SPICE3 and PSpice additionally support a metalsemiconductor FET. source. which can be checked against the characteristics in the data book.mho 4. MESFETs can be represented by the same models as those shown in Figures 3.14 and 3. Two MOSFET models are supported. or MESFET. Vcs) characteristics.5 METALOXIDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) The general form of a metaloxidesemiconductor field effect transistor (MOSFET) statement is . nchannel (NMOS) and pchannel (PMOS).and pchannel MOSFET elements.METALOXiDESEMiCONDUCTOR FiELD EFFECT TRANSISTORS (MOSFETs) 101 and LAMBDA = Yas 10.
NRD and NRS are the equivalent number of squares of the drain and source diffusions. The key letters Land Ware optional. the LEVEL = 1 model. are described in Appendix A and references (Antognetti and Massobrio 1988. in the computation of the drainbulk (DB) and sourcebulk (SB) junction capacitances. VGSO. Vladimirescu and Liu 1981). alternatively. where the operations of the memory cell. in the computation of the DB and SB junction sidewall capacitances. NRD and NRS multiply the sheet resistance. In SPICE2 the defaults for PD and PS are zero. CJ is a model parameter defined by model MODname.5. 3. PD and PS multiply the sidewall bulk junction capacitance per meter. in that order. which incorporate secondorder effects. AD and AS are the areas.5). with VGS = VTO. VGSO. VDSO. By default MOSFETs are initialized cutoff at the limit of turnon. Default values can be defined as DEFL and DEFW in an • OPTIONS control statement (see also Section 9. Note that the following parameters are used only for the very accurate modeling of MOS ICs. in SPICE2 the defaults of the two areas are each 100 /Lm2. Default values can be set at DEFAD and DEFAS in an • OPTIONS statement. VDS = 0. if they are omitted. of the drain and source diffusions of the MOSFET. in meters. and VBSO are used as initial values only when the UIC option is present in the • TRAN statement. This detail of geometry specification is not necessary for firstorder analysis. RSH.1 DC Model The most basic MOSFET model used in SPICE to describe the static BCEs of a MOSFET. the two values that follow MODname are interpreted as length and width. . The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution. in the computation of the parasitic drain and source series resistances. such as RAMs. The keyword IC defines the values of the terminal voltages. It is recommended to set either Land W or DEFL and DEFW. CJSW. respectively. The defaults for NRD and NRS are 1. and VBSO at time t = 0 in a timedomain analysis. because all nchannel transistors have the bulk connected to the most negative voltage and all pchannel transistors have the bulk connected to the most positive voltage. and decoders need to be predicted reliably. AD and AS multiply the bulk junction capacitance per square meter. in square meters. for the DC solution. sense amplifiers. More complex SPICE MOSFET models. and VBS = 1. the threshold voltage. CJ. respectively. Land Ware the length and width of the conducting channel beneath the gate. VDSO. PD and PS are the perimeters of the drain and source diffusions in meters.5.0. between source and drain. is the quadratic ShichmanHodges model (Shichman and Hodges 1968). other SPICE versions may differ in the values assigned to these defaults.102 3 SEMICONDUCTORDEVICE ELEMENTS omitted. Up to eight geometry parameters can be specified for each MOSFET. The SPICE2 builtin defaults for Land Ware 1 m.
similar to the JFET model. or. surface mobility.LD is the effective channel length corrected for the lateral diffusion. transconductance factor. IDs. due to the pnjunction current. saturation.VTH (3. the behavior of the MOSFET is symmetrical. IS.5. JS. For a MOSFET the transconductance factor KP depends both on the device geometry. forO VDS) < VDS < VGS .VTH) . and linear.2 Dynamic and SmallSignal Models The dynamic behavior of a MOSFET is governed by the charge associated with the gateoxidesemiconductor interface and by the charges associated with the drain and source diffusions.VTH) (l 2 + LAMBDA. and output conductance factor in saturation. KP. characterized by the saturation current. Wand L. by its density. PHI . For a pchannel MOSFET the same current equations apply.VBs .J2. bulk threshold parameter. 3. and VDS is replaced by its absolute value in the above equations. PHI. the drain and the source swapping roles: VGS is replaced by VGD. .0. There is an additional current component. and thinoxide thickness.VDs)(1 efj + LAMBDA. PHI) (3.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 103 The drainsource current. VBS < 0. and the process characteristics. the absolute values are used for the terminal voltages and the current flows in the opposite direction. If VDS changes sign. of an nchannel device is defined by the following three equations for the three regions of operations cutoff. surface potential. equivalently.VTH VDS 2L KP W VDs(2(VGS . The drain and source pn junctions are reverse biased. VTO. VTH :5 IDS = 2 (VGS Lefj . and therefore the pnjunction currents are negligible in a firstorder analysis.29) whereLefj = L2.30) is the threshold voltage in the presence of backgate bias. The above equations are valid for VDS > O. VDS) for 0 < VGS . and LAMBDA are the electric parameters of a MOSFET model. LD. is generally applicable to FETs with minor changes to account for the specifics of each device category. respectively: o KP W for VGS ::s. This model. representing the threshold voltage. GAMMA. of the drain and source. respectively. VBS is replaced by VBD. The current IDs flows in the opposite direction. and VTH = VTO + GAMMA ( J2.
CCB = CoxWL CCB = 0 for Vcs :::. and CCB. VTH forO Ccs = ~Cox WL.VTH:::. and CGBO should be used to describe the actual overlap of the drain. The actual gate capacitances. These charges are voltagedependent. CCB = 0 for 0 :::. 3. and a bulk charge.33) CCD = Ccs = !CoxWL. is specified. For a firstorder model it can be assumed that the three MOS charges are associated with three constant capacitors. This distinction is especially important in smallsignal frequency analysis. and CGBO. beyond the channel.31) For a firstorder analysis the constant gate capacitances itances approximated by CGDO CGBO = are specified as overlap capac CGSO 0 = ~CoxL (3. CCD.V DS < Vcs . Ccs.VTH The definition of the overlap capacitances needs to be changed when voltagedependent capacitances are used. are computed i~ SPICE by multiplying CGDO by W. and bulk by the gate. the GS overlap capacitance per unit channel width. 3.104 3 SEMICONDUCTORDEVICE ELEMENTS Three distinct charges can be identified on the plates of the MOS capacitor: a gate. This capacitance has an important effect on the bandwidth of an MOS amplifier. source. respectively. For analog circuits a more careful evaluation of CGDO is necessary. The thinoxide capacitance per unit area is defined by C ox = EoxEO TOX (3. < Vcs . Details on the gate charge and capitance formulations can be found in Appendix A. CCD = 0. CGSO. a channel. CGSO. respectively. The above approximation is appropriate for digital circuits. and TOX is the thinoxide thickness. and CGBO by L. represented by CGDO. It is recommended to set it to zero for a transistor biased in saturation and to the value given in Eqs.32) = where Eox and EO are the permitivities of Si02 and free space. CGDO.17 by specifying TOX in the •MODEL statement. the GB overlap capacitance per channel length. It is preferable to let SPICE use the voltagedependent capacitances shown in Figure 3. The three gate capacitances used by SPICE are computed by adding the capacitances in Eq. Voltagedependent capacitances are always computed for the LEVEL = 2 and LEVEL = 3 models. CGSO by W. TOX. the GD overlap capacitance per unit channel width.32 for a transistor in the linear region. VDS (3. variable gate capacitances are computed for a LEVEL = I model only if the value of the thinoxide thickness parameter. In the three regions of operation the three capacitances are CCD = Ccs = 0.33 to the respective overlap capacitances: .
SPICE2 provides the means for an accurate specification of the junction capacitance for each device geometry and diffusion profile. CGDO CGBO = = CGSO = !CoxLD (3. and the junction grading coefficient.17 MOSFET gate capacitances per unit channel area versus VGs. The depletion charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eqs.35) where CBD. The design of LSI and VLSI circuits requires the most accurate representation of the actual physical realization of the circuit.V Figure 3.VBS/ PB)MJ (3. and a sidewall junction capacitance per unit length.VBD/ PB)MJ CBS (l . and Wov is the gate width extension beyond the channel.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 105 o 14 VCS. one can omit the overlap capacitances when voltagedependent gate capacitances are used in LEVEL = 1. PB. . CBS. C fox is the fieldoxide (isolation) thickness. the builtin bulk junction potential. The DB and SB junction capacitances have a great impact on the operation speed of an IC. Both drain and source junction can be characterized by a bottom junction capacitance per unit area. the zerobias bulksource capacitance.3: CBD = CBD (l . 3. in which case one of the more accurate models presented in Appendix A is recommended. CJ.34) C foxWov where LD is the length of the gate extension over the drain and source diffusions. and MJ are the zerobias bulkdrain capacitance. Unless a very accurate simulation is needed.
and PS. introduced above. 3. the DB and SB junction capacitances can be expressed as CBD CBS = = o . which can make the sidewall contribution the dominant junction capacitance.36) AS .VBDj PB)MJ AD. 3. AS. PD.36. and the geometryoriented specification are available. CBD or CBS.19. The nonlinear current generator IDs is replaced by the resistance r ds and transconductances gm and gmbs de nd(D) ng (G) IDS VBD. CJ + PD. . CJ PS .VBDj PB)MJSW (3.4 using Eqs. CJSW OvBsjPB)MJ+ OvBsjPB)MJSW Note that whenever both the total zerobias junction capacitance. + nb (B) QGS +  VBS' + VGS' QBS S' QGB Rs ns (S) Figure 3.18.106 3 SEMICONDUCTORDEVICE ELEMENTS CJSW. In the largesignal timedomain analysis the gate charges and bulk junction charges are computed from Eq. The capacitances introduced so far are used in the smallsignal analysis. the total capacitances take precedence. Scaled by the device geometry parameters.32 through 3. The reason for this differentiation is the smaller grading coefficient of the sidewall of the diffusion. the largesignal MOSFET model is shown in Figure 3.18 Largesignal MOSFET model. CJSW (1 . AD. The smallsignal MOSFET model is shown in Figure 3.
.5 for the conductance of a diode.i:1 . 3.J.'" J CCD • . these diodes are turned off and gbd and gbs have very small values. gds = rds 1 ~. 3. fined by the following equations: '..1 '. ... The diodes representing the drain and source junctions are modeled by the conductances gbd and gbs in the smallsignal analysis.29) must be used when deriving gm. nb (8) S' " f ..•.METALOXiDESEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETs) 107 .i :l 3.COD hI. The values of gbd and gbs are computed using Eq. nd(D) . Figure ~ • _. . .37) dIDs dVGS dIDs dVBs The expression of IDS appropriate to the region of operation (Eqs. '. and gmbs' In alLMOSFET equations terminal voltages must be referred to nodesD' and. '\ gmVgs' ~ +gnrbsvbs' ~ r d. Usually. " " .19 . f ng (G) . (. L " .~ . gds.( RD D'. resistances RD and RS are nonzero.Smailsignal I ~.S' when the parasitic terminal.odeL U t . dIDs dVDS (3. I ns(S) MQSFET •••• m.
see Examples 10. LEVEL = 1 MOSFET equations are used if this parameter is absent from the • MODEL statement. The drains are connected together at node 2.8 and 10.6 The following statements are examples of MOSFET definitions in SPICE. the only model parameter that is defined is the threshold voltage. except that the characteristics are obtained from a curve tracer. Table 3.MODEL DEP NMOS VTO=3 W=20U W=lOU TOX=. indicating the transistor type.45N CGJX)=3. The sequence is similar to the one described in Example 3. L. node 3.45N CGS0=3.45N MP 2 1 3 3 MODP L=lOU W=40U .Ol LAMBDA=. and defaults are used for KP and the other parameters. The absence of any chargestorage elements from the above model may cause the simulator to abort a transient analysis.5. VTO.lU TOX=. Such limited specification may be useful only for a DC analysis. W.10 for details.MODEL Mom NMOS VTO=l.108 3 SEMICONDUCTORDEVICE ELEMENTS 3. node 0. default to 1 meter.. Ml 1 2 0 0 Mom . where only the ratio of W / L affects the solution. The model parameter is multiplied by the geometry parameter listed in the Scale Factor column on the device statement.005 . The SPICE parameters of MOSFETs are often derived from measurements of IV characteristics of test structures on IC wafers.. the gates are connected at node 1. EXAMPLE 3.MODEL ENH NMOS VTO=l .45N CGS0=3.5 for a JFET. and not the individual values of Wand L.5 Ml is an NMOS transistor with no geometry data specified. The channel length. Note that the VTO specification of the PMOS incorporates the sign. must be specified.lU GAMMA=.OOI LAMBDA=. and the source and bulk of the PMOS are connected to the supply. MN 2 1 0 0 MODN L=lOU W=20U LAMBDA=. > > In every model statement one of the keywords NMOS or PMOS.OOI CGJX)=3.MODEL MODN NMOS VTO=l KP=30U .MODEL MODP PMOS VTO=l KP=15U These statements describe a CMOS inverter. MDRIV 2 1 0 0 ENH L=lOU MLOAD 3 2 2 0 DEP L=20U . the source and bulk of the NMOS are connected to ground.4 summarizes the model parameters introduced so far along with the default values assigned by SPICE2. and width.5 LAMBDA=.3 Model Parameters The general form of the MOSFET model statement is • MODEL MODname NMOS/PMOS <VTO=VTO <KP=KP .
0E9 0. introduced in Example 3.0 I. Exercise Build SPICE decks for the CMOS inverter and enhancementdepletion inverter defined above and trace the I/O transfer characteristic using the •DC statement.0EI6 4. vGso> .0E4 0.5 0 0. The depletion transistor is normally on and its threshold voltage is negative. 3.25 0.lD 0.33 I 1014 0 0 0 00 Example 1.5 1.0Ell 2.5 0.6 0 0 0 0 0 0 0 0.7 I.0EII 4.OE4 10 10 10 5P IP 2.0E1O O.0 0 0.6 1.METALSEMICONDUCTOR FIELD EFFECT TRANSISTORS (MESFETS) 109 Table 3.6 METALSEMICONDUCTOR FIELD EFFECT TRANSISTORS (MESFETS) In SPICE3 the general form of a metalsemiconductor field effect transistor (MESFET) statement is Zname nd ng ns MODname <area> <OFF> < IC=VDSO.OE3 0.2D Scale Factor X 105 n n OIsq F F Fm2 Fml NRD NRS AD AS PD PS Y A Fm1 Fml FmI m m W W L 0 The statements on the previous page describe an enhancementdepletion NMOS inverter.3.4 Name YTO KP GAMMA PHI LAMBDA RD RS RSH CBD CBS CJ MJ CJSW MJSW PB IS CGDO CGSO CGBO TOX LD MOSFET Model Parameters Parameter Threshold voltage Transconductance parameter Bulk threshold parameter Surface potential Channel length modulation parameter Drain ohmic resistance Source ohmic resistance D and S diffusion sheet resistance Zerobias BD junction capacitance Zerobias BS junction capacitance Zerobias bulk junction bottom capacitance Bulk junction grading coefficient Zerobias bulk junction sidewall capacitance Bulk junction grading coefficient Bulk junction potential Bulk junction saturation current GD overlap capacitance per unit channel width GS overlap capacitance per unit channel width GB overlap capacitance per unit channel length Thinoxide thickness Lateral diffusion Units Y Ay2 yl/2 Y yI Default 0 2.
110
3
SEMICONDUCTORDEVICE
ELEMENTS
The letter Z must be the first character in Zname; Z identifies a MESFET only in SPICE3. In PSpice the identification character is B. nd, ng, and ns are the drain, gate, and source nodes, respectively. MODname is the name of the model that defines the parameters for this transistor. Two MESFET models are supported, nchannel (NMF) and pchannel (PMF). The schematic representations of the two types of MESFETs are identical to those of the corresponding types of JFETs, shown in Figure 3.13. The scale factor area is equal to the number of identical transistors connected in parallel, and defaults to 1. The keyword OFF initializes the transistor in the cutoff region for the initial iterations of the DC bias solution. By default MESFETs are initialized conducting, with Ves = VTO, the pinchoff voltage, and VDS = 0.0 for the DC solution. The keyword IC sets the terminal voltages, VDSOand Veso, at time t = 0 in a time domain analysis. VDSOand Veso are used as initial values only when the UIC option is present in the . TRAN statement. The SPICE3 BCEs for this device are given by the Raytheon model (Statz, Newman, Smith, Pucel, and Haus, 1987). The drainsource current, IDs, is given by the following three equations for the three regions of operations, cutoff, saturation, and linear, respectively: 0
IDs = {3(Ves  VTO)2
[1  (1 
ALPHA
V~s
J].
for Ves ::; VTO (l
+ LAMBDA.
VDs)
1
(3
(3(Ves  VTO)2(1 BETA
+ LAMBDA.
VDS)
for 0 < VDs ::; 3/ ALPHA for VDS > 3/ ALPHA
(3.38)
=
1 + B(Ves  VTO)
VTO, BETA, ALPHA, B, and LAMBDA are the threshold voltage, transconductance factor, saturation voltage parameter, doping tail extending parameter, and output conductance factor in saturation, respectively. The above equations are valid for VDS > O. If VDS changes sign, the behavior of the MESFET is symmetrical, the drain and the source swapping roles: Ves is replaced by VeD, and VDS is replaced by its absolute value in the above equations. The current IDS flows in the opposite direction. The dynamic behavior of a MESFET is modeled by two charges associated with the GD and GS junctions. These charges are accumulated on the depletion capacitances of the two reversebiased junctions and are described by Eq. 3.3.
Ces
=
CGS (l  Ves/ PB)o.5 CGD
VeD/ PB)o.5
(3.39)
CeD = (l 
CGS, CGD, and PB are the zerobias gatesource capacitance, zerobias gatedrain capacitance, and the builtin gate junction potential, respectively. The MESFET imple
METALSEMICONDUCTOR
FIELD EFFECT TRANSISTORS (MESFETS)
111
mentation of these capacitances uses voltagedependent factors that control the continuity of the equations around VDS = O. The largesignal and smallsignal MESFET equivalent models are similar to the corresponding JFET models shown in Figures 3.14 and 3.15. The general form of the MESFET model statement is
• MODEL MODname NMF /PMF <VTO=VTO <BETA=BETA ... > >
In every model statement, one of the keywords NMF or PMF must be specified for the transistor type. Table 3.5 summarizes the model parameters introduced so far along with the default values assigned by SPICE3. The threshold voltage, VTO, is signsensitive. MESFETs operate in depletion mode, i.e., they are normally on; therefore VTO is negative for nchannel devices, NMF.
EXAMPLE
Zl
3.7
1 2 3 MODZ ALPHA=l RD=20 RS=20
.MODEL MODZ NMF VTO=3
Zl is a normally on nchannel MESFET with parasitic series drain and source resistances. A normally on pchannel MESFET that conducts the same current as Zl in similar bias conditions is described by the following • MODEL statement:
.MODEL MODZ PMF VTO=3 ALPHA=l RD=20 RS=20
PSpice supports two MESFET models, both with the MODtype keyword GASFET. In addition to the Raytheon model (Statz, Newman, Smith, Pucel, and Haus, 1987) available in SPICE3, PSpice also supports the Curtice model (Curtice 1980).
Table 3.5
Name VTO BETA B ALPHA LAMBDA RD RS CGS CGD PB
MESFET Model Parameters
Parameter Threshold (pinchoff)voltage Transconductance parameter Doping tail extending parameter Saturation voltage parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zerobias GS junction capacitance Zerobias GD junction capacitance Gate junction potential Units V AV2 VI VI VI Default 2.0 104 0.3 2 0 0 0 0 0 1 Example 2.5 1.0E3 0.3 2 1.0E4 100 100 5P IP 0.6 Scale Factor area area area l/area l/area area area
n n
F F V
112
3
SEMICONDUCTORDEVICE
ELEMENTS
3.7
SUMMARY
This chapter has described the semiconductor devices implemented in the most common SPICE programs. The SPICE analytical models and syntax for the diode, the bipolar junction transistor, and the three kinds of field effect transistors, JFET, MOSFET, and MESFET, have been presented in detail. Examples have demonstrated the meanings and the derivations of the model parameters. Each of the semiconductor devices is defined by an dement statement and a set of parameters contained in a •MODELstatement. The same •MODELstatement, that is, the same set of parameters, can be common to more than one device. The diode is defined by the following line: Dname n+ n MODname <area> <OFF> <IC=VDO >
The model parameters describing a diode are listed in Table 3.1 and can be specified in statements of model typeD. The BJT specification is Qname nc nb ne <ns> MODname <area> < OFF> <IC
=
VBEO, CEO> V are
Two types of BJTs are supported in SPICE, NPN and PNP; the model parameters summarized in Table 3.2. The format for JFETs is Jname nd ng ns MODname <area> <OFF> < IC=VDSO,VGSO>
Two types' of JFETs are available in SPICE, NJF and pJF; the model parameters be found in Table 3.3. A MOSFET is defined by the following line: Mname ndng ns nbMODname + «L=>L> < <W=> W> <AD=AD> <OFF> <AS=AS>
can
<PD=PD> <PS= PS> <NRD=NRD> <NRS=NRS> <IC=VDSO, VGSO, BSO> V
+
The two types of MOSFETs supported in SPICE are the NMOSand PMOS devices; the model parameters are listed in Table 3.4. MESFETs are not supported in SPICE2 but are available in SPICE3, PSpice, and most commercial SPICE programs; the syntax differs among SPICE versions. SPICE3 uses the following format: Zname nd ng ns MODname <area> <OFF> <IC=VDSO, vGSO>
The same syntax is used also in PSpice with the sole difference that the identification character is B. The two types of MESFET devices are NMFand PMF. The model parameters are summarized in Table 3.5. The BJT and the MOSFET are described by very complex equations having many parameters. The description in this chapter has not covered secondorder effects. Complete equations of the semiconductor models implemented in SPICE can be found in the book by Antognetti and Massobrio (1988) or in Appendix A.
REFERENCES
113
REFERENCES
Antognetti, P., and G. Massobrio. 1988. Semiconductor Device Modelil1;gwith. SPICE. New York: McGrawHill. Curtice, W. R. 1980. A MESFET model for use in the design of GaAs integrated circuits. IEEE Transactions on Microwave Theory and Techniques MTT28, pp. 448456. Getreu; 1.1976. Modeling the Bipolar Transistor. Beaverton, OR: Tektronix Inc. Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits. 3d ed. New York: John Wiley & Sons. Grove, A. S. 1967. Physics and Technology of Semiconductor Devices. New York: John Wiley & Sons. Motorola Inc. 1988. Motorola Semiconductors Data Book. Phoenix, AZ: Author. Muller, R. S., and T. I. Kamins. 1977. Device Elettronics forlntegrated Circuits. New York: John Wiley & Sons.. . ".. • Shichman; H., and D. A. Hodges. 1968. Modeling and simulation of insulatedgate fieldeffect transistor switching circuits. IEEE Journal of SolidState Circuits SC3 (September), pp.285289. Statz, H., P. Newman, I. W. Smith, R. A. Pucel, and H.A. Haus, 1987. GaAs FET device and circuit simulation in SPICE. IEEE Transactions on Electron Devices (February), pp. 160169. Symmetry Design Systems. 1992. MODPEX. Los Altos, CA: Author. Sze, S. M. 1981. Physics of Semiconductor Devices. New York: John Wiley & Sons. Vladimirescu, A., and S. Liu. 1981. The simulation of MOS integrated circuits using SPICE2, Univ. of California, Berkeley, ERL Memo UCBIERL M80/7 (March). :.' ,.: .. ,. ,,~\., . .,
;. :
"..
~.
:1' •
"
.1'
'j;
j
."
•..•.•'
"
. L'
Four
DC ANALYSIS
4.1
ANALYSIS OVERVIEW This chapter and the following two chapters describe the different analysis types performed by SPICE in its three simulation modes, DC, smallsignal AC, and largesignal transient. Each simulation mode supports more than one analysis type. The specifics of each analysis are explained in the chapters on the corresponding simulation modes. All statements introduced in this chapter and the following two chapters, analysis specifications and output requests, are control statements as defined in Chap. 1 and start with a period in the first column.
4.1.1
Simulation Modes and Analysis Types
The first simulation mode, DC, always computes and lists the voltages at every node in the circuit. The DC node voltages are computed prior to an AC or transient (TRAN) simulation. In the TRAN mode the DC solution can be specifically prohibited. DC supports the following four analysis types:
OP
DC voltages and operating point information for nonlinear elements Smallsignal midfrequency transfer function Transfer curves Sensitivity analysis
TF
DC
SENS
These analyses are presented in the following four sections of this chapter. The last section describes node voltage initialization. SPICE finds the DC solution in most cases
114
ANALYSIS OVERVIEW
115
without any additional information; in the situations where SPICE fails to find the DC solution, initialization options are available. The AC analysis described in Chap. 5 computes the frequency response of linear circuits and of the smallsignal equivalents of nonlinear circuits linearized near the DC bias point. Two additional analysis types can be performed in the frequency domain:
NOISE DISTO
Smallsignal noise response analysis Smallsignal distortion analysis of diode and BJT circuits
In the TRAN mode SPICE computes the largesignal timedomain response of the circuit. An initial transient solution, which is identical to the DC bias, precedes by default a TRAN simulation. The only additional analysis in the timedomain is
FOUR
Fourier analysis
The timedomain analysis is presented in Chap. 6.
4.1.2
Result Processingand Output Variables The results of the different analyses must be requested in • PRINT or . PLOT statements, introduced in Sec. 1.3.3. These statements identify circuit variables, voltages, and currents, to be computed and stored for specific analyses. Analyses are omitted in SPICE2 if no results are requested. SPICE3 performs the specified analyses even in the absence of a • PRINT or . PLOT statement; the results are stored in a rawf ile and can be displayed using the postprocessing utility Nutmeg. Similarly, PSpice runs the analysis and stores the results only if a • PRINT, . PLOT, or the proprietary. PROBE line is present in the input file; • PROBE saves the output results in a binary or a text file, which is used by the graphic display program Probe . . PRINT provides tabular outputs, whereas • PLOT generates lineprinter plots of the desired variables, as seen in Figure 1.7. The general format of the output request statement is
. PRINT/PLOT
AnalysisTYPE OULvar} <OULvar2 ... > <ploLlimits>
where AnalysisTYPE can be DC, AC, NOISE, DISTO, or TRAN and is followed by up to eight output variables (OULvar), which are voltages or currents. If more than eight output variables are desired, additional PRINT/PLOT statements must be used. There is no limit on the number of output variables. Output variables can be node voltages, branch voltages, and currents through voltage sources. A voltage output variable has the general form V (nodel <,node2> ) . If only node} is present, that node voltage is stored; if two nodes are specified, the output variable is the branch voltage across elements connected between node} and node2. A current output variable is of the form I (Vname) where Vname is an independent voltage source defined in the input circuit. The current measured by Vname flows
116
4
DC ANALYSIS
through the source from the positive to the negative source node. PSpice provides the convenience of identifying the current flowing through any circuit element by the expression I <pin> (Element...name) where Element...name corresponds to an element present in the circuit file and pin must be used only for multiterminal devices, such as transistors. I (R3 ), I (L1) , and Ie (Q7) are accepted current variables in PSpice representing the currents flowing through the resistor R1, the inductor L1, and the collector of the BJT Q7. In AC analysis the V and the I are followed by one or more characters specifying the desired format of the complex variable. In the NOISE and DISTO analyses, output variables are limited to the specific functions detailed in Sec. 5.3 and Sec. 5.4, respectively.
4.1.3
Analysis Parameters: Temperature
All element values specified in a SPICE deck are assumed to have been measured at a nominal temperature, TNOM, equal to 27° Celsius (300 K). The simulation of the circuit operation is performed at the nominal temperature of 27° C. The nominal temperature can be set to a different value using the • OPTIONS statement, described in Chap. 9. In practical design situations the operation of the circuit must be verified over a range of temperatures. In SPICE the circuit can be simulated at other temperatures defined in a global statement, • TEMP, with the following syntax:
• TEMP tempI
<temp2 ...
>
The simulation is performed at temperatures tempI, temp2, ... when a • TEMP line is present in the SPICE input file. The temperature values must be specified in degrees Celsius. Note that if the value of the nominal temperature is not present on the • TEMP line, the circuit is not simulated at TNOM. The effects of temperature on the values of different elements is computed by SPICE, and the updated values are used to simulate the circuit. Resistor values are adjusted for temperature variations by the following quadratic equation: value(TEMP)
=
value(TNOM)[l
+ tel(TEMP + tc2(TEMP
 TNOM)  TNOM)2] (4.1)
where TEMP is the circuit temperature, TNOM is the nominal temperature, and tel and tc2 are the first and secondorder temperature coefficients. The behavior of semiconductor devices is affected significantly by temperature; for example, temperature appears explicitly in the exponential terms of the BIT and diode current equations (see Chap. 3), as well as in the expressions of the saturation currents (1s), builtin potentials (cf>]), gain factor ({3F), and pnjunction capacitance (e]). The detailed temperature dependence of the model parameters of semiconductor devices is described in Appendix A. When a circuit is analyzed at a temperature different from TNOM, SPICE2lists the TEMPERATURE ADJUSTED VALUES for each element or model affected by tempera
OPERATING (BIAS) POINT
117
ture. Note that SPICE3 does not support the. TEMP statement; the ambient temperature must be defined on an • OPTIONS line. Exercise Add the statement
.TEMP 100
to the onetransistor input file used in Example 1.3, run SPICE2, and note the differences in the model parameters and DC operating point. Which behavior of the circuit is most affected by temperature variation?
4.2
OPERATING (BIAS) POINT The DC mode solves for the stable operating point of the circuit with only DC supplies applied. Capacitors are open circuits and inductors are shorts in DC. The DC solution consists of two sets of results; first, the DC bias solution, or the voltages at all nodes; and second, the operating point information, or the current, the terminal voltages, and the element values of the smallsignal linear equivalent, computed only for the nonlinear devices in the circuit. SPICE computes and prints the bias solution prior to any other analysis. The operating point, however, is not printed unless requested by an .OP statement. The only time this information is printed without the presence of .OP is when no analysis request is present in the input file. The voltages at all nodes, the total power consumption, and the current through each supply are printed as part of the SMALLSIGNAL BIAS SOLUTION (SSBS). Currents, terminal voltages, and smallsignal equivalent conductances of all nonlinear devices are listed in the OPERATING POINT INFORMATION (OPI) section of the output. The information provided by SPICE about the DC operation of a circuit is best explained by two examples, a linear and a nonlinear circuit.
EXAMPLE 4.1
Replace resistors R 1 and R3 in the bridge T circuit of Figure 1.1, by two capacitors, C1 = Cz = 1 JLF. Verify the DC solution with SPICE. The new circuit is shown in Figure 4.1.
Solution
The DC solution for the resistive circuit was computed in Example 1.1. A capacitor is equivalent to an open circuit in DC; therefore we expect the following DC solution:
V (1)
= V (3) = 12 V; V (2) = 0 V.
The modified SPICE input file and the results of the analysis are shown in Figure 4.2. The information in the SSBS is a complete characterization of the circuit. The
0000 = 27.0000 VOLTAGE NAME SOURCE CURRENTS CURRENT O.000 DEG C NODE VOLTAGE VOLTAGE 12.1 capacitors.OOE+OO WATTS VI TOTAL POWER DISSIPATION Figure 4.118 4 DC ANALYSIS 1 kQ Figure 4.OOOE+OO 0 . BridgeT circuit with BRIDGET CIRCUIT CIRCUIT DESCRIPTION **** * Cl 1 2 lu C2 2 3 lu VI 1 0 12 AC 1 R3 2 0 lk R4 1 3 lk * • E!'ID BRIDGET **** NODE 1) CIRCUIT SMALL SIGNAL BIAS SOLUTION NODE VOLTAGE 2) 0.2 DC solution of bridge.T circuit with capacitors. .0000 TEMPERATURE NODE VOLTAGE 3) 12.
plus a secondorder resistance (see Appendix A for more detail).9 are part of the OPI section. 3.OPERATING (BIAS) POINT 119 only data not computed by SPICE are the branch currents. reproduced here in Figure 4. the series parasitic base resistance.2 Consider next the onetransistor amplifier of the first chapter. If a specific current is desired from SPICE. Solution The values of the smallsignal equivalent model components of QI shown in Figure 3.2. VAF. As seen in the two DC solutions of the bridge. 3. Relate the SPICE2 parameters listed under the OPI with the BIT model presented in Sec. but the node voltages and element values are sufficient for the derivation of any current. internally 1 kn Rc + 5 v= Vee Figure 4.A = 8. introduced in Chap.4 for convenience. EXAMPLE 4. The SPICE2 results obtained in Chap.15 and 3. GMand RPI are computed according to Eqs.1. 3.3. In the absence of the Early voltage. RO is infinite.17: GM RPI RX = IC = 2. and RO is the collectoremitter output resistance. a dummy voltage source must be added in series with the element of interest.14.3 Onetransistor circuit. 1 are repeated in Figure 4. Figures 1. the currents through voltage sources are listed in the SSBS.102 mho Vth = 3 0.2.3. .T circuit.0258 V = BE~:C 1.23 k!1 j" is equal to RB.3 and 4. 10.
OP results for onetransistor circuit.000 DEG C 3/15/83 ********17:11:05***** * • END *******12/20/88 ONETRANSISTOR **** SMALL SIGNAL BIAS SOLUTION ') *********************************************************************** NODE 1) VOLTAGE 0. .000 DEG C ********17:11:05***** OPERATING POINT INFORMATION *********************************************************************** Figure 4.4 .MODEL QMOD NPN .3) TEMPERATURE = 27.6 3/15/83 ONETRANSISTOR **** CIRCUIT (FIG.6 (FIG. 4. 4.OP .000 DEG C ************************************************************************ Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * * * .8967 NODE ( 3) VOLTAGE 5.7934 NODE ( 2) VOLTAGE 2.3) 3/15/83 ********17:11:05***** INPUT LISTING TEMPERATURE = 27.6 (FIG. 4.WIDTH OUT=80 ******** CIRCUIT SPICE 2G.0000 VOLTAGE SOURCE CURRENTS NAME CURRENT VCC 2.120 4 DC ANALYSIS *******12/20/88 ONETRANSISTOR **** ******** CIRCUIT SPICE 2G.124D03 TOTAL POWER DISSIPATION 1.06D02 WATTS *******12/20/88 ******** SPICE 2G.3) TEMPERATURE = 27.
5. fT.793 2.OOE+OO 100.OOE+OO O. which defaults to 1012 n and can be set as an option parameter (see Chaps.4 SPICE2 clamps the maximum resistance to lIGMIN.19 and 3. VOH and VOL. Another example of DC operating point information is included for the depletionload NMOS inverter shown in Figure 4. For a correctly designed enhancementdepletion (ED) inverter. depends on the model parameters of the two .10E03 0. VoH.4. FT. CBX and CCS. The smallsignal capacitances.13E02 1.103 2. TF.23E+03 O. however. respectively. VOL.OOE+OO O. is equal to VDD.OOE+OO O. this explains the very high value of FT in Figure 4. EXAMPLE 4. are only relevant for secondorder effects.000 1. For more than one transistor or other nonlinear element the OPI is computed for each such element. cpr and CMU. are also part of the bias information and are computed according to Eqs.OPERATING (BIAS) POINT 121 **** MODEL IB IC VBE VBC VCE BIPOLAR JUNCTION TRANSISTORS Q1 BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT QMOD 2. or TR.00E+12 O.3 Two important characteristic values of a logic gate are the high and low output voltages.OOE+OO 1. The remaining capacitances. which corresponds to a low VIN.897 100. which corresponds to high VIN. CJC. is infinite. and the corresponding cutoff frequency. 9 and 10).000 8. the supply voltage.10E05 2. in the •MODEL statement the cutoff frequency.20.29E+18 (continued) Figure 4. Since no values are defined for CJE. 3.
where VTOE and VTOD are the enhancement and depletion transistor threshold voltage.3) 2.5 using the following MOS model parameters: VTOE = 1 V. and the geometry ratio. 3. (W / L)[ = 4. Verify the result with SPICE. VOL is calculated by equating the currents of .5 Enhancement depletion NMOS inverter circuit.5 V in order to account for the body effect of the depletion device. as in Eq. respectively.86 V In the above calculation VOL has only been estimated at 0.2) Find the low output voltage. VTOD = 3 V. and (W / L)L = 1. transistors. VOL. of the inverter (Hodges and Jackson 1983): .122 4 DC ANALYSIS 5V Figure 4. KP = 20/LA/V2. and PHI = 2<jJF = 0.5 V1/2. M[ and ML. GAMMA = 0. (4.30: VTHD = VTOD .6 V. KR. of the ED inverter of Figure 4. Assume that VIN = VDD = 5 V.14 V =  JPHI) (4. Solution First calculate the threshold voltage of the depletion device taking into account the body effect.3V + GAMMA ( JPHI + VOL + 0.
29: 1m = IDL (4.4) MI is assumed to operate in the linear region. ML. and depletion transistor.MODEL DMOS NMOS VTO=l VTO= KP=20U 3 KP=20U GAMMA=.6 V. . because VDSI = VOL < VGSI  VTOE since VOL has been approximated at 0. The circuit description is listed first. such as the value of PHI. 0.02 (Mar 1987) ******** 00:11:01 ******** ED NMOS INVERTER **** CIRCUIT DESCRIPTION **************************************************************************** MI 2 1 0 0 EMOS w=40U L=10U ML 3 2 2 0 DMOS TtF10U L=10U VDD 3 0 5 VIN 1 0 5 * * .5 V. and not the default values for other parameters. 5 * .4. Note that only the parameter values specified in the input file are listed.6. The current flowing through the inverter is These results of the SPICE2 analysis are shown in Figure 4. MI. Substitution of the guess for VOL in Eq. 4.27 V.4. 4. the new solution is VOL = 0. ******** 12/29/88 ******** PSpice 3.OPERATING (BIAS) POINT 123 the enhancement transistor. but the result is very close to the SPICE solution. The correction in VTHD has been overestimated.6 SPICE2 input and operating point of MOS inverter.3 yields a simple quadratic equation in VOL for Eqs. followed by the MOSFET MODEL PARAMETERS of transistors MI and ML. 3. according to Eqs.MODEL EMOS NMOS . models EMOS and DMOS. For all the default values of MOSFET parameters see Table 3.OP * • END Figure 4. The SSBS and OPI list the node voltages and smallsignal values of the transistors.
OOE+OO O.OOE+OO O.OOE+OO O. OOE+OO 4.00E05 0.84E05 O.000 2.00E+00 2.92E+00 5.OOE+OO O.00E05 0.26E004 WATTS TEMPERATURE = TOTAL POWER DISSIPATION **** **** MOSFETS OPERATING POINT INFORMATION 27.52E05 O.000 1.OOE+OO O.523E005 O.OOOE+OOO 4. 92E+00 2.OOE+OO O.500 TEMPERATURE NODE 3) VOLTAGE 5.6 124 .OOE+OO O.OOE+OO 1.000 DEG C MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOV CGDOV CGBOV CGS CGD CGB MI EMOS 8.00E+00 2.21E05 2.OOE+OO (continued) ML DMOS 8.0000 NODE 2) VOLTAGE 0.2758 = 27.OOE+OO O.OOE+OO O.OOE+OO O.52E05 5.000 2. 000 3. 56E05 O.0 PARAMETERS DMOS NMOS 1.OOE+OO 1.OOE+OO O.**** TYPE LEVEL VTO KP GAMMA MOSFET MODEL EMOS NMOS 1.OOE+OO O.OOE+OO O.72E+00 2.OOE+OO O.OOE+OO 4.98E04 O.000 DEG C NODE VOLTAGE SOURCE CURRENTS CURRENT 8.76E01 2.0000 **** NODE 1) VOLTAGE NAME VDD VIN SMALL SIGNAL BIAS SOLUTION VOLTAGE 5.OOE+OO O.OOE+OO Figure 4.76E01 O.
Note that VTH for the load transistor ML is corrected to 2. v/i2_value = v/i2_value + step2) v/iLvalue = startl for (v/iLvalue :5 stopl. CBS.3.PRINT DC OULvarI <OULvar2 > . The following statement defines the source and the range of swept values: • DC V/InameI startI stopI step] <V/Iname2 start2 stop2 step2> The voltage or current source names VnameI.3 DC TRANSFER CURVES This analysis computes the DC states of a circuit while a voltage or current source is swept over a given interval. Any node voltage or current through a voltage source can be defined as an output variable. TEMP. VTH also contains corrections due to smallsize geometry for higherlevel MOSFET models. and VBS. In addition to the voltage and current of an independent source. and CGB. The value of the output variable is evaluated by sweeping the variables in the following order: v/i2_value = start2 for (v/i2_value :5 stop2. GMBS.19 and are GDS. SPICE allows a second source to be varied as an outer variable.ploUim2> . Source Vllname] is also called the inner variable and source Vllname2. The output variables of interest must be requested as either a tabular print or a plot . PLOT DC OUT_varI <OULvar2 > <ploUimI. as well as the overlap capacitances. Vname2 or InameI. 4.v/i2_value) + step1) The value viiI _value of source VllnameI is swept first over the interval from startI to stopI for each value. the terminal voltages. rather than gather all curves in a single plot. the backgate biascorrected threshold voltage. The smallsignal characteristics for a MOSFET correspond to the smallsignal model of Figure 3. CGS. Vvs. v/iLvalue = v/iLvalue OULvar = f (vii Lvalue. The variation of two sources does not result in a comprehensive lineprinter plot. as presented in more detail in the works by Antognetti and Massobrio (1988) and Vladimirescu and Liu (1981) and Appendix A. 4. SPICE2 and other SPICE versions allow the user to vary the value of a resistor. and VTH. the program generates one plot for each value of the second source. or the temperature. CBD.92 V according to Eq. GM. the outer variable. The biaspoint information contains the drain current. CGD. vli2_value. Iv. Rname. Iname2 must be defined in another independent source statement. the outer variable. VGS.DC TRANSFER CURVES 125 The output voltage at the drain of MI agrees to two decimal points with the hand calculation. The graphic display tools Nutmeg and Probe can overcome this problem. of Vllname2.
5 0. A different SPICE simulator and plotting package can be used.126 4 DC ANALYSIS In SPICE2 if no DC output variable is defined in either print or plot format. VGs) characteristics of the junction field effect transistor 2N4221. EXAMPLE 4. The second statement produces a tabular output listing of the values of the voltage at node 6 and the voltage difference between nodes 10 and 11. The third statement generates a lineprinter plot of the current flowing through the voltage source VICQ9. the DC sweep analysis is omitted.002 y1.5. BETA = 4. Figure 4.4 Use PSpice and Probe to represent graphically the IDs = f(VDS.25 V.1.PRINT DC V(6) V(lO.5 Y to 0.7 Measurement setup for JFET Yes) characteristics with IDS = f(VDs.11) .LAMBDA = 0.8 Y in steps of 0. The derivation of the SPICE model parameters from data book characteristics is described in Example 3. The first line specifies that voltage source VIN is to be swept from 0.25 . use the Motorola Semiconductors Data Book (Motorola Inc. 104 A/y2. Two very common applications for using DC transfer curves are described in the following examples.5 Y. and from the Motorola data book we can derive the following model parameters: VTO = VGS(ofj) = 3.8 0. PLOT DC I (VICQ9) The above three statements are part of a SPICE input file requiring the computation of DC voltage and current transfer curves. SPICE deck.DC VIN 0. . a dummy voltage source connected at the collector of a transistor. to measure the values of Ie.RD = 200.7. 1988) for the electrical characteristics. Q9. Solution The measurement setup is shown in Figure 4. Example .
. VGs) characteristics of a JFET.END * The output characteristics of the transistor computed by SPICE are shown in Figure 4.PROBE * OTHER SPICE *.002 RD=200 *. the 5 4 « E 3 2 o 5 10 15 20 25 Figure 4.PRINT DC I(VD) .OP . and 0 V. VD and VG. PLOT lines are necessary for graphical results in PSpice.1 V. Note that no • PRINT or . are defined by the •DCstatement. all that is needed is a • PROBE statement. Note that in spite of using a very simple model with just basic parameters.8 Simulated IDS = f(VDS. IV CHARACTERISTICS Jl 2 1 0 MODJ VD 2 0 25 VG 1 0 2 OF JFET 2N4221 * * .3 V. 3.MODEL MODJ NJF VTO=3.8. . .5 BETA=4. Eqs. .1E4 LAMBDA=O.DC VD 0 25 1 VG 3 0 1 * ONLY FOR PSPICE .2 V. The range of values and increments for the two bias sources.25 are used to compute the current IDS for values of VDS from 0 to 25 V in steps of 1 V at four values of VGS.DC TRANSFER CURVES 127 The SPICE input description is listed below.
The effect of changes in the geometry of the transistors. and VIL = 2. VOL = 0.5 V VIL . EXAMPLE 4.VIH = 3. in Wand L. Another common use of DC transfer curves is for the design of logic gates.VOL = 2. The input voltages VIH and VIL are defined by the points where the slope of the voltage transfer characteristic is unity (Hodges and Jackson 1983). such as Parts from MicroSim.5.22 V The above values guarantee a proper operation of the ED NMOS inverter when connected with other logic gates implemented in the same technology that is. NMH and NML. are marked on the plots.5 Find the noise margins NMH and NML of the NMOS inverter in Figure 4. VIH = 1. in NMOS.128 4 DC ANALYSIS computed IV characteristics are close to those in the data book.6: . The four voltages are: VOH = 5 V.3. Solution The following two statements ure 4.28 V. can be easily observed in a repetition of the above analysis.9.5 V. VIH.5 V.DC VIN 0 5 0. defining the high and low noise margins. . Use the parameters of Example 4. which require a thorough characterization of the noise margins. respectively.PLOT DC V(2) must be added to the input circuit description in Fig The resulting SPICE2 plot is shown in Figure 4. and VIL. that is. This example also shows the usefulness of a lineprinter plot for an accurate reading of the output voltages for given input voltages. The four voltages VOH. the gate of transistor M1 is swept from 0 to 5 V. More accurate model parameters can be obtained using parameter extraction programs. These result in NMH and NML = = VOH . VOL.25 .
124EOl 4.165EOl 2.923EOl 5.4 SMALLSIGNAL TRANSFER FUNCTION At the completion of the DC bias solution the linearized network of a nonlinear input circuit is available.240EOl 7.101EOl 5.758EOl * * * * * *.432E+00 3.000EOl 7. The output variable can assume any of the forms described for output variables on PRINT and PLOT DC statements. dVo/ dVi or dIo/ dIi. SPICE2 computes the gain and the input and output resistances of the twoport circuit defined by the.250E+00 2.947EOl 2. The twoport characteristics of the linearized circuit can be obtained by using the .000E+00 1.546E+00 9.000E+00 4.943E+00 4.541EOl 4.000E+00 4. The gain can be a voltage or current gain.000E+00 5. TF statement.0000E+00 8.250E+00 1.SMALLSIGNAL TRANSFER FUNCTION 129 ED NMOS INVERTER **** VIN DC TRANSFER CURVES V(2) O.500E+00 3.250E+00 4. dVo/ dh . VlIname identifies an independent voltage or current source connected at the input of the two ports defined by the above statement.000 DEG C (*)O.OOOE+OO 2.866E+00 2.9 DC transfer characteristic of NMOS inverter. For example.750E+00 5.0000E+00 VIR VIL 5.500EOl 5.9 and listed in Figure 4.4. dIo/ dVi.721EOl 3.750E+00 4.000E+00 5.000E+00 5.000E+00 5.750E+00 3.763E+00 4.000E+00 4. TF OUT_var V/Iname control statement. a transconductance.000E+00 2. or a transresistance.500E+00 4.OOOOE+OO 2.419EOl 3. for a BJT SPICE has computed the values of all the elements of the smallsignal BIT model shown in Figure 3.000E+00 3.750E+00 2.250E+00 3.500E+00 2. 4. * * * * * * * * * * VOL Figure 4.500E+00 1.0000E+OO TEMPERATURE = 27.500EOl 1.087EOl 3.0000E+00 6.
TF analysis of SPICE2. Their values range from 1 nF to 1 p. This source represents the AC input signal ii. listed in Figure 4. coupling capacitors are shorted and highfrequency capacitors are open. Solution The midfrequency smallsignal equivalent circuit of the onetransistor amplifier is shown in Figure 4. in the frequencydomain analysis the assumption that the signal is small limits Vn to Vth. In the largesignal timedomain analysis Vn can have any value. which is a valid approximation of the nonlinear circuit as long as it does not deviate significantly from its bias point. Coupling capacitors are used to decouple amplifier stages from each other and from signal generators for proper bias. the addition of a voltage input source at the base of QI.20 or taken directly from the OPI of transistor QI. EXAMPLE 4. and cjJ is the phase shift of the AC signal.3. Therefore. A pure resistive network is assumed in the transfer function solution. Highfrequency capacitors limit the bandwidth at high frequencies and are exemplified by transistor internal capacitances. In general. which can perturb the DC bias of the circuit. The easiest approach to adding a signal source without perturbing the DC state is to use a current source Ii that has a DC value of zero at the input. node 1. such as C and C!L for a BJT and Cos and COD for a MOSFET.4. Verify the results using the.130 4 DC ANALYSIS An important assumption of • TF is that the midfrequency behavior of the circuit is to be computed. that is. In order that a • TF analysis can be performed. A source in SPICE has also a DC component. . The additional midfrequency assumption simplifies the AC component of the signal to a real rather than complex value.3.6 Find the twoport midfrequency characteristics of the onetransistor amplifier of Figure 4.15 through 3. The inclusion of a smallsignal transfer function in a largesignal DC analysis needs a few more explanations.F. Inductors at midfrequency are assumed to be shorted or open depending on which end of the frequency range they affect. the thermal voltage. the validity of the • TF analysis is limited to circuits that contain only highfrequency capacitors and lowfrequency inductors.10. Vn is the amplitude. would change the operating point of the transistor. The values of the linearized network can be computed using Eqs. an input signal source must be added to the circuit in Figure 4. SPICE treats all capacitors as open and all inductors as shorted in the DC analysis. With this assumption the AC response can be computed on a linear network. This assumption is valid for frequencies at which chargestorage effects can be neglected. the voltage or current at any node is 7T where VN is the DC bias value. 3.
TF V(2) II The modified input circuit and the SPICE2 results of the analysis are shown in Figure 4.SMALLSIGNAL TRANSFER FUNCTION 131 B i.4 for performing the transfer function analysis in SPICE2: II 0 1 .11. are the transresistance. does not disturb the operating point of the circuit. II. .!i0 I I I I I r~ IgmVb. The results confirm the above hand calculations. Ri.6) Ri Ra = II a r = Rc (4. ar. The transfer function characteristics of the onetransistor circuit for a voltage output. Q c Ii t I I E L____ _ __ I I I I I l Figure 4. and a current input. and output resistance. the input resistance. Note in the SSBS that the zerovalued input current source. V2. Ii.7) transfer function: The voltage gain can be obtained from the transresistance Va Vi av = ar Ri (4.5) (4.8) The following two statements must be added to the input description of Figure 4. at the collector of Ql.10 Smallsignal midfrequency equivalent of onetransistor amplifier. Ra: ar = Va ii Vi ii Va ia = V2 RB RB r71' Ii RB II Rc + f3FRc r71' (4.
A voltage transfer function can be obtained by replacing resistor RB with a Thevenin equivalent at node I and specifying the added voltage source as input in the .MODEL * * QMOD NPN II . 4.END SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.11 .WIDTH OUT=80 . 4.06D02 WATTS **** SMALLSIGNAL CHARACTERISTICS = 9.000 DEG C Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 II 0 1 * * * .939Dt04 = 1. .000 DEG C NODE 3) VOLTAGE 5. derived above in Eq. TF statement.TF V(2) .000Dt03 V(2) III INPUT RESISTANCE AT II OUTPUT RESISTANCE AT V (2) Figure 4.7934 NODE 2) VOLTAGE 2.0000 **** NODE 1) VOLTAGE SOURCE CURRENTS NAME VCC CURRENT 2.3) **** INPUT LISTING TEMPERATURE = 27.124D03 TOTAL POWER DISSIPATION 1.8. using a voltage transfer function.8967 TEMPERATURE = 27.132 4 DC ANALYSIS ONETRANSISTOR CIRCUIT (FIG.222Dt03 = 1. av. TF analysis results for a onetransistorcircuit. Exercise Confirm the value of the voltage gain.
Second.SENSITIVITY ANALYSIS 133 4. These values reflect the sensitivities of DC voltages and currents with respect to perturbations in circuit element values. ELEMENT VALUE. The sensitivities with respect to every element in the circuit and all DC model parameters of diodes and BITs are computed for each output variable defined in the.5 SENSITIVITY ANALYSIS Sensitivity analysis offers insight into the effect of the values of circuit elements and variations of model parameters on selected output variables and hence on circuit performance. consider the sensitivity results in the DC SENSITIVITY ANALYSIS section. There are two sensitivity numbers listed for each parameter value: the absolute sensitivity.7 Use SPICE2 to compute the sensitivity of the current provided by the current mirror (Gray and Meyer 1993) shown in Figure 4. No sensitivities with respect to model parameters of IFET or MOSFET transistors are available.02 = 0. No sensitivity analysis is available in SPICE2 for AC or timedomain response.7 V 4. SENS statement. Solution The current supplied by this current source is Ie2 IREF = IREF 1 + 2/ Vee  {3F VBE(on) lA 1. Assume that {3F = 100 and assign the default values to the remaining BIT model parameters. and all results appear under the header DC SENSITIVITIES OF OUTPUT I (VMEAS).. > where output variables OUT_var 1. operating point. SPICE3 does not support this type of analysis. OUT_var2. avj apj. the absolute sensitivity in amperes or volts per . note in the OPI section that the value of Ie2 is very close to the above estimate. In this example a single output variable has been requested.98 rnA 1 rnA = REF 5 .0..12 with respect to the circuit parameters. and sensitivity results of the SPICE2 simulation are listed in Figure 4. The same data are computed for each output variable on the • SENS statement. (avj apj)(pj/ 100).. The fourcolumn tabular output lists the ELEMENT NAME.103 n The input specification.. . are defined in the same manner as for the • PRINT and • PLOT statements. EXAMPLE 4. and the relative sensitivity.3. ELEMENT SENSITIVITY. The sensitivity analysis request has the following form: • SENS OULvarl <OULvar2 . First.13.
13 SPICE2 sensitivity results for the current mirror. The most informative data are the normalized sensitivities. For this small circuit it is easy to spot that a I % change in the value of any of the following elements causes roughly a 1OILA variation in IC2: the reference resistor. and the NORMALIZED SENSITIVITY in amperes or volts per I % variation in the value of the respective element.WIDI'H OUI'=80 • END Figure 4. An increase of REF and IS causes I C2 to CURRENT MIRROR CURRENT SOURCE REF 3 2 4.3k Ql 2 2 0 QMOD Q2 1 2 0 QMOD VMEAS 3 1 VCC 3 0 5 * * . .134 4 DC ANALYSIS 0. and IS. Vcc. REF. the saturation current of transistors Ql and Q2. Current mirror unit of the respective element.OP .MODEL * QMOD NPN BF=100 VA=50 . the supply.SENS I (VMEAS) * .12 current source. REF Figure 4.
028E+l3 O.415E07 1.OOOE+OO O.00E+00 TEMPERATURE ELEMENT SENSITIVITY (AMPS/UNIT) 2.000 DEG C NODE VOLTAGE 3) VOLTAGE NODE VOLTAGE 0.OOOE+OO O.500E+00 2.000E16 1.73EOl 4.OOOE+OO O.325E05 O.0000 NODE 2) TEMPERATURE = 27.038E05 O.OOOE+OO O.000E+Ol O.7733 ( 5.64E06 9.OOOE+OO O.OOOE+OO 1.OOOE+OO O.927E05 2.OOOE+OO O.OOOE+OO O.OOOE+OO O.**** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 5.OOOE+OO O.OOOE+OO 1.028E05 O.64E04 7.0000 VOLTAGE SOURCE CURRENTS NAME CURRENT VMEAS 1.OOOE+OO = DC SENSITIVITY ANALYSIS **** DC SENSITIVITIES OF OUTPUT I(VMEAS) ELEMENT ELEMENT VALUE NAME 27.OOOE+OO REF VMEAS VCC Ql RB RC RE BF ISE BR ISC IS NE NC IKF IKR VAF VAR Figure 4.OOOE+OO 135 .OOOE+OO O.64E06 1.OOOE+OO 1.000E+02 O.OOOE+OO O.OOOE+OO O.OOOE+OO 1.73EOl Q2 QMOD 9.OOOE+OO O.OOOE+OO O.000 DEG C NORMALIZED SENSITIVITY (AMPS/PERCENT) 1.018E07 O.018E07 O.300E+03 O.OOE+OO 7.05E03 7.OOOE+OO 1.OOOE+OO O.OOOE+OO O.OOOE+OO O.OOOE+OO 1.045E003 VCC 2.01E002 WATTS **** OPERATING POINT INFORMATION TEMPERATURE = 27.OOOE+OO O.000 DEG C **** BIPOLAR JUNCTION TRANSISTORS NAME MODEL IB IC VEE VEC VCE Ql QMOD 9.OOOE+OO O.73EOl O.028E003 TOTAL POWER DISSIPATION 1.OOOE+OO 5.OOOE+OO O.23E+00 5.649E04 O.000E+00 O.OOOE+OO 1.OOOE+OO 1.OOOE+OO O.OOOE+OO 5.13 (continued) 4.000E+00 O.
OOOE+OO 1. and so on.OOOE+OO 1.NODESET V(nodel)=valueI <V(node2)=value2 .OOOE+OO O.OOOE+OO 2.056E18 O.6 NODE VOLTAGE INITIALIZATION All nonlinear electrical simulation programs compute the solution iteratively. SPICE2 uses the initial values only as a guidance until it finds a first solution.OOOE+OO O.000E+02 O. but it must not be identical with them. A good example of the use of the • NODESET statement is the DC analysis of bistable circuits.OOOE+OO O. For these situations a node voltage initialization statement is available with the following general format: . The number of requested output variables in sensitivity analysis should be kept small.OOOE+OO 1.OOOE+OO 1..OOOE+OO O. because a large amount of information is generated by this analysis.13 (continued) O.the default number of 100 iterations. if they are correct.OOOE+OO O.OOOE+OO O.000E+Ol O. The following example shows the effect •NODESET has on the final solution.OOOE+OO decrease.018E07 O.OOOE+OO O. In most cases the user does not need to specify any information about initial voltages. 629E06 O. . The final solution is probably in agreement with the •NODESET values.OOOE+OO O.018E07 O.OOOE+OO 1.035E+13 O. The iterative process starts with an initial guess of the voltages. Initially SPICE assumes that all node voltages are zero. > The effect of this statement is to assign valueI to the voltage of node nadel.136 4 DC ANALYSIS Q2 RB RC RE BF ISE BR ISC IS NE NC IKF IKR VAF VAR Figure 4. whereas an increase in Vee brings about an increase in Iez.OOOE+OO 1.000E16 1.147E07 O.OOOE+OO O.OOOE+OO 5.000E+OO O. the search for the DC voltages continues. 4.OOOE+OO 2. There are exceptions when SPICE cannot find the solution in . in the first few solution iterations.OOOE+OO 1. value2 to node node2. however. with the initialization constraint removed until the final solution is reached..035E05 O.OOOE+OO O.OOOE+OO O.OOOE+OO O.500E+OO 2.OOOE+OO 1.OOOE+OO 8.OOOE+OO O.OOOE+OO O.056E16 O. The final solution may differ from the values specified by •NODESET. The effect of a perturbation in BF is far less important.OOOE+OO O.OOOE+OO O.
and the second is with MIl OFF and M12 ON.16. The solution found by SPICE2 has both inverters biased identically. VDD.14. This is a metastable state. and the other would be OFF. .NODE VOLTAGE INITIALIZATION 137 EXAMPLE 4. which is equal to the solution found in Example 4. is a corrected value of the initial guess. Solution The input specification and the bias point obtained from SPICE2 are shown in Figure 4.15.14 MOS flipflop.3.16 is according to expectations. is presented in Section 6.2758.3.3 in conjunction with the timedomain analysis .25 V (V (1) = 0. Another approach to node voltage initialization. V (1) = 0. as listed in the modified input in Figure 4. Use the same MOSFET model parameters as in Example 4. and upon connecting the supply. The flipflop or bistable circuit.14 has two stable operating points: the first is with MIl ON and M12 OFF.• IC can be used to find the DC bias Figure 4.8 Find the DC solution of the flipflop circuit shown in Figure 4. of Figure 4. Note that the voltage at node 1. • IC. The same result can be obtained by adding the keyword OFF to the MIl line. The solution obtained by SPICE2 in the presence of the • NODESET statement and shown also in Figure 4.3 for the same inverter.25). this is equivalent to initializing transistor MIl in the OFF state. with both MIl and M12 conducting. In reality the two inverters are not physically identical. which in reality would not last. one inverter would assume the ON state. The physical imbalance can be reproduced in SPICE2 by initializing the drain voltage of MIl to 5 V (V (2) = 5) and the drain voltage of M12 to 0. The latter value is roughly equal to VOL estimated in Example 4.
25 V(2)=5 .000 DEG C NODE VOLTAGE Figure 4. NMOS FLIPFLOP * * CIRCUIT DESCRIPTION COMES * .138 4 DC ANALYSIS NMOS FLIPFLOP * .OPTION NOPAGE 2 3 1 3 3 1 2 2 1 0 0 2 0 1 5 0 0 0 0 EMOS DMOS EMOS DMOS w=40U W=10U w=40U W=10U L=10U L=10U L=10U L=10U MIl ML1 MI2 ML2 VDD * * * * .0000 = 27.WIDTH OUT=80 . NODESET.NODESET V(1)=0.0000 NODE TEMPERATURE VOLTAGE 3) 5.END **** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 2.2758 NODE 2) VOLTAGE 5. .2701 NODE 3) TEMPERATURE VOLTAGE 5.OP .2701 NODE 2) VOLTAGE 2.0000 = 27. NODESET.OP HERE * .16 SPICE2 bias solution of a MOS flipflop with .MODEL EMOS NMOS VTO=l KP=20U .5 .MODEL DMOS NMOS VTO=3 KP=20U GAMMA=.15 SPICE2 bias solution of a MDS flipflop without .END **** NODE 1) SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.000 DEG C NODE VOLTAGE Figure 4.
. PLOT control statement. DC V/Iname1 startl stopl stepl <V/Iname2 start2 stop2 step2> .. transfer curves.alysis types of the bc mode. the major difference from ..SUMMARY 139 solution. .7 SUMMARY . Node voltages can be initialized for a DC computation using the following statement: . OUT_var. results are stored in the output file only for specified circuit variables.SENS OUT_varl <OULvar2 . . 4. NODESET is that node voltages are forced to the values specified by the user in the • IC statement and are not corrected after an initial pass.. Examples have shown how to apply the various DC analyses to specific circuit problems. > All circuit element values and model parameter values are defined at the nominal temperature. and result processing are also outlined as part ofthe analysis overview. which defaults to 27°e. The general format of the output request is . may differ from the initialization values. node2. This chapter has presented an overview of the SPICE analysis modes and has described in detail the an.. > Note that the final values of the voltages at the nodes nodel. which can be voltages or currents: v (nodel <.NODESET V(nodel)=valuel <V(node2)=value2 . Analysis parameters. and sensitivityare specified by the following control lines: . > With the exception of the DC operating point information.. The DC analysis typesoperating point. PRINT/PLOT AnalysisTYPE OUT_varl <OUT_var2. TEMP templ <temp2 . > <ploUimits> In the DC mode. TF OULvar V/Iname . The ambient temperature for the circuit analysis is defined by . respectively.. 'output variables. TNOM. AnalysisTYPE can be only DC.OP ...node2> ) I (Vname) The output variables for a • DC transfer curve analysis can be saved either in tabular or lineprinter plot format using the • PRINT or .. smallsignal transfer function..
The simulation of MOS integrated circuits using SPICE2. Memo UCBIERL M8017 (March). Meyer. 1988. Gray. G. D. P. Vladimirescu. Motorola Inc. A. and S. and R. G. New York: McGrawHill. New York: John Wiley & Sons. A. REFERENCES Antognetti.... AZ: Author. Analysis and Design of Digital Integrated Circuits New York: McGrawHill. and G.. P. .140 4 DC ANALYSIS . and H. 1988. Motorola Semiconductors Data Book. 3d ed. R. Phoenix. Analysis and Design of Analog Integrated Circuits. Jackson. Semiconductor Device Modeling with SPICE. 1993. Hodges. 1981. Massobrio. Liu. 1983.
In AC the node admittances are complex. 4J. and can also be expressed as magnitude. The periodicity factor. In the frequency domain the voltages and currents of the circuit are also complex numbers.Five AC ANALYSIS 5.1 INTRODUCTION In AC mode SPICE computes the frequency response of linear circuits. 141 . Vth = kT / q. sinwt. is implicitly assumed for all variables in an AC analysis.l) where w = 27T f is the angular frequency measured in radians per second andfis the frequency in Hertz.2) 4J = Phasors consist of a real part. and phase. VR. called phasors: v IVI = = VR + jVI = IVieN J~ + Vi arctan ( ~~ ) (5. VI. Small input signals. are assumed for nonlinear circuits that are linearized around the DC operating point. lVI. and an imaginary part. frequencydependent entities of the form Y = G + jwC + _1_ jwL (5. with amplitudes less than the thermal voltage.
the starting frequency.AC LIN 1000 1K 1MEG The first statement divides the frequency interval between 1 kHz and 1 MHz into three subintervals. • NOISE. 5. 5. DISTO.2.AC OCT 4 1K 1MEG . which is described in Sec. 5.AC. or linearly (LIN).4. which becomes the reference for linearizing nonlinear circuit elements. This analysis provides meaningful results if there is at least one independent source with a specified AC value in the input circuit. The following statement specifies the frequency interval and scale: • AC Interval numpts fstart fstop where Interval is one of the three keywords that indicate whether the frequency varies by decade (DEC). and. 5. for the linear interval numpts is the total number of frequency values betweenfstart andfstop. for analysis of distortion due to semiconductor device nonlinearities. with the last analysis at 1.024 MHz. • PZ. . The 10 frequency values in each subinterval are selected on a logarithmic scale. by octave (OCT).5. since fstop = 1000fstart and 210 = 1024. where f1 is the starting frequency of the subinterval. and fstop. SPICE3 also offers a polezero analysis. presented in Sec. The points in each interval are selected on a logarithmic scale. betweenfstart. the final frequency.AC DEC 10 1K 1MEG . with the endpoint of each subinterval being h = 10II. presented in Sec. The variable numpts specifies the number of frequency points used per interval. The circuit is evaluated at 30 frequencies. for input and output noise computation. Prior to an AC analysis SPICE always computes the DC operating point.3. 5. four per octave. EXAMPLE 5. Solution The following three •AC statements cover the same frequency range but cause circuit evaluations at different frequency points: . These are . The second statement divides the frequency range into subintervals defined by the following relation between endpoints: h = 2f1.1 Describe the differences in the AC analysis for the three types of intervals. presented in Sec. A total of 41 circuit evaluations are performed. for a frequency sweep.142 5 AC ANALYSIS SPICE2 supports several smallsignal analysis types in the frequency domain.2 AC FREQUENCY SWEEP This analysis computes the values of node voltages in the circuit over a specified frequency interval. Ten subintervals are needed.
because it is consistent with a Bode plot of the circuit response. sketch its Bode plot. contain additional information besides the type. and PSpice needs either a PRINT/PLOT line or a . The results of an AC analysis can be viewed in either tabular or lineprinter format by adding one or more of the following statements: ACOULvarl <ACOULvar2 • PLOT AC AC_OUT_varl <ACOUT_var2 • PRINT AC > > <ploLliml. The decade is the most commonly used frequency interval.2 Derive the transfer function V3/ Vj of the bridge. IVI or III Phase of complex number Decibel value of magnitude. The extra characters contained in the output variable's name differentiate among various representations of complex numbers. The accepted names for ACOUT_var are the following: VRor IR VI or II VMor IM VP or IP VDBor IDB Real part of complex value Imaginary part of complex value Magnitude of complex number.1..AC FREQUENCY SWEEP 143 The third statement divides the frequency range in 1000 equal parts. 20 loglO(IVI) or 20 loglO(!II) As in DC analysis a current output variable is specified as l(Vname) where Vname can be any voltage source in the circuit description. One thousand evaluations are necessary in this analysis. V or I. AC_OUT_varl.AC analysis performed with SPICE. EXAMPLE 5. For R Rj = R2 and C = Cj = C2 it is equal to: R2C2S2 R2C2s2 = + 2RCs + 1 + 3RCs + 1 (5. as in Eqs. Solution The transfer function can be derived from the KVL and the BCE relations. 5. and the node numbers. and verify with an . PRINT AC or • PLOT AC statement is necessary in order for SPICE2 to perform the analysis. SPICE3 does not require an output statement. . ploLlim2> Output variables for the AC analysis. and the frequency varies linearly betweenfstart andfstop. PROBE line.T circuit shown in Figure 4. At least one.2.3) . .
The two zeros are equal and are ZI = Z2 = 103 rad/s. the • PROBE line should be added in order to save all the phasors of the circuit. of the magnitude in decibels. of the voltage at node 3 to be saved in the output file. see also Sec. s = (J" + jw.AC * . in order to be able to represent the Bode plot (Dorf 1989). a polezero analysis can be performed in SPICE3. The graphical representation validates the above hand calculations. BRIDGET * V1 C1 C2 R3 R4 1 1 2 2 1 0 2 3 0 3 CIRCUIT 12 AC 1 1u 1u 1k 1k DEC 10 10 10k .144 5 AC ANALYSIS where s is the complex frequency. Because it attenuates signals of a given frequency.82.7.1. VP ( 3 ) .3. VDB ( 3 ) .WIDTH OUT=80 * PSPICE ONLY *. The quadratic equations in the numeratorand denominator must be solved for the zeros and poles. The • PLOT AC statement requests a lineprinter plot. When this example is run on PSpice.5. 102 rad/ s 7 61Hz P2 = 3 2 1 RC The locations of the poles and zeros point to a dip in the frequency characteristic centered around 159 Hz. this circuit is also called a notch filter. The two poles surround the double Zero on the negative real frequency axis and are 3 PI + 2 J5 J5 1 RC . similar to the one of Figure 1. respectively. corresponding to 159 Hz. Note that a decadic interval is specified and the transfer function requested is from 10 Hz to 10 kHz. END The Bode plot of VDB (3) and VP (3) is reproduced in Figure 5. .PROBE * . The SPICE input for the circuit is listed below.PLOT AC VDB(3) VP(3) . In addition to the frequency sweep. and the phase. 5.
The AC amplitude of lA at the input scales the resulting complex voltages and currents to represent the transfer functions with respect to the input. CIC = 2pF. A value different from 1. Add the values of the BE and BC junction capacitances to the model parameters: CIE = IpF. EXAMPLES.a 5" 0CD ::2: '"CD 3 5 10 CD (J) 4 100 Frequency. A .4) Several statements must be added to the SPICE2 input for the onetransistor amplifier in Figure 4.2 and the modified SPICE2 input in Figure 5. First.3.AC FREQUENCY SWEEP 145 0 10 lD "0 "0 1 5 OJ Q) (J) ::T cD 2 0 'c Cl ro . Solution The transfer function of interest is gm f3(jw) g'Tr + jw(C'Tr + CIl) = (5. Identify important frequency points.1 Magnitude and phase of the bridge. node 1: IIIOACI This source has a zero DC current and therefore does not disturb the DC bias point.3 Find the frequency variation of the current gain of the onetransistor amplifier of Figure 4. the input signal source Ii must be connected to the base of Ql.3 by running an • AC analysis.T transfer function.3. Hz 1000 Figure 5. The equivalent smallsignal circuit for the frequency sweep of the current gain is shown in Figure 5.
6 (FIG.MODEL * * QMOD NPN CJE=lP CJC=2P .2  ~    Currentgain amplifier: (a) amplifier circuit. 5. (b) smallsignal equivalent. *******01/14/89 ONETRANSISTOR **** ******** CIRCUIT SPICE 2G.PLOT AC IDB (VMEAS) IP (VMEAS) .lMEG lOG .000 DEG C *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 * II01AC1 VMEAS 4 2 CSHUNT 4 0 .2) 3/15/83 ********17:36:16***** INPUT LISTING TEMPERATURE = 27.1U * . .AC DEC 10 O.END Figure 5.3 SPICE2 onetransistor currentgain circuit with bias information.WIDTH OUT=80 .146 5 AC ANALYSIS o mom C I Ii + RB r" CT"  gmVbe Rc VMEAS +  w Figure 5.OP .
3 147 .000 NODE 3) VOLTAGE 5.23E+03 O.000 1.7934 NODE 2) VOLTAGE 2.0000 NODE 4) DEG C VOLTAGE 2.000 1.00D12 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.103 2.000 1.00E+12 1.793 2.124D03 O.OOE+OO O.OOODtOO VCC VMEAS TOTAL POWER DISSIPATION 1.72E12 1./ .897 100.13E02 1.' Figure 5.000 8.30E+09 (continued) MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT .OOE+OO 1.000 DEG C **** BIPOLAR JUNCTION TRANSISTORS Q1 QMOD 2.000 4.OOE+OO 100..**** TYPE IS BF NF BR NR CJE CJC BJT MODEL PARAMETERS QMOD NPN 1.10E03 0.2.06D02 WATTS **** OPERATING POINT INFORMATION TEMPERATURE = 27.10B05 2.00012 2.00D16 100.29E12 O.000 1.8967 VOLTAGE SOURCE CURRENTS NAME CURRENT .000 DEC C **** NODE 1) TEMPERATURE =27.8967 TEMPERATURE = 27.
and the Bode plot is shown in Figure 5. because VEE is positive.18. for the AC input amplitude proves useful when the output of a circuit needs to be calibrated at 1 V. because VBe is negative.103. C has increased. A decoupling capacitor. This value is very close to the one computed in Eq.6 is very useful for adding AC input signals or for purposely introducing an open circuit in DC without SPICE2 flagging the error LESS THAN TWO ELEMENTS CONNECTED AT NODEx.23. 7T . connected to the collector in parallel with Re is equivalent to a short at high frequencies and an open circuit at DC.19.109 . 3.3. Eq.6) The frequency interval of interest is therefore between 10 MHz and 10 GHz: . 3. 5. A dummy voltage source. or 0 dB. and the zerobias junction capacitances values have been used for C and CIL" This pole corresponds to a 3dB frequency of 43 MHz.4.3. iT. the AC component of the output current 10 must be separated from the DC component and measured.27. The unitygain frequency iT. limit the gain bandwidth of the transistor.J = 1. and CJL has decreased.AC DEC 10 10MEG lOG Last. 27T Hz = 4. which are omitted in this example.20. The input circuit with the bias point information is listed in Figure 5.3 GHz (5.5) The value of r has been taken from the bias point computation in Figure 4.. These capacitances together with the diffusion capacitances. Second.4.6. Fourth. VMEAS must be added in series with CSHUNT to measure the output current. 10• Third.PLOT AC IDB(VMEAS) IP(VMEAS) It produces a Bode plot of the magnitude in decibels and phase in degrees of the current transfer function. 5.14. is two orders of magnitude higher: 7T iT = {3F/[3 = 100. In the OPERATING POINT INFORMATION (OPI). 3. The zeroDC offset current source connected above and in Example 4. section note that the values CPI and CMU have been modified using the actual junction voltages VEE and VEC according to Eqs.10 9 rad s / (5. an AC control statement is needed. defined in Eq. CSHUNT. 027. and 3.148 5 AC ANALYSIS or V. the zerobias junction capacitance values must be added to the •MODEL statement of the npn transistor.4.. The frequency range of interest can be estimated roughly by locating the pole of the current gain at r (C 7T 7T w{3 = 1 7T + C.1012 1 rad s / = 0. Also listed in this section is the value of the unitygain frequency. the output control statement must be added: .
C1> CC1> <0 :2: m C1> (J) 25 60 20 80 15 10 Frequency. is located where (5.98 GHz and 5 GHz.) The unitygain frequency is located where the magnitude curve crosses the OdB mark. This frequency is between 3. Semiconductor devices produce shot noise. This limit is imposed by the noise that is generated in electronic components. (These accurate values are obtained with a • PRINT AC statement.81 MHz. From the AC plot the midfrequency magnitude of the current gain is 39.4 Bode plot for the onetransistor currentgain circuit. and burst noise (Gray and Meyer 1993). 5. A common . The pole position.7) which translated into decibels is equal to . Both /r3 and iT derived from the AC plot confirm the above hand calculations. The next step is to check the values of f{3 and iT in the AC plot. f{3. flicker noise.28 dB and the phase to 40° at 39.3 dB below the midfrequency magnitude of f3F.3 NOISE ANALYSIS There is a lower limit to the amplitude of a signal that can be processed by electronic circuits. Noise characterization of a circuit can be performed by adding to each SPICE component a noise generator.93 dB. The phase of the current gain at /r3 is 45°. The magnitude drops to 37. Noise generation has a random character and can be due to a number of phenomena. MHz 100 Figure 5. which is approximately equal to the value of f3F = 100. The most common is the thermal noise generated in resistors.NOISE ANALYSIS 149 45 IDB (VMEAS) 40 0 al ""0 ""0 35 20 "1J III (J) :T al "c Ol •• (lj 30 40 .
A meansquare value is used for noise sources because the phenomena underlying the chargeflow mechanism are random. inductors.f. {i or v2. and controlled sources are noisefree.. Capacitors.105 eV/K. Noise source . in semiconductor circuits. The total effect of all the noise sources at the output of the circuit is obtained by adding all the meansquare values of the noisy elements reflected at the output: n V~ut = ~ i=1 vt (5.9) where k..f. v2/ I::. The noise current or noise voltage generators associated with different elements are characterized by a meansquare value. The spectral density is measured in V2/Hz or A2/Hz. The noise generators of the different elements in a circuit are uncorrelated. of the noise source. The theoretical mean square of the noise voltage source in series with the noisefree resistor (see Figure 5. some types cover the entire frequency spectrum uniformly and are also known as white noise. electrons and holes.5 of a resistor.f or {i/ I::. A useful measure is the spectral density.150 5 AC ANALYSIS origin of the noise phenomenon is the conduction of electric current by individual carriers. The best known noise behavior of an electronic component is the generation of thermal noise in a resistor.2 IR Figure 5.5) is given by Vk = 4kTR/1f (5. whereas other types are greater at one end of the spectrum than at the other. measured in degrees Kelvin. Tis the absolute temperature. and I::. equal to 8. The various types of noise have different frequency behaviors. is Boltzman's constant. of the measurement.f is the frequency bandwidth G . respectively.62..8) Noisesource values are proportional to the frequency bandwidth.. SPICE models noise in resistors and all semiconductor devices. R is the resistance. I::.
AC request.6 Noise sources of the onetransistor amplifier. is shown in Figure 5. IB or Ie: i~ = 2qIBtif 2qIetif (5. and i~. Vth. The equivalent input noise is obtained by dividing the output noise by the transfer function of the circuit and represents the measure of all noise sources concentrated in a single noise source at the input. . V(nl <. and therefore the analysis can be performed on the linear equivalent of a nonlinear circuit. This report can produce a large amount of printout.NOISE ANALYSIS 151 of the measurement. The noise analysis is performed by SPICE in conjunction with an .4kTGtif R (5.11) (5. The latter approach is used in SPICE because of the ease of adding the contribution of current generators in nodal equations.AC and the •NOISE control statements must be present in the input file.10) with G = 1/ R. a report on each noise source's contribution can be generated by SPICE2 at specified frequencies.5.12) G= The meansquare values of the noise sources are small compared to the thermal voltage. If only one node B + Ii r" Figure 5. Additionally.n2» V/Iname nums n2» which defines the twoport connections of the circuit for the noise computation. The general form of the • NOISE control statement is . SPICE computes the output noise voltage at a specified output and an equivalent input noise voltage or current.6. respectively. as shown in Figure 5. depending on whether the circuit input is defined by a voltage or current source. defines the output port as a voltage between nodes nl and n2. i~. The meansquare value of each source is proportional to the corresponding DC current.NOISE V (nl<. both the . The smallsignal equivalent model of a BIT with the shot noise sources of the base and collector currents. The major source of noise in semiconductor devices is associated with the flow of DC current and is known as shot noise. Another way of representing the noise contribution current generator in parallel with meansquare value is to connect a i2 .
the frequency interval specified in the . VII name. SPICE2 can list the individual contribution of each noise generator at given frequencies. which is the default. The optional qualifiers differentiate between magnitude. at Viiname. If. n2». then SPICE2 does not generate any output related to the two statements. at the output nodes defined in the • NOISE statement.AC statement. At least one resulting noise value must appear on a • PRINT or • PLOT NOISE statement. The number of noisesource summaries for a DEC interval with numpts frequency points per decade and a number of frequency decades in the intervalfstart tofstop equal to decades is equal to decades' numptsj nums + 1. A zero or the absence of a value for nums disables the individual noisesource report. as specified in the •AC statement. of which the input is VINl and the output is node 11. The general form of the output request is • PRINT NOISE ONOISE < (MtDB) > <INOISE ONOISE«MtDB) < (MtDB) > > . and request six noisesource summaries. and INOISE is the equivalent input noise. M. define the twoport circuit. voltage or current. in addition. which can be a voltage or current source and must be present in the circuit description. The results of a noise analysis can be requested in tabular form with a • PRINT statement or as a lineprinter plot with a • PLOT statement. EXAMPLE 5.NOISE line.PLOT NOISE > <INOISE«MtDB»> ONOISE represents the total noise voltage. and decibels. The input of the twoport circuit is identified by an input source.4 . a summary of each noise source value is listed in the result file once every nums frequency points in the intervalfstart to fstop. the value 10 is missing from the • NOISE statement. DB. V(nl <.The output noise and the input noise are computed at all frequencies betweenfstart andfstop. No output is generated in the absence of a • PRINT or • PLOT statement for ACor NOISE. also defined by the .PLOT NOISE ONOISE to the above two statements causes SPICE2 to produce a lineprinter plot of the total rootmeansquare (rms) value of the output voltage noise at node 11.AC DEC 10 1K 100MEG .NOISE V(ll) VIN1 10 The above two statements define the frequency interval. one for each decade. The addition of the statement .152 5 AC ANALYSIS is specified. from fstart = 1 kHz to fstop = 100 MHz. . the output is between it and ground.
1017 y /HZ A2/Hz 2 ~f = 2qIB = 2.1 .12: ~ R} a 2 = 4kTRB = 1.6. CSHUNT net. and the equivalent input noise for the onetransistor amplifier in Figure 5.6.2.1016 y2/Hz = 6.6. Eqs. 1015 y /Hz 2 ~R.2.9 to 5. The contribution of the noise sources connected at the base of the transistor can be obtained by multiplying the meansquare values of i~b and i~ by the square of the transfer function Ii. First. All contributions to the output noise voltage are spectral densities of the meansquare values.10 24 22 A /Hz A /Hz 2 2 = 2.105 ~f = 2qIc '2 = 6. as defined Vol in Sec. The value of the transfer function at midfrequency. the contributions of the two BJT noise currents are evaluated: 72R2 l~f = 6. = 4kTRc .6.1. 10 The contribution of each of the above sources to the output noise voltage is calculated next.1. 1020. 1020.72.1014 y2/Hz ~A2 l~/ .72. 5. 4. 105 y2/Hz = 3. 1019 .6.5 Compute the contribution of each noise source to the output voltage noise. the total output noise. 103 y2/Hz = 1.4.1019.1.72. Check your results with SPICE2.2 = 1.72 .2. Solution The noise sources are shown in the smallsignal equivalent circuit of the onetransistor amplifier in Figure 5.2. 103 A2/Hz = 6. is The contribution of the noise sources connected to the collector is obtained by multiplying i~c and i~ by the square of the output resistance.NOISE ANALYSIS 153 EXAMPLE 5. The values of all noise sources can be computed using the definitions ofthermal and shot noise.6.2 without the VMEAS.
j and iieq/ !J. in order to have a noise analysis performed: . 107 Y/ Jlh.154 5 AC ANALYSIS The noise contributed by the base current at the output is significant because the current amplification available in BITs is high. The shot noise contributions from IB and IC are in agreement with the hand calculations. FN. Each NOISE ANALYSIS summary ends with the meansquare and rms values of TOTAL OUTPUT NOISE VOLTAGE. The RESISTOR SQUARED NOISE VOLTAGES are in agreement with the hand calculations. and the frequency variation of the rms values of va/ !J.6. Below the NOISE ANALYSIS header are the meansquare values of all individual noise sources computed at the output. The input circuit.NOISE V(2) II 10 . The last noise source of a BIT. A frequency sweep of the total output noise voltage and equivalent input noise current is also requested. The • NOISE statement defines node 2 as the noise output and current source I I as the noise input.j  I 4 ""2 . One summary report of each noise source is computed for each frequency decade. which is described in more detail in the reference text by Gray and Meyer (1993). RB. TRANSFER FUNCTION VALUE: V(2l/II . the summary report printed by SPICE2 of the noise analysis at 100 kHz. For this reason lownoise amplifiers often use PETs in the input stage.7. The FREQUENCY precedes each such report. and RE. The parasitic terminal resistors. All noise sources associated with a BJT and their values are listed under TRANSISTOR SQUARED NOISE VOLTAGES.PLOT NOISE ONOISE INOISE The element lines VMEAS and CSHUNT must be deleted since an output voltage must be sampled.3).j The total meansquare output noise voltage v~ is the sum of the meansquare values of all contributions.j computed from 100 kHz to 10 GHz are listed in Figure 5. is the flicker noise component. The following two statements must be added to the SPICE2 input used in the AC sweep (Example 5. Second. RC. resulting in 2 Va _ !J.7 Hz or 2. expressed as an rms value. the noise seen at the output due to Rc and RB is: Va3 2 !J. which is equal to zero in this case because no parasitic resistances have been specified in the •MODEL statement.6 9'1014y2/ !J.j ~ Von . generate thermal noise.
MODEL * .600D07 V/RT HZ **** TOTAL TRANSFER FUNCTION VALUE: V(2)/II EQUIVALENT INPUT NOISE AT II 9.646D17 TRANSISTOR RB 8.WIDTH OUT=80 .OOOD+OO 6.2) TEMPERATURE = 27.679D14 OUTPUT NOISE VOLTAGE 6.OOOD+OO O.AC DEC 10 O.OP .762D14 SQ V/HZ 2.OOOD+OO 6.NOISE V(2) II 10 NOISE ONOISE INOISE .6 3/15/83 ********11:40:54***** (FIG.PLOT SPICE 2G.625D12 /RT HZ (continued on next page) Figure 5.END *******02/03/89 ******** ONETRANSISTOR CIRCUIT ANALYSIS * .904D+04 2.2) TEMPERATURE = 27. .7 Results of onetransistor amplifier noise analysis.OOOD+OO O.130D16 NOISE VOLTAGES (SQ V/HZ) **** RB RC RE IB IC FN SQUARED TOTAL Q1 O.612D14 6.000 DEG C **** INPUT *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K RB 1 3 200K VCC 3 0 5 II * * 0 1 AC 1 QMOD NPN CJE=lP CJC=2P * . 5.693D16 O.NOISE ANALYSIS 155 *******02/03/89 ONETRANSISTOR ******** CIRCUIT LISTING SPICE 2G.000 DEG C **** NOISE *********************************************************************** FREQUENCY = 1. 5.6 3/15/83 ********11:40:54***** (FIG.000D+05 SQUARED HZ VOLTAGES (SQ V/HZ) **** TOTAL RESISTOR NOISE RC 1.lMEG lOG .
574D07 2.162D+06 3.892D08 3. 5..995D+06 2.512D+07 3. + *.566D08 1.012D+05 6.012D+08 6.523D07 2.111D10 4.000D12  .485D10 .*******02/03/89 ******** SPICE 2G.587D09 2.727D09 1.000Dll 3.2) TEMPERATURE = 27.028D10 6.162D+08 3.067D08 4.476D07 2.995D+07 2.310D+09 7.259D+08 1. 943D+07.310D+05 7.968D08 1....574D07 1.069D09 9.000D+05 1.211D10 7. 002D09 3.595D07 2.+)1.000D08 1.147D10 5.585D+05 1.310D+07 7. + *.245D08 7.+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + . +..000 DEG C **** INPUT LISTING *********************************************************************** LEGEND: *: ONOISE +: INOISE FREQ ONOISE *)1.943D+09 1.905D09 7.* * *.943D+08 1..245D08 9.585D+06 1.512D+09 3.855D10 7..162D+05 3.554D07 2.. ..162D+07 3.105D08 2. * * * * +.000D+06 1.102D09 1.259D+09 1.000D+09 1.230D10 7.175D07 2..407D07 2.259D+05 1.000D07 1. Figure 5.981D+08 5..7 (continued) 156 . .995D+08 2..012D+09 6.000D10 1.000D09 1..981D+09 5.000D06 .585D+07 1.. 3. * * * * * * * * * *  . * * * + * +* *+ * + + *.1.774D10 8. + + + + + + + + + + .675D10 5.807D10 6.000D+07 1.* * * * * * * * * * .343D07 1. .441D09 1.520D08 6.123.162D12 1.473D08 1...995D+05 2..585D+08 1.883D09 6.259D+07 1. 1.6 3/15/83 ********11:40:54***** ONETRANSISTOR CIRCUIT (FIG.003D07 1.'995D+09 2.278D09 5.512D+08 3..981D+07 5.799D07 1.943D+06 1.  .585D+09 1.310D+08 7.981D+05 5..512D+06 3.000D10 * * * * * * * * * * * * * * ..000D+10 1.209D09 2.309D07 2..600D07 2..007D09 4..226D09 1.943D+05 1.259D+06 1.587D07 2.512D+05 3.521D10 6..868D08 3..162D+09 3.388D10 7.012D+07 6.310D+06 7. 2.590D10 7.D07 9.162Dll ..564D10 8..981D+06 5.012D+06 6..000D+08 1..
and the equivalent input noise. ONOISE. and the .3dB frequency obtained in the above analysis.~~ DISTORTION ANALYSIS 157 at the corresponding frequency. The falloff of the output noise voltage is due to the 3 dB/octave rolloff of the transfer function. increases starting at 158 MHz. 100 MHz. I GHz. One such summary is printed also for I MHz. signals of frequencies 2Wl and 3Wl (and higher) are generated. a voltage or a current. The distortion measures derived below are computed for nearly linear circuits.13. (3(jw).3.14) intermodulation distortion terms of frequencies (WI + W2) and (WI . Avi. INOI SE. such as When Si is replaced by SI coswltin Eg. proportional to /2. Si: (5. 5. In the frequency plot entitled AC ANALYSIS. 10 MHz. Si = SI COSWjt + S2cosw2t (5. Harmonic distortion is generated in the circuit when one or more sinusoidal signals are applied at the input. So. and the EQUIVALENT INPUT NOISE AT II..4 DISTORTION ANALYSIS The signal applied to an active circuit is distorted because of a number of causes such as nonlinear elements and limiting. is due to the frequency dependence of the current gain. operating at the bias point and at midfrequency. is seen to fall off above 1 MHz. representing the second and third harmonic distortion terms. This analysis is not available in PSpice. 5. The output signal.. For small signals the cause of small distortions is the nonlinear IV characteristic of semiconductor devices.W2) are generated as well. .3dB frequency obtained in the AC frequency sweep. a2.7. these summaries have been omitted from Figure 5. can be expressed as a power series of the input signal. SPICE2 and SPICE3 compute several harmonic distortion characteristics using AC smallsignal analysis. and 10 GHz. Example 5. the output noise voltage. These terms are called sum and difference secondorder intermodulation . and the increase in equivalent input noise. Exercise Explain the difference between the . When a second signal is also present in the input signal.. are constants. al is the transfer function at midfrequency computed by SPICE2 as part of the • TF or •AC analysis.13) where ai. a3. where capacitances and inductances can be neglected.
Each distortion contribution is computed as distortion power in a designated load resistor.14 for the evaluation of the intermodulation distortion terms. The secondorder sum and difference intermodulation components. for a DEC interval with numpts frequency points per decade. and is equal to HD2 = amplitude of secondharmonic distortion signal amplitude of fundamental (5. HD2 is the fractional secondharmonic distortion. The frequency of the first signal. The normalized thirdharmonic distortion magnitude. is computed similarly. A summary of each distortion source in the circuit is listed in the result file once every nums frequency points in the interval from fstart to fstop.wz). Associated with each component of the smallsignal equivalent model of a transistor is a distortion contribution at the output of the circuit. the total harmonic distortion of a given order is obtained by summing up all individual contributions. The thirdorder term in the power series of Eq. in Eq. 5. both an •AC and a • DISTO statement must be present in the input file. is the frequency being swept in .AC statement. f]. 5.16) The last distortion measure computed by SPICE2 is DIM3. A resistor with the same name must be present in the input file. The number of summaries can be related to the type of frequency interval. using the amplitude of the thirdharmonic distortion signal. 8z.13 produces thirdorder intermodulation terms at frequencies (2wz :t wd and (2w] :t wz).158 5 AC ANALYSIS components. of the second input signal. A zero or the absence of a value for nums disables the report on individual distortion sources. The small distortions measures defined above are computed by SPICE2 in conjunction with an AC smallsignal analysis. The expressions hi II and 8z define the frequency. h. and decades decades in the interval from fstart to fstop. The following quantities are computed by SPICE2 as a measure of the different distortion components. specified in the . and amplitude. are computed from the following equation and under the assumption that two signals are present at the input: 1M2 = amplitude of secondorder intermodulation amplitude of fundamental component (5. of frequency 2w] in the absence of the second signal. The general form of the distortion control statement is . decades' numptsl nums + 1 summaries are printed. the normalized thirdorder intermodulation component of frequency (2w] . HD3.13 by 8] cosw]t and ordering the terms of the fundamental and the harmonics. 81M2 and DIM2.DISTO RLname <nums <hi II <Pre! <8z»» RLname is the name of the load resistor for computing the power contribution of the distortion. respectively. 8z coswzt. the frequency interval specified in the •AC statement.15) The expression of HD2 as a function of the power series coefficients is derived by replacing 8i in Eq. 5.
and x stands for any of R. for phase. Va. and DIM3 have the meanings defined above.5 The above two statements request the computation of the small distortion measures in the load resistor ROUT over a frequency interval from 1 kHz to 100 MHz. M. HD3. DIM2. and DIM3 at 1 kHz.17) By default SPICE2 uses 1 mW for P ref..6 . SIM2. a value of It = 0.PLOT DISTO HD2«x) > HD3«x» > HD2.AC statement.PRINT DISTO HD2«x) > HD3«x)> SIM2«x) > DIM2«x) > SIM2«x) > DIM2«x) > + + DIM3«x) > DIM3< (x) . At least one distortion term must appear on a • PRINT or • PLOT DISTO statement. measured in the load resistor RL is hi hi (5. HD3. HD3.16. according to Eqs. which is the default. The distortion terms are computed at all frequencies betweenfstart andfstop as specified in the . which serve as reference for deriving the distortion measures HD2. for logarithmic representation.. The rest of the data in the • DISTO statement define the second signal and reference output power level. The frequency of the second signal 12 is set to 0. for magnitude. Example 5. and 10 MHz.AC DEC 10 1K 100MEG . according to the . The general form of the output request is . for real.7 provides more insight into the derivation of the distortion components of the onetransistor amplifier. 5. and . and DB. For a given value of RL both the amplitude Va and 51 can be calculated. SIM2. EXAMPLE 5.15 and 5. The variable P ref is the power used as reference in the computation of the distortionpower terms in resistor RLname. Pret.9 is used by SPICE2 and 52 defaults to 1.95fl.AC statement specification there are 10 frequency points per decade. 100 kHz. DIM2.DISTO ROUT 20 0.95 1M 0. I for imaginary. The power of the output signal. P. The value 20 in the • DISTO statement establishes the summary to be printed once every 20 frequency points resulting in the three summary frequencies mentioned above. The output produced by SPICE2 will consist of three summaries of all distortion sources and the total distortion terms HD2.DISTORTION ANALYSIS 159 the AC analysis. The frequency sweep of the distortion components can be requested in tabular form with a • PRINT statement or as a lineprinter plot with a • PLOT statement. If fl is not specified. .
3) and check the results using SPICE2. for all computed frequency points between 1 kHz and 100 MHz. The resulting distortion components reflect the actual input amplitude corresponding to P ref. the logarithmic values of the distortion components can be expressed in terms of dBm. If only the total distortion is of interest. by removal of the bias base resistor. such as . nums is set to zero in the • DISTO statement and a • PRINT or • PLOT DISTO statement is added. is preserved. The results of the •AC and • DISTO statements are detailed summaries of all distortion sources in the circuit. The computation of the distortion terms is presented in more detail in the following example. A voltage signal source of amplitude Vbel is also connected at the input. can be expressed as VBE = VBE + Vbe = VBE + Vbel coswt (5. and replacement of it by a bias source of value VBE = 0. Solution amplifier (Fig Expressions for the different distortion terms can be derived based on the exponential IV characteristic of the BIT. and the second intermodulation difference distortion. as shown in Figure 5. This simplification is necessary because distortion is a strong function of the input source resistance. RB.1 rnA. It should be noted that referencing distortion to the output power level uniquely determines the amplitude of the input signal producing that distortion. The onetransistor circuit is simplified. VBE. Pref is used to scale the distortion terms that the output voltage amplitude of the fundamental is equal to If Pref = I mW.8.18) .160 5 AC ANALYSIS the amplitude is 0. The value of P ref can contradict the AC amplitude of the input source. The total voltage applied at the base of Ql.5. equal to the BE voltage obtained with the base resistor such that the quiescent collector current. DIM2. EXAMPLE 5. Ie = 2.7934.7 Compute all distortion measures introduced above for the onetransistor ure 4. a unit often used in telecommunications: dBm distortion = 20logHD where 1 m W corresponds to 0 dBm. HD2. which is usually I V.PRINT DISTO HD2 HD2(P) DIM2 DIM2(P) which lists the magnitude and phase of the second harmonic distortion.
DISTORTION ANALYSIS 161 (1 V) COS rot 5V =+ Vee VBE =+ 0.20 can be expanded in a power series: " .21) .794 V I FigureS. (5...19) The total collector curren~.from Eqs. 5. . Vi 1<:: := Ie 1 + . is an exponential function of the total baseemitter voltage. and an AC component. the exponential in Eq.equal to Vbel.19 and 5. ie. .~e follows'. Because of the assumption of small nonlinearities. The resulting total collector current. + '2 V2 I Ie th Vi 2 +"6 V3 1 Ie th Vi 3 + . 5. VBE.. ie. Ie: ie = Ie + Iecoswt (5. has a DC component.S Simplified onetransistor circuit for distortion analysis..Ie = V Vi th Ie .20) where VBE has been replaced by the sum of its components.2 V + .21: Ie = ie .' Vth IVi IVi ( th )2 + 6 ()3 Vth [ +. where Vi is tlleinput s~gnal. Ie. ] (5.
Re = Pre! = 1 mW 1.333 Vth (5. 4 2.24) .22b) In order to evaluate the above expressions.= 0. The distortion terms follow naturally: (5.1i' for either Vi or Ie in Eq. using the relation So = ajSi.4 rnA Ie Ie 1.162 5 AC ANALYSIS The coefficients ai ofthe power series in Eq. Ie 2 ai 0 4 Ie (5.22b. a2 S = ~ . HD2 e The remaining distortion terms can be derived similarly: HD3 = 24' 1 ( Vth Vi )2 = 2 24' 1 (Ie )2 = 0.23) 1 Vi 1 Ie SIM2 = DIM2 = . respectively: 1 = . HD2 can be rewritten as HD2 = ~ .081 mho = 17mV The secondharmonic distortion is obtained by substituting 5..! The amplitude of the input signal Vi is 1.4 rnA Vi = aj = gm = 0.Ie = 4I _1.13 can be set equal to the coefficients in the above power series.22a or Eq. = . 5. assuming that Si = Vi and So = Ie.. Vi or Ie must be calculated.22a) or.4 V = = J2RePre! = = Ie J2~. 5.018 Ie 2 Ie (5. 1. Both values result from the equation of the output power in Re Po Vo = V ut: = 2 I i.4 __ 0 16 . .
455E+00 27.455E+00 DIM3 (DB) 2.8 and the distortion measures at 1 kHz computed by SPICE2 are listed in Figure 5.AC LIN 1 1K 1K .493E+01 Figure 5.668E02 DEG C **** DIM2 3.000 DEG C DIM3 5.DISTORTION ANALYSIS 163 DIM3 = 1 8".889E02 TEMPERATURE SIM2 3.PRINT DISTO HD2 HD3 SIM2 DIM2 DIM3 .PRINT DISTO HD2 (DB) HD3 (DB) SIM2 (DB) DIM2 (DB) DIM3 (DB) .000E+03 HD2 (DB) 1. (Ie)2 Ie = 0.25) The input statements for the distortion analysis of the onetransistor amplifier of Figure 5. 5.367E01 = 27. 548E+01 HD3 (DB) 3.683E01 HD3 1.4M VEE1 1 4 AC 1 * * .9.OP . Note that/start and/stop in the .000 DIM2 (DB) 9.9 SPICE2 distortion analysis results.END AC ANALYSIS FREQ 1.000 DEG C *********************************************************************** Q1 2 1 0 QMOD RC 2 3 1K *RB 1 3 200K * VCC 3 0 5 VEE 4 0 793. (Vi)2 Vth = 1 8".367E01 = **** AC ANALYSIS FREQ 1.447E+01 TEMPERATURE SIM2 (DB) 9.WIDTH OUT=80 .MODEL QMOD NPN *+ CJE=lP CJC=2P * .000E+03 HD2 1.AC statement have been set equal since only *******03/06/89 ******** SPICE 2G.6 (FIG. .DISTO RC * .054 (5.8) 3/15/83 ********11:10:26***** ONETRANSISTOR CIRCUIT **** INPUT LISTING TEMPERATURE = 27.
The results are stored in the output file if the following line is added to the input circuit: . (s .22 through 5. The polezero analysis computes the transfer function of the circuit represented as a twoport circuit: H(s) = Vo(s) Sj(s) = a (szd(szz)"'(sZn) (s . One of the keywords must be present. whereas in the latter case a separate analysis must be performed each time the twoport representation is redefined.164 5 AC ANALYSIS the total distortion terms at midfrequency are of interest. for circuits containing more than 20 charge storage elements the results must be interpreted carefully. SPICE3 and highend SPICE versions. The field following the node specification defines the type of the input. 5. The output for this analysis is always a voltage. such as SpicePLUS and HSPICE. In interactive mode the same command with the omission of the leading period must be typed at the SPICE3 shell prompt.. or both poles and zeros (PZ). CUR for current input and VOL for voltage input. One of the three keywords must be present. 5. The locations of poles and zeros can in general be inferred from a Bode plot. The distortion terms in dBm are listed in the SPICE2 output as well. •AC. The polezero analysis is very useful for relatively small circuits.pz) . V 0 is the output voltage. which can be either a current or a voltage. PRINT PZ ALL The same command without the leading period can be issued in interactive mode.PI)(S .5 POLEZERO ANALYSIS The frequency sweep. A noteworthy difference between the frequency sweep and the polezero analysis is that in the former case one analysis computes the transfer function from input to any node in the circuit.. should be computed. zeros (ZER). The general form of the polezero statement in SPICE3 is • PZ ni I ni2 no 1 no2 CURNOL POL/ZERIPZ where nil and ni2 are the input nodes and nol and no2 are the output nodes of the twoport representation.25. In many applications. the succession of several poles and zeros makes reading their locations from a frequency plot difficult and makes it necessary to obtain the actual values. and Sj is the input signal.26) where s = j w. The last field specifies whether the poles (POL). provide a polezero analysis.Pm) (5. The distortion terms computed by SPICE2 are in good agreement with the values calculated by hand according to Eqs. introduced above yields the frequency response of circuits in the form of a graph. such as filters or feedback circuits. .
SUMMARY
165
The bridgeT circuit, which has exemplified the .AC frequency sweep, is used below for finding the poles and zeros and double checking the Bode plots.
EXAMPLES.8 Use SPICE3 to compute the poles and zeros of the bridge T filter; compare the results with the hand calculations in Example 5.2 and the Bode plot produced by SPICE.
Solution
The SPICE3 input and results for the polezero analysis are shown in Figure 5.10 on page 166. Note that the • AC statement has been replaced by a • PZ line defining the input of the twoport representation between nodes 1 and 0 and the output between nodes 3 and O. Furthermore, the input is defined as a voltage. The output signal is always assumed to be a voltage. The output contains the two real poles and zeros of the transfer function, which are identical to the hand calculations carried out in Example 5.2. Note that the polezero algorithm usually runs into difficulties when the transfer function is complex and has multiple poles or zeros.
5.6
SUMMARY
This chapter has described the analyses performed by SPICE in the AC mode. The control statements for each analysis have been introduced as well as the specifications of output variables and resultprocessing requests. Several examples have been used to show how to apply the various AC analyses to practical circuit problems. The implications of smallsignal analysis for nonlinear circuits in the AC mode has been addressed in the examples. The AC analysis types, frequency sweep, noise and distortion analysis, and polezero computations are specified by the following control lines:
• AC Interval numpts fstart fstop •NOISE V(nI<,n2»
V/Iname nums
.DISTO RLname <nums <hl!J
<Pre! <52»» . PZ ni 1 ni2 no 1 no2 CURNOL POL/ZERIPZ (SPICE3)
Noise and distortion are frequencydomain analyses; therefore these statements must be used in conjunction with an • AC line. With the exception of the PZ analysis, results are stored in the output file only for specified circuit variables, AC_OULvar, which can be complex voltages or currents: Vx (nodeI <,node2» Ix (Vname)
166
5
AC ANALYSIS
BRID3E VI Cl C2 R3 R4
T FILTER 12 AC 1 1U 1U lK lK
*
1 1 2 2 1
0 2 3 0 3
*
.OP .PZ 1 0 3 0 VOL PZ .PRINT PZ ALL
* END •
Circuit: BRID3E T FILTER
Circuit: BRID3E T FILTER Date: Fri Apr 19 14:55:55 Operating Node
V(3)
1991
point
information:
Voltage 1.000000e+Ol O.OOOOOOe+OO 1.000000e+Ol Current O.OOOOOOe+OO bridge T filter polezero analysis
V(2) V(l)
Source vl#branch
Fri Apr 19 14:55:55
1991
Index
pole(l) 2.618034e+03, O.OOOOOOe+OO
pole(2) 3.819660e+02, O.OOOOOOe+OO
o
bridge T filter polezero analysis Index zero(l) 1.000000e+03, O.OOOOOOe+OO zero(2)
Fri Apr 19 14:55:55
1991
o
1.000000e+03,
O.OOOOOOe+OO
Figure 5.10
Input and results for polezero analysis of bridgeT circuit.
SUMMARY
167
where x defines the output format of the complex variable; accepted formats are Rand I, for real and imaginary part, respectively; Mand P, for magnitude and phase, respectively; and DB, for the decibel value of the magnitude. The output variables of a frequencydomain analysis can be saved either in tabular or linepeinterplot format using the • PRINT or . PLOT control statement, respectively. The general format of the output request is .PRINT/PLOT AC ACOUT_varl <AC_OULvar2 ...
> <ploLlimits>
REFERENCES
Dorf, R. C., 1989. Introduction to Electric Circuits. New York: John Wi1~y&: Sons. Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits, 3d ed. New York: John Wiley & Sons. ' .
"
J
,.
..• I
':r,
Six
TIMEDOMAIN
ANALYSIS
6.1
ANALYSIS DESCRIPTION The transient analysis of SPICE2 computes the time response of a circuit. This analysis mode takes into account all nonlinearities of the circuit. The input signals applied to the circuit can be any of the timedependent functions described in Chap. 2: pulse, exponential, sinusoidal, piecewise linear, and singlefrequency FM. In contrast, in AC analysis only sinusoidal signals with small amplitudes, for which circuits can be considered linear, are used. Timedomain analysis computes, in addition to voltages and currents of timeinvariant elements, the variation of charges, q, and fluxes, e/>, associated with capacitors and inductors. These are described by the branchconstitutive equations (BCEs) for capacitors and inductors defined in Sees. 2.2.3 and 2.2.5: ic VL
= =
dq dt
=
Cdvc dt
(6.1) (6.2)
de/> = L diL dt dt
where ic and Vc are the current and voltage of capacitor C and iL and VL are the current and voltage of inductor L. The BCE for resistors, Ohm's law, is timeinvariant. Two analysis types are supported in SPICE for the timedomain solution:
TRAN
FOUR
Computes the voltage and current waveforms over a given time interval Computes the Fourier coefficients, or spectral components, of periodic signals
168
TRANSIENT ANALYSIS
169
An additional utility for transient analysis, • IC (initial conditions), is used for specifying the initial voltages at selected or all nodes. An INITIAL TRANSIENT SOLUTION (ITS) precedes a timedomain analysis unless it is specifically disabled. It is a DC solution at t = O.
6.2
TRANSIENT ANALYSIS
The following statement is required by SPICE to perform a transient analysis:
. TRAN TSTEP TSTOP <TSTART <TMAX> > <UIC>
The analysis is performed over the time interval from 0 to TSTOp' but results can be output starting from a userdefined time, TSTART, to TSTOP; TSTARTis assumed to be o if it is not specified. TSTEP is the time interval used for printing or plotting the results requested by a • PRINT or a • PLOT. Note that SPICE2 and most programs derived from it use a different internal time step for solving the circuit equations, which is automatically adjusted by the program for accuracy. By default the internal time step is bound by the smaller of (TSTOPTSTART)/50 or 2. TSTEP. Although in most cases the SPICE internal timestep selection algorithm is accurate enough, there are situations when for better accuracy a user may want to restrict the maximum time step. This can be achieved by specifying the value of the maximum allowed internal time step TMAX. The data on a • TRAN statement are ordersensiti ve, and a value for TSTART must always precede TMAX. The timedomain solution is preceded by a DC solution, the ITS, which computes the initial values of voltages and currents necessary for the integration of the BCEs, Eqs. 6.1 and 6.2, or Eqs. 2.5 and 2.10. A user can avoid the initial transient, DC, solution by concluding the. TRAN statement with the keyword UIC (use initial conditions). In this case the initial value of every voltage and current is 0 except those voltages and currents initialized with the IC keyword in the element definition lines or the • IC statement. One scenario where UIC is useful is the computation of the steadystate solution without the transient response leading to it. For a correct solution the user must define the correct initial values for all chargestorage elements in the circuit.
EXAMPLE 6.1
Explain the meaning of the following transient analysis statements:
.TRAN In lOOn .TRAN O.lu 100u 90u .TRAN 100u 1m 0 lOu .TRAN IOn lu mc .PRINT TRAN V(6) I (VCC) .PLOT TRAN V(6) V(2,1) (0,5)
170
6
TIMEDOMAIN
ANALYSIS
Solution
The first statement specifies that a timedomain analysis is to be performed from time to 100 ns and that the results are to be output at a lns interval. The second statement requests that the analysis be performed to 100 Jls and that the results between 90 JlSand 100 Jls be output at a 0.1 JlSinterval. The third statement requests a long analysis to lms with results output every 100Jls but limits the internal time step to lOJls. Finally, the fourth. THAN statement requires SPICE to omit the initial transient, or DC, solution by concluding the statement with the Ule keyword. The desired voltages and currents resulting from a transient analysis are identified in a • PRINT or • PLOT statement. The keyword THAN must be present to identify the analysis type. The time interval and time step for the prints and plots are those specified on the • THAN statement. At least one • PRINT or • PLOT statement must be present in the input file for the analysis to be performed. In this example the values of V ( 6) and the current through voltage source vee are printed and V ( 6) and V ( 2 , 1) are plotted with a common voltage scale with values from 0 to 5 V at the output.
o
EXAMPLE
6.2
Compute the timedomain response of an RLC parallel circuit that at t = 0 is connected to a constant current source as shown in Figure 6.1. Verify the solution with SPICE.
Solution
The KCL applied to node 1 yields the following equation:
Cdvc + dt
.
lL
+ If
Vc
=
I
S
(6.3)
The BCE of the inductor, Eq. 6.2, yields a substitution for iL : diL Ldt leading after differentiation ential equation in vc:
=
Vc
(6.4)
with respect to time to the following secondorder
differ
(6.5)
The solution of this equation is of the form vc(t)
=
Aept
(6.6)
TRANSIENT ANALYSIS
171
t= 0
R 10kQ
Figure 6.1
Parallel RLC circuit.
which put in the differential equation above leads to the characteristic
equation: (6.7)
pZ
where a
+ 2a p + w5
=
0
=
_1_
2RC 1
=
5. 104SI
106 rad/s (6.8)
Wo
= 
jLC
=
The solution of the quadratic equation is
PI,
Z =
a::!:: JaZ

W5
=
a::!:: J(W5
 aZ)
=
a::!:: jWd
(6.9)
which is put in Eq. 6.6 to obtain vdt):
(6.10) a is the damping/actor, and Wd is the damped radian/requency (Nilsson 1990). Coefficients A I and Az are found from the initial conditions; at t = 0, vdO) = 0 and therefore Az = AI. Al is obtained by putting vdO) in Eq. 6.3:
172
6
TIMEDOMAIN ANALYSIS
The timedependent
function vc(t) is 1 . cIse at.sm Wdt Wd
Vc (t ) =
(6.11)
The angular frequency, w, is close to Wo because a is negligible by comparison; therefore the period is T
= 
27r Wo
=
6.28/Ls
(6.12)
PARALLEL
RLC CIRCUIT
IS 0 1 PWL 0 0 IN 1M 1 1M L 101M
*
C lOIN RIO 10K
* .TRAN
. END
lU 1000 .PLOT TRAN V(l)
The SPICE input file for this circuit entitled, PARALLEL RLC CIRCUIT, is shown above. A transient analysis for 100 /Ls is requested corresponding to approximately 16 periods according to the above calculations. The waveform computed by SPICE2 is shown in Figure 6.2 and has the damped sinusoidal shape predicted by Eq. 6.11. The complex algorithms in SPIcI~2 (see Sec. 9.4) can be verified to predict waveforms in agreement with the above handderived solution for this simple problem. According to Eq. 6.11, the amplitude of the oscillation at wot = 7r/2 (for example, at t = 7r/2 /LS for Wo = 106 rad/s) is
After solving for vc(t), one can put Vc of Eq. 6.4 in Eq. 6.3 to obtain a secondorder differential equation in iL(t):
(6.13)
This equation differs from Eq. 6.5 for vc(t) in that the righthand side is nonzero. The solution consists of the damped sinusoidal term, which is the natural solution, and an
which is equal to the input current of 1 rnA.5 1. therefore. represents the transient response.14) The SPICE waveform for iL(t) is shown in Figure 6.5 1. The example also outlined the .. whereas the forced solution is the steadystate response. JlS 60 80 Figure 6. we use a step function at t = 0+ described as a PWL current source. This second approach is equivalent to applying a step function at t = 0+ since all currents and voltages at t = 0 are zero.0 20 Time. It can be seen that once the oscillations die out the inductor current assumes the forced solution.TRANSIENT ANALYSIS 173 1.5 > G . 0. Exercise: Show that no oscillation can be observed in the SPICE solution if the not used when Is is a DC source. ure keyword is The previous example demonstrated the use of the transient analysis in SPICE for computing the response of a linear RLC circuit. In order to observe the oscillations in a circuit. An alternate way to achieve the same result is to use a DC current source at the input and to omit an INITIAL TRANSIENT SOLUTION by specifying the ure option in the • TRAN statement.2 The waveform vc(t) computed by SPICE. The natural solution.0 0. Explain the result.0 0.3. A few comments can be made at this point. additional forced solution: (6.
5 is equal to the following (Gray and Meyer 1993): a(s) 1 + a(s)f (6.15) .174 6 TIMEDOMAIN ANALYSIS 1.2 cannot sustain oscillations.5 Time. oscillator shown in Figure 6. The following example demonstrates the use of SPICE for computing the response of a Colpitts oscillator. connection between the equations describing the electrical circuit and the analysis parameters and solution computed by SPICE. which is shown in Figure 6. In the frequency domain the overall transfer function. the circuit has righthandplane poles. This can be achieved with a gain block connected in a feedback con~ figuration (Pederson and Mayaram 1990). The importance of the different analysis parameters is exemplified best by oscillators. A(s). Oscillations can be sustained only if the real part of the natural frequencies computed from Eq. connected in a feedback loop. or in other words.4 using SPICE.f. which are damped by the factor eat. a(s) (where s = (T + jw is the complex frequency)._~ 1. 6. EXAMPLE 6. Solution The passive RLC circuit in Example 6. I!S Figure 6.0 0. of a gain block.7 is positive.3 The waveformh(t) computedby SPICE.5 « E .3 Verify the oscillation condition and find the amplitude and frequency of the Colpitts .
I I I I I Als) L I S" f ~ I I Figure 6. f: I n= f 10 (6. The plot in Figure 6. .TRANSIENT ANALYSIS 175 0 i(' ie v" 0 if= ie + C. where T(s) = a(s)f. commonbase (CB) transistor network consists of capacitors (6.4 has the amplifier. The feedback C. and C2. The signal fed back to the input is must encircle the point (1.6 is known as the Nyquist The Colpitts oscillator shown in Figure 6. 6. The loop gain of the system. T(s).5 Feedback amplifier.4 Vee 10V Colpitts oscillator.17) s. QI connected in a feedback loop. 0) in the complex frequency plane as shown in Figure oscillate.6 in order for the circuit to diagram.16) where n can be referred to as the capacitive turns ratio and is equal to the inverse of the feedback factor. CD RE RB RL • L C2 o VEE 10 V o Figure 6.
176 6 TIMEDOMAIN ANALYSIS 1m T(joo) T(joo) =a (joo)J= _ gm2L(j (0) n 00=0 Re T(joo) n Figure 6.21) This corresponds to an oscillation frequency fo = 3. When oscillations build up.22) .36 MHz. (6.6 Nyquist diagram. A good approach to ensuring steadystate oscillations (Meyer 1979) is to dimension RL so that the initial loop gain is (6.18) The circuit is unstable.::====== J5' rad/ s = 21. The smallsignal gain a( s) of the CB transistor is (6.19) where Wo is the resonant frequency of the tank circuit in the collector of transistor QI : 1 1 Wo = JLC . and oscillations are initiated when the loop gain is T(jwo) a(jwo)f = =  gmRL n = 1 (6.20) 1012 with (6.1 . 106 rad/ s 106. the smallsignal approximation is no longer valid and the equivalent largesignal Gm must be considered. which is less than gm.450.
6. Eq. is a growing sinusoid that reaches a steadystate amplitude constrained by circuit biasing and loading. 6. The above expression shows that the higher the Q of the tuned circuit.24) where. of a parallel tuned circuit.23) The denominator can be compared with the characteristic equation of the parallel RLC circuit. The above equation is very important for understanding at what rate the oscillations build up. we need to bias the circuit. Eq.27 is also valid for series resonant circuits with the appropriate change in the definition of Q. It has a pair of complex poles leading to a timedomain solution.26) Putting Q in Eq. this can be achieved by setting the emitter current. Eq. defined by Q = R woL = woCR (6.24 leads to the following expression of the circuit response: vo(t) IX eKwot/Q sinwot (6. If gmRd n > 1. In order to complete the circuit specification. 6.11. and a resistor.27) where K is a constant dependent on the actual oscillator configuration. corresponding to complex poles in the right halfplane. 6. The oscillation buildup can be related to the quality factor. VEE.7. of the form (6.TRANSIENT ANALYSIS 177 The gain of the circuit including feedback is (6.24. Eq. The analysis of oscillators with SPICE can be tricky for certain circuits because a large number of periods must be simulated before oscillations can be observed. ex = _1 (1_ gmRL) 2RC n (6. the longer it takes to reach steadystate oscillations. the predicted solution. hE. Q. 6. using a negative supply.25) and represents the damping factor. RE: VEE = lOV . in this example.
103 n l.8) V . of QI.65.7. vo.22.VEE . or V ( 2) in SPICE. The value chosen for RL is 750 n.TRAN 20N 3U . Note that for the graphical output of Nutmeg or Probe. with results to be printed in the output file every 20 ns.178 6 TIMEDOMAIN ANALYSIS RE gm Ie = = 4. .65K VEE 6 0 10 PULSE 15 10 0 0 0 1 * * .PLOT TRAN V(2) I (VC1) . 6. The step function used in simulation is similar to the real situation of connecting a circuit to a supply before proper operation can be observed. the collector voltage.65 kO 0.OPTIONS LIMPTS=5000 ITL5=0 ACCT • END The results of the simulation. note that the negative supply is implemented as a step function using the PULSE source.0. The amplitude of oscillations at the collector. It is always desirable to kick the circuit in order for the program to find the oscillatory solution. Vo. the time step is used only to set a default upper bound on the internal integration time interval. 4.VBE = RE = adEE 099(10 . according to Eq. COLPITTS OSCILLATOR RB101 Q1 9 1 3 Mom VC1 2 9 0 VCC 4 0 10 RL 4 2 750 C1 2 3 500P C2 4 3 4. to 3 f.LS.MODEL Mom NPN RC=10 * . are shown in graphical form in Figure 6.5N L 4 2 5U RE 3 6 4.076 A/V = aF .96mA With the above values the minimum value of RL for which. the circuit oscillates is The SPICE input COLPITTS OSCILLATOR is listed below. The simulation is carried out for ten periods.
2. the maximum integration time step used by SPICE must be limited. A powerseries representation cannot be used because of the large value of Vi compared to Vth' The amplitude of Va derived above is in good agreement with the waveform in Figure 6. In order to obtain a smoother sinusoid. The waveform can be seen to be a piecewise linear approximation of a sinusoid.5 Time. 103 V = 2. The points actually computed by SPICE are apparent on the graph. can be verified at wo: = 0.54 V (6. of QI.5 Figure 6.TRAN 20N 3D 0 lON The new waveform resulting after replacement of the initial. IlS 2. This is achieved by specifying the TMAX parameter on the • TRAN statement: . Iii 10.7. TRAN line with the above line is shown in Figure 6.28) The incremental part of the collector current. 1. Ie. vo.TRANSIENT ANALYSIS 179 13 12 11 > } 10 9 8 7 0.8 and can be observed to be much smoother.95 for Vt/Vth > 6.7 Colpitts oscillator: collector voltage. is a function of b = Vt/Vth and is equal to 0. is approximated by a Fourier series (Pederson and Mayaram 1990) in which the ratio of the modified Bessel functions.9.750. .89.
180 6 TIMEDOMAIN ANALYSIS 13 12 11 > . that at node2 to value2. userdefined initial conditions enhance the accuracy and offer quicker access to the desired solution. Exercise Verify that oscillations can be observed for RL = 395 n but not for RL = 100 exercise should prove the validity of the oscillation condition derived above. initial values for node voltages can be set with the following statement: . This 6. Note that unlike voltages initialized by . Similarly. 4.8 Colpitts oscillator: more time points used for V ( 2 ) . and node voltages.Ie v (node]) =value] <V(node2) =value2 .3 INITIAL CONDITIONS The solution of the time response of electric circuits starts with the timezero values. n.. or initial conditions. which computes the initial conditions. Most SPICE programs support two types of userspecified initial conditions. and so on.IlS Figure 6.2. semiconductordevice junction voltages. As described in Sec. The steadystate timedomain solution of more complex circuits is reached faster if the user initializes voltages across capacitors. First. Initial values of charges on capacitors and semiconductor devices are also computed based on these initial voltages. A transient analysis in SPICE is preceded by an INITIAL TRANSIENT SOLUTION.6. > This command sets the timezero voltage at node] to value]. the •NODESET statement helps the DC solution to be found faster. as shown in Example 6.. currents through inductors." 10 9 8 7 Time..
which is different from the smallsignal bias solution (SSBS). In the absence of UIC an INITIAL TRANSIENT SOLUTION for the entire circuit is computed with the initialized nodes kept at the specified voltages. on the circuit solution. devicebased ICS have no influence ITS uses •IC voltages. which is the result of an . . IC. controlled sources. all the values in the timezero solution except the initialized node voltages are zero. the • IC statement. uses . transmission lines. inductors.IC no no yes yes no no yes yes Effects o( IC Combinations SPICE2/3 Initialization ITS is equivalent to SSBS ITS is equivalent to SSBS. If UIC is specified on the • TRAN line. Therefore the SPICE input file in Example 6. = 1 rnA through the inductor of Solution According to Table 6. The effect of the • IC statement differs depending on whether the UIC parameter is present on the. is different from SSBS. the devicebased Ie. and the UIC keyword. which are used only as initial guesses for the iterative process and then released to converge to a final solution. rest of initial values are zero No ITS. devicebased ICs have no influence No ITS. When initial values are specified both on devices and in an • IC stateme~t. EXAMPLE 6.INITIAL CONDITIONS 181 • NODESET. These values are used only in conjunction with UIC and have no effect on the INITIAL TRANSIENT SOLUTION. rest of initial values are zero Devicebased IC no yes no yes no yes no yes . Second. initial conditions for capacitors.4 Use a devicebased IC to set the initial current iL(O) the parallel RLC circuit in Figure 6. voltages defined by the • IC statement do not change in the final INITIAL TRANSIENT SOLUTION.2 is modified as shown below. and seIl1iconductor devices can b.OP request. IC voltages. Table 6. rest of initial values are zero No ITS. IC next.1 UIC no no no no yes yes yes yes . namely. uses devicebased IC first. The third modification in the RLC description listed below is the replacement of the PWL source used for Is with a DC current.1 summarizes the. In this table ITS stands for initial transient solution. uses devicebased IC. is different from SSBS ITS uses . a devicebased IC effects the solution only when UIC is present in the • TRAN statement.1.e set on a devicebydevice basis using the IC keyword. TRAN line. which in the presence of UIC has the effect of a step function. the devicebased values take precedence: Table 6. As many node voltages should be initialized as possible when the UIC parameter is set. all initial values are zero No ITS.1. effect of the different combinations of initial conditions.
TRAN 1US 100US UIC . Solution Following is the SPICE input for this circuit: RING OSCILLATOR VDD 11 0 5 MOS * M1 1 3 0 0 ENH L=10U w=40U M2 2 1 0 0 ENH L=10U w=40U M3 3 2 0 0 ENH L=10U w=40U . The next example will demonstrate the use of • rc for the correct initialization of a ring oscillator. according to Eq. Depletion NMOS: W = 5 j. L = 10 j. KP = 40 j.Lm.LA/y2. The enhancement and depletion transistors have the following device and model parameters: Enhancement NMOS: W = 40 j.Lm. This constitutes a very important observation: The fastest way to find the steadystate response of a circuit is to initialize as many elements as possible in the state they are expected to reach.3 y.Lm. VTO = 1.8 Y.5 Use SPICE to simulate the behavior of the threestage enhancementdepletion (ED) MOS ring oscillator shown in Figure 6. The explanation for this result is that the specified initial condition corresponds to the steadystate solution. as shown in Table 6.pwr TRAN V(l) .001 yI.Lm.1. fXAMPLf6. In the analysis of oscillators initial conditions must be used in order to shorten the simulation time during the buildup phase (the higher the Q of the circuit.2. LAMBDA = 0. because devicebased rcs have no effect.END WI INITIAL CONDITION The SPICE analysis results in a constant current iL(t) = 1 rnA without the damped oscillations observed in Example 6.9. Note that omission of the keyword urc from the • TRAN statement results in damped oscillations.LA/y2. the longer this phase lasts. The above example demonstrates the use of the devicebased rc and its applicability for finding the steadystate response. L = 10 j.182 6 TIMEDOMAIN ANALYSIS PARALLEL RLC CIRCUIT IS 0 1 1MA L 101MB IC=lMA C101NF R 1 0 10K .001 yI. 6. LAMBDA = 0.27). KP = 40 j. VTO = . CGSO = 20 pF/m.
10.9 NMOS ring oscillator.5U .MODEL ENH NMOS LEVEL=l VTO=1. with an • IC line: .INITIAL CONDITIONS 183 ~ ~ VDD 5V Figure 6.MODEL * .IC V(1)=5 V(2)=0 Resimulation of the circuit including the above line produces the waveforms shown in the graph of Figure 6.4E4 .5 V. settle at 2.PLOT TRAN V(l) V(2) V(3) (0.8 CGS0=20N LAMBDA=. nodes 1.OOl KP=. the outputs of the three inverters.2. An initial imbalance is necessary for oscillations to build up. and 3.5) If the circuit is analyzed as is. no oscillations are observed. Note that the data in the • IC statement are used to compute the INITIAL TRANSIENT SOLUTION in the absence of the UIC parameter. 5 V or 0 V.TRAN • END DEP NMOS LEVEL=l VTO=3 LAMBDA=.0lU . because initial conditions are set up in SPICE by connecting a Thevenin equivalent with a voltage .OOl KP=. The values in the initial solution are not always identical to the values in the • IC statement. this can be achieved by initializing the outputs of the inverters at high or low values. M4 11 1 1 0 DEP L=10U W=5U M5 11 2 2 0 DEP L=10U W=5U M6 11 3 3 0 DEP L=10U W=5U * .4E4 .
In other words. The Thevenin equivalent nets are removed only at the first time point in the transient analysis.184 6 TIMEDOMAIN ANALYSIS 200 Time.10 Waveforms at the outputs of the inverters in the ring oscillator.4 FOURIER ANALYSIS A periodic signal can be decomposed into a number of sinusoidal components of frequencies that are multiples of the fundamental frequency. These components of the signal are also referred to as spectral or harmonic components.29) where !ao is the DC component and the coefficients ah bk of the series are defined by ao = T 2 ft+T t v(t)dt v(t) cos(kwt)dt v(t) sin(kwt)dt (6. 6. a periodic signal can be represented by a Fourier series (Nilsson 1990): 1 v(t) = 2ao + L(ak k=! n coskwt + bk sinkwt) (6.30) ak = T 2 2 ft+T t bk = T ft+T t . equal to the initial value and a 10 resistor to the initialized node. ns 300 400 Figure 6.
.~Ak k=l cos(kwt . Because of the assumption of periodicity.32) In the timedomain mode SPICE can compute the spectral components. The Fourier coefficients defined in Eqs.FOURIER ANALYSIS 185 The coefficients ak and bk give the magnitude of the signal of frequency kw. A few remarks are necessary about the accuracy of the Fourier analysis in SPICE. Ab and the phase. of a given signal if the following line is present along 'with the • TRAN statement: • FOUR freq OUT_varl <OULvar2 ... For an accurate spectral analysis enough periods must be simulated that the circuit reaches the steady state. Only one • FOUR line can be used during an analysis. are voltages and currents the spectral components of which are to be computed. SPICE3 allows the user to define the number of harmonics to be computed. In electrical engineering a different formulation.30 are evaluated based on the values for OULvar computed at discrete time points. that is for the interval (TSTOPl/freq. 6. or the kth harmonic component. using TMAX on the • TRAN line. having only one periodic component.. is used for the Fourier series: 1 v(t) = n "2ao +. thus for good accuracy the maximum time step must be limited. o ULvar2. .cPk) (6. > In the above statementfreq is the fundamental frequency and OULvarl. TSTOP). cPb are given by (6. the Fourier coefficients defined above are computed based on the values of OULvar during the last period.31) where the amplitude. Only a singletone sinusoid has a single spectral component.FOUR lMeg V(3) I (VDD) This line added to a SPICE deck causes the computation of the spectral components of the voltage at node 3 and of the current through the voltage source VDD. magnitude and phase. The frequencies of the harmonics are multiples of the fundamental frequency of 1 MHz. SPICE2 and PSpice compute the first nine spectral components for each of the signals listed on the • FOUR line. which is at the oscillation frequency. . Example .
2 nF/m. VTO= 1 V. Ml: W M2: = W = 20 /Lm. KP= 10 /LAJV2. the output signal contains harmonics of the 20MHz input sinusoid.11 CMOS inverter. CGBO = 2 nF/m. The following line requests the computation of the harmonics for the output signal V ( 2 ) : . L 40 /Lm.DOMAIN ANALYSIS EXAMPLE 6. 5 /Lm.2 nF/m. = L = 5 /Lm. KP = 20 /LAJV2. CGSO= CGDO=0.6 Verify the spectral values computed by SPICE2 for the output signal of the CMOS squarewave clock generator shown in Figure 6. CGSO = CGDO = 0.11.186 6 TIME.. Solution Because the CMOS inverter is nonlinear. CGBO = 2 nF/m.FOUR 20MEG V(2) o {. The two transistors are described by the following model and device parameters: NMOS: PMOS: VTO = 1 V. .\ VDD 5V Figure 6.topeak amplitude of 5 V and a frequency of 20 MHz. A sinusoidal voltage source is applied at the input with a peak.
2N CGB0=2N 1N lOON (1. cPk> appear in the PHASE (DEG) column. The SPICE deck . as showI1 in Figure 6. vo(t) (V (2) ).5 V. Ak> are listed under FOURIER COMPONENT. The output signal.PLOT TRAN V(2) V(l) . V (2 ). PLOT TRAN I (VDD) . shown in Figure 6.for this ex'ample is CMOS INVERTER M1 2 1 0 0 NMOS W=20U L=5U M2 2 1 3 3 PMOS W=40U L=5U VDD 3 0 5 VIN 1 0 SIN 2. described in Sees 9.OP .MODEL PMOS PMOS LEVEL=l .12.5 20MEG VTO=l VTO=l KP=20U KP=10U . is a square wave. which is due to numerical inaccuracy.5 2.12. Note that if the above deck were used the output voltage would display some ringing. A l.5.4. 6. and the phases. For this circuit it is necessary to add the line . the magnitudes of the spectral components.5) .2 and 9.TRAN . simulation of two periods is sufficient for this circuit because no oscillations need to settle.MODEL NMOS NMOS LEVEL=l * + + CGID=.15 V. until 100 ns. and all the even harmonics are negligible. 2N CGBO=2N CGID=.FOURIER ANALYSIS 187 The period of the output signal is 50 ns.30.31.FOUR 20MEG V(2) . The results of the Fourier analysis are listed according to the formulation in Eq. and the phases normalized to cPl' The Fourier series coefficients can be easily checked with Eqs. the amplitude of the fundamental is 3. 2N . and the analysis is requested for two periods. of the fundamental. The results of the Fourier analysis are listed in Figure 6.12 can be expressed as follows: vo(t) = 0 for 0 < t < 2 T for 2 :5 T t <T . END The output waveform.13.OPTION RELTOL = 1E4 in order to obtain the waveform in Figure 6.CGSO=.29 and 6. In the Fourier analysis output two additional columns list the amplitudes of the spectral components normalized to the amplitude. The DC component computed by SPICE2 is 2. 2N CGSO=. This problem can be corrected by SPICE2 analysis option parameters. 6.
055E01 3. 791E+02 1.061E02 3.12 Squarewave signal V ( 2) at the output of the CMOS inverter.962E+01 2. 20 60 Figure 6. J I .74SE+00 . 40 Time. I.000E+OS 1.S9SE01 3.200E+OS 1. ns .000E+07 6. TOTAL HARMONIC = Figure 6.799E+02 1.692E01 2. I J .000 DEG C FOURIER COMPONENTS OF TRANSIENT 2.OOOE+OO 5.945E03 4. 716E+02 1.160E03 1.009E+01 4. 19SE+02 1. **** FOURIER ANALYSIS TEMPERATURE = 27. 593E+02 1.573E01 3.970E03 9.600E+OS 1.613225E+01 PHASE (DEG) 1.147E+00 S.561E03 3.555E02 1. I .3.000E+07 1. 80 .576E+02  .503637E+00 FOURIER COMPONENT 3. I.797E01 .362E02 4.13 Fourier analysis results for the squarewave voltage V ( 2 ) .000E+00 2.612E01 9. .951E01 1.000E+07 S.694E+01 2..7. .188 6 TIMEDOMAIN ANALYSIS 5 '\ 4 r '\ > 3 g > 2 o \. .941E03 6. 794E+02 1.907E01 DISTORTION RESPONSE V (2) DC COMPONENT HARMONIC NO 1 2 3 4 5 6 7 S 9 = FREQUENCY (HZ) 2. SOOE+OS NORMALIZED COMPONENT 1.946E01 1. 7S2E+02 PERCENT NORMALIZED PHASE (DEG) O.400E+OS 1. 425E+02 1.791E+02 1. \.000E+07 4.05SE03 9. .249E02 2.
are derived by solving the integral in Eqs.FOURIER ANALYSIS 189 The DC component. Ao. 6. The second and third NORMALIZED COMPONENTS listed among the Fourier analysis results . The first three harmonics.06 V The above coefficients scaled by the appropriate DC value are generally valid for any square wave. that is.18 V 0 2VDD 3'1T = = 1. note that the function is of odd symmetry: J(t) = J(t) Thus all coefficients ak are zero.5 V Before deriving the coefficients of the harmonics.V = 3. vo(t) also possesses halfwave symmetry.30 for the two values of vo(t) corresponding to the halfperiods of the waveform in Figure 6.. is Ao = 2ao = l' 1 1 Jo (T vo(t)dt = 25 V 1 = 2.5 = 1" 2'1T VDDCOS T b2 b3 = (2'1T) = . J(t) =  J(t . bl> b2.T /2) making all coefficients bk with even k equal to zero (Nilsson 1990). The TOTAL HARMONIC DISTORTION (THD) computed by SPICE is equal to (6. and b3. A useful application of the Fourier analysis is the evaluation of largesignal distortion.12: 2 bi = l' Jo 2 (T vo(t) sin(wt)dt T = 1'VDD TI2 t 10 2 Jo (T12 sin(wt)dt 2. The small discrepancies with the SPICE2 Fourier coefficients can be attributed to the imperfection of the square wave V ( 2 ) .33) In the design of many circuits the THD must be kept below a specified limit.
190
6
TIMEDOMAIN ANALYSIS
correspond to HD2 and HD3 in the AC smallsignal distortion analysis presented in Chapter 5. If the results of the two analyses are compared, the Fourier components should be scaled by the reference power, Pref, in the load resistor to match the values of HD2 and HD3. More detail on the two types of distortion analysis can be found in Chapter 8. Sinusoidal oscillators for various applications must have a small content of harmonics. It is instructive to compute the harmonic content in the output voltage of the Colpitts oscillator.
EXAMPLE 6.7
Use Fourier analysis to find the total harmonic distortion of the output signal of the Colpitts oscillator in Figure 6.4.
Solution
For an accurate estimate of the harmonics, the circuit needs to be simulated for more than the 10 periods used in Example 6.3. We will perform a transient analysis for 10 JLS corresponding to 33 periods; the • TRAN line in the input file is replaced by the following line:
.TRAN 15N lOU 9.3U 15N
The waveform is saved for displaying only the last two periods, and limiting TMAX to 15 ns ensures that at least 20 time points are used in each period to evaluate the response. The following statement defines the frequency of the fundamental and the output variable for which the spectral components are desired:
.FOUR 3.36MEG V(2)
The frequency of the fundamental must be specified as accurately as possible, because an error as small as 1% can make a difference in the values of the Fourier coefficients. The output ofthe Fourier analysis from SPICE2 is listed in Figure 6.14. Note that the amplitude of the fundamental found by the Fourier analysis agrees with the value computed by hand in Example 6.3, Eq. 6.28. The THD of the sinusoidal signal produced is 8.25%.
A few comments are necessary regarding the implementation of Fourier analysis in SPICE3. Although the limit of only nine harmonics imposed by SPICE2 and most other SPICE versions is not a problem for most circuits, this limitation can become an impediment in finding the intermodulation (1M) terms for such circuits as mixers. In
SUMMARY
191
****
FOURIER ANALYSIS
TEMPERATURE
=
27.000 DEG C
FOURIER COMPONENTS OF TRANSIENT RESPONSE V (2) DC COMPONENT HARMONIC NO
1
=
1.000407E+00l FOURIER NORMALIZED COMPONENT COMPONENT 2.523E+000 1.890E00l 7.725E002 3.532E002 1.602E002 7.680E003 4.226E003 2.962E003 2.516E003
=
FREQUENCY (HZ) 3.360E+006 6.720E+006 1.008E+007 1.344E+007 1.680E+007 2.016E+007 2.352E+007 2.688E+007 3.024E+007
PHASE (DEG) 8.683E+00I 1.545E+002 1.471E+002 1.374E+002 1.257E+002 1.111E+002 9.404E+00I 7.896E+00I 6.880E+00I
NORMALIZED PHASE (DEG) O.OOOE+OOO 6.769E+00I 6.027E+00I 5.054E+00I 3.886E+00I 2.426E+00I 7.206E+000 7.869E+000 1.803E+00l
2 3 4 5 6
7
8 9
1.000E+000 7.490E002 3.062E002 1.400E002 6.420E003 3.044E003 1.675E003 1.174E003 9.971E004
TOTAL HARMONIC DISTORTION
8.245843E+000 PERCENT
Figure 6.14 Fourieranalysisof the Colpittsoscillator.
SPICE3 the user can define the number of harmonics to be computed by issuing the following set command in the SPICE3 shell: spice3> set nfreqs=n where nfreqs is the keyword and n is the desired number of harmonics. The default for n is 9. Another variable that can be set by the user in SPICE3 is the degree of the polynomial used to interpolate the waveform. In order to request polynomial interpolation of higher degree, the following command must be issued at the SPICE3 shell prompt: spice3> set polydegree=n where polydegree is the keyword and n is the degree.
6.5
SUMMARY
This chapter presented the analyses performed by SPICE in the time domain. The control statements for each analysis were introduced as well as the specifications of output variables and resultprocessing requests. Emphasis was placed on exemplifying the transient and steadystate responses of both a linear and a nonlinear circuit and comparing the manual derivation with SPICE simulations.
192
6
TIMEDOMAIN
ANALYSIS
SPICE supports two analysis types in the time domain, transient and Fourier analysis, which are specified by the following control lines: . TRAN TSTEP TSTOP <TSTART <TMAX> > <UIC> .FOUR
freq OULvar] <OULvar2 ... >
The. IC (initial conditions) statement is a third control statement introduced in this chapter used for specifying the known node voltages at time t = 0: . IC V (node] )=valuel <V (node2) =value2 ...
>
Initial conditions can also be defined for individual elements; terminal voltages and initial currents can be used to initialize chargestorage and nonlinear elements. Elementbased initial conditions are taken into account only in conjunction with the UIC (use initial conditions) option in the • TRAN statement. Table 6.1 summarizes the ways of setting initial conditions. The waveforms of voltages and currents computed in a transient analysis must be saved by use of the. PRINT or • PLOT control statement, in tabular or lineprinterplot format, respectively. The general format of the output request that must accompany a • TRAN line is . PRINT/PLOT TRAN OUT_var] <OULvar2 ...
> <ploLlimits>
The seven detailed examples in this chapter also highlighted the relation between largesignal timedomain analysis and smallsignal AC analysis.
REFERENCES
Gray, P. R., and R. G. Meyer. 1993. Analysis and Design of Analog Integrated Circuits, 3d. ed. New York: John Wiley & Sons. Meyer, R. G. 1979. Nonlinear integrated circuits. In EE 240 Class Notes. Berkeley: University of California. Nilsson, 1. W. 1990. Electric Circuits, 3d ed. Reading, MA: AddisonWesley. Pederson, D.O., and K. Mayaram. 1990. Integrated Circuits for Communication. Boston: Kluwer Academic Publishers.
Seven
FUNCTIONAL AND HIERARCHICAL SIMULATION
7.1
HIGHLEVEL CIRCUIT DESCRIPTION
The example circuits presented in previous chapters use circuit elements, such as resistors, capacitors, and transistors, that have a onetoone correspondence with components on electronic circuit boards or ICs. Such a description is generally referred to as a structural representation of the circuit. The simulation of a structural circuit produces very accurate results, but may take a long time. The analysis time grows proportionally to the number of components and is dominated by semiconductor elements, which are described by complex nonlinear equations. The analysis time sets a limit on the size of circuits that can be simulated at the structural level. Although circuits with several hundred to a few thousand components can be analyzed with SPICE on current PCs and engineering workstations, alternate ways of modeling circuits can increase design productivity. The most common approach is to group several components in a block according to the function performed. According to this criterion, we can distinguish gain blocks, oscillators, integrators, differentiators, NAND and NOR blocks, adder blocks, and so on. Then, the SPICE description needs to be an equivalent circuit that achieves the same function as the componentlevel implementation. This functional model can be built with fewer components and with special SPICE elements, such as controlled sources. Simulation times for circuits with functional models are considerably shorter than those for detailed circuits.
193
194
7
FUNCTIONAL
AND HIERARCHICAL SIMULATION
SPICE provides a subcircuit capability, which allows a user to define a subnet or a block and then instantiate it repeatedly in the overall circuit. For example, the functional, or transistorlevel, schematic of a NAND gate can be defined once and then instantiated repeatedly to form complex digital or mixed analog/digital circuits. This SPICE feature and its application for large circuits is described in Sec. 7.2. When the SPICE input of large circuits is prepared, the netlist description can be very long and difficult to understand. A hierarchical approach to describing large circuits is recommended; with this approach a designer can quickly recognize the toplevel block diagram of the circuit from the SPICE description. The subcircuit definition capability of the SPICE input language provides the means for hierarchical descriptions. An example of SPICE hierarchical definition is described in Sec. 7.2. In a hierarchical description various blocks can be described at different levels of accuracy. The simplest representation of the function of a given block is an ideal model. Ideal functional blocks are introduced in Sec. 7.3 for both analog and digital circuits. Ideal blocks are very simple and result in short simulation times but may not provide sufficient accuracy or adequate SPICE convergence, as described in Chap. 10. More complex models for SPICE simulation can be developed, which reproduce detailed characteristics of the circuit, such as limited output swing, finite bandwidth, and other range restrictions. These models combine SPICE primitives (Chap. 2) and arbitrary functions (Sec. 7.4.1) to formjunctional models. A few examples of functional models are presented in Sec. 7.4. All details of the operation of circuit blocks or entire ICs can be built into SPICE primitives. The macromodel can incorporate all or a part of the first and secondorder effects of a circuit with a considerably smaller number of elements, resulting in significantly shorter simulation times. An operational amplifier macromodel commonly used by many suppliers of SPICE models for standard parts is described in Sec. 7.5.
7.2
7.2.1
SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY
.SUBCKT Definition A circuit block that appears more than once in the overall circuit and consists of SPICE primitives can be defined as a subcircuit (Vladimirescu, Zhang, Newton, Pederson, and SangiovanniVincentelli 1981). The block can then be referenced as a single component, the subcircuit instance, and connected throughout the circuit. There is a similarity between the. SUBCKT definition and the .MODEL definition. Whereas a .MODEL statement defines a set of parameters to be collectively used by a number of devices, the • SUBCKTdefinition represents a circuit topology, which can be connected through its external pins or nodes anywhere in the circuit. The elements that form the sub circuit block are preceded by the following control statement: . SUBCKT SUBname node} <node2 ...
>
SPICE SUBCIRCUIT
AND CIRCUIT
HIERARCHY
195
where SUBname uniquely identifies the subcircuit and nodel, node2, ... are the external nodes that can be connected to the external circuit. There is no limit to the number of external nodes. The rest of the nodes in the subcircuit definition are referred to as internal nodes. The internal nodes cannot be connected or referenced in the toplevel circuit. The ground node, node 0, is global from the top circuit through all subcircuits. The completion of the subcircuit definition is marked by the following line:
. ENDS
<SUBname>
Repetition of SUBname is not required, except for nested subcircuit definitions, but is recommended for the ease of checking the correctness of the circuit description. In addition to SPICE elements, a number of control statements can be used within a subcircuit definition. Local •MODEL lines introduce models that can be referenced only by elements that belong to the subcircuit. Other • SUBCKT definitions can be nested inside a subcircuit; nested subcircuits can only be referenced from the subcircuit in which they are defined. No other control lines, that is, analysis, print/plot, or initialization requests, are allowed in a subcircuit definition. One difficulty created by this restriction is related to initializing node voltages. Although device initial conditions can be defined for elements inside a subcircuit, no • NODESET or . IC statement can be used to set the starting voltages on internal nodes. This limitation is overcome by declaring all nodes that require initialization as external nodes on the • SUBCKT line.
7.2.2
Subcircuit Instance
A subcircuit block is placed in the circuit by an Xelement call, or subcircuit call, defined by the following line:
Xname xnodel <xnode2 ... > SUBname
The letter X must appear in the first column to identify a subcircuit instance; the number of nodes must be equal to those on the corresponding subcircuit definition, SUBname. xnode l, xnode2, ... , are the numbers or names of the nodes that are to correspond with the nodes nodel, node2, ... of the. SUBCKT line, at the circuit level where SUBname is instantiated. Subcircuit definition and calls can be exemplified by a hierarchical description of the threestage ring oscillator in the previous chapter, Example 6.5. The new SPICE description, using inverters rather than the detailed schematic of the circuit as in Figure 6.9 is listed in Figure 7.1. The corresponding circuit diagram is shown in Figure 7.2.
7.2.3
Circuit Hierarchy
The SPICE subcircuit capability offers the designer the ability to describe a complex circuit in a hierarchical fashion. Any number of hierarchical levels can be defined. The
196
7
FUNCTIONAL
AND HIERARCHICAL SIMULATION
RING OSCILLATOR WI MOS INVERTERS Xl 1 2 5 INVERTER X2 2 3 5 INVERTER X3 3 1 5 INVERTER VDD 5 0 5
*
*
* .SUBCKT INVERTER 1 2 3 * NODES: VIN, VOUT, VDD
M1 2 1 0 0 ENH L=10U W=40U M2 3 2 2 0 DEP L=10U W=5U
*
.MODEL DEP NMOS LEVEL=l VTO=3 LAMBDA=.OOl KP=.4E4 .MODEL ENH NMOS LEVEL=l VTO=l.8 CGS0=20N LAMBDA=.OOl KP=.4E4 INVERTER
* .ENDS
*
.IC V(l)=5 V(2)=0 .TRAN .0lD .5U .PLOT TRAN V(l) V(2) V(3) (0, 5) .WIDTH OUT=80 .END SPICE input for ring oscillator with MOS inverters using
.SUBCKT.
Figure 7.1
hierarchical description of an adder built from NAND gates is presented in this section as an example of the proper application of the SPICE • SUBCKT statement.
EXAMPLE 7.1 Use sub circuits and hierarchy to create the SPICE input of the 4bit adder built with TIL NAND gates that is shown in Figure 7.3 (Vladimirescu 1982). Partition the adder at the following levels: NAND gate, Ibit adder, and 4bit adder. Run SPICE to find the DC operating point of the Ibit adder and interpret the results.
Solution
The first step is to write the SPICE netlist of the TIL NAND gate in Figure 7.3.a. This description is listed between the . SUBCKT NAND and . ENDS NAND lines. The external nodes, or terminals, of the NAND gate are the two inputs INl and IN2, the output, OUT, and the supply connection, VCC. These are the only pins needed for connecting a NAND gate in an external circuit and correspond to the pins available in a 7400series TILle.
SPICE SUBClRCUIT AND CIRCUIT HIERARCHY
197
Figure 7.2
Ring oscillator with MOS inverters.
Next, a description of the Ibit adder is created by specifying how the nine NAND gates in the schematic in Figure 7.3.b are connected. The NAND gates are instantiated in the Ibit description using the X element. This new circuit is labeled as subcircuit ONEBIT and is used at the next level of the hierarchy to define the 4bit adder. The external nodes of ONEBIT are the two inputs, A and B, the carryin bit, CIN, the output, OUT, and carryout bit, COUT, as well as the supply, vee. When digital circuits are described in the following sections of this chapter, node names are uppercase, such as A and OUT, the voltages or analog signals at these nodes are indicated by an uppercase V, as in VA and VOUT, and the boolean (digital) variables associated with the terminals are lowercase, such as a and out. Four ONEBIT subcircuits are connected according to Figure 7.3.c to form the 4bit adder. Four instances (X) of ONEBIT are needed to define the FOURBIT subcircuit. The hierarchical SPICE definitions of the 4bit and Ibit adders and the NAND gate are listed in Figure 7.4. All the toplevel input and output pins of the 4bit adder are
3 Hierarchy of 4bit adder: (a) TTL NAND gate.. . GOUT A B .0 GINOUT A OUT B GOUT (b) ri I I RITO BITI GIN GOUT BITO A BOUT BIT1 BIT2 GIN GOUT A BOUT  FOURRIT BITJ I GIN GOUT I BIT2 A B I BIT3 OUT I  ~ (c) Figure 7. (c) 4bit adder. (b) Ibit adder with symbol.198 7 FUNCTIONAL AND HIERARCHICAL SIMULATION IN1 I~ ~OUT IN2 OUT IN2 (a) .
The DC operating point of the Ibit adder can be found by running the SPICE deck shown in Figure 7. The 4bit adder circuit defined in Figure 7.ENDS FOURBIT (continued on next page) * .5 seems confusing at first. A long list of node ADDER . VCC Xl 1 2 13 9 16 15 ONEBIT X2 3 4 16 10 17 15 ONEBIT X3 5 6 17 11 18 15 ONEBIT X4 7 8 18 12 14 15 ONEBIT .SUBCKT NAND 1 2 3 4 NODES: IN1 IN2 OUT VCC Q1 9 5 1 QMOD D1CLAMP 0 1 DMOD Q2 9 5 2 QMOD D2CLAMP 0 2 DMOD RB 4 5 4K R1 4 6 1.SUBCKT * Figure 7. CARRYOUT. * OUTPUT . 6K Q3 6 9 8 QMOD R2 8 0 1K RC 4 7 130 Q4 7 6 10 QMOD DVBEDROP 10 3 DMOD Q5 3 8 0 QMOD . respectively.BITO / BIT1 / BIT2 / BIT3.ENDS ONEBIT * * FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NODES: INPUT . The SPICE2 output in Figure 7.5 with the subcircuit definitions listed in Figure 7.SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 199 connected to signal sources or resistors.BlTO(2) / BIT1(2) / BIT2(2) / BIT3(2) .4 has three levels of hierarchy. .4 for NAND and ONEBIT.4 BIT ALLNANDGATE BINARY ADDER .SUBCKT ONEBIT 1 2 3 4 5 6 NODES: A B CIN OUT COUT VCC Xl 1 2 7 6 NAND X2 1 7 8 6 NAND X3 2 7 9 6 NAND X4 8 9 10 6 NAND X5 3 10 11 6 NAND X6 3 11 12 6 NAND X7 10 11 13 6 NAND X8 12 13 4 6 NAND X9 11 7 5 6 NAND . CARRYIN.4 Hierarchical SPICE definition of a 4bit adder.ENDS NAND * * .
1 BIT ALLNANDGATE BINARY ADDER **** INPUT LISTING TEMPERATURE 27. IN2. VCC Q1 9 5 1 QMOD D1CLAMP . Q3 6 9 8 QMOD * R2 8 0 1K RC 4 7 130 Q4 7 6 10 QMOD DVBEDROP 10 3 DMOD Q5 3 8 0 QMOD .*** *** DEFINE NOMINAL CIRCUIT *** Xl 1 2 3 4 5 6 7 8 9 10 11 RBITO 9 0 1K RBIT1 10 0 1K RBIT2 11 0 1K RBIT3 12 0 1K RCOUT 13 0 1K VCC 99 0 DC 5V VIN1A 1 0 PULSE(O 3 0 10NS VIN1B 2 0 PULSE(O 3 0 10NS VIN2A 3 0 PULSE(O 3 0 10NS VIN2B 4 0 PULSE(O 3 0 10NS VIN3A 5 0 PULSE(O 3 0 10NS VIN3B 6 0 PULSE(O 3 0 10NS VIN4A 7 0 PULSE(O 3 0 10NS VIN4B 8 0 PULSE(O 3 0 10NS 12 0 13 99 FOURBIT 10NS 10NS 10NS 10NS 10NS 10NS 10NS 10NS 10NS SONS) 20NS lOONS) 40NS 200NS) 80NS 400NS) 160NS 800NS) 320NS 1600NS) 640NS 3200NS) 1280NS 6400NS) * .MODEL .MODEL QMOD NPN(BF=75 RB=100 CJE=lPF CJC=3PF) .OP DMOD D .4 (continued) ******* 02/24/92 ***** SPICE 2G.OPT ACCT .6K.5 SPICE2 output for Ibit adder.ENDS NAND Figure 7.6 3/15/83 ******** 17:44:45 ******* ADDER .0 1 DMOD Q2 9 5 2 QMOD D2CLAMP 0 2 DMOD RB 4 5 4K R1 4 6 1.END Figure 7.SUBCKT NAND 1 2 3 4 NODES: IN1. 200 . OUT.000 DEG C *************************************************************************** .
X1 RC.X8.X7.X1 RC.END ******* ADDER **** 02/24/92 ******** SPICE 2G.X3. Xl RC. OUT.SUBCKT ONEBIT 1 2 3 4 5 6 * NODES: A.X6.X6.X4.X8.X9.X1 RC.X1 R1.000 DEG C *************************************************************************** 1 2 9 13 99 VIN1A VIN1B RBITO RCOUT RB.X1 Q2.X9.X1 D2CLAMP* D1CLAMP* D2CLAMP* DlCLAMP* DlCLAMP* DlCLAMP* Q5.X1 D2CLAMP* Q1.X3..X1 R1.X2.X1 D2CLAMP* Q5.X1.X1 RC.X1 Q1.X1. Xl.X1 RC.6 3/15/83 ******** 17:44:45 **** .X1 Q1.X7.X1 Q2.X7.X1 RC.OPT ACCT NODE .X2.X2.WIDTH OUT=80 .X1 DVBEDRO* DVBEDRO* (continued) ')1\1 100 101 102 DlCLAMP* D2CLAMh DlCLAMh DVBEDRO* Rl.X2.X3.X1 R1.X4.X3.X8.X1 RB.5 .MODEL QMOD NPN(BF=75 RB=100 CJE=lPF CJC=3PF) VCC 99 0 DC 5V VIN1A 1 0 PULSE(O 3 0 10NS 10NS 10NS 50NS) VIN1B 2 0 PULSE(O 3 0 10NS 10NS 20NS lOONS) * * .X1 RB.X5.1 BIT ALLNANDGATE ELEMENT NODE TABLE BINARY ADDER TEMPERATURE = 27 . CIN.X1 Q5.X1 Q1.X1 RB.MODEL DMOD D .X1 RC.X1 RB.X5.X1 RB.X1 Q2. B.X1 VCC Q2.X2.X9.X4.X1 R1.X6.X1 Rl.X1.ENDS ONEBIT *** *** DEFINE NOMINAL CIRCUIT *** Xl 1 2 9 0 13 99 ONEBIT RBITO 9 0 1K RCOUT 13 0 1K .OP .X1 RB.X2.X9.X1 RC.X1 RB.X4.X1 DVBEDRO* Q2. VCC Xl 1 2 7 6 NAND X2 1 7 8 6 NAND X3 2 7 9 6 NAND X4 8 9 10 6 NAND x5 3 10 11 6 NAND X6 3 11 12 6 NAND X7 10 11 13 6 NAND X8 12 13 4 6 NAND X9 11 7 5 6 NAND .X3.X1 Figure 7.X1 Rl.X4. COUT.X5.X1 Q5.X1 Rl.X1 Q1.X5.X9.X1 Rl.Xl.X1 Q1.X1 RB.X1.X6.X3.
X1 Q4.X4.X1 Q2.X1 R2.X6.X1 Q2.X5.X3.X2.X1 Q5.X1 D2CLAMP* D2CLAMP* D1CLAMP* Q5.X8.X7.X4.X7.X4.X1 RC.X1 RB.X1 Q5.X1 Q1.XB.X1 DVBEDRO* Q1.X1 Q2.X4.X8.X1 Q4.X5.X5.X1 Q3.X7.X1 Q4.X4.X4.5 202 .X5.X7.X2.X1 R1.X6.X2.X6.X9.X1 Q3.X1 Q4.X1 Q2.X1.X1 Q2.X1 RC.X1.X1 Q2.X1 Q3.X1 DVBEDRO* Q1.X2.X2.X1 R1.X1 RB.X1.X1 R2.X6.X5.X1 Q3.X4.X1 Q3.X1.X1 Q4.X2.X1 RB.X6.X1 DVBEDRO* DVBEDRO* Q1.X1 RC.X1 Q3.X1 Q4.X7.X1 Q4.X1 Q4.X1 Q3.X4.X1.X3.X7.X6.X7.X1 Q3.X4.X1 Q5.X1 Q4.X1 Q2.X1 Q1.X6.X7.X1 Q4.X4.X3.X1 Q1.X3.X3.X1 Q5.X3.X5.X1 Q4.X1 Q1.X1 DVBEDRO* Q1.103 104 105 106 107 lOB 109 110 111 112 113 114 115 116 117 11B 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 14B 149 150 DVBEDRO* DVBEDRO* Q1.X5.X1 Q3.X2.X1 (continued) D2CLAMP* D1CLAMP* Q5.X6.X1 Q2.X6.X1 Q4.X1 Q2.X5.X1 Q5.X3.X1 RC.X1 R1.X6.X6.X1 Q3.X1 Q4.X1 Q2.X1 Q5.X5.X5.X1 Q1.X3.X1.XB.X1 R1.X1 Q2.X4.X1 RC.X1 Q4.X1 Q2.X2.X2.X1 Q5.X1 R2.X1 Q3.X3.X1.X7.X1 R1.X1 DVBEDRO* Q1.X1.X1 Q3.X7.X7.X1 Q2.X4.X1 Q4.X1 Q2.X2.X1 RC.X1.X1 Q4.X1 Q4.XB.X4.X1 Q5.X1 Q3.X5.X1 Q4.X1 Q1.X6.X1.X2.X1 RB.X1 Q2.X1 Q3.X1 DVBEDRO* Q1.X1 Q5.X1 Q3.XB.X1 R1.X8.X2.X6.X3.X1 Q1.X2.X6.X1 Q2.X6.X7.X1.X1 Q3.X7.X5.X1 Q4.X2.X5.X3.X1.X4.X1 Q3.X1 D1CLAMP* D2CLAMP* Q2.X1 Q2.X1 Q3.X1 DVBEDRO* Q1.X1 Q4.X2.X7.X7.X3.X5.X1 Q3.X1 R2.X1 R2.X1 Q2.X4.X1.X3.X5.X1 RB.X6.X6.X1 Q3.X1 RB.X1 Q1.X4.X1 RB.X1.X1 Q1.X1 Figure 7.X1 Q1.X5.X1 RC.X1 R2.X7.X7.X3.X1 R2.X7.X3.X1.X5.X1 Q2.X1 RB.X1 Q3.X1 Q4.X1 R1.X8.X1 Q3.X1 DVBEDRO* Q1.
0672 4.9994 4.X1 Q5.X1 Q4.X1 Q2.8320 4.X1 02/24/92 ******** Q4.2529 1.8752 4.7590 0.X1 Q4.1 BIT ALLNANDGATE BINARY ADDER **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.X9.5005 NODE ( 9) (101) (105) (109) (113) (117) (121) (125) (129) (133) (137) (141) (145) (149) (153) (157) VOLTAGE 0.X8.X9.0745 0.X1 R2.0363 4.7459 0.X9.X8.X9.38002 WATTS TOTAL POWER DISSIPATION Figure 7.8444 4.5 (continued) .SPICE SUBCIRCUIT AND CIRCUIT HIERARCHY 203 151 152 153 154 155 156 157 158 159 160 ******* R1.0000 3.8752 4.0000 2.X1 RC.7685 0.1122 0.6 3/15/83 ******** 17:44:45 **** ADDER .0000 0.7979 4.1020 NODE ( 13) (102) (106) (110) (114) (118) (122) (126) (130) (134) (138) (142) (146) (150) (154) (158) VOLTAGE 0.5919 4.X1 Q3.075003 9.X9.9639 4.X1 R1.0309 0.0363 4.9642 1.X1 R2.X1 DVBEDRO* Q4.0500 2.1152 0.X1 Q5.2529 0.9642 4.2526 1.X8.000 DEG C *************************************************************************** NODE 1) ( 99) (103) (107) (111) (115) (119) (123) (127) (131) (135) (139) (143) (147) (151) (155) (159) VOLTAGE 0.9639 1.5339 0.6308 3.X1 Q1.8567 0.X1 Q3.0000 2.X1 SPICE 2G.9897 4.X9.5278 3.4928 4.9724 0.X9.1899 0.X9.6308 3.X9.X1 Q3.X1 RB.X8.0179 4.9745 0.0870 0.X9.X8.X9.0000 1.X1 Q3.6303 0.X1 RC.X8.876002 2.9998 1.5122 0.9941 0.X9.X8.0672 4.0000 0.4845 1.X9.X1 Q2.X1 Q3.9998 4.8448 4.X1 DVBEDRO* Q4.0000 5.X8.8448 4.9941 1.9763 4.075003 2.8268 4.0877 1.0000 0.7616 3.X9.9941 1.X1 Q1.0642 2) (100) (104) (108) (112) (116) (120) (124) (128) (132) (136) (140) (144) (148) (152) (156) (160) VOLTAGE SOURCE CURRENTS NAME VCC VIN1A VIN1B CURRENT 1.9998 NODE ( VOLTAGE 0.X1 Q4.0178 3.X9.1940 0.X8.
7. an opamp is a gain block and . A practice that distinguishes the toplevel circuit nodes from those generated by the program due to subcircuit expansion is to make the last node number in the toplevel circuit easy to identify. functional. In order to understand the. a designer can choose among several levels of detail and accuracy for each hierarchical block. The following sections present several approaches to defining SPICE models for more complex blocks. including from 20 to 50 transistors. PSpice uses the composite node names in the SSBS printout. 9. 9. Describing a block by the detailed structural schematic is always straightforward if the schematic is known. The ELEMENT NODE TABLE generated by SPICE2 is also part ofthe output listed in Figure 7.204 7 FUNCTIONAL AND HIERARCHICAL SIMULATION numbers appears in the SMALLSIGNAL BIAS SOLUTION (SSBS) section. The name of an element connected at a node is formed by concatenating the names of the X calls at every level of hierarchy to the element name of a SPICE primitive appearing at the bottom of the hierarchy. The operational amplifier. The composite name starts with the component name followed by the subcircuit instance names that call it. the names at different levels of hierarchy are separated by periods. for both analog and digital circuits an ideal model provides only the single most relevant function of a device.5. Xl is the resistor RB of the X2 NAND instance that is part of the Ibit adder Xl.3 IDEAL MODELS Ideal models are the simplest and computationally most efficient. but it may not be economical. it is advisable to select the representation with only those characteristics that are relevant for a given design. in this case the NAND gate definition level. Component RB. which is widely used in many designs and is considered a basic circuit element due to its availability in IC implementation can be described as an ideal. Once a hierarchy of a circuit is established. both analog and digital.meaning of these newly created node numbers the user must request the NODE option on an • OPTION line: . OPTION NODE For more detail on SPICE options see Chap. This process is similar to using simpler or more complex transistor models by selectively specifying values of model parameters representing certain secondorder effects. making it difficult to trace the hierarchy path of elements having long names. especially the summary in Sec. As described in the following sections. macromodel or as a detailed model. therefore all threedigit numbers are introduced due to subcircuit expansion and the meaning of each node can be derived from the ELEMENT NODE TABLE. X2 . Because the detailed design of an opamp is complex.5. In the adder example the last node number is 99. for example. The composite names are limited to eight characters in SPICE2.
very high input resistance. and amplifiers. The principle of the virtual short can be applied in the analysis of circuits with ideal opamps (Dorf 1989. differentiators.7 by replacing Zf with a capacitor Cf and Zi with a resistor Ri.6. Although very efficient in simulation ideal models can cause problems in SPICE analyses due to the ideality. The correct operation as an integrator can be checked with SPICE both in the time domain and the frequency domain. filters.7.1) A commonly used circuit configuration of the opamp is shown in Figure 7.IDEAL MODELS 205 a transistor is a switch. as shown in Figure 7. The output voltage in the frequency domain is given by (7. Figure 7.6 Idealopamp.2) This feedback connection is often used to implement integrators. An ideal integrator can be built with the circuit in Figure 7. Sedra and Smith 1990). 7. Paul 1989. . This assumption consists of Vid = 0 (7.3. Oldham and Schwartz 1987. An ideal opamp can be reduced to a gain block with infinite input resistance and zero output resistance. and low output resistance.1 Operational Amplifiers The main characteristics of an opamp are very high gain.
SUBCKT) that contains just a voltagecontrolled voltage source.8 Bandpass filter. Cf = I nF.8. EXAMPLE 7. BANDPASS FILTER WI IDEAL OPAMP XOP1 0 1 2 OPAMP RI 3 4 100 CI 1 3 1N RF 1 2 10K CF 1 2 1N VID40AC1 * * Figure 7.2 Check the operation as a bandpass filter of the circuit shown in Figure 7.. Note that the ideal opamp is defined as a subcircuit (.206 7 FUNCTIONAL AND HIERARCHICAL SIMULATION Figure 7. Solution The SPICE input is listed below.Rf = 10 ko'. Use the ideal opamp description with av = 105 and the following values for the resistors and capacitors: Ri = 100 0. as shown in Figure 7.6. C = I nF.7 Opamp in feedback configuration. .
IDEAL MODELS 207 . The output voltage of the openloop ideal opamp model. Its use in SPICE simulations should be limited due to the potential numerical problems that can be caused by the approximations involved. the transfer function becomes (7.2: H(jw) = Vo Vid = _ Rf .ENDS .Q. the passband extends from 15. 7. however.PRINT AC VDB(2) VP(2) .9.AC DEC 10 10 1G . The desired largesignal transfer characteristic can be achieved by adding a voltage limiter to the output stage. where 1/ (RfCf) « w « 1/ (RiCi). A very important nonideality factor to consider in largesignal analyses is the supply voltage.9 kHz to 1. .SUBCKT OPAMP 1 2 3 EGAIN 3 0 1 2 1E5 .59 MHz.5.END The transfer function of this active filter is obtained through substitution of the expressions for Zi and Zf in Eq. possibly causing simulation problems depending on the circuit. that is. R i jw RfCf ~w ( + RfCf 1)( jw + Riq 1) (7. which limits the excursion of the output signal. in Figure 7. as shown by the transfer characteristic.5) The magnitude and phase resulting from the SPICE frequency analysis are plotted in Figure 7. Va versus Vid.3) In the passband. 7.10.37.WIDTH OUT=80 .4) The limits of the passband for this active filter are defined by the two poles: PI P2 = RiCi 107 rad/s (7. can rise to thousands of volts. The Bode plot produced by SPICE is in agreement with the behavior predicted by Eqs. The ideal opamp model presented above is a useful concept for instructional purposes and quick hand calculations.
Vid transfer characteristic. Hz 106 107 108 Figure 7.v. .9 Magnitude and phase of Va of bandpass filter.208 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o lD 0 100 200 300 400 "'C Dl c 25 50 75 100 ::T g ~ g' :a: ai ~ co 0CD m CD en 102 103 104 105 Frequency.d t Ree Ce Vd °dVd (a) Vee (b)  VEE r D2 Vid Vo VEE (c) Figure 7. (c) opamp symbol.10 Nonideal operational amplifier: (a) Va versus (b) opamp model. vee Vo Ro 1 Ve Vo + Vid + + Vid R. g.
AND. the digital functions might not be critical to the performance of the circuit but might need to be included for verifying the correct operation of the overall circuit. Rill and Ro.c. The MOS transistor in this implementation acts as a voltagecontrolled switch.3.ENDS * 7. The ideal opamp also assumes that the frequency bandwidth is infinite.7 D1 8 4 DMOD D2 5 9 DMOD . Note that the simple nonideal opamp model has five terminals.IO.OUT VCC VEE RIN 1 2 1MEG * GAIN STAGE GI 0 6 1 2 1 RCC 6 0 1 CC 6 0 1. An intermediate stage has been added to this model to include the singlepole rolloff of the frequency characteristic. which corresponds to a value Ce = 1.11.b. A simple but nonideal opamp model that includes the above properties is presented in Figure 7.2 Logic Gates and Digital Circuits Many circuits simulated with SPICE have both analog and digital functions.7 VE 3 9 0.IO. OR. .SUBCKT OPAMP 1 2 3 4 5 TERMINALS: IN+ IN. which include the two power supplies.IDEAL MODELS 209 Two additional nonideality factors that should be added to the opamp model in order to avoid very high currents are input and output resistances. Vee and VEE. In this case simplified versions of the logic blocks can be used. The ideal models ofthe NAND.59. These ideal models of logic gates can be used to simulate circuits in SPICE3 and PSpice but not in SPICE2. The pole is defined by the intermediate stage at 10 Hz. and XOR gates using voltagecontrolled switches and positive logic are shown in Figure 7. Ideal logic gate models can be easily derived from the NMOS implementation (Hodges and Jackson 1983). If the analog blocks are required to be characterized with very high accuracy.MODEL DMOD D RS=l . 59E2 * OUTPUT STAGE EGAIN 7 0 6 0 1E5 RO 7 3 100 VC 8 3 0. The simplest and computationally most efficient are the ideal models. in reality the bandwidth of the opamp is finite and is defined by an internal compensation capacitor. 102 F and Re = 1 O. . The corresponding SPICE sub circuit description using typical values is listed below . and the revised symbol is in Figure 7. NOR. Ideal models oflogic gates can be implemented with switches.
7. Compute the response to signals a. the SPICE input of which is listed in Fig. for convenient verification of correct operation. implemented Co. and Ci in Figure 7.2 s (no hysteresis). The computed waveforms s and Co for both the ideal and the detailed implementations (see listing in Figure 7. is by the Ibit adder with carryin Ci and carryout s Co = a + b + Ci = (a + b)ci + a .210 7 FUNCTIONAL AND HIERARCHICAL SIMULATION Computationally efficient models for logic gates accepted by SPICE2 can be implemented as functional models using controlled sources.9 sand Vo NAND AND NOR OR XOR Figure 7. These models are presented in Sec. In PSpice on an IBM PSI280 with a 386 processor at 16 MHz the run times 37. . whereas that of the allNAND implementation is 146 s.b) using the ideal gates shown in Figure 7. The analysis time for the ideal circuit in SPICE3 on a SUN 4/110 workstation is 1.5. s. Solution The Boolean function.12.3.12. 7. EXAMPLE 7.5) are displayed with the input signals on the same graph in Figure 7.13 and the corresponding SPICE3 input is given in Figure 7. compare the results and the run time with those obtained with the detailed model of Figure 7.4.6) The logic diagram of the adder is drawn in Figure 7. using SPICE.14. b.11 Ideal logic gates.b (7.b.3.11.3 Derive the most efficient implementation of the Ibit adder (Figure 7.
G. Note that the waveforms obtained with the two representations are different. b. respectively. the ideal model predicts more changes in the output signals. and Cj and output s and Co for ideal 617 s.IDEAL MODELS 211 a b s (ideal) Co (ideal) s (full) Co (full) 50 100 Time. than the detailed circuit. compared to the delayed response of the transistorlevel version: the ideal circuit lacks of charge a b o o Figure 7. ns 150 Figure 7. The difference between the operations of the two circuits can be traced to the instantaneous switching of the ideal version after each change in input.13 Logic diagram of the Ibit adder. s and Co.12 Ibit adder simulation: input signals and full models. .
MODEL SW VSWITCH RON=l ROFF=lMEG VON=2.1BIT ADDER WITH SWITCHES * .ENDS XOR * .TRAN .ENDS ONEBIT 1 2 3 4 5 6 B CIN OUT COUT VCC * * MAIN * Xl 1 2 CIRCUIT ONEBIT 3 9 13 99 RINA 1 0 1K RINB 2 0 1K RCIN 3 0 1K RBITO 9 0 1K RCOUT 13 0 1K VCC 99 0 5 VINA 1 0 PULSE 0 VINB 2 0 PULSE 0 VCIN 3 0 PULSE 0 3 0 10N 10N 10N 50N 3 0 10N 10N 20N lOON 3 lOON 10N 10N lOON 200N * .SUBCKT ONEBIT * TERMINALS: A Xl 1 2 7 6 XOR X2 1 2 8 6 AND X3 7 3 4 6 XOR X4 3 7 9 6 AND X5 8 9 5 6 OR . 5 VOFF=2.SUBCKT OR 1 2 3 4 * TERMINALS A B OUT RL 3 0 1K VCC Sl 3 4 1 0 SW S2 3 4 2 0 SW . 5 2N 200N SPICE3 description of IBit adder.14 212 .SUBCKT XOR * TERMINALS RL 3 0 1K 1 2 3 4 A B OUT VCC Sl 4 3 1 2 SW S2 4 3 2 1 SW .ENDS AND * . * .END Figure 7.ENDS OR * .SUBCKT AND * TERMINALS RL 3 0 1K 1 2 3 4 A B OUT VCC Sl 4 5 1 0 SW S2 5 3 2 0 SW .
1. ofthesesubcircuits is similar to that of the transistorlevel implementation. such as controlled sources. functional models achieve the same operation as the blocks they represent with just a few controlled soUrces connected in a network having no resemblance to the original one. respectively. ideal models can.FUNCTIONAL MODELS 213 storage. Besides predicting incorrect behavior. and other components.4.v flm~tiom: ~~n h~ 1I~~cl in pynr' tr~n~rpntlpnt~l . On the other hand. 7. as pointed out by the shortcomings of the ideal opamp. The general format for nonlinear controlled sources is Bname node} node2 V/I=expr B in the first column identifies the controlled source as nonlinear.tion has introduced the concept of ideal elements. which are structural. The savings in simulation time are very important. ideal circuit models can also lead to an analysis failure in SPICE. In the following subsections a few examples of functional models are provided that are developed based on the different capabilities of the controlled sources available in the versions of SPICE under consideration. This section describes how the function of a circuit bl~ck c~mbe modeled using controlled sources that are nonlinear or of arbitrary functional form. as ~an any element name in SPICE3. or topology. The circuit structure. which covers all possible cases. the equivalent of a gain block.:>vn .4 F~NCTIONAL MODELS Several ideal subcircuit definitions were introduced in the p~eyious 'section that perform the main function of the circuit blocks they model in a SPICE analysis. The controlled source is connected between nodes node} and node2 and is either a voltage or a current source depending on whether the character at the left of the equal sign is V or I. In a departure from the above circuit models. Linear sources are treated in the same way as in SPICE2.be inappropriate for some analyses. 7. This app~oach was exemplified above for a full adder~mplemented with ideal gates rather than the allNAND TTL transistorlevel implementation used in Example 7. With the hierarchical specification features of SPICE input language. This sec. switches. is supported in SPICE3. These subcircuits are built with just a few SPICE primitives.1 Nonlinear (ArbitraryFunction) Controlled Sources in SPICE3 A single type of nonlinear controlled source. The variable expr is an arbitrary function of the node voltages and currents in the circllit_ All common ~l~m~ntm. and name can be an arbitrary long string. it is possibleto have one description of the toplevel circuit and use different levels of detail in the component building blocks or subcircuits.
EXAMPLE 7. tanh. ln. Wose. tan. respectively. such as 1/ x. Eqs. and atanh. sinh. acosh. asinh.13 to 7. in the frequency domain the source assumes a constant voltage or current value equal to the smallsignal value in the DC operating point (see Sec. therefore.4 Define a functional model of a voltagecontrolled sources.8) ()ose = J: Wose dt = wot +K J: Vc dt = Wo I: (1 + K'vc)dt (7. The nonlinear function applies only to the time domain. vc. These sources are described in the "Analog Behavioral Modeling" section in the PSpice manual (Microsim Corporation 1991). V1s1 and Wo is the signal frequency of the freerunning oscillator when the controlling voltage is zero. and atan. and discontinuous functions. PSpice supports. Controlled sources described by arbitrary functions enable the user to define functional or behavioral models. sin. The function for the B source must express the instantaneous value at any time point.214 7 FUNCTIONAL AND HIERARCHICAL SIMULATION log. and hyperbolie. The following example describes how a voltagecontrolled oscillator can be modeled in SPICE3 using Btype controlled sources.9) Assume that the controlling voltage. for a VCO this function is vose where = Vose sin ()ose (7. and sqrt. can cause an arithmetic exception. Rapidly growing functions. It is important to understand that the SPICE algorithms require nonlinear functions to be continuous and bound. in addition to polynomial sources. A sound approach is to check that the variables of the functions are in a safe range. 7. Vc is implemented as an independent PWL source whose value must be integrated to obtain .2. such as exp(x) and tan(x).7) where K is the VCO gain in rad. oscillator (VCO) in SPICE3 using B Solution A VCO generates a signal whose frequency. Vc: Wose(t) = Wo + Kvc(t) = Wo (1 + K'vc(t)) (7. 7.4. trigonometric. ramps up from 0 V to 1 V in the first half of the time interval and then decreases back to 0 V in the second half of the interval. cosh. is controlled by an input voltage. nonlinear controlled sources equivalent to those in SPICE3 and identified as G or E sources depending on whether the output is current or voltage.15). can cause convergence problems. acos. asin. cos.
END Note that V ( 2) in the expression of BVCO equals the integral of the current through capacitor CINT and represents the time integral of (1 + K'vc) (see Eq.9).5 1 1 0 RIN 1 0 1 * * * * V(2) IS INTEGRAL IN EQ. The model introduced in this example for a VCO is known as afunctional. The SPICE3 Bsource expression does not allow explicit time dependence. Note that the results of these operations are analog. 7. 7.1 and 7.4. Vc = V (1) .PLOT TRAN V(3) V(2) . subtraction.15. a PWL voltage source. 2) in SPICE2 and the arbitraryfunction controlled source in SPICE3 and PSpice. can be used. which varies linearly with time. Addition and multiplication can be achieved with the following polynomial. The waveforms of the controlling voltage.9 BINT 0 2 I=l+V(l) CINT 2 0 1 BVCO 3 0 V=5*SIN(2*PI*10*V(2)) ROUT 3 0 1 * * . 7. or behavioral.01 102M UIC . and division (Epler 1987).9.2 Analog Function Blocks The circuits presented in these sections implement the desired function with the polynomial controlled source (introduced in Chap. or binary. the SPICE3 input circuit is listed below: VCO FUNCTIONAL MODEL FOR SPICE3 * * CONTROL VOLTAGE VC 1 0 PWL 0 0 0. VCVS: EADD 3 0 POLY (2) 1 0 2 0 0 1 1 EMULT 3 0 POLY (2) 1 0 2 0 0 0 0 0 1 .TRAN 0. are shown in Figure 7. and the VCO output. multiplication. rather than digital. The nonlinear controlled source can be used to implement a number of arithmetic functions.3. Vase V (3). 7.FUNCTIONAL MODELS 215 the second term of Eq. as was the case in Examples 7. such as addition. model. Under the assumption that fa = 10 kHz and K' = I VI.
For details on the POLY coefficient specification see Sec. ms 600 Figure 7.16. referenced to ground.I .15 Waveforms Vase and Vc for veo functional model.2. The SPICE specification ofthe two VCCSs needed is GV130101 GV2V3 0 3 POLY (2) 2 0 3 0 0 0 0 0 1 +0 CD (2) + v. .3. The functions implemented by the two elements are V3 V3 = = VI + V2 (7. A divider is slightly more complex and requires two poly sources. .. as shown in Figure 7. 2. 0 +0 v2 0 Figure 7.16 Divider circuit. and V3 are the voltages at nodes 1.2 and 3. V .I.I V I V . 4 If\ vase " II /I II f\ 2 > "C ai :E Ci E a 2 ve «  4 .10) (7. V I V I I I V V V I . V2.I 800 V 200 400 Time. which is node O.11) VI V2 where VI. . .216 7 FUNCTIONAL AND HIERARCHICAL SIMULATION .
is evaluated in AC analysis accordip. The cause of this is the smallsignal nature of AC analysis.VCCSs imposed by the KCL: (7. "dx .fM = = D.FUNCTIONAL MODELS 217 The resulting output voltage..3.2.x . Xl and X2.g to (7.17 and uses a CCCS to transform the current of the bias source. . is performed only in a DC or timedomain largesignal analysis but not in a smallsignal AC analysis. . .13) Therefore. Another useful function that can be implemented with polynomial sources is a meterfor the instantaneous and cumulative power over the time interval of transient analysis.2).XI X2D." . such as multiplication or division. is the quotient VI/V2 because of the equality of the currents of the two.15) fM = XIX2. The value of the function expressed by a nonlinear controlled source f (x + ax) when a small signal ax is added to the quiescent value of the controlling signal x is (7. . V3.12) Note that the large output resistor is needed to satisfy the SPICE topology checker.5.fs D.. " I.J in sinaU~signalanalysis is a linear function given by . and 3.14) .=D. D. the controlled source function tJ. The setup is shown in Figure 7. which 'uses the differential of a nonlinear function in the DC operating point and not the function itself. The derivative offis computed in DC biaspoint analysis in a way similar to the evaluation of smallsignal conductances of semiconductor devices (see Secs. The voltage V3 represents the instantaneous power. 3. which would otherwise flag the two controlled current sources in series as an error.4.j. The addition and multiplication functions implemented with polynomial controlled sources are evaluated according to the following equalitie~ in AC analysis: fs == Xl + X2. An important observation regarding the use of nonlinear controlled sources is that the desired function.X2 +'XID. A controlled source with two arguments.2.X2 (7. 3.XI + D. df" .' D. 3. into a voltage with the correct sign and a VCVS to obtain the product iDD VDD. and V4 is the cumulative . VDD.
0 Figure 7.17) 20 10 > ". by the current time.17 Powermeasuring circuit. . 7.18 is similar to that of a differential amplifier (Gray and Meyer 1993) and is expressed by Vo = Vee tanh V avvid ee (7.0 ° 10 20 1. A good example is the limiter circuit that was used in the previous section at the output of a nonideal opamp block.5 ° 0.16.0 :0.218 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o lQ lQ 0 IF Figure 7. The ease of defining functional models is greatly enhanced by the arbitrary controlled sources available in SPICE3 and PSpice. The output characteristic shown in Figure 7. which can be measured by a PWL voltage source whose value increases proportionally with the analysis time.18 Output of tanh x limiter functional block.5 1. power from 0 to the current time: (7.16) The average power at any time point can be obtained by dividing V4 as given in Eg.
A functional limiter can be built also for SPICE2. 7. The behavior of arctan x is similar to that of tanh x.21) where The functional limiter for SPICE2 is shown in Figure 7.. ex is the CB gain factor.19) where hE is the sum of the emitter currents.18) Its absolute value is limited at 1 for large values of the argument. The functional description of a differential amplifier built with an emittercoupled pair (Gray and Meyer 1993) is as follows: Vo = exRchE tanh (  2~th V"d) (7.. according to the series expansion: tanhx I x . and Rc is the collector resistance. for small values of the argument it is approximately equal to the argument. (7.x 3 3 2 + x 5 = 15 . because the derivative of the arctangent is . which is equal for the two input transistors of a differential pair. 7. and it can be represented by conventional polynomial sources. for small values of the argument it can be approximated by the value of the argument. that is. assuming values between 0 and 7r when x varies from 00 to 00. The behavior of arctan x is identical to that of tanh x.20) Therefore the limiter can be built by implementing the righthand side of Eq.. The limiter built with the arbitrary controlled source defined by Eq. and for large values of the argument it is limited to a constant value. but it takes more components (Mateescu 1991). .arctanu = dt d u' 1 + u2 (7.19.20 and then integrating it to obtain Vo = 2Vcc 7r (f Jo 1 + u2 _U_'_dT _ ~) 2 (7.FUNCTIONAL MODELS 219 In general the function tanhx is ideally suited to implementing a limiter.17 allows the output voltage Vo to follow the input voltage Vid amplified by av as long as avvid is smaller than the supply voltage and then limits Vo to the supply when avvid surpasses the supply voltage.
or integration. its arguments.19 performs a specific function. Another important point is to initialize differentiators and integra . Functional models must be used with care to avoid arithmetic exceptions such as division by zero. Each section is also identified by comments in the SPICE2 input listed in Figure 7.20. 5. and the limiting output function are plotted in Figure 7.19 Circuit diagram of arctan x limiter. The voltages at nodes 2. The voltages representing the values ofthe integral.21. The differentiator is built with an ideal opamp. 6. and 9 are given in the following equations. V2 = U = '7T avVid 2 Vee V9 = u' u' V6 = I t o 1+ u u' dT 2 V7  _ 2Vee 7T (It 0  u' 1 + u2 dT _  7T) 2 Each section in Figure 7. such as division. 7. differentiation.220 7 FUNCTIONAL AND HIERARCHICAL SIMULATION o CD Figure 7. toward the realization of Eq. 7.21.
COMPUTES INTEGRAL OF V (5) E7 7 0 POLY (1) 6 0 15 9. Figure 7.48 lE12 004 lE3 9 1 lE12 A * * COMPUTE U'/(I+U 2) GVP05901 G5 5 0 POLY (2) 2 0 5 0 0 0 1 0 0 0 0 1 R5 5 0 lE12 * * G6 0 6 5 0 1 R6 6 0 lE12 C6 6 0 1 * * INTEGRATION CKT.01 2 0 UIC . EQ.FUNCTIONAL MODELS 221 ARCTAN (X) LIMITER VIN 1 0 PWL 0 1M 2 1M RIN 1 0 lMEG * * * * COMPUTE THE ARGUMENT U.54 R7 7 0 1 * * * LEVELSHIFT AND SCALE * . C3. 7.TRAN .54 R2 2 0 lE12 E3 3 C3 3 R3 4 EDIF RDIF RO 9 * * * DIFFERENTIATION CKT TO COMPUTE U' 0 4 0 9 4 0 201 1 1('=10.END SPICE deck for arctanx limiter. .21 GV 0 2 1 0 lE5 G2 2 0 2 0 9. The capacitor of the differentiator. used in the arctan x function is initialized with the appropriate voltage at t = 0 in order to prevent a convergence failure due to a large voltage at the input of the ideal opamp.PRINT TRAN V(5) V(6) V(7) .20 tors in the expected initial states in order to avoid convergence failures.
such as PSpice and SpicePLUS (Valid Logic Systems 1991).2 by the following transfer function: Ls LCs2 + Ls/R + 1 (7. A functional block that proves very useful in many simulations is a frequencydomain transfer function.22) The PSpice input specification for this block is . With an arbitrary frequencydomain transfer function block one could define the parallel RLC circuit of Example 6. the multiplier. With this capability a variety of filters can be described by the locations of poles and zeros. Both a frequency.PARAM L=lMH C=lNF R=10K EFILTR 1 0 LAPLACE {I(VIN)}={L*s/(L*C*s*s+L/R*s+l)} This block can replace the RLC lumpedelement representation in Example 6. and the differentiator. So far we have defined a number of functional blocks.0 Figure 7. support a frequencydomain transfer function..0 0. such as the adder.mV 0.5 V.2.d= 0 V(1) . the integrator.5 1.21 Simulation results of SPICE2limiter. Some proprietary SPICE simulators.222 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 5 > . these can be saved in a library and then used in any circuit where such blocks are needed. .and a timedomain analysis can be performed with this block."" 0 5 10 15 1.
.2 Assuming that VA and VB take values between 0 and 5 V.23) 3. DeMorgan's theorem (Mano 1976) is applied to transform the OR function into an AND function. 7. such as switches.4. The structure of a universal gate is shown in Figure 7. In order to model the OR function.3.3 Digital Function Blocks In Sec. The elements presented below implement the analog operation of digital circuits.12 kQ 3. The operation of this model is based on the correspondence of the logical AND operation to multiplication. the product must be scaled by 0. which can be implemented as above: a+b=ii. The supply and input resistors are chosen to model the behavior of a TTL gate. logic levels 0 and 1 are expressed in voltages corresponding to positive logic.2.Jj vc (7. which contains only the term VA VB: EAND OUT 0 POLY (2) A 0 BOO 0 0 0 0. The AND function is implemented by the VCVS EAND. that is. digital gates were implemented with simple circuits that are structurally similar to actual implementations but use ideal elements. on ideal building blocks. All digital gates can be described at a functional level with polynomial sources (Sitkowski 1990).12 kQ OUT A B + E 1GQ 1GQ 100Q Figure 7.22.2 so that the output voltage VOUT is 5 V when both inputs are at a logical 1.22 Universal gate functional model.FUNCTIONAL MODELS 223 Exercise Show that the timedomain response of the above block to a current step function calculated by PSpice is identical to the response of the lumped RLC circuit in Figure 6. 7.
224 7 FUNCTIONAL AND HIERARCHICAL SIMULATION The inversion of the input signals is achieved by referencing the two input signals. that is.2. and b. 7. the NAND function. and therefore a fourdimensional polynomial is used.23. leading to the following expression of the XOR function VOUT = O. The XNOR function is implemented by switching the polarity of the VCVS. 2. 7. equivalently. VA an9 VB. iib.2 The order of the coefficients follows the rule introduced in Sec.3.2 0 0 0 0 0 0 0.4. and the NOR function needs only the inputs inverted. is achieved by inverting the polarity of the controlled source and subtracting 5 V from the result.2 The NAND function needs only to have the output inverted. Note that for SPICE2 the node names used above must be replaced by numbers: i 7. .24) a E9 b = iib + ab These functions need four variables. The only terms of the polynomial used in both functions are the product of variables I and 2. with respect to the AND function. to Vee rather than to ground. hydraulic.2 0 0 0 0 0 0 0. and the product of variables 3 and 4. Each variable and its inverse introduce two controlling voltages. according to Eq.4 Equation Solution The operation of electrical systems as well as nonelectric systems. respectively. ii.23: ENAND 0 OUT POLY(2) ENNOR OUT 0 POLY(2) A 0 B 0 5 0 0 0 0. The functional models defined above can be combined in creative ways to solve most complex equations describing not only electrical but also other physical systems. ab. are described by complex nonlinear differential equations.2 A 0 VC B 5 0 0 0 0 0 0. a. and electromechanical systems. input a is VA and input ii is Vee . such as mechanical. b. the inversion of the output function.VBWA The two terms require the definition of coefficients P6 and P13 for both XOR and XNOR. In order to simulate these devices with SPICE it is necessary to create a model or.2 The XOR and XNOR functions are implemented according to the definition (7.VAWB + O.2(Vee . the OR function becomes EaR 0 OUT POLY(2) A VC B VC 5 0 0 0 0. EXOR OUT 0 POLY(4) VC ABO EXNOR 0 OUT POLY (4) VC ABO A 0 VC BOO 0 0 0 0 0. According to Eq.2 A VC B VC 0 0 0 0 0.2(Vee . to cast the component equation in a form that the program can understand and solve.VA' The SPICE definitions of the VCVS for the XOR and XNOR functions are.
The circuit is shown in Figure 7. 7. it can be implemented as a nonlinear controlled voltage source. Note that for PSpice the definitions of G and of the arbitrary controlled sources BRHS and BLAMP need to be changed to the following syntax: ERHS 6 0 VALUE={2.2)S. BLAMP.)2 + f I V V (7.. V.186E4*PWR((I(VA)/V(2)) + +271.!)' V where G(V.= ~ aI2 + bIV + c V2 + d (I V )3 + e (I. Eq. b. which are then added.25) where G is the conductance of the lamp.25.2) The IV characteristic of the lamp obtained from SPICE3 is plotted in Figure 7. the current of which is I = GO'.7 The rest of parameters.25 and corresponds to the operation known from text books. Solution The main part of the model is the defining equation of the conductance G. 7. of the lamp is defined by the following equation: dG . such as multipliers and dividers. 7.422*PWR(I(VA). I. Create a model for both an arbitrary controlled source as well as a polynomial controlled source implementation.5 With the functional blocks defined above develop a circuit that can be used in SPICE to model the turnon IV characteristic of a fluorescent discharge lamp. BRHS. and the voltage.24. equal to the integral of the righthand side of Eq. equal zero. The result is integrated to obtain V(G 1).7*(I(VA)!V(2))} GLAMP 4 5 VALUE={ V(Gl) W(IN) } . The corresponding SPICE3 description is shown in Figure 7. and d.FUNCTIONAL MODELS 225 EXAMPLE 7.23. which sums the terms on the righthand side of Eq. . The relationship between the current. 7.25. 7. c.422. After designing the complete model defined by Eq. f = 271. The lamp is represented by a nonlinear controlled current source. which implement the terms of the righthand side of Eq. I) is the voltage at node G 1.25. A SPICE2 model can be developed using functional blocks.25.25. simulate the turnon characteristic for a lamp with the following parameters: a = 2.
IC V(G1)=1 V(IN)=201 .0 .01E+02 2E+02 6E+01 1.SUBCKT INTEG 1 2 RIN1 1 4 2 RIN2 1 4 2 G1 2 0 4 0 1 R1 2 0 1E12 C1 2 0 1 .2E02 0 ) VB 7 8 PWL ( 0 0 0.7*(I(VA)!V(2)) R8 7 4 978M R7 5 4 10MEG R6 0 IN 1K BLAMP 4 5 I=V(G1)*V(IN) EV5IN0451 L3 0 3.TRAN 0. .422*(I(VA)A2)5.ENDS INTEG VI 5 3 0.55. FLUORESCENT LAMP VA 8 0 DC 201 SIN ( 2.005 .1 0 .24 SPICE3 input for the fluorescent lamp functional model.5M UIC .226 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 0 vB Ra CD J 1 @ + BLAMP 1= VGl VIN R7 10MQ ClO 100 pF VA + EVS R6 +  0 @)  BRHS Figure 7.1 100 ) C10 4 5 lOOP BRHS 6 0 V=2.END Figure 7.186E04*((I(VA)!V(2))A2)+271. 7M XF2 6 G1 INT1M .23 Fluorescent lamp functional model.
called macromodeling. 7. Cohn. which contain ten to a hundred transistors in a detailed representation.25 1V characteristic of fluorescent lamp. This concept was first applied to opamps (Boyle. This section introduces the most general and powerful modeling concept.MACROMODELS 227 V1N. in order to obtain the behavior of the original circuit from a simplified circuit that can be simulated several times faster. A SPICE simulation of a circuit with morethan a couple of opamps can be very expensive. phaselocked loops. and the development of macromodels that implement all or part of the databook characteristics of a given opamp is crucial. Macromodels combine functional elements with accurate nonlinear models for some elements. The components used to model specific characteristics are identified.5 MACROMODELS A number of concepts have been introduced so far in this chapter on higherlevel modeling. and control systems.V Figure 7. and Solomon 1974). The approaches have varied from structural simplifications of the circuit using ideal elements to pure functional blocks. and their evaluation from the data sheet is highlighted. The next section describes a common opamp macromodel. . such as transistors and diodes. Since the introduction in IC realization in the late 1960s. which synthesize the input/output relationship of the circuit. opamps have been widely used in such circuits as active filters. Pederson.
and four diodes are used in the output stage for limiting the voltage excursion and the shortcircuit current. model parameter BF.1. At the conclusion of this section the switching and frequencydomain characteristics of the macromodel compared with those of the detailed circuit are shown in Figures 7. slew rate. gain.31 and 7. is derived from the DC offset and the slew rate.26. equal to Iez. voltage swing.33. such as offset.I B IBI + IBos 2' (7. Is! and IS2. The gain stage is built with linear elements.1 7 FUNCTIONAL AND HIERARCHICAL SIMULATION The Opamp MacroModel The macromodel developed by Boyle et al. which are necessary to model the correct input characteristics.5. the three stages are modeled separately to implement all the datasheet characteristics. The macromodel ofthe JLA 741 opamp is divided into three distinct stages. input and output characteristics.26) IB of Q! and Qz is taken from the data sheet.26 and 7.28) which leads to the values of the model parameter IS of Q! and Qz. Vos. and compensation capacitor Cz: S. The schematic ofthe macromodel is shown in Figure 7. 7. (7. IBos: . is established by the positivegoing slew rate. Table 7.228 7. ICl. The number of transistors in the macromodel has been reduced to only two. of the two transistors. is due to an inequality in the two saturation currents. the macromodel attempts to provide an accurate representation of differential and commonmode gain versus frequency characteristics. (1974) is described in this section. These characteristics are presented in Table 7. f3F.1. The element values and model parameters of Q! and Qz must be derived from the opamp data sheet. shortcircuit current limiting. The macromodel derivation for the JLA741 is outlined below according to Boyle et al. The input stage must be designed to reproduce characteristics such as DC offset. and slew rate. according to the following equation: (7. containing 26 BJTs. and an imbalance is introduced to account for the offset input current. The gain factor. 7. The approach described below can be applied to model a broad class of opamps. the input. the input offset voltage. Unlike the ideal opamp described in Sec.3. . (1974).27. and frequency rolloff. is shown in Figure 7.27) f3F1 and f3F2 are derived from Eqs. and output stages.1.27. The detailed circuit. and accurate largesignal characteristics.
.26 Detailed JLA741 circuit.0 ~ ~ Biasing reference network Input stage Intermediate stage Output stage Figure 7.+Vcc @ @ B 1 A @ Qg 39kn<Rs Cf @ R4 R1 R3 @ VEE 1.
=..! 0 (~ 11 1 1'1 f =. .27 p. y)\.W Q ~ o (Vee! Ve = Rc2 0 Rp Vb D3 @ C2 .= r y~) (V \. 1 (VEE) y~) \.=.A741 macromodel. GemVe I I GaVa 1 I 0(+) \{2. Inputstage Interstage Outputstage Figure 7. VC @ Ral Vs CD R2 v. GbVb I L1EE r D1 D2 D4 H@ Gevs @ c.
3 106 566 76.103 16. The frequency of the dominant pole.2 12.62 80 20 1 2.9 0.72 256 0.217.MACROMODELS 231 Table 7. f3dB.7 0.2 14.105 1.8 25 25 14 13.899 0. of 200 V: (7.1 Parameter Cz (pF) fLA741 Performance Characteristics DeviceLevel Model 30 0.105 103 20 90 75 MacroModel 30 0.5 25.2 12.105 1.9 14.7 Data Sheet 30 0.219. C (7.8 26.9 25.67 0.265 4. is given by (7. RE is chosen so that it matches the output resistance of a transistor with an Early voltage.103 16.2 26.7 S.16. VAF.283 4.17.29) where hE is the sum of the collector and base currents of QI and Q2. (V/fLs) Si (V/fLS) IB (nA) IBos (nA) Vos (mV) avd avd (l kHz) !1c/J(degrees) CMRR(dB) Rout (n) Roose (n) Is~ (rnA) Is~ (rnA) V+(V) V.30) Rei and Rc2 can be derived from the equality 1 Rei = Rc2 = 2 7TJOdB r. set by the compensation capacitor C2 and by Ga = I/ReI.31) 2 .718 255 <1 0.(V) The emitter resistor. The frequency response is established by resistors Rei and Rc2 in the input stage and components of the gain stage.8 106 566 76.
CE and C1• The first is included to model a smaller negativegoing slew rate Sii according to the following equality: \ C1 models the excess phase at fOdB (7. . CM.37) aye = GemR2 whereR2 = lOOk!1andGa = l/Rcl.<jJ given in the data sheet. are defined by the following equalities: aYd =  R2 Rcl (7. and is given by (7. This is achieved by a correct sizing of the transconductances Gem and Gb' The two gains. gains.33) by introducing a second pole at (7.39) where Ro2 is approximately equal to the DC output resistance given in the data sheet. aYd and aye. and is equal to 1 (CMRR)Rcl ayd.36) (7. Gem = (7.38) Transconductance Gb defines the correct openloop DM gain.34) With the phase shift !i.232 7 FUNCTIONAL AND HIERARCHICAL SIMULATION where fOdB is the OdB frequency from the data sheet.35) The gain stage is designed to provide the correct differential mode. CMRR = ayd/ aye. rolloff of 6dB/octave by fOdB can be approximated for a (7. C 1 results as (7. and common mode.32) There are two more capacitors in the input stage.ThevalueofGemisbasedonthecommonmode rejection ratio. DM.
28.0925.2 Parameter lSI (A) p. A 20. the two inputs.A741 circuit shown in Figure 7.1516 37.29.MACROMODELS . and X2 is described by the complete circuit.A741. and for the macromodel. Xl is represented by the macromodel.27 with the component values from Table 7.28.363 229. The circuit for the slewrate performance is shown in Figure 7.1016 8. Table 7.p.30.LA) Rei (0) Rei (0) RE (MO) (pF) CI (pF) Rz (KO) Cz (pF) CE 8. UA 741. 1016 0. reproduced from Boyle et a1. called UA 7 41MAC. UA 7 41MAC.6726 52. for the detailed derivation of this model see that paper.5 V to 5 V is applied to the positive input ports of both opamps. Xl and X2.5288 100 30 Gb(mho) Rol(O) Roz(O) Ism (A) Ism (A) Rc(mO) Gc (mho) Vc (V) VE (V) .2696 7. are used in order to compare the output voltages.A741 MacroModel Value Parameters Parameter Rp(kO) Ga({.774 1. listed in Figure 7.Lmho) Gem(nmho) Value 15. The complete list of the parameters of the macromodel is provided in Table 7. and the SPICE input is shown in Figure 7. for the two opamp models. and the two supplies.1042 b(A) (31 (3z leE ({.1986 5034.2.s pulse from .2 3.8 489.26 and the macromodel in Figure 7.7962 27.1O3Z 8.31 and can be seen to match very well. write the SPICE netlist for the detailed p.9 7.6 Compare the voltagefollower slewrate performance and the openloop f~equency response to fOdB between the complete p.8218 . V3 and V6. (1974).3 1. the output.233 The design of the output stage of the macromodel requires the dimensioning of diodes D1 and D2 and resistor Ra1 for current limiting and diodes D3 and D4 and bias sources Vc and VE for proper output voltage limiting. Solution First.6042 3.1016 52. Both subcircuits have five external terminals. The offset voltages Vas corresponding to each model are applied as DC biases at the inputs of the two opamps. called subcircuit UA 741.0978 76. EXAMPLE 7. The two waveforms of VOUT are plotted in Figure 7.512 4352 2391.5 4.2. The two subcircuit definitions are listed in Figure 7. Note that two unconnected voltage followers.
234 7 FUNCTIONAL AND HIERARCHICAL SIMULATION ************************************* * * DETAILED CIRCUIT FROM BOYLE PAPER * ************************************* . .6 C2=1653 IK=1.36P IS=1.26E15 VA=178.SUBCKT UA741 1 2 24 27 26 NODES: 1m.15N TR=405N + CJE=0.33 PC=0.OUT VCC VEE R1 10 26 1K R2 9 26 50K R3 11 26 1K R4 12 26 3K R5 15 17 39K R6 23 24 50 R7 24 25 25 R8 18 26 100 R9 14 26 50K R10 21 20 40K R11 13 26 50K CaMP 22 8 30PF Q1 3 1 4 BNP1 Q2 3 2 5 BNP1 Q3 7 6 4 BPN1 Q4 8 6 5 BPN1 Q5 7 9 10 BNP1 Q6 8 9 11 BNP1 Q7 27 7 9 BNP1 Q8 3 3 27 BPN1 Q9 6 3 27 BPN1 Q10 6 15 12 BNP1 Q11 15 15 26 BNP1 Q12 17 17 27 BPN1 Q13A 28 17 27 BPN3 Q13B 22 17 27 BPN4 Q14 27 28 23 BNP2 Q15 28 23 24 BNP1 Q16 27 8 14 BNP1 Q17 22 14 18 BNP1 Q18 28 21 20 BNP1 Q19 28 28 21 BNP1 Q20 26 20 25 BPN2 Q21 13 25 24 BPN1 Q22 8 13 26 BNP1 Q23A 26 22 20 BPN5 Q23B 26 22 8 BPN6 Q24 13 13 26 BNP1 * .611M NE=2 PE=0.417P TF=1.6 + ME=0.45 MC=0.MODEL BNP1 NPN BF=209 BR=2.28 Detailed description and macromodel of the JLA741 opamp.33 Figure 7.IN.5 RB=670 RC=300 CCS=1.65P CJC=0.
37K lK=171.MODEL BNP2 NPN BF=400 BR=6. 8 BR=1.45 MC=0.5N TR=2120N + CJE=1.4N TR=220N + CJE=0.55 C2=84.SUBCKT UA741MAC 3 2 6 7 4 NODES: IN+ IN.MODEL BPN5 PNP BF=80 BR=1.ENDS * * UA741 ********************* UA741 MACROMODEL * ********************* .MODEL BPN1 PNP BF=75 BR=3.MACROMODELS 235 .76N TR=243N CJE=2.1516N GA 12 0 8 9 229.90P CJC=2.5288P RP 7 4 15.25 .45 + ME=0.55U NE=2 PE=0.MODEL BPN4 PNP BF=14.MODEL BPN2 PNP BF=117 BR=4.5 RB=1100 RC=170 TF=26.45 C2=1219 lK=80.90P lS=2.126P TF=27.33 PC=0.363K GCM 0 12 1 0 1.6 MC=0.25 .33 PC=0.45 + ME=0.25 PC=0.774U R2 12 0 lOOK C2 12 13 30P GB 13 0 12 0 37.45 MC=0.455P TF=0.55U NE=2 PE=0.MODEL BPN3 PNP BF=13. 9 RE2 1 11 2391.0978 R02 13 0 489.25 + + * .11 C2=1764 lK=270U NE=2 PE=0.8 RB=80 RC=156 TF=27.395E15 VA=267 C2=1543 lK=10M NE=2 PE=0.126P TF=27.0 RB=650 RC=100 TF=26.8P CJC=1.10P CJC=1.6E15 VA=57.55P lS=0.MODEL BPN6 PNP BF=19 BR=1.8 Dl 13 14 DMODl Figure 7.5N TR=9550N + CJE=0.25E15 VA=83.3P lS=2.6 + ME=0.6 MC=0.25 PC=0.37K lK=5M NE=2 PE=0.15E15 VA=55.1 C2=57.6 + ME=0.8 BR=1. 9 RE 1 0 7.259P TF=27.33 .33 PC=0.10P CJC=2.4N TR=2540N + CJE=0.94 C2=478.8 RB=500 RC=150 CCS=2.10P CJC=0.33 .25E15 VA=83.4 lK=590.25 PC=0. 4 RB=100 RC=80 CCS=2 . 4N TR=55N + CJE=0.05P lS=3.49K lK=80.45 + ME=0.4N TR=2540N + CJE=4.80P lS=17.33 .512U C1 8 9 4.63E17 VA=167.79E15 VA=79.55 C2=84.2 R01 13 6 76.33 PC=0.5P lEE 1 4 27.10P CJC=0.8U NE=2 PE=0.OUT VCC VEE Q1 8 2 10 QMODl Q2 9 3 11 QMOD2 RC1 7 8 4352 RC2 7 9 4352 RE1 1 10 2391.5 RB=160 RC=120 CCS=2.6 + ME=0.45 MC=0.6 ME=0.7U NE=2 PE=0.33 .28 (continued) .40P lS=0.27MEG CE 1 07.40P lS=0.1 RB=185 RC=15 CCS=3.45 MC=0.05P CJC=2.6 MC=0.
0925E16 BF=52.7962 .8218E32 .30 .MODEL QMOD1 NPN IS=8E16 BF=52.1042 * . Figure 7.MODEL DMOD3 D IS=8E16 .TRAN .25U SOU .END SPICE input for voltagefollower configuration for slewrate comparison.236 7 FUNCTIONAL AND HIERARCHICAL SIMULATION D2 14 13 DMODl *EC 0 14 6 0 1 GC 0 14 6 0 5034. UA741 SLEW RATE * MACROMODEL Xl 1 3 3 4 5 UA741MAC * FULL MODEL X2 2 6 6 4 5 UA741 VIN1 10 0 DC .3 RC 14 0 0.6726 .MODEL DMOD1 D IS=3.2765M PULSE 5 SOlON VIN2 11 0 DC .1986M D3 6 15 DMOD3 D4 16 6 DMOD3 VC 7 15 1.29 Voltage follower configuration for slewrate comparison.2834M PULSE 5 SOlON RIN1 10 1 100 RIN2 11 2 100 VCC 4 0 15 VEE 5 0 15 * 10N 20U 100U AC 1 10N 20U 100U AC 1 * .6042 VE 16 4 3.MODEL QMOD2 NPN IS=8.28 Figure 7.OPTIONS ACCT .ENDS (continued) Figure 7.
lIS 30 40 Figure 7.32 . Figure 7.TF . as shown in Figure 7.33. the pulse is replaced by an AC source.1 1G SPICE input for openloop frequency response comparison.2834M AC 1 VCC 4 0 15 VEE 5 0 15 * * * * * V(3) .AC DEC 10 . are in an openloop configuration.MACROMODELS 237 4 2 > . Xl and X2. END VIN1 . The magnitudes ofthe two output signals are plotted in Figure 7.TF V(6) VIN2 . The two models track UA741 FREQUENCY RESPONSE MACROMODEL Xl 1 0 3 4 5 UA741MAC * FULL MODEL X2 2 0 6 4 5 UA741 VIN1 1 0 DC . so that the two opamps.32. and the frequency range is set from below the dominant pole defined by the compensation capacitor to six orders of magnitude above that value..0 s 0 2 4 10 20 Time. The SPICE input for the frequency response is modified.2765M AC 1 VIN2 2 0 DC .31 Slewrate results for opamp models.
33 Openloop frequency response comparison. versus only 2 for the macromodel. where the complete circuit requires 56 s versus only 5 s for the macromodel. The same analysis performed by PSpice 01). The gains in analysis time become significant for the transient analysis.uA741 circuit and 0. The reductions in circuit complexity and simulation time are important advantages for macromodels. This option also shows that the run time for the openloop DC operating point is 1.17 sand 21 iterations for the complete . These results were obtained from SPICE2 running on a SUN 4/110 workstation. an IBM PS/2 Model 80 equipped with a 16 MHz 386 processor requires 209 s for the complete circuit versus 14 s for the macromodel. The accounting information option of SPICE. . because in SPICE the transistor is the most timeconsuming component to evaluate. The simpler circuit takes only half the number of iterations used by the full opamp circuit. ACCT (see Sec. 9 for more details. 9. The performance gain is achieved in the analysis of the macromodel circuit partly because fewer time points and iterations are required by this solution. This ratio is very important. offers detailed information on the two circuits. see Chap. a performance gain of 11. each other very well up to 1 MHz. the complete circuit has 26 BITs. versus 16 nodes and 26 elements for the macromodel.5.1). Hz Figure 7.238 7 FUNCTIONAL AND HIERARCHICAL SIMULATION 100 50 OJ "0 "0 :J <Ii '2 Ol ::2: t1l 0 50 100 Frequency.25 sand 32 iterations for the macromodel. Separate runs for individual opamps show that the complete circuit has 79 nodes and 38 components. The above characterization is useful for identifying the range of the macromodel's validity for different applications. after which secondary poles and zeros come into play. In addition.
the savings in run time are of major significance.SUMMARY 239 An important conclusion to the modeling practices described in this chapter is that SPICE can accommodate different levels of accuracy in the representations of circuits. SpicePLUSlProfile. It is up to the user to decide which behavior of a circuit block is important and needs to be modeled for the correct operation of an entire circuit. A number of useful functional blocks can be defined using the polynomial controlled sources available in all SPICE simulators. The subcircuit definition. Ideal models describe the single most relevant function of a device and can be used for computational efficiency in circuits where the ideal blocks are not critical for the circuit performance.. 7. a nearly ideal model of an opamp can run up to two orders of magnitude faster. which need not be electrical.. Functional models implement complex analytical currentvoltage expressions with one or more nonlinear controlled sources. 1991) and Saber (Analogy Inc. such as transistors and capacitors. This approach to modeling and simulation is known as highlevel.27.. Ideal opamps can be used in active filters. Whereas the detailed macromodel can save up to an order of magnitude in run time. a global statement. and the subcircuit instance are defined by the following syntax: • SUBCKT SUBname nodel <node2 . > circuit elements • ENDS Xname xnodel <xnode2 . or behavioral. For the opamp macromodel varying degrees of accuracy can be implemented.. and ideal logic gates save analysis time in mixed analog/digital circuits. voltagecontrolled oscillators. Devices described by complex equations. The SPICE language provides constructs for identifying subcircuits and instantiating them in the circuit description. as exemplified by several digital building blocks.6 SUMMARY This chapter has introduced several concepts pertaining to modeling and simulating electric circuits and systems. which are applicable as well to nonelectrical physical systems.6 to the complex macromodel of Figure 7.1991) make it possible to model circuit blocks such as limiters. With the reduction in complexity. can also be simulated using arbitrary controlled sources. and phaselocked loops with just a few components. from the ideal model in Figure 7. . HSPICE (MetaSoftware Inc. The arbitrary controlled source introduced in SPICE3 and the equivalent or more powerful capabilities in PSpice. in contrast to the structural representation common to circuit schematics. The first step in defining circuit representational levels is to identify a hierarchy when describing a more complex circuit. > SUBname These statements can be nested to create several levels in a hierarchical circuit description. Highlevel circuit representations have been presented in three categories depending on the level of accuracy. Macromodels can achieve the accuracy of a detailed circuit with important savings in analysis time by combining structural elements..
New York: John Wiley & Sons. 1992. CA: Author. B. 1982.. and Schwartz. Newton. Dorf. New York: McGrawHill. Valid Logic Systems. CA: Author. . A. Gray. A. C. Epler. Simulation and modelingThe macromodeling of logic functions for the SPICE simulator.2. G. R. and lOA. 1983. Pederson. Analysis and Design of Analog Integrated Circuits. A. IEEE Circuits and Devices Magazine 6 (September). MetaSoftware Inc. P. of California. Welldesigned macromodels can be simulated up to an order of magnitude faster than the detailed model with little if any loss in accuracy. 1990. Berkeley (August). IEEE Journal of SolidState Circuits (December). Englewood Cliffs.. C. 1991. G. Computer System Architecture.. G. PSpice. Microsim Corporation.. Cohn. L. 1976. 10. and K. B. D. Analysis and Design of Digital Integrated Circuits. D.Vincentelli. Meyer. Univ. 2. 1987. S. CA: Author. 1991. ERL Memo UCBIERL M82175 (October). Saber Users Guide. M. IEEE Circuits and Devices Magazine 3 (September). and 1. OR: Author. 1993. R.0. Oldham. Jackson. HSPICE Users Guide. Mateescu. A. as shown in one ofthe examples.. Macromodeling of integrated circuit operational amplifiers. Introduction to Electronics.3. 1987. as well as in Secs. M. G. R. Vladimirescu. Sitkowski. and R. Smith. New York: McGrawHill. Analog Workbench Reference. Univ. A. New York: McGrawHill. Personal communication. Analogy Inc.2. Solomon.. Berkeley. A. Vol. Version 5. Beaverton. Circuit Analysis Users Guide. and H. M. Paul. LSI circuit simulation on Vector computers. 1989. K. and A. 1981. 1991. Both analog and digital circuit examples have been presented in this chapter to highlight the diverse approaches to highlevel modeling. O. Saunders. R. Dept. Microelectronic Circuits. Analysis of Linear Circuits. New York: John Wiley & Sons. Philadelphia: W. 3d ed. NJ: Prentice Hall. R. E. C. 1989. Sangiovanni. Zhang. W.240 7 FUNCTIONAL AND HIERARCHICAL SIMULATION with functional blocks implemented with controlled sources. D.0. Pederson. SPICE version 2G User's Guide. Mano. Campbell. 10. Release 3. of California. 1990. A cautionary note at the conclusion of this chapter regarding the accuracy of the results using highlevel representations: the analysis is only as accurate as the models used! Erroneous operation as well as analysis difficulties can result from using idealized models. Hodges. 1974. Introduction to Electric Circuits. M. REFERENCES Boyle. of Electrical Engineering and Computer Science. San Jose. SPICE2 application notes for dependent sources. O. Sedra. 1990. Vladimirescu. Irvine. B.
In this section the effect of frequencydependent circuit elements is considered in the derivation of the distortion measures. it is important to understand how to use largesignal timedomain analysis to derive the same distortion measures computed by the smallsignal analysis.1 DISTORTION IN SEMICONDUCTOR CIRCUITS This chapter describes in detail the evaluation of distortion in electronic circuits with SPICE. 241 . 5. in Sec. Emphasis is placed on the smallsignal distortion analysis in SPICE2. 5. 8. which is a powerful tool for designing electronic circuits and ICs. Therefore. 8.2. The total distortion measures are broken down in the SPICE2 output into contributions for each nonlinearity of each diode or BJT in the circuit as exemplified in Sec. 5 the distortion measures were derived for a nearly linear frequencyindependent circuit.4. 8.3 describes the application of Fourier analysis for verifying the results of the onetransistor amplifier and for deriving the intermodulation component for a mixer. A more rigorous analysis of distortion components for a singletransistor amplifier and a mixer circuit is carried out in this chapter.2. 5 was limited to frequencyindependent circuits. SPICE2 provides more distortion information about a circuit than shown in Chap.2.Eight DISTORTION ANALYSIS 8. 8. The main features of the smallsignal distortion analysis were presented in Sec. Sec. The signal amplitude is often larger than the limit for small signals. The distortion analysis presented in Chap.2 SMALLSIGNAL DISTORTION ANALYSIS In Chap.
1) Sia is the result of passing the input signal. are obtained by taking into account all three transfer functions. In Figure 8. Sia: (8.242 8 DISTORTION ANALYSIS The SPICE2 capability of reporting individual distortion sources is explained and the additional feature of the AC analysis that provides a frequency sweep of the distortion coefficients is exemplified. Si. A new operator is introduced. The higherorder terms in the output signal. The two linear filters have transfer functions F(j w) and J(jw).2) . a power series is used to express the highorder terms of the signal at the output of a nonlinear circuit. A. are added to the nonlinear gain block A.1 HighFrequency Distortion In the absence of frequencydependent elements.1 Nonlinear gain block with input and output filters. of the nonlinear gain block. . respectively. So. both filters. to simplify the above expression of Sia to Sia = F(jW)oSi (8. 8. is a power series of the input to A. The output. Soa. Si through F(jw) to get = SI cosw1t + S2cosw2t (8.2. The approach consists of expressing the transfer function of a circuit containing both small nonlinearities and frequencydependent elements (Meyer 1979.4) F(jOJ) J( jOJ) Figure 8. 0. where IF(j w)1 is the magnitude and cPw is the phase of the transfer function.1 two frequencydependent linear circuit blocks. A more general series expansion of a signal is derived below for computing the distortion terms. Pederson and Mayaram 1990).
W] and W2.(2) + cos(2a] + (2)]} + cf>w] W2t + cf>w2 WIt (8.ad + COS(2a2 + a])] + cos(2a] . 8.8) The argument of J in Eq. Wa. The above result is generally valid for circuits with memoryless nonlinearities and linear frequencydependent elements.{[IF(jw])13Sr(COS3a] + (2) + cos(a] . is obtained by including the contribution of the second frequencydependent block. Saa2. The above power series expansion of the output signal is also known as a Volterra series (Narayanan 1967). limited to three terms and up to three signal frequencies. We. are useful for deriving the distortion components in the following section: Saa] =a][IF(jw])IS] Saa2 cosa] + IF(jW2)IS2 cosa2] + 1) + IF(jW2)12Si(cos2a2 cos(a] = ~{[IF(jw])12Sr(COS2a] + 1)] (8. J(jw): So = a]F(jwa)J(jwa) 0 Si + a2F(jwa)F(jWb)J(jWa. which are listed below for an input signal with two frequencies. jWb) + a3F(jWa)F(jWb)F(jwe)J(jwa. .8 is the frequency of a given spectral component which in tum is a linear combination of the input frequencies Wa.7) The signal at the output. and We. Wb. and Saa3. The signal at the output of the nonlinear gain block is a power series of the input signal.(2)]} + 3cos(2)] + 3cosad + IF(jW2)13Si(cos3a2 + 3!F(jwdIS]IF(jW2)12Si[2cosa] + 3IF(jw])!2SrIF(jW2)IS2[2cosa2 In the above equations a] and a2 represent a] a2 = = + COS(2a2 . Wb. jwe) 0 Sf (8. 0 Sf jWb. So. the output becomes Saa = Saa] + Saa2 + Saa3 = a]F(jwa) 0 Si + a2F(jwa)F(jWb) 0 Sf + a3F(jWa)F(jWb)F(jWe) 0 Sf (8.SMALLSIGNAL DISTORTION ANALYSIS 243 The meaning of applying F through the operator 0 on the input signal Si is to multiply the amplitude Sn of each frequency component in Si by IF(jwn)1 and shift its phase by cf>wn.5) The detailed expressions of Saa].6) + 2IF(jwdIIF(jW2)IS]S2[ a Saa3 = .
OP .DISTO RL 1 * .MODEL + + QMOD NPN RB=100 CJE=lP CJC=2P .2.2 Onetransistor amplifier input and DC bias point.OPTION NOPAGE .000 DEG C INPUT LISTING ************************************************************************* Q1 2 1 0 QMOD RL 2 3 1K * VCC 3 0 5 VEE 4 0 793. The linear equivalent of the onetransistor ******* 04/07/89 ******** SPICE 2G. 8. The DC bias solution and the smallsignal parameters of Ql are recomputed and the results are in Figure 8.2.6 3/15/83******** 16:14:42 ***** ONETRANSISTOR ***** CIRCUIT (Figure 5. 8. In conclusion. 5 can be derived as ratios of the second.244 8 DISTORTION ANALYSIS The different distortion measures introduced in Chap.2 Distortion in a OneTransistor Amplifier Consider the onetransistor amplifier of Figure 5.END Figure 8. and We.PRINT DISTO HD2 HD3 SIM2 DIM2 DIM3 .2. second.WIDTH OUT=80 . The following section exemplifies the use of this approach.or thirdorder terms in Eqs. and third order can be isolated to compute the distortions of corresponding order. the distortion terms of a signal at the output of a frequencydependent circuit with small nonlinearities can be found by writing the overall transfer function and replacing the nonlinear signals by series expansions. .8) TEMPERATURE = 27.8 and by an appropriate assignment of ::tWl and ::tW2 to Wa.AC LIN 1 1MEG 1MEG . RB.4M VI 1 4 AC 1 * * .8 with a series base resistance. Transfer functions of first. as listed in Figure 8. of 100 n and junction capacitances CJE and CJC added to the •MODEL statement. Wb.
000 1.0522 TEMPERATURE = 27.OOE+OO CCS O. 95E05 IC 1.000 FT 4.948D03 1.000 TOTAL POWER DISSIPATION **** **** OPERATING POINT INFORMATION TRANSISTORS DEG C BIPOLAR JUNCTION Q1 MODEL QMOD IE 1.00D12 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.00D12 2.00E+12 CPI 1. 000 1.33E+03 RX 1.2 (continued) 245 .26E12 CBX O.OOE+OO BETAAC 100.**** TYPE IS BF NF BR NR RB CJE CJC BIT MODEL PARAMETERS QMOD NPN 1.72E12 CMU 1.948D05 1.000 DEG C **** NODE 1) TEMPERATURE NODE ( 3) VOLTAGE 5.052 BETADC 100.02E+09 Figure 8.793 VBC 2.7934 NODE ( 2) VOLTAGE 3.000 1.53E02 RPI 1.00D16 100.000 100.00E+02 RO 1.75D03 WATTS TEMPERATURE = 27.0000 = 27. 000 1.000 DEG C VOLTAGE NAME VCC VBE VI SOURCE CURRENTS CURRENT 1.259 VCE 3. 95E03 VBE 0.000 8M 7.948D05 9.
equal to 1 in the deck shown in Figure 8. can be expressed as Taylor series around the DC operating values.and thirdorder distortion terms. the DISTORT I ON FREQUENCY and MAG and PHS of the transfer functions for the input signals are listed on the following line. More detail than just the total distortion figures is obtained from SPICE2 when a summary interval. and CJL in the linear equivalent in Figure 8. which are listed under the AC ANALYS I S header. The BJT DISTORTION COMPONENTS are due to the nonlinear voltage dependencies of Ie.4. The DISTORTION ANALYSIS summary report lists five groups of BJT DISTORTION COMPONENTS. such as 2ND HARMONIC DISTORTION. and QBe in the firstorder terms of the corresponding Taylor expansions. C1T. The distortion summary computed by SPICE2 at 1 MHz is listed in Figure 8.19 through 5. SIM2 and DIM2. 5. Note that the addition of the base resistance and the two charge nonlinearities do not significantly affect the absolute values of the second. The higherorder terms of this series constitute distortion sources.9). FREQ1. but the more simple EbersMoll . Each group starts with a header identifying the type of distortion.4. QBE. The distortion contribution in the load resistor is computed for every element in Figure 8.3   l ~ Smallsignal equivalent of the onetransistor amplifier.3. Note that the current equations for Ie and IB in distortion analysis use not the GummelPoon formulation given in Appendix A. 5. as described in Chap. The elements g1T' gJL' gm. QBE. amplifier is shown in Figure 8. Ie. in the same manner as derived in Eqs.4 (Figure 5.21 for an approximation of ie. as compared to the results obtained at 1 kHz in Sec. 5.2.3 associated with a nonlinearity of the transistor.14. 3. go. ie and iB.10 through 3. and the fundamental frequency. for one input signal or FREQl and FREQ2 for two input signals. 5. The contribution of each second or third derivative in the Taylor series to the output distortion is listed in the corresponding column of the SPICE2 printout.3 represent the partial derivatives of IB. as defined in Eqs. DISTO statement. is specified in the. The total currents. HD2 and HD3. see Sec. and the secondorder intermodulation terms. IB. Ie and IB. and QBe.246 8 DISTORTION ANALYSIS rr~l : RB Q1 B' e~ c I~ I I I io + n r en IVb'  o r ! I I I I I I I Figure 8.
98 75.842D02 GO 1.000D20 4.600DI0 PHS 166.016D03 1.000D20 PHS 0.10 GM023 4.509D06 76.871D09 21.10 164.000D20 PHS 0.00D+06 PHS HZ 176.598Dll 38.30 GMU 1.00D+05 HZ SUM COMPONENT 1.000D20 1.50 DB PHASE (continued on next page) Figure 8.842D02 120.000D20 3.253D03 PHS 132.543D03 75.356D08 1.40 47.544D02 PHS 179.00 CB CBR CJE CJC TOTAL MAG 1.352DOl 165.00D+05 HZ DISTORTION FREQUENCY 1.73 0.00 HD3 MAGNITUDE 1.02 14.26 GM02 7.800DOl 1.267D07 22.678D07 55.00 DB HZ 176.**** DISTORTION 2ND HARMONIC DISTORTION ANALYSIS TEMPERATURE 27.32 CBR 1.49 HD2 MAGNITUDE 1.92 CB CBR MAG 1.63 BJT DISTORTION COMPONENTS NAME GM GPI Ql MAG 3.473D06 5.000D20 0.00 0.71 TOTAL 3.22 GM02 7.00 CJC 5.00D+06 MAG FREQUENCY 1.264DI0 0.26 6.00 CJC 9.992D+Ol PHS 176.714D08 14.000D20 0.25 179.00D+06 PHS 6.00D+06 PHS HZ 176.735D08 0.00 3.4 SPICE2.19 14.377DOl 179.84 165. DISTO summary for the onetransistor amplifier.68 GMU 1.377DOl COMPONENT MAG FREQI = 1.061D04 89.30 CJE 3.27 0.68 GM203 6.524D02 13.989D+Ol GO 2.22 9.74 CJE 4.64 GMU 1.00 IM2D MAGNITUDE 3.43 FREQI = PHASE DB HZ 2ND ORDER FREQ2 = DISTORTION 6.00 14.674DOl PHS 75.26 9.632DOl 2.56 34.00D+05 HZ MAG 6.352DOl HZ MAG 6.75 120.512D07 89.61 PHASE 2ND ORDER INTERMODULATION DIFFERENCE FREQ2 = 9.468Dll 21.70 CB CBR MAG 1.00 CJC 4.56 TOTAL 3.31 0.604DOl PHS 166.000D20 0. 674DOl PHASE 164.00 IM2S MAGNITUDE GO 2.989D+Ol PHS 176.00 CJE 8.49 15.53 FREQI 3.00D+06 HZ MAG 6.000D20 1.000D20 PHS 0. 247 .000 FREQI = DEG C 1.000D20 1.989D+Ol BJT DISTORTION COMPONENTS NAME GM GPI GO GMU GM02 Ql MAG 1.261D02 1.63 COMPONENTS GPI 2.209DI0 13.000D20 0.789D02 1.61 GM02 5.00D+06 HZ MAG = 0.88 CB MAG 1.26 BJT DISTORTION NAME Ql GM MAG 3.019D03 62.26 3RD HARMONIC DISTORTION DISTORTION FREQUENCY 1.69 DB TOTAL 1.26 DISTORTION FREQUENCY 2.992D+Ol INTERMODULATION 9.90D+06 PHS 176.989D+Ol BJT DISTORTION COMPONENTS NAME GM GPI Ql MAG 1.00 0.
such as Vbe: (8.674E01 (continued) H03 1. the emission coefficients NF and NR are set equal to 1.39 PHS 0.9890+01 176.78 66. and an incremental component.24 0.10 and 3.842E02 1.ICE) (1  :1~) )(1  IBC = Is (ev8dVth IB .and highlevel injection have been neglected in order to simplify the derivation of higherorder terms and focus the results on the main nonlinear distortion sources.973D10 1.616D03 3.883D02 PHASE 157.95 157.00 0.00 PHS 162.000 DEG C DIM3 4. For completeness the equations of Ic and IB used in SPICE2 for computing distortion are included here: = Ic (lcc .26 GM02 GMU GM GPI GO MAG 5. 3.377E01 14. IBC.eV8c1vth :1~) %R (eV8c1Vth  1) (8.9920+01 PHS 176.25 17. 3.867D07 1.01 26.01 79. such as VBE.685D10 14.12.388D07 4.68 23.000D20 1.9) = IBE + IBC where Icc.000+05 HZ DISTORTION FREQUENCY 1.000+06 PHS HZ MAG 6.86 8.844D01 6.352E01 DIM2 3.000D20 2. are made up of a DC component.100+06 MAG 6.883E02 Figure 8.248 8 DISTORTION ANALYSIS 3RD ORDER INTERMODULATION DIFFERENCE COMPONENT FREQ2 = 9. ICE.11. The base and collector currents are functions of two variables.440002 TEMPERATURE = SIM2 3. Also.82 DB DB **** 27.164D02 3.515D03 1.4 formulation including the Early effect from Eqs. VBE and VBC.97 7.10) . such as VBE.63 BJT DISTORTION COMPONENTS NAME Q1 HZ FREQ1 = 1.23 DB APPROXIMATE CROSS MODULATION COMPONENTS CMA CMP MAGNITUDE MAGNITUDE AC ANALYSIS FREQ 1. The total currents and voltages.10 through 3. The current components for low.22 GM023 TOTAL GM203 CBR CJE CJC CB MAG 1. because of model simplicity at the time of the implementation.000E+06 HD2 1. and IBE have the same meanings as in Eqs.000D20 1.883D02 7.00 1M3 MAGNITUDE 4.486D08 4.
11) where IB is defined by Eqs. alc V Vbe a BE alc Vbe BC 1 (a lc 2vbe a V BE 2 Ie = + av + 2 2 + 2 av a lc av VbeVbe BE BC 2 + 2vbe a lc a V BC 2 2) (8. the input and output voltages of the transistor equivalent network shown in Figure 8.15) .13) gIJ 2av~E 2 dV~E 1 d2lBE 2dV~c gIJ2 = 1 a2lB 2av~c and so on.. (8.12) where alB aVBE alB avBC I a2lB g7T2 g7T = 1 dlcc {3FdVBE I dIcE {3RdVBC 1 d2lBC (8. Note that a value of 1020 represents zero distortion contribution. 8.14) where iP) and i~2)represent the first. A change of variable (8.. (8. Note that Vbe and Vbe are the independent variables in the above equation.9. The incremental component ib has the following Taylor series expansion: ib = ig7T + igIJ = g7TVbe + g7T2v~e + g7T3vbe + . respectively. of the ic series.3.and secondorder terms. are Vbe and Vee. The values listed under GPI and GMUin the HD2 group represent the contributions to the total distortion due to the secondorder terms g7T2 and gIJ2 in ib.SMALLSIGNAL DISTORTION ANALYSIS 249 Similarly.. respectively.. + gIJVbe 2 3 + gIJ2Vbe + gIJ3Vbe + . however. In the same way distortion contributions can be associated with the Taylor coefficients of the expansion of ic: .
and GM02 in the SPICE2 output represent the secondorder distortions (8.GO. Next consider the distortion due to the charge components.2 and 3.17) respectively. The current through a nonlinear capacitance can be expressed in a power series: (8.and secondorder components of ic: (8. 3.4.L alc aVBC GM. The nonlinear charge formulations are described by Eqs. (8.16) where + alcT aVBE alcT aVBC go alc aVBE alcT aVBC = g f.19) .250 8 DISTORTION ANALYSIS leads to the following expression for the first.18) Here C(V) has two possible formulations.
IBc. namely. Icc. 3. The distortion in the load resistor. Kirchhoff's current law (KCL) is applied at nodes B' and C to yield Vi  RB Vb' +  . Note that the circuit distortion is additive in a vector sense.21) = Cdc2 TR.2. two distortion generators of equal magnitude and opposing phase cancel each other. The approach used in Sec. the printout of the distortion components separates them.3 and Co J ClO [1 . RL.21 and 8. 8. respectively.(Vl + Vj)/ cPl]Ml (8.22) respectively. In the smallsignal equivalent C1T and Cf.3. that is.L include both types of capacitances. and Vl is the junction voltage. ID represents the diffusion current. Start out by writing the transfer function for the smallsignal circuit in Figure 8. The total distortion at the output of the linear circuit is obtained by superposition of all individual contributions. ICE and the different charge terms in Eqs. due to each nonlinearity is evaluated by considering only one distortion source at a time.1 to find the transfer function of the frequencydependent and nonlinear blocks of Figure 8. It is instructive to derive by hand the different distortion components for the onetransistor amplifier in order to understand the meaning of the SPICE2 distortion summary report. IBE.13 and 8. ga2 CJE and CJC represent the distortion contributions due to the junction capacitances. CB and CBR represent the contributions due to CDE and CDC.l8: Cde2 = = a2QDE aV~E a2QDc av~c = TF. however.1 is used in this derivation.L  . 3. defined by Eqs. 8. gm2 (8. Icc or ICE.22.14: Cje2 Cjc2 = = dClE dVBE dClc dVBc (8.23) ia igm  if.L = 0 . 8. defined by Eqs.17.20) for the junction capacitances. A source of small distortion can be associated with each nonlinear term (Chisholm and Nagel 1973) in Eqs.3. 1f. 11T = 0 (8.SMALLSIGNAL DISTORTION ANALYSIS 251 for the diffusion capacitances defined by Eq.
8.5.5 X 104 mho l.27) It is calculated by substituting the following circuit component values: RB = g1T 1000. The input equivalent of gIL' CIL.12). The current i1T.24) The derivation is simplified by splitting the circuit in Figure 8.2 the input signal. Each distortion source contribution derived below has a onetoone correspondence with a distortion component in the SPICE2 summary. is multiplied by the voltage gain. Substitution of the firstorder terms in Eqs. 8.3 into two disconnected subnetworks.252 8 DISTORTION ANALYSIS These are general equations.12. iC1T: (8. 8. Similarly to Si in Eq. shown in Figure 8. In the following derivation secondorder distortion figures are computed first. Consider the nonlinearity due to IBc. in Eqs. ig1T (Eqs. The coefficients of the above series are derived by satisfying the KCL (Eqs. second. which must be satisfied for the terms of different orders in the Taylor series expansion of the currents and voltages. 8. represented by ig1T in Eq. the distortion contribution of which appears in the GPI column in the printout. Vi. gIL is very small and can be neglected.23. B'.23 yields from which the following expression for al can be obtained: (8. and thirdorder terms. has a nonlinear component.23) for first. 8. from the output to the internal base. Vi: (8.72pF = = C1T .25) Because ig1T is nonlinear Vb' can be expressed as a power series of the input signal. 7. avl. consists of two sinusoids of frequencies WI and W2 and amplitudes Vii and Vi2: (8. and a linear component.26) where al represents the transfer function from the input to the internal base. 8.
23 is written for the secondorder terms of the currents and voltages: Note that equation: Vi has no terms of second or higher order. 8. CJ.29) The expressions of HD2. (2) 1 Vag'1T Va HD2g'1T = 2 2Van (8.5 Smallsignal equivalent using Miller's theorem. in resistor RL. 8. + + I ~ Figure 8. and DIM2.8 evaluated for a2( jWI. The contribution at the output. SIM2.6 and 8. can be obtained by multiplying the secondorder component in the vb' series by the gain: (8. the first of Eqs. and different combinations of the two must be used depending on which distortion measure is evaluated. anda2( jWI.L) (8. B Q1 I I I I I I I I I I I I I L RB B' C I I~ . respectively. a2 can be expressed from the above g'1T2RBal(jwI)al (jW2) 1 + g'1TRB+ j(WI + (2)RB(C'1T + avi CJ. jwd.j(2).28) where a2 is a function of WI and W2. due to g'1T'result from the secondorder terms in Eqs. The values of a2 represent the secondorder distortion at the internal base due to g'1T'that is.SMALLSIGNAL DISTORTION ANALYSIS 253 r.075 X 103 = 75 Next. the IBe nonlinearity. a2( jWI.L = 1. .30) . j(2).26 pF avi = gmRL = 0.
0145 A/ V2 2 Vth Substitution in Eq.16: (2) .3 . 106) 1.72 + 75.92 where grr2 1 = . (1.jwl) .0145 . jW2 2 Vo SIM2grr = 2 Von (8. jW2) .9 .075 + j6. for SIM2 evaluate .31) The magnitude and phase of SIM2 are ISIM2grr1 LSIM2grr = = 0.0256 13° . The secondorder intermodu1ation components are calculated similarly.45(0. vogrr.053)2 . The distortion signal at the output. =  0.93 . is calculated for a2(jwl. and Von is the normalized output voltage corresponding to 1 mW power in RL.212) = 1. 102(0.9wl.0126 These values are in excellent agreement with the values computed by SPICE2 in the GPI column ofthe 2ND HARMONIC DISTORTION category. a2(jwl.26)1012 jO.075 + j6. a2(jwl.jO. a2(jwl.28 . ') 1 vogrr( jWl.grr.053)2 1.3 . =  1. (2.9 MHz.106).254 8 DISTORTION ANALYSIS where Vo is the gain referenced to the input for an input signal of amplitude IV. 102 . jW2).28 . (1. 8. and its value is substituted into the definition of SIM2 ofEq. = 0.102(1.26)1012 = a2(jwbjwd where WI + W2 = 1. 1. 5.jO.24(0.30 yields the amplitude and phase of HD2grr: IHD2grr1 = 0. corresponding to 1. jWl) is .1.72 + 75.93 .
and GM02. HD2 as predicted in the frequencyindependent case in Example 5.14. The following equations are used to derive HD2gm.1.7° Note that the 1M2 components agree with the SPICE2 results and the magnitudes are equal to 2. 1.93 .7. 8.45(0.23.93 .SMALLSIGNAL DISTORTION ANALYSIS 255 The difference intermodulation component is derived similarly by substituting 1.72 + 75. where WI  Wz is 27Tx 0. Eq.1 MHz.29.053)(0.93 + jO. The harmonic distortion due to the nonlinearity of Ie is summarized in the SPICE2 output in the columns GM. to find b1 and bz: Va are used in the KCL. the second of Eqs.047) 1. GO.26)1O1Z 1.17. ic is expressed as a power series of Vb': (8.jO. 8. gmRL 1 + jWICfoLRL (8. based on the Taylor series expansion of ie around the operating point/c.075 + j6. IOz(1.3.33) with The first. The magnitude and phase of DIM2 are IDIM2g1T LDIM2g1T 1 = 0.34) gmZRL 1 + j(WI + wz)CfoLRL .0255 = 0. 8. The equivalent distortion sources generating these three contributions to the second harmonic are defined in Eqs.jO. the second harmonic component due to the gm distortion source.and secondorder terms of ic and 8.32) and Va is a power series of Vb': (8.012) in Eq.25(0.28' (0.106).
VAF.17: 1 gm 2V gm2 = = / 2 1.37) where the go term has been neglected and . 8. Eqs. equal by default to 1012 mho. which now represents the distortion at the output due to go: (8.256 8 DISTORTION ANALYSIS where gm2 is computed according to the Taylor series coefficients. The resulting value can be verified replacing the secondorder terms in the KCL (Eq. 8. The second harmonic contribution is found in the GO column of the SPICE2 output and is equal to 1. 10.2.1).23) at the output node and using only the go terms of the ic series: (8.45 A V th h2 represents the contribution of gm to the second harmonic in the output voltage: Vogm (2) _ h 2 2Vb' The distortion at the output is computed according to Eq.29: 1 vogm Vo (2) HD2gm 22Von (8.181 166 0 At first glance the distortion due to go should be zero since no value has been specified for the Early voltage.36 X 108.35) resulting in the following values: IHD2gmi LHD2gm = = 0. This result can be explained by the conductance GMIN added in parallel to each junction (see Sec. 8.36) A new value is obtained for h2.
irl. VJE) (8.23 and 8..39) (8. For the evaluation of the distortion contribution of Cje.FC. . Eqs. 8.42) C1/"2 = Cje2 0 . VJE. C are not computed. VJE)(MJE+l) (8. with VBE > FC.4l) described in Sec.40) The values of C1/"O.12 and 8. which were used in calculating the distortion contributions of g1/"' remain valid. Eq. The value listed under GM02 in Figure 8. 8. that is.crE jel VJE(l = MJE .3.2.2.SMALLSIGNAL DISTORTION ANALYSIS 257 The second harmonic distortion coefficient. 8. 10.40: C 1/"1 . 8.20 and the series  112 (l + x)" = 1 + ax + 2!a(a . Eq.C .\ccording to Eq. 8. expressing currents ig1/" andic1/"' must be changed to (8. HD2go. The distortion components due to QBE and QBC. and SPICE uses the following approximation: CJE [MJE C1/"O= Cje = (l :: FC)MJE 1 + VJE(l ] _ FC) (VBE . but Eqs. and Cj2 in Eq. no TF or TR parameters are specified.. the graphical interpretation of the above approximation is shown in Figure 10. 8. and therefore the nonlinearity in C1/"or C IL can be expressed in the single power series (8. Only the junction capacitanc~s CJE anq CJC are defined for transistor Ql in this example..l)x + .which correspond to CjO. 8. are the first and second derivatives of Cj with respect to VJ.25. The coefficients Cjl and Cj2 in the power series of Cj.26.16.38) based on Eqs.FC. Cjl.38.18 and 8.38.41 lead to the coefficients for Eq. respectively.4 can be verified through the above approach.7. 8. is nonzero'because of the GMIN conductance.38 because the BE junction is forward biased. are evaluated next. 8. and C1/"2. represented by C1/"and CIL in Figure 8. The derivatives of Eq.4 x 108 The distortion contribution due to the secondorder crossterm gmo2 in the ic series. follows: IHD2goi = 1.
due to C"..26: of secondorder = Cjcl Cjc2 BC = = 3CJL1 VIC 2 1 +MIC . The distortion contribution due to CJL will be derived next. as shown in Figure 8.ORB)(l + jW2C"... Eq. (8.oRBl j(WI The amplitude and phase of the secondorder distortion.cJLOVIC .26. 8. The firstorder equation and. 8. are (8. First. 8.40 are used to compute the values of the coefficients aI. IHD2c".IRB (l + jWl C". 8. the capacitance of the reversebiased is following derivatives Cjcl and Cjc2: 1 MIC "2.44) where Vo has been replaced by avlvb" C JLO equal to Cjc. 8...23 yields the following value for in (8. a2..[t av V dv~.oRB)[l + j(WI + w2)C".VBc a2 terms in Eqs. The first of Eqs. calculate the distortion due to CJLi.. therefore. = jWICJLOavIVb' + j(WI + W2)CJLla. HD2c".[t + CJL1av 1 (if + CJL2 1 .23 yield the following expression for a2: + W2)C".23 and 8.1 LHD2c". al are the same as for g".8.V BC junction.IV~' + j(WI + W2 + w3)CJL2a~lv~.5.. 3 dv~. The secondorder terms inserted into the first of Eqs..23 is used with i JL expressed by the following series due to the nonlinearity in the junction capacitance C JL: _ dVb' 2 i JL . the reflection of CJL to the input circuit. and has the CJLl CJL2 Substitution Eq.258 8 DISTORTION ANALYSIS Eqs..46) The secondorder distortion component HD2cJLi has the following magnitude: . 106 = 77° which are in excellent agreement with the SPICE2 values.5 .CJLOa 1 .. and a3 of the Vb' series.43) = 4.
47 after inserting the value of bz from Eq. Because 1 MHz is a relatively low frequency.49 = 15. the distortion due to the nonlinear capacitances CIJ.OVo The assumption that the input circuit is linear represents an approximation made in order to avoid the more complex solution. the derivation is more difficult and prone to errors due to some approximations made in hand calculations.]V~ + j(W] + Wz + W3)CIJ.and secondorder terms in Eqs. 5 and equal 2 X HD2.48) (8. component connected at the output node is obtained from Eqs. which gives the total secondharmonic distortion in the load resistor obtained by adding all the complex numbers representing the individual distortion components. The section 2ND HARMONIC DISTORTION is concluded by the line HD2 MAGNITUDE 1.23 yields the following values of the coefficients b] and bz: (8.4 in the CJC column. which is a power series of Vb': Vo ilJ.674D01 PHASE 164. + j(W] + WZ)CIJ. The thirdorder distortion due to the IBe component of the base current can be computed by replacing the thirdorder terms of Eqs.49) The secondorder distortion due to the CIJ. = b]Vb' + bzv~. The magnitude 0.ZV~ (8. 5.5.167 is very close to the value of HD2 obtained in Sec. 8.49: The contribution due to CIJ. which involves the power series of both vb' and Vo simultaneously. and C is negligible compared to the nonlinear resistive contributions. at the output is the sum of the two coefficients This value is in agreement with the value found in the SPICE listing of Figure 8.47) = jW]CIJ.26 into KCL. 8. Eqs. is evaluated from the output circuit in Figure 8.SMALLSIGNAL DISTORTION ANALYSIS 259 The second part of the distortion due to CIJ. 8. The nonlinearity of ilJ.25 and 8. gm and g7T' Similarly. + b3V~.53 DB. 8. 7T . is assumed to be due only to vo. The thirdorder distortion can be computed following the same steps as above. the total secondorder intermodulation sum and difference components track the values of Chap.23. Because the number of terms involved is higher.4 for the transistor with no frequencydependent elements. 8. Substitution of the first.
jW3) .51) and the thirdorder distortion due to g71"is given by (8.54) The thirdorder distortion contribution due to gm in the output voltage is (8.52) The magnitude of this distortion yields which is in agreement with the SPICE2 value for GPI in the 3RD HARMONIC DISTORTION section.260 8 DISTORTION ANALYSIS Coefficient a3 in the Vb' series. and (8. Eq. for the output section of the transistor model.53) where W3 can be :tWl or :tW2 depending on the distortion component to be derived.23. 8. jW2) CJL) I + g71"RB + j(Wl + W2 + w3)RB(C71" + avl (8.50) where the possible values of W3 are :tWl or :tW2.32 and 8. results: a3( jWl.22 X 102 .26. by the insertion of the thirdorder terms in Eqs. 8. Eq. The thirdorder coefficient in the power series for Va results: (8. The thirdorder distortion component due to gm is computed similarly. 8.55) which translates into the following magnitude for HD3: IHD3gmi = 2. The HD3 contribution is obtained by multiplying a3 by the gain avl: at the output (8.33 into KCL.2g71"2RBal (jwl)a2( jWl. jW2.g71"3RBal (jwl)al (jw2)al (jw3) .
equal to 1.79 X 102 predicted by SPICE.6 represents the 1M3 component. can be noticed in the summary report for thirdorder distortion. 8.58 with 52 equal to 1 if not otherwise specified on the • DrSTO line. Assuming that F( jWl) F( jW2). Two additional distortion components.58) as long as frequencydependent effects are not important. for the thirdorder distortion it is harder to separate in hand calculations the different distortion components contributed by Ie. GM2 03 and GM02 3.1 MHz. Shensha.88 X 102 computed by SPICE relates to HD3 approximately according to Eq. Because of the nonlinearities in the circuit. Cross modulation (Meyer. 8.56) gmo23 aVBEaV~e (8.52 where the gm contribution replac'es that of g1T in This value is larger than the 1. The last distortion category computed by SPICE as part of the summary is that of the APPROXIMATE CROSS MODULATION COMPONENTS.SMALLSIGNAL DISTORTION ANALYSIS 261 HD3gm is evaluated according to Eq.59) where m is the modulation index.2 is modulated in amplitude and the other is not: (8. They represent the distortion due to the following partial derivatives in the Taylor series expansion of ie: VO' a31e gm203 aV~EaVBe a31e (8. 8. and the value 1M3 = 4. and is very close to the value obtained in Chap.6 the following crossmodulation term is generated: (8. 8. the carrier signal. 8.W2 = 21T X 1. amplitude modulation is transferred to the signal WI. and Eschenbach 1972) occurs when one of the two input signals in Eq. The term with this frequency in Eqs.84 X 102.60) . In our example this assumption is generally valid. which represents the spectral component at 2Wl . An important distortion measure is the thirdorder intermodulation. 5 for the circuit with pure resistive nonlinearities and without parasitic base resistance. In the thirdorder term in Eqs. the 1M3 distortion can be related to HD3 as follows: (8. denoted 1M3.57) The total third"order distortion HD3 is the magnitude of the vector sum of all components.
nonlinearities only.66) (8. Vi] = Vi2. the following equality results: CMF = 4.62 and the definition of 1M3. For frequencydependent nonlinear circuits the phase shifts of the different transfer functions must be considered in defining a frequencydomain crossmodulation factor. corresponds to CM at low frequencies (defined by Eq.62) where H3( jw!. is defined as the ratio of the transferred modulation to the original fractional modulation. jW2.58. CM. 8.65) and phase cross The above equality is used in SPICE2 to compute the amplitude modulation terms: CMA CMP = 411M31 COS(<PIM3. or resistive. At high frequencies the amplitude crossmodulation.262 8 DISTORTION ANALYSIS The cross modulation index. This definition is valid for memoryless.67) = 411M31 sin(<pIM3. 8. CMP. amplitude (8.<Po) (8. 8. .64) The values computed by SPICE2 are based on the relation between CMF and the thirdorder intermodulation distortion.61) for equal amplitudes of the two input signals. CMA. From comparison of Eq. cos<p (8.<Po) where <PIM3and <Poare the phase of 1M3 and the phase of the signal at the output.8). 1M3. CMF: (8. 8. respectively.IM3 (8.63) A phase crossmodulation factor. Eq.j(2) is the thirdorder transfer function for the modulated w! component (see Eqs. .61) and is equal to CMA where = CMF.6 and 8. can be defined as the ratio of the transferred phase modulation to the original fractional amplitude modulation: CMP = CMFsin<p (8.
the Fourier analysis does not offer the evaluation of intermodulation distortion in the presence of two input signals and the distortion contribution by type of nonlinearity available with the smallsignal . The computation of the spectral components. The Fourier analysis computes the first 10 spectral components in SPICE2 and a userspecified number of harmonics in SPICE3.1 OneTransistor Amplifier Distortion It is a useful exercise to check the distortion measures computed by SPICE2 using .LARGESIGNAL DISTORTION ANALYSIS 263 8.3. 8.3 LARGESIGNAL DISTORTION ANALYSIS A good approach for estimating the total harmonic distortion is to run a largesignal timedomain analysis and then use the • FOUR analysis introduced in Sec. Vo.4) is av = ~ = 69. The amplitude of the output voltage. however. or smallsignal. assumption. or 0 dBm.4.2mV (8. Also. The most important issue is to scale the amplitude of the sinusoidal input signal properly so that the circuit dissipates the same power in the load resistor as specified in the • nrSTO statement. Largesignal analysis provides more accurate results than AC smallsignal analysis because of the removal of the linearity. corresponding to this specification is (8.68) The gain predicted by the AC analysis for this circuit (see the results in Figure 8. can introduce errors due to the approximation of the waveform based on the values stored for the discrete timepoints used in the transient analysis. nrSTO analysis. 6. nrSTO for the onetransistor amplifier in the above section. The distortion components for the above circuit were computed for 1 m W power in RL.69) ONETRANSISTOR CIRCUIT (Figure 5.9 which leads to an input amplitude of Vi = Vo av = 20.8) Ql 2 1 0 QMOD RL 2 3 lK * vce 3 0 5 .
0162 which are close to but slightly less than the values obtained from the • DISTO analysis.WIDTH OUT=80 .264 8 DISTORTION ANALYSIS VEE 4 0 793. The second.OP *.6. as well as the value of TMAX. This value points to a gain of 72. which must be 1.DIS'IO RL 1 * * . Before checking the results of the Fourier analysis. TRAN line. The measurements show that this value is 1.41 V for proper calibration of the spectral components. . of 793. where the accuracy of the linear approximation declines.4M VI 1 4 SIN 0 20. which inserted into Eq.7.MODEL QMOD NPN + RB=lOO + CJE=lP + CJC=2P .PLOT TRAN V(2) . VBE. an amplitude of 20.154 0.46 V. the maximum time step the program is allowed to use in order to estimate the spectral components over the last period. the amplitude of Vo should be 1.4mV .and thirdorder harmonic distortions are HD2 HD3 = = 0.69 leads to the following value of Vi: Vi = 19.2M lMEG AC 1 * * . 2000. one needs to doublecheck that the value of the gain computed in the AC analysis is accurate.OPT NOPAGE REL'IOL=lE4 ITL5=O LIMPTS=5000 • END The SPICE input is shown above.4 mV are shown in Figure 8.4 m V necessary to bias the circuit.TRAN IN 2U 0 IN . The results of the analysis with Vi = 19. First check the value of the first spectral component at 1 MHz.AC LIN 1 lMEG lMEG * . the circuit has the sinusoidal input signal Vi with a DC offset. 8.41 V.FOURIER lMEG V(2) . The discrepancy in the value of the gain can be explained by the fact that the input voltage is very close to the value of Vth. Note the large number of time steps specified on the . that is.2 mY. the thermal voltage. and a frequency of IMHz.
682 131.715 102.004232 5 5.846 197.935 245.LARGESIGNAL DISTORTION ANALYSIS 265 **** FOURIER ANALYSIS TEMPERATURE = 27.055005 0.013 321.000Dt06 1.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V(2) IX:COMPONENT = 2. The mixer operates as an analog multiplier by generating spectral components of frequencies Wlo :t ws' The mixer is followed by a bandpass filter tuned to the difference frequency. L].484004 0. and Vs is defined as the input signal (5): The two signals add up to an input voltage Vi consisting of two frequencies: (8.062005 0.288002 0.466 PERCENT Figure 8.000D+06 4. and a local signal generated in the receiver.000Dt06 5.016205 4 4. R].000 71.409 4.70) .000Dt06 2.241004 0.976 69.000371 7 7.044 48.000Dt06 5. The radio signal.000Dt06 1.299 146.831003 0. Q]. Wi!. The local oscillator frequency is tunable so that the difference between the two signal frequencies is approximately constant.000029 9 9.976003 0. which rejects the sum and other frequency components.505 21. are fed to a mixer circuit.3. The difference frequency is called the intermediate frequency.947 72.388 127.6 Fourier analysis results.412DtOO 1. and generates the local oscillator signal (LO).831DtOO HARMONIC FREQUENCY FOURIER NORMALIZED NO (HZ) COMPONENT COMPONENT 1 1. ws.000Dt06 2. Two voltage sources are connected at the input: Vw sets the bias at the base of transistor.000Dt06 1.477 103.453 0.001296 6 6.154288 3 3.229 179.000Dt06 1.179001 0.520066 PHASE NORMALIZED (DEG) PHASE (DEG) 175. and the load resistor.000008 TOTAL HARMONIC DISTORTION = 15.000105 8 8. A typical singletransistor mixer circuit is shown in Figure 8. in parallel form a bandpass filter at the output of the mixer.263 306.2 SingleDevice Mixer Analysis Mixer circuits are commonly used in radio receivers.7. Wlo. 8. C].000000 2 2.
72) .. ie.21 and in the above sections a power series was used under the assumption of a small signal. namely v. In Eq.71) where leis the quiescent DC value of the collector current...1: = Ie [1 + . There are two possible series expansions for an exponential.j Vth < < 1. + az Vlo Vs COS(Wlo  ws)t + ..266 8 DISTORTION ANALYSIS Figure 8. 8. Singletransistor The transfer characteristic of the BIT is approximately equal to (8.7 mixer. 5. A differencefrequency component is present in the output current. ] (8.2. according to the smallsignal derivation of Sec.
74 into Eq..71 and use of trigonometric identities.ws)t + .. 8. the IF component.. Assume the following values for the amplitudes and frequencies of the two signals: Vlo = 100 m V. A differencefrequency spectral component (Wlo . ] (8. which is the output of interest in a mixer: (8. the exponential can be expanded in a Fourier series with Bessel function coefficients (Pederson and Mayaram 1990): exp(Vs cos wst/Vth) exp(Vlo cos wlot/ Vth) = = Io(s) fo(l) + 21] (s) cos wst + . Vlo is a large signal and .LARGESIGNAL DISTORTION ANALYSIS 267 where Vi is the total input signal for the mixer circuit... 8. all spectral components except the IF component must be rejected by the output filter. For small signals Eqs. is generated as well as other components not included above. This 1M2 component represents the IF signal.1 MHz.. Vs = 1 m V. + 21] (l) cos wlot + .75) IcIo(s)Io(l) is the dynamic average value of the collector current. If the amplitude of an input sinusoid is not small with respect to Vth.73..74) where s I = = and In (x) are modified Bessel functions of order n. and fs = I MHz. which can be found in mathematical tables. flo = 1. the output collector current is ie = IcIo(s)Io(l) + .73) In the case of a mixer or a multiplier the smallsignal assumption is not always true. 1] (s)1](l) COS(Wlo .ws)t = IDe [ 1 + . 8.72 or that in 8. obtained from smallsignal analysis. 8. After substitution ofthe series ofEq.75 are identical. + 2Ie1] (s)1] (I) COS(Wlo . + 2 Io(s)Io(l) where IDe = + . The IF component in Eq. (8. 8.72 and 8.75 derived through a Fourier series expansion is more general than the expression in Eq.ws)..
is much larger than the radio signal.268 8 DISTORTION ANALYSIS therefore Eq. Rej.78) which in this example is over 50.26. for a singletuned parallel RLC filter is given by (8. Vs' The Q of the parallel RLC filter must be dimensioned so that the rejection. The selection of this value is made difficult by the fact that the amplitude of the local oscillator.77) arid using iCij as given in Eq. at Wla is sufficient to boost the IF component.951Dc Vs th vCOSWijt (8.76 the ratio of the LO component to the IF component is given by iCla iCij = 2 Vth Vs (8.79) where = 1 Wa jLC is the resonant frequency and Q is the quality factor defined in Eq.75 must be used to calculate the IF component. 8. The ratios of Bessel coefficients are found in math tables: h(l) fo(l) h(s) = 095 . Vij . Via. s 1 Vs lo(s) 2 2 Vth The difference component of the collector current becomes iCij = 0.76) The correct design of a mixer requires that the amplitude of the IF output voltage be much larger than any other voltage. . 6. ICla = h(l) 21Dc lo(l) COSwiat (8. The rejection of a given frequency component. 8. Re j (w). From the Fourier series.
6 3/15/83 ********18:44:38***** ONE TRANSISTOR MIXER CIRCUIT **** INPUT LISTING TEMPERATURE = 27. two separate runs must be performed.LARGESIGNAL DISTORTION ANALYSIS 269 The ratio of interest between the voltage amplitudes of the IF and LO components is Voil _ 2 VthR. The first set of input commands is If Q = Rej = .TRAN . The IF and LO frequency components can be checked by requesting a • FOUR analysis.OPTIONS RELTOL=lE4 ITL5=0 .WIDTH OUT=80 .TRAN .END Figure 8.8U 600U 45N *. In order to have SPICE2 compute the amplitudes of both the IF and LO components.83UH Mom NPN * * * SUPPLY. leading to an IF voltage component 8.lM V(3) .PLOT TRAN V(3) *******12/13/90 ******** SPICE 2G.244NF 596.TRAN 45N 601.2U 620U 600U 45N .PLOT TRAN V(3) . There is a limit of only nine harmonics printed by SPICE2 including the fundamental.FOURIER 1.MODEL 0 Mom 15K 4.8. * .FOURIER lOOK V(3) *.000 DEG C *********************************************************************** Q1 3 2 R1 3 4 C1 3 4 L1 3 4 .( e] Volo Vs ) (8.7.80)  Wlo 40 for the tuned circuit of Figure 8.lMEG AC 1 .78 100MV 1.FOUR lOOK V(3) .49 times larger than the amplitude of the local oscillator at the output Volo' The SPICE circuit description and the resulting DC operating point are shown in Figure 8.2U 620U 600U 45N .8 SPICE2 input and DC bias point for mixer circuit. the rejection of the LO component is 440. SIGNAL AND LOCAL OSCILLATOR VCC 4 0 10 VS 2 1 0 SIN 0 1MV 1MEG VLO 1 0 0 SIN 0.
251D05 1.000 4.OOE+OO O.000 1.25D02 WATTS TEMPERATURE = TOTAL POWER DISSIPATION **** **** OPERATING POINT INFORMATION 27.25E05 1.220 10.8 .70E+17 (continued) Figure 8.OOE+OO O.OOE+OO 100.0000 = 27.000 SMALL SIGNAL BIAS SOLUTION VOLTAGE 0.000 7.OOE+OO O.00D16 100.000 DEG C BIPOLAR JUNCTION TRANSISTORS Q1 MODEL IE IC VEE VEC VCE BETADC 8M RPI RX RO CPI CMU CBX CCS BETAAC FT MODl 1.000 1.25E03 0.000 DEG C VOLTAGE NAME VCC VLO SOURCE CURRENTS CURRENT 1.000 1.000 100.780 9.07E+03 O.00E+12 O.000 DEG C **** NODE 2) TEMPERATURE NODE 4) VOLTAGE 10.84E02 2.7800 NODE 3) VOLTAGE 10.0000 TEMPERATURE = 27.OOE+OO 1.270 8 DISTORTION ANALYSIS **** TYPE IS BF NF BR NR BIT MODEL PARAMETERS MODl NPN 1.251D03 1.
879 190. for the last two periods (Tij = lO.000Dt05 3.000 95.819D03 DISTORTION 1.000169 0.280 132.211 157.10 Fourier coefficients of the IF component.509D03 5.106690 PHASE (DEG) 89.290 75. ~s Figure 8.000903 0. which request SPICE2 to plot the waveform of V ( 3).us) after 60 cycles have been computed to assure that the circuit has reached steady state.000Dt05 2.000170 0.000256 0.059D03 1.000292 0. FOUR statement requests the harmonics of the 100kHz spectral component.000Dt05 7.950 5. the collector voltage.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V(3) 1.161 67.000090 0.062 109.330 42. The IF waveforms modulated by the LO signal TEMPERATURE = **** FOURIER ANALYSIS 27.000Dt05 4.LARGESIGNAL DISTORTION ANALYSIS 271 15 > 8 :> 10 605 Time.000Dt05 6.000Dt05 9.000Dt05 6.9 IF component waveform.027 61.000000 0.888 19. .077 28.236 TOTAL HARMONIC = Figure 8.714 PERCENT NORMALIZED PHASE (DEG) 0.240 14. The .929 100.000216 0.624D03 1.000Dt05 8.593D03 1. 000Dt01 DC COMPONENT = FOURIER NORMALIZED HARMONIC FREQUENCY COMPONENT (HZ) COMPONENT NO 1 2 3 4 5 6 7 8 9 1.348 62.347D03 1.054D03 1.298 152.000Dt05 5.225DtOO 5.607D04 1.000242 0.
25 .909U 609. the last two periods of the 1.5 610.Is 610.IMHz LO spectral component: .81) where IDe = Iefo(s)Io(l) = (1.5 Figure 8.025815 .090U 45N . and Io(s) = 1.25 . (1.11. 102 A) 0.lMEG V(3) As in the IF signal plot. ).95 .ingEq.76: Voif = IcifRi = 0.TRAN 45N 610.95IDe v th Ri = Vs = 103 0.0 Time.11 Waveform of the LO signal.9 V (8. 10 = 1. 103 A) . The amplitude of Voif computed by SPICE2 is 6. The • TRAN and • FOUR statements for the next run must be changed in order to observe the 1.FOUR 1.This value can be verified by hand uS. .225 V. from tables of Bessel functions. and fo(l) = 10.9. 103 n 6. the resulting Fourier coefficients for the WZo signal are listed > '* :> 609. the Fourier analysis results are listed in Figure 8. 102 A with Ie given by SPICE2.1MHz LO signal waveform are shown in Figure 8.25. 8.272 8 DISTORTION ANALYSIS are shown in Figure 8.10.
12 = Fourier components of the LO signal. 102 440 • 15 .168D02 5.095D02 3.609D02 1.184 251.800Dt06 9.000 DEG C FOURIER COMPONENTS OF TRANSIENT RESPONSE V (3) DC COMPONENT = 4.342 280.9.100Dt06 2. Quarles.TRAN analyses were run with a maximum internal time step TMAX = 45 ns.763D02 6.12. 8.000000 0.109789 0.533 156.418 266.046057 0.701D02 1.624 165. Note that the above .300Dt06 4.700Dt06 8. Since Vlo is not much larger than Vth. The results of the SPICE3 Fourier analysis are listed in Figure 8. The SPICE3 Fourier analysis verifies the ratio VOitiVolo = 8.892D01 7.Vincentelli 1992).900Dt06 8.510 276.881368 PHASE (DEG) 110.038 151. 0.867 142. it is **** FOURIER ANALYSIS TEMPERATURE = 27. Newton.451 146. is larger than that predicted by Eq.069368 0. The same result can be arrived at by using the • DISTO smallsignal analysis as long as the circuit behaves fairly linearly. It is necessary to provide at least 20 points for one period of a sine wave for the calculation of the Fourier coefficients to be accurate. More details about Fourier and distortion analysis in SPICE3 can be found in the latest user's guide (Johnson.23ID02 4.13. The value computed by SPICE2 for Volo.058822 0. and Sangiovanni.456 169.400Dt06 5.344D01 9.041623 23.80: 1.5 predicted above.056 TOTAL HARMONIC DISTORTION Figure 8.500Dt06 6.81 V (8.151106 0. SPICE3 allows a user to define the number of Fourier components computed.085574 0.171 PERCENT NORMALIZED PHASE (DEG) 0. Better accuracy can be obtained from a program that can compute more than nine harmonics. 103 V = 0.000 111.885 0.89 V. in this example both the IF and the LO magnitudes result from a single analysis as the fundamental and the eleventh harmonic. 1.LARGESIGNAL DISTORTION ANALYSIS 273 in Figure 8.25 .051932 0. Pederson.337 257.923 262.752 253. The amplitude of the IF component can vary by 100% depending on which time interval of the IF signal's period the computation is performed. which represents 1I20th of the highestfrequency component of interest in the signal.600Dt06 7.618D02 4.82) The approach of finding the highfrequency component of a modulated signal from a Fourier analysis with this component as fundamental is very inaccurate.298 140.099DtOO HARMONIC FREQUENCY FOURIER NORMALIZED NO (HZ) COMPONENT COMPONENT 1 2 3 4 5 6 7 8 9 1. .200Dt06 3.
AC and.000356766 0. Gridsize: 200. DISTO analysis.103 mW = 175 mW (8.103 )2 15.00663444 0.425 180. instructive to verify the results of the.274 8 DISTORTION ANALYSIS 1> spice3d2 Spice 1 > source 1xtor_mixer.000171327 0.176 18.000165179 0.4 161.00115581 0.311 84. Harmonics: 12.0534 190. Phase 0 100000 200000 300000 400000 500000 600000 700000 800000 900000 1et06 1.163 10.4065 71.117759 Spice 5 > quit Spice3d2 done Figure 8.000225968 0.742 158.7802 %. Mag  Norm.00106594 0.06029 100.131 0 1 2 3 4 5 6 7 8 9 10 11 0 1 0. .00095327 0.84.000185701 0.17 71.13 Fourier components computed by SPICE3 for the mixer circuit.00106634 0. THO: 11. First.00140642 0.224 0.4315 90. the reference power is calculated for an input amplitude Vlo = 100 m V Pre! = :i~Rl = "2 1 1( 4.00102807 0.993 11. The IF component is the DIM2 secondorder difference intermodulation component.1et06 9.8.0016788 0.00026973 0.99887 6. The SPICE2 input and the results of the.735 68.0181946 0. DISTO analyses are listed in Figure 8.14.6825 174.4975 168. It is important to provide the correct information in the • DISTO statement.ckt Circuit: one transistor mixer circuit Spice 2 > run Spice 3 > set nfreqs=12 Spice 4 > fourier lOOk v(3) Fourier analysis for v(3) : No.16 79.296 9.1382 Norm.491 78.84 X 102 mho as computed by SPICE in Figure 8.83) where with 8m = 4. Interpolation Degree: 1 Harmonic Frequency  Magnitude Phase 0 89.732933 0 0 101.0029233 0.00222051 0.6968 99.00015316 0.
676E+03 Smallsignal FREQ 1. 609E02 2. L1 34 '596.837E+00 3.78 100MV 1.MODEL Mom NPN * * * SUPPLY.000E+05 9.268E01 1.647E03 '5'.000E+05 5.026E+04 2.041E+00 1.000E+05 8.618E+00 4.100E+06 HD3 5.802E+00 4.551E+00 1.733E+00 3. 281E+03 1.502E+02.386E+00 .149E+00 3.000E+05.663E+00 TEMPERATURE SIM2 3.895E+01 8.103E+02 1.000E+05 7.83UH .000E+05 8.000E+05 4.249E+03 Figure 8.317E+01 4.000 DEG C AC ANALYSIS DIM2 4.14 distortion analysis results for mixer.891E01 1.312E+00 2.019E+01 2.707E+01 6. 507E+02 3. 691E+03 2. 6.906E+02 3. 841E+01 1.*******12/13/90 ******** SPICE 2G.000E+06 1.887E01 9.000E+05 6.832E+00 '1.000E+05 2.109E+00 2.PRINT AC VM(3) .914E+04 DIM3 2.000E+05 1. 000E+05 2.361E+03 1.155E+03 2. 27. SIGNAL AND LOCAL OSCILLATOR VCC 4 0 10 *VS 2 1 0 SIN 0 75.093E+02 = .589E+04 3.388E+01 1.100E+06 **** VM(3) 7.lMBG ' .000E+05 3.976E+00 4.700E+02 1.424E05 3.5UV 1MEG VLO 2 5 SIN 0.986E+01 1.778E03 5. 1. TEMPERATURE = 27.779E+00 3.931E+02 3.000E+05 7.?44NF .000E+05 3.209E+01 6.645E+00 2.END ACANALYSIS **** .000E+05 1.447E+00 1.PRINT DISTO DIM2 SIM2 HD2 HD3 DIM3 .000E+05 5.897E+02 2.218E+04 3.000E+06 1.01 :AC LIN 11 'lOOK 1. 303E+02 1.259E+02 1.882E+01 7.399E+03 7.WIDTH OUT=80 .803E+02 6.255E+02 '1.000E+05 9.885E+00 2. HD2 1.675E+03 3. 530E+04 2.040E+01 3. 275 .6 3/15/83 ********18:44~38***** ONE TRANSISTOR MIXER CIRCUIT TEMPERATURE = 27.000 DEG C **** INPUT LISTING *********************************************************************** Q1 3 2 0 MODI R1 3 4 15K C1 3 4 4.000E+05 4.DISTO R1 0 .256E+02 9.484E04 4.753E+02 2.303E+00 2.563E+00 3.1MEG AC 1 * .099E+04 1.000 DEG C FREQ 1.121E+03 4.90909 175M .OPTIONS RELTOL=lE4 ITL5=0 .
103 1.23 and Eqs.276 8 DISTORTION ANALYSIS For the • DISTO specification the radio signal S is defined with respect to the LO signal.86) The value of DIM2 computed by SPICE2 is 3. a2 can be evaluated by solving equations similar to Eqs. SPICE2 computes DIM2 according to (8. 8.34: (8.1 = 8. and Van is the normalized voltage amplitude at the output: (8. the •AC and • DISTO lines replace the • TRAN and.8). . the input signal source.32 through 8.14.73. FOUR lines. the amplitude Vs is . 8. which can be applied with any SPICE program. The ratio Vail /Vala can be obtained from the value of DIM2 computed by SPICE at 1.80. see the INPUT LISTING in Figure 8.84 the ratio of the IF to the LO signal at the output can be derived: a2 ViaVs a] = DIM2a] Via = Van 3. 8.1 MHz it is found in the AC ANALYSIS listing for VM ( 3) equal to 1.87) which is the same as the result obtained from largesignal Fourier analysis and hand calculations.68.66 .909 Wla. The purpose has been to familiarize the user with the methodology of evaluating distortion. The results obtained using • DISTO are correct for this example because the only distortion of the signal is due to the transistor nonlinearities. 8. regardless of whether the program supports smallsignal distortion analysis.5 (8. since only one AC source. and at 1. Vi. From Eqs.68x 103. 0. is commented out.4 SUMMARY This chapter has described in detail how to evaluate distortion in electronic circuits using both smallsignal AC and largesignal Fourier analysis in SPICE.01 Via and the frequency Ws is 0. It is advantageous to use the • DISTO analysis whenever the circuit behaves linearly because the • DISTO and •AC analyses are much faster than the • TRAN and • FOUR analyses. is needed to run the AC analysis.84) where a] is the gain. Via. 8.4 Via 72. and 8.1 MHz.66.85) The gain a] is frequencydependent. The following changes must be made to the SPICE2 input used by the previous analyses (see Figure 8. a2 is the secondorder coefficient in the power series. First. Second.
The summary option of . R. The Fourier components computed by SPICE correspond to the distortion components of the same order. Mayaram. O. Newton. 5 have been presented here. Meyer. 1967. Cross modulation and intermodulation in amplifiers at high frequencies. and A. In Nonlinear Analog Circuits EECS 240 Class Notes. M. R. 1973. of California.. to the number of time points computed by the simulator during the last period of the signal. Berkeley: Dept. 1979. of Electrical Engineering and Computer Science. G. J. T. S. Narayanan. Eschenbach. SangiovanniVincentelli.O.. FOUR analysis for circuits with two nearly linear input signals. R. Quarles. B. Transistor distortion analysis using Volterra series representation. 1972. In the second part of the chapter largesignal timedomain analysis and • FOUR analysis were applied to evaluate the same distortion measures derived with smallsignal analysis.. Univ. IEEE Transactions on Circuit Theory (November). DISTO analysis over the. Boston: Kluwer Academic. DISTO was exercised in SPICE2 and the meanings of all the results were explained. Distortion analysis of solidstate circuits. W. Univ. SPICE3 Version 3f User's Manual. of California.. and L. Pederson. Integrated Circuits for Communication. Efficient computer simulation of distortion in Electronic circuits. G. This example also pointed to the advantages of the smallsignal. Berkeley: Dept. IEEE Journal of SolidState Circuits SC7 (February). A. Special consideration must be given to the accuracy of the • FOUR analysis. Johnson. The relationship between smallsignal and largesignal analysis results was exemplified for a singletransistor mixer. and R. Frequencydependent elements were included in the general derivation of the spectral component calculation. that is. D. and K. 1992 (April). of Electrical Engineering and Computer Science. Shensa. D. Commonly used distortion measures were related to the results obtained from SPICE2 for a singletransistor amplifier. Bell System Technical Journal (MayJune). Nagel.REFERENCES 277 All the capabilities of the smallsignal • DISTO analysis of SPICE2 introduced in Chap. H. Meyer. REFERENCES Chisholm. 1990. . S. Pederson.
The timedomain solution. The solution process implemented in SPICE for the timedomain solution is shown in Figure 9. respectively. uses numerical integration to transform the set of ODEs into a set of nonlinear equations.1.1. The solution starts with an initial guess of the operating point. These techniques are described in Sec. 9. see Chaps. ODE.3. which is followed by iterations for solving the DC nonlinear equations.2 and 9.4. 4 and 6. This is the time zero solution. 278 . Generally the program first solves for a stable DC operating point. The iterative process is repeated for every time point at which the circuit equations are solved in transient analysis. respectively. The solution the iterative process converges to represents either the smallsignal bias solution (SSBS) or the initial transient solution (ITS). The most general equations have been shown to be ordinary differential equations. The algorithms used in SPICE for the DC solutions of linear and nonlinear circuits are presented in Secs. which is represented as the outer loop in Figure 9. 9.1. with nonlinear BCEs.Nine SPICE ALGORITHMS AND OPTIONS . 2 and 3. The iterative process is represented by the inner loop in Figure 9.1 OVERVIEW OF ALGORITHMS A number of algorithms have proven well suited for the solution of the equations of electrical circuits and are implemented not only in SPICE simulators but in most circuit simulators in existence today. The various types of BCEs for electrical elements were described in Chaps. 9. which must be solved in the time domain. The timedomain analysis is replaced by a sequence of quasistatic solutions.
The solution approach implemented in these simulators is also referred to as direct methods. A circuit simulator is defined by the following sequence of specific algorithms. . An important characteristic of SPICE is the analysis options. and their derivatives. The choice of algorithms and tolerances is based on a large set of examples. are known as thirdgeneration circuit simulators. such as SPICE2. such as those by McCalla and Pederson (1971) and Hachtel and SangiovanniVincentelli (1981). and finally Gaussian elimination and sparse matrix techniques that solve the linear equations. SPICE should not be treated as a black box that always provides the right answer to no matter what circuit. SPICE3. linearization of these through a modified NewtonRaphson iterative algorithm. an implicit numerical integration method that transforms the nonlinear differential equations into nonlinear algebraic equations. These algorithms are described in detail by McCalla (1988) and Nagel (1975) and in overview papers. which enable the user to select among several numerical methods and analysis tolerances.1 SPICEsolutionalgorithm.OVERVIEW OF ALGORITHMS 279 Initial trial operating point Linearize semiconductor device around trial operating point Discretize differential equations in time Load linear conductances in circuit matrix Define new trial operating point Solve linear equations No Convergence? Yes Increment time No End of time interval? Yes Stop Figure 9. Simulators using these techniques.
A good understanding of this chapter is important for overcoming the analysis failures commonly referred to as convergence problems. Nilsson 1990. OPTl. Certain characteristics of the MNA formulation and Gaussian elimination associated with computer limitations of the representation of real numbers can lead to a loss of accuracy and a wrong solution.2. VB/AS. The matrix formulation for connectivity and nodal equations in SPICE is presented in Sec. These pitfalls are detailed in Sec. OPTIONS OPTl=Namel/vall <OPT2=Name2/val2> . Two important issues are detailed there: the reordering of equations for accuracy and sparsity and the SPICE options available to the user for controlling the linear solution process. to VI. Thus only two nodal equations in two unknowns must be solved.2.. called modified nodal analysis (MNA). its sparsity. was assigned. OPT2. 9.. are implemented in SPICE for the solution of a linear system of simultaneous equations. vall.1 together with the solution algorithm. 9. by inspection. and iteration limits can be found in most versions.2 DC SOLUTION OF LINEAR CIRCUITS This section describes the circuit equation formulation as well as the solution algorithms for linear systems. Namel.1) is derived from the nodal equations written for each node. Each version of SPICE has a few options that differ from the ones in SPICE2. are options recognized by the SPICE program.1 . or a number. but the fundamental options for algorithms. .1 Circuit Equation Formulation: Modified Nodal Equations In Example 1. 9. Paul 1989). the value of the grounded voltage source. The linearequation solution algorithms described here are used for the DC solution of linear circuits and for the the AC solution. is used in SPICE to represent the circuit. the voltage at node 1. val2.1 the DC solution of the bridgeT circuit (Figure 1. An extended version of nodal analysis (Dort 1989...2. . The most important options control the solution algorithms and tolerances and are introduced in this chapter. and its impact on the analysis is also described in this section. the LV factorization.. . In the evaluation of the node voltages. The analysis options introduced throughout this chapter are summarized at the end. The DC equations are formulated with real numbers. 9. 1. tolerances. and the AC equations use complex numbers. The option is followed either by a name. Eqs. An important characteristic of the circuit admittance matrix..2. which always involves linear circuits. This chapter is intended to relate the analysis options accessible to the user with the solution algorithms.. Name2.280 9 SPICE ALGORITHMS AND OPTIONS and the majority of the circuits run well using the default settings. Gaussian elimination and the associated factorization into lower triangular and upper triangular matrices. The general form of the option statement is ..
in series with R4. and its current is unknown. One problem in formulating the conductance matrix. A voltage source connected between two circuit nodes complicates this issue even more and raises the need for a consistent formulation suited for programming. VI +(GI + G2 + G3)V2 G4 . is that a voltage source cannot easily be included in the set of nodal equations: the conductance of an ideal voltage source is infinite.2 Modified bridgeT circuit. 9. The conductance matrix. VI G3 . G. This problem led the developers of SPICE to extend the set of nodal equations to include voltagesource equations represented by currents in the unknown vector and by voltages in the RHS vector. This approach. and I is the righthandside (RHS) current vector.2. 0 R4 + 14 VA 0 R3 VB CD R2 Figure 9. is easily set up by adding all conductances incident into a node to each diagonal term and subtracting the conductances connecting two nodes from the corresponding offdiagonal terms.DC SOLUTION OF LINEAR CIRCUITS 281 and 1. V2 +(G3 G3 . . Representation by matrices and vectors is well suited for programming and therefore is the methodology of choice in SPICE. VA. and Brennan 1975). G. V is the unknown node voltage vector. is therefore an extension of nodal analysis in that the node voltage equations are augmented by current equations for the voltagedefined elements (Nagel and Rohrer 1971. which contains an additional voltage source. modified nodal analysis.T circuit shown in Figure 9.2) where G is the conductance matrix of the circuit. Ruehli.2 are reproduced here: node2: node3: GI .1) Eq. V3 + G4)V3 = 0 = 0 (9. The problem is exemplified by the modified bridge.1 can be expressed as a matrix equation: GV = I (9. Ho.
and therefore the voltage across it is zero and the conductance is infinite.5) where n is the number of circuit nodes excluding ground. including the voltage sources: node 1: node 2: node 3: node 4: VB: VA: In partitioned matrix form the equations become GJ +G4 GJ GI GI + G2 + G3 G3 G4VI" VI V3 +V4 (GI + G4)VI GIVI GIV2 +(GI + G2 + G3)V2 G3V2 G3V3 +G3 V3 /4 G4V4 +II =0 =0 =0 (9. because it is a short in DC.2. The total number of equations. nv is the number of independent voltage sources. Another circuit element that presents the same problem is the inductor. also .4) ~0 :0 :0 0 0 The above MNA equations can be rewritten in abbreviated form: where C and E are the vectors of the current and voltage sources. and nz is the number of inductors. The inductor is also a voltagedefined element in SPICE and is included as a current equation in the MNA formulation. Note that all controlled sources except the voltagecontrolled current source (VCCS).282 9 SPICE ALGORITHMS AND OPTIONS The complete set of equations can now be written for the bridge. which is a transconductance. used to represent a circuit in SPICE is (9. N. respectively.T circuit in Figure 9.3) +G4V4 +/4 =0 = VB = VA 0 G3 G3 G4: 1 0 G4 1 0 0 0 0 0 1 :0 G4 :0 0 1 0 0 :0 I 0 0 1 1 VI V2 V3 V4 II 14 0 0 0 0 VB VA (9. So far the discussion has treated only voltage sources as being difficult to include into a set of nodal equations.
e 3. (O). e 2. The solution can then be found by computing each element of vector x in reverse order (the backsubstitution phase). The Gaussian elimination procedure uses scaling of each equation followed by subtraction from the remaining equations in order to eliminate unknowns one by one until A is reduced to an upper triangular matrix. The superscripts. 31 11 ° e(l) I e(l) 2 e(l) 3 . X2 is eliminated from e~l) by subtracting ei1) multiplied by aWl aW from e~1): (9. This approach is very timeconsuming. eiO). and e~O). [ a(O) I. a(O) 21 a(O) 31 a(O) 12 a(O) 22 a(O) 32 (9.7) the steps leading to the solution are outlined as follows.6) The solution vector.8) Second. For complete details on the MNA matrix representation of different elements consult McCalla's book (1988). The equations are designated by e\O)..DC SOLUTION OF LINEAR CIRCUITS 283 introduce current equations. 9. both in the equation designators and the matrix elements. represent the step of the elimination process. e(O) .e(O) I /0) _ (a(O)/a(O))/O) 2 21 11 I e(O) 3 (a(O)/a(O))e(O) 31 11 I (9. 11 (O). For a 3 X 3 system of linear equations. XI can be eliminated from e(O) and e(O) by subtracting e(O) multiplied by a(O)/a(O) from /0) and subtracting e(O) 2 3 I 21 11 2 I multiplied by a(O)/a(O) from / 3 J. can be computed by inverting matrix A. Eq. First.4. can be expressed as a matrix equation: Ax = b (9. The MNA set of equations that needs to be solved.9) . x. and Gaussian elimination (Forsythe and Moler 1967) is preferred for numerical solutions.
x: (9. This procedure transforms the circuit matrix A into a lower. r 11 a(O) 12 a(O) a(l) 22 13 a(O) a(l) 23 a(2) 33 [ XI ] X2 X3 = r I b(O) b(l) 2 b(2) 3 1 (9. 2 .6 can be rewritten as LUx = b The first step of the method is to factorize A into Land system become (9. backsubstitution leads to the following solution: (9. e(2) .15) Note that inverting Land U is trivial because they are triangular. Equation 9. which for the thirdorder (9.284 9 SPICE ALGORITHMS AND OPTIONS which yields an upper triangular equation system: I' e(2) . and an upper.12) U. which results in a new RHS: (9.13) where U is the result of Gaussian elimination and L stores the scale factors at each elimination step.10) 0 0 0 Third.14) The last step is backsubstitution. 3 . triangular matrix. e(2). The advantage of LU factorization over Gaussian elimination is that the circuit can be solved repeatedly for . U.11) A variant of Gaussian elimination is LV factorization. which computes the elements of the unknown vector. L. The second phase of the solution is the forward substitution.
The zeroelement count in SPICE is taken after reordering. generate zero diagonal elements linked to the current equation (Ho. This additional topological reordering scheme is. up to version F. noise. which can be exploited for reducing data storage and computation. and distortion analyses.4) is that it is diagonally dominant and many offdiagonal terms are zero. could not correct this problem. Vladimirescu 1978). In the conductance matrix of a circuit having a few tens of nodes. 9. A second problem. however. The sparsity is maintained in the currentequation submatrix R (Eq. has 20 zero elements of a total of 36 elements in the matrix.DC SOLUTION OF LINEAR CIRCUITS 285 different excitation vectors. in other words the conductance matrix is sparse. This leads to a cancellation of a diagonal element value during the factorization process. is a cut set of voltagedefined elements. different righthand sides. Earlier versions of SPICE2. not necessary once the numerical reordering known as pivoting is used. The next section explains the need for careful reordering of the equations for maintaining accuracy and sparsity at the same time. The simple explanation of this is that offdiagonal terms are generated by conductances connected between pairs of nodes. and Brennan 1975). In SPICE the row in the MNA matrix corresponding to the current equation of a voltage source is swapped with the node voltage equation corresponding to the positive terminal of the same voltage source (Cohen 1981). also referred to as preordering. Yang. The voltagedefined elements. The sparsity of the matrix can be defined as number of elements equal to zero total number of elements in matrix sparsity =  (9. All SPICE2 version G releases use pivoting in the sparse matrix solution (Boyle 1978. 9. This issue is addressed in the following section on accuracy.6% in this example. 9. An important observation about the conductance matrix G (Eq. A reordering algorithm has been proposed (Hajj. and usually a node is connected to only two or three neighboring nodes.4. only two or three out of a few tens of offdiagonal terms are nonzero.16) The sparsity is 55.4). Ruehli.2 Accuracy and SPICE Options Accuracy problems in the solution of a linear circuit can be classified as either topological or numerical. This problem can be corrected in the setup phase based on a topological reordering. where many diagonal elements are also zero. that is. such as voltage sources and inductors. option ACCT (Sec. which is also topological in nature. The MNA matrix of the bridgeT circuit. Sparsity is a very useful feature. The number obtained from SPICE for the sparsity of this circuit in the accounting summary. and Trick 1981) that finds an equation sequence free of topological problems. This property is useful in certain SPICE analyses. such as sensitivity.5). differs from the above number because SPICE includes the ground node in the computation. raising the total number of elements to 49.2. 9. Eq. . which used only topological reordering. 9.
and reordering to maintain sparsity.  . 1/5 1/5 0 0 0 0 1/5 1/5 0 0 0 0 0 0 0 1 0 1/2 1/2 1 0 1/2 1/2 0 1 1 0 0 0 0 0 0 1 0 0 V] V2 V3 V4 h I 1 Iv 0 0 0 0 3 (9.3 Circuit exemplifying diagonal cancellation. This example shows the need of a reordering scheme based on the matrix entries at each step of the LV decomposition. the circuit matrix becomes 1 1/2 0 0 0 1 0 0 0 0 0 0 0 0 1/5 1/5 0 0 1/5 1/5 0 0 0 0 0 1/2 0 0 1/2 0 1 1 0 '1 1/2 1 Matrix equations 3 and 4 form a diagonal block [ G] G] G] ] G] where G] = during the LV factorization a zero is created on the diagonal at row 4. !.3.17) After preordering. G) R1 CD 50 • L1 1H 0 R2 0 Iv ~ 20 IL t 3V VA Figure 9.286 9 SPICEALGORITHMS AND OPTIONS A circuit that cannot be solved only through preordering The MNA matrix of the circuit is is shown in Figure 9. described below. which swaps row h with node 2 and row Iv with node 4.
As in the previous example. The conductance matrix of the circuit Another accuracy problem. however. real number. of digits. It is assumed that the computer can represent only four digits of floating~point accuracy.5. The nodal equations for this circuit are GI VI .000 a zero is created on the values of infinity for VI computer and cannot be is singular. Another problem is that computers only have finite precision. can be caused by the circuit in Figure due to the fourdigit limitation.DC SOLUTION OF LINEAR CIRCUITS 287 Not all problems associated with the solution of theMNA matrix are topological.19) 1Q 10 kQ Figure 9.gl VI + gz Vz = I + Gz Vz = 0 (9. Figure 9. rounds off element Qzz to (9. [1] The hypothetical computer in this case. can lead to the loss of significance of a matrix term relative to another during the solution of the linear equations. in IEEE floatingpoint format. 12 orders of magnitude.. . up to 15 decimal digits for a doubleprecision. also due to the limited number by the Gaussian elimination process.4 demonstrates this point. This problem is due to the insufficient accuracy of the corrected by reordering. resulting in erroneous and Vz. This case is exemplified 9. Or 64bit.18) a22 = GI + Gz = 1. The equations of the circuit are 1 1] V 0 [ 1 1.0001 [VI]z .4 Circuit exemplifying limited floatingpoint range. The limit of the number of digits in the mantissa of a floatingpoint number. 2) A circuit can have resistors with a range from i mn to 1 Gn. diagonal during Gaussian'elimination. It is easy to imagine that having a switch element (see Chap.S Circuit exemplifying rounding error. The simple circuit (Freret 1976) shown in Figure 9. however. that is.
which grow as a powerlaw function of the gain factors during factorization and can eventually swamp out the diagonal term. yields the following system of equations: After one elimination step the system becomes with the following solution on a computer with fourdigit accuracy: which is obviously incorrect. gl and g2. the offdiagonal elements are transconductances.9 but implemented with bipolar transistors is shown in Figure 9. A ring oscillator similar to that in Figure 6.9999 V2 This type of accuracy loss can also be observed in the case of a series of highgain stages conne.9999 VI = 0. however.288 9 SPICE ALGORITHMS AND OPTIONS Substitution of the values of the conductances. If the rows of the equation are swapped before factorization in order to bring the largest element onto the diagonal. such as a ring oscillator. The exact solution is = 0.cted in a feedback loop. the solution is correct. and the transconductances. as . Replacement of the transistors with a linearized model during each iteration.6. the system of equations becomes with the more realistic solution The accuracy of this solution is still affected by the limited number of digits. GI and G2. for the available number representation.
607 X 102 mho. PIVTOL = 1013. The default for this parameter.20) [Ieql] o + g1T1 V3 The solutions of the node voltages. g1T = 3. V2. or diagonal term. R = 10 kO. or a pivot. and V3. Another numerical problem occurs when the matrix entries at a certain step of the elimination process become very small. A parameter. but they differ if the above system is solved as is. If an element larger than this value is not found in the remainder matrix at any step. 9. should be identical.607 X 104 mho. with the ratio between the largest value in the remainder matrix and the largest value in the initial matrix being of more orders of magnitude than can be represented by the computer. Carry out the Gaussian elimination steps to find the solution for VI. VI.DC SOLUTION OF LINEAR CIRCUITS 289 R R 10 kn 10 kn t I Figure 9. and Ieq = 2. leads to the following system of equations: G [ + g1T2 gm2 0 G + g1T3 gm3 gml o G ][VI]V 2 = Ieq2 Ieq3 (9. described in Sec. and V3 with fourdigit accuracy. was chosen under the assumption that for typical circuits the maximum conductance is 1 mho and that. PIVTOL. is used in SPICE that defines the lowest threshold for accepting an element as a diagonal element. then the matrix is declared singular and SPICE aborts the analysis. Exercise Assume that gm = 3. at least 13 digits of accuracy are used by computers to store the matrix . because the selfconductance of each node. V2.192 X 102 A.3.6 BJT ring oscillator exemplifying rounding error. loses its contribution during the elimination process.
is essential for an accurate solution to a set of equations if the original values can be altered significantly by the factorization process. According to the Markowitz algorithm. very high ratios of conductance values. Reordering based on selecting the largest element for the diagonal. and so on. In SPICE2 the topological aspects are considered in the setup phase when the sparsematrix pointers are defined. the best element to be picked as the next pivot is the one that has the minimum number of offdiagonal entries in the row and column as measured by m = (r .290 9 SPICE ALGORITHMS AND OPTIONS entries. Sometimes it is even necessary to reorder during the iterative process. First. The Markowitz algorithm is used in SPICE to select. The numerical reordering is based on two criteria: partial pivoting for accuracy and the Markowitz algorithm for minimum fillin. if no pivot can be found on the diagonal the rest of the submatrix is searched. but the user must doublecheck the circuit for possible highimpedance nodes. The second constraint mentioned in the previous section is preservation of the sparsity of the matrix. The larger the circuit. An increase of PIVREL forces a better . Pivoting is performed on the diagonal elements. The above examples demonstrate that a topological reordering is not sufficient and that the order of the MNA sparse matrix has to be based on actual values generated by the circuit as well. the more important pivoting becomes. can be chosen. respectively. which defaults to 103. and then the diagonal element with the best Markowitz number is checked as to whether it satisfies the following magnitude test: aii ::::: PIVREL. Therefore SPICE accepts as pivot the element that introduces the fewest fillins as long as it is not PIVREL orders of magnitude smaller than the largest element at that elimination step. A detailed presentation of numerical accuracy issues can also be found in the thesis by Cohen (1981). because of the accumulation of rounding error in the solution process. As part of numerical reordering.21) where rand c are the numbers of nonzero entries of a row and a column. Fillins are the matrix terms that are zero at the beginning of the factorization process and become nonzero during LV decomposition. If this value is nonzero. The selection of a pivot in SPICE proceeds as follows. the one that introduces the fewest jillin terms. The solution obtained afterward can be correct. called pivoting. or a full pivoting strategy. PIVTOL can be reset using the • OPTION statement to accommodate it.1)(c  1) (9. aiMax (9. the largest element is found in the remainder matrix. Reordering is performed at the very first iteration after the actual MNA values have been loaded. among a number of acceptable pivots.22) where aiMax is the maximum entry at the ith elimination step and PIVREL is a SPICE option parameter. which selects the largest element in the remainder of the matrix. which picks the largest element in the column or row. Note that SPICE lists the value of the largest element in the remainder matrix in the *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP number value IS LESS THAN PIVTOL message (see Appendix B for error messages). a partial pivoting strategy.
lA.1.3. until the solutions of two consecutive iterations are the same. In order to modify one or both linear equation option parameters. or in other words. The graphical representation ofthe BCEs for the two elements. PIVREL and PIVTOL.DC SOLUTION OF NONLINEAR CIRCUITS 291 conditioned matrix at the expense of introducing fillin terms. one conductance.3. The timedomain admittance matrix adds the contributions of the charge storage elements. Controlled sources can also be described by nonlinear BCEs that are limited to polynomials in SPICE2 but can be any arbitrary function in SPICE3 and other commercial versions. lD = Is(ev/Vth GV  1) (9. In summary. PIVREL is the other option parameter that a user can modify if SPICE aborts because of singular matrix problems. The criteria for convergence and the options available to the user to control convergence are presented in Sec. The iterative loop marked in Figure 9.2.23b) IG = .1 for the DC solution of nonlinear equations is implemented in SPICE using the NewtonRaphson algorithm. or skip the DC solution and run a transient analysis with the Ule flag on.3.7a. Once an optimal order has been found. it is used throughout the analysis unless at some point a diagonal element is less than PIVTOL. two option parameters control the linear equation solution in SPICE. 9. one adds the following line to the SPICE input file: • OPTIONS PIVTOL=valuel PIVREL=value2 PlVTOL should be reset to a smaller value than the maximum entry listed in the SPICE message as long as the value is nonzero. The modified nodal equations for a circuit with transistors are a set of nonlinear simultaneous equations. This algorithm is described in Sec. G. shown in Figure 9. In this case pivoting on the fly is performed for the remainder of the matrix. If the largest entry is zero. and one current source. 9.3 DC SOLUTION OF NONLINEAR CIRCUITS In Chap. one should carefully check the circuit first. The user is not advised to modify these parameters unless SPICE cannot find a solution because of a singular matrix problem.1 NewtonRaphson Iteration The NewtonRaphson algorithm for the solution of the equations of nonlinear circuits is introduced with the simple circuit consisting of one diode. 9.23a) (9. try increasing PIVREL. 3 semiconductor devices were shown to be described by nonlinear IV characteristics that are exponential or quadratic functions. The iterative solution process continues until the values of the unknown voltages and currents converge. 9. possibly leading to a wellconditioned matrix.
or iteratively. Equation 9. 9.292 9 SPICE ALGORITHMS AND OPTIONS + v ~ Figure 9.23a can be approximated by a Taylor series expansion around a trial solution. 9. VDo: ID = IDo + dV ~I (VD .24.26) The solution of the above equation is VDl.26 is solved repeatedly. the nodal equation for this circuit becomes (G + GDo)V = IA  IDNo (9. is shown in Figure 9. (b) graphical solution. a Norton equivalent with current IDNo and conductance Goo. 9. with new values for GD and IDN at each iteration (i + 1).7 ~ Diode circuit: (a) circuit diagram. or operating point. Equation 9. VDO. The current ID in Eq. which are based on the voltage at the previous iteration . The new circuit and the graphical representation of the linearized BCE of the diode are shown in Figure 9.25 represents the linearized BCE of the diode around a trial operating point.7 b. which must satisfy Kirchhoff's current law.8. which becomes the new trial operating point for the diode.The diode can therefore be represented by a companion model. also known as the tangent method (Ortega and Rheinholdt 1970).25) where only the firstorder term is considered.24) Nonlinear equations of this type are generally solved through an iterative approach. (9. After Eq.25 is substituted into Eq.VDO) = IDo + GDO(VD  VDO) = IDNo + GDOVD D Voo ' (9. such as Newton's method. the solution VD is located at the intersection of the two functions ID and IG.
J. The generalized linearization approach for a set of.28) where for tpe diode equation g(x) and at the solution X. This process converges to the solution. according to Eq. The graphical representatiqn of the iterative process for this circuit is given in Figure 9.8 Linearized companion model of the diode circuit: (a) circuit diagram. called the Jacobian... The general Newton iteration applied to a nonlinear function g(x) of a single variable is (9. For an arbitrary circuit the set of all nonlinear equations is replaced at each iteration by the following set of linear equations: (9.nonlinear equations g(x) = 0 consists in computing the partial derivatives with respect to the controlling voltages.I ~ ~ Figure9. (i). The iterative process is described by the nodal equation (9. = ID(V) = Is(ev/Vth .9. (b) graphical solution.29) . V. I I I I IDN I v L I I I I .27) which represents for this simple case the Newton iteration. Intersection of the linearized diode'conductance with the load line G define the values VDi at successive iterations.9.DC SOLUTION OF NONLINEAR CIRCUITS 293 r.1) Ig+ 1) = Ig). These values form the conductance contribution of the nonlinear BeEs to the MNA of the circuit.25.
9. the iterative scheme can fail to converge. With the limited range of floatingpoint numbers available on a computer and the unboundedness of solutions provided by the Newton algorithm according to Eq.1.9 Newton iteration for the diode circuit.30.31. the equivalent conductance can vary from 0 in the reverse region to infinity in the forward bias region.6. The conductance matrix A and RHS b for a nonlinear circuit have the following matrix representation: A b = J(x(i») +G +C (9. which is solved using the LU factorization described in Sec.30) = J(x(i») .28. Eqs.31) Equation 9. 9. As exemplified by the diode characteristic in Figure 9. and 9.8. where J(x(i») is the Jacobian computed with xU).31 includes the contributions of the linear elements and independent current . G and C.294 9 SPICEALGORITHMS AND OPTIONS v Figure 9. At each iteration the circuit is described as a linear system. respectively. x(i) . An algorithm that controls the changes in the state variables of the nonlinear elements from iteration to iteration is very important if the simulated circuit is to converge to the correct solution.2. This algorithm is known as a limiting algorithm and determines .g(x(i») (9. The nonlinear IV characteristics of semiconductor devices are exponential or quadratic functions. An important question is whether the above equations converge to a solution and how many iterations it takes. 9. sources in the circuit. the solution at the previous iteration. 9.
28 to the following: (9. NewtonRaphson iteration with current .. v Figure 9. 9.32) The parameter ex(O < ex ::s 1) indicates that only a fraction of the change is accepted at each iteration.10 limiting. VI. limits it by correcting the new value of the Newton iteration (Calahan 1972) from Eq. becomes the new trial operating point for the diode in the current iteration.10. 9. This parameter assumes a different value at each iteration and for each device. based on the last linearization of the diode characteristic. which is smaller than the original solution.32. it is accepted directly I. If VI is smaller than Va.32 defines the NewtonRaphson iterative algorithm.DC SOLUTION OF NONLINEAR CIRCUITS 295 the convergence features of the simulator. Equation 9. is used to derive a new current. Eq. At each iteration the new solution of the junction voltage.. VI. The voltage corresponding to on the nonlinear diode characteristic is V. A limiting algorithm selectively accepts the solution unchanged or. A practical implementation of the above modified NewtonRaphson iteration. I. Va. The choice of ex is implemented through the limiting algorithm. if larger than the previous value. The scheme proposed by Colon is successfully used in SPICE and its derivatives to limit the new junction voltage on diodes and BITs. which is tailored to the different nonlinear characteristics of each semiconductor device. V. is shown in Figure 9. when large changes in the value of the nonlinear function would occur.
with a default value of 1012 mho. The danger in the absence of any limiting is that a trial solution can generate very large values of the exponential function. is formed from a relati ve term and an absolute term. such as BE and BC for BITs and BD and BS for MOSFETs.32 defines the NewtonRaphson iteration. the iterative process is finished when the following two conditions are met: 1.296 9 SPICE ALGORITHMS AND OPTIONS as the new trial operating point because there is no danger of a runaway solution. The values of the nonlinear functions and those of the linear approximations are within a prescribed tolerance. Each tolerance.33) The values of node voltages at two consecutive iterations have to satisfy the following inequality for convergence: !y(i+1) n  y(i)l n :=. Therefore. 9. is defined as (9.3. Equation 9. 2. All the voltages and currents of the unknown vector are within a prescribed tolerance for two consecutive iterations. respectively. Yo in Figure 9.34) RELTOL and VNTOL are SPICE option parameters representing the relative and the absolute voltage tolerance. GMIN. the tolerances used in SPICE to establish convergence are introduced. The NewtonRaphson algorithm has quadratic convergence properties if the initial guess.L V . for voltage or current variables. SPICE2 initializes the semiconductor devices in a starting operating point such that nonzero conductances can be loaded into the MNA circuit matrix at the first iteration. and the process fails to converge. which cannot be corrected in subsequent iterations. it is important in a circuit simulator to provide an initial guess as a set either of node voltages or of terminal voltages for the nonlinear semiconductor devices. to prevent zerovalued conductances from being loaded into the circuit admittance matrix when these junctions are reverse biased. E Vn (9. The voltage tolerance for node n. The default values are set to RELTOL YNTOL = 103 = 1 J. is close to the solution.10. Next.2 Convergence and SPICE Options This section addresses the issues of how and when convergence is achieved. connected in parallel to every pn junction. Circuit simulators start out usually with all unknowns set to zero. An additional protection built into SPICE is a parallel minimum conductance. EVn.
37) (9. This limit is set by the option parameter ITL1. max (iD. ID.38) IVJ+1)  VJ)I :5 EVJ ABSTOL is the absolute current tolerance and defaults to 1012 A in SPICE2 and SPICE3. which consists of quasistatic iterative solutions at a discrete set of time points. The advantage of subsequent analyses is that the unknown vector is initialized with the values from the last point. VY+I). This means that a node with 100 V is accurate to 100 m V and a voltage of 10 /LV is accurate to only 1 /Lv. When SPICE computes DC transfer curves. In the following derivation the nonlinear function will be referred to for simplicity as a current. for example. and IDs for all FETs.35) = RELTOL . ID for a diode. Convergence failure can also occur during a transient analysis. SPICE2 prints the message * ERROR*: NO CONVERGENCE IN DC ANALYSIS and the last node voltages.36) and the iteration process converges when liD . with the SPICE defaults. and 9.38 are not satisfied in ITLl iterations. ID) + ABSTOL (9.IDI :5 Ej (9. 9. the nonlinear functions are the currents. which defaults to 50. as the test for convergence: ID ID The tolerance is defined as El A = = GDVJ (i+1)  IDN  Is (evji)/vth 1) (9. evaluated for the last junction voltage solution vji) and the linear approximation iD.DC SOLUTION OF NONLINEAR CIRCUITS 297 The absolute tolerance defines the minimum value for which a given variable is still accurate. Convergence is based not only on the circuit variables but also on the values of the nonlinear functions that define the BCEs of the nonlinear elements.34. using the present voltage solution. the number of allowed iterations is ITLl only for the first value of the sweeping variable and then is reduced to ITL2. Ie and IB for a BIT. such as FETs. For each time point only ITL4 iterations are allowed before a failure of convergence is decreed. 9. SPICE defines the difference between the nonlinear expression.37. If the inequalities ofEqs. whose operation is controlled by the gate voltage and for which IDs is in most applications 1 /LA and higher. There is a limit to the number of iterations computed by SPICE. ITIA defaults to 10. In the case of semiconductor devices. In transient analysis failure to converge at a time does not result in the abortion of thf' :m::llv~i~hnt r::ln~f'~ ::lrf'ihwtion of thf' timf' ~tf'n ::l~f'xnl::linf'n in Sf'r CJ 4 . which defaults to 100. This default is very accurate for the base current of BITs but may be too restrictive for other devices. voltages are accurate to 1 part in 1000 down to 1 /LV of resolution.
the linearized conductances obtained at the previous time point are used again in the circuit matrix. This method consists in finding the DC solution by ramping all independent voltage and current sources from zero to the actual values. transient analysis is divided into a sequence of quasistatic solutions. it is bypassed. There are. This is equivalent to an . This section outlines the numerical techniques used in SPICE to transform a set of differential equations.OP analysis using a • DC transfer curve approach. This is a very timeconsuming process and may not always be necessary. however. this reduction can negatively affect the convergence test for the overall circuit.D. 9. into a set of algebraic equations. 9. the accuracy of these algorithms is analyzed along with the options available to the user regarding numerical methods and error bounds. furthermore. The check for bypassing a device is based on Eqs. because it involves all the algorithms presented so far in this chapter. A more detailed presentation of convergence problems along with examples and solutions can be found in Chap. 10. The bypass operation results for a majority of circuits in analysis time savings without affecting the end result.4 TIMEDOMAIN SOLUTION The timedomain solution is the most complex analysis in a circuit simulator. During the solution process the linear equivalent of each nonlinear element must be evaluated.298 9 SPICE ALGORITHMS AND OPTIONS When SPICE fails to find a DC solution. similar to ITL2 for DC transfer curves. however. an additional option can be used to achieve convergence. . The specific implementation in SPICE is described here. SPICE3 and PSpice perform source ramping automatically when the regular iterative process fails to converge. as shown graphically in the flowchart of Figure 9. Option parameter ITL6 must be set to the number of iterations to be performed for each stepped value of the source. SPICE2 does not automatically use source ramping if it fails to converge. thesis (1975). This check can limit the devices being bypassed by reducing the tolerances. Nagel's Ph. called source ramping. A detailed presentation on the situations requiring the change of these options is provided in the following chapter.1. As described in the introductory overview of algorithms (Sec. during the iterations performed at anyone time point each nonlinear element is checked for a change in the terminal voltages and the output current from the last time point.1). Source ramping can be viewed as a variation of the general modified NewtonRaphson solution algorithm. The presentation of the numerical methods is simplified for the purpose of providing the SPICE user with insight into the workings of the program. All ITLx options can be reset by the user. In timedomain analysis. 9. In other words. If the controlling variables and resulting function of a device have not changed. a rigorous description of the integration algorithm can be found in the book by Chua and Lin (1975) and L. cases when bypass can cause nonconvergence at a later time point. although this should be rarely necessary. such as the ones representing the BCEs of capacitors and inductors.37 and 9.38. a new linearized model is not computed for this device.
4.0 1. across the capacitor over time. across the resistor and the voltage. • EXAMPLE 9.1 Consider the series RC circuit shown in Figure 9. (b) plots of solutions VR(t) and vc(t).1 Numerical Integration The different numerical integration algorithms and their properties are best introduced with an example. at t = 0 a voltage step of magnitude Vi is applied at the input. vcCt). VR(t). Find the voltage. . (b) 1.5 1.15 Figure 9.11a. Vi (a) 'j 0.5 Time.11 RC circuit: (a) circuit diagram.TIMEDOMAIN SOLUTION 299 9.
41) The solutions VR(t) and vcCt) are VR(t) vcCt) and are presented in Figure 9.40) yielding the following differential equations for VR(t) and vcCt): (9.41 into 9.43) where h is the time step. 9. (9.44) . can be expressed by a Taylor series expansion around Xn+! Xn: = Xn + hXn (9. This is identical to the finitedifference approximation of the derivative of x and represents the forwardEuler (FE) integration formula.42) = In SPICE the solution of the above equation in the interval 0 to TSTOP (see also Sec. Substitution of Eqs. let x be the time function to be solved for and Xn the values at the discrete time points tn: The solution at tn+!.39) KVL applied to the circuit allows the following substitution of Vc: vcCt) = Vi  VR(t) (9.11b. assumed equal for all time points for simplicity.2) is performed at a number of discrete time points. For simplicity.300 9 SPICE ALGORITHMS AND OPTIONS Solution From the BCEs of the resistor and capacitor the following equation is obtained: (9.et/T). 6.43 yields the following recursive solution for Vc at tn+!: (9. where the differential equation is replaced by an algebraic equation. = Viet/T Vi(l . Xn+!.
9.TIMEDOMAIN SOLUTION 301 This is represented graphically in Figure 9. Xn+l = Xn + hXn+l (9.12b. A rather sizeable error can be noticed for VC(tn+l) computed with Eq.12a.44. 9.47 with a Taylor expansion: (9. For the FE and BE methods LTE can be approximated by the first discarded term in the Taylor expansion: h2 Xn+l = Xn + hXn + TXn = Ih. whereas the FE is an explicit method. LTE.45 must be solved simultaneously for x as well as for its derivative.48) . The graphical interpretation of this solution is shown in Figure 9. 9. The LTE of the trapezoidal integration formula can be derived by first substituting Xn+l in Eq.45) This represents the backwardEuler (BE) integration formula.43 and 9. Because Eq. 9. 9.47) The higher accuracy ofthis method is obvious from the graphical solution of Vc (tn + 1) shown in Figure 9. xnl (9.13. The actual algorithm is detailed in the following section. because higherorder terms are neglected in the series. The trapezoidal integration is a secondorder method that can be derived based on the observation that a more accurate solution VC(tn+ 1) can be obtained if in Eqs. An important measure of the accuracy of a numerical integration method is the local truncation error.46) LTE Algorithms for automatic timestep control such as the one used in SPICE are based on checking whether the LTE of each timedependent BCE is within prescribed bounds. A different solution is obtained for Vc if in Eq. The two methods introduced so far are known as firstorder methods. it can be thought that using higherorder terms of the series in the solution of xn+ 1 can lead to smaller LTE.43 xn+ 1 is expressed in terms of the derivative at tn+ 1> Xn+ 1. It can be seen that Vn+l as given by the BE formula is less sensitive to the size ofthe time step h than that given by the FE formula. this formula is known as an implicit method. Based on the above definition of LTE. evaluated at each time point.45 the average of the slopes at tn and tn+ 1 are used as compared to either one or the other: (9.
12 BE solution.13 Trapezoidal solution of vdt) between tn and tn+l. Solutions of vdt) between tn and tn+ 1: (a) FE solution. . (b) Figure 9.302 9 SPICE ALGORITHMS AND OPTIONS (a) (b) Figure 9.
53) Equation 9. 9.5. 9. Solution The BCE of a capacitor. (9. . is applied to the above equation and .48: x (9. Use the result to develop a companion model of the capacitor to be used in nodal equations. from the exact solution given by the first three terms of the Taylor series: (9. can be rewritten for a nodal interpretation: L The trapezoidal results in integration In+l idt = r Cdvc (9.47.51) EXAMPLE 9. = In . Eq.52) formula.2 Apply the trapezoidal integration method to the BCE of a capacitor. Eqs..47 byEq. 9.54) or . 9. 9.49) The resulting LTE of the trapezoidal integration method for xn+ is 1 LTE = 3 Ih12 xn .53 can be rewritten as a nodal equation at tn+ 1: (9.. Eq.TIMEDOMAIN SOLUTION 303 and then subtracting the trapezoidal solution.4 and 2.50) The LTE for n+ 1 is obtained by first substituting xn+ 1 in Eq. 2.47. 2C( + h Vn+l : Vn ) (9.49 and then subtracting the resulting equation in xn+ 1 from Eq.
14. An important property of an integration method is its stability or convergence feature. is greater than 2r.42. In SPICE Eq.56) (9. which converges toward zero but does so in an oscillatory manner if h > 2r.55) (9. Electronic circuits have time constants that can differ by several orders of magnitude.14 Companion model for a capacitor. decreases to zero as does the exact solution VR(t) in Eqs.54 is updated at each time point and the contributions are loaded into the circuit matrix and RHS vector. the equations representing these circuits constitute stiff systems. 9. stability is a global measure of how the solution computed by a given method approaches the exact solution as time proceeds to infinity. A quantitative analysis of the stability of the integration methods introduced so far can be performed for the RC circuit in Figure 9. Eqs. and TR solutions computed after n time steps: (FE) (BE) (TR) Vi(l . BE. h. The companion model of the capacitor for nodal analysis is shown in Figure 9. This behavior of the TR method can be observed in SPICE especially when the solution goes through discontinuities. by contrast. 9.11. 9.42 as time increases. The exact solution for VR(t). in other words. Whereas the LTE is a local measure of accuracy at each time point. It is formed of the parallel combination of the equivalent conductance Geq and the equivalent current source Ieq. these methods . Stability is also a function of the specific circuit. The integration methods used to solve such systems must be stiffly stable.57) + h/r)n (l .304 9 SPICE ALGORITHMS AND OPTIONS + G 'q = 2C h Figure 9. An interesting result is offered by the TR method. The BE solution.h/2r)n (l + h/2r)n The FE solution can be seen to lead to the wrong solution if the stepsize. can be compared with the FE. The companion model for an inductor can be derived similarly.h/rt Vi (1 VI (9.
The time~domain response of. if running. 9. The Gear formula of order 2 has an opposite behavior. 9. EXAMPLE 9. Additional integration formulas have been developed that fall in the general category of polynomial integration methods defined by Xn+l = 2: n i=O aiXni + i=1 2: n bixni (9. The algorithm'is a multistep . SPICE3. The TR method converges to a solution in an oscillatory manner (Eq. PSpice uses only the Gear algorithms.3 Find the time response oftl1eLC circuit shown in Figure.algorithm if i > 1. Use both the TRAP and the GEAR options. The Gear formulas of varying order for xn+ 1 are listed in Appendix D. but explicit methods. Although in the vast majority of cases both the TR and the Gear methods lead to the same solution. the method is implicit. BE and TR. that is. . which leads to a damped response. The implicit methods introduced so far. the method is explicit. and if b1 is nonzero. the latter with a MAXORD of 2.58) If b1is zero. . The Gear integration formulas'order 2 to 6 are implemented in SPICE2. 1~A t 1~1 Figure 9.15 LC circuit. such as the FE method. This difference between the two methods is demonstrated by the following example. and most commercial SPICE versions as an alternative to the default TR method. SPICE3. The TR and BE integration methods are the default in the majority of SPICE versions. The Gear integration (Gear 1967) formulas of order 2 to 6 have proven to have good stability properties. if more than one time point from the past is needed to compute Xn+ 1.15 assuming that at t = 0 the switch is opened.TIMEDOMAIN SOLUTION 305 must provide the correct solution without constraining the time step to the smallest time constant in the circuit. are not.a circuit can differ depending on the integration method used.SPICE2 or . and compare the results. the two have different characteristics. are stiffly stable.57) when the time step is larger than a certain limit. .
The result is shown in the lower trace of Figure 9. Recent versions of PSpice produce the decaying waveform. Note that the current source must not appear in the circuit description.306 9 SPICE ALGORITHMS AND OPTIONS LC CIRCUIT L1 101M C1 1 0 1N * IC=lM * * . probably because the Gear 2 method is used as default. however. which is wrong. its effect. The result of trapezoidal integration is free oscillations with an amplitude of 1 V at the resonant frequency of 106 radls. . as seen in the upper trace of Figure 9.16 to be a decaying oscillation.PWT • END 1U 400U TRAN V(l) The SPICE input is listed above. the Ule keyword must be specified in the • TRAN statement.TRAN .16. or 159 kHz. The inclusion of the • OPTIONS statement by removal of the asterisk at the beginning of the line leads to the solutions computation by the Gear formula. must be taken into account by setting the appropriate initial condition for the inductor current. Trapezoidal 1V 0 1V > 1V 0 1V 50 100 150 200 Time. which is valid for t 2': 0. OPTION METHOD=GEAR MAXORD=2 0 UIC * .16 LC circuit response computed with trapezoidal and Gear 2 algorithms.lls 250 300 350 Figure 9. In order to start the analysis from the initial condition at the time the switch is opened.
The default method is trapezoidal.4. order methods. the LTE of a numerical method diminishes for higher. the equations of electronic circuits must be solved by stiffly stable integration methods for which the t~me step is determined by LTE and not by stability constraints.' Second.be achieved by adding the following .OPTIONS line to {he SPICE circuit description: .' This can . MAXORD limits the order of the integration formula used for the variableorder Gear method and is therefore relevant only when METHOD=GEAR. f. .2 Integration Algorithms iii SPICE. SPICE implements the Gear algorithm as a variableorder. but a user can select the Gear algorithm with the optiOhsMETHOD MAXORD. enabling the variable time step algorithm in SPICE to select a larger time step. the stability deteriorates as the order of the method increases. as shown in the previous section. As mentioned above.references.TIMEDOMAIN SOLUTION 307 The stability of integration methods is presentedinrriore detail in the works by McCalla (1988) and by Nagel (1975). Several conclusions can be drawn based on the firstorder analysis presented in this section and the more thorough analysis found in the . 9. secondorder trapezoidal and Gear order 2 to 6. A higherorder method has a smaller LTE.4 Change the SPICE2 default integration method to Gear and limit the order of the integration formula'to 3. ' Solution .OPTIONS METHOD=GEAR MAXORD=3 The variableorder algorithm in SPICE selects at each time point the order that allows for the maximum time step.and for MAXORD a number between 2 and 6 is required. most SPICE programs support two integration algorithms. EXAMPLE 9. by contrast. Accuracy. However. choices and The for METHOD are TRAP or GEAR. and Options This section describes the implementation in SPICE of the integration algorithms introduced in the previous section and the options available to the user to improve the accuracy of a solution. caution must be exercjsed with higher orders because inaccuracy is introduced in the computation of the LTE and of the resulting time step. multistep method. First.
SPICE defines also a charge or flux error: . the next time step.GTOL)/hn The default value for CHGTOL is 1014 C. The highorder derivatives are approximated in SPICE 3x (9. This algorithm is common to most SPICE programs. Ixnl. 9. is given by the following inequality: 6E Iddt3n I which results from the definition of the LTE of the trapezoidal method for Xn+l. (9. max(lxn+ll.59) Xn+ 1 in the above equation represents the current of capacitors or the voltage across inductors. Eq. This error is similar to the one defined for nonlinear equations (Eqs.62) (9. The exact SPICE implementation of the truncation errors is Ex Eqa.64) x/ . An upper bound is calculated for the truncation error at each time point based on the computation of charges or currents of capacitors and fluxes or voltages of inductors. is introduced for the absolute charge or flux error. CH. Ixnl) + ABSTOL (9.63) Ex = max(lxn+ll. = RELTOL. Based on the upper bound E for the LTE at each time point. hn+1. in the above inequality. the LTE at each time point is taken as the maximum of the two errors: (9. d3 dt3. It is important to get an accurate estimate of the third derivative of the charge. .51.61) A new SPICE option.33 and 9.60) . 9.36) and consists of a relative and an absolute error: (9.308 9 SPICE ALGORITHMS AND OPTIONS The truncationerrorbased timestep control algorithm is described next for trapezoidal integration. CHGTOL. RELTOL.
Eg. With the new factor the predicted time step becomes TRTOL.E (9.67.50.67) A value for the maximum time step given by Eg. 9. .€a 3 The default value of 7 for TRTOL has proven to provide a good compromise between accuracy and speed for a large number of circuits. Comparisons between the exact LTE for the circuit in Figure 9. 9.TIMEDOMAIN SOLUTION 309 by divided differences using the following definition: (9. becomes (9.65) which sets the relation between the kth derivative. and the divided difference of order k.68 for all capaciWrs and inductors in the circuit. TRTOL. the time step computation in SPICE. 9.or fluxdefined element in the circuit.DDkl(tn) hn+li (9. and the one approximated by divided differences have shown that the divided difference overestimates the LTE several times (Nagel 1975). DDk. The automatic timestep control algorithm in SPICE selects hn+ 1 based on the minimum value resulted from evaluating Eg.68) ) max (DD 12. This observation has led to the conclusion that a larger time step can be used than the one defined by Eg. dkx/ dtk. 9. . Eg.64. which scales down the divided difference and therefore the LTE.67 is computed for every linear or nonlinear charge.66) L i=1 DD1 is the numerical approximation of the derivative of x between tn and tn+ I: With these formulas for divided differences. 9. An option parameter has been introduced in SPICE.11. The SPICE timeselection algorithm is outlined below. The recursive formula for divided differences is DD k = DDkl(tn+[) k .
310 9 SPICE ALGORITHMS AND OPTIONS tn+! = tn + hn solve at tn+ 1 if iter J1um < ITIA compute hn+l = f( LTE) if (hn+l < 0. After removing the time dependency at tn+ 1 using transformations of the type given by Eq. TMAX) proceed with tn+2 else reject tn+l hn = hn/8 reduce integration order to I (BE) if (hn > h min) then recompute at new tn+! else TIME STEP TOO SMALL. where ITL4 is an option parameter defaulting to 10.abort Assume that the solution at tn has been accepted and hn has been selected as the new time step. the time step can only increase up to the lesser . 9. 6). hn) then reject tn+l hn = hn+! recompute at new tn+! else accept tn+l hn+l = min(hn+I. which is approximately eight orders of magnitude smaller than the print step. if larger than hn. a new tn+! is defined. the set of nonlinear equations is solved as described in Sec. l new tn+ 1 = tn + 8 hn and the solution is repeated. The solution at the newly defined tn+ 1 is performed with the firstorder BE method.3. TSTEP (see Chap. If the new hn is not larger than hmin. hn.9. the program checks whether the nonlinear solution has converged in less than ITIA iterations. The value of hn+l is accepted if it is at least 0.9hn which implies that the LTE is within bounds. If this value for the time step is larger than the minimum acceptable time step. The method is changed back to the secondorder TR only if the new tn+ 1 is accepted. a new value is defined for hn that is of the previous value. hn+l is computed based on the prescribed LTE. 9.2. If a solution could not be obtained in ITIA iterations. Also. hmin.53. hn+l is allowed only to double at each time point. If the solution at tn+l is obtained in less than ITL4 iterations. First. Eg. SPICE aborts the analysis and issues the message *ERROR*: INTERNAL TIMESTEP TOO SMALL IN TRANSIENT ANALYSIS followed by the value of tn and hn.51. 9.
which in tum is a function of the divided difference approximation of the derivative of a voltage or current waveform. Bypassing the reevaluation of certain devices can result in 20% savings in analysis time. In SPICE2 and PSpice the only way to reduce bypassing is to tighten the relative error. The method applied at the first time point following a breakpoint is known as a startup method. This must be done carefully since it can have the adverse effect of nonconvergence depending on the nonlinear equations. TSTEP or TMAX. If they have not changed more than the tolerance errors EV and Ej (Eqs. that are treated differently. which is a time point where an abrupt change in the waveform is anticipated based on the shape of independent source signals. based on the NewtonRaphson iteration count used at each time point. 9. A third implementation detail is the bypass option. is used to solve for the time point immediately following the breakpoint. if LVLTIM = 1.38).TIMEDOMAIN SOLUTION 311 of2. the computation of the linear equivalent is bypassed and the conductance values from the last time point are used. The LTE of the firstorder method is used at the new time point to minimize the error of the approximation. Large inaccuracies are avoided by introducing the concept of a breakpoint. called breakpoints. The timestep selection algorithm is defined by the LVLTIM option. In SPICE2 and other commercial SPICE programs there is an alternate timestep controlling mechanism. which defines in tum the new tn+l.37 and 9. The approximation of the truncation error is therefore based on an often untrue assumption that x(t) is continuously differentiable to order k in the time interval of interest. SPICE3 provides an option at compile time that prohibits bypass. In the first iteration of a new time point SPICE employs a linear prediction step for the voltages and charges of nonlinear branches. If hn+1 evaluated according to Eq. A second accuracyenhancing technique is the prediction of the circuitvariable values for a new time point. such as Ie. There are a few additional details in the integration implementation that a knowledgeable user should be aware of. but it also can cause convergence problems for slowly moving variables that are within the prescribed tolerances compared to the last time point but may differ more than the error tolerance if compared to k time points previously. which represents the LTEbased algorithm. are compared to the corresponding values at the previous time point.9hn. The iteration timestep control proves more . The default value is 2. the solution at tn+ 1 is rejected and the smaller value obtained for the time step is assigned to hn. such as VBE and VBe of a BIT. there are certain time points. and the resulting nonlinear function. Breakpoints are important for an accurate solution because they prevent the evaluation of the LTE based on time points preceding the discontinuity. At a breakpoint a solution of the circuit differential equations is enforced and a firstorder method. At every new time point after the first iteration the nonlinear branch voltages. the iterationcount timestep algorithm is used.51 is less than 0. RELTOL. the backward Euler method. The timestep control algorithm is based on an estimate of the LTE. First. which doubles the time step for any time point where a solution is obtained in less than ITL3 iterations and reduces the time step by 8 when more than ITL4 iterations are required. 9.
9.29. the information is for the slewrate transient analysis of the complete /LA 741 circuit. the majority of the options introduced in this text can be found in most versions.5 SUMMARY OF OPTIONS The various options available to a user for controlling solution algorithms and tolerances have been introduced throughout this chapter. The list starts with circuit statistics. As mentioned previously. Although use of the Gear method can result in a reduction of computed time points and iterations. whose SPICE input is listed in Figure 7.05 times larger than the value obtained for the current order. an order change is performed. Only for tolerances reduced by 2 to 3 orders of magnitude are the higherorder Gear algorithms being exercised.5. The problem with the fifth. This timestep control algorithm is not available in SPICE3 or PSpice. The order leading to the largest time step within the prescribed LTE is chosen. because of the overhead of computing the coefficients of the method at each time step (Nagel 1975). if there is any. the savings in execution time over the TR method is small.17.1 Analysis Summary Before reviewing the analysis options it is instructive to introduce a SPICE option that provides insight into the analysis: the accounting option. 9.312 9 SPICE ALGORITHMS AND OPTIONS conservative but more foolproof for cases when no charge storage parameters are specified in the model definition of a nonlinear device or when the default error bounds are not suitable. The timestep is also controlled by the LTE in the same manner as described above. a MAXORD of 2 or 3 is sufficient. and k + 1.28 and whose schematic is shown in Figure 7. Although options differ among SPICE versions. An additional feature for the Gear method is that the order of the method can also be modified dynamically.and sixthorder Gear algorithms is that the divided difference introduces a sizable error. the Gear algorithms order 2 to 6 are also implemented in SPICE. If the value of hn+ 1 for higher or lower order method is 1. Nagel (1975) has found that for a set of benchmarks using the default tolerances.1. for a complete list of options available in a specific SPICE version the reader is advised to consult the corresponding user's guide. ACCT. So far the timestep control mechanism has been presented only for the TR method. In general it has been found that most problems where Gear is beneficial. the Gear algorithm used order 2 most of the time. A sample output of the information printed by the ACCT request in SPICE2 is shown in Figure 9. This section summarizes the • OPTIONS parameters by function. The highest order of the Gear method to be used is limited by MAXORD and the number of previous time points available since the last breakpoint. k. NUNODS is the number of nodes defined at the top . The time step following a time point where the method of order k has been used is evaluated for orders k . This summary covers most common SPICE options. such as where there is numerical ringing or convergence problems.
43 O.000 DEG C *********************************************************************** NUNODS 6 NUMTEM 1 NSTOP 82.53 0. READIN SETUP TRCURV DCAN DCDCMP DCSOL ACAN TRANAN OUTPUT LOAD CODGEN CODEXC MACINS OVERHEAD TOTAL JOB TIME Figure 9. which is broken down into the different types of semiconductor devices.6 3/15/83 ******** 17:55:34 ***** UA741 FULLMODEL SLEW RATE **** JOB STATISTICS SUMMARY TEMPERATURE = 27. The second set of data summarizes the analyses requested. 7.000 0.60 0. MAXMEM 400000 IOPS 1059.45 35. the total number of elements. 1231. O. MEMUSE 15484 PERSPA 92.5.783 4. NUMTEM is the number of temperatures. NUMRTP 56.17 0.02 56.00 51.980 COPYKNT 41543. level of the circuit.067 0.283 0.00 3. 84.SUMMARY OF OPTIONS 313 ******* 03/23/92 ******** SPICE 2G. NCNODS 27 ICVFLG 0 NTTBR 370. 3. NCNODS is the number of the actual circuit nodes resulting after expansion of subcircuits. JTRFLG is . O.15 0.000 0. 7. These numbers can be verified from the data in Chap. These numbers are followed by NUMEL. NUMEL 42 JACFLG 0 DIODES 0 INOISE 0 BJTS 26 IDIST 0 JFETS 0 NOGO 0 MFETS 0 IFILL 102. and NUMNOD is the number of nodes after adding the internal nodes generated because of the parasitic series resistances of semiconductor devices. NUMNIT 1231. I CVFLG is the requested points in a DC transfer curve.000 0. NUMNOD 79 JTRFLG 201 NTTAR 472. SPICE statistics for the JLA741slewrate analysis in Sec.68 9. NUMTTP 284.
JACFLG is the number of frequency points in the AC analysis. The fourth set summarizes information about the transient solution and memory use. PIVTOL=value (SPICE2 and SPICE3) sets the smallest MNA matrix entry that can be accepted as a pivot. MAXMEMis the amount of memory available. but it may be of interest to users who want to relate the knowledge about algorithms acquired in this chapter to a specific circuit as well as to learn about the ease or difficulty of convergence and timedomain solution. if the analysis has finished. where the time step hn+ 1 had to be rejected and the analysis restarted at tn. These options should not be modified unless convergence failure is caused by singular matrix problems. and CPYKNT is the number of memory transfers. if the analysis has been aborted because of an error. or FALSE. The default is 1013. Note that the outputs produced by different SPICE versions for this option vary but relate some of the same statistics. the circuit matrix is declared singular.314 9 SPICE ALGORITHMS AND OPTIONS the number of transient print/plot points. and INOISE and IDIST indicate whether a smallsignal noise or distortion analysis has been performed. NTTBR is the total number of nonzero terms before reordering. the default is 1012 mho. None of the above information has any bearing on the actual solution. and PERS PA is the sparsity of the MNA matrix expressed as a percentage. NSTOP is the number of MNA equations. IFILL is the number of fillins created during the LU decomposition process and is equal to NTTARNTTBR. or TRUE. NUMRTP is the number of rejected time points.5. PIVREL=value (SPICE2 and SPICE3) represents the ratio between the smallest acceptable pivot and the maximum entry in the respective column. . and NUMNIT is the total number of iterations performed for the transient analysis. NUMTTP is the number of time points at which the circuit has been solved. a larger value for this option can lead to a betterconditioned matrix at the expense of more fillins. NTTAR is the total number of nonzero terms after reordering. lOPS is the number of floatingpoint multiplications and divisions required for each solution of the linear system. 9.2 Linear Equation Options The following options are related to the linear equation solution: GMIN=value defines the minimum conductance connected in parallel to a pn junction. If no entry is larger than value at any LU decomposition step. The third set of data contains the linear system matrix statistics. The last part of the summary lists the times in seconds for the different analyses and solutions and the number of iterations. which is 0. and I. Last in the analysis category is the variable NOGO. MEMUSE is the memory used by the present circuit. The default is 103. Only increasing GMIN can lead in some cases to better convergence.
4 Numerical Integration The options for the timedomain solution can set integration methods as well as tolerances specific to this analysis. the time step is doubled when the circuit converges in fewer iterations. lTL6=value (SPICE2 and SPICE3) represents both a flag for source ramping in a DC solution and the maximum number of iterations allowed for each stepped value of the supplies. which defaults to 1012 A.5. VNTOL=value is the absolute voltage tolerance defined by Eq. 9. The default is 103. TRAN line.36. lTL2=value sets the number of iterations allowed for any new source value in a . The default is 50. A higher value may lead to a solution. The default is 100. The smallest current that can be monitored is equal to value. and bypass.5.33. in connection with the LVLTIM=l option where it defines the lower iteration limit at a time point. 9. These options are the following: lTL1=value sets the maximum number of iterations used for the DC solution. It represents the smallest observable voltage and defaults to 106 V. lTL4=value sets an upper limit to the number of iterations performed at a time point before it is rejected and the time step reduced by 8. ABSTOL=value represents the absolute current tolerance as defined by Eq. 9. this is also the number of iterations used for a first solution in the timedomain when UlC is present on the . This option is a protection against very long simulations and can be turned off by setting value to zero. the default is 10. it defaults to 5000. A few options control the number of iterations allowed in the nonlinear equation solution. The convergence tolerances are the following: RELTOL=value defines the relative error tolerance within which voltages and device currents are required to converge as set forth by Eqs. lTL3=value is meaningful only in SPICE2. This option can have direct impact on convergence.36. 9. .33 and 9.SUMMARY OF OPTIONS 315 9. DC transfer curve analysis.3 Nonlinear Solution Options The options that control the NewtonRaphson solution can be grouped as convergence tolerances and iteration count limits. timestep control. In PSpice value is also used as the maximum number of iterations at each source value during source ramping. lTL5=value is the total number of iterations allowed in a transient analysis.
is the absolute charge tolerance at any time point according to Eq. LVLTIM=value a (SPICE2) selects whether the timestep is controlled by the local truncation error. see Sec. 4. Note that this option effects the analysis results at temperatures specified in the .47.67. NOPAGE NODE suppresses new pages for different analyses and header printing. global device properties. 9. LTE. The tolerances that can be modified in the transient analysis are the following: TRTOL=value CHGTOL=value is a scale factor for LTE as defined in Eq. 9. the default is NONODE.3. 9. TEMP=value. rather than a command line as in SPICE2 and PSpice. the default is 27°e. and two timestep control mechanisms as follows: METHOD=TRAP /GEAR (SPICE2 and SPICE3) selects the numerical integration formula. as defined by Eq. OPTS . 9. of the method (value = 2) or by the iteration count needed at each time point for convergence (value = 1). SPICE implements variableorder Gear integration formula contained in Appendix D. and which information is output.1. The following option modifies the analysis environment: TNOM=value sets the reference temperature the analysis time. The information and its format saved by SPICE in the output file is controlled by the following options: LIST generates a comprehensive summary of all elements in the circuit with connectivity and values. the default is 2. requests the output of a node table. TRAP. the default is NOLIST. TEMP statement. MAXORD=value (SPICE2 and SPICE3) sets the maximum order of the Gear method when selected by the METHOD option. it defaults to 7.5 Miscellaneous Options A number of options in SPICE control the analysis environment.316 9 SPICE ALGORITHMS AND OPTIONS A user can select from two integration methods. which lists the elements connected at every node. In SPICE3 the analysis temperature is also an option. the default is the secondorder trapezoidal method. causes a complete list of all options parameter settings.5. parameters are printed.62. at which all device parameters are assumed to be measured. several integration formula orders. by default the model NOMOD suppresses the listing of device model parameters. The default value is 2. it defaults to 1014 e.
. DEFAD=value sets the global. L. on the device line (see Chap. Cohen. Englewood Cliffs. or default. Berkeley. By default the SPICE2 output line is 120 characters long. 3) overrides the DEFAS value. W. 1978. 3) overrides the DEFAD value. on the device line (see Chap. Chua. PSpice and specific implementations of SPICE2 allow the user to limit the analysis time through the following options parameter: CPTIME=value sets the maximum CPU time for the analysis. L. of California. New York: McGrawHill. The channel length. Univ. There is an additional command belonging in the options category that controls the line length in the SPICE2 output file: •WIDTH OUT=value where value equals the number of characters per line. M Lin. G. . 1972. Calahan. the SPICE builtin default is 1 meter. value must be larger than the number of data points resulting from the analysis. 3) overrides the DEFW value. Note that this option does not affect the computation of the results but only how many digits are printed. 1975. ComputerAided Analysis of Electronic Circuits: Algorithms and Computational Techniques. 0. the SPICE builtin default is 1 m2. D. on the device line (see Chap. AD.REFERENCES 317 NUMDGT=value selects the number of digits to be for results. PLOT. W. 3) overrides the DEFL value. device channel width. source area. or default. or default. A. AD. AS. REFERENCES Boyle. L. on the device line (see Chap. DEFL=value sets the global. the SPICE builtin default is 1m2• The drain area. it defaults to 201. and P. drain area. ComputerAided Network Design. Global geometric dimensions can be defined for MOSFETs as option parameters: DEFW=value sets the global. AS. LIMPTS=value sets the number of points to be saved for a . 1981. More than 4 digits may be meaningless unless RELTOL is reduced. DEFAS=value sets the global. E. The source area. PRINT or a . or default. device channel length. The channel width. the SPICE builtin default is 1 meter. Performance limits of integrated circuit simulation on a dedicated minicomputer system. value is an integer number between printed after the decimal point 0 and 8 and defaults to 4. Personal communication. ERL Memo UCBIERL M81/29 (May). R. NJ: Prentice Hall.
C. 1971. and P. Boston: Kluwer Academic. of Illinois. Stanford. NJ: Prentice Hall."Sparse Matrix Solution with Pivoting in SPICE2. of California. Urbana. 3d ed. Brennan. 1988. ERL Memo ERL M520 (May). C. Analysis of Linear Circuits. 1971. G. W. Computer analysis of nonlinear circuits.. Avoiding zero pivots in the modified nodal approach. L. IEEE Journal of SolidState Circuits SC6 (August): 166182. I.. Minicomputer Calculation of the DC Operating Point of Bipolar Circuits. N. Ortega. Paul. E. 1989. N. W. Ruehli. (May). CA. Univ. 1981. w. Hachtel. of Computer Science..Vincentelli. C. Sangiovanni.. J. Freret. 1975. Numerical integration of stiff ordinary equations. Vladimirescu. 1981.. Stanford Electronics Labs. and R. McCalla. B. Yang. O. SPICE2: A computer program to simulate semiconductor circuits. C. Gear. Nagel. and C. 1976. E.. Moler. Univ. Report 221. New York: Academic Press. Trick. 1975. Fundamentals of ComputerAided Circuit Simulation. A. New York: John Wiley & Sons. 1978. Introduction to Electric Circuits. W. . McCalla. Forsythe. Rheinholdt.. Pederson. 1970. J." EECS 290H project. A. 50151. Reading. Englewood Cliffs. Computer Solution of Linear Algebraic Systems. J. 1967. M. 1989. Rohrer. R. W. Electric Circuits. Iterative Solution of NonLinear Equations in Several Variables. 1967. Ho. and T. L. Technical Report No. A. The modified nodal approach to network analysis. IEEE Transactions on Circuits and Systems CAS28 (April): 271278. Nagel. W.. of California. MA: AddisonWesley. Nilsson. J. Berkeley. Stanford Univ. A survey of thirdgeneration simulation techniques. IEEE Transactions on Circuits and Systems CAS22 (June): 504509. and W. P. 1990. W. P. Hajj. and A. New York: McGrawHill. IEEE Transactions on Circuit Theory CT18 (January). R. Berkeley. R. IEEE Proceedings 69 (October). J. Dept. and D.. Univ. G. excluding radiation (CANCER).318 9 SPICE ALGORITHMS AND OPTIONS Dorf. Elements of computeraided circuit analysis. L.
either its specification or its inoperability. A convergence problem can be categorized as either failure to compute a DC operating point or abortion of the transient analysis because of the reduction of the time step below a certain limit without finding a solution.1 INTRODUCTION Generally. In the majority of the cases when a solution failure occurs it is due to a circuit problem. The two most common messages that SPICE2 prints when it fails to find a solution are *ERROR*: NO CONVERGENCE IN OC ANALYSIS and *ERROR*: INTERNAL TIME STEP TOO SMALL IN TRANSIENT ANALYSIS This chapter describes the most common causes of convergence failure and the appropriate remedies. because of the nonlinearity of the circuit equations and a few imperfections in the analytical device models a solution is not always guaranteed when the circuit and its specification are otherwise correct. the NewtonRaphson iteration. failure to find a solution can occur at the level of the linear equation. SPICE finds a solution to most circuit problems.Ten CONVERGENCE ADVICE 10. or the numerical integration. From the perspective of the previous chapter. However. Rather than present the convergence issues based on the algorithm causing 319 .
oscillators require certain initializations not necessary for amplifiers. An overview of circuitspecific analyses and issues is provided in Sec. and bipolar circuits may need different convergence tolerances than do MOS circuits.5. 10. 10. Section 10. The prescribed remedies include redefinition of analysis options.2.2 contains the most common remedies for SPICE solution failure. Thus. Specific procedures can be followed when SPICE fails to find a DC solution of the circuit.3. . tolerances. Although convergence failure is more common for large circuits. Timedomain analysis can provide an inaccurate solution or fail because of a number of reasons related either to the integration method and associated timestep control or the iterative solution of nonlinear equations.1 COMMON CAUSES OF SOLUTION FAILURE Circuit Description The first thing a user should do after a convergence error occurs is to check the circuit description carefully.320 10 CONVERGENCE ADVICE the problem. Knowledge of the specifics of different types of electronic circuits can assist the user in finding an accurate solution by specifying appropriate analysis modes. the problems presented below can be duplicated only in the specified simulator. 10.2 10. and DC operating point solution with a different analysis. different computers may use different floatingpoint representations and different mathematical libraries of elementary functions.4 describes some of the problems and several approaches that can lead to a solution in these cases. Sometimes the same simulator can succeed or fail to converge depending on the platform. the SPICE input should be compared to the schematic for correct connectivity. A list of every node and the elements connected to it can be obtained by adding the NODE option to the input description: •OPTIONS NODE The user should specifically look for and identify nodes that are floating or undefined in DC. The results presented in this chapter are obtained from SPICE2 and SPICE3 running on SUN workstations and PSpice running on 386/486 PCs. All convergence issues described in this chapter are illustrated by small circuits that can be easily understood by a new user. the problems and their remedies are the same as for the smaller circuits described in this chapter. Additional SPICE information can be helpful for this verification. Note that the convergence problems described are specific to the simulators mentioned in the text. options. and suitable model parameters. Because of differences between SPICE simulators. it has been deemed beneficial to describe the causes for failure from a user's perspective. Section 10. use of builtin convergenceenhancing algorithms. These approaches are presented and exemplified in Sec.
Floatinggate MOS . drain.2. unlike the base of a BJT. or bulk.1 circuit. The gate terminal of a MOSFET. The second message points to the nodes that are floating in DC and cannot be solved. Common error messages related to circuit topology are *ERROR*: *ERROR*: *ERROR*: Vname LESS THAN 2 CONNECTIONS AT NODEnumber NO DC PATH TO GROUND FROM NODEnu~ber INDUCTOR/VOLTAGE SOURCE LOOP FOUND. As described in the previous chapter. source. EXAMPLE 10. which are open circuits in DC. defined in the SPICE deck listed in Figure 10. The following example illustrates an analysis failure due to the improper connection of a MOSFET which goes undetected by SPICE. One such example is the gate terminals of MOSFETs which need to be connected properly for DC biasing. has no DC connection to the other terminals of the device (Grove 1967).1 Find the time response of the circuit shown in Figure 10. inductors are equivalent to zerovalued voltage sources in DC analysis and therefore cannot form a mesh or loop with voltage sources or other inductors. Although SPICE identifies and reports most topology errors. and therefore must be properly biased outside the device. C1 r& =V 1 Figure 10. The third error message records a violation of Kirchhoff's voltage law. CONTAINING The first message identifies any node that has only one terminal of one element connected to it.COMMON CAUSES OF SOLUTION FAILURE 321 SPICE checks every circuit for topological and component value correctness. Most often such nodes are connected to ground through capacitors. some evade the scrutiny.1 to the input signals VA and VB.
WIDTH OUT=80 .END *******01/16/92 ******** SPICE FLOATING GATE OF MOSFET ELEMENT NODE ERROR 2G.000 DEG C **** *********************************************************************** M1 C1 VA VB V1 * 2 4 4 3 2 1 1 3 0 0 0 0 NMOS L=100U W=100U lOP IC=O PULSE 0 5 70U 2N 2N lOU 100U PULSE 0 5 lOU 20U 20U lOU 100U 6 NMOS NMOS VTO=1.TRAN 1U 100U 0 .OPTIONS NODE .6 3/15/83 ********11:48:25***** GATE OF MOSFET MOSFET MODEL ERROR TEMPERATURE = 27.000 DEG C PARAMETERS *********************************************************************** NMOS NMOS 1.MODEL * .3 * .0000 NODE ( 5) VOLTAGE 0.0000 NODE (2) VOLTAGE 0.1.000000D+00)IS *ERROR*: NO CONVERGENCE IN DC ANALYSIS LAST NODE VOLTAGES: NODE ( 1) VOLTAGE 0. .000 1.PRINT TRAN I(V1) I (VA) I(VB) .6 3/15/83********11:48:25***** GATE OF MOSFET INPUT LISTING ERROR TEMPERATURE = 27.322 10 CONVERGENCE ADVICE *******01/16/92 FLOATING ******** SPICE 2G.0000 NODE (3) VOLTAGE 0.2 SPICE2 input and output with node table for circuit in Figure 10. 300 2.6 3/15/83********11:48:25***** **** TABLE TEMPERATURE = 27.0000 ***** JOB ABORTED Figure 10.00D05 LESS THAN PIVTOL TYPE LEVEL VTO KP *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 2(0.000 DEG C *********************************************************************** o VB 1 C1 2 V1 3 VA 4 C1 *******01/16/92 FLOATING **** V1 M1 M1 VB M1 M1 VA ******** SPICE 2G.
is shown in Figure 10. EXAMPLE 10. Alternatively. if a DC solution is needed. and it is up to the user to understand the problem. Unfortunately. the actual value is listed in parentheses in the error message. the information about which terminal of M] is connected at a given node is not provided.3 can be used to measure the collector cutoff current. the following singular matrix message is printed by SPICE2: *ERROR*: MAXIMUM PIVI'OL ENTRY IN THIS COLUMN AT STEP 2 (D. that is. The node table for this circuit. It can be used to defeat the topology checker. which is printed by SPICE when the NODE option is set (see Figure 10. the DC solution should be bypassed by specifying the UIC keyword in the. the capacitor. The initial transient solution. PIVTOL can then be lowered to a value less than the maximum entry and the analysis rerun.6 and 5. proper biasing should be provided to the gate. but care must be exercised.COMMON CAUSES OF SOLUTION FAILURE 323 Solution The SPICE2 output.2. by setting the emitter current supplied by the current . THAN statement. This problem goes undetected by the SPICE topology checker. leaves the gate terminal floating in DC.2 The setup in Figure 10.2. Another element that can cause singular matrix problems is a current source that voluntarily or involuntarily is set to zero. There are several remedies once the cause of this type of failure is understood. The current source in this case is an open circuit. including the input circuit. ICBO. It is left as an exercise for the reader to experiment with the suggested workarounds to find whether they result in the completion of the analysis. a common data sheet parameter. fails with *ERROR*: NO CONVERGENCE IN IX: ANALYSIS A closer look at the output file reveals that the circuit matrix is singular within the SPICE tolerances.3. as described in Examples 4.DDDED) IS LESS THAN The submatrix at the second elimination step is singular because the circuit is open at node 1. which connects the signals VA and VB during the transient response. the DC analysis. as described in Example 10. If only the timedomain response is of interest. If the singular matrix problem occurs but the value of the maximum element at a certain elimination step is nonzero. shows that only C] and M] are connected at node 1.2).
3 Cutoff current measurement circuit. The default is P IVT 0L = 1013• . In the case of correctly defined circuits. .1 but the maximum entry is a finite number. Lowering of PIVTOL allows SPICE to accept smaller values as pivots in the linear equation solution. This problem can be overcome by lowering the value of PIVTOL. The following • OPTIONS line added to the circuit description in Figure lOA. The same message of a singular matrix is printed as in Example 10. see also Sec. 9. source Ie to zero and measuring Ie of the transistor. The cause for this error is that the circuit equations that SPICE solves constitute an underdetermined system and the emitter voltage. 5. Although PSpice finds a solution without flagging a singular matrix. This is equivalent to leaving the emitter of QI open. which is not permitted in SPICE.OPTIONS PIVTOL=lE14 causes SPICE2 to finish the analysis. can be set to any value.2.324 10 CONVERGENCE ADVICE + Figure 10. the problem remains that random numbers are generated during the solution process for VE' Note that for Ie =? 0 SPICE might not find a solution because of the erroneous circuit setup: QI cannot conduct the driving current.77 X 1014. VE = VI. lowering PIVTOL below the value of the maximum entry can cure the problem when a singular matrix is encountered. Solution The input is listed in Figure lOA' together with the SPICE analysis results for Ie = O.
0000 NODE (3) VOLTAGE 15.8M VJC=800M NC=1. lowering PIVTOL below the smallest matrix entry indicated in the error message enables SPICE to compute the solution.5P RC=696.38 IKR=2.526 + VJE=757.773160D14) IS LESS THAN PIVTOL *ERROR*: NO CONVERGENCE IN DC ANALYSIS LAST NODE VOLTAGES: NODE ( 1) VOLTAGE 0.2 AF=1 KF=O FC=0. 25 + VAR=10 CJE=5.OP .OPT ACCT .OPTION PIVTOL=1. 534F + IRB=100U RB=O RBM=O XTI=3 ISC=100P EG=l.4 SPICE2 input and outputfor circuit in Figure 10. END PIVOT CHANGE ON FLY: N= 7 NXTI= 7 NXTJ= 7 ITERNO= 23 TIME= O.0000 ***** JOB ABORTED Figure 10.3. 5 IS=6.9P RE=741. 8M PTF=O + CJS=O MJS=O VJS=750M XCJC=l XTB=l. 3 VAF=49.MODEL M2N2501 NPN + BF=166.ll ISE=23.294 NF=1 BR=744.000 DEG C MEASUREMENT INPUT LISTING *********************************************************************** Q1 3 0 1 M2N2501 AREA=l .1474 NODE (2) VOLTAGE 15.6 3/15/83********11:41:02***** CIRCUIT TEMPERATURE = 27.42F + IKF=113. The conclusion of this example is that a singular matrix message can be caused by an error in the circuit specification and that if the circuit is correct and no floating nodes are found.5 V+ 2 0 15 VC 2 3 0.OOOOOD+OO *ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 8 (5.4M CJC=3. 9 NR=1. .8M MJC=0.1M NE=1.COMMON CAUSES OF SOLUTION FAILURE 325 *******01/16/92 COLLECTOR **** CUTOFF ******** CURRENT SPICE 2G. 038 MJE=O.188K TR=29.0E14 . 31N XTF=100 ITF=317.WIDTH OUT=80 .7M + TF=610 52P VTF=1.0 IE 0 1 0 * * * *.
similar to the gate node of transistor M1 in Example 10.1. connected in parallel.5 GMIN conductance across pnjunctions for BJT and MOSFET. BJTs. GMIN prevents the occurrence of floating nodes in a transistor circuit. The semiconductor model parameters are printed by default in the output file obtained from SPICE2 and PSpice.2. 10. because numerically it can become an open circuit. Ideal elements and unrealistic component values and semiconductor device model parameters can lead to voltages and currents that combined with transcendental equations generate numbers outside the computer range.326 10 CONVERGENCE ADVICE c GMIN D GMIN B G1 GMIN E S GMIN B Figure 10. which can be set as an option. the component values and model parameters should be doublechecked. and JFETs have a very small conductance. after the topology has been verified. The LIST option can be introduced in the SPICE input to obtain a comprehensive summary of all elements and their values.3 Use SPICE to find the operating point and the timedomain response of the halfwave diode rectifier shown in Figure 10. The schematics for the BJT and the MOSFET including GMIN are shown in Figure 105 Large resistances. The simple example presented below leads to a solution failure or erroneous result depending on which SPICE version is used. an alternate way is to use the • NODESET command to initialize the voltages at these nodes. MOSFETs.2 Component Values In the case of an analysis failure or erroneous results. smaller than l/GMIN. GMIN. A highimpedance node can result in the same failure mode as above. As protection against this problem the internal SPICE models of the pn junctions in diodes. . EXAMPLE 10.6. can be added to highimpedance nodes if they do not disturb the operation.
with an ideal diode according to the SPICE input listed in Figure 10. Some versions of SPICE. this solution is wrong. 10308.1) This number is greater than the largest value. however.COMMON CAUSES OF SOLUTION FAILURE 327 CD D1 + V1N 20V ID ~ VD Figure 10.6 Halfwave dioderectifiercircuit.7.MODEL DMOD D * . such as older PSpice releases.OP . limit the value of the exponent to 80 in the internal computation which combined with automatic source ramping leads to a solution. In the absence of an external resistor the role of the diode parasitic series resistance is to provide current limiting in the halfwave rectifier circuit. that is. that can be represented in double precision. For smaller values of the voltage source VIN SPICE may find a solution as long as ID is in the range of floatingpoint numbers. .WIDTH OUI'=80 • END Figure 10. because the current is limited at The error in this example is due to the lack of a parasitic resistance in the diode model. The simulation fails because the absence of current limiting leads to numerical range error in computing the value of (10.   Solution An uninformed user may try to simulate this circuit with the default diode model parameters.7 SPICE descriptionof halfwavediode rectifier. In reality the DIODE CIRCUIT WITHOUT CURRENT LIMITING VIN 1 0 20 Dl 1 0 DMOD .
Power electronics is the one area where resistances Simple theory.2). C]. such as N for a diode. Fe. The value of C] increases toward infinity as the junction voltage VD approaches the builtin voltage VJ according to Eg. This constraint limits the smallest resistance to 1 mD.3 SPICE o Figure 10.2.3. NF and NR for a BJT (see Chapter 3).. which approximates the junction capacitance. Eg. that is. (10. For an accurate solution it is important to observe certain limits on the element values. VJ VJ Junction capacitance approximation in forward . Other model parameters that can cause numerical problems for bipolar devices are the emission coefficients.3 is replaced for pn junctions in all semiconductor models with the tangent to the curve at a junction voltage determined by FC and the builtin voltage.8. It was shown above that the smallest conductance used by SPICE is GM IN = 1012. respectively. 9. The maximum conductance cannot be more than 14 to 15 orders of magnitude larger than the smallest conductance in order to satisfy the constraint set by the limited accuracy of number representation in a computer (see Sec. This error can also occur for JFETs and MOSFETs when improperly biased because of the presence of an ideal pn junction between gate and drain or source or between bulk and drain or source.5. 3.328 10 CONVERGENCE ADVICE pn junction of the diode would melt if no proper currentlimiting resistor is added in the circuit. 3.3 is replaced by the tangent to the curve it describes when the junction voltage reaches half the value of the builtin voltage. 3. Eq. Vi where 0:5 FC < 1. Vi: Vx = FC.8 bias. as well as Fe. for a forwardbiasedjunction. The default for FC is 0.3.2) The approximation is shown graphically in Figure 10. In SPICE the characteristic described by Eg.
and Ko 1985). the presence of VAF in a BIT model results in a finite output conductance of the transistor. as explained in Sec. Convergence problems also occur when the most elementary or ideal models are used. as demonstrated by Example 10.COMMON CAUSES OF SOLUTION FAILURE 329 smaller than 1 n need to be modeled. such as baseresistance modulation. 10. The use of ideal switches also leads to extreme values for the ON and OFF resistances. more complex model can be achieved by initializing key nodes of the circuit. these models are accessed by the LEVEL parameter. RON and ROFF. can help convergence. parameters RBM and IRB.3. Scharfetter. Once a first solution is obtained. and smallsize effects. the lower the chance for such an occurrence. such as finite output conductance and charge storage.3. . The presence of a parameter causes the inclusion of a specific physical effect in the behavior of a semiconductor device. MOSFETs can be described by more complex and accurate models than the SchichmanHodges model presented in Chap. . in a BIT (Appendix A) or smallsize effects in a MOSFET. The higherlevel models include such secondorder effects as subthreshold current. and to 4 in PSpice. Therefore. the smallest values are dictated by semiconductor models and are of the order of femtofarads (l015 F). The simpler the model. convergence with "theinitial. on convergence improvement in DC and transient analysis. it is not necessary to set these two parameters.2.3. it is necessary to use initialization of critical nodes and adjust some options parameters. Once all the above guidelines on circuit correctness and component values limits have been observed and SPICE still does not converge. For example. subthreshold conduction in a MOSFET can help convergence. whereas the absence of the parameter eliminates modeling of the corresponding effect. As explained in Sec. In this situation the user is advised to add those parameters that increase accuracy to the simulation.5. the equations implemented in various versions of SPICE are not perfect. which can go to 3 in SPICE2 (Vladimirescu and Liu 1981). As mentioned earlier. 3.4. Convergence is related not only to specific values of model parameters but also to the complexity of the models. a selective omission of secondorder effects. a nonzero value for LAMBDA in a FET model introduces a finite output conductance in the saturation region. This approach is exemplified by the BiCMOS voltage reference circuit in the following section. when a very complex model is used for a device and the simulation of the circuit fails. 9. velocitylimited saturation. For a specific combination of arguments the function describing the conductances can become discontinuous. similarly. The OFF resistance need not be as large as lIGMIN The same rules on the ratio between the largest and smallest values of a component must be observed also for capacitors and inductors. more than six orders of magnitude apart as long as they are virtual shorts and open circuits by comparison with the other conductances in the circuit. The value of "theequivalent conductance for these elements is also a function of the integration time step. 1 JLF. but the lower limit defined above should still be observed. as described in Sec. 2. to 6 in SPICE3 (Sheu. For practical circuits the largest capacitances should not surpass . These two issues are exemplified in the following two sections. Also.
6E16 UO=139 LAMBDA=O.4 Solution The circuit is a conventional threestage CMOS operational amplifier (Gray and Meyer 1985) in a closedloop unitygain feedback configuration.35EIO CGDO=3.74E4 MJ=0. PSpice and the latest versions of SPICE3 automatically run a builtin convergenceenhancing algorithm after failing to find a solution in the first ITLl iterations.The function of the various transistors is documented in the input file. It is questionable whether it makes sense to use a higher ITLl in PSpice.OPTION ITL1=300 to the input file.35EIO CJ=4.10.9 using SPICE2. however. which may need more than 100 iterations to converge. Note that various SPICE versions handle nonconvergence in different ways.02 CGS0=2.02 XJ=O. This circuit does not converge in PSpice or SPICE3. aborts the run if no convergence is reached in ITLI iterations.76 GAMMA=0. the DC operating point is found by SPICE2 in 108 iterations.4 Compute the operating point of the CMOS operational amplifier shown in Figure 10. which use automatic ramping algorithms.11. The following LEVEL=2 model parameters should be used for the two types of MOS transistors: NMOS: VTO=O.330 10.6 TOX=225EIO NSUB=1. The first step to be taken after a convergence failure is to rerun the circuit for more than the default ITLl iterations.2E6 CGS0=3. The analysis of this circuit produces a DC convergence error in SPICE2.89EIO CJ=3.4 PMOS: VTO=0. and the results are as listed in Figure 10.71 GAMMA=0.5E16 U0=411 LAMBDA=0.3 10 CONVERGENCE ADVICE DC CONVERGENCE This section describes several approaches that can be followed when a circuit that has passed the scrutiny of the previous section fails to converge in DC analysis. and the user must specifically request the sourceramping convergence algorithm by specifying the ITL6 option. It definitely makes sense in SPICE2. listed in Figure 10. This circuit is extracted from the collection of circuits with convergence problems in SPICE prepared by the Microelectronics Center of North Carolina. among the three versions used in this text. ITLl defaults to 100 in SPICE2 and SPICE3 and to 40 in PSpice. .75E4 MJ=O.89EIO CGDO=2. EXAMPLE 10. The iteration count is increased by adding the line . Thus. SPICE2. especially for large circuits. which automatically ramps the supplies after ITLl iterations and may find a solution faster through this approach.29 TOX=225EIO NSUB=3.
.• . .9 CMOS opamp circuit diagram.G) 5V 100n RF ~ ~ Figure 10.
The simulation file is set up for closed loop (unitygain feedback) analysis of transient and ac performance.0 0.5U W=71U W=69U W=35U W=12U L=40U L=10U L=10U. CMOS opamp from the MCNC SPICE test circuits. . L=10U L=10U * DIFFERENTIAL * * MI0 36 33 32 1 AMPLIFIER STAGE L=2U L=2U L=3U L=3U L=2U AD=24P AD=24P AD=136P AD=136P AD=24P AS=24P AS=24P AS=136P AS=136P AS=24P PCH W=11U M20 3 34 32 1 PCH W=11U M30 36 36 o 0 NCH W=6U M40 3 36 o 0 NCH W=6U M50 32 7 1 1 PCH W=14U * * * FOLDED CASCODE STAGE WITH COMPENSATION W=80U L=2U AD=24P AS=24P W=24U L=2U AD=136P AS=136P W=46U L=2U AD=136P AS=136P W=4U L=3U M2 6 7 1 1 PCH M3 6 5 4 0 NCH M4 4 3 0 0 NCH M80 11 5 3 0 NCH CC 6 11 .5 * *.10 * AD=136P AS=136P L=2U AD=136P AS=136P SPICE input for CMOS opamp.332 10 CONVERGENCE ADVICE CMOS OPAMP * * * * * * * This opamp is a conventional 3stage. SUPPLY VOLTAGES VDD 1 0 DC 5 VAP 34 99 PULSE ( 0. internally compensated.5 0 lE9 lE9 50E9 100E9 ) VIN 99 0 DC 2. ANALOG * * M65 M64 M63 M62 M61 0 7 5 5 9 0 7 7 5 9 INPUT * BIAS CIRCUIT * 7 1 1 9 0 1 1 1 0 0 PCH PCH PCH NCH NCH W=4.22PF * COMMON DRAIN OUTPUT STAGE * M7 1 6 12 12 NCH W=100U L=2U M8 12 9 0 0 NCH W=63U Figure 10.
250D04 O. 333 .0207 NODE 3) 7) 32) 99) VOLTAGE 1.6144 2.35E10 CJ=4.5000 1.END Figure 10.4 TOX=225E10 NSUB=1.74E4 MJ=0.35E10 + CGDO=3.10 (continued) *******01/21/92 CMOS OPAMP **** ******** SPICE 2G.2190 2.1081 1.11 CMOS opamp DC solution.3756 1.89E10 CJ=3.75E4 MJ=0.5000 NODE 4) 9) 33) VOLTAGE 1.71 GAMMA=0. 02 PCR PMOS LEVEL=2 VTO=0.89E10 VTO=O.4 TOX=225E10 NSUB=3.0208 3.OOODtOO TOTAL POWER DISSIPATION 1.0208 2.* LOAD CL 12 0 10PF FEEDBACK CONNECTION RF 12 33 100 * * * * * MOSFET PROCESS MODELS NMOS LEVEL=2 CGS0=2.29 * .MODEL * + CGDO=2.76 GAMMA=0.6 CGS0=3.000 DEG C *********************************************************************** NODE ( 1) ( 6) (12) (36) VOLTAGE 5.5000 VOLTAGE SOURCE CURRENTS NAME VDD VAP VIN CURRENT 3.MODEL NCR * .8663 3.6 3/15/83********15:44:54***** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.6E16 + XJ=0.5000 NODE 5) 11) 34) VOLTAGE 2.2E6 UO=139 LAMBDA=O.OPTIONS ACCT ITL1=300 .OP .0000 3.5E16 + U0=411 LAMBDA=O.62003 WATrS Figure 10.OOODtOO O.02 * ANALYSES * .7841 2.
23E12 1.376 2.021 1.OOE+OO O.710 0.219 1.36E07 2.84E13 7.269 0.23E13 2.72E06 5.OOE+OO O.25E14 O.OOE+OO O.OOE+OO O.271 0.216 0.14E14 1.26E13 7.OOE+OO O.68E15 3.59E14 6.27E06 4.OOE+OO o .41E14 5.271 0.08E06 5.748 0.219 1.OOE+OO O.47E05 5.33E14 1.021 0.269 0.000 0.157 1.66E14 7.OOE+OO O.OOE+OO O.108 0.292 0.844 0.OOE+OO 9.38E14 2.000 1.47E05 1.OOE+OO O.710 0.6 3/15/83********15:44:54***** OPERATING POINT INFORMATION TEMPERATURE = 27.OOE+OO O.80E05 3.134 1.16E15 1.OOE+OO 1.~  *******01/21/92 CMOS OPAMP **** ******** SPICE 2G.09E14 O.284 1.219 0.021 0.763 1.000 0.09E14 1.68E15 O.94E15 6.OOE+OO O.OOE+OO 1.965 0.73E15 1.68E14 O.37E06 8.49E06 1.15E15 O.OOE+OO 1.OOE+OO O.750 1.88E15 7.59E14 O.10E07 5.00E04 3.000 0.OOE+OO O.52E05 4.965 0.OOE+OO O.58E13 1.07E05 2.66E14 5.021 0.021 1.62E06 8.79E07 1.10E07 5.865 0.37E05 2.293 2.37E05 6.000 1.42E05 1.OOE+OO O.19E05 1.OOE+OO O.72E06 1.88E15 3.01E14 3.44E05 3.284 1.OOE+OO O.69E15 2.19E05 1.98E06 5.216 1.000 0.OOE+OO O.OOE+OO O.866 1.37E06 1.33E06 3.11 (continued) 334 .69E15 2.OOE+OO 4.21E06 4.64E13 O.216 1.73E:"15 O.332 0.58E15 7.25E12 1.30E06 3.157 1.854 0.58E15 O.OOE+OO 7.108 1.47E15 3.134 2.866 2.47E15 3.267 2.134 3.57E14 3.31E14 1.92E07 1.07E06 5.01E14 3.OOE+OO O.021 0.506 1.91E14 O.42E05 5.33E06 1.463 4.03E05 2.OOE+OO O.OOE+OO O.OOE+OO O.000 DEG C *********************************************************************** **** MOSFETS M20 M61 M10 M62 M64 M63 M65 PCH NCH PCH NCH PCH PCH PCH 8.36E05 7.OOE+OO MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGOOVL CGBOVL CGS CGD CGB MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGOOVL CGOOVL CGS CGD CGB Figure 10.706 0.68E14 1.05E06 5.14E05 3.48E07 3.72E06 8.OOE+OO O.624 3.94E15 O.37E06 1.OOE+OO O.OOE+OO M4 M80 NCH NCH 6.OOE+OO O.OOE+OO M3 NCH 6.000 0.707 0.134 1.710 0.63E15 5.269 3.331 3.99E05 3.OOE+OO 5.49E06 1.OOE+OO O.OOE+OO 5.OOE+OO 1.763 2.16E15 O.14E14 1.OOE+OO O.24E07 1.06E13 3.09E14 1.OOE+OO 2.134 0.062 0.OOE+OO O.265 0.OOE+OO O.51E13 3.68E15 1.88E15 O.79E07 2.84E14 2.86E14 1.29E05 6.OOE+OO O.134 1.92E07 5.444 0.16E14 O.63E06 8.38E14 2.710 0.19E05 1.33E14 1.68E15 1.OOE+OO O.389 3.25E14 1.OOE+OO O.73E15 4.OOE+OO O.000 0.51E15 2.55E05 5.37E06 5.07E05 6.92E04 1.OOE+OO M30 NCH 5.31E14 1.73E15 4.84E14 O.OOE+OO O.000 1.99E04 1.386 1.89E07 2.OOE+OO O.OOE+OO O.OOE+OO M2 M50 M40 PCH PCH NCH 5.355 1.51E15 2.
114 2.OOE+OO 1. ITLl.89E14 M8 NCH 2.OOE+OO O. The next .35E04 1. (continued) ABSTOl. 6.OOE+OO O.09E14 2. and RELTOL. which defaults to 103..28E04 4. Next an operational amplifier that fails DC convergence will be considered.89E14 5. it is recommended to use initialization either by setting the values of key nodes with .12 using SPICE2.17E03 4. nor looser tolerances help the solution of this circuit.05E13 O.95E06 1.500 0. The next step in overcoming a convergence error is to relax the two.DC CONVERGENCE 335 MODEL ID VGS VDS VBS VTH VDSAT GM GDS 8MB CBD CBS CGSOVL CGDOvL CGBOvL CGS CGD CGB M7 NCH 2.500 0.. the absolute'curr~nttolerance.95E06 1. The SPICE input file is listed in Figure 10.NODESET and.OOE+OO Figure 10.9E14 8 5. the sourceramping mechanism must be invoked in SPICE2.11 . When the above options do not lead to a solution.219 2. and the steps that lead to a solution will be outlined.000 0. Especially for MOS circuits the default ABSTOL can be too small.710 0.29E13 O.76E04 2. The opamp is connected in feedback loop. EXAMPLE 10.uA74l operational amplifier with an external follower circuit shown in Figure 10.35E04 1.37E04 2 .352 1.89E14 2. If the ramping methods fail.key tolerances which defaults to I pA. Ie (see Sec.13. the relative convergence tolerance. Solution emitterstage is discrete a unity The simulation of this circuit results in a convergence failure. Neither a higher number of iterations. 4.000 0.6 and Sec.3) or by identifying cutoff devices with the OFF keyword (see Chap.5 Find the DC bias point of the . or some of the iteration options must be changed in PSpice and SPICE3.OOE+OO O. 3).444 9.710 0.09E14 1.82E14 O. The external output formed of two emitterfollower stages built for higher current capability with transistors 2N2222 for Q21 and 2N3055 for Q22.82E14 1.OOE+OO 2.
.A741 opamp with highcurrent output stage.S soon R. SOkn R2 1kn RlO son Vs 1SV Figure 10.12 p.w W Q'I Vs 1SV VT Qg NPNL R.
5K 6 12 7.12.DC CONVERGENCE 337 UA 741 W / POWER OUTPUT STAGE Ql 18 5 24 NPNL AREA=l Q2 18 19 25 NPNL AREA=1 Q3 23 3 25 PNPL AREA=4 Q4 4 3 24 PNPL AREA=4 Q5 3 18 9 PNPL AREA=5 Q6 18 18 9 PNPL AREA=5 Q7 23 21 22 NPNL AREA=l Q8 4 21 20 NPNL AREA=l Q9 9 23 21 NPNL AREA=0.5K 1 7 25 8 1 50 29 14 50 29 15 50K 0 2 500 0 5 300M 30 0 3K 9 30 12K (continued on next page) Figure 10. .5 Q10 17 17 29 NPN AREA=2 Q11 3 17 16 NPNL AREA=2 Q12 29 6 8 PNP AREA=120 Q13 11 13 9 PNP AREA=30 Q14 13 13 9 PNP AREA=12 Q15 9 11 7 NPN AREA=60 Q16 11 7 1 NPN AREA=3 OFF * Q16 11 7 1 NPN AREA=3 Q17 11 12 6 NPN AREA=7 Q18 6 15 14 NPN AREA=7 Q19 6 4 15 NPNL AREA=5 Q20 4 14 29 NPN AREA=4 OFF * Q20 4 14 29 NPN AREA=4 Q21 9 1 2 2N2222 AREA=l Q22 10 2 5 2N3055 AREA=1 Rl R2 R3 R4 R5 R6 R7 R8 R9 RIO R11 R15 R16 R17 R18 * * * THIS CKT FAILS OC CONVERGENCE * 29 21 50K 29 20 lK 29 22 1K 17 13 30K 29 16 5K 12 11 4.13 SPICE input file for circuit of Figure 10.
5 . 7 MJS=O.5 .68 NR=1. 6P VJC=l.MODEL NPN NPN IS=4.221 VAR=500 IKR=O + ISC=O NC=l RB=12 IRB=O RBM=12 RE=100M RC=1.5 .479F BF=260 NF=1.02167 VAR=500 IKR=l ISC=O NC=2 RB=1.l1 XTI=3 KF=O AF=1 FC=O.3 EG=1.68 NR=1.11 XTI=3 + KF=O AF=1 FC=0.OP *.3P BF=120 NF=1.25P + VJE=916M MJE=389. 7 ITF= .155 BR=4.6P VJC=1.C1 11 4 30P VY VT V6 V5 * * 19 30 9 10 0.1 EG=l.07 VAF=260 IKF=lM + ISE=3.394 NR=1.221 VAF=150 IKF= + 1.221 VAF=150 IKF= + 150M ISE=2.074 VAR=500 IKR=O + ISC=O NC=l RB=676M IRB=O RBM=676M RE=100M RC=654M + CJE=22. 518 XCJC=O.66 BR=l NR=1. 8M TF=361.25P VJE=1.07 VAR=500 IKR=O ISC=O NC=l RB=36 + IRB=O RBM=36 RE=500M RC=l CJE=910F VJE=661M + MJE=294M TF=112P XTF=120 VTF=O ITF=O PTF=O + CJC=835F VJC=l MJC=280M XCJC=0.88F BF=150 NF=1.155 BR=4. 5 TR=117.MODEL 2N2222 NPN IS=166. 5N CJS=O VJS=O. 5 TR=19. 72P XTF=21 VTF=4.66 BR=l NR=1.776 BR=2.3M PTF=O CJC=8. 5 * .25P + VJE=916M MJE=389.MODEL NPNL NPN IS=4.64F NE=2.7 EG=l.522 TF=454.11 XTI=3 KF=O AF=1 FC=O.333 + MJC=O.11 XTI=3 KF=O AF=1 FC=0.11 XTI=3 KF=O AF=1 FC=0.24 VTF=4.5 . 5 XTB=2.92P NE=1.074 VAF=78 IKF=500M + ISE=3. 5 TR=400N CJS=O VJS=O. 5 XTB=l.11 XTI=3 KF=O AF=1 FC=O.MODEL PNP PNP IS=218.5 .5 XTB=2. 7 EG=l.OPT ITL6=40 ACCT .0 29 0 15 9 0 15 2N3055 NPN IS=10.5M XCJC=O.4P + XTF=13.479F BF=260 NF=1.34 EG=1.37P VJC=1.3 EG=l.07 VAF=260 IKF=100M + ISE=347.MODEL PNPL PNP IS=218.5 TR=lN + CJS=O VJS=700M MJS=0. 5 XTB=1. 5 + XTB=2. 72P XTF=21 VTF=4.5 CJE=6.02167 VAF=50 IKF=3 ISE= + 500P NE=2 BR=8. 5M XCJC=O.5 XTB=2.MODEL * .50M ISE=23.5 TR=lN + CJS=O VJS=700M MJS=0.5 TR=19. 8M TF=361.88F BF=150 NF=1.83 ITF=216.78F BF=150 NF=1. 7 MJS=O.471P NE=3.92N +CJS=O VJS=700M MJS=O.+ 260M PTF=O CJC=6.07 VAR=500 IKR=O ISC=O NC=l RB=36 + IRB=O RBM=36 RE=500M RC=l CJE=910F VJE=661M + MJE=294M TF=112P XTF=120M VTF=O ITF=O PTF=O + CJC=835F VJC=l MJC=280M XCJC=O.67 MJC=406. 92N + CJS=O VJS=700M MJS=O.8 + IRB=80M RBM=100M RE=5M RC=50M CJE=711P VJE=530M MJE=530M + TF=20N XTF=5 VTF=10 ITF=10 PTF=O CJC=650P VJC=580M MJC=400M + XCJC=O.1P NE=3.221 VAR=500 IKR=O + ISC=O NC=l RB=12 IRB=O RBM=12 RE=100M RC=1.13 (continued) 338 .WIDI'H OUT=80 .5 CJE=6. 7 ITF= + 260M PTF=O CJC=6.364P NE=2.333 MJE=0.END Figure 10.1 NR=1. 67 MJC=406.
For source ramping the function of IT. As a result of this inspection one can see that transistors Q20 and Q16 have the role oflimiting the current through the gain stage Q18 .00IDtOl 1.526D03 1.753DtOO 3. which is the number of iterations taken at each source value. the results are correct because of the correct biasing ofthe output. close to the value of node 19.9773 4. the positive input of the opamp.8930 20) 14.9902 2.9999 13.OPI'IONSITL6=40 The simulation results using this approach are shown in Figure 10.50Dt02 WA'ITS (continued on next page) TOTAL POWER DISSIPATION Figure 10. Q12 and Q15' The source ramping that is invoked automatically in PSpice fails to find a solution for this circuit.4726 14.12.1871 2. at 3 V. in such a situation it is suggested that the user change ITL2.4057 24) 4.L2 in PSpice is similar to that of !TL6 in SPICE2. which is node 5 and the emitter of Q22.6 UA741 W/ POWER OUTPUT STAGE **** SMALL SIGNAL BIAS SOLUTION 3/15/83********11:58:49***** TEMPERATURE = 27.0000 14. As can be verified.8958 4.000 DEG C *********************************************************************** NODE VOLTAGE NODE 2) 6) 10) 14) 18) 22) 29) VOLTAGE 3.0000 NODE 3) 7) 11) 15) 19) 23) 30) VOLTAGE 1.9902 15.Q19 and the output *******01/21/92 ******** SPICE 2G.7862 8) 12) 5.0000 13) 14.7906 1) 5) 3.6087 4.14. This convergence method is exercised by adding the following line to the above circuit file: .3784 17) 14.8498 5.0097 16) 14.859D08 9.DC CONVERGENCE 339 step is to use the builtin sourceramping algorithm.9999 ( ( ( ( ( ( NODE VOLTAGE 4) 13.0004 9) 15.3167 15. Another way of finding the bias point of this circuit is by understanding the role of each transistor. A quick inspection of the operating point of the devices shows that the current through the external transistor Q22 is higher than the current in the class AB output stage of the opamp.3947 2.8792 14.4054 25) VOLTAGE SOURCE CURRENTS NAME VY VT V6 V5 CURRENT 3.4823 14. .7767 2.2969 21) 14.14 SPICE DC solution for the circuit of Figure 10.
896 0.594 0.472 12. 65Ell O.90E12 O.36Ell 6.13E12 3.04E05 8.445 1.865 3.06E13 5. 68E+07 6.26E12 8.69E04 2.94E02 1.40E+05 2.86E08 6.595 0.85E+06 Q6 PNPL 1.222 113.OOE+OO 266.703 196.06E13 O.873 3.706 3.00E01 1.10E08 9.722 3. 14E+06 MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT Q1 NPNL 3.12E05 0.OOE+OO 262.595 0.000 DEG C *********************************************************************** **** BIPOLAR JUNCTION TRANSISTORS Q4 PNPL 6.395 274.21E+05 3.20E+01 2.73E+05 7.595 11.06E13 5._ 340 10 CONVERGENCE ADVICE *******01/21/92 ******** SPICE 2G.51E04 7.829 162.596 0. 31Ell 9.55E13 O.000 9.32E07 2.65E13 3.43Ell 2.14E04 5.26E+05 3.182 255.37E+05 3.473 15.510 15.23E10 4.137 6.78E02 2.00E01 1.81E06 0.6 3/15/83********11:58:49***** UA741 W/ POWER OUTPUT STAGE OPERATING POINT INFORMATION **** TEMPERATURE = 27.18E08 1.611 8.881 3.527 0.29E04 6.89E08 9.12E12 O.OOE+OO O.691 3.35E13 O.16E+06 Q2 Q3 NPNL PNPL 3.618 1.40E+05 2.672 12.203 8.510 11.210 126.81E06 0.99E08 9.527 147.00E+00 1.87E06 9.05E08 9.394 3. 29E+07 1.13E05 8.047 1.66E+06 4.55E+06 1.80E+01 1.882 4.014 162.80E06 2.77E13 1.60E+01 3. 28E+06 Q7 NPNL 3.193 19.20E12 2.65E+07 6.489 7.OOE+OO 163.777 29.42E02 6.642 68.703 0.40E+00 7.52E12 8.809 8.11E04 7. 65Ell 1.68Ell 3.17E+05 3.14 .381 245.07E14 8.OOE+OO 148.31E+03 4. 56E+06 Q8 NPNL 3.OOE+OO 251.36Ell 1.470 16.213 245.622 120. 73E+03 4.14E12 3.518 0.10E+08 MODEL IE IC VBE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETAAC FT Qll Q12 NPNL PNP 8.96Ell 4.18E06 2.527 12.56E04 7.10E12 O.067 255.38E+07 6.95E05 0.618 28.93E10 3.50E+05 2.42E+05 5.46E+04 1.35E13 8.17E12 3.OOE+OO 274.65E+07 6.36E+05 Q13 Q14 PNP PNP 2.OOE+OO O.76E+06 3.52E04 0.577 13.623 47.~_.622 8. OOE+OO 6.60E+01 2.62E04 2.68Ell 3.07E14 O.786 1. 88E+03 1.646 8.08E+07 2.42E08 1.OOE+OO 262.51E04 7. 66E+06 4.OOE+OO 251.17E04 2.46E03 9.OOE+OO 134.000 0.10E12 2.00E+00 2. 99E+06 1.32E07 1.85E06 9.219 163.067 16.400 6.75E+07 1.11E+06 Q9 NPNL 4.60E+01 2.476 1.789 19.21E05 0.504 16.OOE+OO 160.02E+07 (continued) Q10 NPN 4.104 160.50E05 0.08E10 1.OOE+OO O.77E13 1.94E06 0.000 0.104 1.99E08 9.796 8.42E10 3. 17E+05 3. 12E+06 Q5 PNPL 1.OOE+OO 235. 80E+01 2.622 0.786 260.12E12 5.55E13 3.73E+07 6.733 6.85E06 0.90E12 6.69E03 3.42E10 O.60E+01 2.96Ell O.43Ell 5. 61E+05 3.65E13 O.53E04 3.28E04 0.92E06 0.32E+07 Figure 10.317 16.67E+07 3.56E+04 1.38E+05 7.40E+00 7.06E13 2.341 7.
797 5.023 12.14E+00 1.90E+07 9.10E12 0.09E12 O. 84E+03 5.OOE+OO 230.38E12 1.344 2. 25E+00 MODEL IB IC VEE VEC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETMC FT Figure 10.406 1.34E03 0.30E11 1.691 7. Adding the keyword OFF at the end of the lines corresponding to these transistors and commenting out the line defining ITL6 result in the quick convergence of the circuit.63E+05 7. 16E+05 2.74E+11 2. 12E+05 2.62E12 2.615 8.001 5.473 1. 11E+08 Q22 2N3055 2.813 10.65E02 2.001 1. 30E11 O.07E01 6.33E03 0.578 17.186 6. respectively.07E11 9.209 11.692 18.84E05 0. 20E+01 9. PSpice and SPICE3 also converge easily to a solution.45E12 0.23E+06 Q20 NPN 3.23E05 2.OOE+OO 246.58E09 4.11E07 2. In normal operation these two transistors should be turned off.633 9.000 1.OOE+OO 0.16E13 9.09E12 1.76E+03 5.271 1. 391 0.81E+08 Q19 NPNL 1.47E+02 1.OOE+OO 86.75E+00 0.26E05 2.166 184.000 39.692 0.513 8.40E03 0.54E01 0. 14E+00 1. 05E+08 MODEL IB IC VEE VBC VCE BETADC GM RPI RX RO CPI CMU CBX CCS BETMC FT Q15 NPN 2.20E+00 9.86E12 1.OOE+OO 0.28E03 2.196 195.91E11 9.53E05 2.76E+06 2.38E12 O.14 (continued) transistor Q15. 31E01 Q17 NPN 1.33E12 1. 86E+07 1.46E02 2.62E12 O.745 1.925 18. 15E+05 9.16E13 O.49E05 9.28E+06 Q16 NPN 9.023 111.81E12 1. 05E08 1.518 10.00E01 1.002 4.DC CONVERGENCE 341 Q21 2N2222 2.633 0.797 2.693 0.04E10 1.OOE+OO 268.22E+00 1.08E11 2.150 92. 11E+08 Q18 NPN 1. The above example has illustrated how both source ramping and the OFF initialization of transistors can lead to a solution. 33E12 O.121 1. 11E11 1.504 19.76E01 3.00E+00 9.504 256.37E02 2.12E11 1.215 5.48E01 9.11E12 4.27E12 O.OOE+OO 22.977 11.04E+03 6.13E+02 1.71E+11 3.109 8.55E11 1.81E01 6. Another circuit that demonstrates the need . in only 11 iterations in SPICE2.OOE+OO 172.96E+00 1. 27E12 1. 24E+01 6.648 1.02E03 2.97E11 O.059 0.
This circuit. @ CD R2 Rs 10kQ D4 @ 100 kQ 0  @ R4 10kQ Da  Ra 10kQ I 0 Rs 15 kQ ems VEE=15V 0 Figure 10. given in Sec.5.LA741 opamps as the gain stages. may fail to lead to a solution for this circuit depending on the model used for the opamp. All the approaches mentioned above.16. containing highgain stages and highimpedance nodes. Solution The input description of the circuit is listed in Figure 10. is used for the J. D2 R7 15kQ @ +vcc 0 R.342 10 CONVERGENCE ADVICE of initialization is the bistable circuit in Figure 10. .LA741. The subcircuit definition of UA741MAC has to be copied from Figure 7. 10.15 prior to computing the response to a sawtooth input voltage VA.6 Find a DC solution to the bistable circuit shown in Fig. 7.16. implemented with two J. is one that requires +Vcc=15V CD D.28). including source ramping.15. EXAMPLE 10.15 Bistable circuit with /LA 741 opamps. The macromodel UA741MAC.1 (Figure 7.28 into the deck of Figure 10.
Figure 10.MODEL M1M1N914 D IS=lN RS=500M N=1.OPTIONS ACCT .6 *.PLOT TRAN V(3) V(15) V(13) V(S) V(4) * * * INITIALIZATION FOR VIN=15 .OP .WIDTH OUT=SO .5M 0 * 15 13 M1M1N914 AREA=l 13 15 M1M1N914 AREA=l 9 16 M1M1N914 AREA=l 16 11 M1M1N914 AREA=l * .6 V(l5)=O V(S)=.55 TT=5N CJO=l.TRAN .OlM 2M 0 .5 BV=120 IBV=l ' R7 R6 R5 R4 R2 R1 * 1 11 15K 11 4 10K 9 2 15K 4 9 10K S 13 lOOK 15 3 10K RESISTOR * *'FEEDBACK R3 4 15 10K * CNS S 0 1P CN15 15 0 1P XOPA1 0 15 13 1 2 UA741MAC XOPA2 0 S 4 1 2 UA741MAC * * * * .16 343 .15 PWL 0 151M VCC 1 0 15 VEE 2 0 15 D1 D2 D3 D4 * 152M 15 2.ENDS .BISTABLE CIRCUIT WI UA741 OPAMPS *VA 3 0 15 VA 3 0 DC .NODESET V(4)=15 'V(13)=.OPTIONS ITL1=300 ABSTOL=lU .SUBCKT UA741MAC 3 2 6 7 4 * NODES: INt IN.OUT VCC VEE * INSERT UA741 MACROMODEL DEFINITION FROM FIG.11 XTI=3 KF=O AF=1 FC=O.S5P + VJ=650M M=lS0M EG=1. 7~2S * * .END SPICE input for bistable circuit with JLA741 opamps.
5 2. as well as the opamp output. nodes 4 and 13.6V and 0. one of the states of this circuit can be specified with the following • NODESET statement: o .6 V.5 1.0 Time.6 V(8)=O. The waveform at node 4 together with the triangular input voltage is shown in Figure 10.6983 V(4) Note that a DC solution is a prerequisite for a transient analysis unless the UIC keyword is used on the • TRAN line.6 V(4)=15 With this line added to the circuit description solution is obtained: of Figure 10.NODESET V(15)=O V(13)=O. for an NMOS flipflop SPICE finds the metastable state as solution. is limited by the two diodes D1 and Dz to between 0. nodes 8 and 15. with the input at a very low value.17 Transient response of V ( 4) to triangular input V ( 3 ) .0003 0. ms 1.5964 = = = 0. The output of XOPAl.5452 12. As described in Example 4.344 10 CONVERGENCE ADVICE the initialization mentioned in the previous section. node 13.8.0 Figure 10.17. The highimpedance opamp input. This state corresponds to all inputs and outputs of the opamps being at V. Therefore. must be initialized. . in this case an • IC line should be used to define the initial state of the circuit in order to avoid a convergence failure at the first time point. > oj ~ g 0.16 the following refineo v (15) V ( 13 ) V(B) = 0.
DC CONVERGENCE 345 Circuits with highimpedance nodes are often difficult convergence cases for circuit simulators. .18. NPN NPN 9kO o @ Vss Fi~ure 10.18 BiCMOS bias reference circuit. initialization and variations in model parameters and complexity can help convergence. For such circuits a combination of ramping methods. A good example for a difficult convergence case is the BiCMOS reference circuit shown in Figure 10. Highimpedance nodes are common in CMOS and BiCMOS circuits using cascode configurations.
The second approach recommended in convergence cases of circuits using complex models is to eliminate some of the secondorder effects. represented by parameters VMAXand NEFF.19 is the DC operating point shown in Figure 10. represented by parameters UCRIT and UEXP. For more details on the semiconductor device physics see the works by Muller and Kamins (1977) and by Sze (1981).7 Find the currents in the two branches of the thermalvoltagereferenced in Figure 10. 3. saturation due to carrier velocity limitation. therefore we expect the current in the left branch to be approximately five times the current in the right branch. Two approaches are suggested for solving this convergence problem. A rerun of the circuit results in the desired solution in SPICE2 in 96 iterations without the need of ramping.346 10 CONVERGENCE ADVICE EXAMPLE 10.6 /LA (10. . and mobility modulation by the gate voltage. and SPICE2 requires ITL6 to be set to 40 for convergence. set by parameter NFS. Note that a model of higher accuracy is used for the MOSFETs than the one described in Chap. respectively. PSpice finds a solution after source ramping. Deletion ofVMAX and NEFF as well leads to a SPICE2 solution in only 25 iterations. consistent with our estimates. A first approximation is to neglect for all MOSFETs the smallsize effects. The transistors with the larger area are modeled as they are implemented on the layout. current source Solution The areas of the MOS transistors in the left branch are five times the areas of the MOSFETs in the right branch of the circuit. set the ITL6 option in SPICE2 to invoke the sourceramping method. such as narrowwidth modulation of the threshold voltage. The solution to the SPICE input of Figure 10. For the input specification of this circuit shown in Figure 10. and velocitylimited saturation. which make convergence to the DC solution difficult. as five transistors connected in parallel. namely.18. The complete model equations for LEVEL=2 can be found in Appendix A or in the text by Antognetti and Massobrio (1988).19. The LEVEL=2 model includes such secondorder effects as subthreshold conduction. represented by parameter DELTA.3 /LA. which can be estimated from the VBE difference of the two identical BJTs (Gray and Meyer 1985): Vth 1= Rln5 = 4. The currents in the right and left branches are 4.3) Because of the cascode currentsource configuration the drain connections between transistors M3 and Ms and between M4 and M6 are highimpedance nodes. This is achieved by deleting the DELTA parameter from the •MODEL statement.20. First.66 /LA and 23. represented by parameters VMAXand NEFF.
8 TOX=500E10 NSUB=2E15 + XJ=0.WIDTH OUT=80 .OPTION ABSTOL=lN .MODEL NPNMOD NPN IS=2E17 BR=.5E6 U0=640 UCRIT=6E4 UEXP=O.5E6 LD=.OP .18 + VMAX=3E4 NEFF=3.MODEL P PMOS LEVEL=2 + VTO=0.8E4 UEXP=0.5E6 LD=.5 DELTA=2. 347 .5 NFS=3E11 * * * + IKR=lE3 .4 BF=100 ISE=6E17 ISC=26E17 IKF=3E3 + VAF=100 VAR=30 RC=100K RB=200K RE=lK .END * DEFW=20U Figure 10.8 TOX=500E10 NSUB=1.5E6 U0=220 UCRIT=5.MODEL N NMOS LEVEL=2 + VTO=O.l + VMAX=5E4 NEFF=4 DELTA=4 NFS=4E11 .BIOMOS BIAS REFERENCE Q1 10 10 3 NPNMOD 400 Q2 10 10 1 NPNMOD 400 R1 1 2 9K M1A 8 12 11 11 N M1B 8 12 11 11 N M1C 8 12 11 11 N M1D 8 12 11 11 N M1E 8 12 11 11 N M2 12 12 11 11 N M3A 6 13 8 11 N M3B 6 13 8 11 N M3C 6 13 8 11 N M3D 6 13 8 11 N M3E 6 13 8 11 N M4 13 13 12 11 N M5A 6 6 4 10 P W=60U M5B 6 6 4 10 P W=60U M5C 6 6 4 10 P W=60U M5D 6 6 4 10 P W=60U M5E 6 6 4 10 P W=60U M6 13 6 5 10 P W=60U M7A 4 4 3 10 P W=60U M7B 4 4 3 10 P W=60U M7C 4 4 3 10 P W=60U M7D 4 4 3 10 P W=60U M7E 4 4 3 10 P W=60U M8 5 4 2 10 P W=60U VDD 10 0 5 VSS 11 0 5 .OPTION ACCT DEFL=10U *.19 SPICE description of BiCMOS bias reference circuit.3E16 + XJ=0.
000 0.248 2.348 10 CONVERGENCE ADVICE *******02/11/92 BICMOS ******** SPICE 2G.4360 3.00E+02 2.4778 3. 01E07 1.833 0.25E05 1.522 0.25E05 M1B N 4. .60E08 1.78E04 4.66E06 1.000 0.798D05 DISSIPATION 2.841 0.000 0.90E04 9.66E06 1.51E05 2.711 0.246 2.000 0.0000 SOURCE NODE 2) 6) 12) CURRENTS VOLTAGE 4.66E06 4.66E06 1.01E07 1.564 0.000 DEG C *********************************************************************** **** BIPOLAR JUNCTION TRANSISTORS MODEL IB IC VBE VBC VCE BETADC GM RPI RX RO Q1 NPNMOD 2.165 0.66E06 1.152 1.8484 NODE 3) 8) 13) VOLTAGE 4.0000 VOLTAGE NAME VDD VSS CURRENT 2.51E05 1.51E05 1.36E08 4. 25E05 M1C N 4.165 0.152 1.6 3/15/83********15:57:31***** BIAS REFERENCE SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.248 0.8759 3.152 1.46E+05 5.01E07 1.841 0.152 1.000 0.248 2.000 0.80D04 ******** SPICE 2G.165 0.000 DEG C **** *********************************************************************** NODE 1) 5) 11) VOLTAGE 4.84E07 2.6 WATTS 3/15/83********15:57:31***** TOTAL POWER *******02/11/92 BICMOS BIAS REFERENCE OPERATING POINT INFORMATION TEMPERATURE = **** 27.26E+06 Q2 NPNMOD 6.51E05 1.522 72.30E05 0.152 1.66E06 1.841 0.000 0. 01E07 1.152 1.4359 1.67E+04 5.564 81.54E05 5.841 0.26E05 MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB Figure 10. 01E07 1.165 0.01E07 1.51E05 1.000 0.25E05 M3A N 4.6967 NODE 4) 10) VOLTAGE 3.00E+02 4.152 1.248 2.248 2.60E06 0.14E+07 **** MOSFETS M1A N 4.248 2.000 0.20 DC operating point of BiCMOS reference circuit.8354 2.841 0.139 5.25E05 M1D N 4.165 0.2322 5.116 8.66E06 1.2169 5.51E05 1.841 0.798D05 2.318 1.25E05 M2 M1E N N 4.
66E06 1. 31E07 1.000 0.204 1. This method is applied in the next example to obtain the hysteresis curve of a CMOS Schmitt trigger.939 0.60E.204 0.66E06 1.66E06 1. Once a solution is obtained.DC CONVERGENCE 349 M3B MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB N N M3C N M3D N M3E N M4 4.097 0.204 1.29E07 4.564 0.66E06 .58E06 4.60E08 1. 4. 768 1. .29E07 3.06 4.768 1.98E05 2.66E06 1.833 0. which do not allow instantaneous switching to take place.914 1.2..26E05 .31E07 1.98E05 2.248 2.270 2.564 .54E05 5.356 1. The advantage of timedomain analysis for solving circuits with positive feedback and high loop gain resides in the presence of charge storage elements.246 2.66E06 4.58E06 Figure 10.139 .219 0.356 1.54E05 5.564 0.04E05 3.152 0. .833 0. Another approach to 'finding the DC bias point of a circuit is to ramp up the supplies in a transi~nt analysis. initialization of critical nodes can be used to obtain convergence of the circuit using the complex models and default tolerances.04E05 1.275 3.58E06 p.60E08 1.152 1.204 0.000 0.139 5.204 1. 097 .833 0..29E07 1.14E05 1.66E06 1. MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB M7D P 4.98E05 3.20 ( continlfed) This example shows that both source ramping and selective deletion of some secondorder effects can lead to convergence for CMOS and BiCMOS circuits.51E05 1. which displays very abrupt switching at the two thresholds.54E05 5.98E05 1.P P P P 4.66E06 1.000 0.841 0.267 0.564 0.270 2.939 0.270 .204 1.711 0.246 2.097 1.66E. 4.66E06 1.04E05 3.66E06 4.66E06 1:356 1. 5.270 0.711 0.341 1.66E06 4..204 ~1.000 0':833 0.':1'.275 0.54E05 5.768 1.0.29£06 M7C P 4.939 0.66E06 1.66E06 4.29E07 1. 783 0.270 2.58E06 M7E M8 P P 4.204 1.26£05 M5A M5B P P. 29E07 4. 768 1.275 0.356 5.66E06 1..270 0. 00E07 1. 01E07 1.097 1.i75 0.139 5.66E06 4.356 1 :356 1..204 1.275 3.139 5. 097 1.25E05 4.04E05 3.29E06 3.37E~06 3.98E05 1.939 0. Another possible' approach is to increase the values of ABSTOL and RELTOL.246 2.31E07 3. M5E M6 M7A M7B .204 1..356 1.564 0.29E06 4.246 2.26E'05 4.29E'06 .204 1.04E05 1.. 768 1.939 0.000 0.58E06 4.26E05 M5D 4.58E06 MODEL ID VGS VDS VBS VTH VDSAT GM GDS GMB M5C P 4.711 0. 31E07 1.29E07 4.356 1.091 0.564 1. 0.08 1.939 0.356 1.29E06 3.711 0.60E08 1.98E05 1.31E07 3. 356 1.
and pchannel transistors have the following LEVEL=l model parameters: NMOS: VTO=2 PMOS: VTO=2 KP=20U KP=lOU RD=lOO RD=lOO CGSO=lP CGSO=lP If a finite output conductance in saturation needs to be modeled.21 CMOS Schmitt trigger circuit. Vo can be computed while Vi first increases from 0 to Vee and then decreases from Vee to O. . presented in Sec.21. with W = 10 /Lm and L = 10 /Lm.8 Compute the hysteresis characteristic of the CMOS Schmitt trigger (Jorgensen 1976) shown in Figure 10. The output voltage. The positive and negative thresholds of the hysteresis curve are set by the voltages at nodes 5 Figure 10.3. use LAMBDA 0. All transistors have the same geometry.350 10 CONVERGENCE ADVICE EXAMPLE 10. Solution The most appropriate analysis for computing the transfer characteristic is • DC. the DC sweep analysis. The n. 4.05 VI for both transistors. Compare the results from PSpice and SPICE2.
TRAN 1N 200N . except that the switching point occurs at Vi == Vst == Vee 2 . respectively. or 2 V.DC VI 0 12 0. ONLY A . The transistors M2 and M4 form a comparator.5) CMOS SCHMITT TRIGGER * * THIS CIRCUIT DIES IN .TRAN CAN PROVIDE * FOR IMPROVED CONVERGENCE LAMBDA > 0.MODEL N NMOS VTO=2 KP=20U *+ LAMBDA=0. with Vo at Vee. This value of V biases M3 off and M6 on. When Vi == Vs + VTOn.1 *. When Vi is 0. .MODEL P PMOS VTO=2 KP=10U *+ LAMBDA=O. THE HYSTERESIS.OPTION DEFL=10U DEFW=10U . * PSPICE SOURCE RAMPING CANNar SAVE IT. triggering regenerative switching and resulting in Vo going to 0 V and transistors M2 and M6 turning off. M4 starts turning on.22 SPICE input for CMOS Schmitt trigger. When Vi == VTOn. DC AROUND VT+ AND vr. Vst+ of the Schmitt trigger and is equal to Vst+ == 2 + VTOn Vee (10A) The same process takes place when Vi is varied from Vee to 0.OPTION ABSTOL=100N *. Ms turns on and the voltage at o node 5 is set to approximately ~ Vee. M1 2 1 3 2 P * M2 3 1 4 2 P M3 043 2 P M4 4 1 5 0 N M5 5 1 0 0 N M6 2 4 5 0 N . while the pchannel transistor pair MIM3 and the nchannel transistor pair MsM6 are voltage dividers.05 VCC 2 0 12 VI100 *VI 1 0 6 PWL 0 0 lOON 12 200N . which define the two thresholds. This point is the positive switching threshold. pchannel transistors Ml and M2 are turned on and nchannel transistors M4 and Ms are off.\VTOP\ (10.DC CONVERGENCE 351 and 3. CAPS IN MODEL.PROBE •END 0 CGsa=lP RD=100 RD=100 Figure 10. 05 CGsa=lP .
Vst+. After the addition of LAMBDA.23: it is the plot of Vo as a function of Vi. VI must be changed in the input circuit to include the ramping in time. The analysis of this circuit fails both in SPICE2 and PSpice. and the • TRAN line must be added in Figure 10. 12 10 8 > 6 ~ 6 4 2 o .22. PSpice however fails to converge when Vi reaches the positive switching threshold. Every SPICE program can complete this analysis.I 2 . at 200 ns. by sweeping Vi over time from 0 V to Vee and then back to 0 V. Models of higher LEVEL compute a finite conductance internally from process parameters.TRAN 1N 200N The solution is obtained over 200 ns.I .22: VI 1 0 0 PWL 0 0 lOON 12 200N 0 . A basic rule when simulating stacked CMOS transistors is to provide a finite output conductance in saturation for all transistors. In general.I . In order to demonstrate the importance of the charge storage in the circuit it is left for the reader as an exercise to remove CGSO from both •MODEL definitions in Figure 10. In the basic LEVEL=l model. The hysteresis of the Schmitt trigger is shown in Figure 10. with Vi rising to Vee at 100 ns and falling back to 0 at the end of the analysis interval.352 10 CONVERGENCE ADVICE The SPICE input circuit is listed in Figure 10. . The two switching points agree between the two programs and analyses. finite output conductance is modeled when a value is specified for LAMBDA in the •MODEL statement. any SPICE simulator can fail to converge in DC analysis when strong regenerative feedback is present in the circuit.22 and observe the result of the analysis.I ' I . and specifying LAMBDA is necessary only when the internal value must be overridden.I I I I I I o Figure 10.I . The approach to curing this problem is to find a timedomain solution rather than a DC solution. SPICE2 completes the DC transfer characteristic.23 4 VI' V 6 8 10 12 Hysteresis curve of the Schmitt trigger.
Figure 10. iterations. and PSpice exclusively uses the Gear algorithm. By default the time step is controlled by the truncation error in both programs.24 Diode rectifier circuit. convergence failure and accuracy. .24. EXAMPLE 10. an iterationcount timestep control is used in SPICE2.4 TIMEDOMAIN CONVERGENCE This section addresses the convergence problems that can occur during a transient analysis and the ways to overcome these problems. SPICE2 differs from SPICE3 by offering the user the choice of the timestep control method through the LVLTIM option. Ideal representations of semiconductor devices. In addition. Then perform a second analysis including the breakdown voltage for the two diodes. that is. As in the case of DC analysis. whereas PSpice does not offer this choice. The following example illustrates a TIME STEP TOO SMALL (TSTS) failure due to an incomplete model used to represent a diode in a fullwave rectifier circuit. corresponding to LVLTIM = 2 in SPICE2. BV = 100Y.9 Use SPICE to compute the timedomain response of the circuit shown in Figure 10. which doubles the time step at any time point when the program does not need more than 3 iterations to converge. models described only by the default parameters are often the cause of a transient analysis failure.TIMEDOMAIN CONVERGENCE 353 10. are addressed. SPICE2 and SPICE3 use trapezoidal integration by default. Through the METHOD option SPICE2 and SPICE3 offer the user the choice between trapezoidal and Gear variableorder integration. equal to 10. The most important causes for convergence failure are incomplete semiconductor model descriptions and lack of charge storage elements. and cuts it by 8 when convergence is not reached within ITL4. If LVLTIM = 1. the three SPICE versions used in this text differ slightly in the implementation of the integration algorithms and the control a user can exert on the timedomain solution. In the following examples both potential traps of timedomain solution. The model parameters of the diodes are IS = 1014 A and CiO = 10 pF.
8 > € > 0 ~ > 70V 0 10 20 30 40 50 60 Time.0 R2 4 0 10K C2 4 0 2UF IC=80 . Solution In the circuit of Figure 10.2MS 200MS UIC .24 the two diodes. which is the peak value and is reached when the voltage at node 3 reaches its lowest point.MODEL DIO D IS=1. driven by the two sinusoidal sources represent a fullwave rectifier.WIDTH OUT=80 • END Figure 10. The output voltage on capacitor C2 is initialized at 80 V.25 SPICE input for diode rectifier. and the voltage waveforms at nodes 3 and 4 are plotted in Figure 10.OPT ACCT .PLOT TRAN V(1) V(2) V(3) V(4) .354 10 CONVERGENCE ADVICE CHOKE CKT . D1 and D2.0E14 CJO=10PF . which is followed by an RLC lowpass filter.25. SPICE input file for this circuit is listed in Figure 10.FULL WAVE CHOKE INPUT VIN1 1 0 SIN(O 100 50) VIN2 2 0 SIN(O 100 50) Dl 1 3 DIO D2 2 3 DIO R1 3 0 10K L1 3 4 5.TRAN 0.26. ms Figure 10. The . .26 Rectifier waveforms for no BV.
which does not happen in reality and cannot be handled by the existing solution algorithms. In order to model the breakdown characteristic of the diode in the reverse region.27 Rectifier waveforms for BV = 100. In the absence of charge storage elements a circuit tends to switch in zero time. the value of parameter BV is added to the • MODEL line. Note that because of the diode reverse conduction the voltage at node 3 is clamped at 50 V.. Resimulation of the circuit results in a TSTS error in PSpice and a numerical exception in SPICE2. This issue is presented in the following example. . which limits the current when Dr or D2 operate in the breakdown region. TIMEDOMAIN CONVERGENCE 355 100V ~ > 100 100V 100 50V g > ff > 0 50V 0 10 20 30 40 Time.50 V.27. This example has illustrated a failure condition that can develop during the transient analysis because of an ideal model and improper circuit design.. D2 breaks down when V ( 1) reaches 50 V and V ( 2) reaches . MODEL line in Figure 10. and the two diodes could be destroyed in reality. . The solution to this problem is to add a parasitic series resistance.. When a breakdown characteristic is added to the diodes at 100 V. Analysis failure can also occur because of insufficient charge storage in a circuit. Because of the ideality of the diodes in the previous analysis only one is conducting at anyone time and proper current limiting is provided by the load circuit. to the diode model. In reality a careful sizing of the series resistors is necessary in order to limit the reverse current to the maximum value prescribed in the data book and avoid destruction of the diode.25 results in the waveforms V (3) and V (4) shown in Figure 10. Resimulation of the circuit with RS=l 00 added to the. ms ~ > 50 60 70 Figure 10. The addition of series resistance for limiting the current solved the problem. a current path exists from one signal source to the other through the series combination of the two backtoback diodes. RS.
In SPICE2 the analysis fails at t = 46.LS. MODEL statement.10 Simulate the behavior of the NMOS relaxation oscillator shown in Figure 10. The first observation is that the MOS transistors do not have any capacitances given in the • MODEL statement.23 J. s pointed out in Sec.28 NMOS relaxation oscillator.LS. Figure 10. 7 LEVELF=l V'IO=O. the resulting waveforms are shown in Figure 10. Note that the current source. is used only to kickstart the oscillations.28 (Kelessaglou and Pederson 1989) using SPICE.30. CGSO. SPICE computes the waveA form starting from 0 but saves only the results after t = 1. MODl and MOD2. The period and pulse width can be verified by hand using the GDS values printed in the operating point information for depletion devices Ms and Mg.4 ms.Lsto 1800 J. The model parameters for the enhancement and depletion transistors are LEVELF=l V'IO=O. 01 transistor) (depletion transistor) Solution The input description for SPICE is listed in Figure 10. KP=30U 7 KP=30U (enhancement LAMBDA=O.356 10 CONVERGENCE ADVICE EXAMPLE 10. Also note that the substrates of all transistors are connected at VEE = 9 V. hen the time step is reduced below w a minimum value set by the program to be 109 of the smaller of2 X TSTEP or TMAX. .29.2. It is necessary to correct the ideality of the MOSFET models by adding a gatesource capacitance. The transient response is requested to be displayed only from 1400 J. h. the transient analysis finishes successfully. After CGSO=l P is included in the. 6. to the two models.
and V (5) for the NMOS relaxation oscillator.PLOT TRAN V(5) V(l) V(4) .OPTION NOPAGE NOMOD LIMPTS=1001 ITL5=O . V (4) .Ol *+ CGSO==lP .END Figure 10.5 Time.MODEL MOD2 NMOS VTO=O.WIDI'H OUT=80 . 7 KP=30U *+ CGSO==lP .5 Figure 10.TIMEDOMAIN CONVERGENCE 357 MOS RELAXATION OSCILLATOR M1 2 1 0 6 MOD1 W=100U L=5U M2 4 5 0 6 MOD1 W=100U L=5U M3 3 2 2 6 MOD2 W=20U L=5U M4 3 4 4 6 MOD2 W=20U L=5U M5 3 1 1 6 MOD2 W=20U L=5U M6 1 0 0 6 MOD2 W=20U L=5U M7 3 5 5 6 MOD2 W=20U L=5U M8 5 0 0 6 MOD2 W=20U L=5U C1 2 5 lOOP C2 4 1 200P VEE 6 0 9 VDD 3 0 5 11 5 0 PULSE lOU 0 0 0 0 1 .MODEL MOm NMOS V'I'CPtO.7 KP=30U LAMBDA=O. V (2) .30 Waveforms V (1) .TRAN 2U 1800U 1400U .29 SPICE input for NMOS relaxation oscillator. .OP .0 1.OPTION ACCT ABSTOL=lN . ms 1. ~ > 0 > 5 ~ > 0 0.
especially when the circuit switches.PLOT TRAN I (VIN) * . the integration method should be changed to the secondorder Gear .1N 50N lOON . Whenever the simulated response of circuits displays oscillations that are not anticipated by design.5N lOON . This result can be explained only by the oscillatory nature of the trapezoidal integration method. For the first analysis use the default model for the diode with the following two additional parameters: RS=100 TT=40N The parameter TT is a finite transit time of the carriers in the neutral region of the diode.1N .6 when a voltage step from 5 V to 5 V is applied to the circuit. The trapezoidal method was seen to oscillate around the solution for values of the time step that are larger than a limit related to the time constant of the circuit. The waveform of the diode current resulting from the SPICE simulation is plotted in Figure 10.31.'IRAN . Current ringing around the value of zero can be noticed following the storage time.OPTION METHOD=GEAR MAXORD=2 . The following example illustrates ringing around the solution. during which the diode conducts in reverse. EXAMPLE 10.WIDTH OUT=80 • END * The SPICE input description is listed above.MODEL DMOD D RS=lOO + TI'=40N *+ CJO=lOP . Another important issue is the accuracy of the solution computed by the transient analysis. Solution DIODE SWITCHING D1 1 a DMOD VIN 1 0 PULSE 5 5 50N . and during this time the diode conducts in reverse direction. This behavior can be noticed in the computed response of a circuit.358 10 CONVERGENCE ADVICE The above examples have focused on the main causes for the failure of transient analysis and on how to overcome them. the effect of this parameter is that when a diode is switched off it takes a finite time to eliminate the carriers from the neutral region. which results in a smaller time step.11 Find the waveform of the current flowing through the diode D] in Figure 10. Several observations were made in the previous chapter on the stability of numerical integration algorithms. This numerical oscillation can be avoided by selecting the Gear algorithm or controlling the tolerances for a tighter control of the truncation error.
2). ns Figure 10. RS. A common cause for numerical oscillation is sudden changes in a circuit variable or in the model equations.TIMEDOMAIN CONVERGENCE 359 BOmA z ~ 0 40 BOmA TRAP z ~ 0 40 BOmA GEAR 2 z ~ 0 CJO+ TRAP 40 Time. which exhibits the expected behavior. a gradual decay of the current is expected with a time constant equal to CjRs. If this charge is modeled by specifying a value for the parameter CJO on the •MODEL line. Numerical ringing can . repeating the simulation yields the second waveform shown in Figure 10. The charge storage of the diode is incomplete without the depletion region charge (see Sec. It can be noticed that the current returns to zero with minimal numerical ringing.31. After the. In Sec. 6. addition of the above line to the input. A new simulation with CJO added and the default trapezoidal integration yields the third current waveform shown in Figure 10. The latter can also be caused by imperfections in the builtin analytical models in SPICE in addition to the absence of certain model parameters. which controls the number of points evaluated for a signal each period. The model of the diode used in this example is ideal except for the finite transit time. This last observation leads to the conclusion that the more complete the model. method by adding the following line to the SPICE input: •OPTION METHOD=GEAR MAXORD=2 The secondorder Gear method is characterized by numerical damping.4 the accuracy of the Fourier coefficients calculation was shown to depend on the value of TMAX. a few comments are necessary about the impact of transient analysis parameters TSTEP and TMAX on the accuracy of the result. 3. and series resistance. the more accurate and stable is the solution.31 Diode current computed with trapezoidal and Gear 2 integration methods and C]. Next. TT.31.
The SPICE input description and model parameters are listed in Figure 10. Sometimes the maximum time step must be set by the user in order to obtain an accurate solution. the more accurate the results.360 10 CONVERGENCE ADVICE RELTOL. The input voltage is ramped from 0 V to 10 V over 10 /LS. incorrectly displays ringing of 10 /LA after reaching the peak value.34. the more time points are computed. a smooth current waveform.33.34.32. The graphical solution of the inverter current in Figure 10. A value of 50 ns added to the • TRAN line in Figure 10. also be avoided by selecting smaller values for TMAX or reducing the relative tolerance In general. + Figure 10.33 also leads to a smooth waveform. EXAMPLE 10. The same current computed with the Gear 2 method is smooth and overlaps the trapezoidal solution in Figure 10. . Modeling the subthreshold current with parameter NFS added to the device specification has an effect on the result similar to that of the Gear integration. Solution Current flows through the inverter only for values of VIN from 1 V to 9 V. An alternate way to obtain the correct solution is to limit the maximum time step the program takes during the trapezoidal integration. computed with the default trapezoidal method.12 Simulate the current flowing through the CMOS inverter shown in Figure 10. that is.32 CMOS in verter circuit diagram.
2E+S NEFF=3 KF=1.46 CJSW=. '3.SE7 NSUB=.6SE+16 NSS=lE+11 + TPG=l XJ=.WIDTH OUT=80 .MODEL PMOS PMOS + LEVEL=2 VTO=.SE6 LD=.6E9 MJSW=.4E+S NEFF=3 KF=.8 CGSO=.TIMEDOMAIN CONVERGENCE 361 CMOS INVERTER 2 1 0 0 NMOS + L=10U W=20U AD=160P AS=160P PD=36U PS=36U VM 21 2 M2 21 1 3 3 PMOS + L=10U W=40U AD=1600P AS=1600P PD=216U PS=216U VIN 1 0 PWL 0 0 lOU 10 VDD 3 0 10 .TRAN 200N lOU 0 SON .0E32 AF=1.PLOT TRAN I(VM) .66E9 MJSW=.SE16 NSS=lE11 + TPG=l XJ=.2E+4 UEXP=.28E9 CGDO=.0 + NFS=lEll .l + VMAX=1.END * M1 * * * Figure 10.8 GAMMA=.28E9 CGBO=. ~s Figure 10.34 methods.49 CJSW=.18 + VMAX=.4E+4 UEXP=.S2U UO=230 UCRIT=S.7U LD=.28E9 CGBO=.SE7 NSUB=.38E6 UO=610 UCRIT=S.2SE9 + CJ=.0 + NFS=lEll *. CMOS inverter current computed with trapezoidal and Gear 2 integration .TRAN 200N lOU .8 CGSO=.4E3 MJ=.2SE9 + CJ=.69 PB=.MODEL NMOS NMOS + LEVEL=2 VTO=.2E32 AF=1.3E3 MJ=.33 SPICE description of CMOS inverter.28E9 CGDO=. ~ ~ 300 100 o Time.9 GAMMA=.24 TOX=.26 TOX=.6 PB=.
trapezoidal integration. 10. Solution A first approach for simulating this circuit is to replace the crystal with an equivalent circuit with a reduced Q that allows for a rapid buildup of oscillations.8 H Rs = 600 n Co = 7 pF Use the following model parameters for the n. the maximum allowed integration step. An important aid for initiating oscillations in a simulator is either a single pulse at the input of the amplifier block or the initialization of the charge storage elements close to the steadystate values reached during oscillations. in order to control the accuracy of the trapezoidal method. The circuit drawing tal.5 10. The following example provides insight into the analysis of a Pierce crystal oscillator. EXAMPLE 10. Therefore. and Rs.362 10 CONVERGENCE ADVICE PSpice does not provide a choice in integration methods.47 fF Lx = 0. which points to the Gear method. 02 LAMBDA=0. it would theoretically take a number of periods on the same order of magnitude to reach steady state. but seemingly not in PSpice.and pchannel MOSFETs: NMOS: VTO=l PMOS: VTO=l KP=20U KP=lOU LAMBDA=O. Cx. It is impractical to simulate a circuit for so many cycles.1 CIRCUITSPECIFIC CONVERGENCE Oscillators The analysis of oscillators can represent a challenge for the user of circuit simulation. The crystal has a in color television. The crystal has .5795 MHz. Lx. In the previous chapter and in the previous section it was shown that the Gear integration method has a damping effect on oscillations. Another possible difficulty in simulating oscillators is related to the numerical integration methods. Because of the high Q.5. of the order of tens of thousands. It may be necessary to set a value of TMAX. Q.13 Verify the behavior of the CMOS Pierce SPICE2 and PSpice. common equivalent circuit parameters: Cx = 2. The results of PSpice simulations for the above circuits show a certain level of damping. should always be used when simulating oscillators. and has the following crystal oscillator shown in Figure 10.02 An attempt to run the circuit as is or using a startup pulse does not produce the expected oscillations. Co. As described in Example 6.35 using includes the equivalent schematic of the crysresonant frequency of 3.3. The most representative example for the difficulty encountered in simulating oscillators is a crystal oscillator. the number of periods for oscillations to build up is inversely proportional to the quality factor of the resonant circuit. the default in SPICE2 and SPICE3.
35 oscillator. wo. Cx.CIRCUITSPECIFIC CONVERGENCE 363 Figure 10. At frequencies below of the crystal is capacitive.6) This frequency. wo.w}Cl Cz/ (Cl + Cz) = 0. ws. Is and Ip.18 mH (10. of the equivalent circuit is given by Is the reactance Wo = (10. whereas above Is the reactance is inductive and Lx. and Co can be substituted by an effective inductance. The oscillation frequency. Leff. r Pierce CMOS crystal a series and a parallel resonant frequency.7) . leading to the following value for Leff: L _1 eff . is very close to the crystal resonant frequency. respectively.
which provides a 0.5 V.OP .364 10 CONVERGENCE ADVICE The new equivalent resonant circuit has Q = 7. and 0. node 2.MODEL * SOURCE PULSE 0 10M . the previous results can help in this task.36. The • TRAN line requests the results to be saved only after 45 fJS.SUBCKT XTAL 1 2 LEFF 1 3 . when the steady state should have been reached.5 V with an amplitude of 1.PLOT TRAN V(2) V(3) .1N 1 1 NMOS NMOS VTO=l KP=20U LAMBDA=O.75 V at the output of the gain block. Cx. which is considerably smaller than the original value. PIERCE XTAL OSCILLATOR WI CMOS . Co.75 V across the crystal with a period of 280 ns.1 ns pulse for triggering the oscillations. after approximately 150 cycles.ENDS XTAL * * KICKING * VKICK 70 * . The same results are obtained with both SPICE2 and PSpice. VKICK.3. . it is necessary to initialize the charge storage elements as close as possible to the steadystate values. The SPICE input description is listed below. 02 . The crystal equivalent circuit. woo Note that the SPICE circuit description includes a voltage source. Once the correct operatiori of the circuit has been verified. corresponding to the resonant frequency. As shown in Sec. The circuit sustains oscillations centered around 2.* XTAL Xl 3 5 XTAL .1N . Assume that at t = 0+ both V (3) and V (5) are at 2.END Resimulation of the circuit results in the waveforms V (2) and V (3) shown in Figure 10.TRAN 10N 50U 45U 10N .18M RS 3 2 600 RP 1 2 22MEG . 6.OPTION LIMPTS=10000 ITL5=0 M1 M2 RL C1 C2 VDD * 2 2 2 5 3 0 0 NMOS W=40U 1 1 PMOS W=80U 10K 22P 22P 1 0 5 3 3 5 0 7 L=10U L=10U * * .1N . the circuit can be simulated with the real crystal. must be replaced by Left. Lx.02 . that is. a • SUBCKT block represents the crystal.MODEL PMOS PMOS VTO=l KP=10U LAMBDA=0.
Lejf. Lejf.02 (OLD) BECAUSE IT USES TRAP * * * * THIS CKT OSCILLATES . such as Lx. Therefore. the initial current through Lx and Co should approximate the value of the current amplitude through the equivalent crystal. The results of the simulation using the equivalent inductor.5 .OPTION LIMPT8=10000 2 2 2 5 3 3 3 5 0 0 0 0 1 1 10K 22P 22P NMOS w=40U PMOS W=80U IC=2.5 IC=2. PIERCE XTAL OSCILLATOR WI CMOS ONLY PSPICE ITL5=0 L=10U . instead of the crystal can be used for guidance.36 Waveforms V (2) and V ( 3) for oscillator with reduced Q. Note that it is important to initialize the state of one of the crystal components. which corresponds to the maximum current in the inductor Lx..lLS Figure 10. in order to achieve steadystate oscillations in the solution. For a rigorous derivation of the oscillation amplitude consult the text by Pederson and Mayaram (1990). L=10U 3. . M1 M2 RL C1 C2 VDD 1 0 5 * * * XTAL .CIRCUITSPECIFIC CONVERGENCE 365 > E g ai Time.
02 * .47FF eo 1 2 7PF RS 4 2 600 RP 1 2 220K .366 10 CONVERGENCE ADVICE Xl 3 5 XTAL .18M LX 1 3 0.6M ex 3 4 2.8 IC=0.37 and are identical to the previous solution.37 Waveforms V ( 2) and V ( 3) for oscillator with crystal. l!S Figure 10.PLOT TRAN V(2) V(3) .MODEL PMOS PMOS VTO=l KP=10U LAMBDA=0.OP . and the oscillations are sustained for the 200 cycles simulated.END The new SPICE input is shown above. The result > ai ~ g Time. .SUBeKT XTAL 1 2 * LEFF 3 6 .TRAN ION sou 45U ION Ule . The results are shown in Figure 10. The estimated steady state is verified by the analysis performed in SPICE2 or SPICE3. note that the initial pulse is omitted and the keyword UIC is used in the • TRAN statement in order to start the analysis at steady state. 02 .ENDS XTAL * .MODEL NMOS NMOS VTO=l KP=20U LAMBDA=O.
as demonstrated by Example 10.2 BJT versus MOSFET Specifics MOSFET circuits have more convergence problems than bipolar circuits because of a number of differences between the two devices types. Second.4 demonstrated thatthe initialization of two protective devices as OFF improves the convergence .. the physical structures of the two devices are different. selfconductance of the gate)s therefore zero in DC. Tbe continuity of the conductance.. First. A smaller number of iterations has been noticed for analog (linear) bipolar circuits as compared to digital (logic) bipolar circuits because BJTs are initialized 'as' cond~cting in SPICE. generally.mode. independently of region of operation and analysis.MOSFETs are initialized turned off. MOSFETs are initialized with Vcs = VTO. the EbersMoll or Gummel. decaying. and Ko 1985. The. whicJ. Vladimirescu and Liu 1981).. There are differences in the operating points in which the program initializes the two types of devices and in the way new operating points. An important difference between BJTs and MOSFETs in the first iteration is that by default the former are initialized conducting whereas. The gate terminal of a MOSFET is insulated. By contrast. Scharfetter.nulations have different levels of continuity for the equivalent conductance at the tran~i!ion points. summarized}n Appendix A and described in more detail in the references (Antognetti and Massobrio 1988. and the difficulty with MOSFETs is that the actual threshold voltage"VTH. t". in contrast with digital circuits. VTO.1. The default initi~lization oLtransistors has a different impact on convergence depending on the operation of the circuit. the generality of analytical models used in SPICE to describe the two devices is not the same. The explanation can be found in the mode of operation of analog circuits. model parameterNFS.Poon formulation for the BJT transistor applies to all regions of operation. Only MOSFET devices with subthreshold current. are selected at each iteration.CIRCUITSPECIFIC CONVERGENCE 367 of a PSpice analysis for this circuit shows the oscillations explained by the use 'of Gear integration. ave an important percentage of the 'devices turned h off. Experiments in the SPICE code that initialized all MOSFETs in the conduction state have proven to . The differel}r fo. This is one example where convergence can be improved by changing model parameters. Sheu.n. the ilpplementation details in SPICE also affect convergence. often leading to illconditioned circuit matrices. that is. is usually increased by backgate bias to a higher value than the zerobias threshold'voltage. which have the majority of the transistors turned on. and subsequently to the failure of SPICE to find a solution. is Important for the convergence of the iterative process. This secondorder effect is supported only by the higherlevel models. the MOSFETmodels combine different ~quations t~describe distinct regions of operations and various secondorder effects. are initially in the conduction state.icontinuous current flows in or out of the base terminal of a bipolar transistor.5. Whereas. which could be 10. Example 10.arid leads to"a sol~ti(:m without source ramping. which is the first deriv'ative of the funttion.1. Third. it is an open circuit in DC.
10. Transient ramping of the CMOS differential amplifier in Fig.14 Find the DC operating point of the circuit shown in Figure 10.368 10 CONVERGENCE ADVICE speed up the convergence of analog circuits.. the conversion from double.to singleended output is achieved by PMOS transistors M6 through M9. and at the limit between saturation and linear region. and M6M7' Based on the knowledge acquired in Chap. on the other hand. Several options can be modified for this circuit.. especially those with highimpedance nodes. all transistors are biased very close to the threshold voltage.39 fails in SPICE2 but succeeds in PSpice and SPICE3 after source ramping. one can see the difficulty associated with solving the modified nodal equations when a number of nodes are of very low conductance. The state of this circuit is set by connecting the appropriate bias transistors Mll through M14 to the gates of the transistor Ms. When ramping methods fail for this type of difficult circuit. This approach to biasing is common in analog CMOS circuits. Based on the observation of the condition of the circuit matrix. Solution This circuit is a differential amplifier in a unityfeedback loop. If the supplies are ramped for part of the time interval.38 using the LEVEL=2 parameters given in the SPICE description. which are activated only in transient analysis in conjunction with the UIC option. the DC value should be preserved for the rest of the timedomain analysis in order to allow the circuit to settle. The importance of initialization and device specifics for the convergence of MOS analog circuits. A timedomain analysis of an MOS circuit has the additional advantage of a wellconditioned matrix because charge storage elements provide finite conductance at the gates of MOSFETs. A DC solution is avoided by using the UIC keyword on the • THAN line. often present in cascode loads. running a transient analysis while ramping the supplies from 0 to the DC value or leaving them unchanged may lead to a solution. VBSO. The attempt to find the DC operating point of the circuit as it is represented by the input description in Figure 10. It is important to note that SPICE2. and the load transistor pairs M3M4. a first approach is to tighten the pivot selection criterion . Vcso. and additionally. nodes 3 and 4 have very high impedances because of the cascode connection. The user can access initialization through the device initial conditions. on one hand.39 is performed when the • THAN and • PRINT lines are activated. A transient analysis also fails in SPICE2 for this circuit. encounters problems in the matrix solution: the messages PIVOT CHANGE ON THE FLY and *ERROR*: MAXIMUM ENTRY . EXAMPLE 10. can be exemplified by a CMOS differential amplifier (Senderowicz 1991). IC = VDSO. Addition of the option ITL6=40 to the SPICE2 input does not help for this circuit. 9. which provides more feedback related to a solution failure. the differential pair transistor M2. IS LESS THAN PIVTOL can be found in the output file.
Voo CD ~ )17 ~ )16 ~ )Is @ o o o ~ } /10 ~ CD Vss Figure 10.C . W Q'I I.38 CMOS differential amplifier with cascode load.
M12 AND M11 * W=120U 10 1 1 P M11 10 W=120U 2 2 N M12 8 8 2 2 N W=120U M13 6 6 2 N W=120U 7 7 2 M14 200U 110 10 2 1 8 200U 18 200U 16 1 6 17 1 7 400U L=1.0 VFF 3 5 2.0E6 RSH=200 + NFS=100E+9 VMAX=20.2U L=1.0E10 CGDO=2.6U L=4.AMPLIFIER CMOS DIFFERENTIAL * W=120U 2 N M1 11 5 9 2 N W=120U M2 12 6 9 W=120U M3 8 11 2 N 3 12 2 N W=120U M4 4 8 7 2 N W=240U M5 9 2 w=120U 10 13 1 P M6 3 W=120U 14 1 P M7 4 10 W=120U M8 13 4 1 1 P W=120U 1 1 P M9 14 4 * * BIAS CIRCUIT * VOLTAGES AT NODES 6.WIDTH * * + + + + + + N_CHANNEL TRANSISTOR.0E10 CGBO=3.PRINT TRAN V(7) V(8) V(9) V(10) V(ll) *.0 0 100U ION 100U 200U) VSS 2 0 0.O 5.9 DELTA=l + CJ=400E6 MJ=300E3 CJSW=2.8U L=1.2U L=1.39 SPICE input for CMOS differential amplifier with cascode load.2U AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AD=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N AS=2N PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PD=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U PS=12U ARE SUPPLIED BY L=4.2U L=1.l + XJ=lE10 PB=0.OPT ABSTOL=lU *.0E10 CGDO=2.2U AD=2N AD=2N AD=2N AD=2N AS=2N AS=2N AS=2N AS=2N PD=12U PD=12U PD=12U PD=12U PS=12U PS=12U PS=12U PS=12U VDD 1 0 5.00E9 MJSW=1.END 370 Figure 10.8 JS=100.0 *+ PULSE(O. 8 AND 10 * M13.0E10 FC=0.OPT ITL6=40 *.0E9 + NSUB=2.PRINT TRAN V(12) V(13) V(14) * * * .2U L=1.2U L=1.0E+16 UCRIT=2E+4 UEXP=O.0 + CGS0=2.0E+16 UCRIT=2E+4 UEXP=O. SANITIZED MODELS * .00E+3 NEFF=.OP .2U L=1.2U L=1.000 TOX=25.0E6 RSH=100 NFS=200E+9 VMAX=60E+3 NEFF=2.5 * .TRAN IUS 200US UIC *.8U L=9.0 0 100U ION 100U 200U) OUT=80 .5 DELTA=3 CJ=400E6 MJ=300E3 CJSW=2.0 *+ PULSE(O.00E9'MJSW=1.O 2.000 TOX=25.OPT ACCT *.5 P_CHANNEL TRANSISTOR * * * .8 JS=100.l XJ=lE10 LD=100E9 PB=0.MODEL P PMOS LEVEL=2 + U0=200 VTO=700E3 TPG=1.2U L=1.MODEL N NMOS LEVEL=2 U0=600 VTO=700E3 TPG=1.0 CGS0=2.OPT PIVREL=lE2 *.0E9 NSUB=5. 7.PRINT TRAN V(2) V(3) V(4) V(5) V(6) *.0EIO FC=0.OPT ITL4=100 *. .0E10 CGB0=3. M14.
ABSTOL. . MOS analog circuits are biased with VGS close to VTO for maximum gain and at the edge of saturation for maximum output signal swing (Gray & Meyer 1985). the DC operating point is obtained for this circuit in only 8 iterations.54 = 0. linear and saturation regions.28 = 1.41. the absolute current tolerance.29 = 3.OPTIONS ABS'IOL=1U These two options contribute to a successful timedomain solution in SPICE2. the node voltages obtained from the openloop circuit can be used in a • NODESET statement to initialize the closedloop amplifier.19 = 3. One can verify the bias point of the transistors in this circuit and understand that the convergence difficulty is caused by the proximity of the operating points to the limits of the subthreshold conduction. because of the possible operation near threshold of some transistors. can be raised: .1 = 1. .63 = 4. The voltages at the circuit nodes are listed for the last 10 time points in Figure 10. VTH represents the bias.64 + + + + + V(8) V(9) V(10) V(ll) V(12) V(13) V(14) When the node voltages are initialized. An alternate way to find a solution for this circuit and for amplifiers in general is to cut the feedback loop and find a DC solution of the openloop amplifier. The solution and the operating point information are listed in Figure 10.39 = 4. VTO. specified in the •MODEL statement.32 = 0.NODESET + + V(4) + V(5) + V(6) + + + V(7) V(3) = 3.and geometryadjusted values of the zerobias threshold voltages.39 = 0. an average value is chosen to initialize the node voltages with a •NODESET statement. Then.71 = 1. The openloop solution for this circuit is nontrivial.40.29 = 1.OPTIONS PIVREL=lE2 Second.CIRCUITSPECIFIC CONVERGENCE 371 by increasing the value of PIVREL by including the following statement: .
288E+00 3.290E+00 V(4) 3. Figure 10.960E04 1.980E04 1.283E+00 1.372 10 CONVERGENCE ADVICE *******03/07/93 ******** SPICE 2G.289E+00 3.877E01 1.102E+00 1.102E+00 1.633E+00 4.546E+00 1.327E+00 3.635E+00 Transient solution of CMOS differential amplifier.313E+00 3.000 DEG C *********************************************************************** TIME 1.323E+00 3.896E01 1.323E+00 3.903E01 1.950E.711E+00 3.970E04 1.315E+00 3.282E+00 1.000E04 TIME 1.631E+00 4.883E01 3.980E04 1.710E+00 3. .909E01 V(8) 1.893E01 1.910E04 1.630E+00 4.990E04 2.102E+00 1.288E+00 1.920E04 1.285E+00 1.540E+00 1.821E01 3.824E01 3.529E+00 1.844E01 3.920E04 1.04 1.907E01 3.000E04 V(3) 3.712E+OO 3.283E+00 1.102E+00 1.906E01 3.287E+00 3.876E01 3.852E01 3.708E+00 3.940E04 1.320E+00 3.6 3/15/83********20:18:56***** CMOS DIFFERENTIAL AMPLIFIER **** TRANSIENT ANALYSIS TEMPERATURE = 27.940E04 1.629E+00 4.850E01 3.546E+00 V(12) 3.970E04 1.645E+00 4.904E01 V(13) 4.542E+00 1.636E+00 4.950E04 1.867E01 3.874E01 3.287E+00 1.284E+00 1.537E+00 1.990E04 2.960E04 1.312E+00 V(14) 4.284E+00 1.541E+00 1.709E+00 3.286E+00 1.289E+00 1.533E+00 1.287E+00 1.317E+00 3.876E01 1.980E04 1.102E+00 V(ll) 3.930E04 1.538E+00 1.319E+00 3.288E+00 1.791E01 3.626E+00 V(lO) 3.290E+00 V(6) 1.882E01 3.645E+00 4.711E+00 3.883E01 1.281E+00 1.640E+00 4.920E04 1.316E+00 3.930E04 1.950E04 1.910E04 1.990E04 2.940E04 1.712E+00 V(5) 1.288E+00 3.286E+00 3.866E01 1.626E+00 4.930E04 1.853E01 3.817E0l 3.282E+00 1.632E+00 4.707E+00 3.642E+00 4.288E+00 3.970E04 1.638E+00 4.708E+00 3..102E+00 1.288E+00 1.914E01 3.285E+00 1.890E01 1.286E+00 TIME 1.000E04 ..649E+00 4.639E+00 4.939E01 3.910E04 1.102E+00 1.635E+00 4.642E+00 4.639E+00 4.102E+00 1.886E01 1.942E01 V(9) 1.40 V(7) 1.102E+00 1.286E+00 1.897E01 3.635E+00 4.287E+00 3.534E+00 1.710E+00 3.285E+00 3.285E+00 1.102E+00 1.286E+00 3.960E04 1.
The .2872 1.3878 VOLTAGE SOURCE CURRENTS NAME VDD VSS VFF CURRENT 1. some analog.2831 3.0000 1.0000 1.1884 4.67D03 WATTS (continued on next page) TOTAL POWER DISSIPATION Figure 10. the more complex is its behavior. Specifying the state of transistors that are OFF also helps.6421 NODE 3) 7) 11) VOLTAGE 3. The large number of transistors operate in very different conditions depending on the functions of the blocks. Key nodes can be expressed as interface nodes and initialized. For most common purposes a circuit with more than 100 semiconductor devices can be considered a large circuit. This is necessary since • NODESET and • IC cannot initialize nodes internal to a subcircuit. linear or nonlinear. The difficulty of finding a solution is directly related to the number of nonlinear elements.467D03 1.5. the 100 iterations of the default ITLl are often insufficient for finding a DC solution. It is a good practice to describe a large circuit hierarchically. and some digital. the component functional blocks should be characterized individually.CONVERGENCE OF LARGE CIRCUITS 373 10. .467D03 O.6327 NODE 2) 6) 10) 14) VOLTAGE 0. ITLl should be increased to 300 to 500 but not *******03/08/93 ******** SPICE 2G.000 DEG C *********************************************************************** NODE 1) 5) 9) 13) VOLTAGE 5. SPICE requires considerable more iterations than for a few transistors.3 CONVERGENCE OF LARGE CIRCUITS The larger a circuit.5372 0.3848 NODE 4) 8) 12) VOLTAGE 3. Because of the size of the circuit.41 DC operating point computed after initialization.7093 1. or cells.2872 0. With no prior knowledge of the expected function.6 3/15/83********21:30:55***** CMOS DIFFERENTIAL AMPLIFIER **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.1019 0. A large circuit usually consists of a number of individual functional blocks.OOODtOO 3. SUBCKT definition capability of SPKE introduced in Chap.3196 4. 7 should be used for this purpose. Before the entire circuit is stimulated. which perform different functions.
OOE+OO M14 N 4.40E14 2.67E04 2.08E04 4.11E13 1.82E13 5.40E14 2.000 0.291 0.OOE+OO O.000 0.16E03 2.40E14 2.40E14 3.11E13 8.96E13 4.82E03 1.40E14 2.40E14 2.751 0.388 0.04E03 6.762 0.OOE+OO O.40E14 3.314 0.02E03 3.OOE+OO O.60E16 1.40E14 2.OOE+OO O.933 1.76E04 6.188 0.313 1.40E14 2.55E05 1.199 0.188 0.152 3.348 5.18E13 8.OOE+OO O.32E13 7.322 2.932 0.44E15 2.11E13 O.46E06 1.82E15 1.000 0.82E03 9.OOE+OO M8 MODEL 10 MODEL 10 VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGDOVL CGBOVL CGS CGD CGB M4 M3 N N 2.80E14 2.40E14 2.65E13 7.32E04 1.33E13 1.00E16 1.00E04 2.18E13 2.90E13 6.00E04 2.751 0.156 1.857 0.11E13 8.01E13 1.346 0.47E04 2.931 0.64E04 7.23E13 7.OOE+OO O.OOE+OO O.170 0.04E12 5.367 0.35E04 1.361 0.680 1.00E04 1.OOE+OO M7 M6 M5 P P N 4.09E13 7.20E14 9.40E14 2.40E14 2.23E04 6.40E14 2.188 0.00E16 3.37E03 9.40E14 2.60E16 1.172 1.OOE+OO M13 M12 Mll M9 N N P P 2.08E13 4.348 5.202 1.23E04 7.000 0.845 0.13E06 2.79E13 6.000 DEG C *********************************************************************** **** MOSFETS M2 M1 N N 2.60E16 3.00E04 1.31E13 7.21E15 O.OOE+OO O.89E04 6.31E13 8.902 0.000 0.154 0.OOE+OO Figure 10.40E14 2.10E13 1.42E13 5.37E04 5.OOE+OO O.095 1.24E13 4.38E15 1.22E13 7.00E16 1.OOE+OO O.11E13 O.41 (continued) 374 .35E04 2.40E14 4.32E04 1.03E06 1.33E13 1.845 0.88E04 2.OOE+OO O.87E14 O.149 1.30E05 4.680 0.69E04 6.291 1.65E13 2.09E13 8.48E04 4.40E14 2.859 0.40E14 2.25E04 4.102 0.14E04 3.22E13 2.756 0.283 1.OOE+OO O.367 0.537 1.40E14 3.283 1.23E03 7.19E03 1.36E04 7.OOE+OO O.35E04 2.000 0.52E06 7.80E14 2.13E04 2.677 0.358 0.322 1.13E13 8.196 0.08E04 4.00E16 3.102 0.20E14 O.14E06 8.70E04 9.40E14 2.81E13 7.13E13 O.32E04 1.102 1.OOE+OO O.099 0.751 0.40E14 3.06E05 6.59E04 1.09E13 2.OOE+OO VGS VDS VBS VTH VDSAT GM GDS GMB CBD CBS CGSOVL CGDOVL CGBOVL CGS CGD CGB P 2.00E16 1.35E04 2.32E04 2.53E04 7.385 0.30E13 1.46E04 7.60E16 2.84E04 5.11E13 2.306 0.40E13 8.000 0.757 0.765 0.537 1.26E04 5.40E14 3.00E16 3.29E13 5.40E14 2.40E14 3.80E13 5.6 3/15/83********21:30:55***** CMOS DIFFERENTIAL AMPLIFIER **** OPERATING POINT INFORMATION TEMPERATURE = 27.358 0.*******03/08/93 ******** SPICE 2G.540 0.98E04 1.29E13 3.207 2.10E13 1.OOE+OO O.
SUMMARY 375 beyond. Another approach that may help large circuits converge is . For large circuits it can be useful'to initialize all nodes once a solution'is available and reduce the time for subsequent DC solutions. '[he r:esults can then be used either to find an 0p. element values. In other situations a simpler model can lead to better convergence. . however. for example.!te values. Initialization of node voltages and cutoff semiconductor devices can be of help in finding a solution. 3. Source ramping offers a better chance of success than increasing ITLl above the limit of 500 . If automatic convergence algorithms fail. number is low. Note that only tlie MODEL option is turned on by default in most SPICE versions. respectively. the number of iterations taken at each step should be increased.iterations. a transient analysis with ure and all supplies ramped up from zero should help. the NODE. Once a solution is available. and ABSTOL c.?rating point or to initialize another. If all the above attempts fail. PSpice and SPICE3 automatically exercise the ramping methods if the main iterative process fails.3 . SPICE2. 1. needs to be directed to ~pply source ramping by setting ITL6 to a value of 20 to 1OO.transient analysis. LIST and MODEL options provide useful information on connectivity. RELTOL can be increased to 5 X 10. The next step toward finding a solution is to add or delete certain physical effects of the model.6 SUMMARY Based on the information on the solution algorithms of the previous chapter.to relax the tolerances RELTOL and ABSTOL. 4. Examples in this chapter have demonstrated the importance of finite output conductance in saturation and subthreshold conduction for MOS circuits. try first increasing the maximum number of iterations ITLI to 300 to 500. 10. The following is the sequence of actions to undertake when SPICE fails to find the DC solution.7. see Example 10. it can be used for initialization and the tolerances can be tightened back for more rigorous results. 2. If the circuit specification is correct and SPICE does not converge. the probability for a circuit to converge beyond this. Carefully check the circuit connectivity and elem~nt values for possible specification errors and typographical errors.anbe made as high as six orders of magnitude below the highest current of a single device in the circuit. and model parameters.themaxiIhum number of iterations allowed for anyone set of source values. a number of approaches and simulator option parameters for overcoming convergence failure have been presented in this chapter. The time interval should be chosen so that elements with the slowest time constants can settle to steadyst. increase ITL2 in PSpice from the default of 20to 40 or more.
can also lead to a solution. 3. ITIA. however. 7. Check model parameters that can produce unrealistic conductance values. Relax the tolerances ABSTOL and RELTOL. this luxury. such as 103. The solution of largegain blocks connected in a feedback loop can be found by opening the loop and then using the results to initialize the closedloop circuit. 2. GMIN. 4.NODESET initialization to the simulator of choice. such as FC. Check the circuit for charge storage.3. ABSTOL can easily be raised to 1 nA for MOSFETs. Use a different integration method if available. Reduce. If more than one SPICE simulator is available. rather than relax. Also check the circuit for an abnormally high range of values for a single component type.2 for the underlying explanation. to try to solve a difit can be transferred is usually linked to a Not many users have METHOD=GEAR with 8. 8.2. . 1. Reduce the maximum allowed time step. Disable control of truncation error by setting TRTOL to a large value.2). which insures a finite transition time from state to state. Bypass is sometimes the culprit in a failed timedomain analysis. 9. In general. All supplies should be ramped from zero to the final value for part of the interval and then held constant for the nodes to settle. 5. RELTOL and ABSTOL. Increase the number of iterations. allowed at each time point to 40 or higher from the default of 10. ABSTOL should not be more than 9 orders of magnitude smaller than the largest current of a nonlinear device. SPICE2 grants the option of setting LVLTlM=l. MAXORD=2orMAXORD=3 is recommended. which is equivalent to setting TRTOL to a very large value. the ratio of the largest to the smallest value of a component type should preferably be within nine orders of magnitude. The time step in this situation is controlled by the iteration count. as a . See Sec. RELTOL. it is useful ficult circuit with another version.376 10 CONVERGENCE ADVICE 5. orders of magnitude. TMAX. The protective parallel junction conductance. Once a solution is available. 7. which graphical postprocessing package for documentation purposes. Relaxation of the convergence tolerances. A very reliable method for finding a DC solution is to run a transient analysis with the UlC option. a value of 104 or smaller can force a smaller time step and avoid the bypass of a seemingly inactive device (see Sec. 6. 9. can be increased 2 or 3 6. The following steps should be taken. Convergence failure can occur not only in a DC analysis but also in the timedomain solution.
Physics and Technology of Semiconductor Devices.. S. New York: John Wiley & Sons. K. Univ. D.. and K.. T. Vladimirescu. S. Sheu. Senderowicz. 1981. Berkeley. Meyer. Pederson. M. Sze. CMOS Schmitt Trigger. NECTARA knowledgebased environment to enhance SPICE. 1981. SC24 (April) 452457. Pederson.. and T. Personal communication. P. R. 1967. P.984. R. Mayaram. Integrated Circuits for Communications. of California.S. S. Berkeley. Muller. Kamins. 1990. M. A. 1988. 1976. Scharfetter. and R. 1985. New York: McGrawHill. Analysis and Design of Analog Integrated Circuits. and P. O. IEEE Journal of SolidState Circuits. Kelessoglou. B. Massobrio. L.. New York: John Wiley & Sons. Ko 1985. SPICE2 implementation of BSIM. The simulation of MOS integrated circuits using SPICE2. and G. 1991. (October 5). ERL Memo UCB/ERL M8017 (March). ERL Memo UCB/ERL M85/42 (May). Boston: Kluwer Academic. J. Physics of Semiconductor Devices. and S. New York: John Wiley & Sons. G. D.SUMMARY 377 REFERENCES Antognetti. Semiconductor Device Modeling with SPICE. Univ. New York: John Wiley & Sons. A. I. of California.O. Liu. D. 1977. Gray. Device Electronics for Integrated Circuits. U.703.. . 1989. Grove. and D. J. Patent 3. Jorgensen.
APPENDIX A SEMICONDUCTORDEVICE MODELS A.11 Si 0.IN 2P 0.5 100 O.6 0.l Name IS N RS TT CJO VJ M Diode Model Parameters Parameter Units A Default 1 x 1014 1 0 0 0 1 0.11 3 V A 00 Example lE16 1.1 DIODE Table A.5 0 1 area 378 .67 Ge 3 pn 2Sbd 40 lOU Seale Factor area l/area area EG XTI BV IBV FC KF Saturation current Emission coefficient Ohmic resistance Transit time Zerobias junction capacitance Junction potential Grading coefficient Activation energy Is temperature exponent n s F V eV AF Breakdown voltage Current at breakdown voltage Coefficient for forwardbiased depletion capacitance formula Flicker noise coefficient Flicker noise exponent 1 X 103 0.5 1.69 Sbd 0.33 1.
DIODE 379 A. <p](T). equal to TNOM.I.5) C](T2) = C](Td { 1 + M [400 1O6(T2  T1)  <PAT ~]ZT ~](Td ]) (A 6) Model parameters are assumed to be specified at the reference temperature. TNOM can be modified with a • OPTIONS statement.02 X 10.eV /K)T g (1108 K) + T X (A.l. .1) + VDGMIN ID = for VD 2: NkT 5q (Al) IS + VDGMIN IS(eq(Bv+vD)/kT . CIO. Transient.2 Temperature Effects Model parameters IS.5q for VD < BV TTdID + CIO dVD (1 .1) . VI. T1.IBV NkT for BV < VD . which defaults to 300 K.l. { dID TT dVD + (1 _ CIO FC)I+M [1 _ FC(1 + M ) + MVD] VI ~ V FC lor D 2: . IS(eqVD/NkT .l DC. and EG vary with temperature according to the following functions of temperature. VI (A2) A. and AC Models All SPICE2 and SPICE3 model parameters are listed in Table A. C](T) and Eg(T): (A3) (A 4) 4 2 E (T) g = E (0) _ (7. Is(T).VD/VIO)M CD = ~ V FC VI lor D < .
RS.5 1 1 00 00 area area V A A n n n n A s V A degrees s F V F V 0 1.33 area lOON 2P 0. VBe) starts Excess phase at f = 1/ (2nTF) Reverse transit time BE zerobias junction capacitance BE builtin potential BE grading coefficient BC zerobias junction capacitance BC builtin potential BC grading coefficient 1016 0 1.33 2P 0.33 0 0.75 0.2 BIPOLAR JUNCTION Table A.1 lE13 2 3 1.380 APPENDIX A SEMICONDUCTORDEVICE MODELS A.l .f+fI KFl~F t::. and the shot and flicker noise of the pn junction: '2 lRS = 4kTt::.6 0.f RS (A.1 IN Scale Factor area Saturation current Forward current gain Forward emission coefficient Forward Early voltage {3F highcurrent rolloff comer BE junction leakage current BE junction leakage emission coefficient Reverse current gain Reverse emission coefficient Reverse Early voltage (3R highcurrent rolloff comer BC junction leakage current BC junction leakage emission coefficient Collector resistance Emitter resistance Zerobias base resistance Minimum base resistance at high current Current where base resistance falls nalfway to its minimum value Forward transit time Coefficient for bias dependence of TF Voltage for TF dependence on VBC Current where TF = f(lc.1 lE13 2 200 2 100 10 0.5 0 0 0 RB 00 area area l/area I/area l/area l/area area 0 0 00 0 0 0 0 0.5 area area .2 Name IS BF NF VAF IKF ISE NE BR NR VAR IKR ISC NC RC RE RB RBM IRB TF XTF VTF ITF PTF TR CJE VJE MJE CJC VJC MJC TRANSISTOR BJT Model Parameters Parameter Units A V A A Default 1x 100 1 00 00 Example lE16 80 2 100 0.f ld  A.6 0.3 Noise Model The three noise contributions are due to the parasitic series resistance.2 qD t::.7) ~ .5 250 0.75 0.
75 0 1.6 0.1) + ISE(eqVBdNEkT .1) + ISC(eqVBclNCkT  1) (A9) where qb is defined by qb = ~' (1 + Jl VAF + 4q2) VAR _ q.11 3 0 0.5 Scale Factor F V eV XTI XTB FC KF AF 0 0.11 Si A.BIPOLAR JUNCTION TRANSISTOR 381 Table A. IS C4. IS . which correspond to the junction leakage currents ISE and ISC: ISE ISC = = C2. q 2 ( 1 _ VBC _ VBE )' 1) + IKR IS (eqVBclNRkT  (A 10) = IS (eqVBdNFkT _ IKF 1) Older versions of SPICE use parameters C2 and C4.2 Name XCIC CIS VIS MIS EG (continued) Parameter Fraction of CJC connected at internal base node B' CS zerobias junction capacitance CS builtin potential CS grading coefficient Activation energy Is temperature exponent {3F and {3R temperature exponent Coefficient for forwardbiased depletion capacitance formula Flicker noise coefficient Flicker noise exponent Units Default Example 0.5 1.5 0 1 2P area 0.2.1 DC Model Ic ~~ (eqVBdNFkT _ eqVBclNRkT) _ ~~ (eqVBclNRkT .ISC(eqVBclNCkT  1) 1) (A 8) IB = ~~ (eqVBdNFkT  1) + ~~ (eqVBclNRkT .
2 Transient and AC Models CBE CBC CCS Diffusion capacitances = CDE + CJE CDC + CJB. RBB.44IB/ 24/ 'TT2 'TT2IRB JIB/IRB A.=== 1 + J1 + 1.c CJS as (AI2) = = are implemented CDE C DC = _J_ [T/ JVBE S qb (eQV8dNFkT  1)] (A13) = TR qIS eQV8c1NRkT NRkT where TF and = TF[l + XTFeV8c11.44VTF ( Icc Icc + ITF )2] (A 14) Junction capacitances are defined by (AI5) .382 APPENDIX A SEMICONDUCTORDEVICE MODELS The effective series base resistance.2. is RBM RBB.z where z = . = + RB .RBM qb if IRB is not specified (All) ztan2 z if IRB is specified { RBM + 3(RB .RBM) tan z .
20) The temperature dependence mined by Eqs.BIPOLAR JUNCTION TRANSISTOR 383 The Be junction capacitance has two components. one to the internal base node: one connected to the external and CIB.6. cPI. TF (A 17) This effect is also present in the timedomain expression of ie(t). of Eg.2.C CIBC At high frequencies = XJC.4 Noise Model Noise is modeled as thermal noise for the parasitic series resistances flicker noise for i C and iB: i~ and as shot and = 4kTtlf R (A2l) . CIC = (l .I8) (A 19) (A. and CI for the diode is implemented as deter A. A.2.XJC)CIC (A 16) a phase shift equal to () = is applied to the phasor Ie: wPTF. AA to A.3 Temperature Effects The following quantities are adjusted for temperature variation: (A.
0 1.OE8 4.0ElO 1.384 APPENDIX A SEMICONDUCTORDEVICE MODELS :z lb :z = lc A.0E1O 4.OEII 4.0E4 10 10 10 5P IP 2.0ElO O.23) MOSFET MOSFET Model Parameters Parameter Model index Threshold voltage Transconductance parameter Bulk threshold parameter Surface potential Channel length modulation parameter Drain ohmic resistance Source ohmic resistance D and S diffusion sheet resistance Zerobias BD junction capacitance Zerobias BS junction capacitance Zerobias bulk junction bottom capacitance Bulk junction grading coefficient Zerobias bulk junction sidewall capacitance Bulk junction grading coefficient Bulk junction potential Bulk junction saturation current Bulkjunction saturation current per junction area GD overlap capacitance per unit channel width GS overlap capacitance per unit channel width GB overlap capacitance per unit channel length Substrate doping Surface state density Fast surface state density Thinoxide thickness Type of gate material + 1opposite to substrate 1 same as substrate Al gate Metallurgical junction depth Lateral diffusion Surface mobility Units Y A/y2 yl/2 Y yI Default I 0 2 X 105 0 0.25 0.2U 700 .5 1.0EI6 I.5 0 0.6 0 0 0 0 0 0 0 0.3 2q IB 11/ 2q1cl1/ + KF.OEII 2./ IY 11/ (A.6 1.0E3 0.5 0.5U O.OEI5 1.3 Name LEYEL YTO KP GAMMA PHI LAMBDA RD RS RSH CBD CBS CJ MJ CJSW MJSW PB IS JS CGDO CGSO CGBO NSUB NSS NFS TOX TPG Example 1.7 1.0E9 0.0E4 0. s 0 0 600 O.lU Scale Factor n n n F F F/m2 NRD NRS AD AS PD PS F/m Y A Nm2 F/m F/m F/m cm3 cm2 cm2 m AD AS W W L o XJ LD .UO m m cm2N.33 I I x 1014 0 0 0 0 0 0 0 00 Table A.22) (A.
VTRA. .VBIN ." Cox(Vcs .24) and mobility factors are defined by f3 IJ.== VO == IJsCox Lejf w  ilL UEXP (A.A. LEVEL==2: 1]VDS) f3 { ( l:'CS . 3. VDS) ] (A.VBS) (A. are available in all SPICE versions.(PHI .3.26) The builtin voltage including smallsize effects is VBIN == VFB + PHI + DELTA 4 Cox~(PHI 7TES' .25) [ VCRITEs. these two models together with the LEVEL==l model.VTH .1 DC Model The LEVEL parameter differentiates and sets the analytical models describing the behavior ofa MOSFET.VBS)3/2]) (A.VBS)3/2 .2.VDS IDs == ~YS where the transconductance [(PHI + VDS . described in Chap. Only the equations for LEVEL==2 and LEVEL==3 are listed.27) . There are 3 levels in SPICE2 and 6 in SPICE3.
30) D . 2ESi q.2LD if LAMBDA is specified if LAMBDA is not specified (A. is adjusted due to lateral diffusion..(VGS .1) Ws = Xd JPHI .29) VTO where = VFB + PHI .VBIN)  YJ (A.as . L.JPHI) (A.GAMMA JPHI ')Is = GAMMA(l .VBS .32) Ll _ { LAMBDA .NSUB The geometric channel length. LD. and channel shortening in saturation: Left = L . . 33) (A.28) (A.1) Xl aD = 2£ lXl(J 1 + 2 Xl W (A.386 APPENDIX A SEMICONDUCTORDEVICE MODELS The adjusted and zerobias threshold voltages are VTH = VBlN + ')Is ( JPHI . 34) . VDS f(VDSAT) L  The pinchoff saturation voltage is defined by V DSAT .VBS .31) (A.aD) as = IXl 2£ (J 1 + 2 Ws .
Qchan(L) = 0 + VDSAT)'/2 ] (A.VBS 7TESi + DELTA 4C ) Cox mW LEVEL=3: IDS where 1+ FB = f3 (VGS .39) = aQB aVBS = d ( Ys dV ~ J PHI ays .X d [ (XdVMAX)2 2 JJs L.VDSAT) + 2.l XdVMAX + (V DS .av ~ J PHI . 36) Qchan = Cox [VGS . W.VBS .MOSFET 387 The velocitysaturationbased tions: model derives VDSAT and ilL from the following equa IDSAT .VBS)3/2 . NFS Cd Cd Cox (A.41) .VBS)3/2]) eq(VGSVoN)/nkT (A. 37) Subthreshold conduction is modeled when NFS is present: IDS =f3 {(VON .40) (A.VTH .] JJs (A.VBIN . 35) (A.2VDS )V DS (A. 38) VON = VTH +Cis Cox nkT q n=l++Cis = q .'l7VDSAT .(PHI .VBIN ~YS [(PHI where 'l7~DS )VDS + VDS .VMAX.VBS AL .Ys(PHI .
0631353.45) CoxLejf Wp/Xl 1 .50) Xd [ + KAPPA(VDS .47) (A.48) (A. JLs Lejf)2 (A.VTH) (A.VTH)2 1 +FB + (VMAX.VDSAT) .15 X 1022 3 (A.VTH 1 +FB ilL = + VMAX.Xl (A.46) FN = DELTA 'TTESi 2CoxW (A.43) JLejf 1+ JLs JL VMAl.388 APPENDIX A SEMICONDUCTORDEVICE MODELS va JLs = 1 + THETA(VGS = .( 1 + Wp/Xl Fs = 1 _ Xl [LD )2 Lejf LD] . d2 = 0.49) do = 0.01110777 The saturation model is based on velocitylimited carrier flow: VDSAT = VGS .8013292. Lejf JLs EPXd)2 ( 2 (VGS .51) where Ep=  IDSAT GDSATLejf . d] = 0.EPXd] 2 (A.42) (A.44) where a = ETA + We Xl 8. Lejf VDs The threshold voltage is defined by (A.
VDS . and Ko 1985).[ 2(VGS _ ( 1 ]2) ]2) + CGSO.17. VGS ::s. A. Leff (A. VGS > VTH CGB CGS + VDS. CGDO. the expressions are = CGBO' 3CoX CGDO' Leff = = 2 + CGSO. In the cutoff region. Sheu. VTH CGB CGS CGD + VDs.MOSFET 389 For the BSIM and BSIM2 models. + CGDO' W (A 54) W CGD Cox [ 2(VGS _ Cox DS where = Cox W .52) CGSO. V TH. W W (A53) In linear operation.3. and CGB. VTH < VGS ::s. are listed below for the three main regions of operation of a MOSFET.VON VON) _ V DS VGS .VON VON) _ V ( 1 . see the University of California at Berkeley research reports (Jeng 1990. shown graphically as a function of VGS in Figure 3. LEVEL=4 and LEVEL=5 in SPICE3. all three capacitances are constant: CGB CGS CGD = = = Cox + CGBO W W . Scharfetter. Leff €ox€O C ox = TOX The charge conservation model derives asymmetrical capacitances according to the following definitions: Qchan = QD + Qs = (QG + QB) (A55) .2 Transient and AC Models The gate capacitances defined by the Meyer model. = = = CGBO' Cox Leff VGS . CGD. CGS. In saturation.
and C] which have the temperature dependence described for the diode. 1985.390 APPENDIX A SEMICONDUCTORDEVICE MODELS QD = XQC' Qchan (A56) (A5?) _ aQx aQy_ Cxy . and P. cf>]. ERL Memo UCBIERL M90/90 (October).3. B.. Design and modeling of deepsubmicrometer MOSFETs.T. K. the intrinsic concentration ni and the mobility are adjusted for temperature: ni(T) ni(300) _ = ni(300) (T)1.¥.f + KF. M. D. .f ds 3 fC ox L2 eff (A. 1990. Ko. L.Cyx avy avx A. Berkeley.C. ERL Memo UCBIERL M85/42 (May). Scharfetter.4 Noise Model The noise contributed by the drainsource current is j2 = 8kTgm D.3. £g)] 2k 300 (A58) 1. I~~ D. ..5 300 1010 m3 exp [Q(1. SPICE2 implementation of BSIM 'model. Berkeley. J. University of California. University of California.3 Temperature Model In addition to Is.Sheu.60) REFERENCES Jeng.16eV K .45 X jL(T) = jL(300) 300)1.5 (T (A59) A.
*ERROR*: NEGATIVE NODE NUMBER FOUND This statement is printed immediately following an input statement that contains a negative node number.1 GENERAL SYNTAX ERRORS *ERROR*: UNRECOGNIZABLE DATA CARD This message follows an input statement that starts with a number in the first field. This section enumerates all the SPICE2 error and warning messages related to input specifications. does not start with any of the accepted key characters in the first column. It is an added protection that ensures that additional element types are implemented correctly at future times. but the wording may differ. An example is the occurrence of two title statements in the same circuit specification. B. since it duplicates the previous message. This error is fatal. Other SPICE programs flag the same problems as the ones listed below. This error is fatal. *ERROR*: UNKNOWN DATA CARD: Name Name. *ERROR*: ELEMENT TYPE NOT YET IMPLEMENTED This error message should hardly ever occur. that is. is omitted in the first column of a continuation statement. This error may arise when the continuation character. the first field of the statement. This error is fatal. This error is fatal. +. 391 .APPENDIX B ERROR MESSAGES A large percentage of aborted simulation runs are due to erroneous input specifications.
for example. This error is fatal. This error message would occur if. This error is fatal. or the frequency.0 A coupling coefficient in excess of 1 must have been specified in the above statement. even if all bulk terminals are connected to ground. only three nodes are specified for a MOSFET. for transient . F.3 SOURCE SPECIFICATION ERRORS *ERROR*: VOLTAGE SOURCE NOT FOUND ON ABOVE LINE A currentcontrolled source requires the name of the voltage source through which the controlling current flows to be specified. *ERROR*: UNKNOWN SOURCE FUNCTION: sourcefunction A transient source function is specified. The analysis continues with a coupling coefficient of 1. *ERROR*: EITHER TD OR F MUST BE SPECIFIED A value must be specified for either the delay time. This error is fatal.END CARD MISSING *ERROR*: ILLEGAL NUMBERSCAN STOPPED AT COLUMN number A number with an absolute value outside the interval from 1035 to 1035 has been. The voltage source name must follow the node numbers of the source. This A value must be specified for the characteristic error is fatal. the fourth node must be defined for a MOSFET. *ERROR*: ZO MUST BE SPECIFIED impedance of a transmission line. of a transmission line. *ERROR*: . This error is fatal. 8. 8. WARNING: COEFFICIENT OF COUPLING RESET TO 1.392 APPENDIX B ERROR MESSAGES *ERROR*: NODE NUMBERS ARE MISSING This error message is printed immediately following an input statement that does not contain the correct number of nodes for a particular element type.2 MULTITERMINAL ELEMENT ERRORS *ERROR*: MUTUAL INDUCTANCE REFERENCES ARE MISSING A mutual inductance name must be followed by two inductor names starting with the letter L. TD. This error is fatal. Check the types and abbreviations source functions. specified.
PS. AD. 8. which lead to infinite conductances. *ERROR*: VALUE IS ZERO This message follows a zerovalued resistor. SEMICONDUCTORDEVICE. and MOSFET statements. Each of these elements must be accompanied by a positive value. Vi) coordinates must be in increasing order. This error is fatal. Check element statement for valid parameter names. JFET. BJT. *ERROR*: UNKNOWN MODEL TYPE: modeltype A model type was specified in the above statement that is not one of the eight types recognized by SPICE2.ELEMENT. which are assigned in order to L. This error is fatal. *ERROR*: EXTRA NUMERICAL DATA ON MOSFET CARD A MOSFET can have up to eight device parameters. SEMICONDUCTORDEVICE. For convergence reasons it is not advisable to use resistor values less than 1 mf!. *ERROR*: UNKNOWN MODEL PARAMETER: Name The above parameter name is not supported by the model. . *ERROR*: VALUE IS MISSING AND MODEL ERRORS NONPOSITIVE OR IS This error message can follow an element definition statement that is expected to contain a value. *ERROR*: MODEL TYPE IS MISSING Every • MODEL statement must contain a model type.4 ELEMENT. This error is fatal. The following elements belong in this category: resistors. l¥. mutual inductors. This error is fatal. such as area. This error is fatal. capacitors. The number of values in the above line exceeds the maximum number of parameter values. and controlled sources. or L. and NRS. Up to eight values can follow the model name. *ERROR*: MODEL NAME IS MISSING A model name is expected to follow the node specification on diode. NRD. This error is fatal. This error is fatal. *ERROR*: UNKNOWN PARAMETER: Name A parameter name used in an element statement is not valid. This message may be encountered also following a semiconductor device definition statement that contains negative geometry parameters. This error is fatal. AND MODEL ERRORS 393 *ERROR*: ELEMENT Name PIECEWISE LINEAR SOURCE TABLE NOT INCREASING IN TIME The time values of the (ti. The solution of nodal circuit equations in SPICE precludes the use of zerovalued resistors. l¥. AS. inductors. PD.
line. Such a loop would contradict Kirchhoff's WARNING: ATTEMPT TO REFERENCE RESET TO 0 UNDEFINED NODE numberNODE 8.6 SU8C1RCUIT DEFINITION ERRORS *ERROR*: SUBCIRCUIT DEFINITION DUPLICATES NODE number Two terminals (nodes) on the subcircuit definition line have the same number. MODname. . IS UNUSUALLY LARGE AND MIGHT CAUSE NONCONVERGENCE WARNING: IN DIODE MODEL MODname IBV INCREASED TO value TO RESOLVE INCOMPATIBILITY WITH SPECIFIED IS WARNING: UNABLE TO MATCH FORWARD AND REVERSE DIODE REGIONS. *ERROR*: LESS THAN 2 CONNECTIONS AT NODE number At least two elements must be connected at any node. CONTAINING voltage law. *ERROR*: Vname INDUCTOR/VOLTAGE SOURCE LOOP FOUND. *ERROR*: SUBCIRCUIT NAME MISSING A name starting with a character must follow the word. *ERROR*: NONPOSITlVE DEFINITION NODE NUMBER FOUND IN SUBCIRCUIT All node numbers must be positive numbers. *ERROR*: NO DC PATH TO GROUND FROM NODE number From every node there must be a path to ground in order to find a DC solution.394 APPENDIX B ERROR MESSAGES WARNING: MINIMUM BASE RESISTANCE (RBM) IS LESS THAN TOTAL (RB)FOR MODEL MODname RBM SET EQUAL TO RB WARNING: THE VALUE OF LAMBDA FOR MOSFET MODEL.5 CIRCUIT TOPOLOGY ERRORS *ERROR*: CIRCUIT HAS NO NODES The circuit needs to contain at least one other node than ground. subcircuit instantiation. SUBCKT on a subcircuit definition line or the node numbers on an X element. BV = value AND IBV = value 8.
*ERROR*: INTERNAL TIMESTEP TOO SMALL IN TRANSIENT ANALYSIS The smallest acceptable time step has been reached after repetitively cutting the time step without converging to a solution.ANALYSIS ERRORS 395 *ERROR*: SUBCIRCUIT NODES MISSING Node numbers are expected to follow the subcircuit name on a SPICE2 subcircuit definition line. every subcircuit definition must be completed with an • ENDS line.7 ANALYSIS ERRORS *ERROR*: MAXIMUMENTRY IN THIS COLUMNAT STEP LESS THAN PIVTOL number value IS Circuit matrix is singular. *ERROR*: Xname HAS DIFFERENT NUMBER OF NODES THAN SUBname The number of nodes on an X line must match the number of nodes on the subcircuit definition line it references. *ERROR*: . *ERROR*: NO CONVERGENCEIN DC ANALYSIS. see Chaps. • END line. in SPICE2 increase ITL2 and consult Example 10. 10 for advice on overcoming convergence problems. .. WARNING: ABOVE LINE NOT ALLOWEDWITHIN SUBCIRCUIT. see Sec.2. list LAST NODE VOLTAGES: Failure to find a DC solution. 9 and 10 for more insight.1 for detailed examples.ENDS CARD MISSING The end of the circuit deck. has been encountered before all • SUBCKT lines have been matched by • ENDS lines.IGNORED WARNING: NO SUBCIRCUIT DEFINITION KNOWNLINE IGNORED 8. *ERROR*: NO CONVERGENCEIN DC TRANSFER CURVES AT Name = value LAST NODE VOLTAGES: list Solution failure during a • DC analysis at a specific value of the variable Name. *ERROR*: SUBCIRCUIT SUBname IS DEFINED RECURSIVELY A subcircuit definition contains an X element that references the subcircuit being defined. *ERROR*: UNKNOWNSUBCIRCUIT NAME: SUBname A • SUBCKT definition for SUBname referenced by an X element cannot be found in the circuit deck. see Chap. 10.8.
. and when interactivity is available. *ERROR*: MEMORY REQUIREMENT EXCEEDS MACHINE CAPACITY MEMORY NEEDS EXCEED value]. set ITL5 = 0 to remove this limit. equal to 5000 in SPICE2. floatingpoint arithmetic computation may continue after an underflow condition leading to the creation and proliferation of outofrange or NaNs (notanumber). •AC. • TRAN. Many SPICE programs do not have this builtin limit. value2 The analysis of the circuit requires more internal memory than available. to give the user the opportunity to judge the correctness of results and whether analysis should be continued. ANALYSIS OMITTED. WARNING: MORE THAN number POINTS FOR Name ANALYSIS. quantities.OPTION CARD The transient analysis is stopped after a preset number of iterations. WARNING: TOO FEW POINTS FOR PLOTTING Too few points have been computed or requested.TRAN. . WARNING: NO Name OUTPUTS SPECIFIED ••• ANALYSIS OMITTED In SPICE2 a • DC.AC analysis must be accompanied by a .OPTION CARD Some SPICE programs limit the number of print/plot points that can be output by • DC. such as in SPICE3. *ERROR*: TEMPERATURE SWEEP SHOULD BE THE SECOND SWEEP SOURCE. the lineprinter plot has been omitted. note that in IEEE format. or .PLOT or • PRINT request. the user can monitor the correctness of the solution.AC analysis. WARNING: UNDERFLOW OCCURREDnumberTIME(S) WARNING: UNDERFLOWnumberTIME(S) jreq HZ IN AC ANALYSIS AT FREQ WARNING: UNDERFLOWnumberTIME(S) FREQjreq HZ IN DISTORTION ANALYSIS AT A smaller number than can be represented on the computer was generated during a •DC • TRAN.EXECUTE In a •DC statement the temperature variable must always be the second variable if another sweep variable is specified.396 APPENDIX B ERROR MESSAGES *ERROR*: TRANSIENT ANALYSIS ITERATIONS EXCEED LIMIT OF number THIS LIMIT MAY BE OVERRIDDEN USING THE ITL5 PARAMETER ON THE . or • DISTO analysis. SPICE has trapped and minimized the effect of the problem. Use the LIMPTS options parameter to override this limit. CHANGE THE ORDER AND RE. THIS LIMIT MAY BE OVERRIDDEN USING THE LIMPTS PARAMETER ON THE . or .
ANALYSIS OMITTED WARNING: UNKNOWNANALYSIS MODE: Name . 5. ANALYSIS OMITTED WARNING: UNKNOWNFREQUENCY FUNCTION: Name ••• ANALYSIS Frequency variation is limited to LIN. LINE IGNORED The analysis type on a plot or print statement must be one of DC. WARNING: OUTPUT VARIABLE UNRECOGNIZABLE ••• Incorrect sensitivity analysis output specification.. WARNING: FREQUENCY PARAMETERS INCORRECT ••• ANALYSIS WARNING: START FREQ > STOP FREQ ••• ANALYSIS OMITTED OMITTED OMITTED WARNING: TIME PARAMETERS INCORRECT ••• ANALYSIS WARNING: START TIME> STOP TIME ••• ANALYSIS OMITTED OMITTED OMITTED WARNING: ILLEGAL OUTPUT VARIABLE ••• ANALYSIS Incorrect output variable specification in • TF analysis. OCT. TRAN. AC. WARNING: INVALID INPUT SOURCE ••• Incorrect input noise source specification. or DEC. see Chap. WARNING: VOLTAGE OUTPUT UNRECOGNIZABLE ••• Incorrect noise analysis output specification.. . WARNING: UNRECOGNIZABLE OUTPUT VARIABLE ON ABOVE LINE Incorrect output variable specification on a plot or print statement. NOISE or DISTO.ANALYSIS ERRORS 397 WARNING: MISSING PARAMETER(S) ••• Incorrect • DC specification. WARNING: DISTORTION WARNING: DISTORTION OMITTED WARNING: FOURIER LOAD RESISTOR ANALYSIS ANALYSIS OMITTED OMITTED MISSING ••• ANALYSIS ANALYSIS OMITTED PARAMETERS INCORRECT ••• PARAMETERS INCORRECT ••• ANALYSIS OMITTED WARNING: FOURIER ANALYSIS FUNDAMENTAL FREQUENCY IS INCOMPATIBLE WITH TRANSIENT ANALYSIS PRINT INTERVAL ••• FOURIER ANALYSIS OMITTED Transient analysis interval (TSTOP .TSTART) is less than the period of the fundamental specified on the • FOUR line.
MAXIMUM VALUE ASSUMED WARNING: UNKNOWN OPTION: Name WARNING: ••• IGNORED FOR OPTION: Name ••• IGNORED ILLEGAL VALUE SPECIFIED The following warnings are issued for an incorrect •NODE SET or • IC line.8 APPENDIX B ERROR MESSAGES MISCELLANEOUS ERRORS *ERROR*: CPU TIME LIMIT EXCEEDED .. WARNING: NUMDGT MAY NOT EXCEED number. ANALYSIS STOPPED Some SPICE programs allow the user to set a limit on how long an analysis can run..398 B. WARNING: WARNING: OUTOFPLACE INITIAL NONNUMERIC FIELD Name SKIPPED VALUE MISSING FOR NODE number CONDITION FOR GROUND WARNING: ATTEMPT TO SPECIFY IGNORED INITIAL .
...phase»> + <TRANjunction <valuel <value2 . ><IC= iLO> Vname node1 node2 «DC>devalue><AC <acJnag <ac. »> TRAN Junction can be one of the following: V2 <TD <TR <TF<PW<PER»»» SIN(VO VA <FREQ <TD <THETA»» SFFM (VO VA <Fe <MDI <FS> > > ) PULSE(Vl > 399 . ><IC=vco > Cname nodel node2 <cvalue><Mname><L=L><W=W><IC=vco [SPICE3] Lname nodel node2 lvalue <IC=iLO> Lname nodel node2 POLY 10 II < 12 .l ELEMENT STATEMENTS Rname nodel node2 rvalue < TC=tc1<tc2> > Rname nodel node2 <rvalue><Mname><L=L><W=W> Cname nodel node2 lvalue <IC=vco > [SPICE3] Cname nodel node2 POLY Co CI < C2 .APPENDIX C SPICE STATEMENTS This appendix lists all the SPICE statements introduced in this text.. C.. Statements followed by [SPICE3] appear only in SPICE3.phase»> + <TRANjunction <valuel <value2 . »> Iname nodel node2 «DC> devalue><AC <acJnag <ac......
ncZ.Vname Model <ON/OFF> Tnamenl Dname n+ n. » < IC=i(Vname1 ).1l4.ncl.. < IC=VDSO. > [SPICE3] [SPICE3] [SPICE3] Hname n + n ..... i(Vname2) .VCEO> < IC=VDSO. > Po < PI + + < pz . > iz Qname nc nb ne <ns> MODname Mname nd ng ns nb MODname <area> <OFF> < IC=VBEO..MODname Jname nd ng ns MODname nz n3 n4 ZO=zO <TD=td> <F=freq <NL=nl <area><OFF><IC=VDO <area><OFF> »<IC=VIlI.. » <IC=Vncl+...Vname fvalue Fname n+ n<POLY (ndim) > Vname1 <Vname2 .Model <ON/OFF> Wname n+ n.'" Ename n+ n..nc+ nc.llcl.... » Diode model npn BJT model .IlZ.. > > ) Lname2 k gvalue <POLY (ndim) > nc1 evalue Kname Lnamel Gname n+ n Gname n+ n. > Po < PI + < pz ..400 C SPICE STATEMENTS EXP(Vl V2 <TDl TAW TD2 <TAU2») PWL (tI VI < tz Vz < t3V3 .. i(Vname2) ..vcso > «L=>L>«W=>W><AD=AD><AS=AS> + + <PD=PD> <PS=PS> < NRD=NRD > <NRS=NRS> <OFF> <IC=VDSO. VIl3...vcso > [SPICE3] > SUBname C. > Fname n + n . > ii.ncZ.. Bname nodel node2 <VII> =expr Sname n+ n..nc+ nc + nc1 < nc2+ nc2> . » <IC=Vncl+.... > <POLY (ndim) > Vnamel <Vname2 .. vcso... VBSO> <area><OFF> Zname nd ng ns MODname Xname xnodel <xnode2 . vncZ+. > Po < PI < pz .nc+ ncEname n+ n <POLY (ndim) > nc1 + nc1 < nc2+ nc2 ..vllcZ+..2 GLOBAL STATEMENTS • MODEL MODname MODtype <PARAM1=valuel MODtype can be one of the following: D NPN <PARAM2=value2 . > Po < PI < Pz .Vname hvalue Hname n+ n » + <IC=i(Vnamel).
TF OUT_varV/Iname • SENS OUTvar] <OUT_var2 ..CONTROL STATEMENTS 401 PNP NJF PJF NMOS pnp BJT model nchannel JFET model pchannel JFET model nchannel MOSFET model pchannel MOSFET model Diffused resistor model Diffused capacitor model [SPICE3] [SPICE3] [SPICE3] [SPICE3] [SPICE3] PMOS R C URC Uniformdistributed RC model Voltagecontrolled switch model Currentcontrolled switch model nchannel MESFET model pchannel MESFET model SW CSW NMF PMF [SPICE3] [SPICE3] • SUBCKT SUBname node] <node2 .3 CONTROL STATEMENTS .DISTORLname [SPICE3] <nums <f2/fl < Pre! < S2 »» node_out2 <CUR/VOL><POL/ZERlPZ> • PZ node_in] node_in2 node_outl .n2» V/Iname nums .NOISE.. ><ploLlimits> Analysis_TYPE can be one of the following: DC... > • PRINT/PLOT AnalysisTYPE OUT_varl <OUT_var2 .NODESET V(nodel)=value] • IC V(nodel)=valuel • ENDS <SUBname> • END <V(node2)=value2 ..TRAN...DISTO .. > • TEMP temp] <temp2 .....OP • DC V/Iname] start] stop] step] <V/Iname2 start2 stop2 step2> .. > <V(node2)=value2 . > ..AC. > .NOISE V( n]<.TRAN TSTEP TSTOP < TSTART <TMAX»<UIC> •FOURfreq OUT_var] <OUT_var2 .AC DEC/OCTILIN numptsfstartfstop . > C.
25xn1 + TIXn2 .APPENDIX D GEAR INTEGRATION FORMULAS Gear 1: Gear 2: Gear 3: Gear 4: Gear 5: Xn+l =Xn 4 Xn+l Xn+l Xn+l Xn+l + hXn+l . 3h5 d5x 25 Xn+l .3Xn1 + 3Xn+1 = 9 2h3 d3x dt3 6h.  360 450 400 225 72  10 147xn5 180h6 d7 X 3087 dt7 (~) 402 .125 dt5 12 (~) 300 300 137xn .2 dt2 (~) 1 2h .147xn1 + 147xn2 .  .  lOh6 d6x 137 dt6 Xn+l = 147xn .25xn3 200 75 2 3h4d4x dt4 (~) = = + 12h.TIXnl 48 36 25xn .22 + 16 3 25xn2 .147xn3 + 147xn4 + 147xn+1 60h . h2 d2x = 3xn .137xn3 + 137xn4 (~) + 137xn+1 Gear 6: 60h .TIXn+l . (~) 18 9 TIxn .137xn1 + 137xn2 .
SIMPLE DIFFERENTIAL AMPLIFIER Ql 4 2 6 QNL Q2 5 3 6QNL Q3 6 7 9 QNL Q4 7 7 9QNL RSI 1 2 lK RS2 3 o lK RCI 4 8 10K RC2 5 8 10K RBIAS 7 8 20K VCC 8 o 12 VEE 9 o 12 VIN 1 o SIN( o 0. Berkeley.MODEL QNL NPN BF=80 RB=100 CJE=3P CJC=2P VAF=SO ANALYSIS REQUESTS 403 . Most types of statements and analyses are used.APPENDIX E SPICE INPUT DECK This is an example SPICE input for a differential amplifier from the University of California. SPICE benchmarks.1 SMEG) AC 1 * * * * CIRCUIT ELEMENT DESCRIPTION STATEMENTS * * GLOBAL STATEMENTS CCS=2P TF=0.3N TR=6N * * * + . DIFFPAIR CIRCUIT .
pwr TRAN V(5.OP .DC VIN 0.4) .TRAN 5N SOON * * OUTPUT REQUESTS * .25 0.AC DEC 10 1 10GHZ .pwr * END • DC V(5) .TF V(5) VIN .pwr AC \!M(5) VP(5) .404 E SPICE INPUT DECK * .005 .25 0.
BR. 308. 290291 reordering. 2226. 284 pivoting. 381384 parameters.119121. 4748. 296297. 335. 210213. 145149.AC. 371 . 164166 sensitivity. 114140 timedomain. 1617. 315.2426. 2933. 291298 limiting. 116117 types: AC frequency sweep. 196204. 246 DC transfer curves. 8696. 142 ACCT. 215216 Algorithms: convergence enhancing: source ramping. 153157. 2933. 238. current Bias point. 151. 368372 direct methods. 142149. 280283 nonlinear equation solution. 159164 Analysis: modes: AC. 349. 5. 7986. 129132 transient. 7896. 141167 DC. 130132. 312314 Accurac~ 285291. 7879 model: equations. 3. 9394. 164. 285 modified nodal analysis. 350352 distortion. 244262. 346349 transient ramping. 1920. 3436. 114115 parameters. 149157 operating (bias) point. 133136 smallsignal transfer function. 241277 Fourier. 380384 device. 285. 297.INDEX A ABSTOL. 308312 Adder circuit. 1417. 117125. 253284 LV factorization. 157164. 184191 noise. see Gain. 14. 279 linear equation solution: Gaussian elimination. 125129.148 polezero. 1617. 169180 Approximations. 39. See also Numeric integration Amplifier. 299312. 122 B B (nonlinear controlled source) element. 119121. see Analysis Bipolar junction transistor (BIT). 380381 405 . 1517. 285291 Markowitz. 290 sparse matrix. 2426. 298. 291296 numeric integration. 294295 NewtonRaphson. 213216 BF. 168192 overview.
6364 switch. 189190. 6165 nonlinear. 44 semiconductor. 16. 350352 thermalvoltage referenced source.406 INDEX Bistable circuit. 6567 voltage source (CCVS). 87. 380381 diode. 384385 D (diode) element. 57. 149 Branchconstitutive equations (BCE). 5658 Comment line. 296298. 261. 311312. 223224 DIM2 output variable. see Analysis DC model: BJT. 345349 Coefficient of coupling k. see Semiconductor device model Capacitor: linear. 220221 Digital circuit: adder. III MOSFET. 69. 143145. 61. 378 JFET. 22.110 MOSFET. 78.314315.252254 intermodulation. 46 Convergence. 204213 macromodel. 75 model: equations. 213216 linear. 401 Conventions. 126127. 4243 model. 9395. 78. 96. 6364 current mirror. 362367 Differentiator. 82. 77. 280. 109. 221. 368374 inverter. 158. 73. 76. 291. 4445 C (capacitor) element. 14.9697 MESFET. 6365. 75. 213216 polynomial. 275276 DIM3 output variable. 5865. 78. 45. 163. 227240 subcircuit. 7983. 44 nonlinear. see Analysis Default values: BJT. 76. 2933. 79. 7576 Device initial conditions (IC). 213227 ideal. 137138. universal. 226227 Curtice model. 379 JFET. 19. 342344 Bode plot. 97 BV breakdown voltage. 205. 209213 TTL gate.319377 Crossmodulation distortion. 148. 4142. 125127 DC transfer curves. see Distortion Current controlled: current source (CCCS). 378 Distortion: crossmodulation. 39. 261262 harmonic. 316 Circuitblock models: functional. 254255 . 7677. 353355 c Capacitance. 163. 159. 1922 Continuation line. III D DC analysis. 194204 CMOS circuit: differential amplifier. see Adder circuit logic functions. 3839.99 MESFET. 45. 4245 CHGTOL. 102103. 379380 parameters. 18. 6162. 38. 391 Controlled source. 6465 Current source: controlled. 87. 133136 independent. 159. 275276 Diode: device. 323325 Currentvoltage characteristics. 180184. 6165. 360362 opamp. 186189. 5965 Control statement. 7677. semiconductor. 4656 zerovalued. 330335 Schmitt trigger. 18. 4243. 114140 DC bias. 68. 381382 diode.DC statement. 12.385389 . 157158.
1920. 3134 Flip. 298. 287290 Fourier series. 6465 Hybrid parameters. 315 F FC parameter. 256257. 400401 . 121. 46 Initial conditions: IC keyword (device line). see Numeric integration GEAR option. 45 mutual. 19. 180181. 93 EbersMoll model. see Numeric integration EXP signal source.IC statement. 391398 Euler integration. 241262 total harmonic. 16. 145 voltage. 189 . 184185. 326. 220221. 205 Gaussian elimination.ENDS statement. 136139. 19. 181183. 66. 1822 Input resistance. 137139. see Algorithms Gear integration. 131. 344 timedomain (. 381382 H Harmonics. 275 H (CCVS) element. 376 Ground. 278 INOISE output variable. 159.38 GummelPoon model. 297298. 7983 E (VCVS) element. 5354 GMIN option. 216217 E Early voltage. see Circuitblock models G Gain: current. 5658 polynomial. 8183. 6162 Global statement. 173. VAR. 13. 163. 2122. 163. 159. 4647 Independent source: current. 84. 6263 Electric circuit.NODESET). 329.IC). 96. 180181. 164. 185 Frequency sweep. 275 HD3 output variable. 137139. see Current source voltage. see Device initial conditions . see Voltage source Inductor: linear. 187189 . see Analysis Functional model. see Distortion Inverter. 93 I Ideal models. 180184 Initial transient solution. 1822 Element statement. 81. 6364 File input/output. 195 . 184189 HD2 output variable. 158159 Divider. 194195.INDEX 407 largesignal. 399400 . 4. 152 Input language (SPICE). 175176 F (CCCS) element. VAF. see Device initial conditions node voltages: DC (. 3. 22 Error messages. 328 Feedback circuit. 169. 2229.FOUR statement. 22. 335 Initialization: devices (IC).END statement. 195197 ITL options. 205.flop circuit. 143. 316 G (VCCS) element. 175 loop gain. 157164. 174177 feedback factor. 314. 169. see Bistable circuit Floatingpoint accuracy. 8792. 116. see Transfer function Integration. see Circuitblock models I (current source) element. 225226 Intermodulation distortion. see Numeric integration Integrator.DISTO statement. 263274 smallsignal. 305307.
see EbersMoll model GummelPoon. MESFET. 257. 14 distortion. 102107. 2. see Bipolar junction transistor. see Capacitor EbersMoll. see Raytheon model resistor. JFET. 307. 77. 126128 parameters. 289291. 292293. 379. 105106. 321. see Resistor ShichmanHodges. 96 Junction capacitance: forward bias. 108. 68. 39. 4142. 346 Nodal analysis. 8796. 7475 . circuit: PIVREL option. 9798 parameters. discharge. Resistor types.143. see Feedback circuit L (length) parameter. 316 Mixer circuit. 279. 44. 379. 77. 326 Loop gain. 328. 99101 K K (coupled inductors) element. 75 Models: capacitor. 86. 143145. 4546 Limiter circuit.408 INDEX J J (JFET) element. 102103 M Macromodel. 10911 0 model: equations. 280282 . 141142. 97. MOSFET. 225227 Largesignal: analysis. see GummelPoon model Raytheon. 44. see Inductor N NAND circuit. 101102 Metaloxidesemlconductor field effect transistor (MOSFET): device. 384385 Metalsemiconductor field effect transistor (MESFET): device. 316 M (MOSFET) element. 314. see Circuitblock models Magnitude. 74. 394 L Lamp. see Algorithms singular. 210212 NewtonRaphson. see PIVREL option PIVTOL option. see Algorithms MAXORD option. 96 model: equations. 307. see ShichmanHodges model semiconductor devices.39. 5658 Kirchhoff's laws. 141. 196204. 1216. 382383 reverse bias. 215216 Mutual inductance. see Algorithms Multiplier. 303304 linearization. III METHOD option. see Algorithms Linear circuit. AC response. see Algorithms NFS parameter. III Modified nodal analysis (MNA). see Model linearization LIST option. 129130.300. Diode. 108109. 148149 Matrix. 74. 12. 218222 Limiting. see PIVTOL option reordering. 323325. 316. 151.MODEL statement. 292293 parameter extraction. 110111 parameters.382383 Junction field effect transistor (JFET): device. 8486. 101102 model: equations. 265276 Model: companion. 100101. 4. Capacitor. see Distortion L (inductor) element. 385390 parameters. 42. 99. 15. 287. 2122. 14 Linearization. 14. 289. 395 sparse. . 83. 115.
204. 371 Noise: input. 210212 Number fields. 315.75. 307 trapezoidal. see Analysis . see.351 GEAR. 256257 Output variables. 341. 150151 Noise models: BIT. 353.OP statement.RELTOL TNOM. 323325 Operating point information. 136. 357 NOPAGE. 159. 137.347.317. see ACCT CHGTOL. see ABSTOL ACCT. 181:182. 131. 1921.7879. 301306 Nyquist diagram. H 9. 74. see NODE option NOMOD. 322323 Nodevoltage method. 353 MAXORD. 66..86. 315. localtruncation error. see VNTOL option Oscillator: Colpitts. see PIVTOL option RELTOL. 330335 functional model.' DEFL. 305307. 155157 margins. 190191 crystal. see TRAP option TRTOL. 315 ITL6. 66 . 346. 102. 317 . 151152 source. see Nodal analysis . 150151. 21. 145148. 373.NODESET statement. 311. 229238. 93. 102. 376 ITL5. 128:129 meansquare value.321323 zerovalued current source. 300305 Gear.see GMIN option ITLl. 326. 339. 150151 . 182184. 96. 362367 damping factor.357 NUMDGT. 368. 281282. see TNOM option TRAP.347. 152. 335. 220221 macromodel. 375 ITL3. 151152 NOR circuit. 315. 321 ground. 288289 startup. 335338 Open circuit: DC. 310311.INDEX 409 Node: connection. 101102. see Ground numbering. 300305 forwardEuler. 297. ~15316. 330.390 resistor. 155156 Opamp: CMOS. 177178. 316. see PIVREL option PIVTOL. seeCHGTOL DEFAD. 171 quality factor Q.317. 117119. 185 .317 OPTS. 316.364 Output resistance. 312. ONOISE output variable. 297. 102.335. 356358 ring. 308312 stability. 151. 174180.NOISE statement. 117125 Option parameters: ABSTOL. 204207. 304305. 102. 339. see TRTOL option VNTOL. 297298. see METHOD option NODE. 298. see MAXORD option METHOD. Quality factor Q relaxation. 169170. 316. 109110. 380 MOSFET. 20 Numeric integration: backwardEuler. 375 ITL2. 154157 output. 204 NODE option. see GEAR option GMIN. 343344. 315.351 DEFW. . 129. 143. 152.317 DEFAS. 228239 iLA741. 316 PIVREL. 330. 301303. 133.375 LIMPTS. 383384 diode. 115116. 337341 ON initialization.317 LIST. see LIST option LVLTIM. 175176 o OFF initialization. see. 207209 ideal model. 315 ITL4. 311.
99. 170 . 148149 PIVREL option. 289291. 7879 Quality factor Q. see Junction field effect transistor MESFET. 349. 78 S (voltagecontrolled switch) element. 96.PLOT statement. 389390 parameters: BJT. 102. 33 Probe. 296297. 207 Polezero analysis. 314. 308. 3536. 86. 217218 total dissipation. 143. 8384. 143144. 159160. 148. 97. see Model.410 INDEX p Phase. see Transfer function . 109 Schematic. 358359 R (resistor) element. 97. 5965 inductor. 322325. 2937. 379. 127. see Analysis. see Analysis. 371 PIVTOL option. 2325.PROBE statement. 87. zeroes. 315. 110 Rectifier: fullwave. 177. see Junction capacitance metaloxidesemiconductor (MOS). see Transfer function output. 170 Plotting results: Nutmeg. 382 junction. 77. 66 Semiconductor device model: capacitance: diffusion. 81. circuit. 115116 Ring oscillator. 2021.152. 3435 Poles. 99. 104105. 4G42 RELTOL. 13. 88. 62 semiconductor. parameter extraction diode. 4142 thermal noise. circuit. 144 PULSE signal source. 4850 PWL signal source. 375376 Resistance: function of temperature. 20. 143144. 314. 3436. 4344 controlled sources. 117.PRINT statement. see Hybrid parameters JFET. 16. 111 Resistor: model. 115116. see Diode hybrid. 18 Schmitt trigger.152. 103 Scale factors. 141. 143145. 368 . 133 SFFM (singlefrequency frequencymodulated) signal source. 164165 Polynomial functions: capacitance. 2836. 75. 5153 ShichmanHodges model. 149. 7678. 125 . 95. 102103 Simulator. see Noise models Result processing. 350352 Schottky barrier diode. 159160. 2937. 127 xgraph. 290291. 164 parasitic. see Bipolar junction transistor data sheet. operating (bias) point Q Q (BJT) element. 109.PZ statement. 79. 182. 278279 SIN (sinusoidal) signal source.154156. 4142 nonlinear. 5052 Smallsignal analysis. 87. 164. 362 R Raytheon model. 75. 102. see Metaloxidesemiconductor fieldeffect transistor Sensitivity analysis.SENS statement. 4556 Power: measuring circuit. 311. see Oscillator s Saturation current IS. see Metalsemiconductor field effect transistor MOSFET. 353355 halfwave. see Analysis . AC response. 326328. 9495. 41 input. 115116. 78. types Smallsignal bias solution. 5456 .
315.221. 129130 Thermal voltage. 23. 198199. 143. 14. 131. 239 IsSpice. see Distortion Transconductance. 382383 Transmission line. 21. 125 v V (voltage source) element. 309. 181183. see Numeric integration tolerances. Vth. 2628. 6871 . 98. 185. 194195 . 5. 195204 definition. 164. 1. 119 Transfer function. 86. 34. 4. 20. 116 . 315 . see Analysis. see Analysis. 345349 Timedomain analysis: spectral (Fourier). 321. 306. 20. 131 output resistance. 316. 296297. 79. 169170. 298 Spectral analysis. 352. 376 TTL gate. 86. 143.TF statement. 169 TRAP option. Metalsemiconductor field effect transistor Transit time. 69. 37. 7. 379 MOSFET. 311 convergence. 116117 . 239 SPICE2.390 resistor. 4647 VNTOL option. 102. 182. 164. 29. 67. 323. 239 Steadystate solution. 84. 223224 u VIC (Use Initial Conditions) keyword. 145. 83. 21.169. see Input language SPICE programs: HSPICE. see Bipolar junction transistor. 219221 SPICE3. see Initial transient solution overview. 20. Metaloxidesemiconductor field effect transistor.TEMP statement. 13. 344. 76 Thermal voltage referenced bias. types. 298. 96. 77. 222. see Analysis Timestep control. 164. 6265. ideal. 375 T T (transmission line) element. 164. see Analysis transient. 148. 394 Total harmonic distortion. 6869 Temperature analysis: BJT. 177. 107 Solution: accuracy. 366. 41. 291. 15 errors.205 input resistance. 305. 173. see Accuracy bypass. 58.INDEX 411 Smallsignal parameters. 28. 45. 6667 . 27 PSpice. 289291.239 SpicePlus. 77. 18. 8486. 314316 Source ramping. 3334. 110. 33.~eep. 131"132. 173. 379 Topology: circuit. 21. 362 Subcircuit: call (instance). 222223.205207 gain. 194195 Switch: element. 174177. 153. 106107. see Convergence initial transient. 6566 model. 23.383 diode. operating (bias) point stability.SUBCKT statement. 131 Transformer. 278280 smallsignal bias. 27. 296297.TRAN statement. 116.215. 308312. 43. 18. 354. 316. 316 TRTOL option. 27. 7475. Junction field effect transistor. Fourier SPICE input language. 18. 90. 98. 368. 226. 93. 368 Transistors. 145. 58 Transient ramping. 309311 TNOM option.
BV. 99100 saturation.l\. 102103 '. 285286 Voltage source: controlled.412 INDEX Voltage: breakdown. 386388 threshold. 97. Result processing EXP.WIDTH option. see BV breakdown voltage pinchoff. see SFFM signal source SIN. 4656 Volterra series. 195 '.. 6263 Voltagedefined element. VTO. 110111 Voltagecontrolled: current source (VCCS). 9697. 44. 99100. see SIN signal source W (currentcontrolled switch) element. see EXP signal source PULSE. 4142. see PULSE signal source PWL. 6567 voltage source (VCVS). 103. 66 . 317 W (width) parameter. 6162 switch. see Plotting results. 100. 110. see PWL signal source SFFM. 243 w Waveforms: display. 281. x X (subcircuit call) element. 6265 independent. .
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