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TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 – D3972, FEBRUARY 1992

• • • • • • • • • • • • •

Second-Generation PLD Architecture High-Performance Operation: fmax (External Feedback) . . . 71 MHz Propagation Delay . . . 10 ns Max Increased Logic Power – Up to 22 Inputs and 10 Outputs Increased Product Terms – Average of 12 Per Output Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control Power-Up Clear on Registered Outputs TTL-Level Preload for Improved Testability Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features Dependable Texas Instruments Quality and Reliability Package Options Include Plastic Dual-In-Line and Chip Carrier Packages
CLK/I I I I I I I I I I I GND

NT PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13

VCC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I

FN PACKAGE (TOP VIEW)

I I I NC I I I

5 6 7 8 9 10

I I CLK/I NC VCC I/O/Q I/O/Q
4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18

I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q

NC – No internal connection Pin assignments in operating mode

description
The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.
This device is covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

I I GND NC I I/O/Q I/O/Q
Copyright © 1992, Texas Instruments Incorporated

1

A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. the TIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. FEBRUARY 1992 description (continued) Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. Registered outputs selected as active-low power up with their outputs high. TEXAS 75265 . With features such as programmable output logic macrocells and variable product term distribution. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. These functions are common to all registers. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis. Registered outputs selected as active-high power up with their outputs low. The TIBPAL22V10-10C is characterized for operation from 0°C to 75°C. the output registers are loaded with a logic 0. When the asynchronous reset product term is a logic 1. the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the synchronous set product term is a logic 1. Preloading permits full logical verification during product testing. Once blown. Output registers can be preloaded to any desired state during testing.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. 2 POST OFFICE BOX 655303 • DALLAS. The output logic level after set or reset depends on the polarity selected during programming. the verification circuitry is disabled and all other fuses will appear to be open.

TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. FEBRUARY 1992 functional block diagram (positive logic) C1 & 44 x 132 8 Set Reset 1 1S R Output Logic Macrocell I/O/Q EN I/O/Q 10 CLK/I 22 EN I/O/Q 14 EN I/O/Q 16 EN I/O/Q 16 I 11 10 22 EN I/O/Q 14 EN I/O/Q 12 EN I/O/Q 10 EN I/O/Q 8 EN I/O/Q 10 10 denotes fused inputs EN 10 12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3 .

FEBRUARY 1992 TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS First Fuse Numbers 0 Asynchronous Reset (to all registers) Macrocell 23 I/O/Q 396 P = 5808 R = 5809 440 Macrocell 22 I/O/Q 880 I 2 924 P = 5810 R = 5811 Macrocell 21 I/O/Q • DALLAS.4 POST OFFICE BOX 655303 logic diagram (positive logic) CLK/I 1 Increment 0 4 8 12 16 20 24 28 32 36 40 SRPS015 – D3972. TEXAS 75265 1452 I 3 1496 P = 5812 R = 5813 Macrocell 20 I/O/Q 2112 I 4 2156 P = 5814 R = 5815 Macrocell 19 I/O/Q 2860 I 5 P = 5816 R = 5817 .

TEXAS 75265 5 4840 I 8 4884 P = 5822 R = 5823 Macrocell 15 I/O/Q 5324 I 9 5368 P = 5824 R = 5825 SRPS015 – D3972. . FEBRUARY 1992 Macrocell 5720 14 I/O/Q I I 10 5764 P = 5826 R = 5827 Synchronous Set (to all registers) 13 I 11 Fuse number = First Fuse number + Increment Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.2904 Macrocell 18 I/O/Q TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS 3608 I 6 3652 P = 5818 R = 5819 Macrocell 17 I/O/Q POST OFFICE BOX 655303 4268 I 7 4312 P = 5820 R = 5821 Macrocell 16 I/O/Q • DALLAS.

FEBRUARY 1992 output logic macrocell diagram Output Logic Macrocell MUX 2 AR R I=0 1D C1 SS From Clock Buffer MUX 1 1 G1 1S 3 0 1 1 0 S0 G 0 3 S1 AR = asynchronous reset SS = synchronous set 6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 .TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972.

ACTIVE-LOW OUTPUT I/O FEEDBACK. COMBINATIONAL. REGISTERED. ACTIVE-HIGH OUTPUT S1 = 1 S0 = 0 S1 = 1 S0 = 1 I/O FEEDBACK. ACTIVE-LOW OUTPUT REGISTER FEEDBACK. Resultant Macrocell Feedback and Output Logic After Programming POST OFFICE BOX 655303 • DALLAS. ACTIVE-HIGH OUTPUT MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE FUSE SELECT S1 S0 0 0 1 1 0 1 0 1 FEEDBACK AND OUTPUT CONFIGURATION Register feedback Register feedback I/O feedback I/O feedback Registered Registered Combinational Combinational Active low Active high Active low Active high 0 = unblown fuse. FEBRUARY 1992 R 1D C1 1S S1 = 0 S0 = 0 R 1D C1 1S S1 = 0 S0 = 1 REGISTER FEEDBACK.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. COMBINATIONAL. Figure 1. REGISTERED. 1 = blown fuse S1 and S0 are select-function fuses as shown in the output logic macrocell diagram. TEXAS 75265 7 .

. . . . . . . . . . . . . .2 16 UNIT V V V mA mA NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and includes all overshoots due to system and/or tester noise. . –0. . . . . . . . . . . . . . . . . . . . . . .75 2 NOM 5 MAX 5. . . . . . FEBRUARY 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. . . . . . . . – 65°C to 150°C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. . . . . . . . . . . . . . . . . . . . . . . .5 0. . . . . . or feedback after clock↑ Operating free-air temperature 5 10 7 7 9 8 8 0 0 75 ns °C ns ns 4. . . . . . . . . . set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 V to VCC +0. input. . . . . . Testing these parameters should not be attempted without suitable equipment. . . . . . . . . . . –1. . . . . . . . . . . . . .25 5. . . . . . . . . . . . . . . . . 8 POST OFFICE BOX 655303 • DALLAS. . . .2 V to VCC +0. . .5 V Voltage range applied to disabled output (see Note 1) .TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. . . . . 0°C to 75°C Storage temperature range . . . . . . . VCC (see Note 1) . . . .8 – 3. . . . . . . . . . . . . .5 V Operating free-air temperature range . . . . . . . TEXAS 75265 . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . recommended operating conditions MIN VCC VIH VIL IOH IOL tw Supply voltage High-level input voltage (see Note 2) Low-level input voltage (see Note 2) High-level output current Low-level output current Clock high or low Pulse duration Asynchronous reset high or low Input Feedback tsu Setup time before clock↑ Synchronous preset (active) Synchronous preset (inactive) Asynchronous reset (inactive) th TA Hold time. . . . . . . . .

5 V VI = GND.4 V VI = 5. f = 1 MHz.5 V to avoid test problems caused by test equipment ground degradation. VO is set at 0. VCC = 5.25 V.25 V.4 0. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax¶ tpd tpd tpd tpd# ten tdis ¶ fmax (without feedback) = FROM (INPUT) TO (OUTPUT) TEST CONDITION MIN 100 80 71 R1 = 300 Ω. TA = 25°C. VI = 2 V – 30 Outputs open 6 6 MIN 2.2 UNIT V V V mA mA mA µA mA mA mA pF Co f = 1 MHz. VO = 2 V 8 pF † All typical values are at VCC = 5 V. VCC = 5. TEXAS 75265 9 .1 – 130 210 TYP† MAX – 1.25 V. I/O (reset) CLK CLK I.5 0. VCC = 5. Q 1 MHz MAX UNIT Without feedback With internal feedback (counter configuration) With external feedback I.75 V.25 V.75 V.2 mA IOL = 16 mA VO = 2.25 V. R2 = 300 Ω.25 V.25 – 0.7 V VO = 0.7 V VI = 0. respectively.5 11 9 ns ns ns ns ns ns Q Q Feedback I/O.5 V VI = 2.35 0.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. VCC = 4. VCC = 5. VCC = 5.25 V. VCC = 4. TEST CONDITIONS II = – 18 mA IOH = – 3.75 V. t ) POST OFFICE BOX 655303 • DALLAS. VCC = 5. and the duration of the short circuit should not exceed one second. ‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH. Q I/O.1 1 25 – 0. § Not more than one output should be shorted at a time. See Figure 6 1 1 10 15 7 5. I/O I.4 V VO = 0. VCC = 5. FEBRUARY 1992 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK VOH VOL IOZH‡ IOZL‡ II IIH‡ IIL IOS§ ICC Ci I CLK CLK All others VCC = 4.1 – 0. I/O I. I/O t w(low) I/O fmax (with internal feedback) = fmax (with external feedback) = ) tw(high) 1 t su ) t (CLK to feedback) pd t su 1 (CLK to Q) pd # This parameter is calculated from the measured fmax with internal feedback in the counter configuration.

FEBRUARY 1992 preload procedure for registered outputs (see Notes 3 and 4) The output registers can be preloaded to any desired state during device testing.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. Pulse pin 1. Pin numbers shown are for the NT package only. raise pin 13 to VIHH. 4. If chip-carrier socket adapter is not used. then lower pin 13 to VIL. TEXAS 75265 . 10 POST OFFICE BOX 655303 • DALLAS. This permits any state to be tested without having to step through the entire state-machine sequence. td = tsu = tw = 100 ns to 1000 ns. Step 4. clocking in preload data. Step 2. Step 3. With VCC at 5 V and pin 1 at VIL.75 V. pin numbers must be changed accordingly. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Each register is preloaded individually by following the steps given below: Step 1. Preload Waveforms NOTES: 3. Remove output voltage. Preload can be verified by observing the voltage level at the output pin. VIHH = 10.25 V to 10. VIHH Pin 13 tsu td Pin 1 tw VIH VIL VIH Registered I/O Input VIL Output VOL VOH td VIL Figure 2.

To ensure a valid power-up reset. Complete programming specifications. software. VCC 4V tpd † (600 ns typ. The values shown are from characterization data.5 V VIL 5V Figure 3. ‡ This is the setup time for input or feedback. 1. and the latest information on hardware.5 V tw † This is the power-up reset time and applies to registered outputs only. Information on programmers capable of programming Texas Instruments programmable logic is also available. local authorized TI distributor. or by calling Texas Instruments at (214) 997-5666. The output level depends on the polarity selected during programming. all registers are reset to zero. it is important that the rise of VCC be monotonic. algorithms. POST OFFICE BOX 655303 • DALLAS.5 V VOL tsu ‡ VIH CLK 1. Following power-up reset. 1000 ns MAX) Active High Registered Output VOH State Unknown 1. upon request. a low-to-high clock transition must not occur until all applicable input and feedback setup times are met.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. from the nearest TI field sales office.5 V VOL Active Low Registered Output VOH State Unknown 1. Power-Up Reset Waveforms programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. TEXAS 75265 11 . and firmware are available upon request. FEBRUARY 1992 power-up reset Following power up. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization.

4 W PD = 1. Since the condition of eight fully loaded outputs represents the worst-case condition. TEXAS 75265 .2 W PD = 1 W 300 PD = 1. and outputs switching simultaneously.2 W PD = 1 W 200 200 100 100 0 0 10 20 30 40 50 60 70 80 TA – Ambient Temperature – °C (a) TIBPAL22V10-10CNT 0 0 10 20 30 40 50 60 70 80 TA – Ambient Temperature – °C (b) TIBPAL22V10-10CFN Figure 4 12 POST OFFICE BOX 655303 • DALLAS. each application must be evaluated accordingly. FEBRUARY 1992 THERMAL INFORMATION thermal management of the TIBPAL22V10-10C Thermal management of the TIBPAL22V10-10CNT and TIBPAL22V10-10CFN is necessary when operating at certain conditions of frequency. Figures 4 (a) and 4 (b) show the relationship between ambient temperature and transverse airflow at given power dissipation levels.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972.6 W PD = 1. and transverse airflow (FPM). MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE 600 600 MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE Minimum Transverse Air Flow – ft/min 500 Minimum Transverse Air Flow – ft/min 500 400 400 300 PD = 1. output loading. Determining the level of thermal management is based on factors such as power dissipation (PD). ambient temperature (TA).6 W PD = 1.4 W PD = 1. Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switching simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). The device and system application will determine the appropriate level of management. The required transverse airflow can be determined at a particular ambient temperature and device power dissipation level in order to ensure the device specifications.

TEXAS 75265 13 . FEBRUARY 1992 THERMAL INFORMATION POWER DISSIPATION vs FREQUENCY 2000 VCC = 5 V TA = 25 °C CL = 50 pF 10 Outputs Switching 1600 P – Power Dissipation – mW D 1800 1400 1200 1000 1 Output Switching 800 1 2 4 10 20 40 100 200 f – Frequency – MHz Figure 5 POST OFFICE BOX 655303 • DALLAS.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972.

TEXAS 75265 . Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 6. B. duty cycle = 50%. tr = tf = 2 ns.5 V 1.5 V 1. Equivalent loads may be used for testing. 3-STATE OUTPUTS NOTES: A.5 V VOL + 0.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972.7 V Waveform 1 S1 Closed (see Note C) ten Waveform 2 S1 Open (see Note C) 1. When measuring propagation delay times of 3-state outputs.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈0V VOH – 0.5 V 1. D.5 V 0 (see Note B) tdis Low-Level Pulse 3V 1.5 V 0 (see Note B) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input tpd In-Phase Output tpd Out-of-Phase Output (see Note D) 1.5 V VOL tpd VOH 1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES.5 V VOL Output Control (low-level enabling) ten 1. C. 5 pF for tdis.5 V 0 th 3V 1.5 V 1.5 V VOL tdis VOH 1. switch S1 is closed. E.5 V 0 (see Note B) tw High-Level Pulse 3V 1. CL includes probe and jig capacitance and is 50 pF for tpd and ten. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.5 V 1. FEBRUARY 1992 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test CL (see Note A) R2 Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS Timing Input tsu Data Input 1.5 V 1.5 V 3V 1. All input pulses have the following characteristics: PRR ≤ 1 MHz.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS 3V ≈ 2. Load Circuit and Voltage Waveforms 14 POST OFFICE BOX 655303 • DALLAS.5 V 0 tpd VOH 1.

I/O to O.25 V 200 VCC = 5 V 5 tPLH (CLK to Q) 4 tPHL (CLK to Q) 3 2 1 tPLH (I. I/O) tPLH (CLK to Q) 16 14 12 10 8 PROPAGATION DELAY TIME vs LOAD CAPACITANCE VCC = 5 V TA = 25 ° C R1 = 300 Ω R2 = 300 Ω 1 Output Switching tpd (I.75 Figure 7 Figure 8 PROPAGATION DELAY TIME vs FREE . I/O) tPHL (I.Air Temperature – ° C 75 0 4. I/O) tPHL (I.AIR TEMPERATURE 7 6 Propagation Delay Time – ns 5 4 tPHL (CLK to Q) 3 2 1 VCC = 5 V CL = 50 pF R1 = 300 Ω R2 = 300 Ω 10 Output Switching 0 25 50 TA – Free . I/O) PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 190 VCC = 4. FEBRUARY 1992 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE . I/O) 6 tpd (CLK to Q) 4 2 0 0 100 500 200 300 400 CL – Load Capacitance – pF 600 0 Figure 9 t Figure 10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 15 . I/O to O.25 180 0 25 50 TA – Free . I/O to O.AIR TEMPERATURE 220 7 6 Propagation Delay Time – ns I CC – Supply Current – mA 210 VCC = 5. I/O to O.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. I/O to O.75 V TA = 25 ° C CL = 50 pF R1 = 300 Ω R2 = 300 Ω 10 Outputs Switching 5 VCC – Supply Voltage – V 5.Air Temperature – ° C 75 pd – Propagation Delay Time – ns tPLH (I.

I/O to O. I/O to O.TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS015 – D3972. TEXAS 75265 SRPS015 . I/O) = tPLH (CLK to Q) = tPHL (CLK to Q) 7 10 1050 TA = 80 ° C TA = 25 ° C 2 1 6 7 6 3 4 5 Number of Outputs Switching 1000 1 2 4 10 20 40 100 f – Frequency – MHz Figure 11 Figure 12 16 POST OFFICE BOX 655303 • DALLAS. FEBRUARY 1992 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING 7 1200 VCC = 5 V P – Power Dissipation – mW D 6 Propagation Delay Time – ns POWER DISSIPATION vs FREQUENCY 10 . I/O) = tPHL (I.BIT COUNTER MODE 1150 5 4 1100 TA = 0 ° C 3 VCC = 5 V TA = 25 ° C CL = 50 pF R1 = 300 Ω R2 = 300 Ω 1 2 = tPLH (I.

warranty or endorsement thereof. PERSONAL INJURY. copyright. OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH. machine. and advise customers to obtain the latest version of relevant information to verify. TI assumes no liability for applications assistance or customer product design. adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Copyright © 1998. patent infringement. Texas Instruments Incorporated . that information being relied on is current and complete. Specific testing of all parameters of each device is not necessarily performed. before placing orders. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval. mask work right. and limitation of liability. is granted under any patent right. except those mandated by government requirements. In order to minimize risks associated with the customer’s applications. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. either express or implied. including those pertaining to warranty. TI does not warrant or represent that any license. or process in which such semiconductor products or services might be or are used. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement. or other intellectual property right of TI covering or relating to any combination. OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED. AUTHORIZED.

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