Chapter 1

Hardware design environments

1.1 DIGITAL SYSTEM DESIGN PROCESS 1.1.1 Design Automation 1.2 The Art of Modeling 1.3 HARDWARE DESCRIPTION LANGUAGES 1.3.1 A Language for Behavioral Descriptions 1.3.2 A Language for Describing Flow of Data 1.3.3 A Language for Describing Netlists 1.4 HARDWARE SIMULATION 1.4.1 Oblivious Simulation 1.4.2 Event Driven Simulation 1.5 HARDWARE SYNTHESIS TEST APPLICATIONS 1.6 LEVELS OF ABSTRACTION 1.7 SUMMARY

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© 1999, Z. Navabi and McGraw-Hill Inc.

A digital system design process

Design Idea

Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing

Chip or Board

• Top-down design process • Starting with a design idea • Generating a chip or board

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Result of the data path design phase.

DATA

CONTROL

REG1

REG2 Procedure for Control of Movement of Data Between Registers and Buses.

...

MAIN LOGIC UNIT

REG3

LOGIC

...

• Dataflow description • Control Data partitioning

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© 1999, Z. Navabi and McGraw-Hill Inc.

An ISPS example, a simple processor.

mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** {tc} MAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END

• Behavioral Example • Only describing functionality

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© 1999, Z. Navabi and McGraw-Hill Inc.

An AHPL example, a sequential multiplier.

AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2); 1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7]; extra <= 4$0; => ( ^dataready, dataready ) / (1, 2). 2 busy <= \1\; => ( ^ac1[3], ac1[3] ) / (4, 3). 3 extra <= ADD[1:4] (extra; ac2). 4 extra, ac1 <= \0\, extra, ac1[0:2]; count <= INC(count); => ( ^(&/count), (&/count) ) / (2, 5). 5 result = extra, ac1; done = \1\; busy <= \0\; => (1). ENDSEQUENCE CONTROLRESET(1). END.

• Dataflow description • Describing clock control timing • AHPL, A Hardware Programming Language

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© 1999, Z. Navabi and McGraw-Hill Inc.

Full-adder, logical diagram and Verilog code.
a b c g1 w1 g5 s

g2 g3 g4 w3

w2

g6 w4

co

`timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule

• Gate level structural description • Describes gate level timing • Graphical and language based descriptions
CHAPTER 1 6 © 1999, Z. Navabi and McGraw-Hill Inc.

Hardware simulation.

Hardware Description (Model)

Simulation Hardware Model

Simulation Engine Component Library (Models)

Simulation Results (Output)

Test Data (Stimuli)

• Hardware simulation process • Component models, unit model form hardware model • Testbench may provide test data

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Verifying each design stage.

Design Idea SIMULATION TOOLS Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing Product Sample. Chip or Board Final Testing Device Simulator Gate Level Simulator Dataflow Simulator Behavioral Simulator

• Simulate at each step • Simulate to verify translation into lower level • Simulation cost increases at lower levels

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© 1999, Z. Navabi and McGraw-Hill Inc.

Simulating an exclusive-OR

a

1 3

5

7 4 b 2 6

z

t a b

0

1

2

3

4

5

6

7

8

9

0

• Simulating an XOR • Apply data at given time intervals or • Apply data as events occur

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Oblivious simulation.

GATE 1 2 3 4 5 6 7

FUNCTION Input Input NOT NOT AND AND OR

INPUT 1 a b 2 1 1 4 5

INPUT 2 ----3 2 6

VALUE 0 0 1 1 0 0 0

• Table representation • Simulate until no changes are made • Record values at table entries

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© 1999, Z. Navabi and McGraw-Hill Inc.

Event driven simulation.

1 a Inp 0

3 -

5 0 AND 0

NOT

OR 2 b Inp 0 NOT 0 AND 0 4 6

0

Legend: In1 In2 Fnc Out In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value

• Linked list representation • Simulate links with input events • Record values at node entries

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most commercial tools are 2 CHAPTER 1 12 © 1999. Data Path Design Bus & Register Structure Logic Design Chip or Board • Synthesis • Transformation from one level to another • Ideal is 6.. .. Z. Manufacturing 2 Flow Graph. Pseudo Code. .. Design Idea Behavioral Design SYNTHESIS TOOLS 1 4 6 5 3 Physical Design Transistor List. Layout. .Categories of synthesis tools.. Navabi and McGraw-Hill Inc.

. Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives Synthesis Engine Logic Optimization Binding Synthesized Hardware (Netlist) • Hardware description and directives are tool inputs • Three synthesis stages • Layout or netlist is generated CHAPTER 1 13 © 1999.Synthesis process. Navabi and McGraw-Hill Inc. Z.

. c <= a + b. a b a ADDER x b y ADDER c d c • Input description affects synthesis results • Explicit specification of resource sharing • Sharing without and with extra overhead CHAPTER 1 14 © 1999. Navabi and McGraw-Hill Inc. c <= x + y. Z.Resource sharing. c <= a + b. d <= a + b.

5 ISPS 2.5 SUMMARY CHAPTER 2 1 © 1999.1 VHDL INITIATION 2.3.3.Chapter 2 VHDL Background 2.4 IDL 2.6 TEGAS 2.1 AHPL 2.2.3.3.2 Support for Design Hierarchy 2.2.2. Navabi and McGraw-Hill Inc.6 Type Declaration and Usage 2.2 EXISTING LANGUAGES 2.2.2.4 Sequential Statement 2.8 ZEUS 2. Z.7 TI-HDL 2.2.3.2.3.8 Timing Control 2.3 Library Support 2.7 Use of Subprograms 2.1 General Features 2. .3.3 VHDL REQUIREMENTS 2.3 CONLAN 2.2.5 Generic Design 2.2 CDL 2.3.9 Structural Specification 2.4 THE VHDL LANGUAGE 2.3.

Z.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs • Part of VHSIC program CHAPTER 2 2 © 1999. . Navabi and McGraw-Hill Inc.

Z.0 was defined • December 1984 : VHDL 6.0 was released Software development started • 1985 : VHDL 7.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions • 1983 DoD : Requirements were established Contract was awarded to IBM. TI. . Intermetrics ITAR restrictions removed from language • 1984 IBM. TI. Intermetrics : VHDL 2. Navabi and McGraw-Hill Inc.2 was released to IEEE ITAR removed from software • May 1985 : Standard VHDL 1076/A • December 1987 : VHDL 1076-1987 became IEEE standard • 1993 : VHDL 1076-1993 was approved CHAPTER 2 3 © 1999.

Z.Languages reviewed • AHPL • CDL • CONLAN • IDL • ISPS • TEGAS • TI-HDL • ZEUS : A Hardware Programming Language : Computer Design Language : CONsensus LANguage : Interactive Design Language : Instruction Set Processor Specification : TEst Generation And Simulation : TI Hardware Description Language : An HDL by GE corpration CHAPTER 2 4 © 1999. . Navabi and McGraw-Hill Inc.

Simulation. Synthesis. . Automatic hardware • Design Hierarchy Multi-level description Partitioning • Library Support Standard Packages Cell based design • Sequential Statements Behavioral software-like constructs CHAPTER 2 5 © 1999. Navabi and McGraw-Hill Inc. High level design. Z.VHDL Requirements • General Features Documentation. Test.

. Z. Navabi and McGraw-Hill Inc.VHDL Requirements • Generic Design Binding to specific libraries • Type Declaration Strongly typed language • Subprograms • Timing Delays. concurrency • Structural Specification Wiring components CHAPTER 2 6 © 1999.

VHDL Requirements CPU STACK ALU MUX COUNTER ALU BIT n BIT n-1 BIT 0 ALU_BIT ADDER MUX LOGIC MUX AND OR NOT • Use various levels of abstraction for defining a system • Upper level systems are partitioned into lower CHAPTER 2 7 © 1999. Z. . Navabi and McGraw-Hill Inc.

Example for hierarchical partitioning. Navabi and McGraw-Hill Inc. . Z. CPU STA CK A LU M UX COUNTER AL U BI T n BIT n-1 BIT 0 AL U_BI T A DDER M UX L OGIC M UX AND OR NOT • Recursive partitioning • Simple components as terminals CHAPTER 2 8 © 1999.

2 Design Libraries Library Management Library Environment • VHDL defines library usage • Tools define library management CHAPTER 2 9 © 1999. Navabi and McGraw-Hill Inc. 1 . LIBRARY SYSTEM . .An example VHDL environment.3 VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools VHDL Input Analyzer Lib. Z.

6 VHDL OPERATORS 3.1.8 SUMMARY CHAPTER 3 1 © 1999.3.2.1 Design to Perform 3.3.3.Chapter 3 Design Methodology Based on VHDL 3.1 ELEMENTS OF VHDL 3.1.2 Packages 3.2 Setting The Stage 3.4 Final Act 3.3 Libraries and Binding 3. Navabi and McGraw-Hill Inc.4 SUBPROGRAMS 3.2 TOP-DOWN DESIGN 3.3 Design Scenario 3.5 CONTROLLER DESCRIPTION 3.5 Real World 3. .7 CONVENTIONS AND SYNTAX 3. Z.3.1.3 TOP-DOWN DESIGN WITH VHDL 3.1 Describing Components 3.1 Verification 3.3.

Navabi and McGraw-Hill Inc. ENTITY component_name IS input and output ports. . END identifier. CHAPTER 3 2 © 1999. BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters.Interface and architectural specifications. physical and other parameters. END component_name. Z. ARCHITECTURE identifier OF component_name IS declarations.

. ARCHITECTURE structural OF component_i IS . . ARCHITECTURE dataflow OF component_i IS .. Z.. Navabi and McGraw-Hill Inc. .... .. ..... other ARCHITECTURES OF component_i . .Multiple architectural specifications.. CHAPTER 3 3 © 1999.... ENTITY component_i IS PORT (. ARCHITECTURE behavioral OF component_i IS . ) .

Packages. PACKAGE BODY package_name IS type definitions. Navabi and McGraw-Hill Inc. END package_name. sub-program declasrations. Z. sub-programs. CHAPTER 3 4 © 1999. . PACKAGE package_name IS component declarations. END package_name.

specifying parameters of a design. binding components of a library to subcomponents. Z. . END CONFIGURATION. CHAPTER 3 5 © 1999. CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. LIBRARY library_name.Design binding. Navabi and McGraw-Hill Inc.

Recursive partition procedure. END IF. Navabi and McGraw-Hill Inc. END FOR. . Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i). Z. CHAPTER 3 6 © 1999. END Partition.

SSC3n SSC41 SSC42 SSC311 SSC312 SSC3n1 SSC3n2 SUD: System Under Design SSC : System Sub-Component Shaded areas designate sub-componts with hardware implementation.Top-down design.. SUD Design Implementation SSC1 SSC2 SSC3 SSC4 SSC31 . Z. bottom-up implementation.. CHAPTER 3 7 © 1999. Navabi and McGraw-Hill Inc. .

Navabi and McGraw-Hill Inc.Verifying the first level of partitioning. Behavioral Model are mp Co SUD SSC1 SSC2 SSC3 SSC4 Interconnection of Behavioral Models CHAPTER 3 8 © 1999. Z. .

Z. Behavioral Model are omp C SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model CHAPTER 3 9 © 1999.Verifying hardware implementation. Navabi and McGraw-Hill Inc. .

.Verifying the final design. Z.. . SSC3n SSC41 SSC42 SSC311 SSC312 CHAPTER 3 10 © 1999. Navabi and McGraw-Hill Inc. Behavioral Model e par Com SUD SSC1 SSC2 SSC3 SSC4 Har dwa re M odel SSC31 .

Behavioral Model SSC3 Co m pa re SSC31 . Z. SSC3n1 SSC3n2 Hardware Model CHAPTER 3 11 © 1999... ...Verifying hardware implementation of SSC3. SSC3n SSC311 SSC312 . Navabi and McGraw-Hill Inc.

Z. .Verifying the final design. CHAPTER 3 12 © 1999. Navabi and McGraw-Hill Inc. an alternative to the setup of Figure 3.9. p Com are SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model SSC41 SSC42 Verifying the final design.

result ready CHAPTER 3 13 © 1999. Navabi and McGraw-Hill Inc. .Serial adder. a b start clock Synchronously add data on a and b put result on result. Z.

.Available library elements. Navabi and McGraw-Hill Inc. Z. 1R S1 1D Z 1D C1 Q _ 1D (a) Multiplexer (b) Flipflop CHAPTER 3 14 © 1999.

. data1.Multiplexer library element. data0 : IN BIT. END mux2_1. END dataflow. Navabi and McGraw-Hill Inc. z : OUT BIT). PORT (sel. ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). Z. CHAPTER 3 15 © 1999. -ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay. VHDL model of the multiplexer library element.

Z.Dataflow descriptions. Navabi and McGraw-Hill Inc. Busb Reg File Reg1 Alu Controller Reg2 Busa Dataflow descriptions. . CHAPTER 3 16 © 1999.

-ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset. END PROCESS. END IF. Navabi and McGraw-Hill Inc. END flop. VHDL model of the flip-flop library element. Z. END behavioral.Flip-flop library element. CHAPTER 3 17 © 1999. td_in : TIME := 8 NS). ENTITY flop IS GENERIC (td_reset. din. END IF. PORT (reset. . ELSE qout <= din AFTER td_in. qout : BUFFER BIT := '0'). clk : IN BIT.

CHAPTER 3 18 © 1999.Behavioral descriptions. Valid ? Transmit . Behavioral descriptions. . Navabi and McGraw-Hill Inc. . Receive FOR all data : Process data : Queue data : END FOR. Z. .

Divide by 8. ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS). counting : OUT BIT := '0'). IF count = limit THEN counting <= '0' AFTER td_cnt. CONSTANT limit : INTEGER := 8. END PROCESS. Z. END counter. END IF. ELSE IF count < limit THEN count := count + 1. Divide by 8. . END IF. END IF. Navabi and McGraw-Hill Inc. counter. PORT (reset. ELSE counting <= '1' AFTER td_cnt. CHAPTER 3 19 © 1999. END IF. counter. BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0. -ARCHITECTURE behavioral OF counter IS BEGIN PROCESS (clk) VARIABLE count : INTEGER := limit. clk : IN BIT. END behavioral.

. Navabi and McGraw-Hill Inc. VHDL Boolean p r e d e s i g n e d layouts Synthesize l i b r a r y mux2-1 Count flop CMOS layout CHAPTER 3 20 © 1999. Z.Design stage setting.

b. CHAPTER 3 21 © 1999. result <= sum & result (7 DOWNTO 1). ready : OUT BIT. ELSE ready <= '0'. END IF. END IF. END PROCESS. ENTITY serial_adder IS PORT (a. IF count = 8 THEN ready <= '1'. clock : IN BIT. END IF. END serial_adder. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). sum := a XOR b XOR carry. END IF. Navabi and McGraw-Hill Inc. start. carry := '0'. carry := (a AND b) OR (a AND carry) OR (b AND carry). . Serial adder behavioral description.Serial adder behavioral description. END behavioral. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. Z. ELSE IF count < 8 THEN count := count + 1. VARIABLE sum. carry : BIT. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) VARIABLE count : INTEGER := 8.

CHAPTER 3 22 © 1999. Z. .VHDL simulation results. Navabi and McGraw-Hill Inc.

. Z. carry := (a AND b) OR (a AND carry) OR (b AND carry ). CHAPTER 3 23 © 1999. ELSE IF count < 8 THEN count := count + 1.Partial code of serail_adder. END IF. result <= sum & result (7 DOWNTO 1). Navabi and McGraw-Hill Inc. sum := a XOR b XOR carry.

Navabi and McGraw-Hill Inc. . counting counter serial_sum en si a b Adder carry_out Flop result Shift Regiser carry_in clock CHAPTER 3 24 © 1999.General layout of serial_adder. Z.

First level of partitioning. Z. Navabi and McGraw-Hill Inc. serial_adder full_adder flip_flop shifter counter CHAPTER 3 25 © 1999. .

ENTITY fulladder IS PORT (a. Navabi and McGraw-Hill Inc. . CHAPTER 3 26 © 1999. sum. cout <= (a AND b) OR (a AND cin) OR (b AND cin). cout : OUT BIT). Z. END fulladder.Full_adder description. cin : IN BIT. b. END behavioral. -ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin.

clk : IN BIT. reset. CHAPTER 3 27 © 1999. END shifter. Z. Navabi and McGraw-Hill Inc. END BLOCK. END dataflow. . -ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED. ENTITY shifter IS PORT (sin. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)).Shifter VHDL description. enable.

.Completed parts of first partitioning. serial_adder full_adder flop shifter counter CHAPTER 3 28 © 1999. Navabi and McGraw-Hill Inc. Z.

b. din. serial_sum. CHAPTER 3 29 © 1999. reset. td_in : TIME := 8 NS).Structural description of serial_adder. qout : BUFFER BIT := '0'). counting. cin : IN BIT. start. . clock. COMPONENT fulladder IS PORT (a. start. sum. counting : OUT BIT := '0'). END COMPONENT. BEGIN u1 : fulladder PORT MAP (a. END serial_adder. END structural. clk : IN BIT. carry_in). u3 : counter PORT MAP (start. ready : OUT BIT. clk : IN BIT. -SIGNAL serial_sum. u2 : flop PORT MAP (start. PORT (reset. ENTITY serial_adder IS PORT (a. carry_out). COMPONENT shifter IS PORT (sin. b. Navabi and McGraw-Hill Inc. result). END COMPONENT. clock : IN BIT. u5 : ready <= NOT counting. carry_in. enable. cout : OUT BIT). END COMPONENT. b. clock. END COMPONENT. carry_in. counting : BIT. clk : IN BIT. carry_out. clock. -ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS). parout : BUFFER BIT_VECTOR(7 DOWNTO 0)). counting). PORT (reset. COMPONENT flop IS GENERIC (td_reset. u4 : shifter PORT MAP (serial_sum. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). Z. carry_out.

Navabi and McGraw-Hill Inc. .Signal mapping for fulladder instantiation. Z. Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out a b cin sum count Signals in the interface of fulladder CHAPTER 3 30 © 1999.

din . carry_in. b. clk : IN BIT.Interconnecting ports. carry_out. clock. u2 : flop PORT MAP (start. COMPONENT fulladder IS PORT (a. sum. cout : OUT BIT). cin : IN BIT. carry_in. . BEGIN u1 : fulladder PORT MAP (a. carry_out ). counting : BIT. carry_in). Navabi and McGraw-Hill Inc. -SIGNAL serial_sum. td_in : TIME := 8 NS). Z. carry_out . serial_sum. COMPONENT flop IS GENERIC (td_reset. qout : BUFFER BIT := '0'). END COMPONENT. END COMPONENT. PORT (reset. b. CHAPTER 3 31 © 1999.

.Partitioning shifter. shifter der_flop der_flop der_flop der_flop der_flop der_flop der_flop der_flop CHAPTER 3 32 © 1999. . Z. . . Navabi and McGraw-Hill Inc.

. ELSE IF enable = '1' THEN qout <= din. ENTITY der_flop IS PORT (din. END IF. END PROCESS. reset.Behavioral model of der_flop. -ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'. END IF. Z. END behavioral. qout : OUT BIT := '0'). clk : IN BIT. CHAPTER 3 33 © 1999. END der_flop. Navabi and McGraw-Hill Inc. enable. END IF.

parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). -ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din. enable. b5 : der_flop PORT MAP (parout(6). reset. END COMPONENT. enable. enable. b0 : der_flop PORT MAP (parout(1). ENTITY shifter IS PORT (sin. parout(0)). Navabi and McGraw-Hill Inc. clk. reset. clk : IN BIT. parout(5)). reset. b3 : der_flop PORT MAP (parout(4). enable. parout(3)). b1 : der_flop PORT MAP (parout(2). enable. END shifter. reset. enable. b4 : der_flop PORT MAP (parout(5). enable. reset. parout(1)). clk : IN BIT. END structural. parout(7)). reset. b6 : der_flop PORT MAP (parout(7). clk. enable. parout(2)). reset.Structural description of shifter. CHAPTER 3 34 © 1999. clk. clk. . clk. BEGIN b7 : der_flop PORT MAP ( sin. reset. clk. b2 : der_flop PORT MAP (parout(3). clk. Z. parout(6)). reset. reset. clk. parout(4)). enable. enable. qout : BUFFER BIT := '0').

Navabi and McGraw-Hill Inc.Hardware realization of der_flop. . Z. enable reset din S1 1D qout 1R 1D C1 Q dff_in _ 1D clock CHAPTER 3 35 © 1999.

Z.Partitioning der_flop. der_flop mux2_1 flop CHAPTER 3 36 © 1999. . Navabi and McGraw-Hill Inc.

z : OUT BIT). COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). data0 : IN BIT. clk : IN BIT. BEGIN mx : mux2_1 PORT MAP (enable. qout). SIGNAL dff_in : BIT. data1. END COMPONENT. . ff : flop PORT MAP (reset. reset. clk. ENTITY der_flop IS PORT (din. qout : BUFFER BIT := '0'). -ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset. din. dff_in). dff_in.Structural description of der_flop. END COMPONENT. qout : BUFFER BIT). Navabi and McGraw-Hill Inc. Z. din. PORT (reset. clk : IN BIT. PORT (sel. END der_flop. END behavioral. enable. qout. CHAPTER 3 37 © 1999. td_in : TIME := 8 NS).

. Z. . . .Complete design of seraial_adder. Navabi and McGraw-Hill Inc. . mux2-1 flop . CHAPTER 3 38 © 1999. . serial-adder fulladder flop shifter counter der-flop der-flop . . der-flop .

. 1 s1 ..Final Design. . . CHAPTER 3 39 © 1999. . . . reset Counter counting . 1 1R Q 1D C1 carry_in 1R 1D C1 C1 C1 Q carry_out clk . Z. a b Fulladder serial-sum 1 s1 1 1R Q 1D 1R Q 1D 1 s1 1 .. . Navabi and McGraw-Hill Inc.

END PROCESS. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8. carry := (a AND b) OR (a AND carry) OR (b AND carry). ELSE IF count < 8 THEN count := count + 1. start. b. Navabi and McGraw-Hill Inc. ELSE ready <= '0'. CHAPTER 3 40 © 1999. IF count = 8 THEN ready <= '1'. VARIABLE sum. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). VARIABLE count : CNT8 := 8. carry : BIT. result <= sum & result (7 DOWNTO 1). END IF. END serial_adder. END IF. END behavioral. END IF. Z. ready : OUT BIT.Synthesizable serial adder. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. clock : IN BIT. carry := '0'. sum := a XOR b XOR carry. . END IF. ENTITY serial_adder IS PORT (a.

FPGA layout of serial_adder. . Navabi and McGraw-Hill Inc. Z. CHAPTER 3 41 © 1999.

END byte_to_integer. oi := result. PROCEDURE byte_to_integer (ib : IN byte. END LOOP. TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT. Z. BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i.. oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0. . CHAPTER 3 42 © 1999. Navabi and McGraw-Hill Inc.. END IF. .Type conversion procedure.

sc(0) := (a AND b) OR (a AND c) OR (b AND c). RETURN sc. b. c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0). Navabi and McGraw-Hill Inc. END. BEGIN sc(1) := a XOR b XOR c. CHAPTER 3 43 © 1999. FUNCTION fadd (a.The fadd (full adder) function. Z. .

fulladder using fadd. b. sum. ENTITY fulladder IS PORT (a. Navabi and McGraw-Hill Inc. b. END fulladder. CHAPTER 3 44 © 1999. cout) <= fadd (a. -ARCHITECTURE behavioral OF fulladder IS BEGIN (sum. Z. cout : OUT BIT). . cin). cin : IN BIT. END behavioral.

General outline of a controller. Z... x= . . z1 . . . .. xn z<= . . Navabi and McGraw-Hill Inc. . . . . . zn z<= . z<= . clock CHAPTER 3 45 © 1999.. . . x1 x= .

Navabi and McGraw-Hill Inc. .Moore machine description. Z. IF 110 sequence is detected on x THEN z gets '1' x ELSE z gets '0' END. z clk CHAPTER 3 46 © 1999.

Navabi and McGraw-Hill Inc.Sequence detector state machine. . 0 1 1 reset 0 0 0 got1 0 1 got11 0 1 0 got110 1 CHAPTER 3 47 © 1999. Z.

VHDL Description of 110 detector. END PROCESS. END IF. -ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset. END IF. clk : IN BIT . WHEN got110 => IF x = ‘1’ THEN current <= got1. ELSE current <= got110. . ELSE current <= reset. got1. END moore_110_detector. ELSE current <= reset. SIGNAL current : state := reset. CHAPTER 3 48 © 1999. WHEN got11 => IF x = ‘1’ THEN current <= got11. WHEN got1 => IF x = ‘1’ THEN current <= got11. z <= ‘1’ WHEN current = got110 ELSE ‘0’. END IF. BEGIN PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1. ENTITY moore_110_detector IS PORT (x. Z. END behavioral. ELSE current <= reset. got110). END CASE. END IF. END IF. got11. z : OUT BIT). Navabi and McGraw-Hill Inc.

.State transition and corresponding VHDL code... CHAPTER 3 49 © 1999.. WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset. . Z.. 1 reset 0 0 got1 0 got11 0 . Navabi and McGraw-Hill Inc. END IF.

REAL Same Type REM INTEGER Same Type ABS MISCELLENEOUS ** Numeric Left: Numeric Right: Integer Same Type Same as Left CHAPTER 3 50 © 1999. Navabi and McGraw-Hill Inc. Z.VHDL operators. Operators AND NAND XOR = < > SLL SLA ROL + OR NOR XNOR /= <= >= SRL SRA ROR & Operand Type BIT or BOOLEAN All Types Left: BIT or BOOLEAN Vector Right: INTEGER Numeric Array or Array Element Numeric Result Type BIT or BOOLEAN BOOLEAN LOGICAL RELATIONAL SHIFT BOOLEAN ADDING Same Type SIGN + - Same Type * MULTIPLYING MOD / INTEGER. .

A C I E T R d m O e a p IS R HT C U E e o F z m le S IGNAL a. E Dd m . b. . Navabi and McGraw-Hill Inc. N e o architecture declarative_part architecture body architecture statem n e t_part CHAPTER 3 51 © 1999. Z. c : B := '0'.Syntax details of the architecture body. = O FE S c <= a AFTER 10 NS. FE 5 S b< N TaA T R5N . IT B G E IN a <= '1' A T R1 N .

3.1 Concurrent Assignments 4.3 Modeling Hardware 4.1. .2 Concurrency 4.1 Inertial Delay Mechanism 4.4.1 Timing 4.1.4.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS 4.2 Events and Transactions 4.3.2 Transport Delay Mechanism 4.5 SUMMARY CHAPTER 4 1 © 1999.4.4. Z.3.Basic Concepts in VHDL 4.4 Sequential Placements of Transactions 4.2 OBJECTS AND CLASSES 4.1 CHARACTERIZING HARDWARE LANGUAGES 4.3 Comparing Inertial and Transport 4.3 SIGNAL ASSIGNMENTS 4.1.3 Delta Delay 4. Navabi and McGraw-Hill Inc.

Z. • What happens in a real hardware • Must be able to model properly CHAPTER 4 2 © 1999. Navabi and McGraw-Hill Inc. .Value transfer through wires.

a := x.Value transfer through wires. Z. Navabi and McGraw-Hill Inc. b <= x AFTER 3*unit_delay. • In one case immediate assignemnts are done • In another case scheduling is done CHAPTER 4 3 © 1999. a <= x AFTER 4*unit_delay. . b := x.

Z.Describing sub-components. S A B C • Hardware description requires concurrent constructs • Concurrent bodies can be described behaviorally or at the dataflow level CHAPTER 4 4 © 1999. . Navabi and McGraw-Hill Inc.

A VHDL concurrent body • A VHDL concurrent body • Statements are executed when events occur CHAPTER 4 5 © 1999. Navabi and McGraw-Hill Inc. Z. .

IF THEN ELSE . END PROCESS . ... PROCESS . .A VHDL sequential body ARCHITECTURE sequential . Z. BEGIN . FOR LOOP . END ARCHITECTURE • A VHDL sequential body • Statements are executed when program flow reaches them CHAPTER 4 6 © 1999.. BEGIN . ... .. Navabi and McGraw-Hill Inc. ... . .

a b g2 x z g4 c g1 w g3 y • Four concurrent gates • Each has a delay of 12 ns • Change in inputs may result in in output hazards CHAPTER 4 7 © 1999. Navabi and McGraw-Hill Inc. Z. .Illustrating timing and concurrency.

g1 g2 g3 g4 R a tin e c g R a tin e c g R a tin e c g R a t e c ing R a tin e c g 0 12 24 36 Nanosecond • a changes from ‘1’ to ‘0’ • A change in the a input results in domino changes each 12 ns apart • No more events occur when output is reached CHAPTER 4 8 © 1999.Gates reacting to changes. Z. . Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. . Z.a b c w x y z 0 12 24 36 Nanosecond • Timing diagram resulting from input a changing from ‘1’ to ‘0’ at time zero • A glitch appears on the output • Must model hardware to imitate this behavior • Requires timing and concurrency in the language CHAPTER 4 9 © 1999.

.... z_signal • Objects and classes in sequential and concurrent bodies • Foundation for modeling timing and concurrency are signals • Variables are used as software variables CHAPTER 4 10 © 1999. Z. Navabi and McGraw-Hill Inc. y_signal z_signal <= ..Objects and Classes del1_constant del2_constant concurrent_body_1 sequential_body_1 a_signal a_variable := .. ... b_signal y_signal <= . w_signal v_signal concurrent_body_3 u_signal <= local_constant v_signal <= .. w_signal <= ... x_signal y_signal <= .. loop_variable_i .... u_signal concurrent_body_2 x_signal <= ..

Objects and Classes Using Objects In VHDL O B J E C T Signal Variable Constant File BODY Declare YES NO YES YES Concurrent Assign to YES NO --Use YES YES YES YES Declare NO YES YES YES Sequential Assign to YES YES --Use YES YES YES YES • Objects in VHDL bodies • Cannot declare signals in sequential bodies • Variable assignments are only done in sequential bodies CHAPTER 4 11 © 1999. Navabi and McGraw-Hill Inc. Z. .

This is a comment BEGIN -. target2. SIGNAL target1. ‘1’ AFTER 79 NS. ‘0’ AFTER 47 NS. -. ‘0’ AFTER 35 NS. Reject and Transport • Inertial: rejects anything less than its delay • Reject: rejects anything less than or equal to its reject • Transport: does not reject CHAPTER 4 12 © 1999. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. SIGNAL diff12. ‘1’ AFTER 41 NS. END delay.Creating waveform waveform <= ‘1’ AFTER 03 NS. ‘0’ AFTER 08 NS. target3 : BIT. Z. -. .Delay Mechanisms ENTITY example IS END ENTITY. ‘0’ AFTER 58 NS.Illustrating inertial delay target1 <= waveform AFTER 5 NS. diff23 : BIT. • VHDL description for the demonstration of delay mechanisms • Example shows several concurrent statements • Inertial. ‘0’ AFTER 77 NS. ‘1’ AFTER 62 NS. -. -. ‘0’ AFTER 68 NS. ‘1’ AFTER 33 NS. diff13.Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS. ‘0’ AFTER 27 NS. Navabi and McGraw-Hill Inc. ‘0’ AFTER 18 NS. ‘1’ AFTER 71 NS. diff13 <= target1 XOR target3. ‘1’ AFTER 14 NS. ‘1’ AFTER 52 NS. diff23 <= target2 XOR target3.Comparing targets diff12 <= target1 XOR target2. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. ‘1’ AFTER 24 NS. ‘0’ AFTER 85 NS.

Navabi and McGraw-Hill Inc. . Z.Delay Mechanisms R Target 1 or Target 2 C • The RC delay is best represented by inertial delay mechanism • This is a simple version of Inertial • For more accurate modeling Reject can be used CHAPTER 4 13 © 1999.

. Z.Delay Mechanisms 5 6 4 6 3 6 2 6 6 5 6 4 6 3 6 2 6 • Illustrating differences between delay mechanism in VHDL • Positive and negative pulses appear on the LHS CHAPTER 4 14 © 1999. Navabi and McGraw-Hill Inc.

z : OUT BIT).Concurrency ENTITY figure_5_example IS PORT (a. END concurrent. Z. • VHDL description for the gate level circuit for the demonstration of timing and concurrency • Four concurrent statements model gates of the circuit • Events of the RHS cause evaluation and scheduling • A scheduled value may or may not appear on the LHS • A scheduled value is a transaction on the driver of the LHS signal CHAPTER 4 15 © 1999. c : IN BIT. ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w. END figure_5_example. x. z <= x OR y AFTER 12 NS. . y : BIT. BEGIN w <= NOT a AFTER 12 NS. x <= a AND b AFTER 12 NS. y <= c AND w AFTER 12 NS. b. Navabi and McGraw-Hill Inc.

.Concurrency Resolution Function Multiple Driving Values Signal Value • A signal may have more than one driver • Resolving a single value from multiple driving values • Each driver has its own timing • Independent handling of all drivers • A driving value that is current contributes to the resolution function CHAPTER 4 16 © 1999. Z. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. d-t ) 0 EXPIRED 0 t t 0 t1 d tri = (v. d) d-t0 tri = (v. Z.Events and Transactions transaction time component d tri = (v. 0) now • A transaction. . from being created to being expired • A transaction that expires generates a current driving value • This value contributes to the resolution function CHAPTER 4 17 © 1999.

c : BIT := '0'. END demo. BEGIN a <= '1' AFTER 15 NS. b <= NOT a AFTER 5 NS. • A simple description for illustrating events and transactions • Transactions are scheduled on the 3 LHS signals • Order is not significant • Initial transaction are placed on all 3 signals CHAPTER 4 18 © 1999. c <= a AFTER 10 NS. Z. b. Navabi and McGraw-Hill Inc.Events and Transactions ARCHITECTURE demo OF example IS SIGNAL a. .

Events and Transactions a 0 0 0 b c 0 5 10 (a) 15 20 25 NS Transactions W hen They Are Placed on Signals (1. . Z. Navabi and McGraw-Hill Inc. 15) on a (1. 05) on b (0. 10) on c (1. 05) on b (0. 10) on c 0 5 10 (b) 15 20 25 NS Transactions At 5 NS Intervals a c b a c a c b c 0 5 10 (c) 15 20 25 NS Path Of Transactions To Expiration a c b b NS c 0 5 10 15 20 25 • Events and transactions (d) CHAPTER 4 19 © 1999.

Delta Delay ENTITY timing IS PORT (a. -ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z. z <= a AND b AFTER 10 NS. Z. END ENTITY. • Demonstrating need for delta delay • A “hidden” delay exists between z and z_bar • Delta delay makes us believe that they take place at the same real time • The hidden delay is Delta which is not real-time CHAPTER 4 20 © 1999. Navabi and McGraw-Hill Inc. z. . END delta. b : IN BIT. zbar : BUFFER BIT).

BEGIN y <= c AND w. Navabi and McGraw-Hill Inc. x <= a AND b. w <= NOT a. END not_properly_timed.Delta Delay ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w. z <= x OR y AFTER 36 NS. Z. x. y : BIT := '0'. same exact real time CHAPTER 4 21 © 1999. . • VHDL description for demonstrating the delta delay • Sequentiality in execution.

Navabi and McGraw-Hill Inc. we do not see Sequentiality CHAPTER 4 22 © 1999. Z. .Delta Delay a1 b1 c1 w0 x0 y 0 z1 0 1 2δ 3δ 0 δ 12 24 36 NS • Timing diagram showing delta delays • Looking at real times.

c <= NOT b. b <= NOT a.Delta Delay ARCHITECTURE concurrent OF timing_demo IS SIGNAL a. END concurrent. . c : BIT := '0'. Z. transactions and concurrency CHAPTER 4 23 © 1999. BEGIN a <= '1'. • Description for a chain of two inverters • Demonstrating Delta. b. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z.Delta Delay a 0 b0 c 0 0 δ 1 2δ 3δ 0 NS • Timing diagram for timing_demo • Everything happens at real-time 0 CHAPTER 4 24 © 1999. .

y <= NOT x. ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’. Z. . x 0 0 1δ 2δ 3δ 4δ 5δ 6δ 7δ 0 t y 1 0 1δ 2δ 3δ 4δ 5δ 6δ 0 t • Oscillation in zero real time • Don’t try this at home CHAPTER 4 25 © 1999.Delta Delay y x Ideal elements with zero real time delay. Navabi and McGraw-Hill Inc. END forever. BEGIN x <= y. SIGNAL y: BIT := ‘1’.

. BEGIN PROCESS x<= v1 AFTER t1. • Sequential placement of transactions in a sequential body of VHDL • A wait. Z. END sequential. statement suspends a sequential body forever • Sequentially values are placed on the LHS CHAPTER 4 26 © 1999. END PROCESS.Sequential Placement of Transactions ARCHITECTURE sequential OF sequential_placement IS . WAIT. .. Navabi and McGraw-Hill Inc. x<= v2 AFTER t2.

v2 AFTER t2-t1 x <= a AFTER t2.Sequential Placement of Transactions ARCHITECTURE concurrent OF sequential_placement IS . BEGIN a <= v1.. END concurrent. Navabi and McGraw-Hill Inc.. . • Sequential placement of transaction in a concurrent body of VHDL • Same effect as the above process statement CHAPTER 4 27 © 1999. Z.

Z.Sequential Placement of Transactions • Projected output waveform • A new transaction will be compared with all existing transactions • It appends. Navabi and McGraw-Hill Inc. . or overrides existing ones CHAPTER 4 28 © 1999.

.Sequential Placement of Transactions • Multiple drivers of a resolved signal • Each driver timing is treated independently CHAPTER 4 29 © 1999. Navabi and McGraw-Hill Inc. Z.

Navabi and McGraw-Hill Inc.Sequential Placement of Transactions TRANSPORT 1 New Transaction is BEFORE Already Existing Overwrite existing transaction 3 INERTIAL Overwrite existing transaction 2 New Transaction is AFTER Already Existing Append the new transaction. Difference between time of new and existing is greater than the reject value v /=v existing new 5 Append the new transaction Difference between time of new and existing is less than or equal to reject value v /=v existing new 6 Overwrite existing transaction • Effective transactions on the driver of a signal • Multiple transactions are sequentially placed on the signal driver CHAPTER 4 30 © 1999. . Z. v = v existing new 4 Append the new transaction.

Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := ‘Z’. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one. END sequential. Z. x <= TRANSPORT ‘0’ AFTER 3 NS. CHAPTER 4 31 © 1999. . END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. WAIT.

END sequential. Z. WAIT. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. CHAPTER 4 32 © 1999.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. Navabi and McGraw-Hill Inc. . x <= TRANSPORT ‘0’ AFTER 8 NS. END PROCESS. x z z 1 0 7 8 9 0 1 2 3 4 5 6 • Appending transactions • Delay type is transport • The new transaction is after the existing one.

END PROCESS. END sequential. . WAIT. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. Z. x <= ‘0’ AFTER 3 NS. Navabi and McGraw-Hill Inc. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one CHAPTER 4 33 © 1999.Sequential Placement of Transactions ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := ‘Z’.

Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. x <= ‘0’ AFTER 8 NS. Navabi and McGraw-Hill Inc. END PROCESS. . Z. BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS. WAIT. x z z 0 7 8 9 0 1 2 3 4 5 6 • Saving previous transactions of same value • Transactions with the same value are both kept on the driver of x CHAPTER 4 34 © 1999. END sequential.

x Z z Z 1 0 0 1 2 3 4 5 6 7 8 9 • Appending the new transaction of different value • Time difference of new and existing is greater than reject value CHAPTER 4 35 © 1999.Sequential Placement of Transactions ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=’Z’. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. Z. Navabi and McGraw-Hill Inc. WAIT. END PROCESS. . x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS. END sequential.

. WAIT. Z. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=’Z’. END sequential x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions of different value • The new transaction is scheduled after the existing. and has a different value CHAPTER 4 36 © 1999. x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS. END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS.

and transport delay mechanisms • This is a result of sequential placement of transactions CHAPTER 4 37 © 1999. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. '1' AFTER 33 NS. . Navabi and McGraw-Hill Inc. Z.Signal assignments target1 <= waveform AFTER 5 NS. '1' AFTER 14 NS. target2. BEGIN -. 0 3 5 8 14 18 24 27 29 32 33 35 38 40 • Pulse rejection in inertial. '0' AFTER 35 NS. SIGNAL target1.Creating waveform waveform <= '1' AFTER 03 NS. reject. target3 : BIT. END delay. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. '1' AFTER 24 NS. '0' AFTER 18 NS. target3 <= TRANSPORT waveform AFTER 5 NS. -.Sequential Placement of Transactions ENTITY example IS END ENTITY. '0' AFTER 27 NS. '0' AFTER 08 NS.

5) (1.5) (0.0) (0.0) (0.5) (0.0) (0.0) (1.5) (0.5) (1.0) (1. pending.0) (0.5) (0.2) (0.5) (1.5) (0.1) (1.5) (1.CHAPTER 4 (1.5) (0.5) (0. and expired transactions on targets of example 38 5 8 13 14 18 19 23 24 27 29 (1.5) (1.0) (0.0) (1.3) (1.2) (0.0) (0.3) (0.0) (1.0) (1.1) (1.3) (0.5) (1.0) (0.5) (1.0) (1.3) (0.5) (0.2) target1 (1.2) (0.5) (0.3) (0.5) (0.5) (1.5) (1.5) (1.0) (1.5) (0.5) (0.0) (1.0) (1.5) (0.0) (1. Navabi and McGraw-Hill Inc.5) (0.5) (0.2) target3 © 1999.0) (1.3) (0.2) target2 Sequential Placement of Transactions • New.1) (1.0) (1.3) (1.0) (1. 0 3 32 33 35 38 40 . Z.5) (1.

-ARCHITECTURE delay OF example IS SIGNAL a. a AFTER 3 NS.Sequential Placement of Transactions ENTITY example IS END ENTITY.Signal assignments a <= '1' AFTER 5 NS. END delay. Z. '1' AFTER 15 NS. b : BIT. Navabi and McGraw-Hill Inc. BEGIN -. • Sequential placement of transactions by executing concurrent signal assignments • Events on a cause placement of transactions on b • In a waveform. . all but the first are TRANSPORT CHAPTER 4 39 © 1999. b <= '0'. '0' AFTER 10 NS.

2.1 Sequential Comparator 5.4 MODELING A TEST BENCH 5.6 BINDING ALTERNATIVES 5. Zainalabedin Navabi .1 VHDL Description of A Simple Test Bench 5.3.2 NAND Gate Models 5.1.1.2.1 Logic Design of Comparator 5.4.2 Byte Latch 5.4.CHAPTER 5 STRUCTURAL SPECIFICATION OF HARDWARE 5.1 Inverter Model 5.2 VHDL Description of a 4-Bit Comparator 5.3 WIRING ITERATIVE NETWORKS 5.1 Design of a 4-Bit Comparator 5.2 WIRING OF PRIMITIVES 5.6.6.1 PARTS LIBRARY 5.7 SUMMARY CHAPTER 5 1 © 1999.6.3.3 Byte Comparator 5.6 TOP-DOWN WIRING 5.2 VHDL Description of bit_comparator 5.2 Simulation 5.

(c) inv i1 o1 (d) • • • • • Inverter Symbol Entity declaration Architecture body Notation.Parts Library (a) ENTITY inv IS PORT (i1 : IN BIT. (b) ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS. o1 : OUT BIT). END single_delay. END inv. CHAPTER 5 2 © 1999. Zainalabedin Navabi .

Parts Library ENTITY inv IS PORT ( entity declaration i1 : IN BIT . interface_signal_declaration interface_signal_declaration port clause • Details of the entity declaration of inverter • Port clause • Interface signal declaration CHAPTER 5 3 © 1999. Zainalabedin Navabi . o1 : OUT BIT ) . END inv.

Parts Library entity_name Interface Aspect Input Port Output Port Bidirectional Port Buffer Port • • • • • CHAPTER 5 Elements of aspect notation Input Output Inout Buffer is output that can be used on RHS 4 © 1999. Zainalabedin Navabi .

Buffers • Inout implies In and Out (two wires) • Buffer can be used inside an architecture CHAPTER 5 5 © 1999. Outputs. Inputs.Parts Library • Using ports. Bi-directional ports. Zainalabedin Navabi .

Parts Library (a) ENTITY nand2 IS PORT (i1. (b) ARCHITECTURE single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 5 NS. (c) nand2 i1 i2 (d) o1 • Two-input NAND symbol • Entity declaration • Architecture body uses NAND operator CHAPTER 5 6 © 1999. o1 : OUT BIT). Zainalabedin Navabi . END single_delay. END nand2. i2 : IN BIT.

Parts Library PORT ( i1. i2 : IN BIT . Zainalabedin Navabi . o1 : OUT BIT ) identifier_list mode type interface signal declaration port clause interface list interface_signal_declaration • Port clause details for nand2 • Signal declaration includes identifier list • Mode and type are the same as those of the inverter CHAPTER 5 7 © 1999.

Parts Library (a) ENTITY nand3 IS PORT (i1. i3 : IN BIT. (b) ARCHITECTURE single_delay OF nand3 IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS. END nand3. END single_delay. Zainalabedin Navabi . o1 : OUT BIT). i2. (c) i1 i2 i3 nand3 o1 • Three-input NAND symbol • Architecture body and notation are shown • Must use AND and NOT CHAPTER 5 8 © 1999.

Zainalabedin Navabi .Wiring Components Comparator A B A>B A=B > = < A<B • Logical symbol of a single bit comparator • Cascadable comparator • Will design one bit and cascade CHAPTER 5 9 © 1999.

b = 0 1 1 a=b 1 00 01 11 10 a. b > 0 1 1 1 a>b 00 01 11 10 1 1 a. b < 0 1 1 00 01 1 1 a<b 1 11 10 • Karnaugh maps for the outputs of the single bit comparator • Each output depends on data inputs and its corresponding control input CHAPTER 5 10 © 1999.Wiring Components a. Zainalabedin Navabi .

(a’ . b a_gt_b = ((a . b . lt + a’ .Wiring Components a_gt_b = a . Zainalabedin Navabi . b’ a_eq_b = a . b’)’)’ a_eq_b = ((a . b’ . eq)’. b .( b’ . lt)’. lt)’. eq)’)’ a_lt_b = ((a’ . gt + a . gt)’. eq + a’ . b)’)’ • Boolean expression for the outputs • Use DeMorgan’s for all-NAND implementation CHAPTER 5 11 © 1999. lt + b . gt + b’ . b’ .( a’ . gt)’. eq a_lt_b = a’ .(b .( a .

Wiring Components a gt a_gt_b b a b eq a_eq_b a a_lt_b lt b • Logic diagram of bit_comparator • Using only our primitive components CHAPTER 5 12 © 1999. Zainalabedin Navabi .

-. gt.equal -.Wiring Components bit_comparator a b gt eq lt a_gt_b a_eq_b a_lt_b (a) ENTITY bit_comparator IS PORT (a. END bit_comparator.data inputs -.greater -.previous equal -.previous less than -.previous greater than -. eq. b. a_lt_b : OUT BIT). a_eq_b. Zainalabedin Navabi . a_gt_b.less than (b) • Interface description of bit_comparator • Inputs and outputs of BIT type are declared CHAPTER 5 13 © 1999. lt : IN BIT.

Zainalabedin Navabi .Wiring Components bit_comparator (gate_level) a nand2 i1 i2 o1 im3 nand2 i1 i2 o1 im4 i1 i2 i3 nand3 o1 a_gt_b b inv i1 o1 im2 i1 i2 nand2 o1 im5 gt i1 i2 i3 nand3 o1 nand2 nand3 o1 im7 i1 i2 o1 a_eq_b im6 eq lt i1 i2 i3 nand2 i1 i2 o1 im8 inv i1 o1 im1 i1 i2 nand2 o1 im9 i1 i2 i3 nand3 o1 a_lt_b nand2 i1 i2 o1 im10 • Composition Aspect of bit_comparator. CHAPTER 5 14 © 1999.

Zainalabedin Navabi . END COMPONENT. im7). im7. im6). -. a_gt_b). a_lt_b). im8). im10. COMPONENT n3 PORT (i1. im2. im2). im1). im3). im3.nand2 (single_delay).Intermediate signals SIGNAL im1. i2.a_lt_b output g9 : n2 PORT MAP (im1. im9. g12 : n3 PORT MAP (im8. -. FOR ALL : n1 USE ENTITY WORK. g1 : n1 PORT MAP (b. -. a_eq_b). o1: OUT BIT). BEGIN -. i2: IN BIT. im5). im9. im10 : BIT.a_eq_b output g6 : n3 PORT MAP (im1. g7 : n3 PORT MAP (a. lt. im7. im4.Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT. im5. gt. g8 : n2 PORT MAP (im6. b.a_gt_b output g0 : n1 PORT MAP (a. g2 : n2 PORT MAP (a. im10). END COMPONENT. FOR ALL : n3 USE ENTITY WORK. b.im2. o1: OUT BIT). END gate_level.inv (single_delay). im5. g11 : n2 PORT MAP (b. im4). COMPONENT n2 PORT (i1. g10 : n2 PORT MAP (im1. • Architecture body of bit_comparator identified as gate_level • Components instantiations constitute the body • Each instantiation has a label. im9). im8. im6. eq. im4. g3 : n2 PORT MAP (a.nand3 (single_delay). o1: OUT BIT). g4 : n2 PORT MAP (im2. and PORT MAP • Component declarations are local to the architecture CHAPTER 5 15 © 1999. eq. component name. FOR ALL : n2 USE ENTITY WORK. gt. END COMPONENT. i3: IN BIT. g5 : n3 PORT MAP (im3. lt. im2.

g7 : n3 PORT MAP (a. component declaration configuration specification architecture declarative part architecture body signal declaration component instantiation statement architecture statement part • Syntax details of the architecture body bit_comparator • Signals in the entity are visible to the architecture of CHAPTER 5 16 © 1999.. BEGIN . im7....Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n3 PORT (i1. im8. im6. END gate_level. im9. i2. im3. . END COMPONENT... O1: OUT BIT).. b. FOR ALL : n3 USE ENTITY . Zainalabedin Navabi . im2. im10 : BIT.. eq. im4. . i3: IN BIT. .. im7). im5. SIGNAL im1..

instantiation_label component_name component instantiation statement association_list port map aspect • Component instantiation statement syntax details • A label is required • It includes an association list CHAPTER 5 17 © 1999. b.Wiring Components g7 : n3 PORT MAP ( a. eq. Zainalabedin Navabi . im7 ) .

im9).a_gt_b output g0 : ENTITY WORK. gt. b.nand2(single_delay) PORT MAP (im2.nand2(single_delay) PORT MAP (im1.nand3(single_delay) PORT MAP (im8. a_lt_b).a_eq_b output g6 : ENTITY WORK. im5).nand2(single_delay) PORT MAP (b.inv(single_delay) PORT MAP (a. im7. lt. im4. -.nand2(single_delay) PORT MAP (im6. the most recently compiled architecture will be used CHAPTER 5 18 © 1999. g3 : ENTITY WORK. im9.a_lt_b output g9 : ENTITY WORK. im5. im7).nand3(single_delay) PORT MAP (a. im2.nand2(single_delay) PORT MAP (a. g5 : ENTITY WORK. BEGIN -. im3. g10 : ENTITY WORK. im5. lt. eq.im2.nand3(single_delay) PORT MAP (im3. im7.Intermediate signals SIGNAL im1. im10 : BIT. -. im4). im1).nand2(single_delay) PORT MAP (a. g12 : ENTITY WORK. im2). im6). g1 : ENTITY WORK. b.nand2(single_delay) PORT MAP (im1. im10. a_gt_b). END netlist. im8). im6. Zainalabedin Navabi . • Netlist description of bit_comparator • This is direct instantiation • If architecture name is not specified. im10).nand3(single_delay) PORT MAP (im1. g2 : ENTITY WORK. im8. eq. im4.Wiring Components ARCHITECTURE netlist OF bit_comparator IS -. im2. im3). im9. a_eq_b). g7 : ENTITY WORK. g4 : ENTITY WORK. g11 : ENTITY WORK. gt. g8 : ENTITY WORK.inv(single_delay) PORT MAP (b.

Zainalabedin Navabi .Wiring Components • bit_comparator simulation run • keeping control inputs at 010 CHAPTER 5 19 © 1999.

Wiring Iterative Networks 4 Data inputs 4 Four Bit Comparator A B A>B A=B Compare outputs Control inputs > = < A<B • Logical symbol of a 4-bit comparator • Same configuration as that of the one-bit comparator • This is similar to the 74LS85 magnitude comparator CHAPTER 5 20 © 1999. Zainalabedin Navabi .

Wiring Iterative Networks B3 A3 Comparator A B 3 > = < A>B A=B A<B B2 A2 Comparator A B 2 > = < A>B A=B A<B B1 A1 Comparator A B 1 > = < A>B A=B A<B B0 A0 Comparator A B 0 > = < A>B A=B A<B A>B A=B A<B < = > • A 4-bit comparator using four single bit comparators • Numbers different in MSB. Zainalabedin Navabi . produce results faster • Worst case delay for equal inputs CHAPTER 5 21 © 1999.

Zainalabedin Navabi .-. -.a and b data inputs gt. -. (b) entity declaration • Inputs of of BIT_VECTOR type • Can use any range (a) CHAPTER 5 22 © 1999. -.Wiring Iterative Networks nibble_comparator a(3:0) a_gt_b b(3:0) gt eq lt a_eq_b a_lt_b (a) ENTITY nibble_comparator IS PORT (a.a < b END nibble_comparator. • Interface description of nibble_comparator. -.a = b a_lt_b : OUT BIT).previous greater than eq.a > b a_eq_b. interface aspect. -. -.previous less than a_gt_b.previous equal lt : IN BIT. b : IN BIT_VECTOR (3 DOWNTO 0).

Wiring Iterative Networks nibble_comparator(iterative) a(3:0) b(3:0) a(3) b(3) bit_comparator a (gate_level) Bit 3 b gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a(2) b(2) bit_comparator a (gate_level) Bit 2 b gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) bit_comparator a (gate_level) Bit 1 b gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) bit_comparator a (gate_level) Bit 0 b gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect of nibble_comparator CHAPTER 5 23 © 1999. Zainalabedin Navabi .

Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. a_eq_b. FOR ALL : comp1 USE ENTITY WORK. im(2)). • Iterative architecture of nibble_comparator • Uses nested generate statements • Can easily expand by changing numbers CHAPTER 5 24 © 1999. BEGIN c0: comp1 PORT MAP (a(0). im(i*3-2). b(i). c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). eq. im(1). a_lt_b : OUT BIT). gt. im(6). lt : IN BIT. im(i*3+0). a_lt_b).bit_comparator (gate_level). lt. a_gt_b. eq. END GENERATE. gt. SIGNAL im : BIT_VECTOR ( 0 TO 8). im(i*3+2) ). END iterative. END COMPONENT. a_eq_b. b(0). im(i*3+1). b. im(8). c3: comp1 PORT MAP (a(3). im(i*3-3). im(i*3-1). b(3). a_gt_b. Zainalabedin Navabi . im(0). im(7).

im(i*3-3). im(2). im(i*3+0). b(1). im(i*3-2). im(4). Zainalabedin Navabi .Wiring Iterative Networks PORT MAP (a(i). im(i*3+2) ) i=1 i=1 i=1 i=1 i=1 i=1 i=1 i=1 PORT MAP (a(1). im(5) ) • Association list of c instance of comp1 within generate statement • Bit 1 is configured for i value of 1 CHAPTER 5 25 © 1999. im(0). im(i*3-1). im(3). im(1). b(i). im(i*3+1).

b(i). im(i*3-1).Wiring Iterative Networks c1to2 : FOR i IN 1 TO 2 GENERATE c: COMP1 PORT MAP (a(i). im(i*3+2)). END GENERATE . im(i*3-3). im(i*3+0). generate_label generation_scheme generate statement concurrent_statement • • • • Generate statement syntax details This is a concurrent statement The body of a generate statement is concurrent Can use FOR or IF generation scheme CHAPTER 5 26 © 1999. im(i*3+1). Zainalabedin Navabi . im(i*3-2).

• A more flexible iterative architecture of nibble_comparator • Constant n sizes the comparator • There is still a better way. gt. im(i*3-3). b(i). im(i*3-1). lt : IN BIT. im(1). CHAPTER 5 27 © 1999. eq. a_lt_b).bit_comparator (gate_level). BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). Zainalabedin Navabi . im(i*3+1). im(i*3-3). END iterative. im(i*3+2) ). im(i*3-1). eq. im(0). b. b(i). m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i).Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. use unconstrained arrays. im(i*3-2). END COMPONENT. a_eq_b. CONSTANT n : INTEGER := 4. im(i*3-2). END GENERATE. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). a_gt_b. lt. b(i). a_eq_b. im(2) ). a_gt_b. gt. END GENERATE. Chap 7. END GENERATE. FOR ALL : comp1 USE ENTITY WORK. a_lt_b : OUT BIT). im(i*3+0). END GENERATE. SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1).

im(1). • Configuration specifications create some ambiguities • Problem is corrected by Generate Statement Declarative Part • Binding indication appears here CHAPTER 5 28 © 1999. BEGIN least: comp1 PORT MAP (a(i). b(i). Zainalabedin Navabi . gt.bit_comparator (gate_level). eq. im(2) ). lt.Wiring Iterative Networks l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK. im(0). END GENERATE.

the composition aspect • A test bench does not use ports • All signals used must be explicitly declared CHAPTER 5 29 © 1999.Modeling a Test Bench test_bench (input_output) nibble_comparator (iterative) a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • A test bench for nibble_comparator. Zainalabedin Navabi .

a < b (need bit 3 only. -. -. a2: a <= "0000".nibble_comparator(iterative). -.a > b (worst case) "1111" AFTER 1500 NS. gtr : BIT. -. -.a > b (need bit 3 only. b : IN bit_vector (3 DOWNTO 0). SIGNAL eql. -. eql. best case) a3 : b <= "0000". -. FOR a1 : comp4 USE ENTITY WORK. lss). -. a_eq_b. best case) "0000" AFTER 5500 NS.a < b (need bit 2 info) "0000" AFTER 4000 NS. a_lt_b_out : OUT BIT). -ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a. -. -.a > b (need bit 1 info) "1100" AFTER 3500 NS. BEGIN a1: comp4 PORT MAP (a.a < b (worst case) "1110" AFTER 2500 NS.a > b (need bit 3 only. prepare for next) "1111" AFTER 4500 NS. gtr. a_gt_b.a = b (steady state) "1111" AFTER 0500 NS. best case) "0000" AFTER 5500 NS. -.Modeling a Test Bench ENTITY nibble_comparator_test_bench IS END nibble_comparator_test_bench .a < b (need bit 2 info) "1111" AFTER 4000 NS. vdd.a < b (steady state. gnd. SIGNAL a.a < b (steady state. -. Zainalabedin Navabi . ---. -. -. SIGNAL gnd : BIT := '0'. SIGNAL vdd : BIT := '1'.a > b (worst case) "1110" AFTER 1500 NS. ---. CHAPTER 5 30 iterative architecture of © 1999.a < b (need bit 3 only. -. -.a = b (worst case) "0000" AFTER 5000 NS. a_eq_b_out. -. gnd. b : BIT_VECTOR (3 DOWNTO 0). prepare for next) "1111" AFTER 4500 NS. • Test bench for nibble_comparator. a_lt_b : IN BIT. a_gt_b_out.a > b (need bit 1 info) "1010" AFTER 3500 NS. -. b.a = b (worst case) "1111" AFTER 6000 NS. best case) END input_output. lss. END COMPONENT.a < b (worst case) "1100" AFTER 2500 NS.a = b (worst case) "1111" AFTER 5000 NS.a = b (worst case) "0000" AFTER 6000 NS.a = b (steady state) "1110" AFTER 0500 NS.

... . ... "1010" .. .. • Simulation report for simulating iterative comparator test bench • All events are observed CHAPTER 5 31 © 1999....... ........... '0' ....... '1' ... SIGNALS b(3:0) gtr "0000" ...Modeling a Test Bench TIME (NS) 0 5 500 544 548 1500 1544 1548 2500 2533 2537 3500 3522 3526 4000 4500 4544 4548 5000 5011 5015 5500 5544 5548 6000 6011 6015 a(3:0) "0000" ....... . ..... "1110" ... .. .... . ... ....... Zainalabedin Navabi .. .. '1' .... '1' ... "0000" .... . '0' .... ... .. ....... ................ ..... ...... '0' lss '0' ... .... . "1111" .. ........ .... .. ..... "1111" . ..... .. ...... . '1' ...... .. .................. .... .... ... '1' .... ........ . "0000" ... .. ... ...... .. ........ '0' . . ............. . ... .......... ....... . '0' ... ..... . '1' .... "1111" ..... '0' .......... ... .. ... .... ... "0000" "1111" .. . . ................ .. '1' .... . .... .......... "1111" ... .... '0' .... ... ....... ... eql '0' '1' . .. "1100" ... . "1110" ... '0' .. ...... '0' .... .... '1' ..

Zainalabedin Navabi CHAPTER 5 .Binding Alternatives C S 1 3 Q R 2 4 • • • • Logical diagram of a simple latch With equal timing this will not work Will use this example for showing binding alternatives Correct the oscillation problem by binding to NAND gates of different delay values 32 © 1999.

nand2 (single_delay). i2: IN BIT. o1: OUT BIT). • • • • VHDL description of set-reset latch This is using the 2-input NAND for all four instances Signal assignment avoids use of Buffer The single_delay architecture is used CHAPTER 5 33 © 1999. g3 : n2 PORT MAP (im1. c. SIGNAL im1. c.Binding Alternatives ENTITY sr_latch IS PORT (s. im3). im4 : BIT. END sr_latch. c : IN BIT. FOR ALL : n2 USE ENTITY WORK. g2 : n2 PORT MAP (r. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im1). im2. im2). im3. im4. Zainalabedin Navabi . q : OUT BIT). r. END gate_level. im4). im2. q <= im3. BEGIN g1 : n2 PORT MAP (s. END COMPONENT. g4 : n2 PORT MAP (im3.

o1: BUFFER BIT). BEGIN g1 : n2 PORT MAP (s. c. END gate_level. g4 : n2 PORT MAP (q. im4). im1). q).Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im2. im4. im2). g2 : n2 PORT MAP (r. im2. g3 : n2 PORT MAP (im1. c.nand2 (single_delay). i2: IN BIT. im4 : BIT. END COMPONENT. SIGNAL im1. FOR ALL : n2 USE ENTITY WORK. • sr_latch (gate_level) architecture using BUFFER • componet declaration and the actual entity must match is PORT MAP is not used with the configuration specification • The 2-input NAND must change to use BUFFER instead of OUT CHAPTER 5 34 © 1999. Zainalabedin Navabi .

• • • • A faster NAND gate The gate delay is 3 NS Uses the same entity as the single_delay NAND Using this NAND corrects the oscillation problem CHAPTER 5 35 © 1999. Zainalabedin Navabi . END fast_single_delay.Binding Alternatives ARCHITECTURE fast_single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 3 NS.

Zainalabedin Navabi .Binding Alternatives c s i1 i2 (fast_single_delay) sr_latch (gate_level) nand2 g1: im1 (fast_single_delay) nand2 g3: o1 i1 i2 o1 im3 q r i1 i2 (single_delay) nand2 g2: o1 im2 i1 i2 (single_delay) nand2 g4: o1 im4 (a) • SR-latch. using gates with different delays. composition aspect • Same wiring as the latch that oscillates CHAPTER 5 36 © 1999.

different binding • Fast_single_delay architecture is used for g1 and g3 CHAPTER 5 37 © 1999. im4). • SR-latch. im1). END COMPONENT. im2. c. FOR g1.nand2 (fast_single_delay).Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. SIGNAL im1. im3. Zainalabedin Navabi . using gates with different delays. i2: IN BIT. END gate_level. im2. FOR g2. g4 : n2 PORT MAP (im3. q <= im3. g3 : n2 USE ENTITY WORK. im4. o1: OUT BIT). im4 : BIT. g2 : n2 PORT MAP (r. g4 : n2 USE ENTITY WORK. g3 : n2 PORT MAP (im1. im2).nand2 (single_delay). im3). c. architecture body • Same wiring. BEGIN g1 : n2 PORT MAP (s.

composition aspect • This solution uses 3-input NAND gates • The 3-input gates have different delay values than the 2-input NAND gates CHAPTER 5 38 © 1999.Binding Alternatives c s i1 i2 (single_delay) sr_latch (gate_level) nand2 g1: im1 nand2 g3: q o1 i1 i2 (single_delay) o1 im3 r i1 i2 i3 nand3 (single_delay) o1 g2: im2 i1 i2 i3 (single_delay) nand3 im4 o1 g4: (a) • SR-latch. Zainalabedin Navabi . using nand2 and nand3 gates.

y. z). FOR g2.nand3 (single_delay) PORT MAP (x. z). architecture • Configuration specification takes caring of wiring the 3-input NAND into a 2-input NAND • PORT MAP in binding. z: OUT BIT). g4 : n2 USE ENTITY WORK. z). y. SIGNAL im1. • SR-latch. BEGIN g1 : n2 PORT MAP (s. ALTERNATIVELY: FOR g1. im1). END COMPONENT.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x. g4 : n2 PORT MAP (im3. using nand2 and nand3 gates. g3 : n2 USE ENTITY WORK. q <= im3. im4 : BIT. g3 : n2 USE ENTITY WORK. im2. END gate_level. c. im3. FOR OTHERS : n2 USE ENTITY WORK. x. Zainalabedin Navabi . im2). im4. y. c.nand2 (single_delay) PORT MAP (x. im3). overrides the default • Could use OTHERS CHAPTER 5 39 © 1999. im2. y: IN BIT. im4). FOR g1. g3 : n2 PORT MAP (im1. z). x.nand2 (single_delay) PORT MAP (x. y.nand3 (single_delay) PORT MAP (x. g2 : n2 PORT MAP (r.

Zainalabedin Navabi .Binding Alternatives Signals of gate_level of sr_latch r c im2 Port map association of instantiation statement Local ports of g2 instance of n2 x y z Port map association of configuration specification Formal ports of nand3 in1 in2 in3 o1 • Two-step association • Declaration is local • Names in declaration are used only when not specified in a configuration specification CHAPTER 5 40 © 1999.

instantiation_list component_name component specification entity aspect binding indication port map aspect configuration specification • Configuration specification syntax details • Binding indication contains entity aspect. z) . Zainalabedin Navabi . g3 : n2 USE ENTITY WORK.Binding Alternatives FOR g1.nand2 (single_delay) PORT MAP (x. port map aspect. y. and generic map aspect • If not specified. those of the declaration will be used • Declarations are still needed unless direct instantiations are used CHAPTER 5 41 © 1999.

Top-Down Wiring

old_new_comparator byte_comparator i di byte_latch con1 clk clk a b gt eq lt a_gt_b a_eq_b a_lt_b

• Will develop a complete example, compare old and new data, keep a count • Defaults will be used • Most recently compiled architectures are used in the absence of configuration specifications • Composition aspect of old_new_comparator
CHAPTER 5 42 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT); END old_new_comparator; -ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparator PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN); END wiring;

• • • • •
CHAPTER 5

old_new_comparator VHDL description Declarations are present Configuration specifications are missing Use OPEN for unconnected outputs OPEN inputs must have a default value
43 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0)); END byte_latch; -ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE; END iterative;

• • • •

An 8-bit latch is required for this design Use a configurable description based on D-type latch VHDL description of byte_latch. Iterative architecture is used

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Top-Down Wiring

c d inv i1 o1

sr_latch C S q q

R

(a)

• Build a D-latch using our sr_latch and an inverter • Composition aspect is shown

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Top-Down Wiring

ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT; BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar); END sr_based; (b)

• Design of d_latch, VHDL description • Configuration specifications are not used • Local declarations are used for ports and name of the actual entity

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Top-Down Wiring

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );

END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;

• Another necessary component for this design is an 8bit comparator • Byte comparator VHDL description • Uses 8 instances of bit_comparator • Constant n is changed to 8 • Default architectures are used
CHAPTER 5 47 © 1999, Zainalabedin Navabi

Top-Down Wiring
A structural description for a design consists of a wiring specification of its subcomponents. In this chapter, the

definition and usage of components in larger designs was illustrated. Generate statements also were introduced as a convenient way to describe repetitive hardware structures and a notation was defined for graphical representation of structural descriptions. In addition, various forms and

options in component declarations and configuration specifications were discussed. The last part of this chapter presented a top-down design using basic gates and components presented in the earlier sections. Using simple gates, the reader should now be able to design larger digital circuits with many levels of component nesting.

• End Of Chapter 5

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CHAPTER 6 DESIGN ORGANIZATION AND PARAMETERIZATION

6.1 DEFINITION AND USAGE OF SUBPROGRAMS 6.1.1 A Functional Single Bit Comparator 6.1.2 Using Procedures in a Test Bench 6.1.3 Language Aspects of Subprograms 6.1.4 Utility Procedures 6.2 PACKAGING PARTS AND UTILITIES 6.2.1 Packaging Components 6.2.2 Packaging Subprograms 6.3 DESIGN PARAMETRIZATION 6.3.1 Using Default Values 6.3.2 Using Fixed Values 6.3.3 Passing Generic Parameters 6.4 DESIGN CONFIGURATION 6.4.1 A General Purpose Test Bench 6.4.2 Configuring Nested Components 6.4.3 Incremental Binding 6.4.4 An n-bit Register Example 6.4.5 Iterative Parity Checking 6.5 DESIGN LIBRARIES 6.5.1 Existing Libraries 6.5.2 Library Management 6.6 SUMMARY

CHAPTER 6

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© 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

GT Equation EQ Equation LT Equation

a_gt_b = a . gt + b' . gt + a . b' a_eq_b = a . b . eq + a' . b' . eq a_lt_b = b . lt + a' . lt + b . a'

ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;

An architecture for demonstrating use of subprograms

• Demonstrating the use of functions • Use functions in place of Bololean expresssions • A functional bit_comparator, using the same function for two outputs
CHAPTER 6 2 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

FUNCTION fgl ( w, x, g1 :BIT) RETURN BIT IS BEGIN RETURN (w AND g1) OR (NOT x AND g1) OR (w AND NOT x) ; END;

designator formal_parameter_list type_mark subprogram body expression return statement sequential statement subprogram statement part subprogram specification

• Function body is sequential • Use functions for utilities and coding style • Syntax details of a subprogram body, a general view
CHAPTER 6 3 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END structural;

• Using the functional bit_comparator • Structural architecture of a nibble_comparator

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© 1999, Zainalabedin Navabi

target <= TRANSPORT buf AFTER i * period. pos : INTEGER := 0. gnd. SIGNAL a. PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). END apply_data. ELSE buf (j) := '0'. b : BIT_VECTOR (3 DOWNTO 0). 500 NS). CONSTANT period : IN TIME) IS VARIABLE j : INTEGER. • Defining and using a procedure • Procedural architecture of nibble_comparator • INTEGERS type is an array of 13 integers CHAPTER 6 5 © 1999. a_eq_b. gtr. END LOOP. END IF. END procedural. BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i). WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'. lss. j := j + 1. VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). apply_data (b. a_gt_b. FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural). eql. gtr : BIT. lss). SIGNAL gnd : BIT := '0'. a_lt_b : OUT BIT). SIGNAL eql. CONSTANT values : IN integers. b. b : IN bit_vector (3 DOWNTO 0). END LOOP. SIGNAL vdd : BIT := '1'.Definition and Usage of Subprograms ARCHITECTURE procedural OF nibble_comparator_test_bench IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. BEGIN a1: comp4 PORT MAP (a. Zainalabedin Navabi . COMPONENT comp4 PORT (a. 500 NS). 00&15&15&14&14&14&14&10&00&15&00&00&15. vdd. gnd. 00&14&14&15&15&12&12&12&15&15&15&00&00. lt : IN BIT. apply_data (a. tmp := tmp / 2. gt. END COMPONENT. VARIABLE tmp. j := 0. eq.

... ... .... "1110" .. "1110" . "1111" ........ ..... "0000" .. '1' . '1' ........ . '0' lss '0' .. '0' . ................... .. "0000" "1111" . ... '0' . . .. ..... "1100" . .. '0' .... '1' ... ...... '1' ........ ..... SIGNALS b(3:0) gtr "0000" .. '0' ...... '0' ......... • Simulation report resulting from the procedural test bench • All events are observed • Shows increments of 12 NS only CHAPTER 6 6 © 1999... Zainalabedin Navabi .... .. .....Definition and Usage of Subprograms TIME (NS) 0 48 500 548 1500 1548 2500 2536 3500 3524 4000 4500 4548 5000 5012 5500 5548 6000 6012 a(3:0) "0000" .. ... ... "1111" ....... .. .. '0' ..... '1' eql '0' '1' ....... "1010" ... '1' ...... . "1111" ...... '0' ... ........ ...... .... ..... .. "0000" .. . "1111" ....... '0' .. ......... . ............ '1' .. '1' ........ . ..

END apply_data. . VARIABLE buf: BIT_VECTOR (3 DOWNTO 0). Zainalabedin Navabi . FOR i IN 0 TO 12 LOOP . . CONSTANT period : IN TIME ) IS VARIABLE j : INTEGER.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). subprogram specification formal parameter list subprogram declarative part subprogram body loop statement sequential statement subprogram statement part • • • • CHAPTER 6 Details of a subprogram body Function or procedure subprogram specification Subprograms are procedural bodies Nested procedural statements 7 © 1999. VARIABLE tmp : INTEGER := 0. END LOOP. CONSTANT values : IN integers. BEGIN.

END LOOP. . loop parameter specification iteration scheme loop_statement sequence_of_statement • • • • CHAPTER 6 Loops are procedural Loop statement with FOR iteration scheme Can nest procedural statements Sequence_of_statements is the sequential construct 8 © 1999. Zainalabedin Navabi .Definition and Usage of Subprograms FOR i IN 0 TO 12 LOOP . .

ELSE buf (j) := ‘0’. condition if_statement sequence_of_statements sequence_of_statements • Details of the If statement of apply_data procedure • This is a procedural statement • Sequence_of_statements is the sequential construct CHAPTER 6 9 © 1999.Definition and Usage of Subprograms IF (tmp MOD 2 = 1) THEN buf (j) := ’1’. END IF. Zainalabedin Navabi .

• Can do utility procedures • ‘RANGE attribute makes this a generic procedure • Procedure for binary to integer conversion CHAPTER 6 10 © 1999. END bin2int. BEGIN result := 0.Definition and Usage of Subprograms PROCEDURE bin2int (bin : IN BIT_VECTOR. END IF. int := result. int : OUT INTEGER) IS VARIABLE result: INTEGER. Zainalabedin Navabi . END LOOP. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i.

tmp := tmp / 2. END IF. • Another utility procedure • Procedure for integer to binary conversion • ‘LENGTH attribute is used here CHAPTER 6 11 © 1999. BEGIN tmp := int.Definition and Usage of Subprograms PROCEDURE int2bin (int : IN INTEGER. ELSE bin (i) := '0'. END int2bin. bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. END LOOP.1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. Zainalabedin Navabi . FOR i IN 0 TO (bin'LENGTH .

target <= TRANSPORT buf AFTER i * period. END apply_data. buf). CONSTANT values : IN integers. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). • • • • CHAPTER 6 Can use procedures within procedure Another version of apply_data procedure This version takes advantage of the int2bin procedure TRASPORT delay schedules all transactions at time 0 12 © 1999. END LOOP.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). Zainalabedin Navabi .

• Functions can serve as utilities • Binary to integer conversion function • Assumes lower bound of 0. RETURN result. otherwise it is a generic function CHAPTER 6 13 © 1999. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END LOOP.Definition and Usage of Subprograms FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. END IF. BEGIN result := 0. Zainalabedin Navabi . END to_integer.

END COMPONENT.Packaging Parts and Utilities -. END simple_gates. i2. o1: OUT BIT). COMPONENT n2 PORT (i1: i2: IN BIT. o1: OUT BIT). COMPONENT n3 PORT (i1. i3: IN BIT. END COMPONENT.Packaging components PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT. END COMPONENT. o1: OUT BIT). Zainalabedin Navabi . Demonstrating specification and usage of packages • Component declarations as well as utilities can be packaged • A package declaration containing component declarations of simple gates • Eliminates the need for individual declarations CHAPTER 6 14 © 1999.

im8.Packaging Parts and Utilities USE WORK.inv (single_delay). im3). g10 : n2 PORT MAP (im1. lt. same configuration CHAPTER 6 15 © 1999. gt. im2. lt. im4. im5. eq. im9). -. im5. a_eq_b). BEGIN -. g8 : n2 PORT MAP (im6.a_gt_b output g0 : n1 PORT MAP (a. g2 : n2 PORT MAP (a. im9. b. im3. END gate_level. g5 : n3 PORT MAP (im3. ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK. eq. Zainalabedin Navabi . -. im10. a_lt_b). im5). g4 : n2 PORT MAP (im2. im6). g7 : n3 PORT MAP (a. im4). im7. im2).nand2 (single_delay).a_eq_b output g6 : n3 PORT MAP (im1.im2. im10 : BIT. g11 : n2 PORT MAP (b. im7. a_gt_b). im4. im2. im7). -. g1 : n1 PORT MAP (b. im6.nand3 (single_delay). FOR ALL : n3 USE ENTITY WORK. im9.Intermediate signals SIGNAL im1. • Using package of simple gates in gate_level of bit_comparator • This becomes our local declarations • Same naming rules as before. g3 : n2 PORT MAP (a. g12 : n3 PORT MAP (im8.simple_gates. im10).ALL. im8). gt.a_lt_b output g9 : n2 PORT MAP (im1. b. FOR ALL : n2 USE ENTITY WORK. im1).

n1.simple_gates.simple_gates. Zainalabedin Navabi . WORK. • An alternative application of the use clause • Can select only those needed CHAPTER 6 16 © 1999. . -. n2 and n3 component declarations are visible .n2. WORK.Packaging Parts and Utilities USE WORK.n1.simple_gates.n3.

x. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER. bin : OUT BIT_VECTOR). int : OUT INTEGER). Zainalabedin Navabi . gl : BIT) RETURN BIT. CONSTANT period : IN TIME). PROCEDURE int2bin (int : IN INTEGER. END basic_utilities. eq : BIT) RETURN BIT. FUNCTION feq (w. PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). FUNCTION fgl (w. x. • The basic_utilities package declaration • Packaging subprograms replaces their declaration • Types and declarations become visible to architectures CHAPTER 6 17 © 1999. CONSTANT values : IN integers.Packaging Parts and Utilities PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. PROCEDURE bin2int (bin : IN BIT_VECTOR.

FOR i IN 0 TO (bin'LENGTH . END IF. END int2bin. x.Packaging Parts and Utilities PACKAGE BODY basic_utilities IS FUNCTION fgl (w. PROCEDURE bin2int (bin : IN BIT_VECTOR. END bin2int. int : OUT INTEGER) IS VARIABLE result: INTEGER. FUNCTION feq (w. VARIABLE buf : BIT_VECTOR (bin'RANGE). END LOOP. BEGIN result := 0. bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. PROCEDURE int2bin (int : IN INTEGER. END feq. eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq). END LOOP. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. BEGIN tmp := int. gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x). x. Zainalabedin Navabi . • Package body includes body of procedures • The basic_utilities package body • Will use this package in all our examples CHAPTER 6 18 © 1999. END IF. int := result. ELSE bin (i) := '0'.1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. tmp := tmp / 2. END fgl.

Packaging Parts and Utilities PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). END to_integer. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. Zainalabedin Navabi . RETURN result. • Continuation of the basic_utilities package body • New declarations in this body are visible to this body only CHAPTER 6 19 © 1999. END IF. END basic_utilities. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. BEGIN result := 0. CONSTANT values : IN integers. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). target <= TRANSPORT buf AFTER i * period. buf). END LOOP. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). END LOOP. END apply_data.

END functional. a_lt_b <= fgl (b. Zainalabedin Navabi CHAPTER 6 20 . gt) AFTER 12 NS. ARCHITECTURE functional OF bit_comparator IS BEGIN a_gt_b <= fgl (a.ALL. • Using functions of the basic_utilities package • Architecture need not include function body • The USE statement handles visibility © 1999.basic_utilities. lt) AFTER 12 NS.Packaging Parts and Utilities USE WORK. eq) AFTER 12 NS. a. a_eq_b <= feq (a. b. b.

apply_data (b. gnd. b : BIT_VECTOR (3 DOWNTO 0).14. apply_data (a.14. BEGIN a1: comp4 PORT MAP (a.12.10. 500 NS).00).15. a_gt_b. SIGNAL a.Packaging Parts and Utilities USE WORK.15.00. gtr : BIT. gnd.15.15. b. vdd.15. gtr. lss. b : IN bit_vector (3 DOWNTO 0). 0&14&14&15&15&12&12&12&15&15&15&00&00.14.12. 500 NS).15.nibble_comparator(structural). FOR a1 : comp4 USE ENTITY WORK. eq.15. (00.14. 500 NS). lss).ALL. a_lt_b : OUT BIT). 500 NS). SIGNAL gnd : BIT := '0'.15).14.12. ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a. END procedural.15.00.basic_utilities. Zainalabedin Navabi . • • • • CHAPTER 6 Using procedures of the basic_utilities package Concatenate to form 13 integers Can also use aggregate operation Aggregate for elements of the array only 21 © 1999. a_eq_b. SIGNAL vdd : BIT := '1'. END COMPONENT. gt. ALTERNATIVELY: apply_data (a.14. lt : IN BIT.00. eql. 0&15&15&14&14&14&14&10&00&15&00&00&15. apply_data (b.00. (00. SIGNAL eql.

PORT (i1 : IN BIT.Design Parametrization ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. END inv_t. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. Architecture for demonstrating specification and definition of parameters • Start design parameterization examples with same simple structures CHAPTER 6 22 © 1999. tphl : TIME := 3 NS). END average_delay. Zainalabedin Navabi . o1 : OUT BIT).

declares objects of type constant © 1999. • Parametrized gate models • GENERIC is used. tphl : TIME := 4 NS). Zainalabedin Navabi CHAPTER 6 23 . o1 : OUT BIT). i3 : IN BIT. -ARCHITECTURE average_delay OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. END nand2_t. PORT (i1. END nand3_t. PORT (i1. -ARCHITECTURE average_delay OF nand3_t IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2. o1 : OUT BIT). tphl : TIME := 5 NS). END average_delay. i2. i2 : IN BIT.Design Parametrization ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS. END average_delay.

PORT (i1 : IN BIT. END inv_t. tphl : TIME := 3 NS ). interface constant declaration entity declaration interface constant declaration (generic) interface list (formal) generic clause entity header (formal) port clause • Details of the entity declaration of inverter with generics • Using a default value is helpful but not required • Generic clause comes before port clause CHAPTER 6 24 © 1999. Zainalabedin Navabi . o1 : OUT BIT).Design Parametrization ENTITY inv_t IS GENERIC ( tplh : TIME := 5 NS .

Zainalabedin Navabi .Design Parametrization inv_t i1 tplh o1 tphl nand2_t i1 o1 i2 tphl tplh i1 nand3_t o1 i2 i3tplh tphl • Interface aspects of inv_t. nand2_t. and nand3_t • Graphical representation with generics • Port association and generic association must be done when used CHAPTER 6 25 © 1999.

im1). gt. g4 : n2 PORT MAP (im2. o1: OUT BIT). END COMPONENT.inv_t (average_delay). END default_delay. -. Zainalabedin Navabi CHAPTER 6 26 . a_lt_b).a_eq_b output g6 : n3 PORT MAP (im1. FOR ALL : n3 USE ENTITY WORK. im4. im7. im5. im9.nand2_t (average_delay). COMPONENT n3 PORT (i1. g3 : n2 PORT MAP (a.Intermediate signals SIGNAL im1. • Many alternatives for specifying generics • Using default values for the generics of logic gates • No need to declare and specify generics if they are to use default values © 1999. o1: OUT BIT). -. im3). lt. i3: IN BIT. g8 : n2 PORT MAP (im6. FOR ALL : n2 USE ENTITY WORK. eq. im4). im5. im2. gt. END COMPONENT. g5 : n3 PORT MAP (im3. im7). g12 : n3 PORT MAP (im8. FOR ALL : n1 USE ENTITY WORK. im9.im2.nand3_t (average_delay). -. b. g11 : n2 PORT MAP (b. o1: OUT BIT). g10 : n2 PORT MAP (im1. im2. im9).a_gt_b output g0 : n1 PORT MAP (a.a_lt_b output g9 : n2 PORT MAP (im1. END COMPONENT. im10 : BIT. i2: IN BIT. im3.Design Parametrization ARCHITECTURE default_delay OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT. im7. i2. im6. g7 : n3 PORT MAP (a. a_gt_b). g1 : n1 PORT MAP (b. b. im8). im2). BEGIN -. g2 : n2 PORT MAP (a. im4. im6). im8. a_eq_b). eq. COMPONENT n2 PORT (i1. lt. im10. im10). im5).

5 NS) PORT MAP (a. im2. PORT (i1: IN BIT.a_eq_b output g6 : n3 GENERIC MAP (4 NS. i2. 5 NS) PORT MAP (im6. 5 NS) PORT MAP (im1. 5 NS) PORT MAP (b. Zainalabedin Navabi .nand2_t (average_delay). im4. im6. g1 : n1 GENERIC MAP (2 NS. g7 : n3 GENERIC MAP (4 NS. 6 NS) PORT MAP (im1. END COMPONENT. g11 : n2 GENERIC MAP (3 NS.a_lt_b output g9 : n2 GENERIC MAP (3 NS. -. im8). im2. im7. a_lt_b). 5 NS) PORT MAP (im2. im1).a_gt_b output g0 : n1 GENERIC MAP (2 NS. im4. im6). im10. g4 : n2 GENERIC MAP (3 NS. tphl : TIME). im9. g5 : n3 GENERIC MAP (4 NS. 6 NS) PORT MAP (im3. g8 : n2 GENERIC MAP (3 NS. BEGIN -. im4). FOR ALL : n3 USE ENTITY WORK. im10 : BIT. i3: IN BIT. PORT (i1. i2: IN BIT. g3 : n2 GENERIC MAP (3 NS. im9. b. o1: OUT BIT). 6 NS) PORT MAP (im8. im5. eq. im5. -. im9). COMPONENT n3 GENERIC (tplh. END fixed_delay. im3. FOR ALL : n1 USE ENTITY WORK. 5 NS) PORT MAP (im1. b. o1: OUT BIT).nand3_t (average_delay). im2). 6 NS) PORT MAP (a. im5).inv_t (average_delay). im10). gt. 5 NS) PORT MAP (a. • If generics are declared without default values. 4 NS) PORT MAP (a. END COMPONENT.Design Parametrization ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh. SIGNAL im1. gt. tphl : TIME). a_eq_b). o1: OUT BIT). 4 NS) PORT MAP (b. lt. g10 : n2 GENERIC MAP (3 NS. END COMPONENT. tphl : TIME). COMPONENT n2 GENERIC (tplh. im8. im7. a_gt_b). g2 : n2 GENERIC MAP (3 NS. lt. im3). they have to be specified • Associating fixed values with the generics of logic gates • Generic map is shown here CHAPTER 6 27 © 1999. g12 : n3 GENERIC MAP (4 NS. FOR ALL : n2 USE ENTITY WORK. im7).im2. eq. PORT (i1.

im2 ) . instantiation_label component_name generic map aspect port map aspect association_list component instantiation statement association_list • Syntax details • Component instantiation statement with generic map aspect • Generic map aspect comes first CHAPTER 6 28 © 1999.Design Parametrization g1 : n1 GENERIC MAP ( 2 NS. Zainalabedin Navabi . 4 NS ) PORT MAP ( b.

• A bit comparator with timing parameters • Passing generics of bit comparator to its components • Bit comparator has generic parameters that must be passed to it CHAPTER 6 29 © 1999. COMPONENT n3 GENERIC (tplh. END COMPONENT. PORT (i1. im3. END COMPONENT. BEGIN . PORT (i1.less than END bit_comparator_t. -. FOR ALL : n3 USE ENTITY WORK. tphl3 : TIME). tphl1. im8. i2.greater a_eq_b. -. (a) ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh. END COMPONENT. i3: IN BIT.. -. Zainalabedin Navabi .nand3_t (average_delay).previous greater than eq. tplh2. im10 : BIT. im5. im4. -.previous less than a_gt_b. tplh3. b.data inputs gt. -. FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay). im9. tphl2. tphl : TIME). o1: OUT BIT). PORT (a. tphl : TIME).Intermediate signals SIGNAL im1.. tphl : TIME). COMPONENT n2 GENERIC (tplh. im6.im2. -. i2: IN BIT. o1: OUT BIT). PORT (i1: IN BIT.Design Parametrization ENTITY bit_comparator_t IS GENERIC (tplh1. o1: OUT BIT). im7. -. FOR ALL : n2 USE ENTITY WORK. -.equal a_lt_b : OUT BIT).nand2_t (average_delay).previous equal lt : IN BIT.

a_lt_b).. b. tphl2) PORT MAP (im1. im5. -.a_gt_b output g0 : n1 GENERIC MAP (tplh1. tphl2) PORT MAP (im6. a_gt_b). im10. im10). g10 : n2 GENERIC MAP (tplh2. im3). tphl2) PORT MAP (a. im8). im2). eq. lt. im2. g5 : n3 GENERIC MAP (tplh3. im9). tphl2) PORT MAP (im2. im1). g1 : n1 GENERIC MAP (tplh1. g7 : n3 GENERIC MAP (tplh3. tphl1) PORT MAP (b. im2. g3 : n2 GENERIC MAP (tplh2. tphl3) PORT MAP (im8. tphl3) PORT MAP (a.a_eq_b output g6 : n3 GENERIC MAP (tplh3. im4. tphl3) PORT MAP (im3. im5). tphl3) PORT MAP (im1. g2 : n2 GENERIC MAP (tplh2. eq.. a_eq_b). im6). tphl2) PORT MAP (a. g12 : n3 GENERIC MAP (tplh3. im9. tphl2) PORT MAP (b. g11 : n2 GENERIC MAP (tplh2. b. Zainalabedin Navabi .a_lt_b output g9 : n2 GENERIC MAP (tplh2. -. tphl1) PORT MAP (a. im7. gt. im4). • A bit comparator with timing parameters • Gates require generic specification • These override the gate generics CHAPTER 6 30 © 1999.Design Parametrization . lt. tphl2) PORT MAP (im1. -. g8 : n2 GENERIC MAP (tplh2. END passed_delay. gt. g4 : n2 GENERIC MAP (tplh2. im7).

Zainalabedin Navabi .Design Parametrization bit_comparator_t (passed_delay) a nand2_t i1 (average_delay) o1 i2 im3 tplh tphl nand2_t i1 i2 (average_delay) o1 im4 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_gt_b b inv_t im2 i1 (average_delay)o1 nand2_t i1 i2 (average_delay) tplh tphl o1 tplh tphl im5 gt nand3_t i1 (average_delay) o1 i2 i3 tplh tphl nand3_t i1 (average_delay) i2 o1 i3tplh tphl im6 nand2_t i1 i2 im7 (average_delay) eq lt o1 a_eq_b tplh tphl nand2_t i1 i2 inv_t i1 (average_delay)o1 (average_delay) im8 o1 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_lt_b im1 i1 i2 nand2_t (average_delay) tplh tphl o1 im9 tplh tphl nand2_t i1 i2 (average_delay) o1 tplh tplh2 tphl im10 tplh1 tphl1 tphl2 tplh3 tphl3 • Composition aspect of bit_comparator_t • Dotted lines with arrows indicate generics CHAPTER 6 31 © 1999.

gt. gt. im(1). FOR ALL : comp1 USE ENTITY WORK. PORT (a. b(0). • Comp1 is declared with default values • Passing default values of local generics to the generics of bit_comparator_t • These values override at the lower levels CHAPTER 6 32 © 1999. a_eq_b. END GENERATE. Zainalabedin Navabi . tplh1 : TIME := 4 NS. im(i*3-3). tplh2 :TIME := 3 NS. SIGNAL im : BIT_VECTOR ( 0 TO 8). c3: comp1 PORT MAP (a(3). lt. END iterative. a_lt_b : OUT BIT). im(2)). BEGIN c0: comp1 PORT MAP (a(0). a_gt_b. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). a_gt_b. tplh3 : TIME := 6 ns. a_lt_b). im(i*3-1).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 GENERIC ( tplh1 : TIME := 2 NS. tplh3 : TIME := 4 ns. eq. im(8). a_eq_b. im(7). tplh2 :TIME := 5 NS. im(0). b. im(i*3+1).bit_comparator_t (passed_delay). im(i*3+2) ). lt : IN BIT. b(i). im(6). b(3). eq. END COMPONENT. im(i*3+0). im(i*3-2).

OPEN. lt. and using defaults for others • Association by position.. .Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . 8 NS.. OPEN.. im(1). im(0). eq.. OPEN. im(2)). correspond in the order they are listed CHAPTER 6 33 © 1999. BEGIN c0: comp1 GENERIC MAP (OPEN. • Some are associated with OPEN • Associating constants with some of generics of bit_comparator_t. b(0). gt. END iterative. 10 NS) PORT MAP (a(0). Zainalabedin Navabi .

tphl3 => 10 NS) PORT MAP (a(0). same mapping as before It must be: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open.. eq. gt. lt => lt.... im(0). inputs only if default 34 © 1999. gt. b. im(1). a_eq_b => im(1). Zainalabedin Navabi . ARCHITECTURE BECOMES: ARCHITECTURE iterative OF nibble_comparator IS . END iterative. . gt => gt.. b => b(0). BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. lt. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. eq. a_lt_b => im(2)).. • • • • • CHAPTER 6 Using named association. a_eq_b.Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . tphl3 => 10 NS) PORT MAP (a => a(0). SAME FORMAT FOR THE PORTS: PORT AS DECLARED: PORT (a. a_gt_b => im(0).. END iterative. b(0). im(2)). eq => eq. . a_lt_b : OUT BIT). lt : IN BIT.. a_gt_b.

14. SIGNAL eql.14. b. END customizable. END COMPONENT.15. Customizable architecture for demonstrating configuration declarations • A customizable test bench • Configuration specification is not included • Comp4 is not in our work library CHAPTER 6 35 © 1999. gtr.15.15. (0.00. SIGNAL gnd : BIT := '0'. gt. 500 NS). gnd.ALL.15.00.15. eql.00. lss. a_gt_b. gnd.Design Configuration USE WORK. a_eq_b.12. SIGNAL vdd : BIT := '1'. ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a. (0. vdd.14. b : IN BIT_VECTOR (3 DOWNTO 0).12.00). lss). gtr : BIT.basic_utilities.12. eq. SIGNAL a. lt : IN BIT.14.10. Zainalabedin Navabi .00.14.15). apply_data (a.15. 500 NS). BEGIN a1: comp4 PORT MAP (a. a_lt_b : OUT BIT).14.15. b : BIT_VECTOR (3 DOWNTO 0). apply_data (b.15.

ALL. • Configuring customizable for testing structural architecture of nibble_comparator • Hierarchically enter the architecture. END FOR. END functional. Zainalabedin Navabi .Design Configuration 1 USE WORK.nibble_comparator(structural). CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 2 3 USE ENTITY WORK. END FOR. perform binding CHAPTER 6 36 © 1999.

configuring customizable test bench • Pass through hierarchies with arrows CHAPTER 6 37 © 1999.Design Configuration functional nibble_comparator (structural) nibble_comparator_test_bench (customizable) a1: comp4 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • Graphical representation • Composition aspect for functional configuration declaration. Zainalabedin Navabi .

END FOR. Zainalabedin Navabi . END FOR.ALL.Design Configuration USE WORK. CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END average_delay.nibble_comparator(iterative). • Another configuration on top of the test bench • Configuring customizable for testing iterative architecture of nibble_comparator • No need to recompile the test bench CHAPTER 6 38 © 1999.

nibble_comparator (iterative) . Zainalabedin Navabi .Design Configuration CONFIGURATION average_delay OF nibble_ comparator_ test_bench IS FOR customizable FOR al : comp4 USE ENTITY WORK. END FOR. END average_delay. END FOR. identifier entity_name configuration declaration binding indication component configuration block configuration • Details of configuration declaration • Configuration declaration replaces or adds to a configuration specification • Includes component configuration and block configuration CHAPTER 6 39 © 1999.

a_lt_b : OUT BIT). lt : IN BIT. gt. im(i*3+0). im(i*3-1). im(8). eq. END GENERATE. Zainalabedin Navabi . SIGNAL im : BIT_VECTOR ( 0 TO 8). im(i*3+2) ). b(i). b. • A general purpose nibble_comparator • This 4-bit comparator does not use a specific bit comparator • A top-level configuration configures comp1 instantiations CHAPTER 6 40 © 1999. gt. c3: comp1 PORT MAP (a(3). im(i*3+1). im(1). lt. im(6). BEGIN c0: comp1 PORT MAP (a(0). a_gt_b. im(i*3-2). im(i*3-3). a_eq_b. im(0). c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). a_eq_b.Design Configuration ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. END flexible. b(0). END COMPONENT. a_gt_b. b(3). eq. im(7). im(2)). a_lt_b).

Design Configuration default_bit_level bit_comparator(default_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) c3: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a1: comp4 a(2) b(2) c2: comp1 a(3:0) b(3:0) gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect for configuring customizable test bench for testing default_delay bit_comparator • Graphical representation of hierarchies CHAPTER 6 41 © 1999. Zainalabedin Navabi .

c3: comp1 USE ENTITY WORK. • Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator • Binding to the default_delay architecture CHAPTER 6 42 © 1999.Design Configuration USE WORK. END FOR.ALL. FOR c1to2 FOR c: comp1 USE ENTITY WORK. CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR.bit_comparator (default_delay). END FOR. Zainalabedin Navabi . END default_bit_level. FOR flexible FOR c0.nibble_comparator(flexible).bit_comparator (default_delay). END FOR. END FOR. END FOR.

• Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator • Binding to the fixed_delay architecture • Can use ALL or OTHERS CHAPTER 6 43 © 1999.nibble_comparator(flexible).bit_comparator (fixed_delay).ALL. END FOR. END FOR. FOR flexible FOR c0. END FOR. Zainalabedin Navabi .Design Configuration USE WORK. END FOR. END fixed_bit_level. c3: comp1 USE ENTITY WORK.bit_comparator (fixed_delay). CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. FOR c1to2 FOR c: comp1 USE ENTITY WORK. END FOR. END FOR.

Design Configuration passed_bit_level bit_comparator_t(passed_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) tplh1 c3: comp1 tplh2 tplh3 a(3:0) b(3:0) gt eq lt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b 2NS 3NS 4NS 4NS 5NS 6NS a1: comp4 a(2) b(2) c2: comp1 tplh1 tplh2 tplh3 a(3:0) b(3:0) gt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(6) im(7) im(8) 2NS 3NS 4NS 4NS 5NS 6NS gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) 2NS 3NS 4NS 4NS 5NS 6NS c1to2: a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) 2NS 3NS 4NS 4NS 5NS 6NS • Composition aspect of the passed_bit_level • Configuration for test bench for testing passed_delay architecture of bit_comparator_t CHAPTER 6 44 © 1999. Zainalabedin Navabi .

Design Configuration USE WORK. END passed_bit_level. tplh3 => 4 NS. tphl2 => 5 NS. CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. • Using configuration declarations for component bindings. c3: comp1 USE ENTITY WORK. Zainalabedin Navabi . tplh2 => 3 NS.nibble_comparator(flexible).bit_comparator_t (passed_delay) X GENERIC MAP (tplh1 => 2 NS. tphl1 => 4 NS. tplh3 => 4 NS. N FOR c1to2 T FOR c: comp1 A USE ENTITY WORK. FOR flexible FOR c0. END FOR. END FOR. END FOR. tphl3 => 6 NS). S tphl2 => 5 NS.ALL.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. Y END FOR. tphl3 => 6 NS). END FOR. tphl1 => 4 NS. and specification of generic parameters • Same format for generic map and port map aspects as configuration specification CHAPTER 6 45 © 1999. END FOR. tplh2 => 3 NS.

END FOR. FOR c1to2 FOR c: comp1 USE ENTITY WORK. tphl1 => 4 NS. END FOR.Design Configuration FOR flexible FOR c0. tphl3 => 6 NS). c3: comp1 USE ENTITY WORK. tphl3 => 6 NS). tplh3 => 4 NS. tplh3 => 4 NS. END FOR. Zainalabedin Navabi . tphl2 => 5 NS. entity aspect component configuration generic map aspect block configuration component configuration block configuration • Details of a block configuration enclosing component configurations and other block configurations • Binding indication and generic map aspect CHAPTER 6 46 © 1999. END FOR.bit_comparator_t (passed_delay) GENERIC MAP (tphl1 => 2 NS. tphl2 => 5 NS.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. tplh2 => 3 NS. tplh2 => 3 NS. tphl1 => 4 NS.

SIGNAL im : BIT_VECTOR ( 0 TO 8 ). ). BEGIN c0: comp1 PORT MAP ( . END partially_flexible. c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( . . END COMPONENT. • Can do incremental binding • Do some with configuration specification. . c3: comp1 PORT MAP ( . END GENERATE. ). a_eq_b. . and more with configuration declaration • This is an illustration for the primary binding indication CHAPTER 6 47 © 1999.Design Configuration ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. . lt : IN BIT. b. eq.bit_comparator_t (passed_delay). FOR ALL : comp1 USE ENTITY WORK. gt. Zainalabedin Navabi . ). a_lt_b : OUT BIT). . a_gt_b. .

END FOR. FOR flexible FOR c0. END FOR. c3: comp1 GENERIC MAP (tplh1 => 2 NS. tplh2 => 3 NS. Zainalabedin Navabi . tplh2 => 3 NS. tphl3 => 6 NS). END incremental. tphl3 => 6 NS). • Incremental binding indication illustration • Add generic map aspect to the existing binding • Can use different mappings CHAPTER 6 48 © 1999. FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS. tphl2 => 5 NS. tphl1 => 4 NS. tphl2 => 5 NS.ALL. tplh3 => 4 NS. tplh3 => 4 NS. CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR. END FOR.Design Configuration USE WORK.nibble_comparator (partially_flexible). END FOR. END FOR. tphl1 => 4 NS.

im2. im2). Customizable architecture. g4 : n2 PORT MAP (im3. im4 : BIT. c. c. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. END COMPONENT. i2: IN BIT. r. im3. g2 : n2 PORT MAP (r. using a sequential example. q <= im3. o1: OUT BIT). illustrating configurations at several levels of depth • Unbound VHDL description of set-reset latch • Uses the same basic components CHAPTER 6 49 © 1999. END gate_level. im2. q : OUT BIT). im3). g3 : n2 PORT MAP (im1. im4. im1). BEGIN g1 : n2 PORT MAP (s. im4). Zainalabedin Navabi . END sr_latch. c : IN BIT. several levels of hierarchy • A new example.Design Configuration ENTITY sr_latch IS PORT (s. SIGNAL im1.

END COMPONENT. q). BEGIN c1 : sr PORT MAP (d. c : IN BIT. END COMPONENT.Design Configuration ENTITY d_latch IS PORT (d. SIGNAL dbar : BIT. -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr PORT (s. • • • • Building a D-latch Add an inverter to the SR-latch Unbound VHDL description of a D-latch All gate level components are unbound CHAPTER 6 50 © 1999. c : IN BIT. COMPONENT n1 PORT (i1: IN BIT. END d_latch. q : OUT BIT). END sr_based. dbar). Zainalabedin Navabi . r. o1: OUT BIT). c. q : OUT BIT). dbar. c2 : n1 PORT MAP (d.

c : IN BIT.Design Configuration ENTITY d_register IS PORT (d : IN BIT_VECTOR. q(i)). c : IN BIT. END COMPONENT. c. BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i). q : OUT BIT_VECTOR). END d_register. Zainalabedin Navabi . END latch_based. q : OUT BIT). • Generically generate a register • Unbound VHDL description for an n-bit latch • Configuration specification is not included CHAPTER 6 51 © 1999. END GENERATE. -ARCHITECTURE latch_based OF d_register IS COMPONENT dl PORT (d.

Design Configuration average_gate_delay d_latch(sr_based) inv_ t(average_delay) 2 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 g4: i2 o1 i1 c2: o1 i1 g2: i2 o1 o1 3 NS 5 NS 5 NS 6 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS 5 NS 6 NS nand2_t(average_delay) di: i1 i2 g1: c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS • Composition aspect for configuring the latch_based architecture of d_register • Hierarchical configuration CHAPTER 6 52 © 1999. Zainalabedin Navabi Sr_latch (gate_level) 4 NS 5 NS 6 NS 2 NS 4 NS 2 NS 4 NS 2 NS 4 NS 5 NS 6 NS .

5 NS). • Configuring d_register for using average_delay gates CHAPTER 6 53 © 1999.nand2_t(average_delay) 9 GENERIC MAP (5 NS. FOR gate_level FOR g2. END FOR. g4 : n2 USE ENTITY WORK.Design Configuration 1 USE WORK. END FOR. FOR sr_based FOR c1 : sr USE ENTITY WORK. END FOR. END FOR. FOR g1. 6 NS). g3 : n2 2 3 4 5 6 8 USE ENTITY WORK.ALL.d_latch(sr_based). 4 NS). Zainalabedin Navabi . END FOR. END FOR. END FOR. END FOR.nand2_t(average_delay) 10 GENERIC MAP (2 NS.inv_t(average_delay) 7 GENERIC MAP (3 NS. END FOR. CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.sr_latch(gate_level). END average_gate_delay. FOR c2 : n1 USE ENTITY WORK.

3. 6. 2. 2 4 Binding 1.46 dr GENERATE STATEMENT Figure 6. 4. Zainalabedin Navabi .46 di instance of dl Figure 6. 2. 2. 8 10 Binding 1. 2.46 sr_based ARCHITECTURE Figure 6.44 Becomes Visible by: - 2 Visibility 1 3 Visibility 1. 6. 2.45 gate_level ARCHITECTURE Figure 6. 5. 5.44 instances g1.44 instances g2. 8 • Analyzing configuration constructs of the average_gate_delay configuration of d_register • Configuration declaration includes component configurations and block configurations CHAPTER 6 54 © 1999.Design Configuration Block No. 3. 5 8 Visibility 1. 3. 3. 2. g4 of n2 Figure 6. 5 7 Binding 1. 3.45 c1 instance of sr Figure 6. 6 9 Binding 1. 1 Configuration Type Configuration Declaration Block Configuration Block Configuration Component Configuration Block Configuration Component Configuration Component Configuration Block Configuration Component Configuration Component Configuration PURPOSE Visibility or Binding to: Main latch_based ARCHITECTURE Figure 6. 4. 4. 4.45 c2 instance of sr Figure 6. 2. 3 5 Visibility 1. 5. 3. g3 of n2 Figure 6. 4 6 Binding 1. 4.

inv(single_delay). i1. • Configuring d_register for using single_delay architectures of inv and nand2 • Deep inside to reach basic gates and their generic parameters CHAPTER 6 55 © 1999. FOR gate_level FOR g2.Design Configuration USE WORK. END FOR. i2.ALL. FOR g1. Zainalabedin Navabi . END FOR.nand3(single_delay) PORT MAP (i1.sr_latch(gate_level). FOR c2 : n1 USE ENTITY WORK. END FOR.nand2(single_delay). END FOR. g3 : n2 USE ENTITY WORK. o1). CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK. END single_gate_delay. END FOR. END FOR. END FOR.d_latch(sr_based). FOR sr_based FOR c1 : sr USE ENTITY WORK. g4 : n2 USE ENTITY WORK. END FOR. END FOR.

'0' AFTER 0800 NS. • Demonstrating the use of configurations in configuration specifications • Test bench for the single_delay architecture of d_register CHAPTER 6 56 © 1999. FOR r8 : reg USE CONFIGURATION WORK. BEGIN r8: reg PORT MAP (data.Design Configuration ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0). END single. '0' AFTER 0300 NS. '1' AFTER 0200 NS. SIGNAL data. '0' AFTER 1800 NS. X"AA" AFTER 0500 NS. data <= X"00". '1' AFTER 1700 NS. clk <= '0'. clk. Zainalabedin Navabi .single_gate_delay. c : IN BIT. X"55" AFTER 1500 NS. outdata : BIT_VECTOR (7 DOWNTO 0). SIGNAL clk : BIT. END COMPONENT. q : OUT BIT_VECTOR (7 DOWNTO 0) ). '1' AFTER 0700 NS. outdata).

Zainalabedin Navabi . iterative hardware • The final example • Will illustrate indexing for alternative binding • Parity generator/checker circuit CHAPTER 6 57 © 1999.Design Configuration a(0) im(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) im(1) im(2) im(3) im(4) im(5) im(6) odd even One more configuration declaration example.

END inv_t. PORT (i1. END average_delay. o1 : OUT BIT). ---ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS.Design Configuration ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS. tphl : TIME := 3 NS). tphl : TIME := 7 NS). i2 : IN BIT. Zainalabedin Navabi . END xor2_t. END average_delay. PORT (i1 : IN BIT. o1 : OUT BIT). -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. • Components needed for this design • Timed XOR and INV gates needed for the design of the parity circuit CHAPTER 6 58 © 1999. -ARCHITECTURE average_delay OF xor2_t IS BEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2.

im(0)). o1: OUT BIT). a(i+1).Design Configuration ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0). middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1). o1: OUT BIT). END parity. inv: n1 PORT MAP (im(6). END COMPONENT. last: odd <= im(6). SIGNAL im : BIT_VECTOR ( 0 TO 6 ). even). COMPONENT n1 PORT (i1: IN BIT. odd. Zainalabedin Navabi . im(i)). END GENERATE. even : OUT BIT). a(1). -ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT (i1. • Parity circuit description • No configuration specification for the inverter and the exclusive OR gate CHAPTER 6 59 © 1999. i2: IN BIT. END iterative. END COMPONENT. BEGIN first: x2 PORT MAP (a(0).

and OTHERS the rest CHAPTER 6 60 © 1999. FOR inv : n1 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS. END FOR. END FOR. 5 NS). • Parity circuit configuration declaration • Index label of the generate statement • Can use OTHERS. END FOR.xor2_t (average_delay) GENERIC MAP (5 NS. 7 NS). pick some.xor2_t (average_delay) GENERIC MAP (6 NS.inv_t (average_delay) GENERIC MAP (5 NS. FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK. 5 NS). END FOR. END FOR. END FOR. END FOR. FOR middle ( 6) FOR m : x2 USE ENTITY WORK.Design Configuration CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK. 5 NS). Zainalabedin Navabi . END parity_binding.

Use of Libraries Value 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' Representing Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care Standard and user libraries. Zainalabedin Navabi . start with the nine-value standard logic • None standard values • Std_logic logic value system • Satisfies most hardware design needs CHAPTER 6 61 © 1999.

U X 0 1 Z W L H - U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U' X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' 0 '0' '0' '0' '0' '0' '0' '0' '0' '0' 1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' L '0' '0' '0' '0' '0' '0' '0' '0' '0' H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' 'U’ 'X' '0' 'X’ 'X' 'X' '0' 'X' 'X' • AND table for std_logic type • All logic tables are defined and available • Changing BIT to std_logic works in most cases CHAPTER 6 62 © 1999. Zainalabedin Navabi .Use of Libraries .

Use of Libraries LIBRARY IEEE. END average_delay_mvla. i2 : IN std_logic. USE IEEE. PORT (i1.ALL. • A two-input NAND gate in std_logic value system • Specify library and package • All basic functions are available in this package CHAPTER 6 63 © 1999. tphl : TIME := 4 NS). Zainalabedin Navabi . -ARCHITECTURE average_delay_mvla OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. o1 : OUT std_logic).std_logic_1164. END nand2_t. -ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS.

1997 • Other libraries • Can define our own • Directory of ls7400 library containing package declarations. 1997 June 8. Zainalabedin Navabi . 1997 June 6. entities and architectures CHAPTER 6 64 © 1999. 1997 June 6.Use of Libraries LIBRARY ls7400 simple_gates inv inv(single_delay) nand2 nand2(single_delay) nand3 nand3(single_delay) User: John Designer PACKAGE DECLARATION ENTITY ARCHITECTURE ENTITY ARCHITECTURE ENTITY ARCHITECTURE Date June 9. 1997 June 8. 1997 June 6. 1997 June 6.

USE ls7400. • Visibility of user libraries and packages • Making all declarations of simple_gates package of ls7400 library available CHAPTER 6 65 © 1999. STD is the standard library that includes the STANDARD and TEXTIO packages All other libraries and packages must be explicitly specified Use ls7400 as a user defined library LIBRARY ls7400.Use of Libraries • • • • WORK is the default library.simple_gates. Zainalabedin Navabi .ALL.

BEGIN g1 : n2 PORT MAP (s. g2 : n2 PORT MAP (r.simple_gates. g4 : n2 PORT MAP (im3. USE ls7400. im2.Use of Libraries LIBRARY ls7400. im4 : BIT. • Using user libraries • Using component declarations of simple_gates package of ls7400 library for description of set-reset latch CHAPTER 6 66 © 1999. c. END gate_level. im4. Zainalabedin Navabi . g3 : n2 PORT MAP (im1. im1).ALL. im2. -ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1. q <= im3. c. im3). im4). im3. im2).

Use of Libraries LIBRARY ls7400. • Visibility into libraries • Making all entities and architectures of the ls7400 library available CHAPTER 6 67 © 1999. Zainalabedin Navabi . USE ls7400.ALL.

Use of Libraries LIBRARY ls7400. USE ls7400. … FOR g1. .nand2 (single_delay). Zainalabedin Navabi .ALL. . g3 : n2 … USE ENTITY ls7400. • Binding indication needs library name • Using a component configuration for associating g1 and g3 instances of n2 of Figure 661 with nand2 of ls7400 CHAPTER 6 68 © 1999. … END FOR.

We began with the definition of subprograms and emphasized on the use of functions and procedures for simplifying descriptions. We believe VHDL is very strong in this area and serious designers should learn to take advantage of such capabilities of the language. Zainalabedin Navabi . • End Of Chapter 6 CHAPTER 6 69 © 1999. As stated earlier. a large design environment with many logic families and technologies to choose from requires a great deal of library management and parameter specification. Next. design parameterization methods save many compilation runs. Although simple examples and college level exercises can avoid some of these language issues. For small circuits and experimental models. this topic is used mainly for the organization of a design. the subject of packaging utilities and components was addressed.Summary This chapter provides tools for better hardware descriptions and design organization. Design parameterization and configuration of designs were also discussed in great detail.

3 Signal Attributes 7.2 Using Real Numbers For Timing Calculations 7.4 Array Declarations 7.2.4.4 Entity Attributes 7.2 Record Types 7.8 SUMMARY CHAPTER 7 1 © 1999.2.5 Sign Operators 7.2.6 Type Conversions 7.CHAPTER 7 UTILITIES FOR HIGH LEVEL DESCRIPTIONS 7.2.2.1 Logical Operators 7.1 Array Attributes 7.4 Adding Operators 7.1.3 Alias Declaration 7.2 VHDL OPERATORS 7.4.2 Relational Operators 7.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING 7.2.4.4.1.5 File Type and External File I/O 7.6 USER-DEFINED ATTRIBUTES 7.2 Type Attributes 7.8 Aggregate Operation 7. Navabi and McGraw-Hill Inc.1.4 Access Types 7.1.7 Nota Operators 7.1.2.5.4.3 Shift Operators 7.2.4.5.4 OTHER TYPES AND TYPE RELATED ISSUES 7.1 TYPE DECLARATIONS AND USAGE 7. Global Objects 7.5.1 Enumeration Type for Multi-Value Logic 7.1 Subtypes 7.7 PACKAGING BASIC UTILITIES 7.3 Physical Types and RC Timing 7. Z.5.5 PREDEFINED ATTRIBUTES 7.6 Multiplying Operators 7.5. .

initial TYPE qit IS ( ‘0’ . Navabi and McGraw-Hill Inc. Z. 'X'). ‘X’ ) . . 'Z'. ‘Z’ . ‘1’ . identifier enumeration element enumeration element enumeration element enumeration element enumeration type definition type definition type declaration Will use an enumeration type for demonstrating type declarations • 4-value qit type will be used • Enumeration type declaration • Initial value of objects of this type is the left-most enumeration element of the base type CHAPTER 7 2 © 1999. '1'.TYPE DECLARATIONS AND USAGE TYPE qit IS ('0'.

TYPE DECLARATIONS AND USAGE In: 0 1 Z X 1 0 0 X Out • Will develop basic logic gates based on this type • Input-Output mapping of an inverter in qit logic value system CHAPTER 7 3 © 1999. Navabi and McGraw-Hill Inc. Z. .

basic_utilities. -.From PACKAGE USE : qit ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS. PORT (i1 : IN qit. Z.ALL. . • VHDL description of an inverter in qit logic value system • Inputs and outputs are of type qit • Assumes out package contains this type definition CHAPTER 7 4 © 1999. -ARCHITECTURE double_delay OF inv_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. tphl : TIME := 3 NS). o1 : OUT qit). END inv_q. Navabi and McGraw-Hill Inc. END double_delay.TYPE DECLARATIONS AND USAGE USE WORK.

o1<= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE UNAFFECTED. Navabi and McGraw-Hill Inc. . Z. o1 <= a WHEN cond =’1’ ELSE o1. • • • • A new construct is presented This is conditional signal assignment Several alternatives exist in its usage Can use unaffected for assignments to outputs CHAPTER 7 5 © 1999.TYPE DECLARATIONS AND USAGE Z <= a AFTER 5 NS WHEN d = ’1’ ELSE UNAFFECTED WHEN e = ’1’ ELSE b AFTER 5 NS WHEN f = ’1’ ELSE c AFTER 5 NS. or o1 <= a WHEN cond =’1’ ELSE UNAFFECTED.

TYPE DECLARATIONS AND USAGE o1 <= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE ‘X’ AFTER tplh . target waveform condition waveform condition waveform condition waveform conditional signal assignment • Syntax details of a conditional signal assignment • Condition waveform has a series of waveforms with or without condition CHAPTER 7 6 © 1999. . Navabi and McGraw-Hill Inc. Z.

Navabi and McGraw-Hill Inc. CHAPTER 7 7 . Z.TYPE DECLARATIONS AND USAGE In1: In2: 0 1 Z X 0 1 1 1 1 1 1 0 0 X Out Z 1 0 0 X 1 X X X X • We will develop more basic structures in this 4-value logic system • Input-Output mapping of a NAND gate in qit logic value system • Here we assume 1 for high impedance © 1999.

TYPE DECLARATIONS AND USAGE USE WORK.FROM PACKAGE USE : qit ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS.basic_utilities. -. END double_delay. . • • • • VHDL description of a NAND gate in qit logic system A conditional signal assignment is used This is a concurrent statement Conditions are checked sequentially from left to right CHAPTER 7 8 © 1999. Navabi and McGraw-Hill Inc.Can Use: UNAFFECTED. i2 : IN qit. o1 : OUT qit). tphl : TIME := 5 NS).ALL. Z. PORT (i1. END nand2_q. -. -ARCHITECTURE double_delay OF nand2_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh.

TYPE DECLARATIONS AND USAGE inv_rc(double_delay) c_load 25K Ω i1 15K Ω o1 A CMOS inverter example for demonstrating floating point and physical types • • • • Composition aspect of an inverter with RC timing Timing depends on the R and C values Exponential timing is ≅ 3RC Will first demonstrate floating point numbers CHAPTER 7 9 © 1999. Z. . Navabi and McGraw-Hill Inc.

-.0.FROM PACKAGE USE: qit ENTITY inv_rc IS GENERIC (c_load : REAL := 0. CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1.basic_utilities.0E15) * 3 FS. Z.Ohms END inv_rc. . END double_delay. -.Ohms CONSTANT rpd : REAL := 15000. -. CONSTANT rpu : REAL := 25000.Farads PORT (i1 : IN qit.0. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. oull-down and load capacitance • Constant values are used in the conditional signal assignment CHAPTER 7 10 © 1999. o1 : OUT qit). Navabi and McGraw-Hill Inc. • An inverter model with RC timing parameters • Delay cannot be a fraction of FS • Delay values are calculated based on pull-up.ALL.066E-12).0E15) * 3 FS. -.TYPE DECLARATIONS AND USAGE USE WORK.

• • • • Type definition for defining the capacitance physical type Use physical types instead of floating point Base unit must be there All others are then defined CHAPTER 7 11 © 1999. END UNITS. mfr = 1000 ufr.TYPE DECLARATIONS AND USAGE TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr. . ufr = 1000 nfr. far = 1000 mfr. kfr = 1000 far. Z. nfr = 1000 pfr. -. Navabi and McGraw-Hill Inc.Femto Farads (base unit) pfr = 1000 ffr.

. Z. Navabi and McGraw-Hill Inc. -. • Type definition for defining the resistance physical type • Another physical type • RANGE specifies the largest value in terms of base units that an object of this type can get • Intermediate values can take larger values CHAPTER 7 12 © 1999. g_o = 1000 m_o. END UNITS. k_o = 1000 ohms.Milli-Ohms (base unit) ohms = 1000 l_o.TYPE DECLARATIONS AND USAGE TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o. m_o = 1000 k_o.

Navabi and McGraw-Hill Inc. capacitance ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr).TYPE DECLARATIONS AND USAGE USE WORK. END double_delay.FROM PACKAGE USE: qit. CONSTANT rpu : resistance := 25000 ohms. END inv_rc. . -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000.ALL. -. • Using resistance and capacitance physical types in the description of an inverter • Resolutions of Millie-ohms and Femto-farads are taken into account • Divide by 1000 adjusts the time units to FS • Will do it with a better style later CHAPTER 7 13 © 1999. CONSTANT rpd : resistance := 15000 ohms.basic_utilities. PORT (i1 : IN qit. Z. CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. resistance. o1 : OUT qit).

. 0 TO 7 ) OF qit.TYPE DECLARATIONS AND USAGE TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit. Navabi and McGraw-Hill Inc. TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0. TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble. Demonstrating array definition and object declaration • • • • Declaring array types Arrays may be ascending or descending Objects can be indexed as declared n-dimensional arrays may be declared CHAPTER 7 14 © 1999. TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit. Z. TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit.

Navabi and McGraw-Hill Inc. Z.TYPE DECLARATIONS AND USAGE TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit . . identifier range discrete range index constrained constraint array definition type declaration element_subtype_indication • Syntax details of an array type declaration • This is a type declaration • Contains constraint array definition CHAPTER 7 15 © 1999.

SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. ‘1’. Navabi and McGraw-Hill Inc. ‘Z’. ‘1’. OTHERS => ‘1’). association by position • Can use aggregate operation. association by name CHAPTER 7 16 © 1999. ‘1’. . SIGNAL sq8 : qit_byte := (5 => ‘Z’. ‘Z’. ‘1’). SIGNAL sq8 : qit_byte := (‘Z’. OTHERS => ‘1’). ‘Z’. • Objects of array type may be initialized when declared • If explicit initialization is missing. OTHERS => ‘1’). Z.TYPE DECLARATIONS AND USAGE SIGNAL sq8 : qit_byte := "ZZZZZZZZ". 3 TO 4 => ‘X’. all elements are initialized to left-most of array element • Can form a vector of initial values • Can use aggregate operation. SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’.

-.middle 8 bit slice of sq16 to sq8.right rotate sq8. -. sq1 <= sq_4_8 (0.third nibble (number 2) of sq_nibble_8 into sq4. sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5).reversing sq8 into sq4. SIGNAL sq_4_8 : qit_4by_8.reversing sq8 into sq4. sq4(1). -.reversing sq8 into sq4. -. sq4 <= (sq8(2). . (sq4(0). sq8(3). SIGNAL sq16 : qit_word.sq4 into left 4 bit slice of sq16. 7). sq16 (15 DOWNTO 12) <= sq4. Valid Operations: sq8 <= sq16 (11 DOWNTO 4). sq8(4). SIGNAL sq8 : qit_byte. sq4 <= sq_nibble_8 (2). sq8(5)). • • • • • Signal declarations and signal assignments Arrays may be sliced and used on RHS or LHS Aggregate may be used on RHS and LHS Can concatenate any length or slice size Aggregates operation works with array elements only CHAPTER 7 17 © 1999. SIGNAL sq4 : qit_nibble.-. -. sq4(3)) <= sq8 (5 DOWNTO 2). sq1 <= sq_nibble_8(2)(3). sq8 <= sq8(0) & sq8 (7 DOWNTO 1).TYPE DECLARATIONS AND USAGE Signal Declarations: SIGNAL sq1 : qit. SIGNAL sq_nibble_8 : qit_nibble_by_8.nibble 2.lower right bit of sq_4_8 into sq1. bit 3 of sq_nibble_8 into sq1. sq4(2). Navabi and McGraw-Hill Inc. -. -. -. Z.

Slice example: sq_nibble_8(2)(3 DOWN To 2) • Referencing bits of a vector. Z. Navabi and McGraw-Hill Inc. . Nice try! • An slicing example is also shown here CHAPTER 7 18 © 1999. reversing bits of sq8 and assigning them to sq4 • Cannot index opposite to what the type is defined as.TYPE DECLARATIONS AND USAGE Concatenation example: sq4: 3 2 1 0 sq8: 7 6 5 4 3 2 1 0 sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5).

(OTHERS => (0 TO 1 => ‘1’. OTHERS =>’0’)). (OTHERS => (0 TO 1 => ‘1’. 'X'. 'Z'. OTHERS => (0 => ‘X’. '0'. '0' ) ). '1'. Navabi and McGraw-Hill Inc. '0'. 'X' ). 'X'. '0'. '1'. 'Z' ). '0'. 'Z'. 'X'. • Initializing or assignment to a two dimensional array • Right most index applies to deepest set of parenthesis • Can initialize the same way as signal and variable assignment • Constants must have static values CHAPTER 7 19 © 1999. ( 'Z'. 7 => ‘X’. 'Z'. 'X'. '0'. OTHERS =>’1’). Z. '0'. 'X'.TYPE DECLARATIONS AND USAGE SIGNAL sq_4_8 : qit_4by8 := ( ( '0'. SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := (OTHERS => “11000000”). ( 'X'. . (OTHERS => (OTHERS => ‘Z’)). 'X'. 'Z'. 'Z'. 0 => (OTHERS => ‘X’). '1'. 'Z'. OTHERS =>’0’)). '1'. '1'. ( '1'. '1' ). '1'. … := (OTHERS => (OTHERS => ‘0’)) sq_4_8 <= ( 3 => (OTHERS => ‘X’).

Z. OTHERS =>’0’)). Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE qit_2d IS ARRAY (qit. OTHERS => (‘0’ => ‘1’. qit) OF qit. Demonstrating non-integer RANGE and index specification • Instead of integers. CONSTANT qit_nand2_table : qit_2d := ( ‘0’ => (OTHERS => ‘1’). ‘X’ => (‘0’ => ‘1’. ‘X’ => ‘1’. OTHERS => ‘X’). can use other types for array range specification • Then an object of this type may be indexed by enumeration elements of the type in the array range specification CHAPTER 7 20 © 1999. .

'1'). . ('1'. ('1'.basic_utilities.TYPE DECLARATIONS AND USAGE USE WORK. i2 : IN qit. o1 : OUT qit). -ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1'.'0'.'X'. i2) AFTER (tplh + tphl) / 2. • Using qit enumeration type for the discrete range of a two-dimensional array • The constant table is an array qit qit if qit elements CHAPTER 7 21 © 1999.'0'. END nand2_q. tphl : TIME := 5 NS).'0'. Navabi and McGraw-Hill Inc.'X').ALL. BEGIN o1 <= qit_nand2_table (i1.'X')).FROM PACKAGE USE: qit.'0'. -.'1'. ('1'. qit_2d ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS.'1'. PORT (i1. Z. END average_delay.'X'.'X').

Z. . Unconstrained array declarations. TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT. usage and definition • BIT_VECTOR is a predefined unconstrained array of BITs • STRING is that of CHARACTERS • Can define our own • This is read as RANGE Box CHAPTER 7 22 © 1999. TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER.

TYPE DECLARATIONS AND USAGE TYPE integer_vector IS ARRAY ( NATURAL RANGE <> ) OF INTEGER . Z. . identifier type_mark index_subtype definition unconstrained array definition type declaration element_subtype_indication • Syntax details of an unconstrained array declaration • We will use this array in our basic utilities • Cannot have unconstrained array of an unconstrained array. Nice try! CHAPTER 7 23 © 1999. Navabi and McGraw-Hill Inc.

END LOOP. Navabi and McGraw-Hill Inc. buf). • • • • A generic version of the apply_data procedure Uses our own integer_vector from basic_utilities Procedure output. is also unconstrained All will be known when procedure is called CHAPTER 7 24 © 1999.TYPE DECLARATIONS AND USAGE PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR. BEGIN FOR i IN values'RANGE LOOP int2bin (values(i). target <= TRANSPORT buf AFTER i * period. Z. END apply_data. . target. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE). CONSTANT values : IN integer_vector.

END GENERATE. • • • • Keeping our promise of a better n-bit comparator An n-bit comparator Wiring n number of one-bit comparators The integer n depends on the size of a CHAPTER 7 25 © 1999. im(i*3-3). . a_gt_b. im(1). a_lt_b). END structural. im(0). b(i). b(i). b(i). a_lt_b : OUT BIT). a_gt_b. END GENERATE.bit_comparator (functional). im(i*3-2).TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator IS PORT (a. gt. eq. im(i*3-3). gt. gt. Navabi and McGraw-Hill Inc. im(i*3-1). a_gt_b. a_eq_b. BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). a_eq_b. FOR ALL : comp1 USE ENTITY WORK. m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). CONSTANT n : INTEGER := a'LENGTH. im(i*3-1). im(i*3+0). lt. eq. im(i*3-2). a_eq_b. a_lt_b : OUT BIT). Z. lt : IN BIT. END COMPONENT. END n_bit_comparator. b : IN BIT_VECTOR. END GENERATE. b. lt : IN BIT. im(2) ). im(i*3+1). im(i*3+2) ). -ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a. END GENERATE. eq.

FOR a1 : comp_n USE ENTITY WORK. 500 NS). gtr. b. b : BIT_VECTOR (5 DOWNTO 0). b : IN bit_vector. eq. SIGNAL a. -. SIGNAL vdd : BIT := '1'. 00&15&57&17. BEGIN a1: comp_n PORT MAP (a. lss. • Using generic apply_data procedure for testing n_bit_comparator • All unconstrained arrays are fixed according to the parameters passed to them • Can use different size integer vectors CHAPTER 7 26 © 1999.FROM PACKAGE USE: apply_data which uses integer_vector ARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a. a_eq_b. 500 NS). gtr : BIT. gnd. lss). END COMPONENT. lt : IN BIT. -USE WORK. SIGNAL eql. 00&43&14&45&11&21&44&11. SIGNAL gnd : BIT := '0'.basic_utilities. apply_data (a. gnd. gt. a_lt_b : OUT BIT). vdd.ALL. a_gt_b.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator_test_bench IS END n_bit_comparator_test_bench . END procedural. .n_bit_comparator(structural). apply_data (b. Z. eql. Navabi and McGraw-Hill Inc.

--Declare a logical file and open in READ_MODE FILE input_logic_value_file3: logic_data OPEN READ_MODE IS “input. Navabi and McGraw-Hill Inc. --Just declare a logical file FILE input_logic_value_file2: logic_data IS “input. . --Declare a logical file and open with the specified mode Primitive utilities for file declaration and file specification • input_logic_value_file: logical name for file of logic_data type • An explicit OPEN statement must be used for opening • Can open a file in READ_MODE. Z. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER.dat”.TYPE DECLARATIONS AND USAGE First. Then a logical file name must be declared FILE input_logic_value_file1: logic_data.dat”. WRITE_MODE or APPEND_MODE CHAPTER 7 27 © 1999.

dat”. --Just declare a logical file. Then a logical file name must be declared FILE output_logic_value_file1: logic_data.TYPE DECLARATIONS AND USAGE First. WRITE_MODE or APPEND_MODE CHAPTER 7 28 © 1999. Z. --Declare a logical file and open with the specified mode OUPUT FILE : WRITE_MODE or APPEND MODE • An explicit OPEN statement must be used for opening the file in the first alternative • Can open a file in READ_MODE. . Navabi and McGraw-Hill Inc. open later FILE output_logic_value_file2: logic_data OPEN WRITE_MODE IS “input. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER.

TYPE DECLARATIONS AND USAGE An explicit OPEN is needed if file is not implicitly opened FILE_OPEN (input_logic_value_file. NAME_ERROR. The standard package includes: TYPE FILE_OPEN_STATUS IS (OPEN_OK. “output. . FILE_CLOSE (output_logic_value_file). Navabi and McGraw-Hill Inc. WRITE_MODE). • File open alternatives • Status parameter must be declared first • Close a file using its logical name CHAPTER 7 29 © 1999. “input. Z. MODE_ERROR) Closing a file: FILE_CLOSE (input_logic_value_file). WRITE_MODE). FILE_OPEN (output_logic_value_file. READ_MODE). FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS.dat”.dat”.dat”. “output. STATUS_ERROR. output_logic_value_file.

ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current. END IF. period : IN TIME) IS VARIABLE char : CHARACTER. . Z. "unix_file.bit". file_name. IF char = '0' THEN s <= TRANSPORT '0' AFTER current. Navabi and McGraw-Hill Inc. END assign_bits. END IF. BEGIN FILE_OPEN (input_value_file. VARIABLE current : TIME := 0 NS. READ_MODE). FILE input_value_file : logic_data. char). END LOOP. • file_name is a string input containing physical file name • A procedure for reading characters from a file and assigning them to a BIT type • File type is declared in the procedure • En explicit open statement is used CHAPTER 7 30 © 1999. 1500 NS). Calling this procedure: assign_bits (a_signal. file_name : IN STRING. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. IF char = '0' OR char = '1' THEN current := current + period.TYPE DECLARATIONS AND USAGE PROCEDURE assign_bits ( SIGNAL s : OUT BIT.

TYPE DECLARATIONS AND USAGE Declare in an architecture: FILE input_value_file: logic_data IS “my_file. Call the pocedure: read_from_file (SIGNAL target : OUT BIT. it reads the entire unix_file. Z. Navabi and McGraw-Hill Inc.bit”. because a new file object is declared each time it is called • To avoid. declare a file object outside of the procedure CHAPTER 7 31 © 1999. . when assign_bits is called. this_file : IN FILE).bit • Each time reading begins from the top of the file. • In the previous example.

Z. .VHDL OPERATORS Logical Operators: AND. OR. NOR. Navabi and McGraw-Hill Inc. NAND. XNOR. b). NOT Examples of use: x <= a XNOR b. Outlining VHDL operators and their format of use • Logical operators • Order of operand must remain the same • The second format makes operands appear as functions CHAPTER 7 32 © 1999. x <= “XOR” (a. b_vector). XOR. x_vector <= “AND” (a_vector. x_vector <= a_vector AND b_vector.

b_boolean <= i1 /= i2. >= Examples of use: a_boolean <= i1 > i2.VHDL OPERATORS Relational operators: =. >. >. /=. . <=. <=. Z. and ‘X’ is larger all the rest --for BIT: ‘1’ is greater than ‘0’ • = and /= operate on operands of any type • (<. and >=) when used with array operands perform ordering operations • These return TRUE or FALSE based on values of array elements starting from the left CHAPTER 7 33 © 1999. --if a_bit_vector is “00011” and b_bit_vector is “00100” a_bit_vector < b_bit_vector returns TRUE --for qitt: ‘0’ is less than ‘1’. Navabi and McGraw-Hill Inc. <.

VHDL OPERATORS SLL SLA SRL SRA ROL ROR Shift/Rotate Shift Shift Shift Shift Rotate Rotate Left/Right Left Left Right Right Left Right Logical/Arithmetic Logical Arithmetic Logical Arithmetic Logical Logical VHDL operators are formally presented in the next few slides • Shift operators • operand SIFT_OPERATOR number_of_shifts • fill value is the left-most enumeration element CHAPTER 7 34 © 1999. . Z. Navabi and McGraw-Hill Inc.

Z. Navabi and McGraw-Hill Inc.VHDL OPERATORS Start with aq aq SLL 1 aq SLA 1 aq SRL 1 aq SRA 1 aq ROL 1 aq ROR 1 Z 0 0 0 Z 0 X 0 1 1 Z Z 1 Z 1 X X 0 0 X 0 X Z Z 1 1 Z 1 Z 1 1 X X 1 X 1 0 0 Z Z 0 Z 0 X X 1 1 X 1 X 0 X 0 0 Z 0 • Application of shift operators • The result must be placed in a LHS • Left operand remains unchanged CHAPTER 7 35 © 1999. .

/. but allows only elements • Adding.returns remainder of absolute value division (a. . & Multiplying operators: *. Navabi and McGraw-Hill Inc. multiplying. b) a_int MOD b_int -. like concatenation. ABS Examples of use: a+b “+” (a. REM Other operators: ().both integers a_int REM b_int -. MOD. **. aggregate and other operators • Format of use is shown for each operator CHAPTER 7 36 © 1999. -. b.VHDL OPERATORS Adding operators: +. Z. c) – aggregate.

OR. and NOT for qit as easily as for BIT • Tables for the basic logic functions in the qit four value logic system CHAPTER 7 37 © 1999.SUBPROGRAM PARAMETER TYPES AND OVERLOADING a: b: 0 1 Z X 0 0 0 0 0 1 0 1 1 X z = a. Navabi and McGraw-Hill Inc. Z. .b (a) a: b: 0 1 Z X 0 0 1 1 X 1 1 1 1 1 Z 1 1 1 1 X X 1 1 X Z 0 1 1 X 0 X X X X z=a+b (b) a: 0 1 Z X 1 0 0 X z = a' Demonstrating overloading VHDL operators and subprograms (c) • Want to use AND.

qit) OF qit. 'Z'. b : qit) RETURN qit.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. Navabi and McGraw-Hill Inc. 'X'). FUNCTION "NOT" (a : qit) RETURN qit. TYPE qit_1d IS ARRAY (qit) OF qit. '1'. . TYPE qit_2d IS ARRAY (qit. FUNCTION "OR" (a. • In a package declare qit and arrays based on this type • Declare functions to be overloaded • Overloading: identify a function with its operands and name CHAPTER 7 38 © 1999. Z. -- FUNCTION "AND" (a. b : qit) RETURN qit.

'X'.'X')).'1'.'X'). END "AND".'0'. ('0'. FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1'.'X')). END "OR". ('X'.'X').'1'. ('1'.'0'. ('1'. Navabi and McGraw-Hill Inc. • Overloading basic logical functions for the qit four value logic system • Definition of functions CHAPTER 7 39 © 1999.'X').'1'.'1'). Z. FUNCTION "OR" (a. b). .'1'.'0').'1'.'1'. ('0'. ('0'.'1'. b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0'. b).'1'.'1'. BEGIN RETURN qit_not_table (a).'X'). BEGIN RETURN qit_or_table (a.'1'. END "NOT".SUBPROGRAM PARAMETER TYPES AND OVERLOADING FUNCTION "AND" (a.'0'. BEGIN RETURN qit_and_table (a.'1').'1'. b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0'.'X'.'0'.'1'.

USE WORK. -ARCHITECTURE average_delay OF nand2_q IS BEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2. END inv_q. END average_delay. -. • Using overloaded operators • Cannot use NAND since it is only defined for BIT CHAPTER 7 40 © 1999.ALL.FROM PACKAGE USE: qit. END average_delay. "NOT" ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS.FROM PACKAGE USE: qit. o1 : OUT qit). -. Z. tphl : TIME := 3 NS). "AND" ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS. PORT (i1.basic_utilities. o1 : OUT qit).basic_utilities. END nand2_q.ALL. tphl : TIME := 4 NS). Navabi and McGraw-Hill Inc. i2 : IN qit. .SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. -ARCHITECTURE average_delay OF inv_q IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. PORT (i1 : IN qit.

-ARCHITECTURE average_delay OF nand3_q IS BEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2. -. i2.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. • Basic gates in the qit logic value system using overloaded AND operators • Can also overload NAND and other operators • Std_logic has done this for its types CHAPTER 7 41 © 1999. Navabi and McGraw-Hill Inc. i3 : IN qit.FROM PACKAGE USE: qit.ALL.basic_utilities. END average_delay. tphl : TIME := 5 NS). o1 : OUT qit). END nand3_q. PORT (i1. Z. . "AND" ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS.

Z. . b : capacitance) RETURN TIME. Navabi and McGraw-Hill Inc.SUBPROGRAM PARAMETER TYPES AND OVERLOADING In the declaration: FUNCTION "*" (a : resistance. • Overloading the multiplication operator • Returns TIME when multiplying resistance capacitance physical types • Function declaration. END "*". the "*" subprogram body and CHAPTER 7 42 © 1999. In a package body: FUNCTION "*" (a : resistance. b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000.

END inv_rc. o1 : OUT qit). CONSTANT rpu : resistance := 25 k_o. . • Using the overloaded multiplication operator • The double_delay architecture of inv_rc CHAPTER 7 43 © 1999. "*" ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. CONSTANT tphl : TIME := rpd * c_load * 3.basic_utilities. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3. -. PORT (i1 : IN qit. Navabi and McGraw-Hill Inc. resistance. capacitance. CONSTANT rpd : resistance := 15 k_o.ALL. END double_delay.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK.FROM PACKAGE USE: qit. Z.

WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current. Z. WHEN '1' => s <= TRANSPORT '1' AFTER current. VARIABLE current : TIME := 0 NS. FILE input_value_file : logic_data.period. CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current. WHEN OTHERS => current := current . BEGIN FILE_OPEN (input_value_file. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. period : IN TIME) IS VARIABLE char : CHARACTER. END CASE. file_name : IN STRING. char). TYPE logic_data IS FILE OF CHARACTER. file_name : IN STRING. READ_MODE). '1'. END LOOP. WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current. 'Z'. • Overloading the assign_bits procedure for accepting and producing qit data • Procedure and other necessary declarations • Subprogram body uses a case statement CHAPTER 7 44 © 1999. END assign_bits. . Navabi and McGraw-Hill Inc. PROCEDURE assign_bits ( SIGNAL s : OUT qit. period : IN TIME). file_name. current := current + period. PROCEDURE assign_bits ( SIGNAL s : OUT qit. 'X').SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'.

WHEN ‘X’  ‘x’ => target <= TRANSPORT ‘X’ AFTER current. WHEN OTHERS => current := current – period. WHEN ‘1’ => target <= TRANSPORT ‘1’ AFTER current. Z. WHEN ‘Z’  ‘z’ => target <= TRANSPORT ‘Z’ AFTER current. sequence_of statements case_statement alternative expression choice case_statement alternative sequence_of statements sequence_of statements choices case_statement alternative case_statement alternative sequence_of statements choice sequence_of statements case_statement alternative • Syntax details of a sequential case statement • Consists of several case alternatives • All choices must be filled CHAPTER 7 45 © 1999. END CASE.SUBPROGRAM PARAMETER TYPES AND OVERLOADING CASE char IS WHEN ‘0’ => target <= TRANSPORT ‘0’ AFTER current. . Navabi and McGraw-Hill Inc.

BEGIN assign_bits (a. Navabi and McGraw-Hill Inc. o1 : OUT qit). END COMPONENT. -ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr). Z.qit". "data. resistance. i1 : inv PORT MAP (a. 500 NS). PORT (i1 : IN qit.ALL.FROM PACKAGE: qit.basic_utilities.inv_rc(double_delay). z). z : qit. SIGNAL a.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. • Calling the overloaded assign_bits for testing an inverter • The inverter with RC delay is being tested • Type qit operand of the procedure causes the new assign_bits to be called CHAPTER 7 46 © 1999. END input_output. . -. assign_bits ENTITY tester IS END tester. FOR ALL : inv USE ENTITY WORK. capacitance.

records. and aliases are discussed • • • • Subtypes are used for compatibility Base type of a subtype is the original type nibble_bits is not compatible with any BIT_VECTOR rit and bin are fully compatible with qit CHAPTER 7 47 © 1999. SUBTYPE rit IS qit RANGE '0' TO 'Z'. Z. . Navabi and McGraw-Hill Inc. SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9. subtypes. TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT.OTHER TYPES AND RELATED ISSUES SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0). Other type related issues. SUBTYPE bin IS qit RANGE '0' TO '1'.

END RECORD. adr : address.OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode address Instruction format TYPE opcode IS (sta. lda. add. and. instr. mde : mode. TYPE address IS BIT_VECTOR (10 DOWNTO 0). instr <= (adr => (OTHERS => ‘1’). 0. CHAPTER 7 . TYPE instruction_format IS RECORD opc : opcode.opc <= lda. "00000000000"). instr. TYPE mode IS RANGE 0 TO 3. jsr). Z. jmp.adr <= "00011110000". instr. Navabi and McGraw-Hill Inc. sub. nop. SIGNAL instr : instruction_format := (nop.mde <= 2. opc => sub) • • • • • • Record Type Three fields of an instruction Declaration of instruction format A signal of record type Referencing fields of a record type signal Record aggregate 48 © 1999. mde => 2.

OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode page address offset ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr. page and offset addresses • Alias declaration for the page and offset parts of the address • Assignments to page and offset parts of address CHAPTER 7 49 © 1999.adr (7 DOWNTO 0).adr (10 DOWNTO 8). Z. • Alias declaration. ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr. Navabi and McGraw-Hill Inc. offset <= X"F1". . page <= "001".

ACCESS type and implementation and usage of linked lists is demonstrated • Linked list graphical representation • Definition in VHDL starts with an incomplete type definition CHAPTER 7 50 © 1999. TYPE pointer IS ACCESS node. . END RECORD. link : pointer.OTHER TYPES AND RELATED ISSUES head link node data link node data link node data NULL data Integer Type link Pointer Type TYPE node. Z. Navabi and McGraw-Hill Inc. TYPE node IS RECORD data : INTEGER.

OTHER TYPES AND RELATED ISSUES Declaration of head as the head of a linked list to be created: VARIABLE head : pointer := NULL.link := NEW node. • Using the above linked list • Declaring head and linking to it CHAPTER 7 51 © 1999. Linking the next node: head. . Z. head := NEW node. Navabi and McGraw-Hill Inc. Assigning the first node to head.

END LOOP. cache : pointer := NULL. ELSE t1. 12. t1 := t1.link := NEW node. IF i = int'RIGHT THEN t1. (25. END lineup. 18. Inserting integers into the mem linked list: lineup (mem.link. Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES PROCEDURE lineup (VARIABLE head : INOUT pointer.link := NULL. 20)). 19.Insert data in the linked list head := NEW node. int : integer_vector) IS VARIABLE t1 : pointer. FOR i IN int'RANGE LOOP t1. • • • • Creating a linked list and entering data into it Head is returned as the first node of the linked list A new node of type node is obtained and assigned to head Fields of node are accessed and data is entered into them CHAPTER 7 52 © 1999. Declare mem: VARIABLE mem. t1 := head. 17. BEGIN -. .data := int(i). Z. END IF.

. DEALLOCATE (t2). BEGIN -. v : IN INTEGER) IS VARIABLE t1. Navabi and McGraw-Hill Inc. END remove.link := t2. t1.data = v THEN t2 := t1.link.OTHER TYPES AND RELATED ISSUES PROCEDURE remove (VARIABLE head : INOUT pointer. t2 : pointer. Z. t1 := t1.link. WHILE t1 /= NULL LOOP IF t1. END IF. END LOOP.link. • Removing an item from a linked list • The head of the linked list is passed • Node that follows node with value v is removed CHAPTER 7 53 © 1999.Remove node following that with value v t1 := head.

DEALLOCATE (t2).Free all the linked list t1 := head.link. END ll_utilities. END LOOP. Z. .OTHER TYPES AND RELATED ISSUES PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. head := NULL. • Freeing a linked list • Start with he head of a linked list and clear it • All nodes must be deallocated CHAPTER 7 54 © 1999. t1 := t1. END clear. t2 : pointer. WHILE t1 /= NULL LOOP t2 := t1. Navabi and McGraw-Hill Inc. BEGIN -.

END ll_utilities. DEALLOCATE (t2). int : integer_vector) IS VARIABLE t1 : pointer. END RECORD.link := NEW node.link := NULL.link. • Linked list utilities CHAPTER 7 55 © 1999.OTHER TYPES AND RELATED ISSUES PACKAGE ll_utilities IS TYPE node. head := NULL.Free all the linked list t1 := head.link. END LOOP. Z. END lineup. IF i = int'RIGHT THEN t1. t1 := t1. t1. BEGIN -. FOR i IN int'RANGE LOOP t1.data = v THEN t2 := t1. ELSE t1. END IF. -PROCEDURE remove (VARIABLE head : INOUT pointer.link. Navabi and McGraw-Hill Inc. END LOOP. END ll_utilities. WHILE t1 /= NULL LOOP IF t1. PROCEDURE remove (VARIABLE head : INOUT pointer. TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER. END remove. t1 := t1. WHILE t1 /= NULL LOOP t2 := t1. BEGIN -. PROCEDURE lineup (VARIABLE head : INOUT pointer. t1 := t1. v : IN INTEGER).data := int(i). END clear. PROCEDURE clear (VARIABLE head : INOUT pointer). BEGIN -. t1 := head.link.link := t2. . -PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. -PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer. TYPE node IS RECORD data : INTEGER.link. DEALLOCATE (t2). link : pointer. t2 : pointer. int : integer_vector). TYPE pointer IS ACCESS node. t2 : pointer.Remove node following that with value v t1 := head. END LOOP. v : IN INTEGER) IS VARIABLE t1. END IF.Insert data in the linked list head := NEW node.

CANNOT DO qb <= qit_byte (qo). sq4(1). sq4(2). e. -. sq4(2).OTHER TYPES AND RELATED ISSUES SHARED VARIABLE dangerous : INTEGER := 0. ‘X’ can be interpreted as character ‘X’. qb <= qo. Z.. sq4(3)) <= (OTHER => ‘X’). -.. In the assignment: (sq4(0). requires a qualifier: (sq4(0).. sq4(3)) <= qit_nibble’ (OTHERS => ‘X’). TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit.Must do explicit type conversion • Share variables • Using qualifiers • Explicit type conversion between closely related types CHAPTER 7 56 © 1999. . . SIGNAL qo : qit_octal. Navabi and McGraw-Hill Inc.g. INTEGER and REAL TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit. SIGNAL qb : qit_byte. Now ‘X’s are qualified for size and element type Explicit type conversions for closely related types. sq4(1).

Z.OTHER TYPES AND RELATED ISSUES LIBRARY IEEE. USE IEEE. std_logic is an enumeration type with nine logic values ‘U’ is the default initial value std_logic_vector is an unconstraned array of std_logic All logical and shift operators are overloaded for std_logic and std_logic_vector Conversion functions for all subtypes and the BIT type to and from std_logic std_logic.ALL. its overloading and its subtypes is a good example of the above topics • Provides types for most applications • Overloading is done for all operators • Includes conversion functions where needed CHAPTER 7 57 © 1999. Navabi and McGraw-Hill Inc.std_logic_1164. .

‘0’. ‘U’. ‘U’. . ‘0’. ‘Z’ • std_logic subtypes • Enumeration elements are arranged for such subtypes • Our qit is like UX01 or X01Z. Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES TYPE X01 X01Z UX01 UX01Z ‘X’. different initial values CHAPTER 7 58 © 1999. Z. ‘Z’ ‘1’ ‘1’. ‘1’ ‘1’. ‘0’. ‘X’. ‘0’. ‘X’. ‘X’.

Z. Navabi and McGraw-Hill Inc. Type.PREDEFINED ATTRIBUTES Attribute ‘LEFT ‘RIGHT Description Left bound Right bound Example sq_4_8’LEFT(1) sq_4_8’RIGHT sq_4_8’RIGHT(2) sq_4_8’HIGH(2) sq_4_8’LOW(2) sq_4_8’RANGE(2) sq_4_8’RANGE(1) sq_4_8’REVERSE_RANGE(2) sq_4_8’REVERSE_RANGE(1) sq_4_8’LENGTH sq_4_8’ASCENDING(2) sq_4_8’ASCENDING(1) 3 0 7 7 0 Result ‘HIGH ‘LOW ‘RANGE Upper bound Lower bound Range 0 TO 7 3 DOWNTO 0 7 DOWNTO 0 0 TO 3 4 TRUE FALSE ‘REVERSE_RANGE Reverse range ‘LENGTH ‘ASCENDING Length TRUE If Ascending Predefined attributes are demonstrated here. Array. Signal. . and Entity • Predefined Array Attributes • Type of sq_4_8 is qit_4by8 CHAPTER 7 59 © 1999.

... .... Navabi and McGraw-Hill Inc. • Predefined type attributes • The type of qit and rit are enumeration types • More follows . . . Example rit’BASE rit’LEFT qit’LEFT rit’RIGHT qit’RIGHT INTEGER’HIGH rit’HIGH POSITIVE’LOW qit’LOW qit’POS(‘Z’) rit’POS(‘X’) qit’VAL(3) rit’VAL(3) rit’SUCC(‘Z’) Result qit ‘0’ ‘0’ ‘Z’ ‘X’ Large ‘Z’ 1 ‘0’ 2 3 ‘X’ ‘X’ ‘X’ ‘HIGH ‘LOW ‘POS(V) ‘VAL(P) ‘SUCC(V) ‘PRED(V) rit’PRED(‘1’) ‘0’ . CHAPTER 7 60 © 1999. after value V in base of type. . . Z. Value at Position P in base of type.PREDEFINED ATTRIBUTES Attribute ‘BASE ‘LEFT ‘RIGHT Description Base of type Left bound of type or subtype Right bound of type or subtype Upper bound of type or subtype Lower bound of type or subtype Position of value V in base of type. before value V in base of type.. Value.. Value..

‘0’ Error ‘Z’ ‘X’ TRUE TRUE “’Z’” “qZ” qZ Value.. . TRUE if range is ascending Converts value V of type to string. Example Result .. Navabi and McGraw-Hill Inc.... ‘LEFTOF(V) .. left of value V in base of type.. Z. rit’LEFTOF(‘1’) rit’LEFTOF(‘0’) rit’RIGHTOF(‘1’) rit’RIGHTOF(‘Z’) qit’ASCENDING qqit’ASCENDING qit’IMAGE(‘Z’) qqit’IMAGE(qZ) qqit’VALUE(“qZ”) ‘RIGHTOF(V) ‘ASCENDING ‘IMAGE (V) ‘VALUE(S) • Predefined type attributes • The type of qit and rit are enumeration types • Note type versus base of type CHAPTER 7 61 © 1999.. Value. right of value V in base of type. Description .PREDEFINED ATTRIBUTES Attribute . Converts string S to value of type.

CHAPTER 7 62 © 1999.. the value of s1’LAST_VALUE is 0. . if s1 changes.PREDEFINED ATTRIBUTES Attribute T/E Example Kind Type Attribute description for the specified example ‘DELAYED s1’DELAYED (5 NS) SIGNAL As s1 A copy of s1. If s1’EVENT is TRUE. delayed by delta. ‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1 The value of s1 before the most recent event occurred on this signal. Navabi and McGraw-Hill Inc. If no parameter or 0. . . but delayed by 5 NS.. ‘EVENT EV s1’EVENT VALUE BOOLEAN In a simulation cycle. ‘LAST_EVENT EV s1’LAST_VALUE VALUE TIME The amount of time since the last value change on s1. • Predefined signal attributes • Signal s is assumed to be of type BIT • More follows . Z. Equivalent to TRANSPORT delay of s1. ‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN A signal that is TRUE if s1 has not changed in the last 5 NS. . this attribute becomes TRUE. If no parameter or 0. the resulting signal is TRUE if s1 has not changed in the current simulation time.

s1’DRIVING is TRUE in the same process.. Z. for delta time. ‘DRIVING_VALUE s1’DRIVING_VALUE VALUE As s1 The driving value of s1 from within the process this attribute is being applied. If s1’ACTIVE is TRUE. ‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME The amount of time since the last transaction occurred on s1. Navabi and McGraw-Hill Inc. If no parameter or 0. s1’LAST_ACTIVE is 0. ‘DRIVING s1’DRIVING VALUE BOOLEAN If s1is being driven in a process. s1’ACTIVE will be TRUE for this simulation cycle. Initial value of this attribute is not defined. Kind Type ‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS.PREDEFINED ATTRIBUTES Attribute T/E Example . the current simulation cycle is assumed. . • Predefined signal attributes • Signal s is assumed to be of type BIT CHAPTER 7 63 © 1999.. ‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN If s1 has had a transaction in the current simulation cycle. ‘TRANSACTION TR s1’TRANACTION SIGNAL BIT A signal that toggles each time a transaction occurs on s1.

s1 • Blocks show Boolean results CHAPTER 7 64 © 1999. .PREDEFINED ATTRIBUTES 15 TIME (NS) 30 45 60 s1 s1'DELAYED (5NS) s1'STABLE s1'EVENT 10 s1'LAST_EVENT s1'LAST_VALUE s1'QUIET (5NS) 15 20 25 0 5 10 0 5 10 15 s1'ACTIVE 10 s1'LAST_ACTIVE 0 5 10 0 5 10 0 5 10 0 s1'TRANSACTION • Results of signal attributes when applied to the BIT type signal. Z. Navabi and McGraw-Hill Inc.

END brief_d_flip_flop. -ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT. • A simple falling edge Flip-Flop using signal attributes • Two events occur when c changes • Cannot delay the first statement CHAPTER 7 65 © 1999. q <= tmp AFTER 8 NS. c : IN BIT. . q : OUT BIT). BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp. Z. Navabi and McGraw-Hill Inc. END falling_edge.PREDEFINED ATTRIBUTES ENTITY brief_d_flip_flop IS PORT (d.

-ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT. BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp. q : OUT BIT). Z. q <= tmp AFTER 8 NS. END brief_t_flip_flop. • A simple toggle Flip-Flop using signal attributes • Combining several signal attributes • Can only apply if result of an attribute is signal CHAPTER 7 66 © 1999. END toggle.PREDEFINED ATTRIBUTES ENTITY brief_t_flip_flop IS PORT (t : IN BIT. Navabi and McGraw-Hill Inc. .

functions.PREDEFINED ATTRIBUTES Entity Attributes generate a string corresponding to the name of an entity class “entity_class” entities. constants. Z. ‘INSTANCE_NAME: Generates a name that contains entity. labels. Navabi and McGraw-Hill Inc. and instantiation labels leading to the design entity. literals. units. groups. architectures. types. variables. • Entity attributes • Generate a string for the name for an entity class CHAPTER 7 67 © 1999. architecture. procedures. signals. subtypes. packages. configurations. and files ‘SIMPLE_NAME: Generates simple name of a named entity ‘PATH_NAME : Generates a string containing entity names and labels from the top of hierarchy leading to the named entity. components. .

-ARCHITECTURE gate_level OF xoring IS SIGNAL a.').'). END ENTITY. BEGIN o1 <= i1 NAND i2 AFTER 3 NS. simple <= nand2'SIMPLE_NAME. path. . i2. u4 : ENTITY WORK. SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH) := (OTHERS => '. -ARCHITECTURE single_delay OF nand2 IS SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH) := (OTHERS => '. BEGIN u1 : ENTITY WORK. c : BIT. i2. END single_delay. u3 : ENTITY WORK. o1 : OUT BIT). i2 : IN BIT. b). and instance attributes CHAPTER 7 68 © 1999.nand2 PORT MAP (i1. b. i2 : IN BIT. c). c. Z.'). END ENTITY.nand2 PORT MAP (a. a. -ENTITY xoring IS PORT (i1. Navabi and McGraw-Hill Inc. u2 : ENTITY WORK.PREDEFINED ATTRIBUTES ENTITY nand2 IS PORT (i1. • Examples for entity attributes • Simple.nand2 PORT MAP (b. a). o1).nand2 PORT MAP (i1. SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH) := (OTHERS => '. END gate_level. o1 : OUT BIT). path <= nand2'PATH_NAME. instance <= nand2'INSTANCE_NAME.

and instance strings • Results from simulation of the above nand2 CHAPTER 7 69 © 1999. .PREDEFINED ATTRIBUTES Simple: Path: Instance: nand2 :xoring:u1: “xoring(gate_level):u1@nand2(single_delay): • Simple. Z. path. Navabi and McGraw-Hill Inc.

USER-DEFINED ATTRIBUTES

User-defined attributes may be applied to the elements of an entity class

Must declare first: ATTRIBUTE sub_dir : STRING;

Then attribute specification: ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS “/user/vhdl”;

brief_d_flip_flop’sub_dir evaluates to “/user/vhdl”.

User-defined attributes are demonstrated here.

• User defined attributes • No simulation semantics

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USER-DEFINED ATTRIBUTES

PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING; END utility_attributes; -USE WORK.utility_attributes.ALL; -- FROM PACKAGE USE: delay, sub_dir ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS); END brief_d_flip_flop; -ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall; END attributed_falling_edge;

• • • •

Associating attributes to entities and signals A package declares attributes An entity defines An architecture uses attributes

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PACKAGING BASIC UTILITIES

PACKAGE basic_utilities IS ... TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL; ... FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; FUNCTION to_integer (qin : qit_vector) RETURN INTEGER; FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector; ... FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector; ... END basic_utilities;

• Adding what was done to our basic utilities package • Will use this package for homeworks and in other chapters

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PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;

• Complete package declaration

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PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;

• Package body
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PACKAGING BASIC UTILITIES
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;®BB¯

• Package body

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PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits; END basic_utilities;

• The basic_utilities package as will be used in the examples in the chapters that follow

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Summary This chapter presented tools for high level descriptions. Declaration of types and the usage of objects of various types were covered in the first part of the chapter. In the context of describing type-related issues, we introduced the unconstrained array and file type. The basic I/O presented in this chapter showed a simple way to read or write from files. The overloading which is related to types was discussed next. Predefined attributes in VHDL can be looked upon as operators or predefined functions. In modeling, hardware behavior attributes are very useful, as we will see in the following, chapters. Finally in this chapter, we presented the Elements of this package are

basic_utilities package.

useful for hardware modeling and the creation of the package demonstrates the importance of packaging capability in VHDL.

• End Of Chapter 7

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CHAPTER 8 DATAFLOW DESCRIPTIONS IN VHDL

8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals 8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine 8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING 8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY

• • • • • • •

Constructs for dataflow descriptions Multiplexing and clocking, selection constructs; guarded assignments Multiple assignments; Resolutions: anding, oring, wiring Guarded signals State machines, simple sequence detector, multiple active states Open collectors using resolution functions A complete dataflow example

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION
select1

data1

out select2

data2

(a)

1D 2D y S1 S2

D1

Y D2

S1 S2

Will use VHDL for modeling various selection logic implementations

• Basic data selection hardware, logic diagram, symbols • Multiplexers are used for data selection

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION

Q

enable

data

1D C1

clk

• Flip flop clocking selects data • Various forms of data selection may be combined • Will show language constructs for such selections

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© 1999, Z. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION data1 data2 1D 2D Y 1D Q select1 select2 S1 S2 C1 enable clk • Multiplexing and clock enabling. . CHAPTER 8 4 © 1999.

MULTIPLEXING AND DATA SELECTION G0 G1 select lines G2 G3 G4 G5 G6 G7 MUX Z 0 1 2 data inputs 3 4 5 6 7 • An eight-to-one multiplexer. CHAPTER 8 5 © 1999. Navabi and McGraw-Hill Inc. Z. .

END dataflow. Z. -ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector’(s7.basic_utilities. i7 AFTER 3 NS WHEN "10000000" | "Z0000000". 'X' WHEN OTHERS. i3. i0 : IN qit. s4.MULTIPLEXING AND DATA SELECTION USE WORK. i1. i6 AFTER 3 NS WHEN "01000000" | "0Z000000". i2. s1. • • • • Description of a simple multiplexer Selected signal assignment is used Dataflow multiplexing Selected waveforms use choice or choices CHAPTER 8 6 © 1999. i0 AFTER 3 NS WHEN "00000001" | "0000000Z". s5. s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000". s4. s6. qit_vector ENTITY mux_8_to_1 IS PORT ( i7. i5 AFTER 3 NS WHEN "00100000" | "00Z00000".ALL.FROM PACKAGE USE: qit. s1. i6. z : OUT qit ). i3 AFTER 3 NS WHEN "00001000" | "0000Z000". Navabi and McGraw-Hill Inc. -. i1 AFTER 3 NS WHEN "00000010" | "000000Z0". i4. i5. s7. END mux_8_to_1. . s0 : IN qit. s3. s2. s3. s5. i4 AFTER 3 NS WHEN "00010000" | "000Z0000". s2. s6. i2 AFTER 3 NS WHEN "00000100" | "00000Z00".

. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • Syntax details of a selected signal assignment. Z. CHAPTER 8 7 © 1999.

MULTIPLEXING AND DATA SELECTION A0 A1 A2 DCD S0 S1 S2 S3 S4 S5 S6 S7 Another form of selection is a decoder. CHAPTER 8 8 © 1999. . Z. Navabi and McGraw-Hill Inc. which we will model in VHDL • Decoder description uses selected signal assignment • A three-to-eight decoder.

"00000100" AFTER 2 NS WHEN "0Z0" | "010". "00000010" AFTER 2 NS WHEN "00Z" | "001". "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110".ALL. "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111". "00010000" AFTER 2 NS WHEN "100" | "Z00". • VHDL description for the three-to-eight decoder. Z. -. -ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000".MULTIPLEXING AND DATA SELECTION USE WORK. . "00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" . Navabi and McGraw-Hill Inc. END dcd_3_to_8.FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0).basic_utilities. "XXXXXXXX" WHEN OTHERS. "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011". END dataflow. so : OUT qit_vector (7 DOWNTO 0)). • All possibilities must be considered CHAPTER 8 9 © 1999.

Navabi and McGraw-Hill Inc. . BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state. qb <= NOT internal_state AFTER delay2. -ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT. 1D Q Q C1 • A simple flip-flop uses internal_state • On clock edge d is transferred to internal_state • Events on internal_state cause assignments to q and qb CHAPTER 8 10 © 1999. delay2 : TIME := 5 NS). q <= internal_state AFTER delay1. qb : OUT BIT). PORT (d. q. END d_flipflop.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS. END assigning. c : IN BIT. Z.

qb <= GUARDED NOT d AFTER delay2. ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1. Navabi and McGraw-Hill Inc. END guarding. 1D Q Q C1 Several examples will demonstrate guarded blocks and assignments • • • • • The guarding architecture for the d_flipflop entity. Better representation of clocking disconnects d from q Disconnection is specified by GUARDED GUARDED assignments are guarded by guard expression Can also guard selected and conditional signal assignments CHAPTER 8 11 © 1999. . END BLOCK ff.MULTIPLEXING AND DATA SELECTION target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms. Z.

guard_expression concurrent statement block statement part block statement concurrent statement • Syntax details of a guarded block statement with guarded signal assignments • Label is mandatory • Use GUARDED for guard to apply CHAPTER 8 12 © 1999. qb <= GUARDED NOT d AFTER delay2. END BLOCK ff. Navabi and McGraw-Hill Inc. .MULTIPLEXING AND DATA SELECTION ff : BLOCK ( block_label Concurrent statement c = ‘1’ AND NOT c’STABLE ) BEGIN q <= GUARDED d AFTER delay1. Z.

cc. q1. q2. q.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc. q2. FOR c2 : flop USE ENTITY WORK. qb2 : BIT. c : IN BIT. qb2). • A test bench for testing assigning and guarding architectures of d_flipflop • Testbench tests and verifies both descriptions • A simple method for generation of periodic signals CHAPTER 8 13 © 1999. cc. FOR c1 : flop USE ENTITY WORK. qb1).d_flipflop (guarding). c1: flop PORT MAP (dd. Z. qb : OUT BIT). . dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd. END input_output. c2: flop PORT MAP (dd. qb1. cc. SIGNAL dd.d_flipflop (assigning). END COMPONENT. Navabi and McGraw-Hill Inc. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d. q1.

Navabi and McGraw-Hill Inc.... . ......... .. . . .... .. .. . . ........ .... ...... '1' .. ....... . .. '1' c1: state '0' '0' . ... '1' '1' .. ..... .ff : GUARD sees GUARD inside guarding Guard expression is only TRUE for 1 delta © 1999. '0' '0' ...... ... qb1 '0' . .. .... ... .. .... ...... .... ........... .. ... Z. .. .. .. .. • • • • • • Simulation results of the input_output architecture of the flipflop_test All transactions are observed In assigning:Two transactions on internal_state for every clock edge Transaction on q1 at time 0004........ .. . . .. FALSE FALSE .. . .. . .... .......... '0' . ......... .......... .. ..... ..... ........ '0' ... . ..... .. '0' ..... . ........ . .. ..... .... . .. ...... .. . ... .... '1' .... .. '0' '0' .. .. q2 '0' .. ... . ...... ...... '1' .... ...... '1' '1' ...... . . '0' .. . TRUE FALSE . .... . ... '0' . . ... . TRUE FALSE . '0' '0' . . . . '0' ....... ........... ..... .. is due to initialization In guarding:c2. '1' . .MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0004 0005 0400 +1δ δ +2δ δ 0404 0405 0800 +1δ δ +2δ δ 1000 +1δ δ 1200 +1δ δ +2δ δ 1204 1205 1600 +1δ δ +2δ δ 2000 +1δ δ +2δ δ 2004 2005 cc '0' . .. .. TRUE FALSE ............ '1' ... .. '1' .... .. .. '1' ... .. .. ... .. .... . c2:ff GUARD FALSE .. .. . .... . . '0' . '0' '0' .. ... CHAPTER 8 14 . ...... . .. dd '0' .. . .. .... FALSE FALSE ..... ... ... '1' qb2 '0' .. '0' . ... ............. . .. ........... .... ....... .... '0' .. . '1' '1' ........ .... . q1 '0' ... . ... .. ..... ...

. Z. c Scheduling on S (d. 6) (d) Value = s Value = d s • Events on edge detection expression • Demonstrating difference between ‘EVENT and NOT ‘STABLE CHAPTER 8 15 © 1999.MULTIPLEXING AND DATA SELECTION s <= d WHEN (c= ‘1’ AND NOT c’STABLE) ELSE UNAFFECTED. 0) (c) Value = s s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND c’EVENT) ELSE s. c Scheduling on S (d. 0) UNAFFECTED (a) Value = d s Value = s s <= d WHEN (c= ‘1’ AND c’EVENT) ELSE UNAFFECTED. Navabi and McGraw-Hill Inc. c Scheduling on S (d. c Scheduling on S (d. 0) (b) Value = d s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND NOT c’STABLE) ELSE s. 6) (s.

END guarding. . Navabi and McGraw-Hill Inc. qbar <= GUARDED NOT din AFTER delay2. q. delay2 : TIME := 5 NS).MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS. c : IN BIT. END BLOCK ff. qbar => qb). -ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT. PORT MAP (din => d. PORT (d. Z. qout => q. qbar : OUT BIT). BEGIN qout <= GUARDED din AFTER delay1. • • • • Using declarative part of a block statement PORT specifies signals on the outside PORT MAP maps outside signals with those inside Association format is used as expected CHAPTER 8 16 © 1999. qout. qb : OUT BIT). END ENTITY.

. ). . . qbar <= .. . END BLOCK ff. . . Z. ).. . . . Navabi and McGraw-Hill Inc. . BEGIN qout <= . . PORT MAP ( .MULTIPLEXING AND DATA SELECTION ff : BLOCK ( . block_statement port_clause port_map_aspect block_header block_statement_part • Syntax details for block statement with header • Uses this to draw a dashed line around a section of your hardware CHAPTER 8 17 © 1999. ) PORT ( .

. Navabi and McGraw-Hill Inc. 2D Q E2 C1 Q • A positive edge trigger flip-flop with enable input • Can nest block statements • Combining guard expressions must be done explicitly CHAPTER 8 18 © 1999. Z.MULTIPLEXING AND DATA SELECTION 1.

END guarding. END de_flipflop. Navabi and McGraw-Hill Inc. . PORT (d. qb <= GUARDED NOT d AFTER delay2. END BLOCK edge.MULTIPLEXING AND DATA SELECTION ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS. END BLOCK gate. Z. e. q. delay2 : TIME := 5 NS). • VHDL description for the positive edge trigger flip-flop with enable input • Implicit GUARD signals in each block • Useful if different second conditions were used CHAPTER 8 19 © 1999. -ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1. c : IN BIT. qb : OUT BIT).

PORT (d2. -ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1. qb <= GUARDED NOT d3 AFTER delay2.MULTIPLEXING AND DATA SELECTION ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS. Z. e2. d3. END guarding. END dee_flipflop. q. delay2 : TIME := 5 NS). e3. END BLOCK gate2. qb : OUT BIT). gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1. END BLOCK edge. c : IN BIT. Navabi and McGraw-Hill Inc. END BLOCK gate3. 3D Q E2 E3 C1 Q • A positive edge trigger. qb <= GUARDED NOT d2 AFTER delay2. double d flip-flop with independent enable inputs • Clock expression is specified only once CHAPTER 8 20 © 1999. 1. 2D 1. .

Navabi and McGraw-Hill Inc. dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd. SIGNAL dd. '0' AFTER 2200 NS. .MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. END input_output. ee <= '1'. FOR c1 : ff1 USE ENTITY WORK. qb1). c1: ff1 PORT MAP (dd. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc. qb1 : BIT. cc. • A test bench for testing the guarding architectures of de_flipflop • Testbench verifies operation of de_flipflop • After 2200 q1 is disconnected from d CHAPTER 8 21 © 1999. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d. c : IN BIT.de_flipflop (guarding). END COMPONENT. cc. qb : OUT BIT). ee. e. Z. ee. q. q1. q1.

....MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0400 0404 0405 0800 1000 1200 1204 1205 1600 2000 2004 2005 2200 2400 2800 3000 +1δ δ 3200 +1δ δ cc '0' . . .... .. .. ..... .... Z. . . ........ .. ..... . .... dd '0' ... '0' .. '0' . .... '0' '1' .. ...... ... '1' .. '1' . .. ......... .. '1' . '0' . ..... '0' '0' ee '0' '1' .. .... . ..... . . '0' ..... q1 '0' ....... . . '1' ....... '1' .. . '0' . .. . . . ... ... ... .. .. . ....... ... '1' .. '0' . . ... ... '1' '1' . .. ... .. .. ..... • Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • No transactions on the outputs after 2200 NS CHAPTER 8 22 © 1999.. .. ....... .. '0' '1' .... .... .. . qb1 '0' .. .... ........ . .. ..... ........... Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION RHS Activation GUARD 0 Driving Value Projected Output Waveform • Symbolizing guarded signal assignments • Disconnection in a guarded signal assignment • Driving value continues to be updated even if the guard expression is false CHAPTER 8 23 © 1999. . Navabi and McGraw-Hill Inc. Z.

MULTIPLEXING AND DATA SELECTION What follows concentrates on definition & applications of resolution functions • Normally several sources cannot drive a signal • Real circuits smoke. Z. . Navabi and McGraw-Hill Inc. • So does VHDL CHAPTER 8 24 © 1999.

-. circuit_node <= d.ALL. END y_circuit. z <= circuit_node. BEGIN circuit_node <= a.basic_utilities.MULTIPLEXING AND DATA SELECTION USE WORK. z : OUT qit). circuit_node <= b. Z.FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a. • Multiple sources for a simple signal • This results in an error message CHAPTER 8 25 © 1999. d : IN qit. -ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit. b. c. circuit_node <= c. Navabi and McGraw-Hill Inc. . END smoke_generator.

Navabi and McGraw-Hill Inc. Z. . a happy VHDL simulator • Multiple drivers is possible only if a resolution exists • Example in hardware is "open collector" • Pull_up provides resolution CHAPTER 8 26 © 1999.MULTIPLEXING AND DATA SELECTION A happy circuit.

END anding. Z. RETURN accumulate. Navabi and McGraw-Hill Inc. a b anding c d circuit_node • • • • The anding resolution function. qit_vector. ANDs all its drivers Performs the AND function two operand at a time Collect all ANDs and return A notation that we will use CHAPTER 8 27 © 1999. “AND” from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'. .MULTIPLEXING AND DATA SELECTION -.USE qit. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). END LOOP.

BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). CHAPTER 8 . Z. circuit_node <= c. SIGNAL circuit_node : anding qit.ALL. Navabi and McGraw-Hill Inc. END wired_and. BEGIN circuit_node <= a. • • • • • • Multiple sources for a simple signal The difference is in the declaration of the left-hand-side This results in ANDing all sources Specify anding for the resolution on circuit_node Type of circuit_node is a subtype of qit ANDing simultaneously receives all drivers 28 © 1999. END anding. RETURN accumulate. -. z <= circuit_node.MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'. circuit_node <= d. END LOOP. circuit_node <= b.

.MULTIPLEXING AND DATA SELECTION t4 v4 t4 v4 t4 v4 t3 v3 t3 v3 t3 t3 t2 v2 t2 v2 t2 t2 t1 v1 t1 v1 t1 t1 0 0 lhs_signal 0 • • • • Projected output waveforms and resolution functions Every assignment in a concurrent body creates a driver All assignments is a sequential body create only one driver Resolution functions act on expired values CHAPTER 8 29 © 1999. Navabi and McGraw-Hill Inc. Z.

MULTIPLEXING AND DATA SELECTION RHS Activation GUARD t4 v4 Driver 1 t3 v3 t2 v2 t1 v1 0 RHS Activation lhs_signal GUARD t4 v4 Driver 2 t3 v3 t2 v2 t1 v1 0 • Guarded signal assignments into resolved signals • Drivers continue to perform normal in spite of disconnection • Resolution function cannot tell the difference. Navabi and McGraw-Hill Inc. it only sees the driving value CHAPTER 8 30 © 1999. Z. .

t <= i1 AND s1. z <= t. t <= i2 AND s2. t <= i3 AND s3.MULTIPLEXING AND DATA SELECTION USE WORK. BEGIN t <= i7 AND s7. Navabi and McGraw-Hill Inc. SIGNAL t : oring qit. t <= i5 AND s5. t <= i6 AND s6. -. END LOOP.FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. t <= i0 AND s0. • Implementing the eight-to-one multiplexer using eight concurrent assignments • ORing resolution function is used CHAPTER 8 31 © 1999. END multiple_assignments.basic_utilities. END oring. Z.ALL. . RETURN accumulate. t <= i4 AND s4. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i).

Z.'X')).'X').'X'. ('0'. b).MULTIPLEXING AND DATA SELECTION FUNCTION wire (a.'X'.'X').'1'.'1'. .'0'. END wire.'X'. In1: In2: 0 1 Z X 0 0 X 0 X 1 X 1 1 X Out Z 0 1 Z X X X In1 X Out X In2 X • The wire function for modeling wiring two qit type nodes.'Z'.'1'. ('X'. b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'. Navabi and McGraw-Hill Inc. • Input-output mapping • Circuit notation CHAPTER 8 32 © 1999. ('X'.'X'). BEGIN RETURN qit_wire_table (a.

drivers(i)). • The wiring resolution function for qit type operands • Necessary declarations for visibility of the wiring resolution function and its related types and subtypes • If no drivers exist. Navabi and McGraw-Hill Inc. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit.MULTIPLEXING AND DATA SELECTION FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. END LOOP. Z. END wiring. . FUNCTION wiring ( drivers : qit_vector) RETURN qit. RETURN accumulate. SUBTYPE wired_qit IS wiring qit. ‘Z’ will be returned • To declare an array of this resolution CHAPTER 8 33 © 1999.

BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 ). END LOOP. • • • • • • Another complete example The oring resolution function for the BIT type operands OR for BIT is already defined If no drivers. SUBTYPE ored_bit IS oring BIT. '0' is returned Necessary type and subtype definitions for the basic_utilities package Example signal declaration © 1999. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit.MULTIPLEXING AND DATA SELECTION FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. Navabi and McGraw-Hill Inc. END oring. CHAPTER 8 34 . RETURN accumulate. Z.

.MULTIPLEXING AND DATA SELECTION • Will now model this circuit • An NMOS eight-to-one multiplexer • The CMOS version uses transmission gates instead of pass transistors CHAPTER 8 35 © 1999. Navabi and McGraw-Hill Inc. Z.

END BLOCK. Z. . A block statement modeling a transmission gate • Disconnection is realized by block statements • If all drivers are disconnected actual hardware returns to 'Z' CHAPTER 8 36 © 1999.MULTIPLEXING AND DATA SELECTION si ii t bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii. Navabi and McGraw-Hill Inc.

b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. t <= GUARDED i3.FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS SIGNAL t : wired_qit BUS. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. t <= GUARDED i0. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. t <= GUARDED i4. • • • • • Each ii connects to t if si is '1'. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION USE WORK. -. END multiple_guarded_assignments. . b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. ii is disconnected from t if si is '0' Use BUS to implement this behavior Default in wire function is specified as 'Z' This default is used if wiring is called with Null Last disconnection causes call to wiring with Null CHAPTER 8 37 © 1999. t <= GUARDED i2. Z. t <= GUARDED i6. t <= GUARDED i7. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. z <= t. t <= GUARDED i5. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK.ALL.basic_utilities. t <= GUARDED i1. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK.

Navabi and McGraw-Hill Inc. Z. .MULTIPLEXING AND DATA SELECTION • An NMOS half-register with multiplexed input • Modeling this circuit must take inverter input capacitance into account • t holds charge if all are disconnected • Circuit shows a register effect CHAPTER 8 38 © 1999.

b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK.ALL. Navabi and McGraw-Hill Inc. i4. END multiplexed_half_register. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. s4. t <= GUARDED i2. i6. i0 : IN qit. t <= GUARDED i4. • • • • • • Use REGISTER to model retaining of last value No call is made to wiring upon last disconnection BUS and REGISTER are kind specification Signals with kind are guarded signals Guarded signals must be used on LHS of guarded assignments Ok to use unguarded signals on LHS of guarded assignments 39 © 1999. t <= GUARDED i6. s2. i5. i1. wired_qit ENTITY multiplexed_half_register IS PORT (i7. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK.basic_utilities.FROM PACKAGE USE: qit. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. i2. t <= GUARDED i1. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. Z. END guarded_assignments. s5. s3. z : OUT qit ). z <= NOT t AFTER 8 NS. t <= GUARDED i0.MULTIPLEXING AND DATA SELECTION USE WORK. -ARCHITECTURE guarded_assignments OF multiplexed_half_register IS SIGNAL t : wired_qit REGISTER. s7. s6. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. s1. t <= GUARDED i7. -. i3. t <= GUARDED i3. CHAPTER 8 . t <= GUARDED i5. s0 : IN qit.

END. END. Z. . --------------------------------------------------------------------------------------------- BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values. RHS Activation guard_expression t4 v4 Driver i t3 v3 t2 v2 t1 v1 0 guarded_lhs_signal • Turning off drivers from guarded signals • Guard expression controls driver contribution to the resolution function • Continuous contribution stops.MULTIPLEXING AND DATA SELECTION BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values. Navabi and McGraw-Hill Inc. even if a static value remains (if unguarded LHS) CHAPTER 8 40 © 1999.

unguarded • • • • Disconnection disconnects if guarded BUS kind. last disconnection calls resolution function with Null REGISTER. last disconnection is no different than others CHAPTER 8 41 © 1999. disconnection disconnects. last disconnection does not call the resolution function Unguarded.MULTIPLEXING AND DATA SELECTION Before Last Disconnection After Last Disconnection v v f(v) v null v f(null) (a) BUS Kind v v f(v) v null f(v) (b) REGISTER Kind v v f(v) v v f(v) (c) Not Guarded Last disconnections: BUS kind. . Z. REGISTER kind. Navabi and McGraw-Hill Inc. but holds static value at the time of disconnection • For unguarded.

Navabi and McGraw-Hill Inc.basic_utilities. .FROM PACKAGE USE: qit. not REGISTER CHAPTER 8 42 © 1999.ALL. qit_vector. END GENERATE. END BLOCK. s : IN qit_vector. Z. wired_qit ENTITY mux_n_to_1 IS PORT (i. END mux_n_to_1.MULTIPLEXING AND DATA SELECTION USE WORK. END multiple_guarded_assignments. -. -ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j). • • • • mutliple_guarded_assignments architecture of the mux_n_to_1 A general n-bit multiplexer Ports can be resolved signals BUS kind can also be specified. z : OUT wired_qit BUS).

mux_n_to_1 (multiple_guarded_assignments). "0011" AFTER 30 US. Z. -ARCHITECTURE input_output OF mux_tester IS COMPONENT mux PORT (i. . "Z100" AFTER 20 US. END input_output. mm : mux PORT MAP (ii. SIGNAL ii. END COMPONENT. • A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1 • This entity is used as a four bit multiplexer CHAPTER 8 43 © 1999. ENTITY mux_tester IS END mux_tester. z : OUT wired_qit BUS). zz). "1100" AFTER 15 US.basic_utilities. s : IN qit_vector. SIGNAL zz : qit. Navabi and McGraw-Hill Inc.ALL. ss. FOR ALL : mux USE ENTITY WORK. ss <= "0010" AFTER 05 US.MULTIPLEXING AND DATA SELECTION USE WORK. BEGIN ii <= "1010" AFTER 10 US. "000Z" AFTER 25 US. ss : qit_vector (3 DOWNTO 0) := "0000".

.. "Z100" ... .............. ... . ...MULTIPLEXING AND DATA SELECTION TIME (ns) 00000 +1δ δ 05000 +1δ δ 10000 +1δ δ 15000 +1δ δ 20000 +1δ δ 25000 +1δ δ 30000 +1δ δ ii(3:0) "0000" .. ....... "1010" ... '1' • Simulation results of the input_output architecture of the mux_tester • Simulation produces 'X' for two conflicting enabled inputs • Produces 'Z' when no inputs are enabled CHAPTER 8 44 © 1999..... zz '0' 'Z' . "1100" . ........ ...... ... "0011" ......... '0' . "000Z" .... "0010" . ........... '0' . '1' ... Z........ ss(3:0) "0000" .... ..... .... ........ . '1' . 'X' ............ Navabi and McGraw-Hill Inc.......

MULTIPLEXING AND DATA SELECTION Remaining issues: Disconnection Right and left INOUT More issues on resolutions. then will start using resolved. and other signal types • Several examples will follow CHAPTER 8 45 © 1999. guarded signals & resolved signals will de discussed • Will discuss other issues. Z. guarded. Navabi and McGraw-Hill Inc. .

. END ARCHITECTURE.MULTIPLEXING AND DATA SELECTION si ii ARCHITECTURE . END ARCHITECTURE. Z. .. . it takes n NS for t to get ii ARCHITECTURE . Navabi and McGraw-Hill Inc. SIGNAL t : wired_qit. . t <= GUARDED ii AFTER n NS... DISCONNECT t : wired_qit AFTER 6 NS. . SIGNAL t : wired_qit.... t Connection is timed: After connection. . t <= GUARDED ii AFTER n NS. Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE • Specify disconnection in the declaration • Use ALL for all signals of that type • Use OTHERS if some specified otherwise CHAPTER 8 46 © 1999. . . BEGIN . BEGIN ..

Navabi and McGraw-Hill Inc. • Resolved signals on right and left hand sides • What you get is not what you put in • Others contribute to a resolved signal CHAPTER 8 47 © 1999. .MULTIPLEXING AND DATA SELECTION Value used on the right hand side Value placed on driver of a t4 v4 t3 v3 t2 v2 t1 v1 0 Other Drivers a <= a AND b AFTER delay. Z.

x : INOUT BIT) … ENTITY two (b : IN BIT.MULTIPLEXING AND DATA SELECTION ENTITY one (a : IN BIT. .one PORT MAP (a. . ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT. y : INOUT BIT) … -ENTITY three IS END three. END connecting. . . z). z). Navabi and McGraw-Hill Inc. x a z oring y b • Connecting INOUT ports require resolved signals • There are two drivers for each interconnection CHAPTER 8 48 © 1999. BEGIN c1 : ENTITY WORK. c2 : ENTITY WORK. .two PORT MAP (b. Z. .

STATE MACHINE DESCRIPTION Will use resolutions and guarded assignments in several examples • • • • State names indicate detected sequences Use resolutions & guarded blocks A simple 1011 Mealy detector A block statement for each state CHAPTER 8 49 © 1999. Navabi and McGraw-Hill Inc. Z. .

. Navabi and McGraw-Hill Inc. s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset. s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1. END BLOCK clocking. got10. s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10. clk : IN BIT.STATE MACHINE DESCRIPTION ENTITY detector IS PORT (x. use one_of CHAPTER 8 50 © 1999. ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. END detector. FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT). got1. END BLOCK s3. END BLOCK s1. END singular_state_machine. END BLOCK s2. z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'. END BLOCK s4. SIGNAL current : one_of state REGISTER := reset. z : OUT BIT). END one_of. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset. Z. • • • • VHDL description of 1011 detector Only one simultaneous active state Current receives four concurrent assignments Current must be resolved. got101).

basic_utilities. Navabi and McGraw-Hill Inc. goes to 4 when x = '1' CHAPTER 8 51 © 1999. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'.ALL. END BLOCK clocking.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". END BLOCK s4. s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'. END BLOCK s3. END multiple_state_machine. s <= GUARDED "0000". s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. -. END BLOCK s1.STATE MACHINE DESCRIPTION USE WORK. END BLOCK s2. . Z. • • • • • VHDL description of 1011 detector More than one state can simultaneously be active The last description does not allows multiple active states To remedy: use a signal for each state State 3 : goes to 1 when x = '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'.

END BLOCK s2.ALL. . END BLOCK clocking. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s <= GUARDED "0000". Navabi and McGraw-Hill Inc. END BLOCK s3.. Z.. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'.basic_utilities.. s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". -.. . • State 3 : goes to 1 when x = '0'.STATE MACHINE DESCRIPTION USE WORK. END multiple_state_machine. Causes removal of retained value upon last disconnection CHAPTER 8 52 © 1999. goes to 4 when x = '1' • S must be resolved vector REGISTER kind • S <= GUARDED "0000". BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN .

END multiple_moore_machine_1. END detector_m.STATE MACHINE DESCRIPTION ENTITY detector_m IS PORT (x. RETURN accumulate. . BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i).clk : IN BIT. END LOOP. BIT) OF BIT. -ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. SUBTYPE ored_bit IS oring BIT. and s arrays SIGNAL o : ored_bit REGISTER. out_val. END BLOCK clocking. TYPE out_table IS ARRAY (1 TO n.Fill in next_val. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. x). GENERIC (n : INTEGER).'1')) <= GUARDED '1' WHEN x='1' ELSE '0'. s(next_val(i. -. BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i. BIT) OF INTEGER. z <= o. END BLOCK si. Z. TYPE next_table IS ARRAY (1 TO n. Navabi and McGraw-Hill Inc. z : OUT BIT). s (i) <= GUARDED '0'.'0')) <= GUARDED '1' WHEN x='0' ELSE '0'. END oring. o <= GUARDED out_val(i. • • • • A generic state machine A Moore sequence detector Specify transitions & outputting in constant tables Allows multiple machines in one CHAPTER 8 53 © 1999. END GENERATE.

--S1: == z=0. x=1 -CONSTANT next_val : next_table := ( (1 . --S3: -> S1. --S2: == z=0. 2). '0'). 4). Navabi and McGraw-Hill Inc. '0'). 6) ). . Z. 3). --S5: -> S5. 1).STATE MACHINE DESCRIPTION ------------------------------------------------------------------Tables for programming the configurable Moore description -------------------------------------------------------------------. --S4: == z=1. '1') ). --S1: -> S1. x=1 -CONSTANT out_val : out_table := ( ('0' .--S6: -> S5. 0 -('1' . S3 -(1 .Next States: ----x=0. 1 ----. 0 -('1' .Initial Active States: -SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010". --S5: == z=0. S4 -(1 .--S6: == z=1. --S4: -> S1. S1 -(5 . '0'). '1'). 0 -('0' . ---------------------------------------------------------------------------------------------------------------------------------- • • • • Next state and output tables The next_val constant holds next state values The out_val constant holds the output values on the z output Initial starting states are set to '1' in the s vector CHAPTER 8 54 © 1999. S6 -(5 . 1 -('0' . S2 -(1 . 6). --S2: -> S1. '0').Output Values: ----x=0. 0 -('0' . --S3: == z=0. S6 -----.

OPEN COLLECTOR GATES

VCC

a y b

GND

• • • •

Open collector NAND gate A two-input NAND gate, TTL 74LS03 SSI package Resolution functions are used in bussing Will use open collector to illustrate

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;

• VHDL description of a NAND gate with open collector output • Use qit type • Output is ‘Z’ and not ‘1’

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OPEN COLLECTOR GATES
ENTITY test_nand2 IS END test_nand2; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; TIME BEGIN (ns) aa bb assign_bits (aa, "qit_data", 500 NS); 0000 '0' '0' assign_bits (bb, "qit_data", 750 NS); 0010 ... ... c1: nand2 PORT MAP (aa, bb, yy); 1000 '1' ... 1500 ... '1' END input_output;
1512 2500 2510 3000 3012 3750 3760 4000 4500 4512 5000 5010 5500 5512 6000 6010 6750 6762 7500 7510 8250 8262 ... '0' ... 'Z' ... ... ... '0' '1' ... '0' ... 'Z' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... 'Z' ... ... ... ... ... '0' ... '1' ... '0' ... 'Z' ...

yy '0' 'Z' ... ... '0’ ... 'Z' ... '0' ... 'Z' ... ... '0' ... 'Z' ... '0' ... 'Z' ... '0' ... 'Z' ... '0'

• Testing the open-collector NAND gate • Test bench uses external data file • Output is either ‘0’ or ‘Z’, never ‘1’

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;

• VHDL description of TTL 74LS03 • Contains four open collector NAND gates • Will use in a design

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OPEN COLLECTOR GATES

a1 b1

a4 aa pull_up_1 y1 g4 a2 bb b2 pull_up_3 y4 yy g2 pull_up_2 y2 g3 a3 b3 g1 b4

y3

yy = (aa' . bb)’ . (bb' . aa)' = ( aa ⊕ bb )'

• • • •

Implementing XNOR logic using open collector NAND gates Using 74LS03 for implementing an XNOR pull_up3 has two drivers pull_up1 and pull_up2 must be turned to ‘0’, ‘1’ logic

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US, '0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;

• Wiring and testing XNOR function implemented by four open collector AND gates • pull_up_1 and pull_up_2 turn 0,Z to 0,1 • anded_qit resolution function implements wired logic

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OPEN COLLECTOR GATES
TIME (us) 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 aa '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' 'Z' 'Z' 'Z' 'Z' 'Z' 'Z' bb '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' 'Z' pull_up_1 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' pull_up_2 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' pull_up_3 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0'

• Results are observed at 2 us intervals • Simulation shows XNOR implementation • Pull up resolutions turn gate output 'Z' values to '1'

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THREE STATE BUSSING

u1 :

alu

u2 :

reg1

u3 : bus1 8

8 8

bus a

u4 :

unit1

u5 :

unit2

• • • •

A bussing system (bus_sys) Will use resolution functions for describing it A very common hardware for RT level descriptions Some components have three-state outputs some do not

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THREE STATE BUSSING

ENTITY alu IS PORT (… ; zout : out qit_vector (7 DOWNTO 0)); END alu; -ENTITY reg1 IS PORT (… ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); …); END unit1; -ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); …); END unit2;

• Interface of bus sources and destinations • Wired_qit_vector is used for those with three-state outputs • Connection of others must be through three-state constructs

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THREE STATE BUSSING

ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (…; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (…; busa); … u3 : busa <= bus1; … unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;…); … u5 : ENTITY WORK.unit2 PORT MAP (busa;…); … END partial;

• • • •

Partial VHDL description for bussing system example reg1 with three-state output directly drives the bus aluout goes through three-state constructs All required hardware structures are explicitly coded

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Std_logic BUSSING

std_ulogic for “standard unresolved logic” A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms

• Std_logic provides multi-value logic for most applications • No need for new user types • Most designers use the resolved type

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4-bit Count output Reset input • Seen dataflow primitives • Use dataflow for system description • A sequential comparator example CHAPTER 8 66 © 1999. Z.A GENERAL DATAFLOW CIRCUIT 8-bit Parallel data Count equal sequential data on parallel input lines. . Navabi and McGraw-Hill Inc.

• • • • Dataflow description of the sequential comparator circuit inc function is unconstrained Save old data in buff Compares old and new CHAPTER 8 67 © 1999. i := i + 1. Navabi and McGraw-Hill Inc. SIGNAL count : BIT_VECTOR (3 DOWNTO 0). END IF.ALL. SIGNAL buff : BIT_VECTOR (7 DOWNTO 0). int2bin (i. VARIABLE t : BIT_VECTOR (x'RANGE). count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count. matches <= count. reset : IN BIT. Z. -ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0).FROM PACKAGE USE: bin2int. END sequential_comparator. matches : OUT BIT_VECTOR (3 DOWNTO 0)). BEGIN bin2int (x. -.basic_utilities. i). RETURN t.A GENERAL DATAFLOW CIRCUIT USE WORK. clk. BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data. . END BLOCK. END inc. t). END dataflow. IF i >= 2**x'LENGTH THEN i := 0.

... ..... ....... . . . ............... . ...... ......... "11110101" ....... ... ..... ... ........................................................... ..... "0010" .. . "10010110" ..... . ................ ... ............ ..... "10010110" .................... . .... '0' ........ .............. "0000" . .... ......... "0100" ............ .... .. .......................... ....... .... . ........ "0001" ..... ... . ... .............. . "10010110" .. '1' '0' ...... ......... clk '0' ... ................. .. . ... "01010100" .... ........... ... ..... ....... ... matches "0000" "0000" ... ..... .. . '1' data(7:0) "00000000" .. .. . .. .. ..... ........... ....... .......................... . ........ "00010001" ... ........... ......... "0000" ........ ...... '1' '0' ........ .......... ...... ........ '1' '0' .... buff(7:0) "00000000" . .. ............ ........... Navabi and McGraw-Hill Inc.......... "0010" . ..... "0001" . ....... ................. ...... . ..... ..... '1' '0' ....... . ... "11111110" .... .A GENERAL DATAFLOW CIRCUIT TIME (ns) 0000 +1δ δ 0200 0500 1000 +1δ δ 1200 1500 1700 2000 +1δ δ 2500 3000 +1δ δ +2δ δ 3200 3500 3700 4000 +1δ δ 4200 4500 5000 +1δ δ 5500 6000 +1δ δ +2δ δ 6500 7000 +1δ δ +2δ δ 7500 8000 +1δ δ +2δ δ 8500 reset '0' ......... ...... '0' ............... ......................................... .... ....... "11111110" ..... "11111110" .. '1' ... • matches shows count of matching data CHAPTER 8 68 © 1999........ ... ................................. . "01010110" . ............ ................ "11110101" . ....... .... .. .......... ... . count(3:0) "0000" .. .... ....... ..... .... ...... "0011" ... . ....... ................ .... '1' '0' . .......... ....... "10010110" .. ....... '1' '0' . ......... "0001" ......... ..... "0100" .. ... . ..... . ........ ....... Z.................... "10010110" ... . ... . . "00010001" . ........ ............. .............. .... .... . ......... '1' .. "0001" . . "0011" ............... . ..... ....... ..

TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. SUBTYPE anded_qit IS anding qit. Navabi and McGraw-Hill Inc. END basic_utilities. SUBTYPE anded_bit IS anding bit. . SUBTYPE ored_bit IS oring BIT. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. -FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. -FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR. b : qit) RETURN qit. . -FUNCTION anding ( drivers : qit_vector) RETURN qit. FUNCTION wire (a. TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit. SUBTYPE wired_qit IS wiring qit. TYPE anded_qit_vector IS ARRAY (NATURAL RANGE <>) OF anded_qit. -FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT. Z. CHAPTER 8 69 © 1999. SUBTYPE ored_qit IS oring qit. TYPE anded_bit_vector IS ARRAY (NATURAL RANGE <>) OF anded_bit. -FUNCTION wiring ( drivers : qit_vector) RETURN qit. -FUNCTION oring ( drivers : qit_vector) RETURN qit.UPDATING BASIC UTILITIES PACKAGE basic_utilities IS .

.'X'.'X'). drivers(i)). END wiring.'X'). ('X'. CHAPTER 8 70 © 1999. FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. END LOOP. FUNCTION wire (a. . END oring. END anding. BEGIN RETURN qit_wire_table (a.'X'. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate.'0'. FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'. b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.'X')).UPDATING BASIC UTILITIES PACKAGE BODY basic_utilities IS . Z. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). RETURN accumulate. FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'.'Z'.'1'. RETURN accumulate. END LOOP. END LOOP. . ('X'. RETURN accumulate.'1'. b). ('0'. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i).'X').'X'. END wire. Navabi and McGraw-Hill Inc.'1'.

RETURN accumulate. IF i >= 2**x'LENGTH THEN i := 0. END inc. .UPDATING BASIC UTILITIES FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. RETURN t. END LOOP. t). i := i + 1. END oring. int2bin (i. END IF. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). i). END anding. Navabi and McGraw-Hill Inc. Z. FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. RETURN accumulate. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). • Resolution functions and inc function added to basic_utilities CHAPTER 8 71 © 1999. VARIABLE t : BIT_VECTOR (x'RANGE). END LOOP. END basic_utilities. FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'. BEGIN bin2int (x.

Guarded signal assignment and the concept of disconnection. and resolution functions. multiple drivers of signals. This prepared the way for describing resolution functions. A resolution function for a node can be written to match its technology-dependent behavior. which are considered to be among the most important hardware related constructs in the VHDL language. . and guarded signals. Z. guarded assignments. in general a resolved signal is a better representation of a circuit node.SUMMARY This chapter presented signal assignment. • End Of Chapter 8 CHAPTER 8 72 © 1999. Navabi and McGraw-Hill Inc. The resolution functions developed in this chapter are typical of the way buses function in a digital system. were presented. Although VHDL only requires resolution of signals with multiple concurrent sources. or turning off a source.

4.4 FORMATTED ASCII I/O OPERATIONS 9.5.1 Basic Screen Output 9.5 Syntax Details of Process Statements 9.5 MSI BASED DESIGN 9.1.4.2 Concurrent Assertion Statements 9.3 Simulation Report 9.3.3. Z.CHAPTER 9 BEHAVIORAL DESCRIPTION OF HARDWARE 9.1.1 A Behavioral State Machine 9.1 PROCESS STATEMENT 9.2 Two Phase Clocking 9.5.1.1.6 SUMMARY • • • • • • Constructs for sequential descriptions Process statement is a key construct Assertion for behavioral checks Handshaking constructs Timing control Formatted I/O CHAPTER 9 1 © 1999.4. Navabi and McGraw-Hill Inc.4 Interface Handshaking 9.5.1 Declarative Part of a Process 9.2.7 Passive Processes 9.6 Postponed Processes 9.3 Design Implementation 9.2 ASSERTION STATEMENT 9.3 Sensitivity List 9.3.2.3 SEQUENTIAL WAIT STATEMENTS 9.3 Implementing Handshaking 9.1.8 Behavioral Flow Control Constructs 9.2 Description of Components 9.1 Top Level Partitioning 9.2 Statement Part of a Process 9. .4 A First Process Example 9.3.2 A Display Procedure 9.1.1.1 Sequential Use of Assertion Statements 9.1.

PROCESS STATEMENT
Concurrent process statement PROCESS Always alive process declarative_part (non-signal) ...

BEGIN

Always active process statement_part (sequential) ...

END PROCESS;

Process statements describe hardware without much hardware details

• • • •

PROCESS: A concurrent statement, enclosing sequential statements Declarative part contains only variables and constants Use only sequential constructs

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PROCESS BEGIN Reapets forever,
S e q u e n t i a l

In zero time,

Unless suspended

END PROCESS;

• Unless a sequential body is suspended • It executes in zero real and delta time • It repeats itself forever

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ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;

• • • • •

First: a is scheduled for x Next: b is scheduled for y x and y receive values at the same time Both assignments occur a delta later Zero time between both scheduling

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ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;

• First: a is scheduled for x • Next: b is scheduled for y • y receives b sooner than x receiving a

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ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;

• • • • •

Assume x_sig is initially '0' Assignment of '1' to x_sig takes a delta Action_2 will be taken Variable x_var had to be declared inside the Process statement If x_var was used instead of x_sig, action_1 would be taken

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ARCHITECTURE … BEGIN … a <= b; … c <= d; … END …;

ARCHITECTURE … BEGIN … PROCESS (b) … a <= b; END PROCESS; … c <= d; … END …;

Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation Any signal assignment can be expressed by a process statement

• • • • • •

Can use a signal assignment in a sequential body On the left: events on b cause assignment Process is executed when an event occurs on b On the right: (b) is sensitivity list of process Process statement executes only once for every event on b Process suspends till next event on b occurs
© 1999, Z. Navabi and McGraw-Hill Inc.

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R 1D Q

C1 S

Q

A flip-flop will demonstrate assignments and flow in process statements

• Have modeled flip-flops with concurrent statements • A process statement is a powerful construct for such descriptions

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• • • •

Three concurrent processes dff process is sensitive to (rst, set, clk) Internal state receives proper value Events on state cause events on q and qb

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ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;

• Single process assigns values to q and qb • This description eliminates the δ delay of the last description • Less precise timing

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TIME (NS) 0 +1δ δ 6 200 206 +1δ δ 500 1000 1200 1400 1406 +1δ δ 1500 2000 2200 2400 2500 2506 +1δ δ 3000 3300 3500 3506 +1δ δ 4000

ss '0' ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

rr '0' ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ...

cc '0' ... ... ... ... ... '1' '0' ... ... ... ... '1' '0' ... ... '1' ... ... '0' ... '1' ... ... '0'

dd '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ...

q1 '0' ... ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ...

q2 '0' ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ... ...

qb1 '0' '1' ... ... ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ...

qb2 '0' ... '1' ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ... ...

• Simulation run compares flip-flop descriptions • The 3 process description has a δ delay • However, potential of more precise timing

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;

• This example uses a record for delay and flip-flop values • Logic value and delay are assigned to variables • Assignment to variables are done in zero time without the δ delay

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qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3. Z.PROCESS STATEMENT dff: PROCESS (rst. sensitivity_list variable declaration process declarative part process statement ELSEIF rst = ‘1’ THEN state := ‘0’. Navabi and McGraw-Hill Inc. . q <= state AFTER (sq_delay + rq_delay + cq_delay)/3. END IF. END PROCESS dff. ELSEIF clk = -‘1’ AND clk’EVENT THEN state := d. clk) VARIABLE state : BIT := ‘0’ BEGIN IF set = ‘1’ THEN state := ‘1’. set. sequential statement process statement part sequential statement sequential statement • Syntax details include sensitivity list CHAPTER 9 13 © 1999.

Z. clk) BEGIN . becomes active becomes active clk set rst t1+1δ δ δ t1+2δ t1+3δ δ • Postponed process • Wait until the last event in a real time increment • Signal assignments can become postponed CHAPTER 9 14 © 1999. set. set. . Navabi and McGraw-Hill Inc. . . END. dff : POSTPONED PROCESS(rst.PROCESS STATEMENT dff : PROCESS(rst. . . END. clk) BEGIN .

sq_delay). q. END IF. ELSIF clk = '1' AND clk'EVENT THEN sd := (d. rq_delay). set. END PROCESS dff_arch. END behavioral. -USE WORK.state AFTER sd.ALL. cq_delay : TIME := 6 NS). ENTITY d_sr_flipflop IS GENERIC (sq_delay. qb <= NOT sd.PROCESS STATEMENT PACKAGE bt IS TYPE bit_time IS RECORD state : BIT. SHARED VARIABLE sd : bit_time := ('0'. Z. -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst.delay. . rq_delay. delay : TIME. • A passive process statement may appear in the entity statement part • Cannot make assignments to signals • This models the same flip-flop CHAPTER 9 15 © 1999. set. END ENTITY.delay. clk) BEGIN IF set = '1' THEN sd := ('1'.bt. 0 NS). rst. qb : OUT BIT). END PACKAGE bt. END PROCESS dff. BEGIN dff: PROCESS (rst. cq_delay).state AFTER sd. PORT (d. clk) BEGIN q <= sd. Navabi and McGraw-Hill Inc. ELSIF rst = '1' THEN sd := ('0'. clk : IN BIT. END RECORD. set.

EXIT WHEN condition. END IF. . IF x = 25 THEN EXIT. Navabi and McGraw-Hill Inc. Z..PROCESS STATEMENT long_runing : LOOP ... NEXT loop_label WHEN condition. . • • • • Loop is a sequential statement Example runs forever unless exited EXIT & NEXT control flow of loops EXIT & NEXT can be conditioned CHAPTER 9 16 © 1999. END LOOP long_runing..

.. Z.. loop_2 : WHILE j <= 90 LOOP . sequential_statement_3.. .. ....... sequential_statement_5. sequential_statement_2.PROCESS STATEMENT loop_1 : FOR i IN 5 TO 25 LOOP . . sequential_statement_4. sequential_statement_1. Navabi and McGraw-Hill Inc. • • • • Conditional Next Statements in a Loop FOR. WHILE are controlled forms of loop Can still use NEXT and EXIT The above NEXT statement causes looping to continue with statements 1 17 © 1999.. .. .. . sequential_statement_6. NEXT loop_1 WHEN condition_1. END LOOP loop_1. END LOOP loop_2. CHAPTER 9 ...

ASSERTION STATEMENT ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level. Navabi and McGraw-Hill Inc. MAKE SURE THAT false IS TRUE. . • • • • Use assert to flag violations Use assert to report events Can be sequential or concurrent Severity: FAILURE ERROR WARNING NOTE CHAPTER 9 18 © 1999. REPORT “reporting_message” SEVERITY severity_level. OTHERWISE REPORT "reporting_message". MAKE SURE THAT assertion_condition IS TRUE. Z. OTHERWISE REPORT "reporting_message" AND TAKE THE ACTION AT THIS severity_level.

END PROCESS dff. END IF. BEGIN dff: PROCESS (rst.ASSERTION STATEMENT ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. qb <= NOT state. IF set = '1' THEN state <= '1' AFTER sq_delay. set. • Conditions are checked only when process is activated • Make sure that set='1' AND rst='1' does not happen • Severity NOTE issues message CHAPTER 9 19 © 1999. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. Navabi and McGraw-Hill Inc. Z. . q <= state. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. END behavioral.

Z.ASSERTION STATEMENT ASSERT Good conditions REPORT Violation of good conditions SEVERITY Level. Navabi and McGraw-Hill Inc. ASSERT NOT things_that_should_not_happen REPORT a_message_that_bad_things_have_happened SEVIRITY action_to_take. • Good conditions may be too many to list • Good conditions = NOT (Bad conditions) • Easier to use NOT of unwanted cases CHAPTER 9 20 © 1999. .

.. Navabi and McGraw-Hill Inc.. • ASSERT hold_violation check REPORT..ASSERTION STATEMENT clock setup time data hold time Setup and Hold time checks use assert statement and signal attributes • Use ASSERT to check setup and hold • ASSERT set_up_violation check REPORT. . CHAPTER 9 21 © 1999. Z.

then a setup time violation has occurred. Navabi and McGraw-Hill Inc. Z. . if (data input has not been stable at least for the amount of the setup time). Setup Check in VHDL (clock = '1' AND NOT clock'STABLE) AND (NOT data'STABLE (setup_time)) • When the clock changes.ASSERTION STATEMENT clock setup time data hold time Setup Check in English When (clock changes from zero to 1). check for stable data • Check is placed after clock changes CHAPTER 9 22 © 1999.

ASSERTION STATEMENT clock setup time data hold time Hold Check in English When (there is a change on the data input) if the (logic value on the clock is '1') and the (clock has got a new value more recent than the amount of hold time). Hold Check in VHDL (data'EVENT) AND (clock = '1') AND (NOT clock'STABLE (hold_time)) • When data changes while clock is '1'. check for stable clock • Check is placed after data changes CHAPTER 9 23 © 1999. then hold time violation has occurred. . Navabi and McGraw-Hill Inc. Z.

setup. Z. BEGIN dff: PROCESS (rst. hold : TIME := 4 NS). • Using assertion statements for illegal Set-Reset combinations • Setup and Hold time violations • Concurrent and sequential assertion statements CHAPTER 9 24 © 1999. -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. END IF. q <= state. END PROCESS dff. clk : IN BIT. qb <= NOT state. set. ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING. BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING. Navabi and McGraw-Hill Inc. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. END d_sr_flipflop. ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. . cq_delay : TIME := 6 NS. q.ASSERTION STATEMENT ENTITY d_sr_flipflop IS GENERIC (sq_delay. IF set = '1' THEN state <= '1' AFTER sq_delay. set. rq_delay. PORT (d. rst. END behavioral. qb : OUT BIT).

Is the same as WAIT ON the_signal UNTIL expression_is_true. WAIT FOR 0 NS.SEQUENTIAL WAIT STATEMENTS WAIT FOR waiting_time. --"forever" © 1999. WAIT UNTIL waiting_condition. Used for handshaking and delay modeling WAIT FOR real_time. WAIT. WAIT ON waiting_sensitivity_list. --"a long time" WAIT ON (event on a signal). WAIT FOR. Navabi and McGraw-Hill Inc. Z. Is the same as WAIT ON a_signal UNTIL signal_is_true. CHAPTER 9 25 . WAIT UNTIL event makes condition true. WAIT ON some_event UNTIL a_condition FOR some_time. WAIT UNTIL a_signal_is_true. WAIT UNTIL expression_with_signal_and_variable_is_true. WAIT statements for flow control of sequential statements • • • • • • Sequential statements. WAIT.

ARCHITECTURE … … BEGIN … PROCESS (a. b.. END PROCESS. b. BEGIN … … … … END PROCESS. END ARCHITECTURE. c)..SEQUENTIAL WAIT STATEMENTS ARCHITECTURE … … BEGIN … PROCESS . Z. . Navabi and McGraw-Hill Inc. c) ... BEGIN … … … WAIT ON (a. A process with sensitivity behaves as A process with WAIT ON at the end • WAIT ON at the end is equivalent to using sensitivity list • Cannot use WAIT in a process with sensitivity list • WAIT suspends a Process CHAPTER 9 26 © 1999. END ARCHITECTURE.

SEQUENTIAL WAIT STATEMENTS Several examples will demonstrate WAIT statements in processes • A Moore 1011 detector • Can use WAIT in a Process statement CHAPTER 9 27 © 1999. Z. . Navabi and McGraw-Hill Inc.

WHEN got1 => WAIT UNTIL clk = '1'. END moore_detector. Z. WAIT UNTIL clk = '1'. IF x = '1' THEN current <= got1011. got101. IF x = '1' THEN current <= got1. WAIT FOR 1 NS. got1011). -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. WHEN got10 => WAIT UNTIL clk = '1'. got1. ELSE current <= got10. END PROCESS. . and clocked CHAPTER 9 28 © 1999. z : OUT BIT). ELSE current <= got10. Navabi and McGraw-Hill Inc. WHEN got101 => WAIT UNTIL clk = '1'. IF x = '1' THEN current <= got101. WHEN got1011 => z <= '1'. ELSE current <= reset. clk : IN BIT. END IF. END behavioral_state_machine. END IF. • • • • VHDL Description of the 1011 Sequence Detector Using Process and Wait Statements Each choice corresponds to a state Each state can be independently timed. ELSE current <= reset. END IF. SIGNAL current : state := reset. ELSE current <= got1. END CASE. IF x = '0' THEN current <= got10. BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'. END IF. IF x = '1' THEN current <= got1. z <= '0'.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. END IF. got10.

got1.. clk : IN BIT. END moore_detector. Navabi and McGraw-Hill Inc.. BEGIN PROCESS BEGIN CASE current IS . . END behavioral_state_machine. got10. got1011). .SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. • • • • • WAIT for rising edge of clk Assign new state to current Wait for transaction on current Can use WAIT ON current 'TRANSACTION instead Timing check flexibility in each state CHAPTER 9 29 © 1999. END PROCESS. END CASE. ELSE current <= got1. got101. IF x = '0' THEN current <= got10. END IF. WHEN got1 => WAIT UNTIL clk = '1'. Z.. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset.. SIGNAL current : state := reset. WAIT FOR 1 NS. z <= '0'. z : OUT BIT).

Z. WHEN got101 => IF x = '1' THEN current <= got1011. END CASE. . ELSE current <= got10. END IF. END PROCESS. SIGNAL current : state := reset. END IF. ELSE current <= reset. END IF. got101. • A simple state machine description • Not much timing flexibility • Allows a single clock • But easy and covers most cases CHAPTER 9 30 © 1999. z <= '1' WHEN current = got1011 ELSE '0'. got1011). z : OUT BIT).SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. clk : IN BIT. ELSE current <= got1. END IF. got10. WHEN got10 => IF x = '1' THEN current <= got101. ELSE current <= reset. END moore_detector. WHEN got1011 => IF x = '1' THEN current <= got1. WHEN got1 => IF x = '0' THEN current <= got10. END IF. BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1. got1. ELSE current <= got10. END behavioral_state_machine. Navabi and McGraw-Hill Inc. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. END IF.

Z.SEQUENTIAL WAIT STATEMENTS outputs next state Logic REG present state • Mealy machine detecting 101 • Use a style that separates logic and register parts • Also use an asynchronous reset CHAPTER 9 31 © 1999. . Navabi and McGraw-Hill Inc.

END behavioral. Navabi and McGraw-Hill Inc. END IF. SIGNAL nxt. • VHDL description for a state machine with asynchronous reset • Most synthesis tools accept this style • Flexible in register part control CHAPTER 9 32 © 1999. x) BEGIN z <= '0'. END IF. WHEN c => IF x = '0' THEN nxt <= a. WHEN b => IF x = '0' THEN nxt <= c. END IF. END CASE. ELSE nxt <= b. ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt. BEGIN reg : PROCESS (clk. ELSE nxt <= b. -ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a. -logic : PROCESS (present. END IF. r) BEGIN IF r = '1' THEN present <= a. END PROCESS. present : state. z : OUT BIT). IF present = c AND x = '1' THEN z <= '1'. Z. END ENTITY. END PROCESS. CASE present IS WHEN a => IF x = '0' THEN nxt <= a. c). clk : IN BIT. b.SEQUENTIAL WAIT STATEMENTS ENTITY asynch_reset_detector IS PORT (x. . END IF. r. ELSE nxt <= b.

.5 1.0 1. .5 2. c2 <= '1'.. Z. Navabi and McGraw-Hill Inc. WAIT FOR 10 NS. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. Time 0.. . WAIT FOR 480 NS.. c2 <= '0'.0 US c1 c2 10NS 10NS • Generation of the second phase of a two phase non-overlapping clocking • c2 is generated by phase2 process CHAPTER 9 33 © 1999. END PROCESS phase2.SEQUENTIAL WAIT STATEMENTS .

Z.start the following when ready to accept data WAIT UNTIL data_ready = '1'. WAIT UNTIL accepted = '1'. Navabi and McGraw-Hill Inc. --can use data_lines for other purposes System B: -. accepted <= '1'. data_ready <= '1'.start processing the newly received data WAIT UNTIL data_ready = '0'. • Systems A & B talk • A prepares data.SEQUENTIAL WAIT STATEMENTS data_lines system A data_ready valid data accepted system B Process Data System A: -. data_ready <= '0'. -. B accepts data • B releases A when data is picked CHAPTER 9 34 © 1999.start the following when ready to send data_lines <= newly_prepared_data. accepted <= '0'. .

Z. .SEQUENTIAL WAIT STATEMENTS 4 SYSTEM I in_data in_ready 16 out_data A in_received out_ready out_received B • • • • Use handshaking mechanism in an interface A prepares 4 bit data. talk to B to put data CHAPTER 9 35 © 1999. Navabi and McGraw-Hill Inc. B needs 16 bit data Create interface system I Talk to A to get data.

out_ready : OUT BIT).When ready. . END system_i. b_talk: PROCESS BEGIN .. • a_talk process & b_talk process also talk to each other • Use buffer_full. Navabi and McGraw-Hill Inc. buffer_picked. out_received : IN BIT. END waiting..When data is received.SEQUENTIAL WAIT STATEMENTS ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0). -.. END PROCESS a_talk. and word_buffer for a_talk and b_talk communication CHAPTER 9 36 © 1999. BEGIN a_talk: PROCESS BEGIN .. Z. collect 4 4-bit data.Talk to A. in_ready.. -ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full.. keep a count -. pass 16-bit data to b_talk . in_received. END PROCESS b_talk. buffer_picked : BIT := '0'.Wait for 16-bit data from a_talk -. out_data : OUT BIT_VECTOR (15 DOWNTO 0)... -. send to B using proper handshaking . SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0).

in_received <= '0'. END PROCESS b_talk. WAIT UNTIL in_ready = '0'. out_ready <= '0'. WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data. • a_talk gets data from A and talks to b_talk • b_talk talks to a_talk and sends data to B CHAPTER 9 37 © 1999. END IF. out_data <= word_buffer. . buffer_picked <= '0'. buffer_picked <= '1'.SEQUENTIAL WAIT STATEMENTS a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0. BEGIN WAIT UNTIL in_ready = '1'. Z. count := count + 1. END CASE. in_received <= '1'. out_ready <= '1'. WAIT UNTIL buffer_picked = '1'. buffer_full <= '1'. count := 0. WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data. buffer_full <= '0'. b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'. END PROCESS a_talk. WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data. WAIT UNTIL buffer_full = '0'. WAIT UNTIL out_received = '1'. WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data. Navabi and McGraw-Hill Inc. CASE count IS WHEN 0 => NULL.

Z. Navabi and McGraw-Hill Inc.SEQUENTIAL WAIT STATEMENTS clock Arbiter req ues t1 gra nt1 req ues t2 gra nt2 38 • • • • • req ues t0 gra nt0 Bus arbiter interface Simplified for this first example Synchronized arbitration A request input stays asserted until granted A request input is granted only one clock cycle of bus use CHAPTER 9 © 1999. req ues t3 gra nt3 .

FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000". END LOOP. grant : BUFFER BIT_VECTOR (3 DOWNTO 0). WAIT ON clock. END behavioral. END IF. process sensitivity cannot be used CHAPTER 9 39 © 1999. Navabi and McGraw-Hill Inc. END IF. ELSE grant (i) <= '0'. END PROCESS wait_cycle.SEQUENTIAL WAIT STATEMENTS ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0). clock : IN BIT). Z. grant (i) <= '1'. • Bus arbiter description • Check all requests after the falling edge of the clock • Because of the 20 NS wait. . END arbiter. -ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS.

CONSTANT t : TIME := 1 US. clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk. sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i). r(i) <= '1'. 3 US. 8 US). CONSTANT delays : time_array := (4 US. -ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT. clk).SEQUENTIAL WAIT STATEMENTS ENTITY arbtest IS END arbtest. SIGNAL r. END GENERATE. END io. g : BIT_VECTOR (3 DOWNTO 0). Navabi and McGraw-Hill Inc. • Testing the arbiter • Four processes for generating data are generated • The time_array constant specifies timing requests coming from a source CHAPTER 9 40 © 1999. r(i) <= '0'. WAIT UNTIL clk = '0'. 15 US. BEGIN arb : ENTITY WORK. Z. END PROCESS. . g.arbiter PORT MAP (r. TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME. WAIT UNTIL g(i) = '1'.

if stop bit is not seen Overrun error if start bit appears too soon CHAPTER 9 41 © 1999. . Navabi and McGraw-Hill Inc. Z.SEQUENTIAL WAIT STATEMENTS S2P da tar ea dy ov err un fra me _e rro r pa ral lel _o ut serial rec eiv ed 8 A 10 bit frame reading begins start bit data bits stop bit • • • • • Another example using WAIT statements Serial_to_parallel interface RS232 frame with one start bit and one stop bit Framing error.

CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US. END waiting. overrun <= '0'. END PROCESS too_fast. WAIT FOR full_bit.SEQUENTIAL WAIT STATEMENTS ENTITY serial2parallel IS GENERIC (bps : INTEGER). END IF. END PROCESS collect. END LOOP. WAIT ON dataready. • • • • • Serial2parallel VHDL description Two concurrent processes One waits for prepared data to be picked up (collect). Z. Navabi and McGraw-Hill Inc. END serial2parallel. WAIT UNTIL received = '1'. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). CONSTANT half_bit : TIME := (1E6/REAL(bps))/2. END IF. received : IN qit. IF dataready = '1' THEN ELSE WAIT UNTIL serial = '0'. while The other waits for untimely serial data to arrive (too_fast) WAIT statements are used in both processes 42 © 1999. parallel_out <= buff. IF serial = '0' THEN too_fast : PROCESS frame_error <= '1'. FOR count IN 0 TO 7 LOOP WAIT FOR full_bit.0 * 1 US. ELSE WAIT UNTIL received = '0'. dataready <= '0'. BEGIN WAIT UNTIL serial = '1'. frame_error <= '0'. WAIT FOR half_bit. frame_error : OUT qit. CHAPTER 9 . overrun. buff (count) := serial. overrun <= '1'. dataready : BUFFER qit. -ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS --VARIABLE buff : qit_vector (7 DOWNTO 0). END IF. IF dataready = '1' THEN dataready <= '1'. BEGIN WAIT UNTIL serial = '0'. PORT (serial.

of CHARACTER type INPUT. to write line to file READ procedure. Z.FORMATTED ASCII I/O OPERATIONS TEXTIO package is in the STD library TEXTIO contains: LINE type. to check the end of a file Examples will demonstrate TEXTIO package and its applications • Only CHARACTERS are handled • All predefined standard types are converted to CHARACTERS • Subprograms are overloaded for all standard types CHAPTER 9 43 © 1999. Navabi and McGraw-Hill Inc. to write data into a WRITELINE procedure. a pointer to STRING TEXT file type. to read a line from file READ procedure. to read data from a line a line WRITE procedure. to read data from a line a line ENDFILE function. OUTPUT files for standard device IO READLINE procedure. .

writes the value v to LINE l WRITELINE(f. READ_MODE). -.txt”. REAL..txt”. . FILE f : TEXT IS “input. “output. FILE_CLOSE (f).txt”. v.writes l to file f ENDFILE(f) -. WRITE_MODE). and unit if v is of type TIME CHAPTER 9 44 © 1999..reads a value v of its type from l WRITE(l. APPEND_MODE).txt”.. INTEGER. Z. STRING.).txt”. -. BOOLEAN. . l).FORMATTED ASCII I/O OPERATIONS VARIALE I : LINE. .returns TRUE if the end of f • READ and WRITE procedures are valid for: BIT. Navabi and McGraw-Hill Inc.read a line of file f into buffer l READ(l. FILE_OPEN (f. READLINE(f. v. “input. and TIME • Other parameters of these procedures include orientation. FILE f : TEXT OPEN READ_MODE IS “input. CHARACTER. FILE_OPEN (f. FILE_OPEN (f. l) -. FILE f : TEXT.. “output.) -. BIT_VECTOR. size.

got101). LEFT. got1. Z. END LOOP. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. 7). defined in VHDL for the standard output • INPUT and OUTPUT work in all operating systems CHAPTER 9 45 © 1999.TEXTIO.FORMATTED ASCII I/O OPERATIONS USE STD. RETURN sources(sources'LEFT). • A resolution function that writes its active drivers each time it is called • New code is highlighted • Unix device tty is the standard output • Can use OUTPUT... END one_of. TYPE state IS (reset. BEGIN FOR i IN sources'RANGE LOOP WRITE (l. FUNCTION one_of (sources : state_vector) RETURN state IS VARIABLE l : LINE. got10. . . FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". WRITELINE (flush. Navabi and McGraw-Hill Inc.ALL. l). state'IMAGE(sources(i)).

.". ELSIF value1'EVENT THEN WRITE (l. RIGHT. value1. RIGHT. WRITELINE (flush. NOW. • A display procedure for writing time and events • New values are listed • Filler is used for signal values that do not change CHAPTER 9 46 © 1999. filler. WRITE (l. LEFT. value1. filler. Navabi and McGraw-Hill Inc. l). VARIABLE l : LINE. WRITE (l. ELSE WRITE (l. 3). value2. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". 0). 3). Z. RIGHT. VARIABLE filler : STRING (1 TO 3) := " . BEGIN WRITE (l. END display. END IF. IF value1'EVENT AND value2'EVENT THEN WRITE (l. 3). RIGHT. NS). 0). value2. 3). RIGHT. WRITE (l.. LEFT.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. 8.

3). WRITE (l. value1. IF value1'EVENT AND value2'EVENT THEN WRITE (l. END PROCESS phase2. ELSE WRITE (l. RIGHT. 3). 0). NOW. 3). END IF. END input_output. WRITE (l. . USE STD. c2 <= '1'. RIGHT. filler. 0). LEFT. WAIT FOR 480 NS. END display. ELSIF value1'EVENT THEN WRITE (l. VARIABLE l : LINE.. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". Navabi and McGraw-Hill Inc. RIGHT. WRITELINE (flush. • Call the display procedure anytime a clock phase changes • This procedure is also called once at the beginning of simulation CHAPTER 9 47 © 1999. c2). Z. 3). c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. BEGIN WRITE (l. NS). filler. c2 <= '0'. l). VARIABLE filler : STRING (1 TO 3) := " . ENTITY two_phase_clock IS END two_phase_clock.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. BEGIN SIGNAL c2 : BIT := '0'. value1. RIGHT.ALL.TEXTIO. 8. RIGHT. display (c1. value2. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. WAIT FOR 10 NS. value2. WRITE (l. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'.". LEFT.

value2 : BIT. LEFT. END displaying. 3). . WRITE (l. Z. value1. FILE flush : TEXT). VARIABLE l : LINE. FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " . 0).". value2. filler. 0). NS). RIGHT. END displaying.. WRITE (l. • A procedure for writing in an already open file • A file of type TEXT is passed to this procedure • This goes in our new displaying package CHAPTER 9 48 © 1999.FORMATTED ASCII I/O OPERATIONS PACKAGE displaying IS PROCEDURE display (SIGNAL value1. RIGHT. ELSIF value1'EVENT THEN WRITE (l. LEFT. RIGHT. END display. IF value1'EVENT AND value2'EVENT THEN WRITE (l. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. Navabi and McGraw-Hill Inc. RIGHT. 3). 3). WRITELINE (flush. ELSE WRITE (l. value2. l). NOW. filler. 8. 3). value1. WRITE (l. END IF. RIGHT. BEGIN WRITE (l. value2 : BIT.

c2 <= '0'..ALL. BEGIN display (c1.TEXTIO. c2 <= '1'. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. Navabi and McGraw-Hill Inc.out". Z. value2 : BIT.ALL. FILE flush : TEXT) IS . END input_output. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. USE WORK. FILE flush : TEXT). FILE data : TEXT OPEN WRITE_MODE IS "clock. SIGNAL c2 : BIT := '0'.ALL. END displaying. END PROCESS phase2. value2 : BIT.TEXTIO. PACKAGE displaying IS PROCEDURE display (SIGNAL value1. END display. WAIT FOR 10 NS. USE STD. • Passing an open file to a procedure • File declaration takes place in the declarative part of an architecture • File remains open after being written into • Writing can continue elsewhere CHAPTER 9 49 © 1999. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. .. WAIT FOR 480 NS. data).displaying. ENTITY two_phase_clock IS END two_phase_clock. c2. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. END displaying.FORMATTED ASCII I/O OPERATIONS USE STD.

..... ..... 1 0 .. ... 1 0 . .. 1 0 . 1 0 ... .. . 1 0 .FORMATTED ASCII I/O OPERATIONS 0 500 510 990 1000 1500 1510 1990 2000 2500 2510 2990 3000 3500 3510 3990 4000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns . • Output file generated by the input_output architecture • File closes at the end of simulation CHAPTER 9 50 © 1999. Z. 1 0 .. 1 0 . .. 0 . . Navabi and McGraw-Hill Inc. 1 0 .

WRITELINE (flush. 5). LEFT. CONSTANT print_resolution : TIME := 5 NS. RIGHT. Z. ELSE WRITE (l. WRITE (l. IF s = '1' THEN WRITE (l. IF NOW = 0 US THEN VARIABLE lo_to_hi : STRING (1 TO 3) := ". c1. NOW. calls the append_wave_slice procedure Buffer l is visible in the procedure. ELSE ENTITY two_phase_clock IS END two_phase_clock. SIGNAL c2 : BIT := '0'. writing: PROCESS (print_tick. c2) • • • • Generating an ASCII plot file 5 NS print resolution reports of the two-phase clock description Process wakes up. Navabi and McGraw-Hill Inc. phase2: PROCESS -BEGIN ARCHITECTURE input_output OF two_phase_clock WAIT UNTIL c1 = '0'. RIGHT. appending is done to this line CHAPTER 9 51 © 1999. ELSE END input_output. print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED. SIGNAL c1 : BIT := '1'.". lo_to_hi. append_wave_slice (c2). END IF. FILE flush : TEXT OPEN WRITE_MODE IS "clock4. WAIT FOR 480 NS. NS). c1. RIGHT. l). BEGIN END PROCESS phase2. IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN append_wave_slice (c1). END IF. END IF.-+". lo_value. 5).ALL. ELSE WRITE (l.FORMATTED ASCII I/O OPERATIONS c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US USE STD. c2 <= '0'. BEGIN VARIABLE hi_value : STRING (1 TO 3) := " |". VARIABLE hi_to_lo : STRING (1 TO 3) := "+-. WRITE (l.out". IF s = '1' THEN WRITE (l. PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| ". c2 <= '1'. WRITELINE (flush. SIGNAL print_tick : BIT := '0'. . END PROCEDURE append_wave_slice. 0). VARIABLE l : LINE. BEGIN END IF. l). hi_value.TEXTIO. RIGHT. header. 5). hi_to_lo. 5). 8. VARIABLE header : STRING (1 TO 18) := " c1 c2 ". RIGHT. IS WAIT FOR 10 NS. END PROCESS writing.

" for 1 to 0 Write ". Navabi and McGraw-Hill Inc.. ns ns ns ns ns ns ns ns ns ns ns | | | | +-.FORMATTED ASCII I/O OPERATIONS c1 480 485 490 495 500 505 510 510 515 520 525 . "| " for '0' Write "+-.. | | | | | | c2 | | | | | | | . .-+ | | | • • • • • Plot generated by the ploting process Plotting is activated every 5 NS Write " |" for '1'.-+" for 0 to 1 CHAPTER 9 52 © 1999. Z.

74LS85. Navabi and McGraw-Hill Inc.MSI BASED DESIGN 8 data_in clk clear_bar load_bar count_in 4 sequential comparator 4 count Produces modulo-16 count of consecutive matching data Closing the chapter. . Z. 74LS163 Assume these parts are available CHAPTER 9 53 © 1999. will present a top-down design with MSI parts • • • • Sequential comparator circuit Design based on MSI parts 74LS377.

. Z. Navabi and McGraw-Hill Inc.MSI BASED DESIGN sequential comparator 8-bit register 8-bit comparator 4-bit counter 4-bit comparator 4-bit comparator • Partition the circuit into smaller components • Partition until library components or synthesizable parts are reached • Will use top-down technique in designing a CPU in Chapter 10 CHAPTER 9 54 © 1999.

3. 5D [1] [2] [4] [8] • Standard MSI parts • Register. comparator. Z. Navabi and McGraw-Hill Inc.4+ GI 1C2 < = > P P<Q P=Q P>Q Q 2D 1. .MSI BASED DESIGN 74LS377 74LS85 74LS163 5CT=0 CTRDIV16 M1 M2 3CT=15 G3 G4 C5/2. counter CHAPTER 9 55 © 1999.

PORT (a. b : IN qit_vector (3 DOWNTO 0). ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay. lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay. a_eq_b <= '0' AFTER prop_delay. Z.basic_utilities. . a_lt_b : OUT qit). eq. a_lt_b <= '0' AFTER prop_delay. lt : IN qit. END ls85_comparator. END PROCESS. eq. b. Navabi and McGraw-Hill Inc. four bit comparator • Relational operators. a_lt_b <= lt AFTER prop_delay. gt. a_eq_b <= '0' AFTER prop_delay. a_eq_b <= eq AFTER prop_delay. a_eq_b. ordering for array operands • Default delays can be configured later CHAPTER 9 56 © 1999. • 74LS85. END behavioral. END IF. ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS). gt. a_lt_b <= '1' AFTER prop_delay. ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay. a_gt_b.ALL. -ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a.MSI BASED DESIGN USE WORK.

ALL. END dataflow. q8 : OUT qit_vector (7 DOWNTO 0)). Z. g_bar : IN qit. d8 : IN qit_vector (7 DOWNTO 0).MSI BASED DESIGN USE WORK. . • 74LS377. PORT (clk. END ls377_register. ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS).basic_utilities. Navabi and McGraw-Hill Inc. BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0'). -ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN. q8 <= GUARDED d8 AFTER prop_delay. clocked register • Default delays can be used or reconfigured CHAPTER 9 57 © 1999.

END IF. IF (internal_count = "1111" AND ent = ‘1’) THEN rco <= '1' AFTER prop_delay. ELSIF (ld_bar = '0') THEN internal_count := abcd. Navabi and McGraw-Hill Inc. END ls163_counter. q_abcd : OUT qit_vector (3 DOWNTO 0). BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000". ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS).basic_utilities. END IF. END PROCESS counting.ALL. . ELSE rco <= '0'. END IF. q_abcd <= internal_count AFTER prop_delay.MSI BASED DESIGN USE WORK. ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count). clr_bar. Z. ent : IN qit. four bit synchronous counter • Default delays can be overwritten CHAPTER 9 58 © 1999. abcd : IN qit_vector (3 DOWNTO 0). PORT (clk. enp. -ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000". rco : OUT qit). • 74LS163. END behavioral. ld_bar.

Z. specify delay CHAPTER 9 59 © 1999. .MSI BASED DESIGN LS377_register(behavioral) clk clear_bar load_bar data_in 8 4 8 clk d8 reg: d_register 4 q8 4 standard sequential comparator(structural) LS163_counter(behavioral) a b gt eq lt cmp_hi: comparator a_gt_b a_eq_b a_lt_b clk clr_bar load_bar enp ent abcd cnt: counter rco 4 q_abcd count g_bar prop_delay prop_delay 4 a b count_in gt eq lt 4 cmp_lo: comparator a_gt_b a_eq_b prop_delay a_lt_b prop_delay 15NS 18NS LS85_comparator(behavioral) 22NS • Design is based on available parts • Configure to use LS library. Navabi and McGraw-Hill Inc.

count. END COMPONENT. clr_bar. ent : IN qit. vdd. lt : IN qit. END sequential_comparator. old_data (3 DOWNTO 0). gt. lt_i). SIGNAL compare_out : qit. clear_bar. SIGNAL gt_i. SIGNAL old_data : qit_vector (7 DOWNTO 0).basic_utilities.ALL. abcd : IN qit_vector (3 DOWNTO 0). count : OUT qit_vector (3 DOWNTO 0) ). BEGIN reg: d_register PORT MAP (clk. gnd. a_eq_b. OPEN. cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4). SIGNAL gnd : qit := '0'. count_in : IN qit_vector (3 DOWNTO 0). vdd. gnd. clk. b : IN qit_vector (3 DOWNTO 0). gt_i. END structural. • Design is based on available parts • Assert statement in the entity declaration • Configure to use LS library. ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0). OPEN). . old_data). eq_i. compare_out. -ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk. a_gt_b. OPEN). count_in. clear_bar. specify delay CHAPTER 9 60 © 1999. load_bar : IN qit. Navabi and McGraw-Hill Inc. g_bar : IN qit. cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0). compare_out. gt_i. ld_bar. eq_i. load_bar. q_abcd : OUT qit_vector (3 DOWNTO 0). END COMPONENT. old_data (7 DOWNTO 4). lt_i : qit. Z. lt_i. BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING. q8 : OUT qit_vector (7 DOWNTO 0)). COMPONENT comparator PORT (a. data_in. eq_i. cnt: counter PORT MAP (clk. SIGNAL vdd : qit := '1'. rco : OUT qit). gnd.MSI BASED DESIGN USE WORK. d8 : IN qit_vector (7 DOWNTO 0). COMPONENT counter PORT (clk. eq. END COMPONENT. enp. a_lt_b : OUT qit).

. END FOR. END FOR.MSI BASED DESIGN USE WORK. FOR ALL : comparator USE ENTITY WORK. • Configuring the structural architecture of the sequential_comparator • Configuration declaration binds to 74LS parts • Generic values overwrite those of the 74LS parts CHAPTER 9 61 © 1999. FOR cnt : counter USE ENTITY WORK. CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK. END standard. END FOR.ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS).ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS). Z.ALL. Navabi and McGraw-Hill Inc.ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS). END FOR.

ck. mfi : seq_comp PORT MAP (data. FOR mfi : seq_comp USE CONFIGURATION WORK. SIGNAL cnt_out : qit_vector (3 DOWNTO 0). '0' AFTER 50 US. data <= "00000000". clear_bar. "01010100" AFTER 25 US. END input_output. '0' AFTER 60 US. ENTITY test_sequential_comparator IS END test_sequential_comparator. SIGNAL data : qit_vector (7 DOWNTO 0). cnt_out). BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck. count_in : IN qit_vector (3 DOWNTO 0).MSI BASED DESIGN USE WORK.basic_utilities. count : OUT qit_vector (3 DOWNTO 0) ). clk.standard. SIGNAL ck. "0111" AFTER 55 US. ld_bar <= '1'. Navabi and McGraw-Hill Inc. "01110111" AFTER 3 US.ALL. . END COMPONENT. ld_bar : qit. cl_bar. "1011" AFTER 40 US. load_bar : IN qit. cl_bar. SIGNAL cnt : qit_vector (3 DOWNTO 0). cnt <= "1111". -ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0). cnt. • Testbench verifies behavior • Configuration specification associates mfi: seq_comp with the standard configuration declaration CHAPTER 9 62 © 1999. ld_bar. "10101100" AFTER 5 US. Z. cl_bar <= '1'. '1' AFTER 55 US.

Although behavioral level constructs of VHDL provide a convenient method of describing very complex hardware. handshaking. Various forms of wait statements were extensively used in these descriptions. and file I/O.SUMMARY This chapter presented descriptions of hardware at the behavioral level and discussed how a process statement can be used to describe the main functionality of a module. In the first part of the chapter. Behavioral descriptions can be read and understood by non-technical managers and others who are not very familiar with VHDL. a hardware designer can completely describe a digital circuit without having to use these constructs. Z. . Navabi and McGraw-Hill Inc. syntax and semantics for various forms of this construct were described. • End Of Chapter 9 CHAPTER 9 63 © 1999. We then showed how process statements are used to describe controlling hardware.

1 DEFINING A COMPREHENSIVE EXAMPLE 10.1 Data and Control Partitioning 10.5.3 General Description Methodology 10.6 A TEST BENCH FOR THE PARWAN CPU 10.1 Memory Organization of Parwan 10.4 Programming in Parwan Assembly 10.2 Timing of Data and Control Events 10.2 Synthesizability 10.3.7.4 Parwan Behavioral Architecture 10.2 Instruction Set 10.3 Interface Description of Parwan 10.3 Instruction Format 10.7.2 PARWAN CPU 10.3 BEHAVIORAL DESCRIPTION OF PARWAN 10. Z.3 Hardware Modifications 10.4.3.1 Timing and Clocking 10.3.7 Wiring Data and Control Sections 10.8 SUMMARY CHAPTER 10 1 © 1999.5.5 Data Section of Parwan 10.4.CHAPTER 10 CPU MODELING AND DESIGN 10.4.7.2 Global View of Parwan Components 10.6 Control Section of Parwan 10.3.5 DATAFLOW DESCRIPTION OF PARWAN 10.2. Navabi and McGraw-Hill Inc.2.3 Instruction Execution 10. .5.2 Packages 10.4 PARWAN BUSSING STRUCTURE 10.2.7 A MORE REALISTIC PARWAN 10.2.5.4 Description of Components 10.1 Interconnection of Components 10.5.5.5.1 CPU Control Signals 10.

Z. PAR_1. and show its hardware details • • • • • General Layout of Parwan PARWAN. A Reduced Processor Simple 8-bit CPU. 12-bit Address Primarily designed for educational purposes Includes most common instructions CHAPTER 10 2 © 1999.DEFINING A COMPREHENSIVE EXAMPLE MAR PC IR SR AC ALU SHU Controller Will define a CPU describe it in VHDL. 8-bit Data. . Navabi and McGraw-Hill Inc.

page 1 . . 1 0 Offset E:00 . • • • • • Page and Offset Parts of Parwan addresses Memory divided into pages Pages of 256 bytes Address has page and offset part Uses memory mapped IO CHAPTER 10 3 © 1999.2:FF MEMORY: 5 4 3 2 page 0 . Z. page 2 . .1:FF 2:00 . Navabi and McGraw-Hill Inc.E:FF F:00 .F:FF page 14 . .0:FF 1:00 . .PARWAN CPU 7 6 1 1 1 0 0 9 Page 0 8 0 0 7 6 0 5 0 4 0 0 3 2 0 1 0 0 0:00 . . page 15 . .

ASL. (8 bit) JSR. . (12 bits) direct/indirect LDA. Navabi and McGraw-Hill Inc. STA PAGE Address. JMP. BRA_V. CLA. ASR • • • • Three groups of instructions Full Address instructions include page and offset Page address instructions include offset No Address instructions occupy a single byte CHAPTER 10 4 © 1999. SUB. ADD.PARWAN CPU FULL Address. Z. AND. CMA. BRA_C. BRA_N NO Address NOP. CMC. BRA_Z.

Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Brief Description Load AC w/(loc) AND AC w/(loc) Add (loc) to AC Sub (loc) from AC Jump to adr Store AC in loc Subroutine to tos Branch to adr if V Branch to adr if C Branch to adr if Z Branch to adr if N No operation Clear AC Complement AC Complement carry Arith shift left Arith shift right Address Bits 12 12 12 12 12 12 8 8 8 8 8 - Address Scheme FULL FULL FULL FULL FULL FULL PAGE PAGE PAGE PAGE PAGE NONE NONE NONE NONE NONE NONE Indirect Address YES YES YES YES YES YES NO NO NO NO NO NO NO NO NO NO NO Flags Use -------c--c----------v---c---z---n ----------c-------- Flags Set --zn --zn vczn vczn -----------------------------zn -c-vczn --zn • • • • Summary of Parwan instructions. . Navabi and McGraw-Hill Inc. Load and store operations Arithmetic & logical operations jmp and branch instructions CHAPTER 10 5 © 1999. Z.

Z. Navabi and McGraw-Hill Inc.PARWAN CPU Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Opcode Bits 765 000 001 010 011 100 101 110 111 111 111 111 111 111 111 111 111 111 D/I Bit 4 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 0 0 0 0 0 0 Bits 3210 Page adr Page adr Page adr Page adr Page adr Page adr ---1000 0100 0010 0001 0000 0001 0010 0100 1000 1001 • Parwan instruction opcodes • CPU contains V C Z N flags • Instructions use and/or influence these flags CHAPTER 10 6 © 1999. .

SUB. CMA. SUB. ASL. LDA. ASR use V C Z N BRA_V BRA_C. CMC BRA_Z BRA_N • Arithmetic instructions influence all flags • Branch instructions use corresponding flags • Shift instructions influence all flags CHAPTER 10 7 © 1999. ADD.PARWAN CPU influence ADD. LDA. CMA. . ASR ADD. ASL. ASL ADD. SUB. Z. CMC ADD. SUB. ASL. SUB. Navabi and McGraw-Hill Inc. AND. AND.

Navabi and McGraw-Hill Inc. Z. .complete address pg: loc opc page pg: loc+1 offset • • • • • Addressing in full-address instructions Full address instructions use two bytes Right hand side of first byte is page Second byte contains offset Bit 4 is direct/indirect [0/1] indicator CHAPTER 10 8 © 1999.

Navabi and McGraw-Hill Inc. Z.PARWAN CPU complete address pg: loc jsr or branch pg: loc+1 offset • • • • • Addressing in page-address instructions Page address instructions use two bytes All of first byte is used by opcode Page part of address uses current page Second byte is the offset CHAPTER 10 9 © 1999. .

. BRA_C 6A 5:0D 5:0E 5:0F 11110100 6A . Z... .. BRANCH TO 6A if carry is set c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A • Branching is done within current page only • A branch instruction CHAPTER 10 10 © 1999.PARWAN CPU MEMORY . Navabi and McGraw-Hill Inc.

. 5:33 5:34 00000000 SUBROUTINE CODE .... Navabi and McGraw-Hill Inc... .. 5:33 PC-> 5:34 .PARWAN CPU MEMORY PC-> 5:11 5:12 5:13 MEMORY 5:11 5:12 5:13 ....... before and after jsr Store jsr return address at tos Begin subroutine at tos+1 Use indirect jmp to tos for return from subroutine CHAPTER 10 11 © 1999. . Z.. 5:55 5:56 5:57 JMP Indirect 3 3 B E F O R E J S R 5:55 5:56 5:57 JMP Indirect 3 3 .. JSR 3 3 INSTR AFTER JSR . 1 3 SUBROUTINE CODE .. JSR 3 3 INSTR AFTER JSR .. A F T E R J S R • • • • • An example for the execution of jsr Memory and pc. ..

Navabi and McGraw-Hill Inc. Indirect addressing affects offset only To obtain actual address full addressing is used To obtain data page addressing is used CHAPTER 10 12 © 1999. . Z.PARWAN CPU Indirect address Actual address Data Any page and offset Same page Indirecting effects offset operand 0:25 opc 1 6 6:1F 1 8 0:26 3 5 6:35 1 F • • • • An example for indirect addressing in Parwan.

store count back -.end if zero count -.store pointer back -.increment pointer -.load count -. i sta 4:03 lda 4:00 add 4:02 sta 4:00 lda 4:01 sub 4:02 bra_z sta 4:01 lda 4:03 jmp 0:17 nop -.decrement count :2D -.adding completed • • • • • An example program for Parwan CPU A program to add 10 bytes Use location 4:00 for data pointer Use location 4:01 for counter Constant 1 in 4:02 is used for +1 and -1 CHAPTER 10 13 © 1999.clear accumulator -.PARWAN CPU 0:15 0:16 0:17 0:19 0:1B 0:1D 0:1F 0:21 0:23 0:25 0:27 0:29 0:2B 0:2D cla asl add. .store partial sum -.load 01 in 4:02 -.add bytes -.load 10 in 4:01 -.load 25 in 4:00 -.clears carry 4:00 -. Navabi and McGraw-Hill Inc.go for next byte -.load pointer -. Z.get partial sum -.

-LIBRARY par_library.par_utilities. USE cmos.ALL.ALL. Navabi and McGraw-Hill Inc. USE par_library.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. • Packages used will be described • A single component will describe all of Parwan CHAPTER 10 14 © 1999. Coding for the behavioral description of Parwan will be presented. USE par_library. -ENTITY par_central_processing_unit IS . Z... -ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral. . END par_central_processing_unit.ALL.par_parameters.basic_utilities.

SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0). b : qit) RETURN qit . -PACKAGE par_utilities IS FUNCTION "XOR" (a. SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0).BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT zero_12 : twelve := "000000000000". b : qit_vector. SUBTYPE twelve IS qit_vector (11 DOWNTO 0). cin : qit) RETURN qit_vector. Navabi and McGraw-Hill Inc. -SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0). FUNCTION sub_cv (a. b : qit_vector) RETURN qit_vector.ALL. SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0). cin : qit) RETURN qit_vector.basic_utilities. -FUNCTION add_cv (a. • • • • Declarations of par_utilities package of par_library Machine descriptions require utilities Use basic_utilities Additional utilities are included in par_utilities CHAPTER 10 15 © 1999. . FUNCTION "NOT" (a : qit_vector) RETURN qit_vector. CONSTANT zero_8 : byte := "00000000". FUNCTION "AND" (a. SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0). b : qit_vector) RETURN qit_vector. -FUNCTION set_if_zero (a : qit_vector) RETURN qit. FUNCTION "OR" (a. -SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0). -CONSTANT zero_4 : nibble := "0000". USE cmos. -SUBTYPE nibble IS qit_vector (3 DOWNTO 0). SUBTYPE byte IS qit_vector (7 DOWNTO 0). b : qit_vector. -END par_utilities. Z.

RETURN r. END LOOP loop1. • Body of par_utilities package of par_library library • Define XOR in qit • Overload logical operators with qit_vector CHAPTER 10 16 © 1999. Navabi and McGraw-Hill Inc.'1'. . BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i). END "OR".'0'.'X').'X'). BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i).'X'). ('1'. RETURN r. END "NOT". FUNCTION "AND" (a.b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE). ('1'. b).'X'.'X')).BEHAVIORAL DESCRIPTION OF PARWAN PACKAGE BODY par_utilities IS FUNCTION "XOR" (a. END LOOP loop1.'0'.'0'.'0'. b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0'. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i). -FUNCTION "OR" (a.'X'. BEGIN RETURN qit_xor_table (a. -FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE).'1'. RETURN r.b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE). END "XOR". ('X'. END "AND". Z. END LOOP loop1.

b : qit_vector. b_sign: qit. IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'.extra r bits : msb: overflow. BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'. cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0). not_b. END LOOP. CHAPTER 10 17 . END sub_cv. r(a'LEFT+1) := c(a'LEFT). END IF. • • • • Body of the par_utilities package of par_library library add_cv adds its operands creates c and v bits Put overflow in leftmost result bit Put carry to the right of overflow © 1999. FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'. b_sign := b(b'LEFT). --overflow ELSE r(a'LEFT+2) := '0'. not_c). c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)). EXIT. r(0) := a(0) XOR b(0) XOR cin. r := add_cv (a. c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)). -. VARIABLE not_c : qit. BEGIN a_sign := a(a'LEFT). END add_cv. Z. cin : qit) RETURN qit_vector IS VARIABLE r. not_c := NOT cin. END set_if_zero. FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1). BEGIN not_b := NOT b. RETURN r. VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0). next to msb: carry VARIABLE a_sign. END par_utilities.BEHAVIORAL DESCRIPTION OF PARWAN FUNCTION add_cv (a. FUNCTION sub_cv (a. RETURN r. c: qit_vector (a'LEFT + 2 DOWNTO 0). RETURN zero. b : qit_vector. END IF. Navabi and McGraw-Hill Inc. END LOOP.

CONSTANT lda : qit_vector (2 DOWNTO 0) := "000". CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110". END par_parameters. CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111". CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000".basic_utilities. CONSTANT add : qit_vector (2 DOWNTO 0) := "010". CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001". CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001". USE cmos. CONSTANT sta : qit_vector (2 DOWNTO 0) := "101". Z.ALL. CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011". . • Declaration of par_parameters Package of par_library • Assign appropriate names to opcodes • par_parameters is used for readability CHAPTER 10 18 © 1999. CONSTANT ann : qit_vector (2 DOWNTO 0) := "001". -PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110". CONSTANT indirect : qit := '1'. CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11". CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100". Navabi and McGraw-Hill Inc. CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010". CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100".BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos.

PORT (clk : IN qit. cycle_time : TIME := 4 US). USE par_library. -ENTITY par_central_processing_unit IS GENERIC (read_high_time. read_low_time. databus : INOUT wired_byte BUS := "ZZZZZZZZ". Navabi and McGraw-Hill Inc.basic_utilities.ALL. • Interface description of Parwan CHAPTER 10 19 © 1999.par_parameters. write_low_time : TIME := 2 US.ALL.par_utilities. USE par_library. . USE cmos. -LIBRARY par_library. Z.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. interrupt : IN qit.ALL. read_mem. write_high_time. END par_central_processing_unit. write_mem : OUT qit. adbus : OUT twelve ).

26. IF byte1 (7 DOWNTO 5) = jsr THEN Execute jsr instruction.read operand for lda. -. increment pc.ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN Execute jmp instruction. increment pc. Figure 10. Figure 10.19. ELSE -. ELSE -. top. Figure 10.22. Remove memory from databus. sub Read memory onto databus. -.all other two-byte instructions IF byte1 (4) = indirect THEN Use byte1 and byte2 to get address. byte2 has address. Figure 10.23.20.17. Figure 10. and.18.BEHAVIORAL DESCRIPTION OF PARWAN ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS Declare necessary variables. Figure 10. Figure 10. Figure 10. Figure 10. add. -. sub END IF. -. END IF. IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN Execute single-byte instructions. BEGIN IF interrupt = '1' THEN Handle interrupt. Execute lda. Figure 10. ELSE -. and.16. add.21. Navabi and McGraw-Hill Inc. .two-byte instructions Read second byte into byte2.interrupt / otherwise END PROCESS. address in byte2. END IF. Figure 10.26.jsr / bra / other double-byte instructions END IF. and. add. -. Figure 10. and sub. Z. END behavioral. middle. bottom. ELSIF byte1 (7 DOWNTO 5) = sta THEN Execute sta instruction.no interrupt Read first byte into byte1.jmp / sta / lda.26. Figure 10.24. • Outline of the Behavioral Description of Parwan CHAPTER 10 20 © 1999. write ac.25. ELSIF byte1 (7 DOWNTO 4) = bra THEN Execute bra instructions. ELSE -.single-byte / double-byte END IF.

n : qit. Z. Reading the first byte CHAPTER 10 21 © 1999. • Variable declarations of Parwan behavioral model pc := zero_12. c. Interrupt handling. part of Parwan behavioral model • Filling the outline of the behavioral description of Parwan • Declarations. pc := inc (pc). z. . • Reading the first byte from the memory. byte2 : byte. byte1.BEHAVIORAL DESCRIPTION OF PARWAN VARIABLE pc : twelve. read_mem <= '0'. VARIABLE v. • Interrupt handling of Parwan behavioral model adbus <= pc. WAIT FOR read_low_time. VARIABLE ac. WAIT FOR read_high_time. byte1 := byte (databus). Navabi and McGraw-Hill Inc. read_mem <= '1'. VARIABLE temp : qit_vector (9 DOWNTO 0). WAIT FOR cycle_time.

asl. IF ac = zero_8 THEN z := '1'. WHEN asr => ac := ac (7) & ac (7 DOWNTO 1). IF c /= n THEN v := '1'. n := ac (7). cma. ac := ac (6 DOWNTO 0) & '0'.BEHAVIORAL DESCRIPTION OF PARWAN CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8. Z. n := ac (7). cla. asr CHAPTER 10 22 © 1999. END CASE. WHEN cmc => c := NOT c. n := ac (7). WHEN asl => c := ac (7). • Executing single-byte instructions in the behavioral model of Parwan • Using the least significant nibble for decoding instructions • Decoding instructions. END IF. END IF. . WHEN cma => ac := NOT ac. IF ac = zero_8 THEN z := ‘1’. END IF. END IF. Navabi and McGraw-Hill Inc. WHEN OTHERS => NULL. cmc. IF ac = zero_8 THEN z := '1'.

write_mem <= '1'. • Reading the second byte from the memory. pc (7 DOWNTO 0) := inc (byte2). WAIT FOR write_low_time. part of Parwan behavioral model databus <= wired_byte (pc (7 DOWNTO 0) ). pc := inc (pc). WAIT FOR read_high_time. Navabi and McGraw-Hill Inc. Z. write_mem <= '0'. . • Execution of the jsr instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Reading the second byte. read_mem <= '0'. WAIT FOR read_low_time. byte2 := byte (databus).BEHAVIORAL DESCRIPTION OF PARWAN adbus <= pc. Executing jsr CHAPTER 10 23 © 1999. databus <= "ZZZZZZZZ". read_mem <= '1'. adbus (7 DOWNTO 0) <= byte2. WAIT FOR write_high_time.

Navabi and McGraw-Hill Inc. WAIT FOR read_high_time. Z. • Handling indirect addressing by the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Branch instruction. byte2 := byte (databus). END IF. read_mem <= '0'. WAIT FOR read_low_time. • Execution of branch instructions in the behavioral model of Parwan adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). read_mem <= '1'. adbus (7 DOWNTO 0) <= byte2.BEHAVIORAL DESCRIPTION OF PARWAN IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2. . Handling indirect addressing CHAPTER 10 24 © 1999.

. WAIT FOR write_low_time. databus <= wired_byte (ac). Navabi and McGraw-Hill Inc. Z. • Execution of sta instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Handling jmp and sta instructions CHAPTER 10 25 © 1999. WAIT FOR write_high_time. write_mem <= '0'.BEHAVIORAL DESCRIPTION OF PARWAN pc := byte1 (3 DOWNTO 0) & byte2. • Execution of jmp instruction in the behavioral model of Parwan adbus <= byte1 (3 DOWNTO 0) & byte2. write_mem <= '1'. databus <= "ZZZZZZZZ".

add. END CASE. c := temp (8). and. • Execution of lda. WAIT FOR read_high_time. WHEN sbb => temp := sub_cv (ac. IF ac = zero_8 THEN z := '1'. Z. WHEN OTHERS => NULL. c). c). . c := temp (8). byte (databus). WHEN add => temp := add_cv (ac. v := temp (9). Navabi and McGraw-Hill Inc. adbus (7 DOWNTO 0) <= byte2. ac := temp (7 DOWNTO 0). ac := temp (7 DOWNTO 0). WAIT FOR read_low_time. CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus). and sub instructions in the behavioral model of Parwan CHAPTER 10 26 © 1999.BEHAVIORAL DESCRIPTION OF PARWAN adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). read_mem <= '1'. END IF. read_mem <= '0'. byte (databus). n := ac (7). WHEN ann => ac := ac AND byte (databus). v := temp (9).

. Z. ADBUS obus_on_dbus 8 8 4 8 AC ac_out a_side ALU b_side IR ir_out PC_PAGE pc_out PC_OFFSET CONTROLLER alu_flags 4 8 mar_page_bus mar_inp MAR_PAGE OBUS 4 mar_offset_bus alu_out SHU 4 8 MAR_OFFSET 8 mar_out SR 4 read_mem write_mem interrupt ADBUS 12 • Bussing structure of Parwan CHAPTER 10 27 © 1999..PARWAN BUSSING STRUCTURE databus_on_dbus DATABUS dbus_on_databus DBUS 8 4096 byte memory . Navabi and McGraw-Hill Inc. .

Navabi and McGraw-Hill Inc. . Z.PARWAN BUSSING STRUCTURE Component AC IR PC MAR SR ALU SHU Type Register Register Loadable Up Counter Register Register Arithmetic Unit Shifter Logic Bits 8 8 12 12 4 8 8 • • • • Machine has 7 components Behavioral description helps partitioning the circuit Circuit components will be identified Bussing specifies interconnection of these components CHAPTER 10 28 © 1999.

Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac . Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir Pc_on_mar_page_bus Get Address Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus Get Operand. Navabi and McGraw-Hill Inc.. Next Fetch • Steps for execution of lda CHAPTER 10 29 © 1999.PARWAN BUSSING STRUCTURE LDA Instruction: Cycle 1 Begin Fetch Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Pc_on_mar_page_bus.. . Z.

PARWAN BUSSING STRUCTURE Data Signals DATA SECTION Data Components and Buses CONTROL SECTION Control Signals • Data and control sections of Parwan CPU • 31 control signals from the controller to the data unit CHAPTER 10 30 © 1999. Navabi and McGraw-Hill Inc. Z. .

alu_add. alu_a. load_offset_pc. pc_on_mar_offset_bus. load_offset_mar load_sr. alu_b.DATAFLOW DESCRIPTION OF PARWAN Applies To AC IR PC Category Register Control Register Control Register Control Signal Name load_ac. cm_carry_sr pc_on_mar_page_bus. arith_shift_right alu_and. alu_not. reset_pc Loads ac Resets ac Loads ir Increments pc Functionality Loads page part of pc Loads offset part of pc Resets pc Loads page part of mar Loads offset part of mar Loads sr Complements carry flag of sr Puts page part of pc on mar page bus Puts 4 bits of ir on mar page bus Puts offset part of pc on mar offset bus Puts dbus on mar offset bus Puts offset part of pc on dbus Puts obus on dbus Puts external databus on internal dbus Puts all of mar on adbus Puts internal dbus on external databus Shifter shifts its input one place to the left Shifter shifts its input one place to the right Output of alu becomes and of its two inputs Output of alu becomes complement of its b input Output of alu becomes the same as its a input alu perfporms add operation on its two inputs Output of alu becomes the same as its b input alu perfporms subtraction of its two inputs Starts a memory read operation Starts a memory write operation Interrupts CPU MAR SR MAR_BUS Register Control Register Control Bus Control load_page_mar. databus_on_dbus ADBUS DATABUS SHU ALU Bus Control Bus Control Logic Units Logic Units mar_on_adbus dbus_on_databus arith_shift_left. zero_ac load_ir increment_pc. obus_on_dbus. Z. ir_on_mar_page_bus. write_mem. dbus_on_mar_offset_bus DBUS Bus Control pc_offset_on_dbus. . alu_sub Others I/O read_mem. interrupt • Inputs and outputs of Parwan control section • Signals for flow of data and data clocking CHAPTER 10 31 © 1999. load_page_pc. Navabi and McGraw-Hill Inc.

Z.DATAFLOW DESCRIPTION OF PARWAN System Clock Control Signal 1 Control Signal 2 Control signals remain asserted for a complete clock cycle Allows logic unit propagation Clock data and control at the same time Clock data while control signals are still valid • Timing of control signals • Assume falling edge trigger data and control CHAPTER 10 32 © 1999. . Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. • Operations and flags of alu • A control signal for each operation CHAPTER 10 33 © 1999. Z. .DATAFLOW DESCRIPTION OF PARWAN Id 0 1 2 3 4 5 Opcode line alu_and alu_not alu_a alu_add alu_b alu_sub Operation a AND b NOT b a b PLUS a b b MINUS a Flags zn zn zn vczn zn vczn Individual data components will be described in VHDL. Will also show hardware.

Navabi and McGraw-Hill Inc. 4. 3. 5) CO (0. . 1. 2.DATAFLOW DESCRIPTION OF PARWAN ai bi alu_and alu_not 0 1 2 3 4 5 VI CI ZI NI A B A B A B A B A B A B A B A B ALU (3. 5) VO (3. 2. 3. 5) NO alu_a alu_add [0] [1] [2] [3] [4] [5] [6] [7] alu_sub + alu_b - • Parwan alu • Logic symbol • One bit gate level hardware CHAPTER 10 34 © 1999. Z. 5) ZO (0. 1. 4.

DATAFLOW DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000". • Package declaration for the alu_operations package • Simplify code and add readability CHAPTER 10 35 © 1999.ALL. Navabi and McGraw-Hill Inc. CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000". USE cmos. Z. CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000". -PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001". . CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010".basic_utilities. CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100". END alu_operations.

v := v_flag_in. z_out <= t (7 DOWNTO 0). in_flags : IN nibble. alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0). ALIAS c_flag_in : qit IS in_flags(2). alu_not. n : qit. -ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side. Z. -. alu_not. ALIAS n_flag_in : qit IS in_flags(0). v := v_flag_in. c := c_flag_in. n := t(7). c := t(8). alu_a. alu_a. out_flags <= (v. c := t(8). END PROCESS coding. alu_and. c_flag_in). b_side : IN byte. . v := t(9). alu_and) IS • Behavioral description of arithmetic logic unit of Parwan CHAPTER 10 36 © 1999. END behavioral. WHEN b_input => t (7 DOWNTO 0) := b_side. c := c_flag_in. alu_b. alu_not. BEGIN WHEN a_add_b => t := add_cv (b_side. c. alu_a. END CASE. ALIAS z_flag_in : qit IS in_flags(1). alu_and. alu_b. z. alu_add. n).DATAFLOW DESCRIPTION OF PARWAN ENTITY arithmetic_logic_unit IS PORT (a_side. END arithmetic_logic_unit. b_side. alu_sub : IN qit. alu_add. a_side. out_flags : OUT nibble). a_side. WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side. v := t(9). c_flag_in). alu_b. c := c_flag_in. WHEN b_compl => t (7 DOWNTO 0) := NOT b_side. c. v := v_flag_in. WHEN OTHERS => NULL. CASE qit_vector (5 DOWNTO 0)’ (alu_sub. ALIAS v_flag_in : qit IS in_flags(3). z_out : OUT byte. WHEN a_input => t (7 DOWNTO 0) := a_side. alu_add. c := c_flag_in.other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side. v := v_flag_in. Navabi and McGraw-Hill Inc. z := set_if_zero (t (7 DOWNTO 0)). z. VARIABLE v.

DATAFLOW DESCRIPTION OF PARWAN L R Input Output SHU L R VI CI ZI NI [0] [1] [2] [3] [4] [5] [6] [7] i+1 i i ( L) VO (L) CO (L. R) ZO (L. . Navabi and McGraw-Hill Inc. R) NO i-1 • Parwan shu • Logic symbol • One bit hardware CHAPTER 10 37 © 1999. Z.

END IF. v := v_flag_in. END behavioral. arith_shift_left. out_flags : OUT nibble). ALIAS v_flag_in : qit IS in_flags(3). END shifter_unit. • Behavioral Description of the Shifter Unit of Parwan CHAPTER 10 38 © 1999.DATAFLOW DESCRIPTION OF PARWAN ENTITY shifter_unit IS PORT (alu_side : IN byte. BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0). Navabi and McGraw-Hill Inc. arith_shift_left. z. Z. END PROCESS coding. (v. n). arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0). n) := in_flags. z. out_flags <= (v. c := alu_side (7). z := set_if_zero (t). c. arith_shift_right : IN qit. obus_side <= t. n : qit. in_flags : IN nibble. n := t (7). -ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side. c. v := alu_side (6) XOR alu_side (7). n := t (7). ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'. ALIAS z_flag_in : qit IS in_flags(1). ALIAS c_flag_in : qit IS in_flags(2). z. . c. z := set_if_zero (t). ALIAS n_flag_in : qit IS in_flags(0). obus_side : OUT byte. ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1). VARIABLE v. c := c_flag_in.

3D 1. 3D [0] [1] [2] [3] N Z C V input c 2D Q output c load G1 cm_carry 1C2 • The status register • Logic symbol • One bit hardware CHAPTER 10 39 © 1999. . Z. 3D 2. Navabi and McGraw-Hill Inc. 3D 1. 3D 1.DATAFLOW DESCRIPTION OF PARWAN load cm_carry G1 G2 C3 SR N Z C V 1.

out_status : OUT nibble. END behavioral. -ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000". Navabi and McGraw-Hill Inc. Z. • Behavioral description of the status register of Parwan CHAPTER 10 40 © 1999. cm_carry. ck : IN qit ). BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags. ALIAS internal_c : qit IS internal_state (2). END IF. out_status <= internal_state. ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c.DATAFLOW DESCRIPTION OF PARWAN ENTITY status_register_unit IS PORT (in_flags : IN nibble. END status_register_unit. load. END PROCESS. . END IF.

4D 3. 4D 2. 4D 2. 4D 3. 4D 2. 4D 2. 4D 3. 4D 3. Navabi and McGraw-Hill Inc. 4D 2. 4D 3. 4D 3.DATAFLOW DESCRIPTION OF PARWAN load zero G1 M2 M3 1C4 AC zero '0' I0 '0' I1 '0' I2 '0' I3 '0' I4 '0' I5 '0' I6 '0' I7 2. 4D 2. . 4D 3. 4D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 2D Q Oi I o2 o3 o4 o5 o6 o7 i G1 1C2 • Parwan accumulator • Logic symbol • One bit hardware CHAPTER 10 41 © 1999. 4D 3. Z. 4D 2.

o8 : OUT byte.DATAFLOW DESCRIPTION OF PARWAN ENTITY accumulator_unit IS PORT (i8 : IN byte. load. END BLOCK enable. END BLOCK clocking. zero. Navabi and McGraw-Hill Inc. END accumulator_unit. Z. -ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8. END dataflow. . • Dataflow description of Parwan accumulator CHAPTER 10 42 © 1999. ck : IN qit).

. Z.DATAFLOW DESCRIPTION OF PARWAN IR LOAD CI 1C2 I I0 I1 I2 I3 I4 I5 I6 I7 2D 2D 2D 2D 2D 2D 2D 2D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 o2 o3 o4 i 2D Q Oi load o5 o6 o7 G1 1C2 • The Parwan instruction register • Logic symbol • One bit hardware CHAPTER 10 43 © 1999. Navabi and McGraw-Hill Inc.

END instruction_register_unit.DATAFLOW DESCRIPTION OF PARWAN ENTITY instruction_register_unit IS PORT (i8 : IN byte. Z. Navabi and McGraw-Hill Inc. END dataflow. END BLOCK enable. . -ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8. ck : IN qit). o8 : OUT byte. END BLOCK clocking. • Dataflow description of the instruction register of Parwan CHAPTER 10 44 © 1999. load.

3D 2. 3D 1. 3D 2. Z. 3D 2. Navabi and McGraw-Hill Inc. 3D 2. 3D 1.DATAFLOW DESCRIPTION OF PARWAN reset load_page load_offset increment 3R G1 G2 G4 C3/4+ PC I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. . 3D 2. 3D 2. 3D 1. 3D 1. 3D 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 O i-1 reset o4 o5 o6 o7 o8 o9 o10 o11 2R Q Oi G1 1T C2 load_pc_offset clock • Parwan program counter • Logic symbol • One bit hardware CHAPTER 10 45 © 1999.

Navabi and McGraw-Hill Inc. END IF. increment. END behavioral. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). -ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. . o12 : OUT twelve. • Behavioral description of the program counter of Parwan CHAPTER 10 46 © 1999. load_offset. END IF. load_page. ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). END program_counter_unit. reset. END IF. BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12. END PROCESS.DATAFLOW DESCRIPTION OF PARWAN ENTITY program_counter_unit IS PORT (i12 : IN twelve. END IF. Z. ck : IN qit). ELSIF increment = '1' THEN internal_state := inc (internal_state). o12 <= internal_state.

3D 1. 3D 1. 3D 2. 3D 2. 3D 1. 3D 2. 3D 2. 3D 2. 3D 2. 3D 1. Z. 3D 2. Navabi and McGraw-Hill Inc. .DATAFLOW DESCRIPTION OF PARWAN MAR load_page load_offset G1 G2 C3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 I i 2D Q Oi load G1 1C2 • Logic symbol for the memory address register of Parwan CHAPTER 10 47 © 1999.

Z. ck : IN qit). load_page. load_offset. END IF. Navabi and McGraw-Hill Inc. END behavioral. END IF. • Behavioral description of the memory address register of Parwan CHAPTER 10 48 © 1999. BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). END IF. -ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. o12 : OUT twelve.DATAFLOW DESCRIPTION OF PARWAN ENTITY memory_address_register_unit IS PORT (i12 : IN twelve. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). END memory_address_register_unit. END PROCESS. o12 <= internal_state. .

reset_pc. pc_offset_on_dbus. Navabi and McGraw-Hill Inc.logic unit function control inputs: arith_shift_left. Z. dbus_on_databus. ir_on_mar_page_bus. alu_b. load_page_mar. databus_on_dbus. alu_add.register controls: load_ac. • Entity Declaration of the Data Section of Parwan • Wires all components • Specifies bussing CHAPTER 10 49 © 1999. load_offset_pc. pc_on_mar_offset_bus. -. alu_and. clk : IN qit. dbus_on_mar_offset_bus. alu_sub : IN qit. status : OUT nibble ). cm_carry_sr. zero_ac. -. . END par_data_path. increment_pc. obus_on_dbus. arith_shift_right. load_offset_mar. adbus : OUT twelve.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_data_path IS PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ".outputs to the controller: ir_lines : OUT byte. alu_not. load_ir.bus connections: pc_on_mar_page_bus. alu_a. load_page_pc. load_sr. mar_on_adbus. -. -.

o12 : OUT twelve.program_counter_unit (behavioral). alu_not.accumulator_unit (dataflow). cm_carry. load_offset. ck : IN qit ). END COMPONENT. alu_add. load. reset. load. alu_b. FOR r3: pc USE ENTITY WORK. -COMPONENT ir PORT (i8: IN byte. o8: OUT byte. .DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE structural OF par_data_path IS -COMPONENT ac PORT (i8: IN byte. alu_sub : IN qit. END COMPONENT. load_page. -SIGNAL ac_out. ir_out. -COMPONENT shu PORT (alu_side : IN byte. ck : IN qit). increment. END COMPONENT. FOR l1 : alu USE ENTITY WORK. out_status : OUT nibble. obus_side : OUT byte. • Declarative Part of the structural Architecture of par_data_path • Components are declared • Busses and signals are declared CHAPTER 10 50 © 1999. END COMPONENT. arith_shift_right : IN qit.status_register_unit (behavioral). alu_a.memory_address_register_unit (behavioral). SIGNAL dbus : wired_byte BUS. ck : IN qit). FOR r5 : sr USE ENTITY WORK. -COMPONENT alu in_flags : IN nibble. SIGNAL alu_a_inp : byte. alu_out. END COMPONENT. z_out : OUT byte. zero. o12 : OUT twelve. mar_out : twelve. SIGNAL alu_flags. out_flags : OUT nibble). FOR r2: ir USE ENTITY WORK. ck: IN qit). in_flags : IN nibble. END COMPONENT. out_flags : OUT nibble). -COMPONENT mar PORT (i12 : IN twelve. FOR l2 : shu USE ENTITY WORK.shifter_unit (behavioral). o8: OUT byte. END COMPONENT. shu_flags. Navabi and McGraw-Hill Inc. ck: IN qit).arithmetic_logic_unit (behavioral). Z. load. FOR r1: ac USE ENTITY WORK. load_page. b_side : IN byte. obus : byte. arith_shift_left. sr_out : nibble. -COMPONENT pc PORT (i12 : IN twelve. SIGNAL mar_inp : twelve.instruction_register_unit (dataflow). -COMPONENT sr PORT (in_flags : IN nibble. SIGNAL pc_out. FOR r4: mar USE ENTITY WORK. load_offset. PORT (a_side. alu_and. SIGNAL mar_bus : wired_twelve BUS.

END BLOCK databus1. ac_out. clk). END BLOCK ir2. END BLOCK dbus3. -r2: ir PORT MAP (obus.bus connections --dbus1: alu_a_inp <= qit_vector (dbus). . clk). -databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus. Navabi and McGraw-Hill Inc. • Statement part of the par_data_path structural Architecture • Uses block statements for bussing • Register interconnections follow registers instantiation CHAPTER 10 51 © 1999. END BLOCK dbus2.DATAFLOW DESCRIPTION OF PARWAN BEGIN -. Z. -mar_bus1: mar_inp <= qit_vector (mar_bus). load_ac. zero_ac. ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)). ir1: ir_lines <= ir_out. -obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus). ir_out. dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus. load_ir. END BLOCK obus1. dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus.register connections --r1: ac PORT MAP (obus. --.

load_offset_mar. mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out. -r4: mar PORT MAP (mar_inp. alu_sub. END BLOCK mar1. ac_out. load_sr. sr1: status <= sr_out. END structural. END BLOCK pc2. Z.DATAFLOW DESCRIPTION OF PARWAN r3: pc PORT MAP (mar_out. load_page_pc. pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). alu_b. pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). alu_flags). load_offset_pc. sr_out. -r5: sr PORT MAP (shu_flags. • Statement part of the par_data_path structural Architecture • Ends with logic unit instantiations CHAPTER 10 52 © 1999. obus. arith_shift_left. reset_pc. alu_and. sr_out. l2: shu PORT MAP (alu_out. cm_carry_sr. clk). clk). alu_a. pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)).connection of logical and register structures --l1: alu PORT MAP (alu_a_inp. END BLOCK pc3. alu_out. END BLOCK pc1. --. shu_flags). pc_out. mar_out. clk). increment_pc. alu_flags. . alu_add. alu_not. Navabi and McGraw-Hill Inc. arith_shift_right. load_page_mar.

Navabi and McGraw-Hill Inc. style.DATAFLOW DESCRIPTION OF PARWAN To other control FF inputs External Signals logic block control FF i Q All Signals Activating State i 1D i C1 signals issuing control signals control signals to data section en system clock For the Parwan controller. hardware and coding will be described. . Z. • Typical hardware surrounding a control flip-flop • The logic block is designated by a bubble • Controller is built using one-hot encoding CHAPTER 10 53 © 1999.

Z. .DATAFLOW DESCRIPTION OF PARWAN csx a b c logic block i d e logic block j csy Q 1D i C1 en 1D j C1 Q en 1D k C1 Q clock • Example for the structure of Parwan control section • Showing 3 states in a one-hot implementation CHAPTER 10 54 © 1999. Navabi and McGraw-Hill Inc.

pc_offset_on_dbus. -.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_control_unit IS GENERIC (read_delay. END par_control_unit. Navabi and McGraw-Hill Inc. dbus_on_databus. -. increment_pc. -. dbus_on_mar_offset_bus. -. databus_on_dbus. alu_b. alu_sub : OUT ored_qit BUS. interrupt : IN qit ). load_ir. alu_not. ir_on_mar_page_bus.inputs from the data section: ir_lines : IN byte. load_offset_pc.logic unit function control outputs: arith_shift_left. pc_on_mar_offset_bus. obus_on_dbus. write_mem : OUT ored_qit BUS. cm_carry_sr. BEGIN • • • • Entity declaration of Parwan control section Showing signals for the data unit Declaring states of the machine is shown Declarative part of the par_control_unit dataflow architecture CHAPTER 10 55 © 1999. mar_on_adbus. write_delay : TIME := 3 NS). load_sr. load_page_pc. . Z. arith_shift_right. -. alu_add. status : IN nibble. load_page_mar. alu_a. ------------------------------------------------------------------------------------------------ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. alu_and. zero_ac.bus connection control signals: pc_on_mar_page_bus. load_offset_mar.memory control and other external signals: read_mem. PORT (clk : IN qit. reset_pc.register control signals: load_ac.

.DATAFLOW DESCRIPTION OF PARWAN par_control_unit control_signal_1 assignments to control_signal_1 control_signal_2 control_signal_3 oring_qit type signals • Assigning signals with implied oring. Navabi and McGraw-Hill Inc. par_control_unit outputs CHAPTER 10 56 © 1999. Z.

start of fetch -.DATAFLOW DESCRIPTION OF PARWAN s1: BLOCK (s(1) = '1') BEGIN -. s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'. load_offset_mar <= GUARDED '1'. .goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'. -.reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'.pc to mar pc_on_mar_page_bus <= GUARDED '1'. END BLOCK ck. -. END BLOCK s1. Z. pc_on_mar_offset_bus <= GUARDED '1'. pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 2 reset_pc 1D 1 interrupt C1 • State 1: starting a fetch • VHDL code • Gate level hardware CHAPTER 10 57 © 1999. load_page_mar <= GUARDED '1'. Navabi and McGraw-Hill Inc.

load_ir <= GUARDED '1'. alu_a <= GUARDED ‘1’. Z. Navabi and McGraw-Hill Inc.fetching continues -. -. databus_on_dbus <= GUARDED '1'. .DATAFLOW DESCRIPTION OF PARWAN s2: BLOCK (s(2) = '1') BEGIN -.goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'. END BLOCK ck. -. read_mem <= GUARDED '1' AFTER read_delay.read memory into ir mar_on_adbus <= GUARDED '1'. END BLOCK s2.increment pc increment_pc <= GUARDED '1'. mar_on_adbus read_mem databus_on_dbus alu_a load_ir increment_pc 3 1D 2 C1 • State 2: completing a fetch • VHDL code • Gate level hardware CHAPTER 10 58 © 1999.

load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. END BLOCK sb. Z. load_offset_mar <= GUARDED '1'. pc_on_mar_offset_bus <= GUARDED '1'. arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'. load_page_mar <= GUARDED '1'. END BLOCK ck. arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'. -.perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not. load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. -.DATAFLOW DESCRIPTION OF PARWAN s3: BLOCK (s(3) = '1') BEGIN -. cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'. for next read pc_on_mar_page_bus <= GUARDED '1'. END BLOCK ck. alu_b) <= GUARDED qit_vector’(“10”) WHEN ir_lines (1) = ‘1’ ELSE qit_vector’( “01”).pc to mar. Navabi and McGraw-Hill Inc. • State 3: preparing for address fetch • Execution of single byte instructions • VHDL code CHAPTER 10 59 © 1999. . END BLOCK s3. ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'.goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'.

DATAFLOW DESCRIPTION OF PARWAN pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 4 1D 3 IR7 IR6 IR5 IR4 C1 2 IR3 2 1 0 IR3 2 1 0 IR1 arith_shift_left arith_shift_right alu_not alu_b IR1 IR3 IR1 cm_carry_sr IR2 IR3 1 IR3 0 zero_ac load_ac load_sr • State 3: preparing for address fetch • Execution of single byte instructions • Gate level hardware CHAPTER 10 60 © 1999. . Z. Navabi and McGraw-Hill Inc.

END BLOCK pg.page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'. Navabi and McGraw-Hill Inc.indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'. • • • • State 4: completing address of full address instructions Branching for indirect.read memory into mar offset mar_on_adbus <= GUARDED '1'.goto 5 for indirect. -. Z.page from ir. 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'. -. read_mem <= GUARDED '1' AFTER read_delay. dbus_on_mar_offset_bus <= GUARDED '1'. load_page_mar <= GUARDED '1'.jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'. and branch VHDL code Gate level hardware CHAPTER 10 61 © 1999. -. -. direct. databus_on_dbus <= GUARDED '1'. -.increment pc increment_pc <= GUARDED '1'. -.DATAFLOW DESCRIPTION OF PARWAN s4: BLOCK (s(4) = '1') BEGIN -. and offset from next memory makeup 12-bit address -. END BLOCK sp.keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -. 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'.bra END BLOCK ck. -. jsr.completed operand (dir/indir) address -.direct END BLOCK ck. -. END BLOCK s4. .goto 7 for jsr. load_offset_mar <= GUARDED '1'.

. jsr. Navabi and McGraw-Hill Inc. Z. direct.DATAFLOW DESCRIPTION OF PARWAN mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offet_bus load_offset_mar increment_pc ir_on_mar_page_bus load_page_mar IR7 1D 4 6 5 C1 IR4 6 IR5 9 7 • State 4: completing address of full address instructions • Branching for indirect. and branch • Gate level hardware CHAPTER 10 62 © 1999.

END BLOCK s5. dbus_on_mar_offset_bus <= GUARDED '1'. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN s5: BLOCK (s(5) = '1') BEGIN -. Z.read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'. load_offset_mar <= GUARDED '1'. END BLOCK ck. mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offset_bus load_offset_mar 6 1D 5 c1 • State 5: taking care of indirect addressing • Actual address will now go in MAR CHAPTER 10 63 © 1999. databus_on_dbus <= GUARDED '1'.goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay. -.indirect addressing -. .

Reading and executing jmp. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN . jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • • • • • State 6: reading the actual operand. END BLOCK jm. and sub instructions Outline of the VHDL code Outline of the hardware Three separate blocks for [jmp]... Navabi and McGraw-Hill Inc. add. add. sub] CHAPTER 10 64 © 1999. Z. [sta]. add. sta.perform lda. and [lda. lda.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN . and. and.. .... END BLOCK st. sub END BLOCK s6. and. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN . -. END BLOCK rd.

sub] CHAPTER 10 65 © 1999. -. . • • • • State 6: reading the actual operand. END BLOCK ck. and. add. END BLOCK jm. Z.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'.. . Navabi and McGraw-Hill Inc. END BLOCK s6. load_offset_pc <= GUARDED '1'.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'.. Reading and executing jmp instruction VHDL code Two more blocks for [sta]. and [lda.

END BLOCK st. . Navabi and McGraw-Hill Inc. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. dbus_on_databus <= GUARDED '1'. write_mem <= GUARDED '1' AFTER write_delay. END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN .... add. ac on databus. sub] CHAPTER 10 66 © 1999. • • • • State 6: reading the actual operand. write to memory mar_on_adbus <= GUARDED '1'. obus_on_dbus <= GUARDED '1'.mar on adbus.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. -. END BLOCK s6. Reading and executing sta instruction Partial VHDL code Need one more block for handling [lda. alu_b <= GUARDED ‘1’.. . and. Z.

-. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’. Navabi and McGraw-Hill Inc. sta. add.mar on adbus. lda. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. Z. END BLOCK ck. and. add. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. add. and. read memory for operand. and. read_mem <= GUARDED '1' AFTER read_delay.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. and sub instructions Completing the VHDL code This last block handles [lda.. -. sub END BLOCK s6.perform lda. sub] CHAPTER 10 67 © 1999.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN . load_sr <= GUARDED '1'. load_ac <= GUARDED '1'. • • • • State 6: reading the actual operand. END BLOCK rd. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. perform operation mar_on_adbus <= GUARDED '1'. databus_on_dbus <= GUARDED '1'.. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. . Reading and executing jmp.

-. END BLOCK ck. read_mem <= GUARDED '1' AFTER read_delay. END BLOCK jm.mar on adbus. and.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'. END BLOCK rd. add.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. load_sr <= GUARDED '1'. sub END BLOCK s6. load_ac <= GUARDED '1'. load_offset_pc <= GUARDED '1'. write_mem <= GUARDED '1' AFTER write_delay. alu_b <= GUARDED ‘1’. . sta. END BLOCK ck. databus_on_dbus <= GUARDED '1'.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. -. • State 6: reading the actual operand. dbus_on_databus <= GUARDED '1'. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. END BLOCK st. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’. add. perform operation mar_on_adbus <= GUARDED '1'.mar on adbus. -. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. lda. read memory for operand. Navabi and McGraw-Hill Inc.perform lda. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. write to memory mar_on_adbus <= GUARDED '1'. -. and executing jmp. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. Z. obus_on_dbus <= GUARDED '1'. END BLOCK ck. ac on databus. and sub instructions • Complete VHDL code CHAPTER 10 68 © 1999.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. and. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’.

and sub instructions • Complete gate level hardware CHAPTER 10 69 © 1999. . lda. add. sta. and executing jmp.DATAFLOW DESCRIPTION OF PARWAN jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • State 6: reading the actual operand. Navabi and McGraw-Hill Inc. and. Z.

goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'. dbus_on_databus <= GUARDED '1'. Z. Navabi and McGraw-Hill Inc. mar_on_adbus pc_offset_on_dbus dbus_on_databus write_mem load_offset_pc 8 1D 7 c1 • • • • State 7: writing return address of subroutine Making pc point to top of subroutine Complete VHDL code Hardware CHAPTER 10 70 © 1999. write_mem <= GUARDED '1' AFTER write_delay. pc_offset_on_dbus <= GUARDED '1'. END BLOCK s7. -. END BLOCK ck.address of subroutine to pc load_offset_pc <= GUARDED '1'.jsr -. -.write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s7: BLOCK (s(7) = '1') BEGIN -. .

-. Z.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s8: BLOCK (s(8) = '1') BEGIN -. . Navabi and McGraw-Hill Inc. increment_pc 9 1D 8 c1 • State 8: incrementing pc to skip location reserved for return address • VHDL code • Hardware CHAPTER 10 71 © 1999. END BLOCK s8.increment pc increment_pc <= GUARDED '1'.

goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. ir3 status3 ir2 status2 load_offset_pc ir1 status1 ir0 status0 1 1D 9 C1 • State 9: conditional loading of pc for branch instructions • VHDL code • Gate level hardware CHAPTER 10 72 © 1999.DATAFLOW DESCRIPTION OF PARWAN s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'. END BLOCK ck. . Navabi and McGraw-Hill Inc. END BLOCK s9. Z. -.

OOOO S8: BLOCK (s(8) = '1') BEGIN . ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000".. • • • • Ending the dataflow description of the par_control_unit Controller outline Need to clock all states A zero driver is placed on all state.. BEGIN s(next) <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. Navabi and McGraw-Hill Inc.State blocks end here END dataflow. BEGIN S1: BLOCK (s(1) = '1') BEGIN . END BLOCK ck. . BEGIN s(next) <= GUARDED '1'.. END BLOCK ck. BEGIN s(next) <= GUARDED '1'.... END BLOCK s8. END BLOCK s2. S2: BLOCK (s(2) = '1') BEGIN . Z. S9: BLOCK (s(9) = '1') BEGIN .. END BLOCK ck. BEGIN s(next) <= GUARDED '1'. END BLOCK ck. END BLOCK s1. CHAPTER 10 73 © 1999. END BLOCK ck. -... END BLOCK s9.

Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN Q 1D 1 C1 en 1D 2 C1 Q 3 C1 Q en Q 1D 4 C1 en 1D 5 C1 Q 1D 6 C1 Q en Q 1D 7 C1 1D 8 C1 Q 1D 9 C1 Q • Complete control unit • Wire individual control flip-flops • Oring is done at inputs of states when branching is done to them CHAPTER 10 74 © 1999. Z. .

. read_mem. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_central_processing_unit IS PORT (clk : IN qit. adbus : OUT twelve ). interrupt : IN qit. write_mem : OUT qit. Z. END par_central_processing_unit. • Entity declaration of the Parwan CPU for its dataflow description • Complete CPU wires data and control CHAPTER 10 75 © 1999. databus : INOUT wired_byte BUS := "ZZZZZZZZ".

-COMPONENT par_control_unit PORT (clk : IN qit. END dataflow. . FOR data: par_data_path USE ENTITY WORK. zero_ac. interrupt : IN qit ). adbus : OUT twelve. zero_ac. status ). ir_lines. ir_lines. BEGIN data: par_data_path PORT MAP (databus. load_ac. CHAPTER 10 76 . • The general outline of dataflow architectture of Parwan CPU. END COMPONENT. adbus. ir_lines : OUT byte. END COMPONENT. . ctrl: par_control_unit PORT MAP (clk. -SIGNAL load_ac. ir_lines : IN byte. status : IN nibble. . zero_ac. . . .par_data_path (structural). interrupt ). read_mem. clk : IN qit. . . FOR ctrl: par_control_unit USE ENTITY WORK. load_ac. SIGNAL ir_lines : byte. . read_mem. Navabi and McGraw-Hill Inc. . write_mem : OUT qit. Z. . . write_mem.par_control_unit (dataflow). zero_ac. • Data and control declarations • Data and control wiring © 1999. clk. status : OUT nibble ). status. .DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte. load_ac. . SIGNAL status : nibble. load_ac. zero_ac. .

31) "10000000". Z. "00011000". "00100100". "00000000". "01100000". '0' AFTER 4500 NS. nop. END IF. --jmp 18 "00000000". "00010010". "00011011". interrupt. • A simple testbench • Include CPU instantiation. "00011111". add 27 "11100010". qit2int (address. BEGIN WAIT ON read. --(28. SIGNAL data : wired_byte := "ZZZZZZZZ". "01110000". TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. "00000000". read. -. "01011010". data <= "ZZZZZZZZ". read_mem. cpu : parwan PORT MAP (clock. 25. data. "00011100". sta 25 "00100000". write. WAIT UNTIL read = '0'. "00100100". END COMPONENT. 29. "01000000". databus : INOUT wired_byte BUS. Navabi and McGraw-Hill Inc. 26. "00000000". cma. asr. "00010010". interrupt. jsr 36 "11101000". WAIT UNTIL write = '0'. --(24. write_mem : OUT qit.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit. ia). 27) "00001100". "10010000". sub 28 "00010000". "11000000". END input_output. jmp 32 "00000000". "00011101". END PROCESS mem. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. VARIABLE ia : INTEGER. . "00100000". --asl. a short memory. "11100010". BEGIN int : interrupt <= '1'. "00000000".. interrupt : IN qit. "00000000". address). ELSE data <= wired_byte ( memory (ia) ). IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". • A simple test bench for Parwan behavioral and dataflow descriptions. adbus : OUT twelve ). "11101001". write. --lda 24. "01011100". END IF. 30. "11100000". "00000000". "10000000". and read/write handshaking CHAPTER 10 77 © 1999. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). "00011001". SIGNAL address : twelve. "00011010". --cac. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". "10100000". --and 26. write : qit. read. SIGNAL clock. --lda i 29. END IF. jmp i 36 OTHERS => (OTHERS => ‘0’)). "00000000".

nop. 27) "00001100". "00000000". "00011011". 25. "00010010". "10010000". "00000000". --lda i 29.. "10100000". "00011000". "01100000". --asl. TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. 26. "00000000". 30. "00100000".. "00100100". "11100000". --and 26. "00000000". mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". "00000000". -. "01011010". cpu : parwan PORT MAP (clock. SIGNAL address : twelve. asr.. cma. VARIABLE ia : INTEGER. "10000000". BEGIN . write. Navabi and McGraw-Hill Inc. interrupt. "01110000". "00011111". sub 28 "00010000".. read. jsr 36 "11101000". 29. Z. • Initializing memory for Parwan instructions CHAPTER 10 78 © 1999. SIGNAL data : wired_byte := "ZZZZZZZZ". "00000000". read.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . "01011100". "11101001". SIGNAL clock. data. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. END input_output. jmp i 36 OTHERS => (OTHERS => ‘0’)). "00011100". "11000000". --cac. interrupt. address). "11100010".. --(24. "00010010". jmp 32 "00000000". "00100100". --lda 24. --(28. "00000000". "00011010". "00011101". write : qit. --jmp 18 "00000000". . 31) "10000000". '0' AFTER 4500 NS. sta 25 "00100000". "00011001". BEGIN int : interrupt <= '1'. add 27 "11100010". "01000000".

ELSE data <= wired_byte ( memory (ia) ). data.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . write. . write. interrupt. write : qit. END IF. '0' AFTER 4500 NS. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := . BEGIN WAIT ON read. END PROCESS mem.. cpu : parwan PORT MAP (clock. END input_output. ia). clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. VARIABLE ia : INTEGER. END IF.. address). END IF. interrupt. SIGNAL data : wired_byte := "ZZZZZZZZ". read. qit2int (address. • • • • Produce test waveforms on interrupt and clock signals Testing is done by modeling memory read and write operations A single process assigns values from memory to databus Same process handles memory write CHAPTER 10 79 © 1999. data <= "ZZZZZZZZ". BEGIN int : interrupt <= '1'. TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. WAIT UNTIL write = '0'. Z. read.. WAIT UNTIL read = '0'. IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". SIGNAL address : twelve.. Navabi and McGraw-Hill Inc. SIGNAL clock.

END FOR.par_central_processing_unit(behavioral). END dataflow. Navabi and McGraw-Hill Inc. END FOR. binding will be done by configuration declaration • Hold data normally at z (High Impedance) CHAPTER 10 80 © 1999.par_central_processing_unit(dataflow). . Z. (a) CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow. END FOR.A TEST BENCH FOR THE PARWAN CPU CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral. (b) • Parwan tester applies data to Parwan buses • Component is declared. END behavior. END FOR.

.read memory into ir read_mem <= '1'. IF ready = '1' THEN databus_on_dbus <= '1'.A MORE REALISTIC PARWAN WHEN instr_fetch => ---------------------------------------2 -. • Memory and bus signaling for fetch state of controller • Signals provide for slower memory handshaking • Buss access signals are included CHAPTER 10 81 © 1999. ELSE next_state <= instr_fetch. IF grant = '1' THEN mar_on_adbus <= '1'. WHEN do_one_bytes => --------------------------------------3 .. Navabi and McGraw-Hill Inc. alu_a <= ‘1’. load_ir <= '1'. Z. END IF. next_state <= do_one_bytes. . END IF. increment_pc <= '1'. ELSE next_state <= instr_fetch.

We used one-to-one hardware correspondence so that no intelligent tools are required for the generation of hardware. A design carried to the stage where a dataflow model can be generated is only a few simple steps away from complete hardware realization. • End of Chapter 10 CHAPTER 10 82 © 1999. Navabi and McGraw-Hill Inc.SUMMARY This chapter showed how VHDL could be used to describe a system at the behavioral level before the system is even designed. . Z. We consider the design presented here a manual design. For completing the design of Parwan. flip-flop and gate interconnections should replace the component descriptions in the Parwan dataflow model. The use of VHDL as a top-down partitioning and verification tool has helped us form such a methodology for manual design. and at the dataflow level after major design decisions have been made. while the dataflow description can be used to verify the bussing and register structure of the design. The behavioral description aids designers as they verify their understanding of the problem. The methodology presented here can be applied to designs of much larger magnitude.

5.6.1 Cache Structure 11.CHAPTER 11 INTERFACE DESIGN AND MODELING 11.5.5.4 DMA Controller 11.4 Controller Modeling 11.5 DMA DEVICE 11. .6.2 Interface Through Arbiter 11.3 MEMORY SIGNALS 11. Z.4 SHARING SYSTEM BUSES 11.4.1 SYSTEM OVERVIEW 11.4.2 Wait Operation 11.2 Cache Interface 11.1 Arbitration Operation 11.3 Interface to CPU 11. Navabi and McGraw-Hill Inc.1 Serial Connection 11.2 CPU TIMING 11.3 Cache Structure Modeling 11.7 COMPLETE SYSTEM 11.5.6.3 Arbiter Model 11.6.8 SUMMARY CHAPTER 11 1 © 1999.4.6 CPU CACHE 11.

. Z. Navabi and McGraw-Hill Inc. CHAPTER 11 2 © 1999.SYSTEM OVERVIEW Arbiter Memory 4096*8 DMA Device Serial To Parallel serial_in DMA Controller cache memory & controller Address Decoder CPU • Bussing arrangement and system components.

Navabi and McGraw-Hill Inc.SYSTEM OVERVIEW 8 dat abu s 12 ad bu s rea gra rea w dy nt d_ rite me _m m em 8-bit CPU (Parwan) halted interrupt • CPU interface CHAPTER 11 3 © 1999. . Z.

Z. Navabi and McGraw-Hill Inc. .MEMORY SIGNALS clock read_mem grant ready adbus valid databus valid (a) • CPU read and write requests CHAPTER 11 4 © 1999.

Z. Navabi and McGraw-Hill Inc.MEMORY SIGNALS clock write_mem grant ready adbus valid databus valid (b) • CPU read and write requests CHAPTER 11 5 © 1999. .

. Z. Navabi and McGraw-Hill Inc.MEMORY SIGNALS cs rwbar Memory 4096*8 dat abu s • Memory interface adb us CHAPTER 11 6 © 1999.

Navabi and McGraw-Hill Inc. .MEMORY SIGNALS Memory Wait cs rwbar adbus databus valid • Memory read operation CHAPTER 11 7 © 1999. Z.

Z. . Navabi and McGraw-Hill Inc.SHARING SYSTEM BUSES memsel rwbar ready gra wr nt ite rea _req d_ ue req st ue st clock Bus Arbiter and Wait Handler skip_wait port 1 port 2 port 3 port 4 • Controlling bus access CHAPTER 11 8 © 1999.

Navabi and McGraw-Hill Inc. Z. .SHARING SYSTEM BUSES clock read_request i grant i memsel rwbar ready wait for bus access wait for device wait for wait state to complete • Bus grant for read operation CHAPTER 11 9 © 1999.

. END arbitrator. ready : OUT qit). grant (i) <= '1'. END behavioral. WAIT FOR clock_period. END IF. WAIT ON clock. rwbar. END PROCESS wait_cycle. ready <= '0'. • Arbiter VHDL description CHAPTER 11 10 © 1999. FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000". memsel <= '1'. write_request : IN nibble. END IF. END LOOP. ready <= '1'. skip_wait : IN qit. ELSE grant (i) <= '0'.SHARING SYSTEM BUSES ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1). grant : BUFFER nibble. rwbar <= read_request (i). clock. PORT (read_request. Z. IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'. END IF. -ARCHITECTURE behavioral OF arbitrator IS BEGIN -. memsel. Navabi and McGraw-Hill Inc. clock_period : TIME := 1 US).Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. END LOOP wait. EXIT. memsel <= '0'.

. Z. Navabi and McGraw-Hill Inc.DMA DEVICE Serial To Parallel serial pa ral lel _o ut ov err u fra n m_ err or 11 8 • Interface of serial-to-parallel converter CHAPTER 11 da tar ea rec dy eiv ed © 1999.

Z. Navabi and McGraw-Hill Inc. .DMA DEVICE 8 de v_ da ta er err de de ro or v_ v_ r2 1 rd rc y v read_mem write_mem databus grant DMA Controller addressbus ready status_write clk sel ect _re g status_read 4 • Interface of the DMA controller CHAPTER 11 12 © 1999.

Z.DMA DEVICE Address 1111:1111_1100 1111:1111_1101 1111:1111_1110 1111:1111_1111 DMA Registers Least 8 bits of starting address Most 4 bits of start Number of bytes to transfer done ie er2 er1 ie wr rd go • DMA Registers CHAPTER 11 13 © 1999. . Navabi and McGraw-Hill Inc.

DMA DEVICE 4 adbus Address Decoder active • Decoding for selecting DMA registers CHAPTER 11 14 © 1999. Z. Navabi and McGraw-Hill Inc. .

active : OUT qit. CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001". END CASE. WHEN "10" => selects <= "0100". ELSE active <= '0'. END PROCESS. WHEN "11" => selects <= "1000". Navabi and McGraw-Hill Inc. • VHDL description of DMA register address decoder CHAPTER 11 15 © 1999. Z.DMA DEVICE ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"). selects <= "0000". . END quad_adrdcd. -ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'. PORT (adbus : IN twelve. WHEN OTHERS => selects <= "0000". selects : OUT nibble). END behavioral. END IF. WHEN "01" => selects <= "0010".

Navabi and McGraw-Hill Inc. Z.DMA DEVICE S2P serial 8 de er err dev dev v_ ro r2 or1 _rdy _rcv da ta read_mem 8 write_mem databus grant ready 12 addressbus status_read status_write sel ect _re g adbus status_sel active • DMA device CHAPTER 11 16 © 1999. pa ral lel _o ut ov err u fra n m_ e da rror tar rec ead eiv y ed DMA 4 selects Decoder .

error2. ready. write_mem : OUT qit := '0'. status_wr : IN qit.DMA DEVICE ENTITY dma_controller IS PORT (clk : IN qit. -. --device signals error1. grant : IN qit. databus : INOUT byte := "ZZZZZZZZ". Navabi and McGraw-Hill Inc. dev_rdy : IN qit. -. dev_rcv : OUT qit.cpu signals select_reg : IN nibble. END dma_controller. . adbus : INOUT twelve := "ZZZZZZZZZZZZ".memory signals read_mem. Z. dev_data : IN byte ). status_rd. • DMA controller entity declaration CHAPTER 11 17 © 1999.

Navabi and McGraw-Hill Inc. ALIAS wr : qit IS rfile(3)(2). CHAPTER 11 18 © 1999. ALIAS rd : qit IS rfile(3)(1). Z. • Outline of DMA controller architecture. • DMA controller declarations. SIGNAL done : qit := '0'. ALIAS ie : qit IS rfile(3)(3).19) END behavioral. . TYPE r4 IS ARRAY (0 TO 3) OF byte.17) BEGIN “get serial. SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8).18) -“direct CPU communications” blocks (Figure 11. ALIAS go : qit IS rfile(3)(0).DMA DEVICE ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11. put parallel” process statement (Figure 11.

END LOOP writing. END IF. VARIABLE pntr : twelve. END IF. databus <= "ZZZZZZZZ". done <= '0'. VARIABLE numb : byte. BEGIN WAIT UNTIL go = '1'. . dev_rcv <= '1'. -. IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb .put to mem write_mem <= '1'. Z. adbus <= pntr. END PROCESS get_put. • DMA controller “get serial and put parallel” process CHAPTER 11 19 © 1999. WAIT UNTIL grant = '1'. WAIT UNTIL clk = '1'. numb := rfile(2).get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'. buff := dev_data. dev_rcv <= '0'. Navabi and McGraw-Hill Inc. pntr := rfile(1)(3 DOWNTO 0) & rfile(0). WAIT UNTIL clk = '0'. -.1.DMA DEVICE get_put : PROCESS VARIABLE buff : byte := zero_8. databus <= buff. done <= '1'. write_mem <= '0'. pntr := pntr + 1. WAIT UNTIL ready = '1'. adbus <= "ZZZZZZZZZZZZ".

ie. .DMA DEVICE cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ". r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1'. • DMA controller “direct CPU communications” blocks CHAPTER 11 20 © 1999. END BLOCK. error2. Navabi and McGraw-Hill Inc. END GENERATE cpu_direct. END BLOCK. error1). Z. r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus.

status_rd. END COMPONENT dma. dev_data : IN byte ). s2p_er2 : qit. dataready : BUFFER qit. frame_error : OUT qit. read_mem. END COMPONENT s2p. s2p_rdy. s2p_par). COMPONENT s2p IS GENERIC (bps : INTEGER := 9600). adbus : INOUT twelve. PORT (adbus : IN twelve. ready. -. grant : IN qit. status_sel : OUT qit. overrun. Navabi and McGraw-Hill Inc. serial_in : IN qit). parallel_out : BUFFER qit_vector (7 DOWNTO 0)). databus : INOUT byte := "ZZZZZZZZ". dev_rdy : IN qit. SIGNAL s2p_rdy. select_reg. ready. write_mem : OUT qit. Z. error1. grant. active : OUT qit. adbus : INOUT twelve. description for diagram of Figure 11. s2p_er2. select_reg : IN nibble. databus. COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"). END dma_serial_device. s2p_er1. selects : OUT nibble). SIGNAL cpu_mem_data : byte. • DMA serial device. s2p_er2. status_rd.memory signals read_mem. PORT (serial. s2p_er1. databus : INOUT byte := "ZZZZZZZZ". s2p_rcv. status_wr : IN qit. c2 : dcd PORT MAP (adbus. s2p_rcv. received : IN qit. dev_rcv : OUT qit. s2p_par). ready. error2.DMA DEVICE ENTITY dma_serial_device IS PORT (clk : IN qit. END structural. status_rd. status_wr : IN qit. read_mem.14 CHAPTER 11 21 © 1999. BEGIN c1 : dma PORT MAP (clk. . select_reg). -ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit. grant : IN qit. s2p_rdy. status_wr. SIGNAL cpu_mem_addr : twelve. status_sel. s2p_er1. SIGNAL select_reg : nibble. write_mem : OUT qit := '0'. END COMPONENT dcd. write_mem. c3 : s2p PORT MAP (serial_in. SIGNAL s2p_par : byte. s2p_rcv. adbus.

. Z. Navabi and McGraw-Hill Inc.CPU CACHE adbus valid set tag 5 To 32 tag line Way 0 Way 1 5 DCD LSB 7 MSB 8 8 v=1 & v=1 Match & Match 0 8 1 Hit • Cache Block Diagram CHAPTER 11 22 © 1999.

. Navabi and McGraw-Hill Inc.CPU CACHE adbus 5 7 MSB LSB 5 To 32 1: If a recent data was found in Way 0. 0: If a recent data was found in Way 1. DCD lru • The lru table CHAPTER 11 23 © 1999. Z.

Navabi and McGraw-Hill Inc. . Z.CPU CACHE me me m_ m_ ad dat bu abu s s rea gra wr read dy nt_ ite_ _m _m m m e em em em m cache da tab us ad bu s rea dy gra nt wr ite rea d 24 clk • Cache Interface CHAPTER 11 © 1999.

memory signals read_mem. write_mem : OUT qit. ready_mem : IN qit. grant_mem. grant. ready : OUT qit. -. Z.CPU CACHE ENTITY cache_system IS PORT (clk : IN qit. END cache_system. databus : INOUT byte := "ZZZZZZZZ". Navabi and McGraw-Hill Inc. mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ".cpu signals read. • Cache Entity Declaration CHAPTER 11 25 © 1999. -. adbus : INOUT twelve := "ZZZZZZZZZZZZ" ). . mem_databus : INOUT byte := "ZZZZZZZZ". write : IN qit.

END control_and_memory. . write data in cache and memory If miss: Find least recently used For write. Z.CPU CACHE ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read. write If hit: For read. • Outline of cache VHDL description CHAPTER 11 26 © 1999. pass data to CPU For write. read from memory and pass on to CPU Wait until (read OR write)=’1’. write data in cache and memory For read. END PROCESS. Navabi and McGraw-Hill Inc.

ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0). TYPE cache_type IS ARRAY (ways) OF each_cache. TYPE lru_type IS ARRAY (sets) OF ways. 0). VARIABLE hit : BOOLEAN. TYPE line IS ARRAY (0 TO 0) OF byte. Z. . data : line. ALIAS tag_value : tags IS adbus (11 DOWNTO 5).CPU CACHE SUBTYPE ways IS INTEGER RANGE 0 TO 1. tag : tags. Navabi and McGraw-Hill Inc. TYPE each_cache IS ARRAY (sets) OF entry. free : ways. VARIABLE w. SUBTYPE tags IS qit_vector (6 DOWNTO 0). SUBTYPE sets IS INTEGER RANGE 0 TO 31. • Controller local declarations CHAPTER 11 27 © 1999. CONSTANT nw : ww := (1. TYPE entry IS RECORD valid : BOOLEAN. END RECORD. SIGNAL cache : cache_type. SIGNAL lru : lru_type. • Cache structure declarations VARIABLE s : sets. TYPE ww IS ARRAY(ways) OF ways.

ELSIF write = '1' THEN cache(w)(s). mem_databus <= databus.valid <= TRUE. END IF.tag = tag_value AND cache(i)(s). mem_adbus <= "ZZZZZZZZZZZZ". Z.CPU CACHE grant <= '1'. END LOOP. WAIT UNTIL read = '0'. s := TO_INTEGER (set_value). WAIT UNTIL grant_mem = '1'. hit := FALSE. END IF. w := i. ready <= '0'. mem_adbus <= adbus. • Controller code for cache hit CHAPTER 11 28 © 1999. ready <= '0'.data(0) <= databus. Navabi and McGraw-Hill Inc. cache(w)(s). write_mem <= '1'. FOR i IN ways LOOP IF cache(i)(s).valid THEN hit := TRUE. mem_databus <= "ZZZZZZZZ". write_mem <= '0'. databus <= "ZZZZZZZZ". • Controller search in cache IF hit THEN lru (s) <= nw (w). . WAIT UNTIL write = '0'.data(0). WAIT UNTIL ready_mem = '1'. IF read = '1' THEN ready <= '1'. WAIT UNTIL clk = '0'. databus <= cache(w)(s). ready <= '1'.

ready <= '0'. .valid <= TRUE. mem_databus <= "ZZZZZZZZ". IF write = '1' THEN cache(free)(s). WAIT UNTIL ready_mem = '1'.tag <= tag_value.data(0) <= databus. mem_adbus <= adbus. lru (s) <= nw (lru (s)).valid <= TRUE.tag <= tag_value. cache(free)(s). cache(free)(s).miss free := lru (s).data(0) <= mem_databus. cache(free)(s). WAIT UNTIL grant_mem = '1'. Z. write_mem <= '1'. cache(free)(s). mem_adbus <= "ZZZZZZZZZZZZ". END IF. cache(free)(s). databus <= mem_databus. mem_databus <= databus. read_mem <= '0'. WAIT UNTIL grant_mem = '1'. ready <= '1'. WAIT UNTIL read = '0'.CPU CACHE ELSE -. ready <= '1'. • Controller code for cache miss CHAPTER 11 29 © 1999. Navabi and McGraw-Hill Inc. WAIT UNTIL write = '0'. ready <= '0'. ELSIF read = '1' THEN read_mem <= '1'. mem_adbus <= "ZZZZZZZZZZZZ". mem_adbus <= adbus. END IF. write_mem <= '0'. WAIT UNTIL ready_mem = '1'.

CPU CACHE Arbiter s2p Mem DMA Cache Decoder Parwan CPU • Board level interface CHAPTER 11 30 © 1999. Z. . Navabi and McGraw-Hill Inc.

grant_mem(1). mem : memory PORT MAP (cs. cs. csh_grant). Navabi and McGraw-Hill Inc. • Interface board VHDL description CHAPTER 11 31 © 1999. wr_req(0). wr_req(1). '0' AFTER 4500 NS. -ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1'. serial_in). halted. skip_wait. address). cpu : parwan PORT MAP (clock. cpu_write. rwbar. END system. csh_ready. . address. cpu_data. arb : arbitr GENERIC MAP ((OTHERS => 2). cpu_address). cpu_read. cpu_address. grant_mem(0). csh_grant. grant_mem. csh : cache PORT MAP (clock. ready. clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock. clock. srg : sergen PORT MAP (serial_in). interrupt. rwbar. ready). rd_req(1). skip_wait. data. rd_req(0). Z. dev : serial PORT MAP (clock. data. period) PORT MAP (rd_req. cpu_write. cpu_read. cpu_read. wr_req. data. cpu_data. cpu_write. ready. address.CPU CACHE ENTITY parwan_tester IS END parwan_tester. csh_ready.

Z. Language constructs for behavioral descriptions and timing and control were emphasized. We have illustrated how such handshaking schemes can be described in VHDL. • End of Chapter 11 CHAPTER 11 32 © 1999. The examples presented here. . show various forms of using wait statements in describing a design. The interface of the memory component is non-responsive. We illustrated the use of VHDL in a component level design environment. As opposed to Chapter 10 in which hardware details of a design were of concern. and how VHDL constructs can be used for handing communication between various devices. Several components with differing handshaking schemes were independently described.SUMMARY In this chapter we presented a board level design in VHDL. VHDL constructs used in this chapter were primarily at the behavioral level as discussed in Chapter 9. while other components such as the CPU and cache controller have two or three line fully-responsive or partially-responsive handshaking schemes. this chapter presented design at a higher level of abstraction. Navabi and McGraw-Hill Inc.

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