Vhdl Lecture Notes - Navabi | Vhdl | Hardware Description Language

Chapter 1

Hardware design environments

1.1 DIGITAL SYSTEM DESIGN PROCESS 1.1.1 Design Automation 1.2 The Art of Modeling 1.3 HARDWARE DESCRIPTION LANGUAGES 1.3.1 A Language for Behavioral Descriptions 1.3.2 A Language for Describing Flow of Data 1.3.3 A Language for Describing Netlists 1.4 HARDWARE SIMULATION 1.4.1 Oblivious Simulation 1.4.2 Event Driven Simulation 1.5 HARDWARE SYNTHESIS TEST APPLICATIONS 1.6 LEVELS OF ABSTRACTION 1.7 SUMMARY

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© 1999, Z. Navabi and McGraw-Hill Inc.

A digital system design process

Design Idea

Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing

Chip or Board

• Top-down design process • Starting with a design idea • Generating a chip or board

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© 1999, Z. Navabi and McGraw-Hill Inc.

Result of the data path design phase.

DATA

CONTROL

REG1

REG2 Procedure for Control of Movement of Data Between Registers and Buses.

...

MAIN LOGIC UNIT

REG3

LOGIC

...

• Dataflow description • Control Data partitioning

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© 1999, Z. Navabi and McGraw-Hill Inc.

An ISPS example, a simple processor.

mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** {tc} MAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END

• Behavioral Example • Only describing functionality

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© 1999, Z. Navabi and McGraw-Hill Inc.

An AHPL example, a sequential multiplier.

AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2); 1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7]; extra <= 4$0; => ( ^dataready, dataready ) / (1, 2). 2 busy <= \1\; => ( ^ac1[3], ac1[3] ) / (4, 3). 3 extra <= ADD[1:4] (extra; ac2). 4 extra, ac1 <= \0\, extra, ac1[0:2]; count <= INC(count); => ( ^(&/count), (&/count) ) / (2, 5). 5 result = extra, ac1; done = \1\; busy <= \0\; => (1). ENDSEQUENCE CONTROLRESET(1). END.

• Dataflow description • Describing clock control timing • AHPL, A Hardware Programming Language

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© 1999, Z. Navabi and McGraw-Hill Inc.

Full-adder, logical diagram and Verilog code.
a b c g1 w1 g5 s

g2 g3 g4 w3

w2

g6 w4

co

`timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule

• Gate level structural description • Describes gate level timing • Graphical and language based descriptions
CHAPTER 1 6 © 1999, Z. Navabi and McGraw-Hill Inc.

Hardware simulation.

Hardware Description (Model)

Simulation Hardware Model

Simulation Engine Component Library (Models)

Simulation Results (Output)

Test Data (Stimuli)

• Hardware simulation process • Component models, unit model form hardware model • Testbench may provide test data

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Verifying each design stage.

Design Idea SIMULATION TOOLS Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing Product Sample. Chip or Board Final Testing Device Simulator Gate Level Simulator Dataflow Simulator Behavioral Simulator

• Simulate at each step • Simulate to verify translation into lower level • Simulation cost increases at lower levels

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© 1999, Z. Navabi and McGraw-Hill Inc.

Simulating an exclusive-OR

a

1 3

5

7 4 b 2 6

z

t a b

0

1

2

3

4

5

6

7

8

9

0

• Simulating an XOR • Apply data at given time intervals or • Apply data as events occur

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Oblivious simulation.

GATE 1 2 3 4 5 6 7

FUNCTION Input Input NOT NOT AND AND OR

INPUT 1 a b 2 1 1 4 5

INPUT 2 ----3 2 6

VALUE 0 0 1 1 0 0 0

• Table representation • Simulate until no changes are made • Record values at table entries

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© 1999, Z. Navabi and McGraw-Hill Inc.

Event driven simulation.

1 a Inp 0

3 -

5 0 AND 0

NOT

OR 2 b Inp 0 NOT 0 AND 0 4 6

0

Legend: In1 In2 Fnc Out In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value

• Linked list representation • Simulate links with input events • Record values at node entries

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.. .. Navabi and McGraw-Hill Inc. Design Idea Behavioral Design SYNTHESIS TOOLS 1 4 6 5 3 Physical Design Transistor List. Z.. most commercial tools are 2 CHAPTER 1 12 © 1999. Data Path Design Bus & Register Structure Logic Design Chip or Board • Synthesis • Transformation from one level to another • Ideal is 6. . Pseudo Code.Categories of synthesis tools. Manufacturing 2 Flow Graph. Layout..

Synthesis process. Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives Synthesis Engine Logic Optimization Binding Synthesized Hardware (Netlist) • Hardware description and directives are tool inputs • Three synthesis stages • Layout or netlist is generated CHAPTER 1 13 © 1999. Navabi and McGraw-Hill Inc. . Z.

Z. d <= a + b. Navabi and McGraw-Hill Inc. . a b a ADDER x b y ADDER c d c • Input description affects synthesis results • Explicit specification of resource sharing • Sharing without and with extra overhead CHAPTER 1 14 © 1999.Resource sharing. c <= x + y. c <= a + b. c <= a + b.

.1 AHPL 2. Navabi and McGraw-Hill Inc.2 Support for Design Hierarchy 2.1 General Features 2.2.4 Sequential Statement 2.2.3.1 VHDL INITIATION 2.2.3.3.2.3.2.5 Generic Design 2.3.8 ZEUS 2.3.4 IDL 2.2 CDL 2.3.2.7 Use of Subprograms 2.5 ISPS 2.3.3 Library Support 2.7 TI-HDL 2.4 THE VHDL LANGUAGE 2.Chapter 2 VHDL Background 2.2 EXISTING LANGUAGES 2.3 CONLAN 2.2.5 SUMMARY CHAPTER 2 1 © 1999.8 Timing Control 2. Z.3 VHDL REQUIREMENTS 2.2.9 Structural Specification 2.6 TEGAS 2.3.6 Type Declaration and Usage 2.

. Z.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs • Part of VHSIC program CHAPTER 2 2 © 1999. Navabi and McGraw-Hill Inc.

TI.2 was released to IEEE ITAR removed from software • May 1985 : Standard VHDL 1076/A • December 1987 : VHDL 1076-1987 became IEEE standard • 1993 : VHDL 1076-1993 was approved CHAPTER 2 3 © 1999. Intermetrics ITAR restrictions removed from language • 1984 IBM.0 was released Software development started • 1985 : VHDL 7. Intermetrics : VHDL 2. TI. Z. Navabi and McGraw-Hill Inc.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions • 1983 DoD : Requirements were established Contract was awarded to IBM.0 was defined • December 1984 : VHDL 6. .

. Z. Navabi and McGraw-Hill Inc.Languages reviewed • AHPL • CDL • CONLAN • IDL • ISPS • TEGAS • TI-HDL • ZEUS : A Hardware Programming Language : Computer Design Language : CONsensus LANguage : Interactive Design Language : Instruction Set Processor Specification : TEst Generation And Simulation : TI Hardware Description Language : An HDL by GE corpration CHAPTER 2 4 © 1999.

Automatic hardware • Design Hierarchy Multi-level description Partitioning • Library Support Standard Packages Cell based design • Sequential Statements Behavioral software-like constructs CHAPTER 2 5 © 1999. Navabi and McGraw-Hill Inc. High level design. Test. Synthesis. . Simulation.VHDL Requirements • General Features Documentation. Z.

VHDL Requirements • Generic Design Binding to specific libraries • Type Declaration Strongly typed language • Subprograms • Timing Delays. concurrency • Structural Specification Wiring components CHAPTER 2 6 © 1999. Z. . Navabi and McGraw-Hill Inc.

. Z.VHDL Requirements CPU STACK ALU MUX COUNTER ALU BIT n BIT n-1 BIT 0 ALU_BIT ADDER MUX LOGIC MUX AND OR NOT • Use various levels of abstraction for defining a system • Upper level systems are partitioned into lower CHAPTER 2 7 © 1999. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z.Example for hierarchical partitioning. . CPU STA CK A LU M UX COUNTER AL U BI T n BIT n-1 BIT 0 AL U_BI T A DDER M UX L OGIC M UX AND OR NOT • Recursive partitioning • Simple components as terminals CHAPTER 2 8 © 1999.

Navabi and McGraw-Hill Inc. Z.3 VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools VHDL Input Analyzer Lib. . 1 .2 Design Libraries Library Management Library Environment • VHDL defines library usage • Tools define library management CHAPTER 2 9 © 1999.An example VHDL environment. LIBRARY SYSTEM .

2 TOP-DOWN DESIGN 3.3.6 VHDL OPERATORS 3.2 Packages 3.3 Design Scenario 3.1 Design to Perform 3.8 SUMMARY CHAPTER 3 1 © 1999.3.2 Setting The Stage 3. .1.1.1 Describing Components 3.7 CONVENTIONS AND SYNTAX 3.3.4 SUBPROGRAMS 3.Chapter 3 Design Methodology Based on VHDL 3.5 CONTROLLER DESCRIPTION 3. Navabi and McGraw-Hill Inc.4 Final Act 3.3.3 TOP-DOWN DESIGN WITH VHDL 3. Z.1.5 Real World 3.2.1 ELEMENTS OF VHDL 3.3.3 Libraries and Binding 3.1 Verification 3.

END identifier. END component_name. Z. ENTITY component_name IS input and output ports. physical and other parameters. Navabi and McGraw-Hill Inc. ARCHITECTURE identifier OF component_name IS declarations. . BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters. CHAPTER 3 2 © 1999.Interface and architectural specifications.

.. .. ARCHITECTURE dataflow OF component_i IS . other ARCHITECTURES OF component_i . ARCHITECTURE structural OF component_i IS . ) . . ENTITY component_i IS PORT (. Z. ..Multiple architectural specifications.... Navabi and McGraw-Hill Inc. CHAPTER 3 3 © 1999... ARCHITECTURE behavioral OF component_i IS . ..... .. .

sub-program declasrations. Z. PACKAGE BODY package_name IS type definitions. PACKAGE package_name IS component declarations. sub-programs. END package_name. . END package_name.Packages. Navabi and McGraw-Hill Inc. CHAPTER 3 4 © 1999.

Z. Navabi and McGraw-Hill Inc. END CONFIGURATION. binding components of a library to subcomponents. . LIBRARY library_name. CHAPTER 3 5 © 1999.Design binding. CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. specifying parameters of a design.

Z. END IF.Recursive partition procedure. Navabi and McGraw-Hill Inc. . CHAPTER 3 6 © 1999. Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i). END FOR. END Partition.

Z. . SUD Design Implementation SSC1 SSC2 SSC3 SSC4 SSC31 .. CHAPTER 3 7 © 1999.Top-down design. Navabi and McGraw-Hill Inc. bottom-up implementation.. SSC3n SSC41 SSC42 SSC311 SSC312 SSC3n1 SSC3n2 SUD: System Under Design SSC : System Sub-Component Shaded areas designate sub-componts with hardware implementation.

Z. Navabi and McGraw-Hill Inc. . Behavioral Model are mp Co SUD SSC1 SSC2 SSC3 SSC4 Interconnection of Behavioral Models CHAPTER 3 8 © 1999.Verifying the first level of partitioning.

Navabi and McGraw-Hill Inc. Z. Behavioral Model are omp C SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model CHAPTER 3 9 © 1999.Verifying hardware implementation. .

SSC3n SSC41 SSC42 SSC311 SSC312 CHAPTER 3 10 © 1999.Verifying the final design.. Behavioral Model e par Com SUD SSC1 SSC2 SSC3 SSC4 Har dwa re M odel SSC31 .. . Navabi and McGraw-Hill Inc. Z.

SSC3n1 SSC3n2 Hardware Model CHAPTER 3 11 © 1999..Verifying hardware implementation of SSC3. Navabi and McGraw-Hill Inc. . SSC3n SSC311 SSC312 ... Behavioral Model SSC3 Co m pa re SSC31 . Z..

an alternative to the setup of Figure 3. Navabi and McGraw-Hill Inc.9. CHAPTER 3 12 © 1999.Verifying the final design. . Z. p Com are SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model SSC41 SSC42 Verifying the final design.

result ready CHAPTER 3 13 © 1999. a b start clock Synchronously add data on a and b put result on result.Serial adder. Navabi and McGraw-Hill Inc. . Z.

Z. 1R S1 1D Z 1D C1 Q _ 1D (a) Multiplexer (b) Flipflop CHAPTER 3 14 © 1999. . Navabi and McGraw-Hill Inc.Available library elements.

CHAPTER 3 15 © 1999. ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). data1. Navabi and McGraw-Hill Inc. PORT (sel. END mux2_1. -ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay. VHDL model of the multiplexer library element.Multiplexer library element. z : OUT BIT). data0 : IN BIT. Z. END dataflow. .

Z. CHAPTER 3 16 © 1999.Dataflow descriptions. . Busb Reg File Reg1 Alu Controller Reg2 Busa Dataflow descriptions. Navabi and McGraw-Hill Inc.

ENTITY flop IS GENERIC (td_reset. qout : BUFFER BIT := '0'). CHAPTER 3 17 © 1999. END flop. clk : IN BIT. VHDL model of the flip-flop library element. .Flip-flop library element. td_in : TIME := 8 NS). END behavioral. -ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset. PORT (reset. din. Z. END IF. END IF. ELSE qout <= din AFTER td_in. END PROCESS. Navabi and McGraw-Hill Inc.

Receive FOR all data : Process data : Queue data : END FOR. Navabi and McGraw-Hill Inc. CHAPTER 3 18 © 1999. . Behavioral descriptions. Z. . Valid ? Transmit . .Behavioral descriptions.

END IF. PORT (reset. counter. Z.Divide by 8. Divide by 8. -ARCHITECTURE behavioral OF counter IS BEGIN PROCESS (clk) VARIABLE count : INTEGER := limit. END IF. counting : OUT BIT := '0'). ELSE counting <= '1' AFTER td_cnt. CHAPTER 3 19 © 1999. END PROCESS. ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS). END behavioral. Navabi and McGraw-Hill Inc. . ELSE IF count < limit THEN count := count + 1. END IF. BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0. counter. CONSTANT limit : INTEGER := 8. END IF. IF count = limit THEN counting <= '0' AFTER td_cnt. clk : IN BIT. END counter.

. VHDL Boolean p r e d e s i g n e d layouts Synthesize l i b r a r y mux2-1 Count flop CMOS layout CHAPTER 3 20 © 1999. Z.Design stage setting. Navabi and McGraw-Hill Inc.

start. . Navabi and McGraw-Hill Inc. Serial adder behavioral description. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. CHAPTER 3 21 © 1999. carry : BIT. carry := (a AND b) OR (a AND carry) OR (b AND carry). Z. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) VARIABLE count : INTEGER := 8. ELSE ready <= '0'. END IF. IF count = 8 THEN ready <= '1'. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END PROCESS. END IF. result <= sum & result (7 DOWNTO 1). END behavioral. END IF. ready : OUT BIT. b. END serial_adder.Serial adder behavioral description. sum := a XOR b XOR carry. carry := '0'. ENTITY serial_adder IS PORT (a. VARIABLE sum. ELSE IF count < 8 THEN count := count + 1. clock : IN BIT. END IF.

VHDL simulation results. CHAPTER 3 22 © 1999. Z. . Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc.Partial code of serail_adder. carry := (a AND b) OR (a AND carry) OR (b AND carry ). sum := a XOR b XOR carry. CHAPTER 3 23 © 1999. END IF. ELSE IF count < 8 THEN count := count + 1. Z. . result <= sum & result (7 DOWNTO 1).

Z. counting counter serial_sum en si a b Adder carry_out Flop result Shift Regiser carry_in clock CHAPTER 3 24 © 1999.General layout of serial_adder. Navabi and McGraw-Hill Inc. .

. Navabi and McGraw-Hill Inc.First level of partitioning. serial_adder full_adder flip_flop shifter counter CHAPTER 3 25 © 1999. Z.

-ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin. . Z.Full_adder description. CHAPTER 3 26 © 1999. sum. cout : OUT BIT). cin : IN BIT. END fulladder. END behavioral. ENTITY fulladder IS PORT (a. cout <= (a AND b) OR (a AND cin) OR (b AND cin). b. Navabi and McGraw-Hill Inc.

END BLOCK. CHAPTER 3 27 © 1999. clk : IN BIT. enable. ENTITY shifter IS PORT (sin. reset. Z. Navabi and McGraw-Hill Inc. . END shifter. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). END dataflow. -ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED.Shifter VHDL description.

serial_adder full_adder flop shifter counter CHAPTER 3 28 © 1999. Z. .Completed parts of first partitioning. Navabi and McGraw-Hill Inc.

clk : IN BIT. u2 : flop PORT MAP (start. b. PORT (reset. td_in : TIME := 8 NS). enable. start. COMPONENT shifter IS PORT (sin. b. reset. END COMPONENT. counting : BIT. start. ready : OUT BIT. clk : IN BIT. clock. serial_sum. counting). u3 : counter PORT MAP (start. u4 : shifter PORT MAP (serial_sum. qout : BUFFER BIT := '0'). .Structural description of serial_adder. clock : IN BIT. cout : OUT BIT). Z. END structural. carry_out. BEGIN u1 : fulladder PORT MAP (a. u5 : ready <= NOT counting. END COMPONENT. END serial_adder. -ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS). COMPONENT fulladder IS PORT (a. cin : IN BIT. CHAPTER 3 29 © 1999. b. carry_out. clock. carry_out). carry_in). carry_in. -SIGNAL serial_sum. END COMPONENT. din. COMPONENT flop IS GENERIC (td_reset. clock. ENTITY serial_adder IS PORT (a. counting. Navabi and McGraw-Hill Inc. result). sum. parout : BUFFER BIT_VECTOR(7 DOWNTO 0)). counting : OUT BIT := '0'). carry_in. PORT (reset. clk : IN BIT. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END COMPONENT.

. Navabi and McGraw-Hill Inc.Signal mapping for fulladder instantiation. Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out a b cin sum count Signals in the interface of fulladder CHAPTER 3 30 © 1999. Z.

u2 : flop PORT MAP (start. counting : BIT. CHAPTER 3 31 © 1999. serial_sum. clock. b.Interconnecting ports. carry_out ). COMPONENT flop IS GENERIC (td_reset. Navabi and McGraw-Hill Inc. BEGIN u1 : fulladder PORT MAP (a. carry_out . din . carry_in. b. Z. carry_out. PORT (reset. END COMPONENT. sum. . carry_in. qout : BUFFER BIT := '0'). END COMPONENT. cout : OUT BIT). td_in : TIME := 8 NS). carry_in). COMPONENT fulladder IS PORT (a. -SIGNAL serial_sum. clk : IN BIT. cin : IN BIT.

. Z. shifter der_flop der_flop der_flop der_flop der_flop der_flop der_flop der_flop CHAPTER 3 32 © 1999. . Navabi and McGraw-Hill Inc.Partitioning shifter. . .

END IF. CHAPTER 3 33 © 1999. END IF. END der_flop. ELSE IF enable = '1' THEN qout <= din. END behavioral. qout : OUT BIT := '0'). clk : IN BIT. enable. . reset. Navabi and McGraw-Hill Inc. END PROCESS. ENTITY der_flop IS PORT (din. -ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'. END IF.Behavioral model of der_flop. Z.

b0 : der_flop PORT MAP (parout(1). reset. clk. reset. reset. parout(2)). Z. enable. ENTITY shifter IS PORT (sin. reset. b3 : der_flop PORT MAP (parout(4). . enable. parout(5)). parout(4)). END shifter. enable. parout(7)). clk. BEGIN b7 : der_flop PORT MAP ( sin. END COMPONENT. clk. enable. b4 : der_flop PORT MAP (parout(5). reset. parout(6)). b2 : der_flop PORT MAP (parout(3). reset. b1 : der_flop PORT MAP (parout(2). clk. enable. clk : IN BIT. -ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din. reset. b5 : der_flop PORT MAP (parout(6). parout(3)). clk : IN BIT. parout(1)).Structural description of shifter. clk. enable. enable. clk. reset. qout : BUFFER BIT := '0'). clk. enable. b6 : der_flop PORT MAP (parout(7). enable. CHAPTER 3 34 © 1999. clk. enable. reset. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). Navabi and McGraw-Hill Inc. parout(0)). END structural. reset.

enable reset din S1 1D qout 1R 1D C1 Q dff_in _ 1D clock CHAPTER 3 35 © 1999.Hardware realization of der_flop. Navabi and McGraw-Hill Inc. . Z.

.Partitioning der_flop. Navabi and McGraw-Hill Inc. der_flop mux2_1 flop CHAPTER 3 36 © 1999. Z.

clk : IN BIT. clk : IN BIT. ENTITY der_flop IS PORT (din. qout : BUFFER BIT). clk. reset. data0 : IN BIT. ff : flop PORT MAP (reset. z : OUT BIT). END behavioral. BEGIN mx : mux2_1 PORT MAP (enable. din. PORT (sel. Navabi and McGraw-Hill Inc. . END der_flop. qout : BUFFER BIT := '0'). PORT (reset. td_in : TIME := 8 NS). qout). enable. dff_in. END COMPONENT. dff_in). SIGNAL dff_in : BIT. data1.Structural description of der_flop. qout. din. -ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset. END COMPONENT. Z. CHAPTER 3 37 © 1999. COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS).

CHAPTER 3 38 © 1999. Z. . serial-adder fulladder flop shifter counter der-flop der-flop . mux2-1 flop . .Complete design of seraial_adder. . . . . . Navabi and McGraw-Hill Inc. der-flop .

.. . reset Counter counting . a b Fulladder serial-sum 1 s1 1 1R Q 1D 1R Q 1D 1 s1 1 . Navabi and McGraw-Hill Inc.Final Design.. . . 1 1R Q 1D C1 carry_in 1R 1D C1 C1 C1 Q carry_out clk . . . Z. CHAPTER 3 39 © 1999. 1 s1 . .

VARIABLE sum. sum := a XOR b XOR carry. result <= sum & result (7 DOWNTO 1). CHAPTER 3 40 © 1999. IF count = 8 THEN ready <= '1'. ELSE IF count < 8 THEN count := count + 1. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END serial_adder. END behavioral. ELSE ready <= '0'. start. VARIABLE count : CNT8 := 8. Navabi and McGraw-Hill Inc. b. END PROCESS. END IF.Synthesizable serial adder. . -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8. END IF. END IF. carry := '0'. ENTITY serial_adder IS PORT (a. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. carry : BIT. ready : OUT BIT. Z. clock : IN BIT. END IF. carry := (a AND b) OR (a AND carry) OR (b AND carry).

. Navabi and McGraw-Hill Inc. Z. CHAPTER 3 41 © 1999.FPGA layout of serial_adder.

.. TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT. CHAPTER 3 42 © 1999. oi := result.Type conversion procedure. BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i. Z. oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0. END LOOP.. PROCEDURE byte_to_integer (ib : IN byte. . Navabi and McGraw-Hill Inc. END IF. END byte_to_integer.

Z. CHAPTER 3 43 © 1999. BEGIN sc(1) := a XOR b XOR c. c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0). FUNCTION fadd (a. b. . Navabi and McGraw-Hill Inc. sc(0) := (a AND b) OR (a AND c) OR (b AND c). END. RETURN sc.The fadd (full adder) function.

cin). END fulladder. . END behavioral. Z. CHAPTER 3 44 © 1999. cout : OUT BIT). sum. ENTITY fulladder IS PORT (a. cin : IN BIT. b. Navabi and McGraw-Hill Inc. b. -ARCHITECTURE behavioral OF fulladder IS BEGIN (sum. cout) <= fadd (a.fulladder using fadd.

. . x1 x= . . z<= .. zn z<= . . x= .. . . . xn z<= . . .. . .General outline of a controller. clock CHAPTER 3 45 © 1999. z1 .. Navabi and McGraw-Hill Inc. . Z.

Navabi and McGraw-Hill Inc. .Moore machine description. Z. IF 110 sequence is detected on x THEN z gets '1' x ELSE z gets '0' END. z clk CHAPTER 3 46 © 1999.

0 1 1 reset 0 0 0 got1 0 1 got11 0 1 0 got110 1 CHAPTER 3 47 © 1999.Sequence detector state machine. Z. Navabi and McGraw-Hill Inc. .

WHEN got110 => IF x = ‘1’ THEN current <= got1. END moore_110_detector. ELSE current <= reset. z : OUT BIT). -ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset. . END IF. END IF. Z. got11. WHEN got1 => IF x = ‘1’ THEN current <= got11. WHEN got11 => IF x = ‘1’ THEN current <= got11. clk : IN BIT . ELSE current <= got110. Navabi and McGraw-Hill Inc. END IF. CHAPTER 3 48 © 1999. END CASE. END behavioral. got1.VHDL Description of 110 detector. ENTITY moore_110_detector IS PORT (x. END PROCESS. SIGNAL current : state := reset. END IF. BEGIN PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1. z <= ‘1’ WHEN current = got110 ELSE ‘0’. got110). ELSE current <= reset. ELSE current <= reset. END IF.

Navabi and McGraw-Hill Inc.State transition and corresponding VHDL code. WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset. ... Z. END IF. .. CHAPTER 3 49 © 1999. 1 reset 0 0 got1 0 got11 0 ..

. Navabi and McGraw-Hill Inc. Z.VHDL operators. Operators AND NAND XOR = < > SLL SLA ROL + OR NOR XNOR /= <= >= SRL SRA ROR & Operand Type BIT or BOOLEAN All Types Left: BIT or BOOLEAN Vector Right: INTEGER Numeric Array or Array Element Numeric Result Type BIT or BOOLEAN BOOLEAN LOGICAL RELATIONAL SHIFT BOOLEAN ADDING Same Type SIGN + - Same Type * MULTIPLYING MOD / INTEGER. REAL Same Type REM INTEGER Same Type ABS MISCELLENEOUS ** Numeric Left: Numeric Right: Integer Same Type Same as Left CHAPTER 3 50 © 1999.

Syntax details of the architecture body. . FE 5 S b< N TaA T R5N . = O FE S c <= a AFTER 10 NS. IT B G E IN a <= '1' A T R1 N . b. A C I E T R d m O e a p IS R HT C U E e o F z m le S IGNAL a. E Dd m . Navabi and McGraw-Hill Inc. N e o architecture declarative_part architecture body architecture statem n e t_part CHAPTER 3 51 © 1999. Z. c : B := '0'.

4.1 Timing 4.5 SUMMARY CHAPTER 4 1 © 1999.1.3 Delta Delay 4. Z.1 Inertial Delay Mechanism 4.2 OBJECTS AND CLASSES 4.3.2 Events and Transactions 4. .1 Concurrent Assignments 4. Navabi and McGraw-Hill Inc.2 Concurrency 4.3.4 Sequential Placements of Transactions 4.3 Comparing Inertial and Transport 4.1 CHARACTERIZING HARDWARE LANGUAGES 4.Basic Concepts in VHDL 4.3 SIGNAL ASSIGNMENTS 4.1.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS 4.4.4.3 Modeling Hardware 4.4.3.2 Transport Delay Mechanism 4.1.

. Navabi and McGraw-Hill Inc. • What happens in a real hardware • Must be able to model properly CHAPTER 4 2 © 1999. Z.Value transfer through wires.

. b <= x AFTER 3*unit_delay.Value transfer through wires. Navabi and McGraw-Hill Inc. b := x. a := x. Z. • In one case immediate assignemnts are done • In another case scheduling is done CHAPTER 4 3 © 1999. a <= x AFTER 4*unit_delay.

Describing sub-components. . S A B C • Hardware description requires concurrent constructs • Concurrent bodies can be described behaviorally or at the dataflow level CHAPTER 4 4 © 1999. Navabi and McGraw-Hill Inc. Z.

Z.A VHDL concurrent body • A VHDL concurrent body • Statements are executed when events occur CHAPTER 4 5 © 1999. . Navabi and McGraw-Hill Inc.

. .. PROCESS . . IF THEN ELSE .. BEGIN . .. Z.A VHDL sequential body ARCHITECTURE sequential .. . Navabi and McGraw-Hill Inc... FOR LOOP . . END ARCHITECTURE • A VHDL sequential body • Statements are executed when program flow reaches them CHAPTER 4 6 © 1999. . . END PROCESS . BEGIN ..

Z. Navabi and McGraw-Hill Inc. .Illustrating timing and concurrency. a b g2 x z g4 c g1 w g3 y • Four concurrent gates • Each has a delay of 12 ns • Change in inputs may result in in output hazards CHAPTER 4 7 © 1999.

Gates reacting to changes. g1 g2 g3 g4 R a tin e c g R a tin e c g R a tin e c g R a t e c ing R a tin e c g 0 12 24 36 Nanosecond • a changes from ‘1’ to ‘0’ • A change in the a input results in domino changes each 12 ns apart • No more events occur when output is reached CHAPTER 4 8 © 1999. Z. . Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc.a b c w x y z 0 12 24 36 Nanosecond • Timing diagram resulting from input a changing from ‘1’ to ‘0’ at time zero • A glitch appears on the output • Must model hardware to imitate this behavior • Requires timing and concurrency in the language CHAPTER 4 9 © 1999. . Z.

..... b_signal y_signal <= .Objects and Classes del1_constant del2_constant concurrent_body_1 sequential_body_1 a_signal a_variable := . loop_variable_i .. .... w_signal <= .. u_signal concurrent_body_2 x_signal <= . Navabi and McGraw-Hill Inc.. y_signal z_signal <= .... z_signal • Objects and classes in sequential and concurrent bodies • Foundation for modeling timing and concurrency are signals • Variables are used as software variables CHAPTER 4 10 © 1999. w_signal v_signal concurrent_body_3 u_signal <= local_constant v_signal <= . x_signal y_signal <= ... Z.

Z. Navabi and McGraw-Hill Inc. .Objects and Classes Using Objects In VHDL O B J E C T Signal Variable Constant File BODY Declare YES NO YES YES Concurrent Assign to YES NO --Use YES YES YES YES Declare NO YES YES YES Sequential Assign to YES YES --Use YES YES YES YES • Objects in VHDL bodies • Cannot declare signals in sequential bodies • Variable assignments are only done in sequential bodies CHAPTER 4 11 © 1999.

‘1’ AFTER 14 NS. -. ‘1’ AFTER 41 NS. diff23 : BIT. ‘1’ AFTER 52 NS. Navabi and McGraw-Hill Inc.This is a comment BEGIN -. ‘0’ AFTER 27 NS. Reject and Transport • Inertial: rejects anything less than its delay • Reject: rejects anything less than or equal to its reject • Transport: does not reject CHAPTER 4 12 © 1999. SIGNAL target1. target3 : BIT.Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS. diff13. ‘1’ AFTER 33 NS.Illustrating inertial delay target1 <= waveform AFTER 5 NS. ‘0’ AFTER 58 NS. -. . ‘0’ AFTER 18 NS. ‘0’ AFTER 35 NS. ‘0’ AFTER 85 NS. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. ‘1’ AFTER 24 NS.Comparing targets diff12 <= target1 XOR target2. • VHDL description for the demonstration of delay mechanisms • Example shows several concurrent statements • Inertial. target2.Creating waveform waveform <= ‘1’ AFTER 03 NS. ‘0’ AFTER 08 NS. -.Delay Mechanisms ENTITY example IS END ENTITY. ‘0’ AFTER 77 NS. ‘1’ AFTER 71 NS. END delay. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. ‘1’ AFTER 62 NS. -. diff13 <= target1 XOR target3. SIGNAL diff12. ‘1’ AFTER 79 NS. ‘0’ AFTER 47 NS. Z. diff23 <= target2 XOR target3. ‘0’ AFTER 68 NS.

Navabi and McGraw-Hill Inc. . Z.Delay Mechanisms R Target 1 or Target 2 C • The RC delay is best represented by inertial delay mechanism • This is a simple version of Inertial • For more accurate modeling Reject can be used CHAPTER 4 13 © 1999.

Z. . Navabi and McGraw-Hill Inc.Delay Mechanisms 5 6 4 6 3 6 2 6 6 5 6 4 6 3 6 2 6 • Illustrating differences between delay mechanism in VHDL • Positive and negative pulses appear on the LHS CHAPTER 4 14 © 1999.

z <= x OR y AFTER 12 NS. • VHDL description for the gate level circuit for the demonstration of timing and concurrency • Four concurrent statements model gates of the circuit • Events of the RHS cause evaluation and scheduling • A scheduled value may or may not appear on the LHS • A scheduled value is a transaction on the driver of the LHS signal CHAPTER 4 15 © 1999. END figure_5_example. . c : IN BIT. y <= c AND w AFTER 12 NS. x. BEGIN w <= NOT a AFTER 12 NS. x <= a AND b AFTER 12 NS. ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w.Concurrency ENTITY figure_5_example IS PORT (a. b. END concurrent. z : OUT BIT). y : BIT. Navabi and McGraw-Hill Inc. Z.

Concurrency Resolution Function Multiple Driving Values Signal Value • A signal may have more than one driver • Resolving a single value from multiple driving values • Each driver has its own timing • Independent handling of all drivers • A driving value that is current contributes to the resolution function CHAPTER 4 16 © 1999. . Navabi and McGraw-Hill Inc. Z.

d) d-t0 tri = (v. . Z.Events and Transactions transaction time component d tri = (v. 0) now • A transaction. Navabi and McGraw-Hill Inc. d-t ) 0 EXPIRED 0 t t 0 t1 d tri = (v. from being created to being expired • A transaction that expires generates a current driving value • This value contributes to the resolution function CHAPTER 4 17 © 1999.

Z. c <= a AFTER 10 NS.Events and Transactions ARCHITECTURE demo OF example IS SIGNAL a. BEGIN a <= '1' AFTER 15 NS. b <= NOT a AFTER 5 NS. Navabi and McGraw-Hill Inc. b. • A simple description for illustrating events and transactions • Transactions are scheduled on the 3 LHS signals • Order is not significant • Initial transaction are placed on all 3 signals CHAPTER 4 18 © 1999. . c : BIT := '0'. END demo.

Events and Transactions a 0 0 0 b c 0 5 10 (a) 15 20 25 NS Transactions W hen They Are Placed on Signals (1. 10) on c 0 5 10 (b) 15 20 25 NS Transactions At 5 NS Intervals a c b a c a c b c 0 5 10 (c) 15 20 25 NS Path Of Transactions To Expiration a c b b NS c 0 5 10 15 20 25 • Events and transactions (d) CHAPTER 4 19 © 1999. 10) on c (1. 15) on a (1. Navabi and McGraw-Hill Inc. . Z. 05) on b (0. 05) on b (0.

END ENTITY. b : IN BIT. • Demonstrating need for delta delay • A “hidden” delay exists between z and z_bar • Delta delay makes us believe that they take place at the same real time • The hidden delay is Delta which is not real-time CHAPTER 4 20 © 1999. Z. Navabi and McGraw-Hill Inc. z. -ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z. z <= a AND b AFTER 10 NS. zbar : BUFFER BIT). END delta. .Delta Delay ENTITY timing IS PORT (a.

y : BIT := '0'.Delta Delay ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w. x <= a AND b. BEGIN y <= c AND w. • VHDL description for demonstrating the delta delay • Sequentiality in execution. Z. Navabi and McGraw-Hill Inc. . z <= x OR y AFTER 36 NS. x. w <= NOT a. END not_properly_timed. same exact real time CHAPTER 4 21 © 1999.

Navabi and McGraw-Hill Inc. . we do not see Sequentiality CHAPTER 4 22 © 1999.Delta Delay a1 b1 c1 w0 x0 y 0 z1 0 1 2δ 3δ 0 δ 12 24 36 NS • Timing diagram showing delta delays • Looking at real times. Z.

c <= NOT b. • Description for a chain of two inverters • Demonstrating Delta. b. Z. transactions and concurrency CHAPTER 4 23 © 1999. . c : BIT := '0'. END concurrent. BEGIN a <= '1'. b <= NOT a. Navabi and McGraw-Hill Inc.Delta Delay ARCHITECTURE concurrent OF timing_demo IS SIGNAL a.

Z.Delta Delay a 0 b0 c 0 0 δ 1 2δ 3δ 0 NS • Timing diagram for timing_demo • Everything happens at real-time 0 CHAPTER 4 24 © 1999. . Navabi and McGraw-Hill Inc.

ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’.Delta Delay y x Ideal elements with zero real time delay. END forever. SIGNAL y: BIT := ‘1’. y <= NOT x. x 0 0 1δ 2δ 3δ 4δ 5δ 6δ 7δ 0 t y 1 0 1δ 2δ 3δ 4δ 5δ 6δ 0 t • Oscillation in zero real time • Don’t try this at home CHAPTER 4 25 © 1999. . Z. BEGIN x <= y. Navabi and McGraw-Hill Inc.

END PROCESS. Z. .Sequential Placement of Transactions ARCHITECTURE sequential OF sequential_placement IS . BEGIN PROCESS x<= v1 AFTER t1. END sequential. WAIT.. • Sequential placement of transactions in a sequential body of VHDL • A wait. x<= v2 AFTER t2. statement suspends a sequential body forever • Sequentially values are placed on the LHS CHAPTER 4 26 © 1999. Navabi and McGraw-Hill Inc..

END concurrent.Sequential Placement of Transactions ARCHITECTURE concurrent OF sequential_placement IS . ... • Sequential placement of transaction in a concurrent body of VHDL • Same effect as the above process statement CHAPTER 4 27 © 1999. v2 AFTER t2-t1 x <= a AFTER t2. Z. Navabi and McGraw-Hill Inc. BEGIN a <= v1.

Navabi and McGraw-Hill Inc. or overrides existing ones CHAPTER 4 28 © 1999.Sequential Placement of Transactions • Projected output waveform • A new transaction will be compared with all existing transactions • It appends. Z. .

Z.Sequential Placement of Transactions • Multiple drivers of a resolved signal • Each driver timing is treated independently CHAPTER 4 29 © 1999. Navabi and McGraw-Hill Inc. .

v = v existing new 4 Append the new transaction. . Difference between time of new and existing is greater than the reject value v /=v existing new 5 Append the new transaction Difference between time of new and existing is less than or equal to reject value v /=v existing new 6 Overwrite existing transaction • Effective transactions on the driver of a signal • Multiple transactions are sequentially placed on the signal driver CHAPTER 4 30 © 1999.Sequential Placement of Transactions TRANSPORT 1 New Transaction is BEFORE Already Existing Overwrite existing transaction 3 INERTIAL Overwrite existing transaction 2 New Transaction is AFTER Already Existing Append the new transaction. Z. Navabi and McGraw-Hill Inc.

CHAPTER 4 31 © 1999. WAIT. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := ‘Z’. x <= TRANSPORT ‘0’ AFTER 3 NS. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. Z. END PROCESS. END sequential. .

. Z. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. x <= TRANSPORT ‘0’ AFTER 8 NS. WAIT. END sequential. x z z 1 0 7 8 9 0 1 2 3 4 5 6 • Appending transactions • Delay type is transport • The new transaction is after the existing one. CHAPTER 4 32 © 1999.

x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one CHAPTER 4 33 © 1999. END sequential. Navabi and McGraw-Hill Inc. WAIT. x <= ‘0’ AFTER 3 NS. . Z.Sequential Placement of Transactions ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := ‘Z’. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. END PROCESS.

. BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS. x z z 0 7 8 9 0 1 2 3 4 5 6 • Saving previous transactions of same value • Transactions with the same value are both kept on the driver of x CHAPTER 4 34 © 1999.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. WAIT. END PROCESS. Navabi and McGraw-Hill Inc. Z. x <= ‘0’ AFTER 8 NS. END sequential.

BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS. END sequential. x Z z Z 1 0 0 1 2 3 4 5 6 7 8 9 • Appending the new transaction of different value • Time difference of new and existing is greater than reject value CHAPTER 4 35 © 1999. . Navabi and McGraw-Hill Inc. Z.Sequential Placement of Transactions ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=’Z’. WAIT. END PROCESS.

END sequential x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions of different value • The new transaction is scheduled after the existing. Z. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=’Z’. x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS. . END PROCESS. and has a different value CHAPTER 4 36 © 1999. Navabi and McGraw-Hill Inc. WAIT.

target3 <= TRANSPORT waveform AFTER 5 NS. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. '0' AFTER 27 NS. SIGNAL target1. '0' AFTER 08 NS. target3 : BIT. '1' AFTER 24 NS.Signal assignments target1 <= waveform AFTER 5 NS. . target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. 0 3 5 8 14 18 24 27 29 32 33 35 38 40 • Pulse rejection in inertial. '0' AFTER 35 NS. Z. Navabi and McGraw-Hill Inc. '0' AFTER 18 NS. target2. reject.Creating waveform waveform <= '1' AFTER 03 NS. '1' AFTER 33 NS. END delay. -. and transport delay mechanisms • This is a result of sequential placement of transactions CHAPTER 4 37 © 1999. '1' AFTER 14 NS. BEGIN -.Sequential Placement of Transactions ENTITY example IS END ENTITY.

5) (0.5) (1.2) (0.0) (0.0) (0.5) (1.5) (0.0) (0.1) (1.0) (1.5) (1.0) (1.0) (0.5) (0.0) (0.2) target2 Sequential Placement of Transactions • New.0) (0.2) (0.0) (1.5) (0.3) (1.5) (0. and expired transactions on targets of example 38 5 8 13 14 18 19 23 24 27 29 (1.3) (0. pending.5) (1.0) (1.5) (0.2) target3 © 1999.3) (0.5) (0.5) (1.0) (1.CHAPTER 4 (1.5) (1.5) (0.2) target1 (1.0) (1.0) (1.0) (1.3) (1.1) (1.5) (0.5) (0. Z.0) (0.5) (1.5) (0. Navabi and McGraw-Hill Inc.0) (1.0) (1.1) (1.5) (0.0) (1.3) (0.2) (0.3) (0.5) (0.3) (0.5) (0.5) (0.5) (1.0) (1.5) (1.0) (1.5) (1.5) (1. 0 3 32 33 35 38 40 .

'0' AFTER 10 NS. BEGIN -. . b : BIT. END delay. Z. a AFTER 3 NS. all but the first are TRANSPORT CHAPTER 4 39 © 1999. Navabi and McGraw-Hill Inc. '1' AFTER 15 NS.Signal assignments a <= '1' AFTER 5 NS. b <= '0'.Sequential Placement of Transactions ENTITY example IS END ENTITY. -ARCHITECTURE delay OF example IS SIGNAL a. • Sequential placement of transactions by executing concurrent signal assignments • Events on a cause placement of transactions on b • In a waveform.

2 Simulation 5.6.1 Inverter Model 5.6 BINDING ALTERNATIVES 5.2 NAND Gate Models 5.1.3 WIRING ITERATIVE NETWORKS 5.1 Sequential Comparator 5.4.6.2 WIRING OF PRIMITIVES 5.2.1 Design of a 4-Bit Comparator 5.CHAPTER 5 STRUCTURAL SPECIFICATION OF HARDWARE 5.7 SUMMARY CHAPTER 5 1 © 1999.4 MODELING A TEST BENCH 5.1 PARTS LIBRARY 5.6.1 Logic Design of Comparator 5.2 Byte Latch 5.3.4.3.6 TOP-DOWN WIRING 5.3 Byte Comparator 5.1 VHDL Description of A Simple Test Bench 5. Zainalabedin Navabi .2 VHDL Description of a 4-Bit Comparator 5.1.2.2 VHDL Description of bit_comparator 5.

(c) inv i1 o1 (d) • • • • • Inverter Symbol Entity declaration Architecture body Notation. o1 : OUT BIT). END single_delay. (b) ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS. Zainalabedin Navabi .Parts Library (a) ENTITY inv IS PORT (i1 : IN BIT. END inv. CHAPTER 5 2 © 1999.

END inv.Parts Library ENTITY inv IS PORT ( entity declaration i1 : IN BIT . Zainalabedin Navabi . interface_signal_declaration interface_signal_declaration port clause • Details of the entity declaration of inverter • Port clause • Interface signal declaration CHAPTER 5 3 © 1999. o1 : OUT BIT ) .

Zainalabedin Navabi .Parts Library entity_name Interface Aspect Input Port Output Port Bidirectional Port Buffer Port • • • • • CHAPTER 5 Elements of aspect notation Input Output Inout Buffer is output that can be used on RHS 4 © 1999.

Bi-directional ports. Inputs. Buffers • Inout implies In and Out (two wires) • Buffer can be used inside an architecture CHAPTER 5 5 © 1999.Parts Library • Using ports. Zainalabedin Navabi . Outputs.

(b) ARCHITECTURE single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 5 NS.Parts Library (a) ENTITY nand2 IS PORT (i1. (c) nand2 i1 i2 (d) o1 • Two-input NAND symbol • Entity declaration • Architecture body uses NAND operator CHAPTER 5 6 © 1999. END nand2. Zainalabedin Navabi . END single_delay. i2 : IN BIT. o1 : OUT BIT).

Zainalabedin Navabi . i2 : IN BIT .Parts Library PORT ( i1. o1 : OUT BIT ) identifier_list mode type interface signal declaration port clause interface list interface_signal_declaration • Port clause details for nand2 • Signal declaration includes identifier list • Mode and type are the same as those of the inverter CHAPTER 5 7 © 1999.

Zainalabedin Navabi . o1 : OUT BIT). i3 : IN BIT. END nand3.Parts Library (a) ENTITY nand3 IS PORT (i1. (c) i1 i2 i3 nand3 o1 • Three-input NAND symbol • Architecture body and notation are shown • Must use AND and NOT CHAPTER 5 8 © 1999. END single_delay. i2. (b) ARCHITECTURE single_delay OF nand3 IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS.

Zainalabedin Navabi .Wiring Components Comparator A B A>B A=B > = < A<B • Logical symbol of a single bit comparator • Cascadable comparator • Will design one bit and cascade CHAPTER 5 9 © 1999.

b < 0 1 1 00 01 1 1 a<b 1 11 10 • Karnaugh maps for the outputs of the single bit comparator • Each output depends on data inputs and its corresponding control input CHAPTER 5 10 © 1999.Wiring Components a. Zainalabedin Navabi . b = 0 1 1 a=b 1 00 01 11 10 a. b > 0 1 1 1 a>b 00 01 11 10 1 1 a.

gt + a .( b’ . b’ . b . gt)’. b a_gt_b = ((a .Wiring Components a_gt_b = a . b . lt + a’ . b)’)’ • Boolean expression for the outputs • Use DeMorgan’s for all-NAND implementation CHAPTER 5 11 © 1999. gt)’. lt)’. b’ . eq)’)’ a_lt_b = ((a’ . lt)’. lt + b . eq + a’ .( a .( a’ .(b . Zainalabedin Navabi . gt + b’ .(a’ . b’ a_eq_b = a . b’)’)’ a_eq_b = ((a . eq a_lt_b = a’ . eq)’.

Zainalabedin Navabi .Wiring Components a gt a_gt_b b a b eq a_eq_b a a_lt_b lt b • Logic diagram of bit_comparator • Using only our primitive components CHAPTER 5 12 © 1999.

eq. a_eq_b.previous equal -.data inputs -.previous less than -. lt : IN BIT.greater -. Zainalabedin Navabi .less than (b) • Interface description of bit_comparator • Inputs and outputs of BIT type are declared CHAPTER 5 13 © 1999. END bit_comparator. b. a_lt_b : OUT BIT). a_gt_b.Wiring Components bit_comparator a b gt eq lt a_gt_b a_eq_b a_lt_b (a) ENTITY bit_comparator IS PORT (a.previous greater than -. gt.equal -. -.

Wiring Components bit_comparator (gate_level) a nand2 i1 i2 o1 im3 nand2 i1 i2 o1 im4 i1 i2 i3 nand3 o1 a_gt_b b inv i1 o1 im2 i1 i2 nand2 o1 im5 gt i1 i2 i3 nand3 o1 nand2 nand3 o1 im7 i1 i2 o1 a_eq_b im6 eq lt i1 i2 i3 nand2 i1 i2 o1 im8 inv i1 o1 im1 i1 i2 nand2 o1 im9 i1 i2 i3 nand3 o1 a_lt_b nand2 i1 i2 o1 im10 • Composition Aspect of bit_comparator. CHAPTER 5 14 © 1999. Zainalabedin Navabi .

g2 : n2 PORT MAP (a. im3. i2.Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT.Intermediate signals SIGNAL im1. Zainalabedin Navabi . im8. g12 : n3 PORT MAP (im8. eq. b. lt.nand3 (single_delay).a_lt_b output g9 : n2 PORT MAP (im1. im9). im6. END COMPONENT. COMPONENT n2 PORT (i1. -. im4. im2. i2: IN BIT. im5). a_gt_b).a_eq_b output g6 : n3 PORT MAP (im1. im2. im9. END COMPONENT. im6). im10). im4). lt.inv (single_delay). FOR ALL : n2 USE ENTITY WORK. g1 : n1 PORT MAP (b. -.nand2 (single_delay). g10 : n2 PORT MAP (im1. o1: OUT BIT). o1: OUT BIT). o1: OUT BIT). im3). a_eq_b). im4. a_lt_b). g4 : n2 PORT MAP (im2.im2. im8). FOR ALL : n3 USE ENTITY WORK. FOR ALL : n1 USE ENTITY WORK. component name. im7. gt. im2). im5. BEGIN -. im5. gt. im9. b. im1). im10. im7. g11 : n2 PORT MAP (b. END gate_level. im10 : BIT. • Architecture body of bit_comparator identified as gate_level • Components instantiations constitute the body • Each instantiation has a label. i3: IN BIT. COMPONENT n3 PORT (i1. g5 : n3 PORT MAP (im3. g3 : n2 PORT MAP (a. g8 : n2 PORT MAP (im6. im7). g7 : n3 PORT MAP (a.a_gt_b output g0 : n1 PORT MAP (a. eq. END COMPONENT. -. and PORT MAP • Component declarations are local to the architecture CHAPTER 5 15 © 1999.

g7 : n3 PORT MAP (a. im7. i2. Zainalabedin Navabi .. im2. im6.. END gate_level. FOR ALL : n3 USE ENTITY ... im7). i3: IN BIT. . . END COMPONENT. im3.. im9. SIGNAL im1. BEGIN ... . im8. im5....Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n3 PORT (i1. component declaration configuration specification architecture declarative part architecture body signal declaration component instantiation statement architecture statement part • Syntax details of the architecture body bit_comparator • Signals in the entity are visible to the architecture of CHAPTER 5 16 © 1999. im10 : BIT. O1: OUT BIT). b. im4. eq.

im7 ) . instantiation_label component_name component instantiation statement association_list port map aspect • Component instantiation statement syntax details • A label is required • It includes an association list CHAPTER 5 17 © 1999. b.Wiring Components g7 : n3 PORT MAP ( a. eq. Zainalabedin Navabi .

im6.nand2(single_delay) PORT MAP (a. im7.nand3(single_delay) PORT MAP (im3. g1 : ENTITY WORK. a_eq_b).nand3(single_delay) PORT MAP (im1.nand2(single_delay) PORT MAP (im1. g11 : ENTITY WORK. im6). lt. im7).nand2(single_delay) PORT MAP (im6.a_lt_b output g9 : ENTITY WORK. g4 : ENTITY WORK. im7.nand2(single_delay) PORT MAP (im1. g10 : ENTITY WORK.nand3(single_delay) PORT MAP (a. im2). im9. gt. im8). g8 : ENTITY WORK. im4.Wiring Components ARCHITECTURE netlist OF bit_comparator IS -.Intermediate signals SIGNAL im1.nand2(single_delay) PORT MAP (a. g3 : ENTITY WORK. im5). lt. im2. Zainalabedin Navabi .inv(single_delay) PORT MAP (a. im4. im10). g12 : ENTITY WORK. END netlist. b.a_gt_b output g0 : ENTITY WORK.nand2(single_delay) PORT MAP (b. • Netlist description of bit_comparator • This is direct instantiation • If architecture name is not specified. a_gt_b). im1). the most recently compiled architecture will be used CHAPTER 5 18 © 1999. im9). gt.nand3(single_delay) PORT MAP (im8. BEGIN -. im4).im2. im5. im10 : BIT. g5 : ENTITY WORK. g7 : ENTITY WORK. a_lt_b). im3. im3).inv(single_delay) PORT MAP (b. im2. im8.nand2(single_delay) PORT MAP (im2. eq. im5. im9. -.a_eq_b output g6 : ENTITY WORK. b. im10. g2 : ENTITY WORK. eq. -.

Zainalabedin Navabi .Wiring Components • bit_comparator simulation run • keeping control inputs at 010 CHAPTER 5 19 © 1999.

Zainalabedin Navabi .Wiring Iterative Networks 4 Data inputs 4 Four Bit Comparator A B A>B A=B Compare outputs Control inputs > = < A<B • Logical symbol of a 4-bit comparator • Same configuration as that of the one-bit comparator • This is similar to the 74LS85 magnitude comparator CHAPTER 5 20 © 1999.

Zainalabedin Navabi .Wiring Iterative Networks B3 A3 Comparator A B 3 > = < A>B A=B A<B B2 A2 Comparator A B 2 > = < A>B A=B A<B B1 A1 Comparator A B 1 > = < A>B A=B A<B B0 A0 Comparator A B 0 > = < A>B A=B A<B A>B A=B A<B < = > • A 4-bit comparator using four single bit comparators • Numbers different in MSB. produce results faster • Worst case delay for equal inputs CHAPTER 5 21 © 1999.

previous equal lt : IN BIT.a < b END nibble_comparator. interface aspect.previous less than a_gt_b. -.Wiring Iterative Networks nibble_comparator a(3:0) a_gt_b b(3:0) gt eq lt a_eq_b a_lt_b (a) ENTITY nibble_comparator IS PORT (a.-.a and b data inputs gt. -. b : IN BIT_VECTOR (3 DOWNTO 0).previous greater than eq. -. • Interface description of nibble_comparator. -. -. -.a > b a_eq_b.a = b a_lt_b : OUT BIT). (b) entity declaration • Inputs of of BIT_VECTOR type • Can use any range (a) CHAPTER 5 22 © 1999. Zainalabedin Navabi .

Wiring Iterative Networks nibble_comparator(iterative) a(3:0) b(3:0) a(3) b(3) bit_comparator a (gate_level) Bit 3 b gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a(2) b(2) bit_comparator a (gate_level) Bit 2 b gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) bit_comparator a (gate_level) Bit 1 b gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) bit_comparator a (gate_level) Bit 0 b gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect of nibble_comparator CHAPTER 5 23 © 1999. Zainalabedin Navabi .

SIGNAL im : BIT_VECTOR ( 0 TO 8). im(6). Zainalabedin Navabi . a_eq_b. eq. END iterative. im(2)). b(i). lt : IN BIT. gt. a_eq_b. a_gt_b. END GENERATE. BEGIN c0: comp1 PORT MAP (a(0). a_lt_b : OUT BIT). im(i*3+2) ). im(8). im(i*3+1). im(7). eq. • Iterative architecture of nibble_comparator • Uses nested generate statements • Can easily expand by changing numbers CHAPTER 5 24 © 1999. im(i*3+0). im(0). c3: comp1 PORT MAP (a(3). gt. b(3). im(1). b(0).bit_comparator (gate_level). b. im(i*3-3). c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). im(i*3-2). lt. a_lt_b). END COMPONENT. im(i*3-1). FOR ALL : comp1 USE ENTITY WORK.Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. a_gt_b.

im(i*3-2). b(1). im(5) ) • Association list of c instance of comp1 within generate statement • Bit 1 is configured for i value of 1 CHAPTER 5 25 © 1999. im(i*3+0).Wiring Iterative Networks PORT MAP (a(i). im(2). b(i). im(0). Zainalabedin Navabi . im(i*3+2) ) i=1 i=1 i=1 i=1 i=1 i=1 i=1 i=1 PORT MAP (a(1). im(3). im(4). im(1). im(i*3-1). im(i*3-3). im(i*3+1).

b(i). im(i*3+2)). END GENERATE . im(i*3-3). im(i*3+1).Wiring Iterative Networks c1to2 : FOR i IN 1 TO 2 GENERATE c: COMP1 PORT MAP (a(i). im(i*3-1). generate_label generation_scheme generate statement concurrent_statement • • • • Generate statement syntax details This is a concurrent statement The body of a generate statement is concurrent Can use FOR or IF generation scheme CHAPTER 5 26 © 1999. im(i*3-2). im(i*3+0). Zainalabedin Navabi .

gt. END COMPONENT. eq. a_lt_b). lt. im(i*3+2) ). BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i).Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. END iterative. Zainalabedin Navabi . eq. im(i*3+1). FOR ALL : comp1 USE ENTITY WORK. CONSTANT n : INTEGER := 4. Chap 7. CHAPTER 5 27 © 1999. im(i*3+0). a_gt_b. im(i*3-3). im(i*3-2). b(i). SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). b(i). END GENERATE. lt : IN BIT. a_lt_b : OUT BIT). END GENERATE. a_eq_b. b.bit_comparator (gate_level). END GENERATE. im(i*3-1). a_eq_b. • A more flexible iterative architecture of nibble_comparator • Constant n sizes the comparator • There is still a better way. b(i). END GENERATE. im(i*3-2). m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). use unconstrained arrays. im(i*3-1). im(1). im(0). a_gt_b. im(2) ). im(i*3-3). gt.

bit_comparator (gate_level). im(1). gt. im(2) ). END GENERATE.Wiring Iterative Networks l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK. lt. eq. Zainalabedin Navabi . b(i). BEGIN least: comp1 PORT MAP (a(i). im(0). • Configuration specifications create some ambiguities • Problem is corrected by Generate Statement Declarative Part • Binding indication appears here CHAPTER 5 28 © 1999.

Modeling a Test Bench test_bench (input_output) nibble_comparator (iterative) a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • A test bench for nibble_comparator. Zainalabedin Navabi . the composition aspect • A test bench does not use ports • All signals used must be explicitly declared CHAPTER 5 29 © 1999.

Modeling a Test Bench ENTITY nibble_comparator_test_bench IS END nibble_comparator_test_bench . -.a = b (worst case) "1111" AFTER 5000 NS. prepare for next) "1111" AFTER 4500 NS. -. -. a_gt_b. SIGNAL vdd : BIT := '1'. -. -.a = b (worst case) "0000" AFTER 5000 NS. gtr. a_lt_b : IN BIT. • Test bench for nibble_comparator. SIGNAL a. lss. a_eq_b. -. vdd. gtr : BIT. END COMPONENT. a2: a <= "0000". -. -ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a.a < b (worst case) "1110" AFTER 2500 NS. prepare for next) "1111" AFTER 4500 NS. -. a_lt_b_out : OUT BIT). best case) a3 : b <= "0000".a < b (need bit 2 info) "1111" AFTER 4000 NS. b. best case) "0000" AFTER 5500 NS. eql. FOR a1 : comp4 USE ENTITY WORK. -.a > b (need bit 1 info) "1100" AFTER 3500 NS. b : IN bit_vector (3 DOWNTO 0).a > b (need bit 3 only.a < b (steady state.a < b (need bit 2 info) "0000" AFTER 4000 NS. -.a = b (steady state) "1110" AFTER 0500 NS. SIGNAL eql. -. ---. SIGNAL gnd : BIT := '0'. -. a_gt_b_out.a = b (steady state) "1111" AFTER 0500 NS. -. gnd.a > b (worst case) "1111" AFTER 1500 NS.a < b (need bit 3 only.a = b (worst case) "1111" AFTER 6000 NS.nibble_comparator(iterative). gnd.a > b (need bit 3 only. -.a < b (need bit 3 only. lss).a > b (worst case) "1110" AFTER 1500 NS. -. best case) "0000" AFTER 5500 NS.a < b (worst case) "1100" AFTER 2500 NS.a = b (worst case) "0000" AFTER 6000 NS. BEGIN a1: comp4 PORT MAP (a.a > b (need bit 1 info) "1010" AFTER 3500 NS.a < b (steady state. b : BIT_VECTOR (3 DOWNTO 0). -. -. best case) END input_output. a_eq_b_out. -. Zainalabedin Navabi . ---. CHAPTER 5 30 iterative architecture of © 1999.

.. .... "1111" ..... ... ........ .. ..... ...... .. '0' . . . ... ........ "1010" ................ ..... . .. "1111" ... "1111" . . eql '0' '1' .. . '1' ....... ... '0' . .... '1' ..... '0' ... .. ........ .. '0' ... "1111" .. . '0' . "0000" . . . "1110" ... ....... '1' ...... ... ..... ........ .. .. "1100" ....... ... . ... .. . .. "0000" "1111" ... .. • Simulation report for simulating iterative comparator test bench • All events are observed CHAPTER 5 31 © 1999..... "0000" .... ..... '1' . .... ...... .. ... .... .. .... ........ . ........... '0' . ... .. '1' ...............Modeling a Test Bench TIME (NS) 0 5 500 544 548 1500 1544 1548 2500 2533 2537 3500 3522 3526 4000 4500 4544 4548 5000 5011 5015 5500 5544 5548 6000 6011 6015 a(3:0) "0000" . ....... .. .. "1110" . .... .... '1' ........... .. '1' ........ ... . Zainalabedin Navabi ....... SIGNALS b(3:0) gtr "0000" .......... . ..... '0' .................. .. . .............. . .. .................. '0' lss '0' ......... .... . .. .... '0' ... '1' ........

Zainalabedin Navabi CHAPTER 5 .Binding Alternatives C S 1 3 Q R 2 4 • • • • Logical diagram of a simple latch With equal timing this will not work Will use this example for showing binding alternatives Correct the oscillation problem by binding to NAND gates of different delay values 32 © 1999.

c : IN BIT. q <= im3. BEGIN g1 : n2 PORT MAP (s. SIGNAL im1. im4 : BIT. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1.nand2 (single_delay). Zainalabedin Navabi . o1: OUT BIT). c. im2. • • • • VHDL description of set-reset latch This is using the 2-input NAND for all four instances Signal assignment avoids use of Buffer The single_delay architecture is used CHAPTER 5 33 © 1999. FOR ALL : n2 USE ENTITY WORK. q : OUT BIT). im4). r.Binding Alternatives ENTITY sr_latch IS PORT (s. im3). END sr_latch. im1). g2 : n2 PORT MAP (r. im2). im4. g4 : n2 PORT MAP (im3. c. END gate_level. im2. END COMPONENT. im3. i2: IN BIT. g3 : n2 PORT MAP (im1.

im4. Zainalabedin Navabi . o1: BUFFER BIT).nand2 (single_delay). q). END gate_level. g2 : n2 PORT MAP (r. • sr_latch (gate_level) architecture using BUFFER • componet declaration and the actual entity must match is PORT MAP is not used with the configuration specification • The 2-input NAND must change to use BUFFER instead of OUT CHAPTER 5 34 © 1999. im4). g3 : n2 PORT MAP (im1. im1). FOR ALL : n2 USE ENTITY WORK. im2. im4 : BIT. im2). BEGIN g1 : n2 PORT MAP (s.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. g4 : n2 PORT MAP (q. im2. END COMPONENT. c. c. SIGNAL im1. i2: IN BIT.

• • • • A faster NAND gate The gate delay is 3 NS Uses the same entity as the single_delay NAND Using this NAND corrects the oscillation problem CHAPTER 5 35 © 1999.Binding Alternatives ARCHITECTURE fast_single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 3 NS. END fast_single_delay. Zainalabedin Navabi .

Binding Alternatives c s i1 i2 (fast_single_delay) sr_latch (gate_level) nand2 g1: im1 (fast_single_delay) nand2 g3: o1 i1 i2 o1 im3 q r i1 i2 (single_delay) nand2 g2: o1 im2 i1 i2 (single_delay) nand2 g4: o1 im4 (a) • SR-latch. using gates with different delays. Zainalabedin Navabi . composition aspect • Same wiring as the latch that oscillates CHAPTER 5 36 © 1999.

im2. im1). im4 : BIT. im3. i2: IN BIT. g2 : n2 PORT MAP (r. im4. g4 : n2 USE ENTITY WORK. q <= im3. im4). g3 : n2 PORT MAP (im1. architecture body • Same wiring. Zainalabedin Navabi .nand2 (single_delay).Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im2. c. END COMPONENT. • SR-latch. o1: OUT BIT). FOR g2. im3). im2). g4 : n2 PORT MAP (im3. different binding • Fast_single_delay architecture is used for g1 and g3 CHAPTER 5 37 © 1999. FOR g1. c.nand2 (fast_single_delay). g3 : n2 USE ENTITY WORK. BEGIN g1 : n2 PORT MAP (s. SIGNAL im1. END gate_level. using gates with different delays.

using nand2 and nand3 gates. composition aspect • This solution uses 3-input NAND gates • The 3-input gates have different delay values than the 2-input NAND gates CHAPTER 5 38 © 1999.Binding Alternatives c s i1 i2 (single_delay) sr_latch (gate_level) nand2 g1: im1 nand2 g3: q o1 i1 i2 (single_delay) o1 im3 r i1 i2 i3 nand3 (single_delay) o1 g2: im2 i1 i2 i3 (single_delay) nand3 im4 o1 g4: (a) • SR-latch. Zainalabedin Navabi .

y. z). z: OUT BIT). FOR g2. BEGIN g1 : n2 PORT MAP (s. g2 : n2 PORT MAP (r. im4). • SR-latch. architecture • Configuration specification takes caring of wiring the 3-input NAND into a 2-input NAND • PORT MAP in binding. im2.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x. g3 : n2 PORT MAP (im1. ALTERNATIVELY: FOR g1. c. END gate_level. y.nand2 (single_delay) PORT MAP (x. im3. g3 : n2 USE ENTITY WORK. END COMPONENT. y. g3 : n2 USE ENTITY WORK. z). g4 : n2 USE ENTITY WORK. y. im4. z). im4 : BIT.nand3 (single_delay) PORT MAP (x. y: IN BIT. q <= im3. z). FOR OTHERS : n2 USE ENTITY WORK. SIGNAL im1. using nand2 and nand3 gates. im3). c. im2. Zainalabedin Navabi . overrides the default • Could use OTHERS CHAPTER 5 39 © 1999.nand3 (single_delay) PORT MAP (x. im1). x.nand2 (single_delay) PORT MAP (x. g4 : n2 PORT MAP (im3. im2). x. FOR g1.

Binding Alternatives Signals of gate_level of sr_latch r c im2 Port map association of instantiation statement Local ports of g2 instance of n2 x y z Port map association of configuration specification Formal ports of nand3 in1 in2 in3 o1 • Two-step association • Declaration is local • Names in declaration are used only when not specified in a configuration specification CHAPTER 5 40 © 1999. Zainalabedin Navabi .

and generic map aspect • If not specified.nand2 (single_delay) PORT MAP (x. z) . port map aspect. Zainalabedin Navabi . those of the declaration will be used • Declarations are still needed unless direct instantiations are used CHAPTER 5 41 © 1999. y. instantiation_list component_name component specification entity aspect binding indication port map aspect configuration specification • Configuration specification syntax details • Binding indication contains entity aspect. g3 : n2 USE ENTITY WORK.Binding Alternatives FOR g1.

Top-Down Wiring

old_new_comparator byte_comparator i di byte_latch con1 clk clk a b gt eq lt a_gt_b a_eq_b a_lt_b

• Will develop a complete example, compare old and new data, keep a count • Defaults will be used • Most recently compiled architectures are used in the absence of configuration specifications • Composition aspect of old_new_comparator
CHAPTER 5 42 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT); END old_new_comparator; -ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparator PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN); END wiring;

• • • • •
CHAPTER 5

old_new_comparator VHDL description Declarations are present Configuration specifications are missing Use OPEN for unconnected outputs OPEN inputs must have a default value
43 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0)); END byte_latch; -ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE; END iterative;

• • • •

An 8-bit latch is required for this design Use a configurable description based on D-type latch VHDL description of byte_latch. Iterative architecture is used

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© 1999, Zainalabedin Navabi

Top-Down Wiring

c d inv i1 o1

sr_latch C S q q

R

(a)

• Build a D-latch using our sr_latch and an inverter • Composition aspect is shown

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Top-Down Wiring

ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT; BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar); END sr_based; (b)

• Design of d_latch, VHDL description • Configuration specifications are not used • Local declarations are used for ports and name of the actual entity

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Top-Down Wiring

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );

END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;

• Another necessary component for this design is an 8bit comparator • Byte comparator VHDL description • Uses 8 instances of bit_comparator • Constant n is changed to 8 • Default architectures are used
CHAPTER 5 47 © 1999, Zainalabedin Navabi

Top-Down Wiring
A structural description for a design consists of a wiring specification of its subcomponents. In this chapter, the

definition and usage of components in larger designs was illustrated. Generate statements also were introduced as a convenient way to describe repetitive hardware structures and a notation was defined for graphical representation of structural descriptions. In addition, various forms and

options in component declarations and configuration specifications were discussed. The last part of this chapter presented a top-down design using basic gates and components presented in the earlier sections. Using simple gates, the reader should now be able to design larger digital circuits with many levels of component nesting.

• End Of Chapter 5

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CHAPTER 6 DESIGN ORGANIZATION AND PARAMETERIZATION

6.1 DEFINITION AND USAGE OF SUBPROGRAMS 6.1.1 A Functional Single Bit Comparator 6.1.2 Using Procedures in a Test Bench 6.1.3 Language Aspects of Subprograms 6.1.4 Utility Procedures 6.2 PACKAGING PARTS AND UTILITIES 6.2.1 Packaging Components 6.2.2 Packaging Subprograms 6.3 DESIGN PARAMETRIZATION 6.3.1 Using Default Values 6.3.2 Using Fixed Values 6.3.3 Passing Generic Parameters 6.4 DESIGN CONFIGURATION 6.4.1 A General Purpose Test Bench 6.4.2 Configuring Nested Components 6.4.3 Incremental Binding 6.4.4 An n-bit Register Example 6.4.5 Iterative Parity Checking 6.5 DESIGN LIBRARIES 6.5.1 Existing Libraries 6.5.2 Library Management 6.6 SUMMARY

CHAPTER 6

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© 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

GT Equation EQ Equation LT Equation

a_gt_b = a . gt + b' . gt + a . b' a_eq_b = a . b . eq + a' . b' . eq a_lt_b = b . lt + a' . lt + b . a'

ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;

An architecture for demonstrating use of subprograms

• Demonstrating the use of functions • Use functions in place of Bololean expresssions • A functional bit_comparator, using the same function for two outputs
CHAPTER 6 2 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

FUNCTION fgl ( w, x, g1 :BIT) RETURN BIT IS BEGIN RETURN (w AND g1) OR (NOT x AND g1) OR (w AND NOT x) ; END;

designator formal_parameter_list type_mark subprogram body expression return statement sequential statement subprogram statement part subprogram specification

• Function body is sequential • Use functions for utilities and coding style • Syntax details of a subprogram body, a general view
CHAPTER 6 3 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END structural;

• Using the functional bit_comparator • Structural architecture of a nibble_comparator

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© 1999, Zainalabedin Navabi

Zainalabedin Navabi . VARIABLE tmp. vdd. a_gt_b. END COMPONENT. j := j + 1. pos : INTEGER := 0. ELSE buf (j) := '0'. target <= TRANSPORT buf AFTER i * period. BEGIN a1: comp4 PORT MAP (a. tmp := tmp / 2. VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). gnd. a_eq_b. • Defining and using a procedure • Procedural architecture of nibble_comparator • INTEGERS type is an array of 13 integers CHAPTER 6 5 © 1999. END apply_data. COMPONENT comp4 PORT (a. SIGNAL gnd : BIT := '0'. lss). END procedural. j := 0. 500 NS). b : IN bit_vector (3 DOWNTO 0). SIGNAL eql. b. END LOOP. PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'. 00&14&14&15&15&12&12&12&15&15&15&00&00. apply_data (a. lss. SIGNAL vdd : BIT := '1'. lt : IN BIT. 500 NS). b : BIT_VECTOR (3 DOWNTO 0). eq. FOR a1 : comp4 USE ENTITY WORK. gt. END LOOP. gtr. END IF. CONSTANT period : IN TIME) IS VARIABLE j : INTEGER. gnd. eql. CONSTANT values : IN integers. a_lt_b : OUT BIT).nibble_comparator(structural). SIGNAL a. apply_data (b. BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i). gtr : BIT. 00&15&15&14&14&14&14&10&00&15&00&00&15.Definition and Usage of Subprograms ARCHITECTURE procedural OF nibble_comparator_test_bench IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER.

.... '1' . ............. '1' . '0' .. ... '1' ... "1100" .. '0' ....Definition and Usage of Subprograms TIME (NS) 0 48 500 548 1500 1548 2500 2536 3500 3524 4000 4500 4548 5000 5012 5500 5548 6000 6012 a(3:0) "0000" . ....... '1' .................. . ... '1' eql '0' '1' . "1110" ..... ........... . ... . '0' ...... "1010" . "0000" . ... '1' ... .. • Simulation report resulting from the procedural test bench • All events are observed • Shows increments of 12 NS only CHAPTER 6 6 © 1999. ........... '0' ..... ... '0' . '0' . '0' lss '0' ..... '1' .......... ............ "1111" .... ... ......... '0' ...... .. '0' ... "1111" . "1110" ... .. . SIGNALS b(3:0) gtr "0000" ......... .. "1111" .. "0000" "1111" .... . '1' .......... "0000" . ........ .. ...... ..... . "1111" .. ... .... . ........ Zainalabedin Navabi ....

BEGIN. Zainalabedin Navabi . END apply_data. CONSTANT period : IN TIME ) IS VARIABLE j : INTEGER. . CONSTANT values : IN integers.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). . subprogram specification formal parameter list subprogram declarative part subprogram body loop statement sequential statement subprogram statement part • • • • CHAPTER 6 Details of a subprogram body Function or procedure subprogram specification Subprograms are procedural bodies Nested procedural statements 7 © 1999. END LOOP. VARIABLE tmp : INTEGER := 0. VARIABLE buf: BIT_VECTOR (3 DOWNTO 0). FOR i IN 0 TO 12 LOOP .

. . loop parameter specification iteration scheme loop_statement sequence_of_statement • • • • CHAPTER 6 Loops are procedural Loop statement with FOR iteration scheme Can nest procedural statements Sequence_of_statements is the sequential construct 8 © 1999.Definition and Usage of Subprograms FOR i IN 0 TO 12 LOOP . END LOOP. Zainalabedin Navabi .

END IF.Definition and Usage of Subprograms IF (tmp MOD 2 = 1) THEN buf (j) := ’1’. ELSE buf (j) := ‘0’. Zainalabedin Navabi . condition if_statement sequence_of_statements sequence_of_statements • Details of the If statement of apply_data procedure • This is a procedural statement • Sequence_of_statements is the sequential construct CHAPTER 6 9 © 1999.

BEGIN result := 0. int : OUT INTEGER) IS VARIABLE result: INTEGER. Zainalabedin Navabi . FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END bin2int. • Can do utility procedures • ‘RANGE attribute makes this a generic procedure • Procedure for binary to integer conversion CHAPTER 6 10 © 1999. END IF. END LOOP.Definition and Usage of Subprograms PROCEDURE bin2int (bin : IN BIT_VECTOR. int := result.

bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER.Definition and Usage of Subprograms PROCEDURE int2bin (int : IN INTEGER. BEGIN tmp := int. ELSE bin (i) := '0'. tmp := tmp / 2. END LOOP. FOR i IN 0 TO (bin'LENGTH . Zainalabedin Navabi . END int2bin. • Another utility procedure • Procedure for integer to binary conversion • ‘LENGTH attribute is used here CHAPTER 6 11 © 1999. END IF.1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'.

• • • • CHAPTER 6 Can use procedures within procedure Another version of apply_data procedure This version takes advantage of the int2bin procedure TRASPORT delay schedules all transactions at time 0 12 © 1999. target <= TRANSPORT buf AFTER i * period. Zainalabedin Navabi . END apply_data. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). buf). CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0).Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). CONSTANT values : IN integers. END LOOP.

otherwise it is a generic function CHAPTER 6 13 © 1999. Zainalabedin Navabi . RETURN result. • Functions can serve as utilities • Binary to integer conversion function • Assumes lower bound of 0. END LOOP. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END IF. BEGIN result := 0. END to_integer.Definition and Usage of Subprograms FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER.

END COMPONENT. o1: OUT BIT). COMPONENT n3 PORT (i1. Demonstrating specification and usage of packages • Component declarations as well as utilities can be packaged • A package declaration containing component declarations of simple gates • Eliminates the need for individual declarations CHAPTER 6 14 © 1999. Zainalabedin Navabi . END simple_gates. COMPONENT n2 PORT (i1: i2: IN BIT. o1: OUT BIT). i3: IN BIT. END COMPONENT.Packaging components PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT. o1: OUT BIT). END COMPONENT. i2.Packaging Parts and Utilities -.

im5). lt. im10. eq. im4. im10 : BIT. g11 : n2 PORT MAP (b. im2.Packaging Parts and Utilities USE WORK. im3). g2 : n2 PORT MAP (a. gt. im7. g1 : n1 PORT MAP (b. im7. -. g12 : n3 PORT MAP (im8. im2. im9. im4. g10 : n2 PORT MAP (im1. -. b. END gate_level.nand3 (single_delay).Intermediate signals SIGNAL im1. im7). FOR ALL : n2 USE ENTITY WORK. Zainalabedin Navabi .ALL. im3. im6. gt. lt. im8. eq. a_lt_b). • Using package of simple gates in gate_level of bit_comparator • This becomes our local declarations • Same naming rules as before. im5. im5. im8).a_lt_b output g9 : n2 PORT MAP (im1. g3 : n2 PORT MAP (a. im2).a_gt_b output g0 : n1 PORT MAP (a. a_eq_b). ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK. g7 : n3 PORT MAP (a. im1).simple_gates. g8 : n2 PORT MAP (im6. im6).im2. -. im4). g5 : n3 PORT MAP (im3.a_eq_b output g6 : n3 PORT MAP (im1.inv (single_delay). BEGIN -.nand2 (single_delay). b. g4 : n2 PORT MAP (im2. same configuration CHAPTER 6 15 © 1999. FOR ALL : n3 USE ENTITY WORK. im9. im10). a_gt_b). im9).

n1.simple_gates. n2 and n3 component declarations are visible . -.n3. Zainalabedin Navabi .simple_gates. WORK.n1. • An alternative application of the use clause • Can select only those needed CHAPTER 6 16 © 1999.Packaging Parts and Utilities USE WORK.simple_gates. .n2. WORK.

FUNCTION fgl (w. PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). PROCEDURE int2bin (int : IN INTEGER. • The basic_utilities package declaration • Packaging subprograms replaces their declaration • Types and declarations become visible to architectures CHAPTER 6 17 © 1999. END basic_utilities. PROCEDURE bin2int (bin : IN BIT_VECTOR. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER. Zainalabedin Navabi . x. x. eq : BIT) RETURN BIT. int : OUT INTEGER). CONSTANT values : IN integers. bin : OUT BIT_VECTOR).Packaging Parts and Utilities PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. CONSTANT period : IN TIME). gl : BIT) RETURN BIT. FUNCTION feq (w.

Zainalabedin Navabi . BEGIN tmp := int. eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq). END LOOP. VARIABLE buf : BIT_VECTOR (bin'RANGE). END feq.1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. int := result. END int2bin. END fgl. int : OUT INTEGER) IS VARIABLE result: INTEGER. PROCEDURE int2bin (int : IN INTEGER. x. END IF. • Package body includes body of procedures • The basic_utilities package body • Will use this package in all our examples CHAPTER 6 18 © 1999. PROCEDURE bin2int (bin : IN BIT_VECTOR. tmp := tmp / 2. BEGIN result := 0.Packaging Parts and Utilities PACKAGE BODY basic_utilities IS FUNCTION fgl (w. FOR i IN 0 TO (bin'LENGTH . bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. x. gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x). FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END IF. END bin2int. END LOOP. FUNCTION feq (w. ELSE bin (i) := '0'.

END LOOP. END LOOP. • Continuation of the basic_utilities package body • New declarations in this body are visible to this body only CHAPTER 6 19 © 1999.Packaging Parts and Utilities PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). RETURN result. END basic_utilities. Zainalabedin Navabi . CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). buf). END to_integer. END apply_data. BEGIN result := 0. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. CONSTANT values : IN integers. target <= TRANSPORT buf AFTER i * period. END IF. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i).

b. ARCHITECTURE functional OF bit_comparator IS BEGIN a_gt_b <= fgl (a.Packaging Parts and Utilities USE WORK. gt) AFTER 12 NS. Zainalabedin Navabi CHAPTER 6 20 .ALL. lt) AFTER 12 NS. a_lt_b <= fgl (b. • Using functions of the basic_utilities package • Architecture need not include function body • The USE statement handles visibility © 1999. END functional. a. b.basic_utilities. a_eq_b <= feq (a. eq) AFTER 12 NS.

apply_data (b. gnd.15. lt : IN BIT.Packaging Parts and Utilities USE WORK. END COMPONENT. gt. 0&15&15&14&14&14&14&10&00&15&00&00&15. (00. SIGNAL gnd : BIT := '0'.00). BEGIN a1: comp4 PORT MAP (a.ALL. b : IN bit_vector (3 DOWNTO 0). SIGNAL a.12. apply_data (a. 500 NS). lss.14. a_eq_b. Zainalabedin Navabi . vdd. lss).14. apply_data (b.15.12. b : BIT_VECTOR (3 DOWNTO 0). 0&14&14&15&15&12&12&12&15&15&15&00&00. SIGNAL eql.basic_utilities.00. ALTERNATIVELY: apply_data (a.15. eql.14.10. a_gt_b.15).15. 500 NS). FOR a1 : comp4 USE ENTITY WORK. ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a.nibble_comparator(structural).15.00.15. gtr : BIT. SIGNAL vdd : BIT := '1'. 500 NS). • • • • CHAPTER 6 Using procedures of the basic_utilities package Concatenate to form 13 integers Can also use aggregate operation Aggregate for elements of the array only 21 © 1999.14. (00. eq. gtr. b. 500 NS).12. END procedural.00.15.14.14. a_lt_b : OUT BIT).00. gnd.15.

Architecture for demonstrating specification and definition of parameters • Start design parameterization examples with same simple structures CHAPTER 6 22 © 1999. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. o1 : OUT BIT). END average_delay. tphl : TIME := 3 NS). PORT (i1 : IN BIT.Design Parametrization ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. Zainalabedin Navabi . END inv_t.

PORT (i1. tphl : TIME := 5 NS). i2 : IN BIT. declares objects of type constant © 1999.Design Parametrization ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. i2. tphl : TIME := 4 NS). -ARCHITECTURE average_delay OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. o1 : OUT BIT). END average_delay. i3 : IN BIT. • Parametrized gate models • GENERIC is used. o1 : OUT BIT). END nand3_t. -ARCHITECTURE average_delay OF nand3_t IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2. END nand2_t. ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS. PORT (i1. END average_delay. Zainalabedin Navabi CHAPTER 6 23 .

Zainalabedin Navabi . tphl : TIME := 3 NS ). END inv_t. PORT (i1 : IN BIT. o1 : OUT BIT).Design Parametrization ENTITY inv_t IS GENERIC ( tplh : TIME := 5 NS . interface constant declaration entity declaration interface constant declaration (generic) interface list (formal) generic clause entity header (formal) port clause • Details of the entity declaration of inverter with generics • Using a default value is helpful but not required • Generic clause comes before port clause CHAPTER 6 24 © 1999.

and nand3_t • Graphical representation with generics • Port association and generic association must be done when used CHAPTER 6 25 © 1999. Zainalabedin Navabi .Design Parametrization inv_t i1 tplh o1 tphl nand2_t i1 o1 i2 tphl tplh i1 nand3_t o1 i2 i3tplh tphl • Interface aspects of inv_t. nand2_t.

im7. FOR ALL : n2 USE ENTITY WORK. im4. lt. g3 : n2 PORT MAP (a.a_lt_b output g9 : n2 PORT MAP (im1. b. g4 : n2 PORT MAP (im2. im4. im7. i2: IN BIT.Intermediate signals SIGNAL im1. a_eq_b). i3: IN BIT. eq. im6.a_eq_b output g6 : n3 PORT MAP (im1. im8. END default_delay. -. g2 : n2 PORT MAP (a. im2. g5 : n3 PORT MAP (im3. eq. g8 : n2 PORT MAP (im6. im6). Zainalabedin Navabi CHAPTER 6 26 . -.im2. im1). im9. im10. g7 : n3 PORT MAP (a. END COMPONENT. FOR ALL : n1 USE ENTITY WORK. im10 : BIT. g1 : n1 PORT MAP (b.Design Parametrization ARCHITECTURE default_delay OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT. im2). COMPONENT n3 PORT (i1. BEGIN -. a_lt_b). im8). o1: OUT BIT). END COMPONENT. im2. FOR ALL : n3 USE ENTITY WORK. im5. b. o1: OUT BIT). g10 : n2 PORT MAP (im1.inv_t (average_delay). END COMPONENT. im9). o1: OUT BIT).nand3_t (average_delay). im10). gt. im5.a_gt_b output g0 : n1 PORT MAP (a. im5). im3. a_gt_b). im4). im7). -.nand2_t (average_delay). • Many alternatives for specifying generics • Using default values for the generics of logic gates • No need to declare and specify generics if they are to use default values © 1999. im9. gt. im3). g12 : n3 PORT MAP (im8. i2. lt. COMPONENT n2 PORT (i1. g11 : n2 PORT MAP (b.

4 NS) PORT MAP (b. lt. g7 : n3 GENERIC MAP (4 NS. g4 : n2 GENERIC MAP (3 NS. 4 NS) PORT MAP (a. END fixed_delay. im5). • If generics are declared without default values. im5.a_lt_b output g9 : n2 GENERIC MAP (3 NS. -. b. im1). im4. im3. END COMPONENT. im6. a_lt_b). 5 NS) PORT MAP (a. 5 NS) PORT MAP (b. PORT (i1. g1 : n1 GENERIC MAP (2 NS. im8). END COMPONENT. Zainalabedin Navabi .im2.a_eq_b output g6 : n3 GENERIC MAP (4 NS. PORT (i1. im7). im9. g2 : n2 GENERIC MAP (3 NS.Design Parametrization ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh. gt. 5 NS) PORT MAP (im6. FOR ALL : n2 USE ENTITY WORK. tphl : TIME).nand3_t (average_delay). im6). a_eq_b). im10 : BIT.a_gt_b output g0 : n1 GENERIC MAP (2 NS. 5 NS) PORT MAP (a. g10 : n2 GENERIC MAP (3 NS. o1: OUT BIT). END COMPONENT. SIGNAL im1. o1: OUT BIT). im4). 6 NS) PORT MAP (im8. im10). PORT (i1: IN BIT. eq. g5 : n3 GENERIC MAP (4 NS. 6 NS) PORT MAP (a. a_gt_b). -. o1: OUT BIT). im9). COMPONENT n2 GENERIC (tplh. tphl : TIME). g12 : n3 GENERIC MAP (4 NS. g11 : n2 GENERIC MAP (3 NS.nand2_t (average_delay). b. im9. 6 NS) PORT MAP (im3. i2: IN BIT. im2. im4. BEGIN -. 6 NS) PORT MAP (im1.inv_t (average_delay). im8. lt. tphl : TIME). FOR ALL : n1 USE ENTITY WORK. im2. im5. im3). g3 : n2 GENERIC MAP (3 NS. FOR ALL : n3 USE ENTITY WORK. 5 NS) PORT MAP (im2. g8 : n2 GENERIC MAP (3 NS. they have to be specified • Associating fixed values with the generics of logic gates • Generic map is shown here CHAPTER 6 27 © 1999. im2). im7. eq. im7. 5 NS) PORT MAP (im1. i2. 5 NS) PORT MAP (im1. gt. i3: IN BIT. COMPONENT n3 GENERIC (tplh. im10.

im2 ) .Design Parametrization g1 : n1 GENERIC MAP ( 2 NS. 4 NS ) PORT MAP ( b. instantiation_label component_name generic map aspect port map aspect association_list component instantiation statement association_list • Syntax details • Component instantiation statement with generic map aspect • Generic map aspect comes first CHAPTER 6 28 © 1999. Zainalabedin Navabi .

END COMPONENT. im6. COMPONENT n2 GENERIC (tplh. b. im8. -. -. FOR ALL : n3 USE ENTITY WORK. -.previous less than a_gt_b. PORT (i1.greater a_eq_b.data inputs gt.previous greater than eq. tphl : TIME).nand2_t (average_delay). -. FOR ALL : n2 USE ENTITY WORK.im2. tphl3 : TIME). BEGIN .inv_t (average_delay). tphl2. i3: IN BIT. im3. i2: IN BIT.. -. • A bit comparator with timing parameters • Passing generics of bit comparator to its components • Bit comparator has generic parameters that must be passed to it CHAPTER 6 29 © 1999. o1: OUT BIT). -. PORT (i1: IN BIT. tphl : TIME).less than END bit_comparator_t. COMPONENT n3 GENERIC (tplh. (a) ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh. END COMPONENT..nand3_t (average_delay). o1: OUT BIT). Zainalabedin Navabi . PORT (a. -. tphl1. im5. i2.previous equal lt : IN BIT.Intermediate signals SIGNAL im1. im7. im4. o1: OUT BIT).Design Parametrization ENTITY bit_comparator_t IS GENERIC (tplh1. tplh3. im9. -. FOR ALL : n1 USE ENTITY WORK. tphl : TIME). END COMPONENT.equal a_lt_b : OUT BIT). PORT (i1. tplh2. im10 : BIT.

im7). a_eq_b).a_lt_b output g9 : n2 GENERIC MAP (tplh2. im7. lt. tphl2) PORT MAP (im2.a_eq_b output g6 : n3 GENERIC MAP (tplh3. b. eq. g12 : n3 GENERIC MAP (tplh3. tphl2) PORT MAP (im1. im9. g11 : n2 GENERIC MAP (tplh2. eq. im3). im6). a_lt_b). tphl3) PORT MAP (a. g8 : n2 GENERIC MAP (tplh2.Design Parametrization . END passed_delay. -. im1). im8).a_gt_b output g0 : n1 GENERIC MAP (tplh1. -. im10). im4. tphl3) PORT MAP (im8. g1 : n1 GENERIC MAP (tplh1. im10. g10 : n2 GENERIC MAP (tplh2. tphl3) PORT MAP (im1. im9). im2). tphl1) PORT MAP (b. tphl3) PORT MAP (im3. im5). a_gt_b). tphl2) PORT MAP (im6. g5 : n3 GENERIC MAP (tplh3. -. tphl1) PORT MAP (a. tphl2) PORT MAP (a. im5. tphl2) PORT MAP (im1. im2. g2 : n2 GENERIC MAP (tplh2. g3 : n2 GENERIC MAP (tplh2. im2. tphl2) PORT MAP (a.. lt. b. tphl2) PORT MAP (b.. • A bit comparator with timing parameters • Gates require generic specification • These override the gate generics CHAPTER 6 30 © 1999. g7 : n3 GENERIC MAP (tplh3. g4 : n2 GENERIC MAP (tplh2. gt. gt. Zainalabedin Navabi . im4).

Zainalabedin Navabi .Design Parametrization bit_comparator_t (passed_delay) a nand2_t i1 (average_delay) o1 i2 im3 tplh tphl nand2_t i1 i2 (average_delay) o1 im4 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_gt_b b inv_t im2 i1 (average_delay)o1 nand2_t i1 i2 (average_delay) tplh tphl o1 tplh tphl im5 gt nand3_t i1 (average_delay) o1 i2 i3 tplh tphl nand3_t i1 (average_delay) i2 o1 i3tplh tphl im6 nand2_t i1 i2 im7 (average_delay) eq lt o1 a_eq_b tplh tphl nand2_t i1 i2 inv_t i1 (average_delay)o1 (average_delay) im8 o1 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_lt_b im1 i1 i2 nand2_t (average_delay) tplh tphl o1 im9 tplh tphl nand2_t i1 i2 (average_delay) o1 tplh tplh2 tphl im10 tplh1 tphl1 tphl2 tplh3 tphl3 • Composition aspect of bit_comparator_t • Dotted lines with arrows indicate generics CHAPTER 6 31 © 1999.

tplh3 : TIME := 4 ns. a_lt_b). im(6). im(1). END iterative. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). eq. im(i*3+1). im(i*3-1). im(i*3+2) ). im(8). tplh1 : TIME := 4 NS. b. a_lt_b : OUT BIT).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 GENERIC ( tplh1 : TIME := 2 NS. im(i*3-3). b(0). END GENERATE. eq. tplh2 :TIME := 5 NS. gt. lt. im(7). b(3). im(i*3-2). FOR ALL : comp1 USE ENTITY WORK. a_eq_b. c3: comp1 PORT MAP (a(3). im(i*3+0). a_eq_b. • Comp1 is declared with default values • Passing default values of local generics to the generics of bit_comparator_t • These values override at the lower levels CHAPTER 6 32 © 1999. Zainalabedin Navabi . SIGNAL im : BIT_VECTOR ( 0 TO 8). PORT (a.bit_comparator_t (passed_delay). b(i). BEGIN c0: comp1 PORT MAP (a(0). END COMPONENT. tplh2 :TIME := 3 NS. im(2)). gt. tplh3 : TIME := 6 ns. a_gt_b. im(0). a_gt_b. lt : IN BIT.

im(0).. eq. OPEN. Zainalabedin Navabi .Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . • Some are associated with OPEN • Associating constants with some of generics of bit_comparator_t. b(0). BEGIN c0: comp1 GENERIC MAP (OPEN. im(2)). OPEN. 10 NS) PORT MAP (a(0). correspond in the order they are listed CHAPTER 6 33 © 1999. OPEN. and using defaults for others • Association by position. lt. .. 8 NS.. END iterative. gt.. im(1).

gt.. b => b(0).. gt. b(0). . im(2)). im(1). END iterative. . tphl3 => 10 NS) PORT MAP (a(0). END iterative. Zainalabedin Navabi .. a_lt_b : OUT BIT). eq. gt => gt. ARCHITECTURE BECOMES: ARCHITECTURE iterative OF nibble_comparator IS . a_gt_b. im(0). tphl3 => 10 NS) PORT MAP (a => a(0). inputs only if default 34 © 1999. lt. a_eq_b => im(1).. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. a_eq_b.Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . b. lt : IN BIT. lt => lt. a_gt_b => im(0). a_lt_b => im(2)). eq => eq.. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS.. SAME FORMAT FOR THE PORTS: PORT AS DECLARED: PORT (a. same mapping as before It must be: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open.. eq. • • • • • CHAPTER 6 Using named association..

500 NS).15. (0. a_eq_b. lss). 500 NS).14. BEGIN a1: comp4 PORT MAP (a.00.00.12. SIGNAL eql. eql. apply_data (b.12. gnd. ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a. gt.00.basic_utilities.15. b : BIT_VECTOR (3 DOWNTO 0).15. apply_data (a. eq. END COMPONENT.15. gnd.Design Configuration USE WORK. SIGNAL gnd : BIT := '0'.15). gtr. Zainalabedin Navabi .10.14. lss. lt : IN BIT.ALL. SIGNAL vdd : BIT := '1'. (0. Customizable architecture for demonstrating configuration declarations • A customizable test bench • Configuration specification is not included • Comp4 is not in our work library CHAPTER 6 35 © 1999.15. END customizable.14. b : IN BIT_VECTOR (3 DOWNTO 0).15. a_lt_b : OUT BIT).15. gtr : BIT.14.15.00. SIGNAL a.14.12.00). vdd.14. b. a_gt_b.

END FOR. END FOR.ALL.nibble_comparator(structural). Zainalabedin Navabi . perform binding CHAPTER 6 36 © 1999. END functional. CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 2 3 USE ENTITY WORK.Design Configuration 1 USE WORK. • Configuring customizable for testing structural architecture of nibble_comparator • Hierarchically enter the architecture.

Zainalabedin Navabi .Design Configuration functional nibble_comparator (structural) nibble_comparator_test_bench (customizable) a1: comp4 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • Graphical representation • Composition aspect for functional configuration declaration. configuring customizable test bench • Pass through hierarchies with arrows CHAPTER 6 37 © 1999.

Zainalabedin Navabi .ALL. END FOR.Design Configuration USE WORK. END average_delay. • Another configuration on top of the test bench • Configuring customizable for testing iterative architecture of nibble_comparator • No need to recompile the test bench CHAPTER 6 38 © 1999. END FOR. CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative).

Design Configuration CONFIGURATION average_delay OF nibble_ comparator_ test_bench IS FOR customizable FOR al : comp4 USE ENTITY WORK. identifier entity_name configuration declaration binding indication component configuration block configuration • Details of configuration declaration • Configuration declaration replaces or adds to a configuration specification • Includes component configuration and block configuration CHAPTER 6 39 © 1999. nibble_comparator (iterative) . END FOR. END FOR. Zainalabedin Navabi . END average_delay.

a_gt_b. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). gt. a_eq_b. eq. im(6). im(i*3+1). SIGNAL im : BIT_VECTOR ( 0 TO 8). im(i*3-3). a_lt_b). c3: comp1 PORT MAP (a(3). END flexible. b(0). a_lt_b : OUT BIT). im(2)). END COMPONENT. gt. im(0). a_eq_b. • A general purpose nibble_comparator • This 4-bit comparator does not use a specific bit comparator • A top-level configuration configures comp1 instantiations CHAPTER 6 40 © 1999. im(7). lt.Design Configuration ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. im(i*3-2). Zainalabedin Navabi . lt : IN BIT. b. im(i*3+0). b(i). im(8). im(i*3-1). b(3). a_gt_b. eq. im(i*3+2) ). BEGIN c0: comp1 PORT MAP (a(0). END GENERATE. im(1).

Design Configuration default_bit_level bit_comparator(default_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) c3: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a1: comp4 a(2) b(2) c2: comp1 a(3:0) b(3:0) gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect for configuring customizable test bench for testing default_delay bit_comparator • Graphical representation of hierarchies CHAPTER 6 41 © 1999. Zainalabedin Navabi .

CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. c3: comp1 USE ENTITY WORK. FOR flexible FOR c0. • Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator • Binding to the default_delay architecture CHAPTER 6 42 © 1999. END FOR. END FOR. END FOR. END default_bit_level.bit_comparator (default_delay).bit_comparator (default_delay). Zainalabedin Navabi . END FOR. END FOR. END FOR.nibble_comparator(flexible).Design Configuration USE WORK.ALL. FOR c1to2 FOR c: comp1 USE ENTITY WORK.

Design Configuration USE WORK.nibble_comparator(flexible).ALL. END FOR. Zainalabedin Navabi . END FOR.bit_comparator (fixed_delay).bit_comparator (fixed_delay). • Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator • Binding to the fixed_delay architecture • Can use ALL or OTHERS CHAPTER 6 43 © 1999. END FOR. END FOR. END FOR. FOR c1to2 FOR c: comp1 USE ENTITY WORK. END FOR. FOR flexible FOR c0. c3: comp1 USE ENTITY WORK. CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END fixed_bit_level.

Zainalabedin Navabi .Design Configuration passed_bit_level bit_comparator_t(passed_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) tplh1 c3: comp1 tplh2 tplh3 a(3:0) b(3:0) gt eq lt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b 2NS 3NS 4NS 4NS 5NS 6NS a1: comp4 a(2) b(2) c2: comp1 tplh1 tplh2 tplh3 a(3:0) b(3:0) gt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(6) im(7) im(8) 2NS 3NS 4NS 4NS 5NS 6NS gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) 2NS 3NS 4NS 4NS 5NS 6NS c1to2: a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) 2NS 3NS 4NS 4NS 5NS 6NS • Composition aspect of the passed_bit_level • Configuration for test bench for testing passed_delay architecture of bit_comparator_t CHAPTER 6 44 © 1999.

nibble_comparator(flexible). tplh2 => 3 NS. tphl1 => 4 NS. tplh3 => 4 NS. FOR flexible FOR c0. tphl3 => 6 NS). END FOR. N FOR c1to2 T FOR c: comp1 A USE ENTITY WORK. S tphl2 => 5 NS.Design Configuration USE WORK.bit_comparator_t (passed_delay) X GENERIC MAP (tplh1 => 2 NS. Zainalabedin Navabi .bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. END FOR. END passed_bit_level. tphl1 => 4 NS. • Using configuration declarations for component bindings.ALL. and specification of generic parameters • Same format for generic map and port map aspects as configuration specification CHAPTER 6 45 © 1999. tplh2 => 3 NS. END FOR. c3: comp1 USE ENTITY WORK. tphl2 => 5 NS. END FOR. END FOR. tplh3 => 4 NS. Y END FOR. CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. tphl3 => 6 NS).

bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. tphl3 => 6 NS). c3: comp1 USE ENTITY WORK. tplh2 => 3 NS. FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tphl1 => 2 NS. tphl3 => 6 NS). END FOR. tplh3 => 4 NS. END FOR. tphl2 => 5 NS. entity aspect component configuration generic map aspect block configuration component configuration block configuration • Details of a block configuration enclosing component configurations and other block configurations • Binding indication and generic map aspect CHAPTER 6 46 © 1999. tphl1 => 4 NS. END FOR. Zainalabedin Navabi . tplh2 => 3 NS. tphl2 => 5 NS. END FOR. tplh3 => 4 NS. tphl1 => 4 NS.Design Configuration FOR flexible FOR c0.

a_gt_b. a_lt_b : OUT BIT). a_eq_b. . ). ). END COMPONENT. . c3: comp1 PORT MAP ( . . . c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( . ). and more with configuration declaration • This is an illustration for the primary binding indication CHAPTER 6 47 © 1999. END GENERATE. . • Can do incremental binding • Do some with configuration specification. lt : IN BIT. BEGIN c0: comp1 PORT MAP ( . Zainalabedin Navabi . END partially_flexible. FOR ALL : comp1 USE ENTITY WORK. SIGNAL im : BIT_VECTOR ( 0 TO 8 ). eq.Design Configuration ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. gt. .bit_comparator_t (passed_delay). b.

tphl1 => 4 NS. • Incremental binding indication illustration • Add generic map aspect to the existing binding • Can use different mappings CHAPTER 6 48 © 1999. tphl1 => 4 NS. END FOR. END FOR. tplh3 => 4 NS. FOR flexible FOR c0. Zainalabedin Navabi .Design Configuration USE WORK. tplh3 => 4 NS. tphl2 => 5 NS. END FOR. CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.ALL. tphl3 => 6 NS). tplh2 => 3 NS. tplh2 => 3 NS. END FOR. END incremental. c3: comp1 GENERIC MAP (tplh1 => 2 NS. FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS. tphl3 => 6 NS). END FOR. tphl2 => 5 NS.nibble_comparator (partially_flexible). END FOR.

im4 : BIT. using a sequential example. im3). im2). END COMPONENT. END sr_latch. g4 : n2 PORT MAP (im3. r. c. q <= im3. im4. im3. im1). g2 : n2 PORT MAP (r. q : OUT BIT). c : IN BIT. c. g3 : n2 PORT MAP (im1. im4). Zainalabedin Navabi . i2: IN BIT. im2. SIGNAL im1. Customizable architecture. END gate_level. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. several levels of hierarchy • A new example. im2.Design Configuration ENTITY sr_latch IS PORT (s. illustrating configurations at several levels of depth • Unbound VHDL description of set-reset latch • Uses the same basic components CHAPTER 6 49 © 1999. o1: OUT BIT). BEGIN g1 : n2 PORT MAP (s.

c2 : n1 PORT MAP (d. q). • • • • Building a D-latch Add an inverter to the SR-latch Unbound VHDL description of a D-latch All gate level components are unbound CHAPTER 6 50 © 1999. c : IN BIT. Zainalabedin Navabi . END COMPONENT. c : IN BIT. dbar. r. SIGNAL dbar : BIT.Design Configuration ENTITY d_latch IS PORT (d. COMPONENT n1 PORT (i1: IN BIT. dbar). q : OUT BIT). q : OUT BIT). c. END sr_based. BEGIN c1 : sr PORT MAP (d. END COMPONENT. o1: OUT BIT). -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr PORT (s. END d_latch.

Zainalabedin Navabi .Design Configuration ENTITY d_register IS PORT (d : IN BIT_VECTOR. END d_register. END latch_based. c. -ARCHITECTURE latch_based OF d_register IS COMPONENT dl PORT (d. q(i)). q : OUT BIT_VECTOR). • Generically generate a register • Unbound VHDL description for an n-bit latch • Configuration specification is not included CHAPTER 6 51 © 1999. END COMPONENT. BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i). c : IN BIT. c : IN BIT. END GENERATE. q : OUT BIT).

Zainalabedin Navabi Sr_latch (gate_level) 4 NS 5 NS 6 NS 2 NS 4 NS 2 NS 4 NS 2 NS 4 NS 5 NS 6 NS .Design Configuration average_gate_delay d_latch(sr_based) inv_ t(average_delay) 2 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 g4: i2 o1 i1 c2: o1 i1 g2: i2 o1 o1 3 NS 5 NS 5 NS 6 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS 5 NS 6 NS nand2_t(average_delay) di: i1 i2 g1: c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS • Composition aspect for configuring the latch_based architecture of d_register • Hierarchical configuration CHAPTER 6 52 © 1999.

g4 : n2 USE ENTITY WORK. END FOR. END FOR. END FOR.nand2_t(average_delay) 10 GENERIC MAP (2 NS. FOR sr_based FOR c1 : sr USE ENTITY WORK. END average_gate_delay.inv_t(average_delay) 7 GENERIC MAP (3 NS. FOR g1. END FOR. CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK. g3 : n2 2 3 4 5 6 8 USE ENTITY WORK.nand2_t(average_delay) 9 GENERIC MAP (5 NS. 4 NS). END FOR.Design Configuration 1 USE WORK. Zainalabedin Navabi . 6 NS). END FOR. • Configuring d_register for using average_delay gates CHAPTER 6 53 © 1999. END FOR.ALL.sr_latch(gate_level). FOR gate_level FOR g2. END FOR. 5 NS). END FOR.d_latch(sr_based). FOR c2 : n1 USE ENTITY WORK.

4. 5.45 c2 instance of sr Figure 6. 4. 5 8 Visibility 1. 6.Design Configuration Block No. 3. 1 Configuration Type Configuration Declaration Block Configuration Block Configuration Component Configuration Block Configuration Component Configuration Component Configuration Block Configuration Component Configuration Component Configuration PURPOSE Visibility or Binding to: Main latch_based ARCHITECTURE Figure 6. g4 of n2 Figure 6. 4. 2.45 c1 instance of sr Figure 6.46 di instance of dl Figure 6.46 dr GENERATE STATEMENT Figure 6.44 instances g1.44 instances g2. 2 4 Binding 1. 3.46 sr_based ARCHITECTURE Figure 6.44 Becomes Visible by: - 2 Visibility 1 3 Visibility 1. 5. 3. 4 6 Binding 1. 4. 3. Zainalabedin Navabi . 6 9 Binding 1. 2. 6. 2. 2.45 gate_level ARCHITECTURE Figure 6. 4. g3 of n2 Figure 6. 2. 8 10 Binding 1. 3 5 Visibility 1. 8 • Analyzing configuration constructs of the average_gate_delay configuration of d_register • Configuration declaration includes component configurations and block configurations CHAPTER 6 54 © 1999. 2. 3. 3. 5. 5 7 Binding 1. 2.

g3 : n2 USE ENTITY WORK. FOR c2 : n1 USE ENTITY WORK.ALL. END FOR.inv(single_delay). END FOR. END FOR. CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK. END FOR. END FOR. END FOR. o1). END FOR.d_latch(sr_based). FOR gate_level FOR g2. FOR sr_based FOR c1 : sr USE ENTITY WORK. END FOR. i1. • Configuring d_register for using single_delay architectures of inv and nand2 • Deep inside to reach basic gates and their generic parameters CHAPTER 6 55 © 1999. FOR g1.Design Configuration USE WORK.nand2(single_delay). i2.nand3(single_delay) PORT MAP (i1.sr_latch(gate_level). END FOR. Zainalabedin Navabi . END single_gate_delay. g4 : n2 USE ENTITY WORK.

FOR r8 : reg USE CONFIGURATION WORK. • Demonstrating the use of configurations in configuration specifications • Test bench for the single_delay architecture of d_register CHAPTER 6 56 © 1999. outdata : BIT_VECTOR (7 DOWNTO 0). '1' AFTER 1700 NS. q : OUT BIT_VECTOR (7 DOWNTO 0) ). X"55" AFTER 1500 NS. clk <= '0'. END COMPONENT. '0' AFTER 0300 NS. SIGNAL data. data <= X"00".single_gate_delay. c : IN BIT. SIGNAL clk : BIT. '1' AFTER 0200 NS.Design Configuration ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0). '0' AFTER 0800 NS. outdata). '1' AFTER 0700 NS. '0' AFTER 1800 NS. X"AA" AFTER 0500 NS. BEGIN r8: reg PORT MAP (data. END single. Zainalabedin Navabi . clk.

Design Configuration a(0) im(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) im(1) im(2) im(3) im(4) im(5) im(6) odd even One more configuration declaration example. Zainalabedin Navabi . iterative hardware • The final example • Will illustrate indexing for alternative binding • Parity generator/checker circuit CHAPTER 6 57 © 1999.

END inv_t.Design Configuration ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS. END xor2_t. o1 : OUT BIT). ---ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. END average_delay. • Components needed for this design • Timed XOR and INV gates needed for the design of the parity circuit CHAPTER 6 58 © 1999. PORT (i1 : IN BIT. END average_delay. Zainalabedin Navabi . -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. tphl : TIME := 7 NS). PORT (i1. -ARCHITECTURE average_delay OF xor2_t IS BEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2. tphl : TIME := 3 NS). o1 : OUT BIT). i2 : IN BIT.

Design Configuration ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0). END parity. even : OUT BIT). last: odd <= im(6). a(1). SIGNAL im : BIT_VECTOR ( 0 TO 6 ). odd. END COMPONENT. END iterative. middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1). even). END GENERATE. inv: n1 PORT MAP (im(6). -ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT (i1. BEGIN first: x2 PORT MAP (a(0). im(0)). Zainalabedin Navabi . • Parity circuit description • No configuration specification for the inverter and the exclusive OR gate CHAPTER 6 59 © 1999. i2: IN BIT. o1: OUT BIT). im(i)). END COMPONENT. o1: OUT BIT). COMPONENT n1 PORT (i1: IN BIT. a(i+1).

5 NS). END FOR.xor2_t (average_delay) GENERIC MAP (6 NS. END FOR.Design Configuration CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS. • Parity circuit configuration declaration • Index label of the generate statement • Can use OTHERS. END FOR. 7 NS). FOR middle ( 6) FOR m : x2 USE ENTITY WORK. END parity_binding. FOR inv : n1 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS.inv_t (average_delay) GENERIC MAP (5 NS. 5 NS). pick some. and OTHERS the rest CHAPTER 6 60 © 1999. 5 NS). END FOR. FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK. Zainalabedin Navabi . END FOR. END FOR. END FOR.

start with the nine-value standard logic • None standard values • Std_logic logic value system • Satisfies most hardware design needs CHAPTER 6 61 © 1999. Zainalabedin Navabi .Use of Libraries Value 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' Representing Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care Standard and user libraries.

U X 0 1 Z W L H - U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U' X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' 0 '0' '0' '0' '0' '0' '0' '0' '0' '0' 1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' L '0' '0' '0' '0' '0' '0' '0' '0' '0' H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' 'U’ 'X' '0' 'X’ 'X' 'X' '0' 'X' 'X' • AND table for std_logic type • All logic tables are defined and available • Changing BIT to std_logic works in most cases CHAPTER 6 62 © 1999. Zainalabedin Navabi .Use of Libraries .

tphl : TIME := 4 NS).ALL. Zainalabedin Navabi .std_logic_1164. END average_delay_mvla.Use of Libraries LIBRARY IEEE. PORT (i1. i2 : IN std_logic. USE IEEE. -ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. • A two-input NAND gate in std_logic value system • Specify library and package • All basic functions are available in this package CHAPTER 6 63 © 1999. -ARCHITECTURE average_delay_mvla OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. END nand2_t. o1 : OUT std_logic).

1997 June 8. entities and architectures CHAPTER 6 64 © 1999. Zainalabedin Navabi . 1997 June 6. 1997 June 6. 1997 June 8. 1997 June 6. 1997 June 6.Use of Libraries LIBRARY ls7400 simple_gates inv inv(single_delay) nand2 nand2(single_delay) nand3 nand3(single_delay) User: John Designer PACKAGE DECLARATION ENTITY ARCHITECTURE ENTITY ARCHITECTURE ENTITY ARCHITECTURE Date June 9. 1997 • Other libraries • Can define our own • Directory of ls7400 library containing package declarations.

• Visibility of user libraries and packages • Making all declarations of simple_gates package of ls7400 library available CHAPTER 6 65 © 1999. STD is the standard library that includes the STANDARD and TEXTIO packages All other libraries and packages must be explicitly specified Use ls7400 as a user defined library LIBRARY ls7400. USE ls7400.simple_gates. Zainalabedin Navabi .Use of Libraries • • • • WORK is the default library.ALL.

g4 : n2 PORT MAP (im3. • Using user libraries • Using component declarations of simple_gates package of ls7400 library for description of set-reset latch CHAPTER 6 66 © 1999. -ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1. im1).simple_gates. g2 : n2 PORT MAP (r. g3 : n2 PORT MAP (im1. im2. im2. Zainalabedin Navabi .Use of Libraries LIBRARY ls7400.ALL. c. im2). USE ls7400. im4). im3. BEGIN g1 : n2 PORT MAP (s. im4 : BIT. END gate_level. q <= im3. im3). im4. c.

Use of Libraries LIBRARY ls7400. Zainalabedin Navabi . • Visibility into libraries • Making all entities and architectures of the ls7400 library available CHAPTER 6 67 © 1999.ALL. USE ls7400.

• Binding indication needs library name • Using a component configuration for associating g1 and g3 instances of n2 of Figure 661 with nand2 of ls7400 CHAPTER 6 68 © 1999.Use of Libraries LIBRARY ls7400.nand2 (single_delay). . . g3 : n2 … USE ENTITY ls7400. Zainalabedin Navabi . … FOR g1. USE ls7400. … END FOR.ALL.

Although simple examples and college level exercises can avoid some of these language issues. We believe VHDL is very strong in this area and serious designers should learn to take advantage of such capabilities of the language. We began with the definition of subprograms and emphasized on the use of functions and procedures for simplifying descriptions. the subject of packaging utilities and components was addressed. this topic is used mainly for the organization of a design. design parameterization methods save many compilation runs. • End Of Chapter 6 CHAPTER 6 69 © 1999. For small circuits and experimental models. Zainalabedin Navabi . Next. a large design environment with many logic families and technologies to choose from requires a great deal of library management and parameter specification.Summary This chapter provides tools for better hardware descriptions and design organization. As stated earlier. Design parameterization and configuration of designs were also discussed in great detail.

2.5.7 PACKAGING BASIC UTILITIES 7.6 Type Conversions 7.1.4.4 Access Types 7.1 Subtypes 7.2 Record Types 7.3 Physical Types and RC Timing 7.6 USER-DEFINED ATTRIBUTES 7.4. Navabi and McGraw-Hill Inc.2.2 Relational Operators 7.2 VHDL OPERATORS 7.2 Type Attributes 7.5.4.2.2 Using Real Numbers For Timing Calculations 7.1.5 PREDEFINED ATTRIBUTES 7. Global Objects 7.1.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING 7.3 Alias Declaration 7.4 Entity Attributes 7.5.4. .1.5.6 Multiplying Operators 7.CHAPTER 7 UTILITIES FOR HIGH LEVEL DESCRIPTIONS 7.4 Adding Operators 7.5 Sign Operators 7.4.2.1 TYPE DECLARATIONS AND USAGE 7.1 Logical Operators 7.2.3 Shift Operators 7.4 OTHER TYPES AND TYPE RELATED ISSUES 7.2.2.8 Aggregate Operation 7.5.8 SUMMARY CHAPTER 7 1 © 1999.5 File Type and External File I/O 7.1.4.3 Signal Attributes 7.2.7 Nota Operators 7. Z.1 Array Attributes 7.4 Array Declarations 7.1 Enumeration Type for Multi-Value Logic 7.

‘X’ ) . ‘1’ .TYPE DECLARATIONS AND USAGE TYPE qit IS ('0'. identifier enumeration element enumeration element enumeration element enumeration element enumeration type definition type definition type declaration Will use an enumeration type for demonstrating type declarations • 4-value qit type will be used • Enumeration type declaration • Initial value of objects of this type is the left-most enumeration element of the base type CHAPTER 7 2 © 1999. . 'X'). ‘Z’ . Navabi and McGraw-Hill Inc. 'Z'. initial TYPE qit IS ( ‘0’ . '1'. Z.

.TYPE DECLARATIONS AND USAGE In: 0 1 Z X 1 0 0 X Out • Will develop basic logic gates based on this type • Input-Output mapping of an inverter in qit logic value system CHAPTER 7 3 © 1999. Navabi and McGraw-Hill Inc. Z.

basic_utilities. END inv_q. Z. o1 : OUT qit). tphl : TIME := 3 NS).ALL.TYPE DECLARATIONS AND USAGE USE WORK. -. END double_delay. • VHDL description of an inverter in qit logic value system • Inputs and outputs are of type qit • Assumes out package contains this type definition CHAPTER 7 4 © 1999.From PACKAGE USE : qit ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS. -ARCHITECTURE double_delay OF inv_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. PORT (i1 : IN qit. . Navabi and McGraw-Hill Inc.

• • • • A new construct is presented This is conditional signal assignment Several alternatives exist in its usage Can use unaffected for assignments to outputs CHAPTER 7 5 © 1999. Z.TYPE DECLARATIONS AND USAGE Z <= a AFTER 5 NS WHEN d = ’1’ ELSE UNAFFECTED WHEN e = ’1’ ELSE b AFTER 5 NS WHEN f = ’1’ ELSE c AFTER 5 NS. or o1 <= a WHEN cond =’1’ ELSE UNAFFECTED. o1<= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE UNAFFECTED. Navabi and McGraw-Hill Inc. . o1 <= a WHEN cond =’1’ ELSE o1.

target waveform condition waveform condition waveform condition waveform conditional signal assignment • Syntax details of a conditional signal assignment • Condition waveform has a series of waveforms with or without condition CHAPTER 7 6 © 1999.TYPE DECLARATIONS AND USAGE o1 <= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE ‘X’ AFTER tplh . Z. . Navabi and McGraw-Hill Inc.

TYPE DECLARATIONS AND USAGE In1: In2: 0 1 Z X 0 1 1 1 1 1 1 0 0 X Out Z 1 0 0 X 1 X X X X • We will develop more basic structures in this 4-value logic system • Input-Output mapping of a NAND gate in qit logic value system • Here we assume 1 for high impedance © 1999. Navabi and McGraw-Hill Inc. CHAPTER 7 7 . Z.

.ALL. END double_delay. END nand2_q. • • • • VHDL description of a NAND gate in qit logic system A conditional signal assignment is used This is a concurrent statement Conditions are checked sequentially from left to right CHAPTER 7 8 © 1999. Z. -ARCHITECTURE double_delay OF nand2_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh. -.basic_utilities.Can Use: UNAFFECTED. PORT (i1. tphl : TIME := 5 NS). -. i2 : IN qit.TYPE DECLARATIONS AND USAGE USE WORK. Navabi and McGraw-Hill Inc.FROM PACKAGE USE : qit ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS. o1 : OUT qit).

.TYPE DECLARATIONS AND USAGE inv_rc(double_delay) c_load 25K Ω i1 15K Ω o1 A CMOS inverter example for demonstrating floating point and physical types • • • • Composition aspect of an inverter with RC timing Timing depends on the R and C values Exponential timing is ≅ 3RC Will first demonstrate floating point numbers CHAPTER 7 9 © 1999. Navabi and McGraw-Hill Inc. Z.

Farads PORT (i1 : IN qit. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. -.Ohms CONSTANT rpd : REAL := 15000. Navabi and McGraw-Hill Inc.Ohms END inv_rc. CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1.066E-12). CONSTANT rpu : REAL := 25000.basic_utilities.ALL.0. -. o1 : OUT qit). END double_delay. Z.0.0E15) * 3 FS. -.FROM PACKAGE USE: qit ENTITY inv_rc IS GENERIC (c_load : REAL := 0. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1. • An inverter model with RC timing parameters • Delay cannot be a fraction of FS • Delay values are calculated based on pull-up. oull-down and load capacitance • Constant values are used in the conditional signal assignment CHAPTER 7 10 © 1999.0E15) * 3 FS. -.TYPE DECLARATIONS AND USAGE USE WORK. .

Z. far = 1000 mfr. . nfr = 1000 pfr.TYPE DECLARATIONS AND USAGE TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr.Femto Farads (base unit) pfr = 1000 ffr. Navabi and McGraw-Hill Inc. mfr = 1000 ufr. • • • • Type definition for defining the capacitance physical type Use physical types instead of floating point Base unit must be there All others are then defined CHAPTER 7 11 © 1999. END UNITS. kfr = 1000 far. ufr = 1000 nfr. -.

TYPE DECLARATIONS AND USAGE TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o. END UNITS.Milli-Ohms (base unit) ohms = 1000 l_o. Z. m_o = 1000 k_o. k_o = 1000 ohms. • Type definition for defining the resistance physical type • Another physical type • RANGE specifies the largest value in terms of base units that an object of this type can get • Intermediate values can take larger values CHAPTER 7 12 © 1999. g_o = 1000 m_o. -. Navabi and McGraw-Hill Inc. .

CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000. o1 : OUT qit). capacitance ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). -. END inv_rc. CONSTANT rpd : resistance := 15000 ohms. • Using resistance and capacitance physical types in the description of an inverter • Resolutions of Millie-ohms and Femto-farads are taken into account • Divide by 1000 adjusts the time units to FS • Will do it with a better style later CHAPTER 7 13 © 1999. Navabi and McGraw-Hill Inc. Z.FROM PACKAGE USE: qit. .basic_utilities.ALL. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. PORT (i1 : IN qit. END double_delay.TYPE DECLARATIONS AND USAGE USE WORK. resistance. CONSTANT rpu : resistance := 25000 ohms. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000.

TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit. Demonstrating array definition and object declaration • • • • Declaring array types Arrays may be ascending or descending Objects can be indexed as declared n-dimensional arrays may be declared CHAPTER 7 14 © 1999.TYPE DECLARATIONS AND USAGE TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit. Z. . 0 TO 7 ) OF qit. Navabi and McGraw-Hill Inc. TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble. TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit. TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0.

identifier range discrete range index constrained constraint array definition type declaration element_subtype_indication • Syntax details of an array type declaration • This is a type declaration • Contains constraint array definition CHAPTER 7 15 © 1999. Z. . Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit .

Navabi and McGraw-Hill Inc. OTHERS => ‘1’). Z. 3 TO 4 => ‘X’. OTHERS => ‘1’). SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. all elements are initialized to left-most of array element • Can form a vector of initial values • Can use aggregate operation. ‘Z’. association by name CHAPTER 7 16 © 1999.TYPE DECLARATIONS AND USAGE SIGNAL sq8 : qit_byte := "ZZZZZZZZ". ‘1’. SIGNAL sq8 : qit_byte := (5 => ‘Z’. association by position • Can use aggregate operation. ‘Z’. ‘1’. SIGNAL sq8 : qit_byte := (‘Z’. OTHERS => ‘1’). SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. ‘1’). • Objects of array type may be initialized when declared • If explicit initialization is missing. . ‘1’. ‘Z’.

sq4(1).right rotate sq8.-. -. SIGNAL sq_4_8 : qit_4by_8. -.lower right bit of sq_4_8 into sq1. -. sq8(5)). -. Navabi and McGraw-Hill Inc. Z. sq8(3).middle 8 bit slice of sq16 to sq8. sq1 <= sq_4_8 (0. sq16 (15 DOWNTO 12) <= sq4. SIGNAL sq8 : qit_byte. SIGNAL sq_nibble_8 : qit_nibble_by_8. . Valid Operations: sq8 <= sq16 (11 DOWNTO 4). -.sq4 into left 4 bit slice of sq16. (sq4(0). sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5).nibble 2. -. sq8(4).reversing sq8 into sq4. SIGNAL sq4 : qit_nibble. sq1 <= sq_nibble_8(2)(3). sq8 <= sq8(0) & sq8 (7 DOWNTO 1). SIGNAL sq16 : qit_word.reversing sq8 into sq4.reversing sq8 into sq4. -. sq4 <= sq_nibble_8 (2). 7). sq4(3)) <= sq8 (5 DOWNTO 2). bit 3 of sq_nibble_8 into sq1.third nibble (number 2) of sq_nibble_8 into sq4.TYPE DECLARATIONS AND USAGE Signal Declarations: SIGNAL sq1 : qit. sq4(2). -. sq4 <= (sq8(2). • • • • • Signal declarations and signal assignments Arrays may be sliced and used on RHS or LHS Aggregate may be used on RHS and LHS Can concatenate any length or slice size Aggregates operation works with array elements only CHAPTER 7 17 © 1999.

Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE Concatenation example: sq4: 3 2 1 0 sq8: 7 6 5 4 3 2 1 0 sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5). reversing bits of sq8 and assigning them to sq4 • Cannot index opposite to what the type is defined as. Nice try! • An slicing example is also shown here CHAPTER 7 18 © 1999. Slice example: sq_nibble_8(2)(3 DOWN To 2) • Referencing bits of a vector. Z. .

• Initializing or assignment to a two dimensional array • Right most index applies to deepest set of parenthesis • Can initialize the same way as signal and variable assignment • Constants must have static values CHAPTER 7 19 © 1999. 'Z'. '1'. '1'. 'X'. . 'X'. '0' ) ). '1'. 'Z'.TYPE DECLARATIONS AND USAGE SIGNAL sq_4_8 : qit_4by8 := ( ( '0'. ( '1'. '0'. (OTHERS => (0 TO 1 => ‘1’. 'X'. ( 'Z'. 'Z'. '1'. 0 => (OTHERS => ‘X’). '1'. 7 => ‘X’. (OTHERS => (0 TO 1 => ‘1’. 'X' ). '1'. 'Z'. OTHERS =>’0’)). '0'. 'X'. '0'. 'X'. '0'. Navabi and McGraw-Hill Inc. '0'. ( 'X'. 'Z'. '1' ). OTHERS => (0 => ‘X’. … := (OTHERS => (OTHERS => ‘0’)) sq_4_8 <= ( 3 => (OTHERS => ‘X’). (OTHERS => (OTHERS => ‘Z’)). OTHERS =>’1’). 'Z'. SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := (OTHERS => “11000000”). '0'. 'Z' ). Z. 'X'. OTHERS =>’0’)).

‘X’ => (‘0’ => ‘1’. OTHERS => ‘X’). . CONSTANT qit_nand2_table : qit_2d := ( ‘0’ => (OTHERS => ‘1’). Navabi and McGraw-Hill Inc. Z. ‘X’ => ‘1’. Demonstrating non-integer RANGE and index specification • Instead of integers.TYPE DECLARATIONS AND USAGE TYPE qit_2d IS ARRAY (qit. qit) OF qit. OTHERS => (‘0’ => ‘1’. OTHERS =>’0’)). can use other types for array range specification • Then an object of this type may be indexed by enumeration elements of the type in the array range specification CHAPTER 7 20 © 1999.

'X')).'1'. -ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1'.'X').'0'.'X'.ALL.'X'. ('1'. qit_2d ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS. . -. PORT (i1. tphl : TIME := 5 NS). BEGIN o1 <= qit_nand2_table (i1.'1'. i2 : IN qit. Z.FROM PACKAGE USE: qit. END nand2_q. o1 : OUT qit).TYPE DECLARATIONS AND USAGE USE WORK.'0'. ('1'. END average_delay.'0'. Navabi and McGraw-Hill Inc.basic_utilities. i2) AFTER (tplh + tphl) / 2. ('1'.'X'). • Using qit enumeration type for the discrete range of a two-dimensional array • The constant table is an array qit qit if qit elements CHAPTER 7 21 © 1999.'0'.'1').

Z. TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER. Unconstrained array declarations.TYPE DECLARATIONS AND USAGE TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT. Navabi and McGraw-Hill Inc. usage and definition • BIT_VECTOR is a predefined unconstrained array of BITs • STRING is that of CHARACTERS • Can define our own • This is read as RANGE Box CHAPTER 7 22 © 1999. . TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER.

.TYPE DECLARATIONS AND USAGE TYPE integer_vector IS ARRAY ( NATURAL RANGE <> ) OF INTEGER . Nice try! CHAPTER 7 23 © 1999. Navabi and McGraw-Hill Inc. Z. identifier type_mark index_subtype definition unconstrained array definition type declaration element_subtype_indication • Syntax details of an unconstrained array declaration • We will use this array in our basic utilities • Cannot have unconstrained array of an unconstrained array.

Z. target <= TRANSPORT buf AFTER i * period. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE). Navabi and McGraw-Hill Inc. BEGIN FOR i IN values'RANGE LOOP int2bin (values(i).TYPE DECLARATIONS AND USAGE PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR. END apply_data. • • • • A generic version of the apply_data procedure Uses our own integer_vector from basic_utilities Procedure output. buf). END LOOP. target. is also unconstrained All will be known when procedure is called CHAPTER 7 24 © 1999. . CONSTANT values : IN integer_vector.

a_lt_b). . SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). eq. BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). im(0). im(i*3-1). FOR ALL : comp1 USE ENTITY WORK. im(i*3-1). a_lt_b : OUT BIT). b(i). im(1). a_lt_b : OUT BIT). im(i*3-3). b(i). END structural. gt. gt. END GENERATE. END GENERATE.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator IS PORT (a. Navabi and McGraw-Hill Inc. gt. a_eq_b. eq. im(i*3-2). lt. im(i*3+2) ).bit_comparator (functional). Z. b : IN BIT_VECTOR. b. • • • • Keeping our promise of a better n-bit comparator An n-bit comparator Wiring n number of one-bit comparators The integer n depends on the size of a CHAPTER 7 25 © 1999. a_eq_b. b(i). eq. END GENERATE. a_eq_b. a_gt_b. im(i*3+1). END COMPONENT. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). im(i*3-3). im(i*3+0). CONSTANT n : INTEGER := a'LENGTH. a_gt_b. END GENERATE. lt : IN BIT. a_gt_b. END n_bit_comparator. im(i*3-2). lt : IN BIT. -ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a. im(2) ).

lss). b : IN bit_vector. -. b. • Using generic apply_data procedure for testing n_bit_comparator • All unconstrained arrays are fixed according to the parameters passed to them • Can use different size integer vectors CHAPTER 7 26 © 1999. lss.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator_test_bench IS END n_bit_comparator_test_bench . . eql. gnd. 00&15&57&17. gnd.basic_utilities. gtr : BIT. gtr. -USE WORK. gt. apply_data (a. 500 NS). SIGNAL a. lt : IN BIT. vdd. FOR a1 : comp_n USE ENTITY WORK.n_bit_comparator(structural). 500 NS). Z. apply_data (b. a_lt_b : OUT BIT). a_gt_b. END procedural. SIGNAL vdd : BIT := '1'.ALL. END COMPONENT. SIGNAL gnd : BIT := '0'.FROM PACKAGE USE: apply_data which uses integer_vector ARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a. 00&43&14&45&11&21&44&11. BEGIN a1: comp_n PORT MAP (a. b : BIT_VECTOR (5 DOWNTO 0). Navabi and McGraw-Hill Inc. a_eq_b. eq. SIGNAL eql.

Then a logical file name must be declared FILE input_logic_value_file1: logic_data.TYPE DECLARATIONS AND USAGE First. Z. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER. .dat”. Navabi and McGraw-Hill Inc. --Just declare a logical file FILE input_logic_value_file2: logic_data IS “input. WRITE_MODE or APPEND_MODE CHAPTER 7 27 © 1999.dat”. --Declare a logical file and open with the specified mode Primitive utilities for file declaration and file specification • input_logic_value_file: logical name for file of logic_data type • An explicit OPEN statement must be used for opening • Can open a file in READ_MODE. --Declare a logical file and open in READ_MODE FILE input_logic_value_file3: logic_data OPEN READ_MODE IS “input.

the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER. WRITE_MODE or APPEND_MODE CHAPTER 7 28 © 1999. Z. . Then a logical file name must be declared FILE output_logic_value_file1: logic_data.TYPE DECLARATIONS AND USAGE First. Navabi and McGraw-Hill Inc. --Just declare a logical file.dat”. --Declare a logical file and open with the specified mode OUPUT FILE : WRITE_MODE or APPEND MODE • An explicit OPEN statement must be used for opening the file in the first alternative • Can open a file in READ_MODE. open later FILE output_logic_value_file2: logic_data OPEN WRITE_MODE IS “input.

output_logic_value_file. “input.dat”. WRITE_MODE). FILE_CLOSE (output_logic_value_file). STATUS_ERROR. MODE_ERROR) Closing a file: FILE_CLOSE (input_logic_value_file). “output. “output.TYPE DECLARATIONS AND USAGE An explicit OPEN is needed if file is not implicitly opened FILE_OPEN (input_logic_value_file. The standard package includes: TYPE FILE_OPEN_STATUS IS (OPEN_OK. READ_MODE).dat”. . • File open alternatives • Status parameter must be declared first • Close a file using its logical name CHAPTER 7 29 © 1999. Navabi and McGraw-Hill Inc. FILE_OPEN (output_logic_value_file. Z. NAME_ERROR.dat”. WRITE_MODE). FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS.

period : IN TIME) IS VARIABLE char : CHARACTER. END assign_bits. .bit". END IF.TYPE DECLARATIONS AND USAGE PROCEDURE assign_bits ( SIGNAL s : OUT BIT. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. Calling this procedure: assign_bits (a_signal. 1500 NS). FILE input_value_file : logic_data. Navabi and McGraw-Hill Inc. ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current. file_name : IN STRING. • file_name is a string input containing physical file name • A procedure for reading characters from a file and assigning them to a BIT type • File type is declared in the procedure • En explicit open statement is used CHAPTER 7 30 © 1999. Z. BEGIN FILE_OPEN (input_value_file. IF char = '0' THEN s <= TRANSPORT '0' AFTER current. END IF. END LOOP. IF char = '0' OR char = '1' THEN current := current + period. "unix_file. READ_MODE). file_name. VARIABLE current : TIME := 0 NS. char).

declare a file object outside of the procedure CHAPTER 7 31 © 1999. this_file : IN FILE). . • In the previous example. Call the pocedure: read_from_file (SIGNAL target : OUT BIT. because a new file object is declared each time it is called • To avoid.bit”.TYPE DECLARATIONS AND USAGE Declare in an architecture: FILE input_value_file: logic_data IS “my_file. it reads the entire unix_file. Navabi and McGraw-Hill Inc. when assign_bits is called. Z.bit • Each time reading begins from the top of the file.

NOR. NAND. x <= “XOR” (a. x_vector <= a_vector AND b_vector. XOR. NOT Examples of use: x <= a XNOR b. b). Outlining VHDL operators and their format of use • Logical operators • Order of operand must remain the same • The second format makes operands appear as functions CHAPTER 7 32 © 1999.VHDL OPERATORS Logical Operators: AND. XNOR. b_vector). Z. x_vector <= “AND” (a_vector. OR. . Navabi and McGraw-Hill Inc.

<=. >. . and >=) when used with array operands perform ordering operations • These return TRUE or FALSE based on values of array elements starting from the left CHAPTER 7 33 © 1999. >= Examples of use: a_boolean <= i1 > i2. Navabi and McGraw-Hill Inc. Z. --if a_bit_vector is “00011” and b_bit_vector is “00100” a_bit_vector < b_bit_vector returns TRUE --for qitt: ‘0’ is less than ‘1’.VHDL OPERATORS Relational operators: =. /=. >. <. b_boolean <= i1 /= i2. and ‘X’ is larger all the rest --for BIT: ‘1’ is greater than ‘0’ • = and /= operate on operands of any type • (<. <=.

. Navabi and McGraw-Hill Inc.VHDL OPERATORS SLL SLA SRL SRA ROL ROR Shift/Rotate Shift Shift Shift Shift Rotate Rotate Left/Right Left Left Right Right Left Right Logical/Arithmetic Logical Arithmetic Logical Arithmetic Logical Logical VHDL operators are formally presented in the next few slides • Shift operators • operand SIFT_OPERATOR number_of_shifts • fill value is the left-most enumeration element CHAPTER 7 34 © 1999. Z.

VHDL OPERATORS Start with aq aq SLL 1 aq SLA 1 aq SRL 1 aq SRA 1 aq ROL 1 aq ROR 1 Z 0 0 0 Z 0 X 0 1 1 Z Z 1 Z 1 X X 0 0 X 0 X Z Z 1 1 Z 1 Z 1 1 X X 1 X 1 0 0 Z Z 0 Z 0 X X 1 1 X 1 X 0 X 0 0 Z 0 • Application of shift operators • The result must be placed in a LHS • Left operand remains unchanged CHAPTER 7 35 © 1999. Navabi and McGraw-Hill Inc. . Z.

both integers a_int REM b_int -. multiplying. & Multiplying operators: *.returns remainder of absolute value division (a.VHDL OPERATORS Adding operators: +. /. MOD. like concatenation. ABS Examples of use: a+b “+” (a. **. b) a_int MOD b_int -. Navabi and McGraw-Hill Inc. b. REM Other operators: (). Z. aggregate and other operators • Format of use is shown for each operator CHAPTER 7 36 © 1999. . but allows only elements • Adding. -. c) – aggregate.

OR. Z. and NOT for qit as easily as for BIT • Tables for the basic logic functions in the qit four value logic system CHAPTER 7 37 © 1999. Navabi and McGraw-Hill Inc.b (a) a: b: 0 1 Z X 0 0 1 1 X 1 1 1 1 1 Z 1 1 1 1 X X 1 1 X Z 0 1 1 X 0 X X X X z=a+b (b) a: 0 1 Z X 1 0 0 X z = a' Demonstrating overloading VHDL operators and subprograms (c) • Want to use AND. .SUBPROGRAM PARAMETER TYPES AND OVERLOADING a: b: 0 1 Z X 0 0 0 0 0 1 0 1 1 X z = a.

Navabi and McGraw-Hill Inc. TYPE qit_2d IS ARRAY (qit. 'X'). qit) OF qit. -- FUNCTION "AND" (a. FUNCTION "NOT" (a : qit) RETURN qit. • In a package declare qit and arrays based on this type • Declare functions to be overloaded • Overloading: identify a function with its operands and name CHAPTER 7 38 © 1999. TYPE qit_1d IS ARRAY (qit) OF qit.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. b : qit) RETURN qit. FUNCTION "OR" (a. b : qit) RETURN qit. '1'. Z. 'Z'. .

'0').'1'. END "NOT". ('0'.SUBPROGRAM PARAMETER TYPES AND OVERLOADING FUNCTION "AND" (a. . b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0'. ('0'.'X').'1'.'X')). ('1'. ('1'.'X').'1'.'1'. b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0'.'1'.'X'). b).'1'.'1'. FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1'.'0'. b). Navabi and McGraw-Hill Inc. FUNCTION "OR" (a. • Overloading basic logical functions for the qit four value logic system • Definition of functions CHAPTER 7 39 © 1999. END "OR".'1'.'1'.'X').'X')). BEGIN RETURN qit_or_table (a.'X'.'1'. BEGIN RETURN qit_and_table (a.'0'.'0'. ('X'. ('0'. END "AND".'1'.'1').'1').'1'.'X'. BEGIN RETURN qit_not_table (a).'0'. Z.

Navabi and McGraw-Hill Inc. • Using overloaded operators • Cannot use NAND since it is only defined for BIT CHAPTER 7 40 © 1999. o1 : OUT qit). -. -ARCHITECTURE average_delay OF inv_q IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. -.ALL. "NOT" ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS. "AND" ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS.FROM PACKAGE USE: qit.basic_utilities. USE WORK.basic_utilities. END inv_q. END average_delay.ALL. i2 : IN qit. PORT (i1.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. o1 : OUT qit). Z. -ARCHITECTURE average_delay OF nand2_q IS BEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2. . END average_delay. PORT (i1 : IN qit.FROM PACKAGE USE: qit. tphl : TIME := 4 NS). tphl : TIME := 3 NS). END nand2_q.

FROM PACKAGE USE: qit. Navabi and McGraw-Hill Inc.basic_utilities. -. END nand3_q. -ARCHITECTURE average_delay OF nand3_q IS BEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. . tphl : TIME := 5 NS). • Basic gates in the qit logic value system using overloaded AND operators • Can also overload NAND and other operators • Std_logic has done this for its types CHAPTER 7 41 © 1999. o1 : OUT qit). i2.ALL. END average_delay. "AND" ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS. PORT (i1. Z. i3 : IN qit.

Z. Navabi and McGraw-Hill Inc. In a package body: FUNCTION "*" (a : resistance. the "*" subprogram body and CHAPTER 7 42 © 1999. b : capacitance) RETURN TIME. b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000. . END "*".SUBPROGRAM PARAMETER TYPES AND OVERLOADING In the declaration: FUNCTION "*" (a : resistance. • Overloading the multiplication operator • Returns TIME when multiplying resistance capacitance physical types • Function declaration.

Navabi and McGraw-Hill Inc.ALL. • Using the overloaded multiplication operator • The double_delay architecture of inv_rc CHAPTER 7 43 © 1999. resistance.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. capacitance. PORT (i1 : IN qit. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. END double_delay. Z.basic_utilities. o1 : OUT qit). -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3. END inv_rc. "*" ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). CONSTANT tphl : TIME := rpd * c_load * 3. . CONSTANT rpu : resistance := 25 k_o. CONSTANT rpd : resistance := 15 k_o.FROM PACKAGE USE: qit. -.

END LOOP. char). PROCEDURE assign_bits ( SIGNAL s : OUT qit. period : IN TIME). Navabi and McGraw-Hill Inc. • Overloading the assign_bits procedure for accepting and producing qit data • Procedure and other necessary declarations • Subprogram body uses a case statement CHAPTER 7 44 © 1999. Z. . WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. current := current + period.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. file_name : IN STRING. WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current. WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current. BEGIN FILE_OPEN (input_value_file. WHEN '1' => s <= TRANSPORT '1' AFTER current. file_name. END assign_bits. 'X'). period : IN TIME) IS VARIABLE char : CHARACTER. '1'. FILE input_value_file : logic_data. WHEN OTHERS => current := current . CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current. VARIABLE current : TIME := 0 NS. READ_MODE). END CASE.period. PROCEDURE assign_bits ( SIGNAL s : OUT qit. 'Z'. TYPE logic_data IS FILE OF CHARACTER. file_name : IN STRING.

WHEN ‘Z’  ‘z’ => target <= TRANSPORT ‘Z’ AFTER current. WHEN ‘X’  ‘x’ => target <= TRANSPORT ‘X’ AFTER current. WHEN OTHERS => current := current – period. Z. END CASE. Navabi and McGraw-Hill Inc. WHEN ‘1’ => target <= TRANSPORT ‘1’ AFTER current. . sequence_of statements case_statement alternative expression choice case_statement alternative sequence_of statements sequence_of statements choices case_statement alternative case_statement alternative sequence_of statements choice sequence_of statements case_statement alternative • Syntax details of a sequential case statement • Consists of several case alternatives • All choices must be filled CHAPTER 7 45 © 1999.SUBPROGRAM PARAMETER TYPES AND OVERLOADING CASE char IS WHEN ‘0’ => target <= TRANSPORT ‘0’ AFTER current.

o1 : OUT qit). • Calling the overloaded assign_bits for testing an inverter • The inverter with RC delay is being tested • Type qit operand of the procedure causes the new assign_bits to be called CHAPTER 7 46 © 1999. END COMPONENT. z : qit. BEGIN assign_bits (a. PORT (i1 : IN qit. resistance. z).ALL. 500 NS). -. END input_output. i1 : inv PORT MAP (a. capacitance. Z.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. FOR ALL : inv USE ENTITY WORK. -ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr). SIGNAL a.qit".basic_utilities. .FROM PACKAGE: qit. Navabi and McGraw-Hill Inc. assign_bits ENTITY tester IS END tester.inv_rc(double_delay). "data.

SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9. Z. TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT. records. and aliases are discussed • • • • Subtypes are used for compatibility Base type of a subtype is the original type nibble_bits is not compatible with any BIT_VECTOR rit and bin are fully compatible with qit CHAPTER 7 47 © 1999. Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0). . SUBTYPE rit IS qit RANGE '0' TO 'Z'. SUBTYPE bin IS qit RANGE '0' TO '1'. subtypes. Other type related issues.

jmp. adr : address. Navabi and McGraw-Hill Inc. "00000000000"). Z. instr. TYPE instruction_format IS RECORD opc : opcode.mde <= 2. SIGNAL instr : instruction_format := (nop. mde : mode. lda.OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode address Instruction format TYPE opcode IS (sta. sub. instr <= (adr => (OTHERS => ‘1’). CHAPTER 7 . instr. and.opc <= lda. instr. add.adr <= "00011110000". 0. mde => 2. jsr). nop. TYPE address IS BIT_VECTOR (10 DOWNTO 0). TYPE mode IS RANGE 0 TO 3. END RECORD. opc => sub) • • • • • • Record Type Three fields of an instruction Declaration of instruction format A signal of record type Referencing fields of a record type signal Record aggregate 48 © 1999.

Z. ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr.OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode page address offset ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr.adr (7 DOWNTO 0). .adr (10 DOWNTO 8). Navabi and McGraw-Hill Inc. page and offset addresses • Alias declaration for the page and offset parts of the address • Assignments to page and offset parts of address CHAPTER 7 49 © 1999. • Alias declaration. page <= "001". offset <= X"F1".

OTHER TYPES AND RELATED ISSUES head link node data link node data link node data NULL data Integer Type link Pointer Type TYPE node. Z. . TYPE node IS RECORD data : INTEGER. ACCESS type and implementation and usage of linked lists is demonstrated • Linked list graphical representation • Definition in VHDL starts with an incomplete type definition CHAPTER 7 50 © 1999. TYPE pointer IS ACCESS node. Navabi and McGraw-Hill Inc. END RECORD. link : pointer.

link := NEW node. • Using the above linked list • Declaring head and linking to it CHAPTER 7 51 © 1999. Assigning the first node to head.OTHER TYPES AND RELATED ISSUES Declaration of head as the head of a linked list to be created: VARIABLE head : pointer := NULL. Navabi and McGraw-Hill Inc. head := NEW node. . Linking the next node: head. Z.

link. 19. (25. END lineup. cache : pointer := NULL.link := NEW node.OTHER TYPES AND RELATED ISSUES PROCEDURE lineup (VARIABLE head : INOUT pointer.Insert data in the linked list head := NEW node. 20)). END LOOP. 17. Declare mem: VARIABLE mem. ELSE t1. IF i = int'RIGHT THEN t1. .link := NULL. END IF. Navabi and McGraw-Hill Inc.data := int(i). Z. • • • • Creating a linked list and entering data into it Head is returned as the first node of the linked list A new node of type node is obtained and assigned to head Fields of node are accessed and data is entered into them CHAPTER 7 52 © 1999. 18. Inserting integers into the mem linked list: lineup (mem. t1 := t1. FOR i IN int'RANGE LOOP t1. 12. t1 := head. BEGIN -. int : integer_vector) IS VARIABLE t1 : pointer.

OTHER TYPES AND RELATED ISSUES PROCEDURE remove (VARIABLE head : INOUT pointer. DEALLOCATE (t2). t1. BEGIN -. t1 := t1.link.Remove node following that with value v t1 := head. t2 : pointer. Navabi and McGraw-Hill Inc. v : IN INTEGER) IS VARIABLE t1.link := t2.link.link. . • Removing an item from a linked list • The head of the linked list is passed • Node that follows node with value v is removed CHAPTER 7 53 © 1999.data = v THEN t2 := t1. END IF. END LOOP. WHILE t1 /= NULL LOOP IF t1. Z. END remove.

END clear. Z. Navabi and McGraw-Hill Inc. t1 := t1. . WHILE t1 /= NULL LOOP t2 := t1. BEGIN -.link. • Freeing a linked list • Start with he head of a linked list and clear it • All nodes must be deallocated CHAPTER 7 54 © 1999. DEALLOCATE (t2). head := NULL.Free all the linked list t1 := head.OTHER TYPES AND RELATED ISSUES PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. t2 : pointer. END LOOP. END ll_utilities.

Navabi and McGraw-Hill Inc. t2 : pointer. END LOOP. END clear. WHILE t1 /= NULL LOOP IF t1.link.link. BEGIN -. t1 := t1. int : integer_vector) IS VARIABLE t1 : pointer. PROCEDURE remove (VARIABLE head : INOUT pointer. -PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. t2 : pointer. link : pointer. int : integer_vector). END lineup. END IF. FOR i IN int'RANGE LOOP t1.link. -PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer. END remove. Z.data = v THEN t2 := t1.Insert data in the linked list head := NEW node. WHILE t1 /= NULL LOOP t2 := t1. t1 := t1. -PROCEDURE remove (VARIABLE head : INOUT pointer.link := NULL. END LOOP. DEALLOCATE (t2).link.OTHER TYPES AND RELATED ISSUES PACKAGE ll_utilities IS TYPE node. t1. BEGIN -. t1 := t1.data := int(i). DEALLOCATE (t2). END ll_utilities.Remove node following that with value v t1 := head. TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER. END LOOP.link := NEW node. TYPE node IS RECORD data : INTEGER. IF i = int'RIGHT THEN t1.Free all the linked list t1 := head. END IF. PROCEDURE lineup (VARIABLE head : INOUT pointer. t1 := head. TYPE pointer IS ACCESS node. END ll_utilities. • Linked list utilities CHAPTER 7 55 © 1999. BEGIN -. head := NULL.link. . END RECORD.link := t2. PROCEDURE clear (VARIABLE head : INOUT pointer). ELSE t1. v : IN INTEGER). v : IN INTEGER) IS VARIABLE t1.

SIGNAL qo : qit_octal.Must do explicit type conversion • Share variables • Using qualifiers • Explicit type conversion between closely related types CHAPTER 7 56 © 1999. TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit. ..OTHER TYPES AND RELATED ISSUES SHARED VARIABLE dangerous : INTEGER := 0. . Z. sq4(3)) <= qit_nibble’ (OTHERS => ‘X’). sq4(1). -. Navabi and McGraw-Hill Inc. e. -.g. Now ‘X’s are qualified for size and element type Explicit type conversions for closely related types.. sq4(1). ‘X’ can be interpreted as character ‘X’. sq4(2). INTEGER and REAL TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit. In the assignment: (sq4(0). sq4(3)) <= (OTHER => ‘X’). qb <= qo. sq4(2).CANNOT DO qb <= qit_byte (qo). requires a qualifier: (sq4(0).. SIGNAL qb : qit_byte.

its overloading and its subtypes is a good example of the above topics • Provides types for most applications • Overloading is done for all operators • Includes conversion functions where needed CHAPTER 7 57 © 1999.OTHER TYPES AND RELATED ISSUES LIBRARY IEEE. Z. USE IEEE.ALL. Navabi and McGraw-Hill Inc.std_logic_1164. . std_logic is an enumeration type with nine logic values ‘U’ is the default initial value std_logic_vector is an unconstraned array of std_logic All logical and shift operators are overloaded for std_logic and std_logic_vector Conversion functions for all subtypes and the BIT type to and from std_logic std_logic.

Z. ‘0’. ‘0’. ‘X’.OTHER TYPES AND RELATED ISSUES TYPE X01 X01Z UX01 UX01Z ‘X’. ‘Z’ ‘1’ ‘1’. ‘X’. ‘X’. different initial values CHAPTER 7 58 © 1999. ‘U’. ‘Z’ • std_logic subtypes • Enumeration elements are arranged for such subtypes • Our qit is like UX01 or X01Z. . ‘0’. ‘1’ ‘1’. ‘U’. ‘0’. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Signal. . Type. and Entity • Predefined Array Attributes • Type of sq_4_8 is qit_4by8 CHAPTER 7 59 © 1999. Z. Array.PREDEFINED ATTRIBUTES Attribute ‘LEFT ‘RIGHT Description Left bound Right bound Example sq_4_8’LEFT(1) sq_4_8’RIGHT sq_4_8’RIGHT(2) sq_4_8’HIGH(2) sq_4_8’LOW(2) sq_4_8’RANGE(2) sq_4_8’RANGE(1) sq_4_8’REVERSE_RANGE(2) sq_4_8’REVERSE_RANGE(1) sq_4_8’LENGTH sq_4_8’ASCENDING(2) sq_4_8’ASCENDING(1) 3 0 7 7 0 Result ‘HIGH ‘LOW ‘RANGE Upper bound Lower bound Range 0 TO 7 3 DOWNTO 0 7 DOWNTO 0 0 TO 3 4 TRUE FALSE ‘REVERSE_RANGE Reverse range ‘LENGTH ‘ASCENDING Length TRUE If Ascending Predefined attributes are demonstrated here.

Value. Z.PREDEFINED ATTRIBUTES Attribute ‘BASE ‘LEFT ‘RIGHT Description Base of type Left bound of type or subtype Right bound of type or subtype Upper bound of type or subtype Lower bound of type or subtype Position of value V in base of type... Value at Position P in base of type.... Navabi and McGraw-Hill Inc. .. . after value V in base of type. . . . .. • Predefined type attributes • The type of qit and rit are enumeration types • More follows .. CHAPTER 7 60 © 1999. Value. before value V in base of type. Example rit’BASE rit’LEFT qit’LEFT rit’RIGHT qit’RIGHT INTEGER’HIGH rit’HIGH POSITIVE’LOW qit’LOW qit’POS(‘Z’) rit’POS(‘X’) qit’VAL(3) rit’VAL(3) rit’SUCC(‘Z’) Result qit ‘0’ ‘0’ ‘Z’ ‘X’ Large ‘Z’ 1 ‘0’ 2 3 ‘X’ ‘X’ ‘X’ ‘HIGH ‘LOW ‘POS(V) ‘VAL(P) ‘SUCC(V) ‘PRED(V) rit’PRED(‘1’) ‘0’ .

Converts string S to value of type. ‘0’ Error ‘Z’ ‘X’ TRUE TRUE “’Z’” “qZ” qZ Value. . Description . Value. Navabi and McGraw-Hill Inc... Example Result .. left of value V in base of type. right of value V in base of type.....PREDEFINED ATTRIBUTES Attribute . rit’LEFTOF(‘1’) rit’LEFTOF(‘0’) rit’RIGHTOF(‘1’) rit’RIGHTOF(‘Z’) qit’ASCENDING qqit’ASCENDING qit’IMAGE(‘Z’) qqit’IMAGE(qZ) qqit’VALUE(“qZ”) ‘RIGHTOF(V) ‘ASCENDING ‘IMAGE (V) ‘VALUE(S) • Predefined type attributes • The type of qit and rit are enumeration types • Note type versus base of type CHAPTER 7 61 © 1999. TRUE if range is ascending Converts value V of type to string. ‘LEFTOF(V) .. Z.

If no parameter or 0. . Z. If no parameter or 0.. but delayed by 5 NS. Navabi and McGraw-Hill Inc. CHAPTER 7 62 © 1999. ‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN A signal that is TRUE if s1 has not changed in the last 5 NS. ‘EVENT EV s1’EVENT VALUE BOOLEAN In a simulation cycle.. ‘LAST_EVENT EV s1’LAST_VALUE VALUE TIME The amount of time since the last value change on s1. the resulting signal is TRUE if s1 has not changed in the current simulation time. if s1 changes. this attribute becomes TRUE. ‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1 The value of s1 before the most recent event occurred on this signal. • Predefined signal attributes • Signal s is assumed to be of type BIT • More follows . . . the value of s1’LAST_VALUE is 0. If s1’EVENT is TRUE. Equivalent to TRANSPORT delay of s1. .PREDEFINED ATTRIBUTES Attribute T/E Example Kind Type Attribute description for the specified example ‘DELAYED s1’DELAYED (5 NS) SIGNAL As s1 A copy of s1. delayed by delta.

Navabi and McGraw-Hill Inc. s1’DRIVING is TRUE in the same process. If s1’ACTIVE is TRUE. s1’LAST_ACTIVE is 0.PREDEFINED ATTRIBUTES Attribute T/E Example . Kind Type ‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS. • Predefined signal attributes • Signal s is assumed to be of type BIT CHAPTER 7 63 © 1999. s1’ACTIVE will be TRUE for this simulation cycle. Initial value of this attribute is not defined. for delta time. ‘DRIVING_VALUE s1’DRIVING_VALUE VALUE As s1 The driving value of s1 from within the process this attribute is being applied. the current simulation cycle is assumed. . If no parameter or 0. Z. ‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN If s1 has had a transaction in the current simulation cycle. ‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME The amount of time since the last transaction occurred on s1. ‘DRIVING s1’DRIVING VALUE BOOLEAN If s1is being driven in a process... ‘TRANSACTION TR s1’TRANACTION SIGNAL BIT A signal that toggles each time a transaction occurs on s1.

PREDEFINED ATTRIBUTES 15 TIME (NS) 30 45 60 s1 s1'DELAYED (5NS) s1'STABLE s1'EVENT 10 s1'LAST_EVENT s1'LAST_VALUE s1'QUIET (5NS) 15 20 25 0 5 10 0 5 10 15 s1'ACTIVE 10 s1'LAST_ACTIVE 0 5 10 0 5 10 0 5 10 0 s1'TRANSACTION • Results of signal attributes when applied to the BIT type signal. Navabi and McGraw-Hill Inc. s1 • Blocks show Boolean results CHAPTER 7 64 © 1999. Z. .

-ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT. q : OUT BIT). q <= tmp AFTER 8 NS. END falling_edge. • A simple falling edge Flip-Flop using signal attributes • Two events occur when c changes • Cannot delay the first statement CHAPTER 7 65 © 1999. END brief_d_flip_flop. c : IN BIT.PREDEFINED ATTRIBUTES ENTITY brief_d_flip_flop IS PORT (d. Z. Navabi and McGraw-Hill Inc. . BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp.

Navabi and McGraw-Hill Inc. q : OUT BIT). . BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp. q <= tmp AFTER 8 NS. END toggle. -ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT.PREDEFINED ATTRIBUTES ENTITY brief_t_flip_flop IS PORT (t : IN BIT. • A simple toggle Flip-Flop using signal attributes • Combining several signal attributes • Can only apply if result of an attribute is signal CHAPTER 7 66 © 1999. Z. END brief_t_flip_flop.

components. Z. labels. procedures. literals. architecture. variables.PREDEFINED ATTRIBUTES Entity Attributes generate a string corresponding to the name of an entity class “entity_class” entities. architectures. groups. packages. and files ‘SIMPLE_NAME: Generates simple name of a named entity ‘PATH_NAME : Generates a string containing entity names and labels from the top of hierarchy leading to the named entity. types. signals. • Entity attributes • Generate a string for the name for an entity class CHAPTER 7 67 © 1999. . ‘INSTANCE_NAME: Generates a name that contains entity. functions. configurations. constants. subtypes. units. Navabi and McGraw-Hill Inc. and instantiation labels leading to the design entity.

BEGIN u1 : ENTITY WORK. b. -ARCHITECTURE gate_level OF xoring IS SIGNAL a. END single_delay. i2 : IN BIT. c : BIT. and instance attributes CHAPTER 7 68 © 1999. Navabi and McGraw-Hill Inc. .nand2 PORT MAP (i1. b). path <= nand2'PATH_NAME. i2 : IN BIT.PREDEFINED ATTRIBUTES ENTITY nand2 IS PORT (i1. u4 : ENTITY WORK. o1).'). END ENTITY. BEGIN o1 <= i1 NAND i2 AFTER 3 NS. simple <= nand2'SIMPLE_NAME. i2. END gate_level. SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH) := (OTHERS => '.nand2 PORT MAP (i1. Z. i2. -ENTITY xoring IS PORT (i1. a). c. SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH) := (OTHERS => '. END ENTITY. o1 : OUT BIT). a.nand2 PORT MAP (a. u2 : ENTITY WORK. path. • Examples for entity attributes • Simple. o1 : OUT BIT). u3 : ENTITY WORK.nand2 PORT MAP (b.'). c).'). -ARCHITECTURE single_delay OF nand2 IS SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH) := (OTHERS => '. instance <= nand2'INSTANCE_NAME.

and instance strings • Results from simulation of the above nand2 CHAPTER 7 69 © 1999. Z. path. .PREDEFINED ATTRIBUTES Simple: Path: Instance: nand2 :xoring:u1: “xoring(gate_level):u1@nand2(single_delay): • Simple. Navabi and McGraw-Hill Inc.

USER-DEFINED ATTRIBUTES

User-defined attributes may be applied to the elements of an entity class

Must declare first: ATTRIBUTE sub_dir : STRING;

Then attribute specification: ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS “/user/vhdl”;

brief_d_flip_flop’sub_dir evaluates to “/user/vhdl”.

User-defined attributes are demonstrated here.

• User defined attributes • No simulation semantics

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USER-DEFINED ATTRIBUTES

PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING; END utility_attributes; -USE WORK.utility_attributes.ALL; -- FROM PACKAGE USE: delay, sub_dir ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS); END brief_d_flip_flop; -ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall; END attributed_falling_edge;

• • • •

Associating attributes to entities and signals A package declares attributes An entity defines An architecture uses attributes

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PACKAGING BASIC UTILITIES

PACKAGE basic_utilities IS ... TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL; ... FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; FUNCTION to_integer (qin : qit_vector) RETURN INTEGER; FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector; ... FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector; ... END basic_utilities;

• Adding what was done to our basic utilities package • Will use this package for homeworks and in other chapters

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PACKAGING BASIC UTILITIES
PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;

• Complete package declaration

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PACKAGING BASIC UTILITIES
PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;

• Package body
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PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;®BB¯

• Package body

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PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits; END basic_utilities;

• The basic_utilities package as will be used in the examples in the chapters that follow

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Summary This chapter presented tools for high level descriptions. Declaration of types and the usage of objects of various types were covered in the first part of the chapter. In the context of describing type-related issues, we introduced the unconstrained array and file type. The basic I/O presented in this chapter showed a simple way to read or write from files. The overloading which is related to types was discussed next. Predefined attributes in VHDL can be looked upon as operators or predefined functions. In modeling, hardware behavior attributes are very useful, as we will see in the following, chapters. Finally in this chapter, we presented the Elements of this package are

basic_utilities package.

useful for hardware modeling and the creation of the package demonstrates the importance of packaging capability in VHDL.

• End Of Chapter 7

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CHAPTER 8 DATAFLOW DESCRIPTIONS IN VHDL

8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals 8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine 8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING 8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY

• • • • • • •

Constructs for dataflow descriptions Multiplexing and clocking, selection constructs; guarded assignments Multiple assignments; Resolutions: anding, oring, wiring Guarded signals State machines, simple sequence detector, multiple active states Open collectors using resolution functions A complete dataflow example

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION
select1

data1

out select2

data2

(a)

1D 2D y S1 S2

D1

Y D2

S1 S2

Will use VHDL for modeling various selection logic implementations

• Basic data selection hardware, logic diagram, symbols • Multiplexers are used for data selection

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION

Q

enable

data

1D C1

clk

• Flip flop clocking selects data • Various forms of data selection may be combined • Will show language constructs for such selections

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© 1999, Z. Navabi and McGraw-Hill Inc.

Z.MULTIPLEXING AND DATA SELECTION data1 data2 1D 2D Y 1D Q select1 select2 S1 S2 C1 enable clk • Multiplexing and clock enabling. Navabi and McGraw-Hill Inc. . CHAPTER 8 4 © 1999.

MULTIPLEXING AND DATA SELECTION G0 G1 select lines G2 G3 G4 G5 G6 G7 MUX Z 0 1 2 data inputs 3 4 5 6 7 • An eight-to-one multiplexer. . Navabi and McGraw-Hill Inc. Z. CHAPTER 8 5 © 1999.

s3. s1. s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000". s7. i3. s4.ALL. -. i3 AFTER 3 NS WHEN "00001000" | "0000Z000". i4. i0 AFTER 3 NS WHEN "00000001" | "0000000Z". s6. 'X' WHEN OTHERS. -ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector’(s7. z : OUT qit ). Navabi and McGraw-Hill Inc. i6 AFTER 3 NS WHEN "01000000" | "0Z000000". qit_vector ENTITY mux_8_to_1 IS PORT ( i7. i5 AFTER 3 NS WHEN "00100000" | "00Z00000".FROM PACKAGE USE: qit. s6. s1. Z. s2. END dataflow.basic_utilities. i7 AFTER 3 NS WHEN "10000000" | "Z0000000". i1 AFTER 3 NS WHEN "00000010" | "000000Z0". s4. i1. • • • • Description of a simple multiplexer Selected signal assignment is used Dataflow multiplexing Selected waveforms use choice or choices CHAPTER 8 6 © 1999.MULTIPLEXING AND DATA SELECTION USE WORK. i0 : IN qit. s2. i2 AFTER 3 NS WHEN "00000100" | "00000Z00". i6. s3. . s5. i5. s5. i2. s0 : IN qit. i4 AFTER 3 NS WHEN "00010000" | "000Z0000". END mux_8_to_1.

Z.MULTIPLEXING AND DATA SELECTION • Syntax details of a selected signal assignment. . Navabi and McGraw-Hill Inc. CHAPTER 8 7 © 1999.

MULTIPLEXING AND DATA SELECTION A0 A1 A2 DCD S0 S1 S2 S3 S4 S5 S6 S7 Another form of selection is a decoder. Z. . CHAPTER 8 8 © 1999. Navabi and McGraw-Hill Inc. which we will model in VHDL • Decoder description uses selected signal assignment • A three-to-eight decoder.

END dataflow. "00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" . "00000100" AFTER 2 NS WHEN "0Z0" | "010". "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111". Z. "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011". Navabi and McGraw-Hill Inc. "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110".basic_utilities. "XXXXXXXX" WHEN OTHERS.FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0).MULTIPLEXING AND DATA SELECTION USE WORK. -ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000". so : OUT qit_vector (7 DOWNTO 0)). . • All possibilities must be considered CHAPTER 8 9 © 1999. "00000010" AFTER 2 NS WHEN "00Z" | "001". -. • VHDL description for the three-to-eight decoder.ALL. END dcd_3_to_8. "00010000" AFTER 2 NS WHEN "100" | "Z00".

. Navabi and McGraw-Hill Inc. END d_flipflop. qb <= NOT internal_state AFTER delay2. delay2 : TIME := 5 NS). -ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT. qb : OUT BIT). Z. END assigning.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS. q. q <= internal_state AFTER delay1. c : IN BIT. BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state. 1D Q Q C1 • A simple flip-flop uses internal_state • On clock edge d is transferred to internal_state • Events on internal_state cause assignments to q and qb CHAPTER 8 10 © 1999. PORT (d.

Z. qb <= GUARDED NOT d AFTER delay2. . 1D Q Q C1 Several examples will demonstrate guarded blocks and assignments • • • • • The guarding architecture for the d_flipflop entity. END BLOCK ff. END guarding. ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1. Navabi and McGraw-Hill Inc. Better representation of clocking disconnects d from q Disconnection is specified by GUARDED GUARDED assignments are guarded by guard expression Can also guard selected and conditional signal assignments CHAPTER 8 11 © 1999.MULTIPLEXING AND DATA SELECTION target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms.

Z. . Navabi and McGraw-Hill Inc. END BLOCK ff. qb <= GUARDED NOT d AFTER delay2. guard_expression concurrent statement block statement part block statement concurrent statement • Syntax details of a guarded block statement with guarded signal assignments • Label is mandatory • Use GUARDED for guard to apply CHAPTER 8 12 © 1999.MULTIPLEXING AND DATA SELECTION ff : BLOCK ( block_label Concurrent statement c = ‘1’ AND NOT c’STABLE ) BEGIN q <= GUARDED d AFTER delay1.

cc.d_flipflop (assigning). c : IN BIT. q1. FOR c1 : flop USE ENTITY WORK. Z. • A test bench for testing assigning and guarding architectures of d_flipflop • Testbench tests and verifies both descriptions • A simple method for generation of periodic signals CHAPTER 8 13 © 1999. qb1). c1: flop PORT MAP (dd.d_flipflop (guarding). dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd. SIGNAL dd. FOR c2 : flop USE ENTITY WORK. END input_output. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc. qb1. qb : OUT BIT). END COMPONENT. qb2 : BIT. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d. qb2). q1. Navabi and McGraw-Hill Inc. q2. c2: flop PORT MAP (dd. . cc. q2. cc.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. q.

. FALSE FALSE . FALSE FALSE ... ..... . .......... .. . .. ... ..... .. '0' ... . .. ... CHAPTER 8 14 . ..... . .. .. '0' '0' . . .. .... . ....... '1' ..... ..... ....... '0' '0' . . . '1' c1: state '0' '0' .... ..... .. .. . ........ . ... .. ..MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0004 0005 0400 +1δ δ +2δ δ 0404 0405 0800 +1δ δ +2δ δ 1000 +1δ δ 1200 +1δ δ +2δ δ 1204 1205 1600 +1δ δ +2δ δ 2000 +1δ δ +2δ δ 2004 2005 cc '0' .... .. .......... .. ... TRUE FALSE ... .. .... qb1 '0' . .............. . .. . . . ........... . ..... .. . . ... '1' ....... .......... . '1' . .. .... ... . .... . • • • • • • Simulation results of the input_output architecture of the flipflop_test All transactions are observed In assigning:Two transactions on internal_state for every clock edge Transaction on q1 at time 0004. '1' '1' .... .. .... . .... .... ... is due to initialization In guarding:c2... . '1' . ... '0' ..... . Navabi and McGraw-Hill Inc....... '0' . '1' '1' .... . ........ '0' . .. . '0' .. ... .... '0' ..... TRUE FALSE .... ....... ..... .. '0' .............. ..... ..... .. '0' .. '1' '1' ... q2 '0' . .... . . . ... . .. .. . .. '0' '0' .. ....... ... .. .. . .... .... .. ... ..... q1 '0' . . '0' '0' .. '1' ... '1' ....... ... dd '0' .. .. ..... .. ... .....ff : GUARD sees GUARD inside guarding Guard expression is only TRUE for 1 delta © 1999...... TRUE FALSE . '1' ...... .. .. . .. '0' .. ..... ... . .......... ... . .. .. .. .... ........ .. c2:ff GUARD FALSE ... Z. ........... ... . '1' qb2 '0' . ..

0) (b) Value = d s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND NOT c’STABLE) ELSE s. c Scheduling on S (d. c Scheduling on S (d. c Scheduling on S (d. . c Scheduling on S (d. 0) (c) Value = s s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND c’EVENT) ELSE s. 6) (d) Value = s Value = d s • Events on edge detection expression • Demonstrating difference between ‘EVENT and NOT ‘STABLE CHAPTER 8 15 © 1999.MULTIPLEXING AND DATA SELECTION s <= d WHEN (c= ‘1’ AND NOT c’STABLE) ELSE UNAFFECTED. 6) (s. Navabi and McGraw-Hill Inc. 0) UNAFFECTED (a) Value = d s Value = s s <= d WHEN (c= ‘1’ AND c’EVENT) ELSE UNAFFECTED. Z.

qb : OUT BIT). qout => q. PORT MAP (din => d. qout. BEGIN qout <= GUARDED din AFTER delay1.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS. • • • • Using declarative part of a block statement PORT specifies signals on the outside PORT MAP maps outside signals with those inside Association format is used as expected CHAPTER 8 16 © 1999. qbar <= GUARDED NOT din AFTER delay2. . q. c : IN BIT. END guarding. qbar => qb). qbar : OUT BIT). -ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT. PORT (d. Navabi and McGraw-Hill Inc. Z. delay2 : TIME := 5 NS). END BLOCK ff. END ENTITY.

. . ). . Z. . Navabi and McGraw-Hill Inc.. . BEGIN qout <= .. .MULTIPLEXING AND DATA SELECTION ff : BLOCK ( . . block_statement port_clause port_map_aspect block_header block_statement_part • Syntax details for block statement with header • Uses this to draw a dashed line around a section of your hardware CHAPTER 8 17 © 1999. END BLOCK ff. ). qbar <= . ) PORT ( . . . . PORT MAP ( . .

MULTIPLEXING AND DATA SELECTION 1. Z. . 2D Q E2 C1 Q • A positive edge trigger flip-flop with enable input • Can nest block statements • Combining guard expressions must be done explicitly CHAPTER 8 18 © 1999. Navabi and McGraw-Hill Inc.

• VHDL description for the positive edge trigger flip-flop with enable input • Implicit GUARD signals in each block • Useful if different second conditions were used CHAPTER 8 19 © 1999. .MULTIPLEXING AND DATA SELECTION ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS. Z. qb <= GUARDED NOT d AFTER delay2. e. END guarding. q. PORT (d. Navabi and McGraw-Hill Inc. c : IN BIT. -ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1. delay2 : TIME := 5 NS). END de_flipflop. END BLOCK gate. END BLOCK edge. qb : OUT BIT).

END dee_flipflop. END guarding. -ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1. END BLOCK edge. 2D 1. gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1.MULTIPLEXING AND DATA SELECTION ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS. qb <= GUARDED NOT d2 AFTER delay2. 1. e2. . END BLOCK gate3. qb <= GUARDED NOT d3 AFTER delay2. c : IN BIT. d3. qb : OUT BIT). e3. double d flip-flop with independent enable inputs • Clock expression is specified only once CHAPTER 8 20 © 1999. q. Z. Navabi and McGraw-Hill Inc. delay2 : TIME := 5 NS). 3D Q E2 E3 C1 Q • A positive edge trigger. PORT (d2. END BLOCK gate2.

FOR c1 : ff1 USE ENTITY WORK. END COMPONENT. Navabi and McGraw-Hill Inc. qb : OUT BIT). • A test bench for testing the guarding architectures of de_flipflop • Testbench verifies operation of de_flipflop • After 2200 q1 is disconnected from d CHAPTER 8 21 © 1999. cc. dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd. ee <= '1'. ee. SIGNAL dd.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. q1. e.de_flipflop (guarding). cc. ee. c1: ff1 PORT MAP (dd. qb1 : BIT. '0' AFTER 2200 NS. Z. END input_output. q1. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc. c : IN BIT. q. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d. qb1). .

..... . . ... .... '1' . '0' '1' . '0' ..... .. . .... '0' . .. . ...... '1' .... . .. .... ........ . dd '0' . . ... '0' '1' . .. .. . . ....... ... . . .. ...... . ...... ....... '1' . ...... ...... . . '0' ....... .. .. .. ..MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0400 0404 0405 0800 1000 1200 1204 1205 1600 2000 2004 2005 2200 2400 2800 3000 +1δ δ 3200 +1δ δ cc '0' . '1' . .. '0' '0' ee '0' '1' ... . . .... .. q1 '0' ....... '1' . ... . . . .... '1' '1' . ...... . '0' .. .. ............. '0' ........ .. qb1 '0' . .... ... .. ...... '1' . Navabi and McGraw-Hill Inc. '0' ... • Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • No transactions on the outputs after 2200 NS CHAPTER 8 22 © 1999... . Z. ......... ....

MULTIPLEXING AND DATA SELECTION RHS Activation GUARD 0 Driving Value Projected Output Waveform • Symbolizing guarded signal assignments • Disconnection in a guarded signal assignment • Driving value continues to be updated even if the guard expression is false CHAPTER 8 23 © 1999. Navabi and McGraw-Hill Inc. . Z.

• So does VHDL CHAPTER 8 24 © 1999. Z. .MULTIPLEXING AND DATA SELECTION What follows concentrates on definition & applications of resolution functions • Normally several sources cannot drive a signal • Real circuits smoke. Navabi and McGraw-Hill Inc.

• Multiple sources for a simple signal • This results in an error message CHAPTER 8 25 © 1999. . b. Navabi and McGraw-Hill Inc. c. -ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit.ALL. -. circuit_node <= b. BEGIN circuit_node <= a. END y_circuit. Z. z : OUT qit). circuit_node <= d. d : IN qit.basic_utilities. z <= circuit_node. END smoke_generator.FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a.MULTIPLEXING AND DATA SELECTION USE WORK. circuit_node <= c.

a happy VHDL simulator • Multiple drivers is possible only if a resolution exists • Example in hardware is "open collector" • Pull_up provides resolution CHAPTER 8 26 © 1999. Z.MULTIPLEXING AND DATA SELECTION A happy circuit. Navabi and McGraw-Hill Inc. .

Z. . Navabi and McGraw-Hill Inc. qit_vector. RETURN accumulate. “AND” from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'. END anding. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i).USE qit.MULTIPLEXING AND DATA SELECTION -. ANDs all its drivers Performs the AND function two operand at a time Collect all ANDs and return A notation that we will use CHAPTER 8 27 © 1999. END LOOP. a b anding c d circuit_node • • • • The anding resolution function.

ALL. circuit_node <= c. BEGIN circuit_node <= a. z <= circuit_node. Navabi and McGraw-Hill Inc. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). Z. • • • • • • Multiple sources for a simple signal The difference is in the declaration of the left-hand-side This results in ANDing all sources Specify anding for the resolution on circuit_node Type of circuit_node is a subtype of qit ANDing simultaneously receives all drivers 28 © 1999.basic_utilities. END wired_and.FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'.MULTIPLEXING AND DATA SELECTION USE WORK. RETURN accumulate. circuit_node <= b. END LOOP. circuit_node <= d. -. END anding. CHAPTER 8 . SIGNAL circuit_node : anding qit.

. Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION t4 v4 t4 v4 t4 v4 t3 v3 t3 v3 t3 t3 t2 v2 t2 v2 t2 t2 t1 v1 t1 v1 t1 t1 0 0 lhs_signal 0 • • • • Projected output waveforms and resolution functions Every assignment in a concurrent body creates a driver All assignments is a sequential body create only one driver Resolution functions act on expired values CHAPTER 8 29 © 1999.

Z. Navabi and McGraw-Hill Inc. it only sees the driving value CHAPTER 8 30 © 1999.MULTIPLEXING AND DATA SELECTION RHS Activation GUARD t4 v4 Driver 1 t3 v3 t2 v2 t1 v1 0 RHS Activation lhs_signal GUARD t4 v4 Driver 2 t3 v3 t2 v2 t1 v1 0 • Guarded signal assignments into resolved signals • Drivers continue to perform normal in spite of disconnection • Resolution function cannot tell the difference. .

z <= t. BEGIN t <= i7 AND s7. END multiple_assignments. Navabi and McGraw-Hill Inc. Z. END oring. RETURN accumulate. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). END LOOP. • Implementing the eight-to-one multiplexer using eight concurrent assignments • ORing resolution function is used CHAPTER 8 31 © 1999.basic_utilities. t <= i4 AND s4. SIGNAL t : oring qit. t <= i0 AND s0. t <= i3 AND s3.MULTIPLEXING AND DATA SELECTION USE WORK. t <= i2 AND s2. t <= i5 AND s5.FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. t <= i6 AND s6. .ALL. t <= i1 AND s1. -.

('0'.'X'.MULTIPLEXING AND DATA SELECTION FUNCTION wire (a. In1: In2: 0 1 Z X 0 0 X 0 X 1 X 1 1 X Out Z 0 1 Z X X X In1 X Out X In2 X • The wire function for modeling wiring two qit type nodes.'X')). END wire.'X'. BEGIN RETURN qit_wire_table (a.'1'. ('X'.'1'. b). • Input-output mapping • Circuit notation CHAPTER 8 32 © 1999.'Z'. Z.'1'. Navabi and McGraw-Hill Inc. ('X'.'X'.'X'). . b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.'X').'0'.'X').

• The wiring resolution function for qit type operands • Necessary declarations for visibility of the wiring resolution function and its related types and subtypes • If no drivers exist. END LOOP. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate.MULTIPLEXING AND DATA SELECTION FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. SUBTYPE wired_qit IS wiring qit. drivers(i)). FUNCTION wiring ( drivers : qit_vector) RETURN qit. Z. TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. . Navabi and McGraw-Hill Inc. RETURN accumulate. ‘Z’ will be returned • To declare an array of this resolution CHAPTER 8 33 © 1999. END wiring.

'0' is returned Necessary type and subtype definitions for the basic_utilities package Example signal declaration © 1999. • • • • • • Another complete example The oring resolution function for the BIT type operands OR for BIT is already defined If no drivers.MULTIPLEXING AND DATA SELECTION FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. END LOOP. END oring. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. Z. FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. RETURN accumulate. SUBTYPE ored_bit IS oring BIT. Navabi and McGraw-Hill Inc. CHAPTER 8 34 . BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 ).

Z. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • Will now model this circuit • An NMOS eight-to-one multiplexer • The CMOS version uses transmission gates instead of pass transistors CHAPTER 8 35 © 1999. .

A block statement modeling a transmission gate • Disconnection is realized by block statements • If all drivers are disconnected actual hardware returns to 'Z' CHAPTER 8 36 © 1999. . END BLOCK. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION si ii t bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii. Z.

• • • • • Each ii connects to t if si is '1'.ALL. t <= GUARDED i4. t <= GUARDED i3. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. -. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. t <= GUARDED i7. ii is disconnected from t if si is '0' Use BUS to implement this behavior Default in wire function is specified as 'Z' This default is used if wiring is called with Null Last disconnection causes call to wiring with Null CHAPTER 8 37 © 1999. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. t <= GUARDED i6. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK.FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS SIGNAL t : wired_qit BUS. t <= GUARDED i2.basic_utilities. t <= GUARDED i5.MULTIPLEXING AND DATA SELECTION USE WORK. Z. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. t <= GUARDED i0. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. t <= GUARDED i1. . z <= t. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. Navabi and McGraw-Hill Inc. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. END multiple_guarded_assignments.

MULTIPLEXING AND DATA SELECTION • An NMOS half-register with multiplexed input • Modeling this circuit must take inverter input capacitance into account • t holds charge if all are disconnected • Circuit shows a register effect CHAPTER 8 38 © 1999. Z. Navabi and McGraw-Hill Inc. .

BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. CHAPTER 8 . t <= GUARDED i5. s6. -ARCHITECTURE guarded_assignments OF multiplexed_half_register IS SIGNAL t : wired_qit REGISTER. i0 : IN qit. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. -. t <= GUARDED i0.FROM PACKAGE USE: qit. t <= GUARDED i4. s3. i1. s7. wired_qit ENTITY multiplexed_half_register IS PORT (i7. s0 : IN qit. END multiplexed_half_register. Z. t <= GUARDED i2. i6. t <= GUARDED i6. z <= NOT t AFTER 8 NS. s4. i3. i5. i4.basic_utilities. Navabi and McGraw-Hill Inc. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. t <= GUARDED i1. z : OUT qit ). s2. END guarded_assignments. s1. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. i2.ALL. s5. • • • • • • Use REGISTER to model retaining of last value No call is made to wiring upon last disconnection BUS and REGISTER are kind specification Signals with kind are guarded signals Guarded signals must be used on LHS of guarded assignments Ok to use unguarded signals on LHS of guarded assignments 39 © 1999. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. t <= GUARDED i3.MULTIPLEXING AND DATA SELECTION USE WORK. t <= GUARDED i7.

END. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values. Z. END. RHS Activation guard_expression t4 v4 Driver i t3 v3 t2 v2 t1 v1 0 guarded_lhs_signal • Turning off drivers from guarded signals • Guard expression controls driver contribution to the resolution function • Continuous contribution stops. even if a static value remains (if unguarded LHS) CHAPTER 8 40 © 1999. --------------------------------------------------------------------------------------------- BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values. .

disconnection disconnects. unguarded • • • • Disconnection disconnects if guarded BUS kind. REGISTER kind. but holds static value at the time of disconnection • For unguarded. Z.MULTIPLEXING AND DATA SELECTION Before Last Disconnection After Last Disconnection v v f(v) v null v f(null) (a) BUS Kind v v f(v) v null f(v) (b) REGISTER Kind v v f(v) v v f(v) (c) Not Guarded Last disconnections: BUS kind. last disconnection calls resolution function with Null REGISTER. Navabi and McGraw-Hill Inc. last disconnection does not call the resolution function Unguarded. . last disconnection is no different than others CHAPTER 8 41 © 1999.

s : IN qit_vector. END BLOCK. • • • • mutliple_guarded_assignments architecture of the mux_n_to_1 A general n-bit multiplexer Ports can be resolved signals BUS kind can also be specified.ALL. -ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j).basic_utilities. . not REGISTER CHAPTER 8 42 © 1999. Z. -. END GENERATE. END mux_n_to_1. Navabi and McGraw-Hill Inc.FROM PACKAGE USE: qit. END multiple_guarded_assignments. z : OUT wired_qit BUS). wired_qit ENTITY mux_n_to_1 IS PORT (i.MULTIPLEXING AND DATA SELECTION USE WORK. qit_vector.

mm : mux PORT MAP (ii. "Z100" AFTER 20 US. FOR ALL : mux USE ENTITY WORK. . zz). ss : qit_vector (3 DOWNTO 0) := "0000". SIGNAL ii. SIGNAL zz : qit.mux_n_to_1 (multiple_guarded_assignments). • A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1 • This entity is used as a four bit multiplexer CHAPTER 8 43 © 1999. END input_output. ss <= "0010" AFTER 05 US. "000Z" AFTER 25 US. ENTITY mux_tester IS END mux_tester. ss. -ARCHITECTURE input_output OF mux_tester IS COMPONENT mux PORT (i. BEGIN ii <= "1010" AFTER 10 US. Navabi and McGraw-Hill Inc. END COMPONENT. "1100" AFTER 15 US.ALL. "0011" AFTER 30 US.MULTIPLEXING AND DATA SELECTION USE WORK. Z. s : IN qit_vector. z : OUT wired_qit BUS).basic_utilities.

. "1100" ...... ... '0' ... "Z100" ...... . "0010" . ..... Navabi and McGraw-Hill Inc... ........ '0' . .. zz '0' 'Z' ............. ....... ... '1' ... .. 'X' . . "1010" . ss(3:0) "0000" .......... .... '1' .... "0011" ... '1' • Simulation results of the input_output architecture of the mux_tester • Simulation produces 'X' for two conflicting enabled inputs • Produces 'Z' when no inputs are enabled CHAPTER 8 44 © 1999.................... ....... .... .. Z.........MULTIPLEXING AND DATA SELECTION TIME (ns) 00000 +1δ δ 05000 +1δ δ 10000 +1δ δ 15000 +1δ δ 20000 +1δ δ 25000 +1δ δ 30000 +1δ δ ii(3:0) "0000" .... "000Z" ....

and other signal types • Several examples will follow CHAPTER 8 45 © 1999. Z. Navabi and McGraw-Hill Inc. guarded signals & resolved signals will de discussed • Will discuss other issues. . guarded. then will start using resolved.MULTIPLEXING AND DATA SELECTION Remaining issues: Disconnection Right and left INOUT More issues on resolutions.

SIGNAL t : wired_qit. .. . DISCONNECT t : wired_qit AFTER 6 NS. . Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE • Specify disconnection in the declaration • Use ALL for all signals of that type • Use OTHERS if some specified otherwise CHAPTER 8 46 © 1999.. Z. Navabi and McGraw-Hill Inc. END ARCHITECTURE. BEGIN . . it takes n NS for t to get ii ARCHITECTURE . END ARCHITECTURE. SIGNAL t : wired_qit. .MULTIPLEXING AND DATA SELECTION si ii ARCHITECTURE .. t Connection is timed: After connection. .... BEGIN . t <= GUARDED ii AFTER n NS.. .. t <= GUARDED ii AFTER n NS.

Z. Navabi and McGraw-Hill Inc. • Resolved signals on right and left hand sides • What you get is not what you put in • Others contribute to a resolved signal CHAPTER 8 47 © 1999.MULTIPLEXING AND DATA SELECTION Value used on the right hand side Value placed on driver of a t4 v4 t3 v3 t2 v2 t1 v1 0 Other Drivers a <= a AND b AFTER delay. .

c2 : ENTITY WORK. END connecting. x a z oring y b • Connecting INOUT ports require resolved signals • There are two drivers for each interconnection CHAPTER 8 48 © 1999. Z. . BEGIN c1 : ENTITY WORK. .two PORT MAP (b. . . ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT.MULTIPLEXING AND DATA SELECTION ENTITY one (a : IN BIT. z). . z). Navabi and McGraw-Hill Inc. y : INOUT BIT) … -ENTITY three IS END three. x : INOUT BIT) … ENTITY two (b : IN BIT. .one PORT MAP (a.

. Z.STATE MACHINE DESCRIPTION Will use resolutions and guarded assignments in several examples • • • • State names indicate detected sequences Use resolutions & guarded blocks A simple 1011 Mealy detector A block statement for each state CHAPTER 8 49 © 1999. Navabi and McGraw-Hill Inc.

FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT). END BLOCK s1. use one_of CHAPTER 8 50 © 1999. • • • • VHDL description of 1011 detector Only one simultaneous active state Current receives four concurrent assignments Current must be resolved. . END BLOCK s3. got101). Z. END BLOCK s4. z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'. SIGNAL current : one_of state REGISTER := reset. END singular_state_machine. s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset. z : OUT BIT). END one_of. got10. s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset. got1. Navabi and McGraw-Hill Inc.STATE MACHINE DESCRIPTION ENTITY detector IS PORT (x. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. END detector. clk : IN BIT. ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset. s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1. END BLOCK s2. END BLOCK clocking.

s <= GUARDED "0000". • • • • • VHDL description of 1011 detector More than one state can simultaneously be active The last description does not allows multiple active states To remedy: use a signal for each state State 3 : goes to 1 when x = '0'. END BLOCK s4. s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. . s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. Navabi and McGraw-Hill Inc. END multiple_state_machine.basic_utilities. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'. END BLOCK clocking.ALL. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'.STATE MACHINE DESCRIPTION USE WORK. goes to 4 when x = '1' CHAPTER 8 51 © 1999. s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. Z.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. END BLOCK s2. END BLOCK s3. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. -. END BLOCK s1.

-. END BLOCK clocking.. . Causes removal of retained value upon last disconnection CHAPTER 8 52 © 1999. .STATE MACHINE DESCRIPTION USE WORK.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. goes to 4 when x = '1' • S must be resolved vector REGISTER kind • S <= GUARDED "0000". • State 3 : goes to 1 when x = '0'. END BLOCK s2.ALL. END multiple_state_machine... s <= GUARDED "0000".. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. END BLOCK s3. Navabi and McGraw-Hill Inc.basic_utilities. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. Z. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN .

END oring. o <= GUARDED out_val(i. END LOOP. END GENERATE. • • • • A generic state machine A Moore sequence detector Specify transitions & outputting in constant tables Allows multiple machines in one CHAPTER 8 53 © 1999. s(next_val(i. SUBTYPE ored_bit IS oring BIT. out_val. END BLOCK clocking. BIT) OF INTEGER.'0')) <= GUARDED '1' WHEN x='0' ELSE '0'. END BLOCK si.clk : IN BIT. Navabi and McGraw-Hill Inc. END multiple_moore_machine_1. -ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. END detector_m. and s arrays SIGNAL o : ored_bit REGISTER. Z. TYPE out_table IS ARRAY (1 TO n. z <= o. z : OUT BIT). GENERIC (n : INTEGER). TYPE next_table IS ARRAY (1 TO n. s (i) <= GUARDED '0'. x). -. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). BIT) OF BIT.STATE MACHINE DESCRIPTION ENTITY detector_m IS PORT (x.Fill in next_val. BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i. .'1')) <= GUARDED '1' WHEN x='1' ELSE '0'. RETURN accumulate.

4).Next States: ----x=0. --S4: -> S1. 1 -('0' . --S3: == z=0. '1'). 0 -('0' . S1 -(5 .STATE MACHINE DESCRIPTION ------------------------------------------------------------------Tables for programming the configurable Moore description -------------------------------------------------------------------. 6) ). . --S1: == z=0.Initial Active States: -SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010". 1 ----. S2 -(1 . --S3: -> S1. '1') ). x=1 -CONSTANT next_val : next_table := ( (1 . 0 -('1' . S6 -(5 . '0'). 1). 2).--S6: == z=1. ---------------------------------------------------------------------------------------------------------------------------------- • • • • Next state and output tables The next_val constant holds next state values The out_val constant holds the output values on the z output Initial starting states are set to '1' in the s vector CHAPTER 8 54 © 1999. '0'). S4 -(1 . --S1: -> S1. '0'). '0'). Navabi and McGraw-Hill Inc.--S6: -> S5. --S2: == z=0. 3). Z. x=1 -CONSTANT out_val : out_table := ( ('0' . 6). --S4: == z=1. --S5: -> S5. 0 -('0' .Output Values: ----x=0. S6 -----. S3 -(1 . --S5: == z=0. --S2: -> S1. 0 -('1' .

OPEN COLLECTOR GATES

VCC

a y b

GND

• • • •

Open collector NAND gate A two-input NAND gate, TTL 74LS03 SSI package Resolution functions are used in bussing Will use open collector to illustrate

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;

• VHDL description of a NAND gate with open collector output • Use qit type • Output is ‘Z’ and not ‘1’

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OPEN COLLECTOR GATES
ENTITY test_nand2 IS END test_nand2; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; TIME BEGIN (ns) aa bb assign_bits (aa, "qit_data", 500 NS); 0000 '0' '0' assign_bits (bb, "qit_data", 750 NS); 0010 ... ... c1: nand2 PORT MAP (aa, bb, yy); 1000 '1' ... 1500 ... '1' END input_output;
1512 2500 2510 3000 3012 3750 3760 4000 4500 4512 5000 5010 5500 5512 6000 6010 6750 6762 7500 7510 8250 8262 ... '0' ... 'Z' ... ... ... '0' '1' ... '0' ... 'Z' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... 'Z' ... ... ... ... ... '0' ... '1' ... '0' ... 'Z' ...

yy '0' 'Z' ... ... '0’ ... 'Z' ... '0' ... 'Z' ... ... '0' ... 'Z' ... '0' ... 'Z' ... '0' ... 'Z' ... '0'

• Testing the open-collector NAND gate • Test bench uses external data file • Output is either ‘0’ or ‘Z’, never ‘1’

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;

• VHDL description of TTL 74LS03 • Contains four open collector NAND gates • Will use in a design

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OPEN COLLECTOR GATES

a1 b1

a4 aa pull_up_1 y1 g4 a2 bb b2 pull_up_3 y4 yy g2 pull_up_2 y2 g3 a3 b3 g1 b4

y3

yy = (aa' . bb)’ . (bb' . aa)' = ( aa ⊕ bb )'

• • • •

Implementing XNOR logic using open collector NAND gates Using 74LS03 for implementing an XNOR pull_up3 has two drivers pull_up1 and pull_up2 must be turned to ‘0’, ‘1’ logic

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US, '0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;

• Wiring and testing XNOR function implemented by four open collector AND gates • pull_up_1 and pull_up_2 turn 0,Z to 0,1 • anded_qit resolution function implements wired logic

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OPEN COLLECTOR GATES
TIME (us) 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 aa '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' 'Z' 'Z' 'Z' 'Z' 'Z' 'Z' bb '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' 'Z' pull_up_1 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' pull_up_2 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' pull_up_3 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0'

• Results are observed at 2 us intervals • Simulation shows XNOR implementation • Pull up resolutions turn gate output 'Z' values to '1'

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THREE STATE BUSSING

u1 :

alu

u2 :

reg1

u3 : bus1 8

8 8

bus a

u4 :

unit1

u5 :

unit2

• • • •

A bussing system (bus_sys) Will use resolution functions for describing it A very common hardware for RT level descriptions Some components have three-state outputs some do not

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THREE STATE BUSSING

ENTITY alu IS PORT (… ; zout : out qit_vector (7 DOWNTO 0)); END alu; -ENTITY reg1 IS PORT (… ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); …); END unit1; -ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); …); END unit2;

• Interface of bus sources and destinations • Wired_qit_vector is used for those with three-state outputs • Connection of others must be through three-state constructs

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THREE STATE BUSSING

ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (…; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (…; busa); … u3 : busa <= bus1; … unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;…); … u5 : ENTITY WORK.unit2 PORT MAP (busa;…); … END partial;

• • • •

Partial VHDL description for bussing system example reg1 with three-state output directly drives the bus aluout goes through three-state constructs All required hardware structures are explicitly coded

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Std_logic BUSSING

std_ulogic for “standard unresolved logic” A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms

• Std_logic provides multi-value logic for most applications • No need for new user types • Most designers use the resolved type

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Z. Navabi and McGraw-Hill Inc.A GENERAL DATAFLOW CIRCUIT 8-bit Parallel data Count equal sequential data on parallel input lines. 4-bit Count output Reset input • Seen dataflow primitives • Use dataflow for system description • A sequential comparator example CHAPTER 8 66 © 1999. .

int2bin (i. -. END IF. count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count. END sequential_comparator. t). • • • • Dataflow description of the sequential comparator circuit inc function is unconstrained Save old data in buff Compares old and new CHAPTER 8 67 © 1999. int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0). Navabi and McGraw-Hill Inc. Z. RETURN t.basic_utilities. END dataflow. SIGNAL count : BIT_VECTOR (3 DOWNTO 0).FROM PACKAGE USE: bin2int. IF i >= 2**x'LENGTH THEN i := 0. BEGIN bin2int (x. matches : OUT BIT_VECTOR (3 DOWNTO 0)). SIGNAL buff : BIT_VECTOR (7 DOWNTO 0). i := i + 1. i). BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data. matches <= count. clk. -ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER.ALL. reset : IN BIT.A GENERAL DATAFLOW CIRCUIT USE WORK. END inc. . END BLOCK. VARIABLE t : BIT_VECTOR (x'RANGE).

........................................ ... .. count(3:0) "0000" ....... ... ...... . "0011" ............... .... "10010110" ....... ..................... . ...... '0' ... ....................... "01010100" ......... . ........... ...... .. .. ..... ... .... ............ ....... '1' '0' .......... matches "0000" "0000" ... "10010110" . .... ..... . ........... ............ ....... ..... ...... ......................... .. ............ "0000" .... .......... .. '1' '0' . .. ..... .. .. ............... .... Navabi and McGraw-Hill Inc.. . "0010" ... .............. .. .. ........ ......... '1' . '1' data(7:0) "00000000" ............ .... '1' '0' .... "00010001" .. ..... buff(7:0) "00000000" .... "0001" ... ... ..... ..... .... .... ..... "0010" .. . "10010110" ........... "01010110" . . ....... ................... "0001" ......... ....... ....... Z. ... .. . .. . ..... . '1' '0' . ....... '1' ............... .... .. . ............. .......... clk '0' ..... ... "0001" .......... ......... .. . ... ..... ........... "11110101" .. . .... .................. "10010110" ... .......... "0100" . ..........A GENERAL DATAFLOW CIRCUIT TIME (ns) 0000 +1δ δ 0200 0500 1000 +1δ δ 1200 1500 1700 2000 +1δ δ 2500 3000 +1δ δ +2δ δ 3200 3500 3700 4000 +1δ δ 4200 4500 5000 +1δ δ 5500 6000 +1δ δ +2δ δ 6500 7000 +1δ δ +2δ δ 7500 8000 +1δ δ +2δ δ 8500 reset '0' . "0100" ............... ..... . ... .. ................ . ............. .................... .......... ... . "0001" . ... ...... .... ... "11111110" . . . ... .... ... ..... '1' '0' .. .. .. "00010001" ....... ......... '0' ........ ..... "11111110" ....... • matches shows count of matching data CHAPTER 8 68 © 1999............ ... ................... . "11110101" ... ... .. "11111110" .. ... ....... ... '1' '0' ..................... ........... .............. ........ "0000" .......................... ... "0011" ....... ... ... ................... "10010110" . ..................................... .... ... ... ....................... . .

. b : qit) RETURN qit. SUBTYPE ored_bit IS oring BIT. SUBTYPE anded_qit IS anding qit. -FUNCTION wiring ( drivers : qit_vector) RETURN qit.UPDATING BASIC UTILITIES PACKAGE basic_utilities IS . TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. SUBTYPE wired_qit IS wiring qit. -FUNCTION anding ( drivers : qit_vector) RETURN qit. -FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. -FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR. Z. END basic_utilities. TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit. -FUNCTION oring ( drivers : qit_vector) RETURN qit. TYPE anded_bit_vector IS ARRAY (NATURAL RANGE <>) OF anded_bit. . TYPE anded_qit_vector IS ARRAY (NATURAL RANGE <>) OF anded_qit. SUBTYPE ored_qit IS oring qit. CHAPTER 8 69 © 1999. -FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. SUBTYPE anded_bit IS anding bit. Navabi and McGraw-Hill Inc. FUNCTION wire (a.

'1'. END anding. END oring. Navabi and McGraw-Hill Inc. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. RETURN accumulate. .'X'.'Z'. drivers(i)).'X'). END LOOP. FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'.'X'). Z.'X')).'1'. ('X'. ('X'.'0'. END wire. .'1'. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i).'X'). END LOOP. FUNCTION wire (a.UPDATING BASIC UTILITIES PACKAGE BODY basic_utilities IS . BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). RETURN accumulate. b). ('0'. b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.'X'. . END wiring. FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'.'X'. CHAPTER 8 70 © 1999. END LOOP. BEGIN RETURN qit_wire_table (a. RETURN accumulate.

.UPDATING BASIC UTILITIES FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. END LOOP. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). RETURN accumulate. END inc. RETURN accumulate. t). BEGIN bin2int (x. int2bin (i. Navabi and McGraw-Hill Inc. END LOOP. END oring. END basic_utilities. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). IF i >= 2**x'LENGTH THEN i := 0. • Resolution functions and inc function added to basic_utilities CHAPTER 8 71 © 1999. FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'. END IF. i). END anding. Z. VARIABLE t : BIT_VECTOR (x'RANGE). RETURN t. i := i + 1.

were presented. The resolution functions developed in this chapter are typical of the way buses function in a digital system. which are considered to be among the most important hardware related constructs in the VHDL language.SUMMARY This chapter presented signal assignment. in general a resolved signal is a better representation of a circuit node. and guarded signals. This prepared the way for describing resolution functions. . Z. multiple drivers of signals. guarded assignments. Although VHDL only requires resolution of signals with multiple concurrent sources. A resolution function for a node can be written to match its technology-dependent behavior. or turning off a source. and resolution functions. Navabi and McGraw-Hill Inc. Guarded signal assignment and the concept of disconnection. • End Of Chapter 8 CHAPTER 8 72 © 1999.

1 Declarative Part of a Process 9.2 Description of Components 9.1.5.1.4.3 Design Implementation 9.2 Statement Part of a Process 9.6 Postponed Processes 9.5 MSI BASED DESIGN 9. Z.3.1.2.1 Sequential Use of Assertion Statements 9.1.5 Syntax Details of Process Statements 9.5.4 Interface Handshaking 9. .1 Top Level Partitioning 9. Navabi and McGraw-Hill Inc.3 Simulation Report 9.1.1.5.2 A Display Procedure 9.6 SUMMARY • • • • • • Constructs for sequential descriptions Process statement is a key construct Assertion for behavioral checks Handshaking constructs Timing control Formatted I/O CHAPTER 9 1 © 1999.4 FORMATTED ASCII I/O OPERATIONS 9.3.2 Two Phase Clocking 9.1 A Behavioral State Machine 9.4 A First Process Example 9.1.1.8 Behavioral Flow Control Constructs 9.CHAPTER 9 BEHAVIORAL DESCRIPTION OF HARDWARE 9.3 Implementing Handshaking 9.4.4.1 Basic Screen Output 9.2 ASSERTION STATEMENT 9.3.3 SEQUENTIAL WAIT STATEMENTS 9.3 Sensitivity List 9.3.2.7 Passive Processes 9.2 Concurrent Assertion Statements 9.1 PROCESS STATEMENT 9.

PROCESS STATEMENT
Concurrent process statement PROCESS Always alive process declarative_part (non-signal) ...

BEGIN

Always active process statement_part (sequential) ...

END PROCESS;

Process statements describe hardware without much hardware details

• • • •

PROCESS: A concurrent statement, enclosing sequential statements Declarative part contains only variables and constants Use only sequential constructs

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PROCESS BEGIN Reapets forever,
S e q u e n t i a l

In zero time,

Unless suspended

END PROCESS;

• Unless a sequential body is suspended • It executes in zero real and delta time • It repeats itself forever

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ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;

• • • • •

First: a is scheduled for x Next: b is scheduled for y x and y receive values at the same time Both assignments occur a delta later Zero time between both scheduling

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ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;

• First: a is scheduled for x • Next: b is scheduled for y • y receives b sooner than x receiving a

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ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;

• • • • •

Assume x_sig is initially '0' Assignment of '1' to x_sig takes a delta Action_2 will be taken Variable x_var had to be declared inside the Process statement If x_var was used instead of x_sig, action_1 would be taken

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ARCHITECTURE … BEGIN … a <= b; … c <= d; … END …;

ARCHITECTURE … BEGIN … PROCESS (b) … a <= b; END PROCESS; … c <= d; … END …;

Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation Any signal assignment can be expressed by a process statement

• • • • • •

Can use a signal assignment in a sequential body On the left: events on b cause assignment Process is executed when an event occurs on b On the right: (b) is sensitivity list of process Process statement executes only once for every event on b Process suspends till next event on b occurs
© 1999, Z. Navabi and McGraw-Hill Inc.

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PROCESS STATEMENT

R 1D Q

C1 S

Q

A flip-flop will demonstrate assignments and flow in process statements

• Have modeled flip-flops with concurrent statements • A process statement is a powerful construct for such descriptions

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• • • •

Three concurrent processes dff process is sensitive to (rst, set, clk) Internal state receives proper value Events on state cause events on q and qb

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ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;

• Single process assigns values to q and qb • This description eliminates the δ delay of the last description • Less precise timing

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TIME (NS) 0 +1δ δ 6 200 206 +1δ δ 500 1000 1200 1400 1406 +1δ δ 1500 2000 2200 2400 2500 2506 +1δ δ 3000 3300 3500 3506 +1δ δ 4000

ss '0' ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

rr '0' ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ...

cc '0' ... ... ... ... ... '1' '0' ... ... ... ... '1' '0' ... ... '1' ... ... '0' ... '1' ... ... '0'

dd '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ...

q1 '0' ... ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ...

q2 '0' ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ... ...

qb1 '0' '1' ... ... ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ...

qb2 '0' ... '1' ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ... ...

• Simulation run compares flip-flop descriptions • The 3 process description has a δ delay • However, potential of more precise timing

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;

• This example uses a record for delay and flip-flop values • Logic value and delay are assigned to variables • Assignment to variables are done in zero time without the δ delay

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set. sensitivity_list variable declaration process declarative part process statement ELSEIF rst = ‘1’ THEN state := ‘0’. END IF. ELSEIF clk = -‘1’ AND clk’EVENT THEN state := d. q <= state AFTER (sq_delay + rq_delay + cq_delay)/3. clk) VARIABLE state : BIT := ‘0’ BEGIN IF set = ‘1’ THEN state := ‘1’. sequential statement process statement part sequential statement sequential statement • Syntax details include sensitivity list CHAPTER 9 13 © 1999. Z. END PROCESS dff.PROCESS STATEMENT dff: PROCESS (rst. . qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3. Navabi and McGraw-Hill Inc.

END. . Navabi and McGraw-Hill Inc. clk) BEGIN . . set. . becomes active becomes active clk set rst t1+1δ δ δ t1+2δ t1+3δ δ • Postponed process • Wait until the last event in a real time increment • Signal assignments can become postponed CHAPTER 9 14 © 1999. dff : POSTPONED PROCESS(rst. . set.PROCESS STATEMENT dff : PROCESS(rst. clk) BEGIN . . END. Z.

delay. clk : IN BIT. rq_delay. ELSIF rst = '1' THEN sd := ('0'. END IF.PROCESS STATEMENT PACKAGE bt IS TYPE bit_time IS RECORD state : BIT. cq_delay). . q. clk) BEGIN q <= sd. BEGIN dff: PROCESS (rst. END RECORD.state AFTER sd. END PROCESS dff. END PACKAGE bt. ELSIF clk = '1' AND clk'EVENT THEN sd := (d. set. SHARED VARIABLE sd : bit_time := ('0'. rq_delay). -USE WORK. END PROCESS dff_arch. • A passive process statement may appear in the entity statement part • Cannot make assignments to signals • This models the same flip-flop CHAPTER 9 15 © 1999. qb <= NOT sd.ALL.delay. qb : OUT BIT). delay : TIME.bt. Navabi and McGraw-Hill Inc. Z. -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst. END ENTITY. 0 NS). set.state AFTER sd. PORT (d. cq_delay : TIME := 6 NS). rst. END behavioral. clk) BEGIN IF set = '1' THEN sd := ('1'. set. sq_delay). ENTITY d_sr_flipflop IS GENERIC (sq_delay.

• • • • Loop is a sequential statement Example runs forever unless exited EXIT & NEXT control flow of loops EXIT & NEXT can be conditioned CHAPTER 9 16 © 1999.. END IF. . EXIT WHEN condition.. Navabi and McGraw-Hill Inc. END LOOP long_runing. IF x = 25 THEN EXIT. NEXT loop_label WHEN condition. .PROCESS STATEMENT long_runing : LOOP .. Z..

. END LOOP loop_2. WHILE are controlled forms of loop Can still use NEXT and EXIT The above NEXT statement causes looping to continue with statements 1 17 © 1999.. ... CHAPTER 9 . Navabi and McGraw-Hill Inc. .PROCESS STATEMENT loop_1 : FOR i IN 5 TO 25 LOOP . sequential_statement_3. . sequential_statement_5. . loop_2 : WHILE j <= 90 LOOP ... • • • • Conditional Next Statements in a Loop FOR. sequential_statement_4.. Z... sequential_statement_1... END LOOP loop_1... sequential_statement_2.... . sequential_statement_6.. NEXT loop_1 WHEN condition_1.

• • • • Use assert to flag violations Use assert to report events Can be sequential or concurrent Severity: FAILURE ERROR WARNING NOTE CHAPTER 9 18 © 1999. OTHERWISE REPORT "reporting_message". MAKE SURE THAT assertion_condition IS TRUE. OTHERWISE REPORT "reporting_message" AND TAKE THE ACTION AT THIS severity_level. Z.ASSERTION STATEMENT ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level. REPORT “reporting_message” SEVERITY severity_level. Navabi and McGraw-Hill Inc. . MAKE SURE THAT false IS TRUE.

qb <= NOT state. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. .ASSERTION STATEMENT ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. Z. ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. END IF. set. q <= state. • Conditions are checked only when process is activated • Make sure that set='1' AND rst='1' does not happen • Severity NOTE issues message CHAPTER 9 19 © 1999. BEGIN dff: PROCESS (rst. END PROCESS dff. IF set = '1' THEN state <= '1' AFTER sq_delay. Navabi and McGraw-Hill Inc. END behavioral.

Z. ASSERT NOT things_that_should_not_happen REPORT a_message_that_bad_things_have_happened SEVIRITY action_to_take. Navabi and McGraw-Hill Inc. . • Good conditions may be too many to list • Good conditions = NOT (Bad conditions) • Easier to use NOT of unwanted cases CHAPTER 9 20 © 1999.ASSERTION STATEMENT ASSERT Good conditions REPORT Violation of good conditions SEVERITY Level.

Navabi and McGraw-Hill Inc.. Z.. CHAPTER 9 21 © 1999.ASSERTION STATEMENT clock setup time data hold time Setup and Hold time checks use assert statement and signal attributes • Use ASSERT to check setup and hold • ASSERT set_up_violation check REPORT. • ASSERT hold_violation check REPORT. ...

check for stable data • Check is placed after clock changes CHAPTER 9 22 © 1999. Navabi and McGraw-Hill Inc. . Z. if (data input has not been stable at least for the amount of the setup time). Setup Check in VHDL (clock = '1' AND NOT clock'STABLE) AND (NOT data'STABLE (setup_time)) • When the clock changes.ASSERTION STATEMENT clock setup time data hold time Setup Check in English When (clock changes from zero to 1). then a setup time violation has occurred.

. Hold Check in VHDL (data'EVENT) AND (clock = '1') AND (NOT clock'STABLE (hold_time)) • When data changes while clock is '1'. check for stable clock • Check is placed after data changes CHAPTER 9 23 © 1999. Navabi and McGraw-Hill Inc. then hold time violation has occurred.ASSERTION STATEMENT clock setup time data hold time Hold Check in English When (there is a change on the data input) if the (logic value on the clock is '1') and the (clock has got a new value more recent than the amount of hold time). Z.

q <= state. clk : IN BIT. set. hold : TIME := 4 NS). ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. set. BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING. qb <= NOT state.ASSERTION STATEMENT ENTITY d_sr_flipflop IS GENERIC (sq_delay. Navabi and McGraw-Hill Inc. END PROCESS dff. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. q. END behavioral. rq_delay. BEGIN dff: PROCESS (rst. IF set = '1' THEN state <= '1' AFTER sq_delay. setup. PORT (d. • Using assertion statements for illegal Set-Reset combinations • Setup and Hold time violations • Concurrent and sequential assertion statements CHAPTER 9 24 © 1999. cq_delay : TIME := 6 NS. END IF. . clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING. END d_sr_flipflop. rst. Z. qb : OUT BIT).

WAIT UNTIL a_signal_is_true. Navabi and McGraw-Hill Inc. WAIT UNTIL waiting_condition. WAIT UNTIL expression_with_signal_and_variable_is_true. WAIT. WAIT statements for flow control of sequential statements • • • • • • Sequential statements. WAIT ON some_event UNTIL a_condition FOR some_time. WAIT UNTIL event makes condition true. --"a long time" WAIT ON (event on a signal). Is the same as WAIT ON a_signal UNTIL signal_is_true. Is the same as WAIT ON the_signal UNTIL expression_is_true. WAIT ON waiting_sensitivity_list. CHAPTER 9 25 . --"forever" © 1999. Used for handshaking and delay modeling WAIT FOR real_time. WAIT FOR. WAIT FOR 0 NS. Z. WAIT.SEQUENTIAL WAIT STATEMENTS WAIT FOR waiting_time.

BEGIN … … … WAIT ON (a. b. c) . END ARCHITECTURE. c)...SEQUENTIAL WAIT STATEMENTS ARCHITECTURE … … BEGIN … PROCESS . A process with sensitivity behaves as A process with WAIT ON at the end • WAIT ON at the end is equivalent to using sensitivity list • Cannot use WAIT in a process with sensitivity list • WAIT suspends a Process CHAPTER 9 26 © 1999. BEGIN … … … … END PROCESS. ARCHITECTURE … … BEGIN … PROCESS (a.. END ARCHITECTURE. END PROCESS. . Navabi and McGraw-Hill Inc. Z. b..

SEQUENTIAL WAIT STATEMENTS Several examples will demonstrate WAIT statements in processes • A Moore 1011 detector • Can use WAIT in a Process statement CHAPTER 9 27 © 1999. Navabi and McGraw-Hill Inc. . Z.

IF x = '1' THEN current <= got101. IF x = '0' THEN current <= got10. END PROCESS. • • • • VHDL Description of the 1011 Sequence Detector Using Process and Wait Statements Each choice corresponds to a state Each state can be independently timed. z <= '0'. END behavioral_state_machine. got1011). WAIT UNTIL clk = '1'. ELSE current <= reset. clk : IN BIT.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. WAIT FOR 1 NS. and clocked CHAPTER 9 28 © 1999. Z. SIGNAL current : state := reset. . END IF. IF x = '1' THEN current <= got1. WHEN got10 => WAIT UNTIL clk = '1'. BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'. z : OUT BIT). END IF. END moore_detector. IF x = '1' THEN current <= got1. ELSE current <= reset. WHEN got1 => WAIT UNTIL clk = '1'. END IF. WHEN got101 => WAIT UNTIL clk = '1'. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. Navabi and McGraw-Hill Inc. got10. ELSE current <= got1. got1. got101. END IF. END CASE. WHEN got1011 => z <= '1'. ELSE current <= got10. ELSE current <= got10. IF x = '1' THEN current <= got1011. END IF.

z <= '0'. END IF. IF x = '0' THEN current <= got10. WAIT FOR 1 NS. got1011). END PROCESS. Navabi and McGraw-Hill Inc. SIGNAL current : state := reset. Z. WHEN got1 => WAIT UNTIL clk = '1'. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. z : OUT BIT)... END moore_detector. got10. END behavioral_state_machine. got101. BEGIN PROCESS BEGIN CASE current IS .. ..SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. • • • • • WAIT for rising edge of clk Assign new state to current Wait for transaction on current Can use WAIT ON current 'TRANSACTION instead Timing check flexibility in each state CHAPTER 9 29 © 1999. ELSE current <= got1. END CASE. . clk : IN BIT. got1.

END IF. z <= '1' WHEN current = got1011 ELSE '0'. END IF. Z. ELSE current <= reset.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. ELSE current <= got1. END behavioral_state_machine. END CASE. clk : IN BIT. ELSE current <= got10. got10. Navabi and McGraw-Hill Inc. WHEN got101 => IF x = '1' THEN current <= got1011. got1. got101. WHEN got10 => IF x = '1' THEN current <= got101. BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1. z : OUT BIT). END PROCESS. END IF. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. END IF. WHEN got1011 => IF x = '1' THEN current <= got1. • A simple state machine description • Not much timing flexibility • Allows a single clock • But easy and covers most cases CHAPTER 9 30 © 1999. END moore_detector. WHEN got1 => IF x = '0' THEN current <= got10. END IF. END IF. SIGNAL current : state := reset. ELSE current <= got10. ELSE current <= reset. . got1011).

Navabi and McGraw-Hill Inc.SEQUENTIAL WAIT STATEMENTS outputs next state Logic REG present state • Mealy machine detecting 101 • Use a style that separates logic and register parts • Also use an asynchronous reset CHAPTER 9 31 © 1999. . Z.

c). clk : IN BIT. ELSE nxt <= b. END IF. WHEN c => IF x = '0' THEN nxt <= a. END IF. x) BEGIN z <= '0'. • VHDL description for a state machine with asynchronous reset • Most synthesis tools accept this style • Flexible in register part control CHAPTER 9 32 © 1999. SIGNAL nxt. WHEN b => IF x = '0' THEN nxt <= c. Z. BEGIN reg : PROCESS (clk. CASE present IS WHEN a => IF x = '0' THEN nxt <= a. END CASE. z : OUT BIT). END IF. END PROCESS. r. ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt. IF present = c AND x = '1' THEN z <= '1'. b. r) BEGIN IF r = '1' THEN present <= a. -logic : PROCESS (present. . ELSE nxt <= b. END ENTITY. present : state.SEQUENTIAL WAIT STATEMENTS ENTITY asynch_reset_detector IS PORT (x. END IF. ELSE nxt <= b. END PROCESS. -ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a. END IF. Navabi and McGraw-Hill Inc. END behavioral.

. .0 1.5 2.. c2 <= '0'.. Time 0. Navabi and McGraw-Hill Inc. Z.. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'.SEQUENTIAL WAIT STATEMENTS . WAIT FOR 480 NS..0 US c1 c2 10NS 10NS • Generation of the second phase of a two phase non-overlapping clocking • c2 is generated by phase2 process CHAPTER 9 33 © 1999. WAIT FOR 10 NS. c2 <= '1'.5 1. END PROCESS phase2.

data_ready <= '1'. data_ready <= '0'. Z.start the following when ready to send data_lines <= newly_prepared_data.start the following when ready to accept data WAIT UNTIL data_ready = '1'.start processing the newly received data WAIT UNTIL data_ready = '0'. Navabi and McGraw-Hill Inc. WAIT UNTIL accepted = '1'. accepted <= '0'. B accepts data • B releases A when data is picked CHAPTER 9 34 © 1999.SEQUENTIAL WAIT STATEMENTS data_lines system A data_ready valid data accepted system B Process Data System A: -. -. • Systems A & B talk • A prepares data. accepted <= '1'. --can use data_lines for other purposes System B: -. .

SEQUENTIAL WAIT STATEMENTS 4 SYSTEM I in_data in_ready 16 out_data A in_received out_ready out_received B • • • • Use handshaking mechanism in an interface A prepares 4 bit data. talk to B to put data CHAPTER 9 35 © 1999. Z. Navabi and McGraw-Hill Inc. . B needs 16 bit data Create interface system I Talk to A to get data.

-. and word_buffer for a_talk and b_talk communication CHAPTER 9 36 © 1999. END PROCESS b_talk..Talk to A. buffer_picked. Z. -.. -ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full.. buffer_picked : BIT := '0'. SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0).When ready. collect 4 4-bit data.. b_talk: PROCESS BEGIN .. END system_i. in_ready.SEQUENTIAL WAIT STATEMENTS ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0).. • a_talk process & b_talk process also talk to each other • Use buffer_full.When data is received. send to B using proper handshaking .. END PROCESS a_talk. out_received : IN BIT. in_received. BEGIN a_talk: PROCESS BEGIN .Wait for 16-bit data from a_talk -. keep a count -. pass 16-bit data to b_talk .. out_ready : OUT BIT). . Navabi and McGraw-Hill Inc. END waiting. out_data : OUT BIT_VECTOR (15 DOWNTO 0).

out_ready <= '1'. WAIT UNTIL buffer_picked = '1'. END PROCESS b_talk. . WAIT UNTIL buffer_full = '0'. END IF. count := count + 1. WAIT UNTIL in_ready = '0'. buffer_full <= '1'. WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data. out_ready <= '0'. in_received <= '0'. BEGIN WAIT UNTIL in_ready = '1'. WAIT UNTIL out_received = '1'. • a_talk gets data from A and talks to b_talk • b_talk talks to a_talk and sends data to B CHAPTER 9 37 © 1999. in_received <= '1'. Z. buffer_picked <= '1'. END PROCESS a_talk. WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data. END CASE. CASE count IS WHEN 0 => NULL. WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data. Navabi and McGraw-Hill Inc. count := 0. buffer_picked <= '0'.SEQUENTIAL WAIT STATEMENTS a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0. out_data <= word_buffer. WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data. buffer_full <= '0'. b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'.

SEQUENTIAL WAIT STATEMENTS clock Arbiter req ues t1 gra nt1 req ues t2 gra nt2 38 • • • • • req ues t0 gra nt0 Bus arbiter interface Simplified for this first example Synchronized arbitration A request input stays asserted until granted A request input is granted only one clock cycle of bus use CHAPTER 9 © 1999. req ues t3 gra nt3 . Z. Navabi and McGraw-Hill Inc.

END LOOP. clock : IN BIT). END PROCESS wait_cycle. • Bus arbiter description • Check all requests after the falling edge of the clock • Because of the 20 NS wait. Z. END arbiter. END IF. grant (i) <= '1'. Navabi and McGraw-Hill Inc. FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000". END behavioral. process sensitivity cannot be used CHAPTER 9 39 © 1999. -ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. WAIT ON clock. . ELSE grant (i) <= '0'. grant : BUFFER BIT_VECTOR (3 DOWNTO 0).SEQUENTIAL WAIT STATEMENTS ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0). END IF.

r(i) <= '0'. -ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT. clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk. WAIT UNTIL clk = '0'. r(i) <= '1'. Z.SEQUENTIAL WAIT STATEMENTS ENTITY arbtest IS END arbtest. TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME. CONSTANT delays : time_array := (4 US. 15 US. g : BIT_VECTOR (3 DOWNTO 0). SIGNAL r. Navabi and McGraw-Hill Inc. 8 US). END PROCESS. END GENERATE. clk).arbiter PORT MAP (r. . 3 US. WAIT UNTIL g(i) = '1'. BEGIN arb : ENTITY WORK. sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i). CONSTANT t : TIME := 1 US. • Testing the arbiter • Four processes for generating data are generated • The time_array constant specifies timing requests coming from a source CHAPTER 9 40 © 1999. g. END io.

. if stop bit is not seen Overrun error if start bit appears too soon CHAPTER 9 41 © 1999.SEQUENTIAL WAIT STATEMENTS S2P da tar ea dy ov err un fra me _e rro r pa ral lel _o ut serial rec eiv ed 8 A 10 bit frame reading begins start bit data bits stop bit • • • • • Another example using WAIT statements Serial_to_parallel interface RS232 frame with one start bit and one stop bit Framing error. Navabi and McGraw-Hill Inc. Z.

0 * 1 US. WAIT FOR half_bit. WAIT ON dataready. overrun <= '1'. frame_error <= '0'. Z. overrun <= '0'. END LOOP. END IF. BEGIN WAIT UNTIL serial = '1'. • • • • • Serial2parallel VHDL description Two concurrent processes One waits for prepared data to be picked up (collect). buff (count) := serial. FOR count IN 0 TO 7 LOOP WAIT FOR full_bit. PORT (serial. END IF. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). ELSE WAIT UNTIL received = '0'. frame_error : OUT qit. IF dataready = '1' THEN dataready <= '1'. END waiting. END serial2parallel. WAIT UNTIL received = '1'. CONSTANT half_bit : TIME := (1E6/REAL(bps))/2. -ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS --VARIABLE buff : qit_vector (7 DOWNTO 0). while The other waits for untimely serial data to arrive (too_fast) WAIT statements are used in both processes 42 © 1999. BEGIN WAIT UNTIL serial = '0'.SEQUENTIAL WAIT STATEMENTS ENTITY serial2parallel IS GENERIC (bps : INTEGER). dataready <= '0'. END IF. overrun. received : IN qit. IF dataready = '1' THEN ELSE WAIT UNTIL serial = '0'. IF serial = '0' THEN too_fast : PROCESS frame_error <= '1'. CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US. parallel_out <= buff. dataready : BUFFER qit. Navabi and McGraw-Hill Inc. CHAPTER 9 . END PROCESS collect. END PROCESS too_fast. WAIT FOR full_bit.

to read data from a line a line WRITE procedure. OUTPUT files for standard device IO READLINE procedure. a pointer to STRING TEXT file type. to check the end of a file Examples will demonstrate TEXTIO package and its applications • Only CHARACTERS are handled • All predefined standard types are converted to CHARACTERS • Subprograms are overloaded for all standard types CHAPTER 9 43 © 1999. to read data from a line a line ENDFILE function. of CHARACTER type INPUT.FORMATTED ASCII I/O OPERATIONS TEXTIO package is in the STD library TEXTIO contains: LINE type. Navabi and McGraw-Hill Inc. to read a line from file READ procedure. . to write data into a WRITELINE procedure. Z. to write line to file READ procedure.

“input. “output.. and unit if v is of type TIME CHAPTER 9 44 © 1999.).reads a value v of its type from l WRITE(l. FILE_OPEN (f.txt”..) -. . . Navabi and McGraw-Hill Inc. READ_MODE). CHARACTER.returns TRUE if the end of f • READ and WRITE procedures are valid for: BIT.txt”. FILE_OPEN (f. v. FILE_CLOSE (f). size. BOOLEAN. -. BIT_VECTOR. .txt”. FILE f : TEXT. Z. and TIME • Other parameters of these procedures include orientation. “output. FILE f : TEXT OPEN READ_MODE IS “input. WRITE_MODE). INTEGER. REAL. -..txt”. STRING. FILE f : TEXT IS “input. l) -. v.writes l to file f ENDFILE(f) -.read a line of file f into buffer l READ(l. APPEND_MODE).FORMATTED ASCII I/O OPERATIONS VARIALE I : LINE. READLINE(f.txt”. FILE_OPEN (f.writes the value v to LINE l WRITELINE(f.. l).

.TEXTIO. RETURN sources(sources'LEFT). Z. got10. BEGIN FOR i IN sources'RANGE LOOP WRITE (l.FORMATTED ASCII I/O OPERATIONS USE STD.ALL. TYPE state IS (reset. Navabi and McGraw-Hill Inc. 7). FUNCTION one_of (sources : state_vector) RETURN state IS VARIABLE l : LINE. WRITELINE (flush. END LOOP. . l). FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty".. LEFT. END one_of. • A resolution function that writes its active drivers each time it is called • New code is highlighted • Unix device tty is the standard output • Can use OUTPUT. defined in VHDL for the standard output • INPUT and OUTPUT work in all operating systems CHAPTER 9 45 © 1999. state'IMAGE(sources(i)). TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. . got101). got1.

ELSIF value1'EVENT THEN WRITE (l. • A display procedure for writing time and events • New values are listed • Filler is used for signal values that do not change CHAPTER 9 46 © 1999. 0). Z. value2.. LEFT. Navabi and McGraw-Hill Inc. value1. VARIABLE l : LINE. 3). VARIABLE filler : STRING (1 TO 3) := " .FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. RIGHT. WRITE (l. RIGHT. value2. l).". NS). END IF. WRITE (l. END display. RIGHT. ELSE WRITE (l. value1. WRITE (l. IF value1'EVENT AND value2'EVENT THEN WRITE (l. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". LEFT. filler. RIGHT. filler. 8. . RIGHT. 3). WRITELINE (flush. 3). 3). BEGIN WRITE (l. NOW. 0).

". filler. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. Navabi and McGraw-Hill Inc. ELSIF value1'EVENT THEN WRITE (l. filler. value1. 3). NOW. RIGHT. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. BEGIN SIGNAL c2 : BIT := '0'. LEFT.TEXTIO. USE STD. WRITELINE (flush. END display.ALL. RIGHT. WRITE (l. WRITE (l. RIGHT. . value1. WAIT FOR 480 NS. WAIT FOR 10 NS. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". display (c1. Z. c2). ENTITY two_phase_clock IS END two_phase_clock. 3). WRITE (l. RIGHT. RIGHT. VARIABLE l : LINE. 3). c2 <= '0'. END IF. VARIABLE filler : STRING (1 TO 3) := " . 3). • Call the display procedure anytime a clock phase changes • This procedure is also called once at the beginning of simulation CHAPTER 9 47 © 1999. ELSE WRITE (l. value2. NS). 0). c2 <= '1'.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. IF value1'EVENT AND value2'EVENT THEN WRITE (l. 8. END PROCESS phase2. l). BEGIN WRITE (l. 0). phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. LEFT.. value2. END input_output.

0). WRITE (l. value1. 3). value1. LEFT. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. ELSIF value1'EVENT THEN WRITE (l. RIGHT. l). END displaying. Navabi and McGraw-Hill Inc. WRITELINE (flush. value2. VARIABLE l : LINE. value2 : BIT. END IF. RIGHT. 3). WRITE (l. END displaying. 0). BEGIN WRITE (l. NOW. . WRITE (l. IF value1'EVENT AND value2'EVENT THEN WRITE (l. FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " . RIGHT. END display. filler. ELSE WRITE (l. filler. value2 : BIT. NS). • A procedure for writing in an already open file • A file of type TEXT is passed to this procedure • This goes in our new displaying package CHAPTER 9 48 © 1999. 3). value2.. FILE flush : TEXT). RIGHT. 8. LEFT.". Z.FORMATTED ASCII I/O OPERATIONS PACKAGE displaying IS PROCEDURE display (SIGNAL value1. RIGHT. 3).

FORMATTED ASCII I/O OPERATIONS USE STD.ALL. value2 : BIT. END display.. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. PACKAGE displaying IS PROCEDURE display (SIGNAL value1..ALL. WAIT FOR 10 NS. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'.out". -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. data). FILE flush : TEXT) IS . c2 <= '0'. ENTITY two_phase_clock IS END two_phase_clock. BEGIN display (c1. END displaying. SIGNAL c2 : BIT := '0'. value2 : BIT.displaying. USE WORK.ALL. c2 <= '1'. FILE flush : TEXT). END PROCESS phase2. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. Z. END input_output. Navabi and McGraw-Hill Inc. . USE STD.TEXTIO. END displaying. WAIT FOR 480 NS.TEXTIO. c2. • Passing an open file to a procedure • File declaration takes place in the declarative part of an architecture • File remains open after being written into • Writing can continue elsewhere CHAPTER 9 49 © 1999. FILE data : TEXT OPEN WRITE_MODE IS "clock.

. Navabi and McGraw-Hill Inc. 1 0 . ... Z. ... .. • Output file generated by the input_output architecture • File closes at the end of simulation CHAPTER 9 50 © 1999. .FORMATTED ASCII I/O OPERATIONS 0 500 510 990 1000 1500 1510 1990 2000 2500 2510 2990 3000 3500 3510 3990 4000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns .... 1 0 .. 1 0 .. 1 0 .... . 0 . 1 0 . . .. 1 0 .. . 1 0 .. 1 0 .

".out". PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| ". RIGHT. IS WAIT FOR 10 NS. ELSE END input_output. lo_value.FORMATTED ASCII I/O OPERATIONS c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US USE STD. BEGIN END PROCESS phase2. . l). SIGNAL c1 : BIT := '1'. ELSE WRITE (l. END PROCEDURE append_wave_slice. NS). IF s = '1' THEN WRITE (l. 5).TEXTIO. ELSE ENTITY two_phase_clock IS END two_phase_clock. 0). IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN append_wave_slice (c1). VARIABLE hi_to_lo : STRING (1 TO 3) := "+-. c1. Navabi and McGraw-Hill Inc. SIGNAL c2 : BIT := '0'. FILE flush : TEXT OPEN WRITE_MODE IS "clock4. print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED. lo_to_hi. ELSE WRITE (l. header. BEGIN END IF. LEFT. Z. RIGHT. 5). RIGHT. RIGHT. hi_to_lo. IF NOW = 0 US THEN VARIABLE lo_to_hi : STRING (1 TO 3) := ". 5). WAIT FOR 480 NS. END IF. c1. END PROCESS writing. c2 <= '1'. append_wave_slice (c2). CONSTANT print_resolution : TIME := 5 NS. l). END IF. WRITELINE (flush. IF s = '1' THEN WRITE (l. 8. NOW. RIGHT. SIGNAL print_tick : BIT := '0'.-+". WRITE (l. END IF. calls the append_wave_slice procedure Buffer l is visible in the procedure.ALL. hi_value. c2 <= '0'. writing: PROCESS (print_tick. phase2: PROCESS -BEGIN ARCHITECTURE input_output OF two_phase_clock WAIT UNTIL c1 = '0'. appending is done to this line CHAPTER 9 51 © 1999. WRITE (l. VARIABLE header : STRING (1 TO 18) := " c1 c2 ". c2) • • • • Generating an ASCII plot file 5 NS print resolution reports of the two-phase clock description Process wakes up. VARIABLE l : LINE. BEGIN VARIABLE hi_value : STRING (1 TO 3) := " |". 5). WRITELINE (flush.

-+ | | | • • • • • Plot generated by the ploting process Plotting is activated every 5 NS Write " |" for '1'.. ns ns ns ns ns ns ns ns ns ns ns | | | | +-. | | | | | | c2 | | | | | | | .. Z.-+" for 0 to 1 CHAPTER 9 52 © 1999." for 1 to 0 Write ". "| " for '0' Write "+-. Navabi and McGraw-Hill Inc. .FORMATTED ASCII I/O OPERATIONS c1 480 485 490 495 500 505 510 510 515 520 525 .

MSI BASED DESIGN 8 data_in clk clear_bar load_bar count_in 4 sequential comparator 4 count Produces modulo-16 count of consecutive matching data Closing the chapter. Navabi and McGraw-Hill Inc. will present a top-down design with MSI parts • • • • Sequential comparator circuit Design based on MSI parts 74LS377. Z. 74LS85. 74LS163 Assume these parts are available CHAPTER 9 53 © 1999. .

.MSI BASED DESIGN sequential comparator 8-bit register 8-bit comparator 4-bit counter 4-bit comparator 4-bit comparator • Partition the circuit into smaller components • Partition until library components or synthesizable parts are reached • Will use top-down technique in designing a CPU in Chapter 10 CHAPTER 9 54 © 1999. Navabi and McGraw-Hill Inc. Z.

Navabi and McGraw-Hill Inc.MSI BASED DESIGN 74LS377 74LS85 74LS163 5CT=0 CTRDIV16 M1 M2 3CT=15 G3 G4 C5/2. Z. 5D [1] [2] [4] [8] • Standard MSI parts • Register.3. . counter CHAPTER 9 55 © 1999.4+ GI 1C2 < = > P P<Q P=Q P>Q Q 2D 1. comparator.

END ls85_comparator. lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay. -ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a. ordering for array operands • Default delays can be configured later CHAPTER 9 56 © 1999. b : IN qit_vector (3 DOWNTO 0).ALL. ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS). END PROCESS. END behavioral.MSI BASED DESIGN USE WORK. Navabi and McGraw-Hill Inc. a_lt_b <= lt AFTER prop_delay. a_eq_b <= '0' AFTER prop_delay. b. a_eq_b <= '0' AFTER prop_delay. END IF. eq. a_lt_b <= '1' AFTER prop_delay. gt. Z. a_eq_b. PORT (a. ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay. a_lt_b : OUT qit). ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay. a_lt_b <= '0' AFTER prop_delay. • 74LS85. . lt : IN qit.basic_utilities. a_gt_b. eq. gt. a_eq_b <= eq AFTER prop_delay. four bit comparator • Relational operators.

Navabi and McGraw-Hill Inc. ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS). • 74LS377. Z. q8 <= GUARDED d8 AFTER prop_delay. d8 : IN qit_vector (7 DOWNTO 0). BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0'). END dataflow. q8 : OUT qit_vector (7 DOWNTO 0)).MSI BASED DESIGN USE WORK.ALL.basic_utilities. PORT (clk. END ls377_register. . -ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN. clocked register • Default delays can be used or reconfigured CHAPTER 9 57 © 1999. g_bar : IN qit.

abcd : IN qit_vector (3 DOWNTO 0). ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count). • 74LS163. rco : OUT qit). END IF. END IF. ld_bar. PORT (clk.ALL. BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000". ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS). ELSIF (ld_bar = '0') THEN internal_count := abcd.MSI BASED DESIGN USE WORK.basic_utilities. END behavioral. IF (internal_count = "1111" AND ent = ‘1’) THEN rco <= '1' AFTER prop_delay. . Z. -ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000". enp. q_abcd : OUT qit_vector (3 DOWNTO 0). clr_bar. four bit synchronous counter • Default delays can be overwritten CHAPTER 9 58 © 1999. ent : IN qit. q_abcd <= internal_count AFTER prop_delay. END ls163_counter. Navabi and McGraw-Hill Inc. END PROCESS counting. END IF. ELSE rco <= '0'.

. specify delay CHAPTER 9 59 © 1999. Navabi and McGraw-Hill Inc.MSI BASED DESIGN LS377_register(behavioral) clk clear_bar load_bar data_in 8 4 8 clk d8 reg: d_register 4 q8 4 standard sequential comparator(structural) LS163_counter(behavioral) a b gt eq lt cmp_hi: comparator a_gt_b a_eq_b a_lt_b clk clr_bar load_bar enp ent abcd cnt: counter rco 4 q_abcd count g_bar prop_delay prop_delay 4 a b count_in gt eq lt 4 cmp_lo: comparator a_gt_b a_eq_b prop_delay a_lt_b prop_delay 15NS 18NS LS85_comparator(behavioral) 22NS • Design is based on available parts • Configure to use LS library. Z.

SIGNAL vdd : qit := '1'. gt_i. count_in. COMPONENT counter PORT (clk. cnt: counter PORT MAP (clk.basic_utilities. eq_i. END structural. eq_i. lt : IN qit. vdd. compare_out. OPEN. a_lt_b : OUT qit).MSI BASED DESIGN USE WORK. q_abcd : OUT qit_vector (3 DOWNTO 0). old_data). clr_bar. a_gt_b. b : IN qit_vector (3 DOWNTO 0). OPEN). g_bar : IN qit. lt_i). count : OUT qit_vector (3 DOWNTO 0) ). Z. ent : IN qit. END COMPONENT. vdd.ALL. lt_i : qit. eq_i. clear_bar. gnd. eq. d8 : IN qit_vector (7 DOWNTO 0). END sequential_comparator. ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0). enp. specify delay CHAPTER 9 60 © 1999. abcd : IN qit_vector (3 DOWNTO 0). END COMPONENT. lt_i. ld_bar. cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4). compare_out. SIGNAL gt_i. gt. SIGNAL compare_out : qit. BEGIN reg: d_register PORT MAP (clk. cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0). COMPONENT comparator PORT (a. SIGNAL old_data : qit_vector (7 DOWNTO 0). a_eq_b. clear_bar. • Design is based on available parts • Assert statement in the entity declaration • Configure to use LS library. clk. rco : OUT qit). OPEN). count_in : IN qit_vector (3 DOWNTO 0). load_bar : IN qit. -ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk. BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING. gt_i. END COMPONENT. old_data (3 DOWNTO 0). . gnd. q8 : OUT qit_vector (7 DOWNTO 0)). data_in. count. Navabi and McGraw-Hill Inc. load_bar. SIGNAL gnd : qit := '0'. old_data (7 DOWNTO 4). gnd.

ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS). FOR ALL : comparator USE ENTITY WORK. END standard.ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS).MSI BASED DESIGN USE WORK. FOR cnt : counter USE ENTITY WORK. • Configuring the structural architecture of the sequential_comparator • Configuration declaration binds to 74LS parts • Generic values overwrite those of the 74LS parts CHAPTER 9 61 © 1999. END FOR. Navabi and McGraw-Hill Inc. END FOR. END FOR. Z. .ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS).ALL. END FOR. CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK.

BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck.basic_utilities. count_in : IN qit_vector (3 DOWNTO 0). SIGNAL ck. load_bar : IN qit. ck. cnt_out). cnt. "10101100" AFTER 5 US. clk. ld_bar. END input_output. cl_bar. ld_bar <= '1'.MSI BASED DESIGN USE WORK. Navabi and McGraw-Hill Inc.standard. "0111" AFTER 55 US. Z. FOR mfi : seq_comp USE CONFIGURATION WORK. '0' AFTER 60 US. cl_bar. SIGNAL data : qit_vector (7 DOWNTO 0). . data <= "00000000". '1' AFTER 55 US. cnt <= "1111". END COMPONENT. count : OUT qit_vector (3 DOWNTO 0) ). ld_bar : qit. '0' AFTER 50 US. "01010100" AFTER 25 US. mfi : seq_comp PORT MAP (data. "1011" AFTER 40 US. • Testbench verifies behavior • Configuration specification associates mfi: seq_comp with the standard configuration declaration CHAPTER 9 62 © 1999. -ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0). "01110111" AFTER 3 US. cl_bar <= '1'.ALL. SIGNAL cnt_out : qit_vector (3 DOWNTO 0). SIGNAL cnt : qit_vector (3 DOWNTO 0). clear_bar. ENTITY test_sequential_comparator IS END test_sequential_comparator.

a hardware designer can completely describe a digital circuit without having to use these constructs. In the first part of the chapter. Although behavioral level constructs of VHDL provide a convenient method of describing very complex hardware. . Navabi and McGraw-Hill Inc.SUMMARY This chapter presented descriptions of hardware at the behavioral level and discussed how a process statement can be used to describe the main functionality of a module. • End Of Chapter 9 CHAPTER 9 63 © 1999. Various forms of wait statements were extensively used in these descriptions. We then showed how process statements are used to describe controlling hardware. Behavioral descriptions can be read and understood by non-technical managers and others who are not very familiar with VHDL. handshaking. syntax and semantics for various forms of this construct were described. and file I/O. Z.

3. Navabi and McGraw-Hill Inc.5.1 DEFINING A COMPREHENSIVE EXAMPLE 10.5.2.7 A MORE REALISTIC PARWAN 10.4.2.2 Packages 10.7. Z.4 Parwan Behavioral Architecture 10.2 Global View of Parwan Components 10.5 DATAFLOW DESCRIPTION OF PARWAN 10.5.1 Interconnection of Components 10.3 Instruction Format 10.3 Instruction Execution 10.2 PARWAN CPU 10.1 Memory Organization of Parwan 10.CHAPTER 10 CPU MODELING AND DESIGN 10.5.3 BEHAVIORAL DESCRIPTION OF PARWAN 10.3 Hardware Modifications 10.5.5.7.4.8 SUMMARY CHAPTER 10 1 © 1999.3.2.2 Timing of Data and Control Events 10.6 A TEST BENCH FOR THE PARWAN CPU 10.1 Data and Control Partitioning 10.2.2 Instruction Set 10.5.2 Synthesizability 10.3.3 General Description Methodology 10.4.4 Description of Components 10.4 Programming in Parwan Assembly 10.3 Interface Description of Parwan 10.4 PARWAN BUSSING STRUCTURE 10. .7 Wiring Data and Control Sections 10.3.5 Data Section of Parwan 10.6 Control Section of Parwan 10.7.1 Timing and Clocking 10.1 CPU Control Signals 10.

Z.DEFINING A COMPREHENSIVE EXAMPLE MAR PC IR SR AC ALU SHU Controller Will define a CPU describe it in VHDL. A Reduced Processor Simple 8-bit CPU. 8-bit Data. and show its hardware details • • • • • General Layout of Parwan PARWAN. Navabi and McGraw-Hill Inc. PAR_1. . 12-bit Address Primarily designed for educational purposes Includes most common instructions CHAPTER 10 2 © 1999.

page 2 . .PARWAN CPU 7 6 1 1 1 0 0 9 Page 0 8 0 0 7 6 0 5 0 4 0 0 3 2 0 1 0 0 0:00 . . . . . page 1 .2:FF MEMORY: 5 4 3 2 page 0 .0:FF 1:00 . .E:FF F:00 . page 15 .1:FF 2:00 . Z. 1 0 Offset E:00 . Navabi and McGraw-Hill Inc. • • • • • Page and Offset Parts of Parwan addresses Memory divided into pages Pages of 256 bytes Address has page and offset part Uses memory mapped IO CHAPTER 10 3 © 1999.F:FF page 14 .

ASL. SUB. BRA_C. (12 bits) direct/indirect LDA. BRA_V. STA PAGE Address. JMP. CMC. ADD. . ASR • • • • Three groups of instructions Full Address instructions include page and offset Page address instructions include offset No Address instructions occupy a single byte CHAPTER 10 4 © 1999. CMA. Z. Navabi and McGraw-Hill Inc. AND. BRA_N NO Address NOP. (8 bit) JSR. BRA_Z.PARWAN CPU FULL Address. CLA.

Z. Load and store operations Arithmetic & logical operations jmp and branch instructions CHAPTER 10 5 © 1999. Navabi and McGraw-Hill Inc. .Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Brief Description Load AC w/(loc) AND AC w/(loc) Add (loc) to AC Sub (loc) from AC Jump to adr Store AC in loc Subroutine to tos Branch to adr if V Branch to adr if C Branch to adr if Z Branch to adr if N No operation Clear AC Complement AC Complement carry Arith shift left Arith shift right Address Bits 12 12 12 12 12 12 8 8 8 8 8 - Address Scheme FULL FULL FULL FULL FULL FULL PAGE PAGE PAGE PAGE PAGE NONE NONE NONE NONE NONE NONE Indirect Address YES YES YES YES YES YES NO NO NO NO NO NO NO NO NO NO NO Flags Use -------c--c----------v---c---z---n ----------c-------- Flags Set --zn --zn vczn vczn -----------------------------zn -c-vczn --zn • • • • Summary of Parwan instructions.

Z. .PARWAN CPU Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Opcode Bits 765 000 001 010 011 100 101 110 111 111 111 111 111 111 111 111 111 111 D/I Bit 4 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 0 0 0 0 0 0 Bits 3210 Page adr Page adr Page adr Page adr Page adr Page adr ---1000 0100 0010 0001 0000 0001 0010 0100 1000 1001 • Parwan instruction opcodes • CPU contains V C Z N flags • Instructions use and/or influence these flags CHAPTER 10 6 © 1999. Navabi and McGraw-Hill Inc.

SUB. SUB. SUB. ASL. ASL. Navabi and McGraw-Hill Inc. CMA. CMA. Z.PARWAN CPU influence ADD. . ADD. ASL. SUB. AND. ASR ADD. AND. CMC ADD. ASL ADD. CMC BRA_Z BRA_N • Arithmetic instructions influence all flags • Branch instructions use corresponding flags • Shift instructions influence all flags CHAPTER 10 7 © 1999. LDA. LDA. SUB. ASR use V C Z N BRA_V BRA_C.

Z. . Navabi and McGraw-Hill Inc.complete address pg: loc opc page pg: loc+1 offset • • • • • Addressing in full-address instructions Full address instructions use two bytes Right hand side of first byte is page Second byte contains offset Bit 4 is direct/indirect [0/1] indicator CHAPTER 10 8 © 1999.

Navabi and McGraw-Hill Inc.PARWAN CPU complete address pg: loc jsr or branch pg: loc+1 offset • • • • • Addressing in page-address instructions Page address instructions use two bytes All of first byte is used by opcode Page part of address uses current page Second byte is the offset CHAPTER 10 9 © 1999. Z. .

Navabi and McGraw-Hill Inc.PARWAN CPU MEMORY .. BRANCH TO 6A if carry is set c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A • Branching is done within current page only • A branch instruction CHAPTER 10 10 © 1999. . Z... BRA_C 6A 5:0D 5:0E 5:0F 11110100 6A ..

before and after jsr Store jsr return address at tos Begin subroutine at tos+1 Use indirect jmp to tos for return from subroutine CHAPTER 10 11 © 1999. . Z... 5:33 5:34 00000000 SUBROUTINE CODE .. JSR 3 3 INSTR AFTER JSR ..... 5:55 5:56 5:57 JMP Indirect 3 3 B E F O R E J S R 5:55 5:56 5:57 JMP Indirect 3 3 . 1 3 SUBROUTINE CODE .. .. A F T E R J S R • • • • • An example for the execution of jsr Memory and pc. 5:33 PC-> 5:34 .. ......PARWAN CPU MEMORY PC-> 5:11 5:12 5:13 MEMORY 5:11 5:12 5:13 ... JSR 3 3 INSTR AFTER JSR . Navabi and McGraw-Hill Inc..

.PARWAN CPU Indirect address Actual address Data Any page and offset Same page Indirecting effects offset operand 0:25 opc 1 6 6:1F 1 8 0:26 3 5 6:35 1 F • • • • An example for indirect addressing in Parwan. Navabi and McGraw-Hill Inc. Z. Indirect addressing affects offset only To obtain actual address full addressing is used To obtain data page addressing is used CHAPTER 10 12 © 1999.

Navabi and McGraw-Hill Inc.clear accumulator -.load 10 in 4:01 -.load 01 in 4:02 -.end if zero count -.store count back -.go for next byte -.load count -. .load pointer -.store partial sum -.clears carry 4:00 -.load 25 in 4:00 -. Z.decrement count :2D -. i sta 4:03 lda 4:00 add 4:02 sta 4:00 lda 4:01 sub 4:02 bra_z sta 4:01 lda 4:03 jmp 0:17 nop -.add bytes -.store pointer back -.PARWAN CPU 0:15 0:16 0:17 0:19 0:1B 0:1D 0:1F 0:21 0:23 0:25 0:27 0:29 0:2B 0:2D cla asl add.increment pointer -.adding completed • • • • • An example program for Parwan CPU A program to add 10 bytes Use location 4:00 for data pointer Use location 4:01 for counter Constant 1 in 4:02 is used for +1 and -1 CHAPTER 10 13 © 1999.get partial sum -.

END par_central_processing_unit. .par_utilities.. Navabi and McGraw-Hill Inc. USE par_library.. Coding for the behavioral description of Parwan will be presented. -ENTITY par_central_processing_unit IS .ALL.par_parameters.ALL. -ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral.ALL. USE par_library. -LIBRARY par_library. • Packages used will be described • A single component will describe all of Parwan CHAPTER 10 14 © 1999.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. USE cmos.basic_utilities. Z.

SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0). CONSTANT zero_12 : twelve := "000000000000". cin : qit) RETURN qit_vector. -END par_utilities. -SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0). CONSTANT zero_8 : byte := "00000000". -PACKAGE par_utilities IS FUNCTION "XOR" (a.basic_utilities. FUNCTION sub_cv (a. Z. FUNCTION "AND" (a. SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0).BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. SUBTYPE byte IS qit_vector (7 DOWNTO 0). • • • • Declarations of par_utilities package of par_library Machine descriptions require utilities Use basic_utilities Additional utilities are included in par_utilities CHAPTER 10 15 © 1999. -FUNCTION set_if_zero (a : qit_vector) RETURN qit. -FUNCTION add_cv (a. SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0). -CONSTANT zero_4 : nibble := "0000". FUNCTION "NOT" (a : qit_vector) RETURN qit_vector. b : qit_vector) RETURN qit_vector. b : qit_vector. FUNCTION "OR" (a. SUBTYPE twelve IS qit_vector (11 DOWNTO 0). USE cmos. -SUBTYPE nibble IS qit_vector (3 DOWNTO 0). b : qit_vector. -SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0). . SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0).ALL. cin : qit) RETURN qit_vector. b : qit) RETURN qit . Navabi and McGraw-Hill Inc. b : qit_vector) RETURN qit_vector.

('1'.'1'. • Body of par_utilities package of par_library library • Define XOR in qit • Overload logical operators with qit_vector CHAPTER 10 16 © 1999. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i).'0'.'X').'X'). Z. ('X'.'X'). BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i). END LOOP loop1. ('1'. RETURN r. FUNCTION "AND" (a. b).b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE). END LOOP loop1. END "OR". END "NOT". END "XOR". END "AND". RETURN r. END LOOP loop1.'X')).'X'. -FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE).'1'.b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE). .'0'.'0'. -FUNCTION "OR" (a.'X'. b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0'.BEHAVIORAL DESCRIPTION OF PARWAN PACKAGE BODY par_utilities IS FUNCTION "XOR" (a. Navabi and McGraw-Hill Inc. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i). BEGIN RETURN qit_xor_table (a.'0'. RETURN r.

END LOOP. c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)). cin : qit) RETURN qit_vector IS VARIABLE r. END IF. RETURN r. END set_if_zero. BEGIN not_b := NOT b. FUNCTION sub_cv (a. --overflow ELSE r(a'LEFT+2) := '0'. IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'. next to msb: carry VARIABLE a_sign.BEHAVIORAL DESCRIPTION OF PARWAN FUNCTION add_cv (a. BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'. VARIABLE not_c : qit. cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0). FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'. END IF. -. VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0). r(0) := a(0) XOR b(0) XOR cin. Navabi and McGraw-Hill Inc. r(a'LEFT+1) := c(a'LEFT). END LOOP. b_sign := b(b'LEFT). r := add_cv (a.extra r bits : msb: overflow. c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)). b : qit_vector. END par_utilities. RETURN zero. END add_cv. END sub_cv. not_c := NOT cin. b_sign: qit. c: qit_vector (a'LEFT + 2 DOWNTO 0). EXIT. b : qit_vector. • • • • Body of the par_utilities package of par_library library add_cv adds its operands creates c and v bits Put overflow in leftmost result bit Put carry to the right of overflow © 1999. RETURN r. not_c). CHAPTER 10 17 . BEGIN a_sign := a(a'LEFT). Z. FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1). not_b.

CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001". Z. END par_parameters.ALL.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. • Declaration of par_parameters Package of par_library • Assign appropriate names to opcodes • par_parameters is used for readability CHAPTER 10 18 © 1999. -PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110". CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010". CONSTANT add : qit_vector (2 DOWNTO 0) := "010". CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111". CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000".basic_utilities. USE cmos. Navabi and McGraw-Hill Inc. CONSTANT ann : qit_vector (2 DOWNTO 0) := "001". CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100". . CONSTANT indirect : qit := '1'. CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011". CONSTANT lda : qit_vector (2 DOWNTO 0) := "000". CONSTANT sta : qit_vector (2 DOWNTO 0) := "101". CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001". CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110". CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11". CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100".

PORT (clk : IN qit. read_low_time. USE par_library. cycle_time : TIME := 4 US). write_high_time. Navabi and McGraw-Hill Inc.ALL.par_parameters. END par_central_processing_unit.basic_utilities. -ENTITY par_central_processing_unit IS GENERIC (read_high_time. USE cmos. . Z. adbus : OUT twelve ).ALL.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. • Interface description of Parwan CHAPTER 10 19 © 1999.par_utilities. interrupt : IN qit. -LIBRARY par_library.ALL. write_mem : OUT qit. databus : INOUT wired_byte BUS := "ZZZZZZZZ". write_low_time : TIME := 2 US. read_mem. USE par_library.

26. Figure 10.single-byte / double-byte END IF. Z.21. Figure 10. END behavioral. and.26. -. Remove memory from databus.18. and. increment pc.no interrupt Read first byte into byte1. address in byte2. add. add. Figure 10. top. increment pc. Figure 10. END IF. middle.jsr / bra / other double-byte instructions END IF.jmp / sta / lda.interrupt / otherwise END PROCESS.16. IF byte1 (7 DOWNTO 5) = jsr THEN Execute jsr instruction. Navabi and McGraw-Hill Inc.19.read operand for lda. Figure 10. BEGIN IF interrupt = '1' THEN Handle interrupt. Figure 10. . ELSE -. sub Read memory onto databus. ELSIF byte1 (7 DOWNTO 4) = bra THEN Execute bra instructions. Figure 10. ELSE -. Figure 10. Figure 10. • Outline of the Behavioral Description of Parwan CHAPTER 10 20 © 1999. END IF. and. -.17.BEHAVIORAL DESCRIPTION OF PARWAN ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS Declare necessary variables.ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN Execute jmp instruction.22. byte2 has address. Figure 10. ELSIF byte1 (7 DOWNTO 5) = sta THEN Execute sta instruction. and sub. -. add. -.20.26.24. ELSE -. Figure 10. Figure 10.two-byte instructions Read second byte into byte2. bottom. sub END IF. IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN Execute single-byte instructions.23.25. Figure 10. ELSE -. -.all other two-byte instructions IF byte1 (4) = indirect THEN Use byte1 and byte2 to get address. write ac. Execute lda.

z. n : qit. byte1 := byte (databus). read_mem <= '1'. part of Parwan behavioral model • Filling the outline of the behavioral description of Parwan • Declarations. WAIT FOR read_high_time. Interrupt handling. . Navabi and McGraw-Hill Inc. WAIT FOR read_low_time. Z. VARIABLE v. VARIABLE ac. c. WAIT FOR cycle_time. byte1. byte2 : byte.BEHAVIORAL DESCRIPTION OF PARWAN VARIABLE pc : twelve. Reading the first byte CHAPTER 10 21 © 1999. • Variable declarations of Parwan behavioral model pc := zero_12. read_mem <= '0'. • Interrupt handling of Parwan behavioral model adbus <= pc. pc := inc (pc). • Reading the first byte from the memory. VARIABLE temp : qit_vector (9 DOWNTO 0).

. END IF. IF c /= n THEN v := '1'. WHEN asr => ac := ac (7) & ac (7 DOWNTO 1). n := ac (7). END IF. END IF. cma. asl. END CASE. cmc. IF ac = zero_8 THEN z := '1'. Z. cla. WHEN asl => c := ac (7). WHEN cmc => c := NOT c. IF ac = zero_8 THEN z := ‘1’. • Executing single-byte instructions in the behavioral model of Parwan • Using the least significant nibble for decoding instructions • Decoding instructions. n := ac (7). WHEN OTHERS => NULL. WHEN cma => ac := NOT ac.BEHAVIORAL DESCRIPTION OF PARWAN CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8. IF ac = zero_8 THEN z := '1'. n := ac (7). Navabi and McGraw-Hill Inc. asr CHAPTER 10 22 © 1999. END IF. ac := ac (6 DOWNTO 0) & '0'.

write_mem <= '1'. WAIT FOR write_low_time. Z. read_mem <= '0'. Navabi and McGraw-Hill Inc. byte2 := byte (databus). adbus (7 DOWNTO 0) <= byte2. . WAIT FOR read_low_time.BEHAVIORAL DESCRIPTION OF PARWAN adbus <= pc. part of Parwan behavioral model databus <= wired_byte (pc (7 DOWNTO 0) ). • Reading the second byte from the memory. pc := inc (pc). write_mem <= '0'. • Execution of the jsr instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Reading the second byte. WAIT FOR read_high_time. pc (7 DOWNTO 0) := inc (byte2). Executing jsr CHAPTER 10 23 © 1999. WAIT FOR write_high_time. read_mem <= '1'. databus <= "ZZZZZZZZ".

read_mem <= '0'. byte2 := byte (databus). adbus (7 DOWNTO 0) <= byte2. read_mem <= '1'. Navabi and McGraw-Hill Inc. . END IF. WAIT FOR read_high_time. WAIT FOR read_low_time. • Execution of branch instructions in the behavioral model of Parwan adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0).BEHAVIORAL DESCRIPTION OF PARWAN IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2. Z. • Handling indirect addressing by the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Branch instruction. Handling indirect addressing CHAPTER 10 24 © 1999.

• Execution of sta instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Handling jmp and sta instructions CHAPTER 10 25 © 1999. Navabi and McGraw-Hill Inc. write_mem <= '1'.BEHAVIORAL DESCRIPTION OF PARWAN pc := byte1 (3 DOWNTO 0) & byte2. Z. . databus <= wired_byte (ac). databus <= "ZZZZZZZZ". WAIT FOR write_low_time. write_mem <= '0'. WAIT FOR write_high_time. • Execution of jmp instruction in the behavioral model of Parwan adbus <= byte1 (3 DOWNTO 0) & byte2.

read_mem <= '1'. Z. . and sub instructions in the behavioral model of Parwan CHAPTER 10 26 © 1999. c). IF ac = zero_8 THEN z := '1'. v := temp (9). END CASE. adbus (7 DOWNTO 0) <= byte2. WAIT FOR read_low_time. byte (databus). WHEN sbb => temp := sub_cv (ac. add. WHEN OTHERS => NULL. ac := temp (7 DOWNTO 0). n := ac (7). and. Navabi and McGraw-Hill Inc. ac := temp (7 DOWNTO 0). c). byte (databus). CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus). WHEN ann => ac := ac AND byte (databus). END IF. c := temp (8). c := temp (8).BEHAVIORAL DESCRIPTION OF PARWAN adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). read_mem <= '0'. WHEN add => temp := add_cv (ac. • Execution of lda. v := temp (9). WAIT FOR read_high_time.

ADBUS obus_on_dbus 8 8 4 8 AC ac_out a_side ALU b_side IR ir_out PC_PAGE pc_out PC_OFFSET CONTROLLER alu_flags 4 8 mar_page_bus mar_inp MAR_PAGE OBUS 4 mar_offset_bus alu_out SHU 4 8 MAR_OFFSET 8 mar_out SR 4 read_mem write_mem interrupt ADBUS 12 • Bussing structure of Parwan CHAPTER 10 27 © 1999.PARWAN BUSSING STRUCTURE databus_on_dbus DATABUS dbus_on_databus DBUS 8 4096 byte memory . Navabi and McGraw-Hill Inc. .. Z..

Navabi and McGraw-Hill Inc. . Z.PARWAN BUSSING STRUCTURE Component AC IR PC MAR SR ALU SHU Type Register Register Loadable Up Counter Register Register Arithmetic Unit Shifter Logic Bits 8 8 12 12 4 8 8 • • • • Machine has 7 components Behavioral description helps partitioning the circuit Circuit components will be identified Bussing specifies interconnection of these components CHAPTER 10 28 © 1999.

..PARWAN BUSSING STRUCTURE LDA Instruction: Cycle 1 Begin Fetch Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Pc_on_mar_page_bus. Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac . Z.. Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir Pc_on_mar_page_bus Get Address Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus Get Operand. Next Fetch • Steps for execution of lda CHAPTER 10 29 © 1999. Navabi and McGraw-Hill Inc.

Z. Navabi and McGraw-Hill Inc. .PARWAN BUSSING STRUCTURE Data Signals DATA SECTION Data Components and Buses CONTROL SECTION Control Signals • Data and control sections of Parwan CPU • 31 control signals from the controller to the data unit CHAPTER 10 30 © 1999.

write_mem. zero_ac load_ir increment_pc. pc_on_mar_offset_bus. alu_sub Others I/O read_mem. obus_on_dbus. alu_a. load_offset_pc. load_page_pc. dbus_on_mar_offset_bus DBUS Bus Control pc_offset_on_dbus. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN Applies To AC IR PC Category Register Control Register Control Register Control Signal Name load_ac. interrupt • Inputs and outputs of Parwan control section • Signals for flow of data and data clocking CHAPTER 10 31 © 1999. ir_on_mar_page_bus. reset_pc Loads ac Resets ac Loads ir Increments pc Functionality Loads page part of pc Loads offset part of pc Resets pc Loads page part of mar Loads offset part of mar Loads sr Complements carry flag of sr Puts page part of pc on mar page bus Puts 4 bits of ir on mar page bus Puts offset part of pc on mar offset bus Puts dbus on mar offset bus Puts offset part of pc on dbus Puts obus on dbus Puts external databus on internal dbus Puts all of mar on adbus Puts internal dbus on external databus Shifter shifts its input one place to the left Shifter shifts its input one place to the right Output of alu becomes and of its two inputs Output of alu becomes complement of its b input Output of alu becomes the same as its a input alu perfporms add operation on its two inputs Output of alu becomes the same as its b input alu perfporms subtraction of its two inputs Starts a memory read operation Starts a memory write operation Interrupts CPU MAR SR MAR_BUS Register Control Register Control Bus Control load_page_mar. databus_on_dbus ADBUS DATABUS SHU ALU Bus Control Bus Control Logic Units Logic Units mar_on_adbus dbus_on_databus arith_shift_left. alu_b. cm_carry_sr pc_on_mar_page_bus. . arith_shift_right alu_and. load_offset_mar load_sr. alu_not. alu_add. Z.

Z.DATAFLOW DESCRIPTION OF PARWAN System Clock Control Signal 1 Control Signal 2 Control signals remain asserted for a complete clock cycle Allows logic unit propagation Clock data and control at the same time Clock data while control signals are still valid • Timing of control signals • Assume falling edge trigger data and control CHAPTER 10 32 © 1999. . Navabi and McGraw-Hill Inc.

Z. Navabi and McGraw-Hill Inc. . • Operations and flags of alu • A control signal for each operation CHAPTER 10 33 © 1999. Will also show hardware.DATAFLOW DESCRIPTION OF PARWAN Id 0 1 2 3 4 5 Opcode line alu_and alu_not alu_a alu_add alu_b alu_sub Operation a AND b NOT b a b PLUS a b b MINUS a Flags zn zn zn vczn zn vczn Individual data components will be described in VHDL.

1. 3. 2. 4. . Z. 5) CO (0. 5) VO (3. 5) ZO (0. 2. 3.DATAFLOW DESCRIPTION OF PARWAN ai bi alu_and alu_not 0 1 2 3 4 5 VI CI ZI NI A B A B A B A B A B A B A B A B ALU (3. 4. 1. Navabi and McGraw-Hill Inc. 5) NO alu_a alu_add [0] [1] [2] [3] [4] [5] [6] [7] alu_sub + alu_b - • Parwan alu • Logic symbol • One bit gate level hardware CHAPTER 10 34 © 1999.

END alu_operations.DATAFLOW DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000". . -PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001". Z. CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010". CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000". CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000". • Package declaration for the alu_operations package • Simplify code and add readability CHAPTER 10 35 © 1999.basic_utilities.ALL. CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100". USE cmos. Navabi and McGraw-Hill Inc.

b_side.other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side. b_side : IN byte. alu_a. v := v_flag_in. alu_b. out_flags : OUT nibble). v := t(9). WHEN OTHERS => NULL. WHEN b_input => t (7 DOWNTO 0) := b_side. BEGIN WHEN a_add_b => t := add_cv (b_side. alu_b. c_flag_in). n : qit. WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side. n := t(7). n). c_flag_in). WHEN b_compl => t (7 DOWNTO 0) := NOT b_side. z_out : OUT byte. END behavioral. a_side. END arithmetic_logic_unit. alu_add. alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0). v := v_flag_in. z := set_if_zero (t (7 DOWNTO 0)). c. alu_not. alu_and. Navabi and McGraw-Hill Inc. WHEN a_input => t (7 DOWNTO 0) := a_side. alu_sub : IN qit. z. in_flags : IN nibble. VARIABLE v. alu_and) IS • Behavioral description of arithmetic logic unit of Parwan CHAPTER 10 36 © 1999. ALIAS c_flag_in : qit IS in_flags(2). alu_add. -. alu_a. c := c_flag_in. z_out <= t (7 DOWNTO 0). ALIAS v_flag_in : qit IS in_flags(3). CASE qit_vector (5 DOWNTO 0)’ (alu_sub. z. v := t(9). . c := c_flag_in. ALIAS z_flag_in : qit IS in_flags(1). ALIAS n_flag_in : qit IS in_flags(0). alu_a.DATAFLOW DESCRIPTION OF PARWAN ENTITY arithmetic_logic_unit IS PORT (a_side. c := t(8). c. alu_b. alu_add. v := v_flag_in. Z. v := v_flag_in. c := c_flag_in. -ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side. alu_and. c := t(8). END PROCESS coding. END CASE. out_flags <= (v. c := c_flag_in. alu_not. a_side. alu_not.

R) NO i-1 • Parwan shu • Logic symbol • One bit hardware CHAPTER 10 37 © 1999. R) ZO (L. Navabi and McGraw-Hill Inc. Z. .DATAFLOW DESCRIPTION OF PARWAN L R Input Output SHU L R VI CI ZI NI [0] [1] [2] [3] [4] [5] [6] [7] i+1 i i ( L) VO (L) CO (L.

n : qit. z := set_if_zero (t). c. c. . BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0). n) := in_flags. n). ALIAS n_flag_in : qit IS in_flags(0). n := t (7). out_flags : OUT nibble). z. END IF. END PROCESS coding. z. c. END shifter_unit. v := alu_side (6) XOR alu_side (7). • Behavioral Description of the Shifter Unit of Parwan CHAPTER 10 38 © 1999. in_flags : IN nibble. c := c_flag_in. n := t (7). VARIABLE v. -ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side. ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'. (v. obus_side <= t. obus_side : OUT byte.DATAFLOW DESCRIPTION OF PARWAN ENTITY shifter_unit IS PORT (alu_side : IN byte. z. ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1). c := alu_side (7). arith_shift_left. arith_shift_left. END behavioral. Z. ALIAS v_flag_in : qit IS in_flags(3). Navabi and McGraw-Hill Inc. arith_shift_right : IN qit. arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0). z := set_if_zero (t). ALIAS z_flag_in : qit IS in_flags(1). ALIAS c_flag_in : qit IS in_flags(2). out_flags <= (v. v := v_flag_in.

Z. . 3D 1.DATAFLOW DESCRIPTION OF PARWAN load cm_carry G1 G2 C3 SR N Z C V 1. 3D 1. 3D [0] [1] [2] [3] N Z C V input c 2D Q output c load G1 cm_carry 1C2 • The status register • Logic symbol • One bit hardware CHAPTER 10 39 © 1999. 3D 2. Navabi and McGraw-Hill Inc. 3D 1.

cm_carry. Navabi and McGraw-Hill Inc. ck : IN qit ). END IF. out_status : OUT nibble. Z. END PROCESS. • Behavioral description of the status register of Parwan CHAPTER 10 40 © 1999. BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags.DATAFLOW DESCRIPTION OF PARWAN ENTITY status_register_unit IS PORT (in_flags : IN nibble. . load. ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c. out_status <= internal_state. END IF. -ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000". END behavioral. END status_register_unit. ALIAS internal_c : qit IS internal_state (2).

4D 3. 4D 3. 4D 2. 4D 2. 4D 3.DATAFLOW DESCRIPTION OF PARWAN load zero G1 M2 M3 1C4 AC zero '0' I0 '0' I1 '0' I2 '0' I3 '0' I4 '0' I5 '0' I6 '0' I7 2. Navabi and McGraw-Hill Inc. 4D 3. 4D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 2D Q Oi I o2 o3 o4 o5 o6 o7 i G1 1C2 • Parwan accumulator • Logic symbol • One bit hardware CHAPTER 10 41 © 1999. Z. 4D 2. 4D 2. 4D 3. 4D 3. 4D 2. 4D 2. 4D 2. 4D 3. 4D 3. .

zero. Navabi and McGraw-Hill Inc. END accumulator_unit. load. END dataflow.DATAFLOW DESCRIPTION OF PARWAN ENTITY accumulator_unit IS PORT (i8 : IN byte. . Z. END BLOCK clocking. • Dataflow description of Parwan accumulator CHAPTER 10 42 © 1999. ck : IN qit). -ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8. o8 : OUT byte. END BLOCK enable.

DATAFLOW DESCRIPTION OF PARWAN IR LOAD CI 1C2 I I0 I1 I2 I3 I4 I5 I6 I7 2D 2D 2D 2D 2D 2D 2D 2D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 o2 o3 o4 i 2D Q Oi load o5 o6 o7 G1 1C2 • The Parwan instruction register • Logic symbol • One bit hardware CHAPTER 10 43 © 1999. Z. Navabi and McGraw-Hill Inc. .

. load. ck : IN qit). -ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8. END BLOCK enable. END dataflow. Z. • Dataflow description of the instruction register of Parwan CHAPTER 10 44 © 1999. Navabi and McGraw-Hill Inc. END instruction_register_unit. o8 : OUT byte.DATAFLOW DESCRIPTION OF PARWAN ENTITY instruction_register_unit IS PORT (i8 : IN byte. END BLOCK clocking.

3D 2. 3D 1. 3D 2. 3D 1. 3D 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 O i-1 reset o4 o5 o6 o7 o8 o9 o10 o11 2R Q Oi G1 1T C2 load_pc_offset clock • Parwan program counter • Logic symbol • One bit hardware CHAPTER 10 45 © 1999. Navabi and McGraw-Hill Inc. 3D 2. Z. . 3D 2. 3D 1. 3D 2.DATAFLOW DESCRIPTION OF PARWAN reset load_page load_offset increment 3R G1 G2 G4 C3/4+ PC I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 2. 3D 1.

ck : IN qit). o12 <= internal_state. Navabi and McGraw-Hill Inc. END behavioral. . END IF. END PROCESS. • Behavioral description of the program counter of Parwan CHAPTER 10 46 © 1999. BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12. load_page. -ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. o12 : OUT twelve. END IF. reset. load_offset. END IF. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). Z. END program_counter_unit.DATAFLOW DESCRIPTION OF PARWAN ENTITY program_counter_unit IS PORT (i12 : IN twelve. ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). increment. ELSIF increment = '1' THEN internal_state := inc (internal_state). END IF.

3D 2. 3D 2. 3D 1. 3D 2. .DATAFLOW DESCRIPTION OF PARWAN MAR load_page load_offset G1 G2 C3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 1. 3D 2. 3D 1. 3D 2. 3D 2. Navabi and McGraw-Hill Inc. 3D 2. Z. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 I i 2D Q Oi load G1 1C2 • Logic symbol for the memory address register of Parwan CHAPTER 10 47 © 1999. 3D 1.

Z. o12 <= internal_state. -ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8).DATAFLOW DESCRIPTION OF PARWAN ENTITY memory_address_register_unit IS PORT (i12 : IN twelve. Navabi and McGraw-Hill Inc. END IF. END IF. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). END memory_address_register_unit. • Behavioral description of the memory address register of Parwan CHAPTER 10 48 © 1999. END IF. . load_page. ck : IN qit). o12 : OUT twelve. END behavioral. END PROCESS. load_offset.

load_page_pc. • Entity Declaration of the Data Section of Parwan • Wires all components • Specifies bussing CHAPTER 10 49 © 1999. status : OUT nibble ). alu_add. load_ir. -. load_offset_mar. alu_not. zero_ac. alu_b. clk : IN qit. increment_pc. -.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_data_path IS PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ". alu_sub : IN qit. load_offset_pc.bus connections: pc_on_mar_page_bus. adbus : OUT twelve. Z. load_sr. -. END par_data_path. .logic unit function control inputs: arith_shift_left. pc_on_mar_offset_bus.outputs to the controller: ir_lines : OUT byte. databus_on_dbus. dbus_on_mar_offset_bus. Navabi and McGraw-Hill Inc. -. arith_shift_right. cm_carry_sr. mar_on_adbus. dbus_on_databus. reset_pc. obus_on_dbus. ir_on_mar_page_bus. alu_a. load_page_mar.register controls: load_ac. pc_offset_on_dbus. alu_and.

reset. b_side : IN byte. arith_shift_left. FOR r2: ir USE ENTITY WORK. ck: IN qit). zero. load_page. obus : byte. z_out : OUT byte. END COMPONENT. o8: OUT byte. alu_out. ck: IN qit). ck : IN qit).status_register_unit (behavioral). -COMPONENT ir PORT (i8: IN byte.shifter_unit (behavioral). SIGNAL dbus : wired_byte BUS. -COMPONENT pc PORT (i12 : IN twelve. FOR l2 : shu USE ENTITY WORK. SIGNAL pc_out. SIGNAL mar_inp : twelve. sr_out : nibble. out_flags : OUT nibble). alu_b.memory_address_register_unit (behavioral). -COMPONENT alu in_flags : IN nibble. load_offset. FOR r5 : sr USE ENTITY WORK. load. ck : IN qit). SIGNAL alu_a_inp : byte. alu_not. END COMPONENT. load. Navabi and McGraw-Hill Inc. alu_and. • Declarative Part of the structural Architecture of par_data_path • Components are declared • Busses and signals are declared CHAPTER 10 50 © 1999. Z. increment. END COMPONENT. SIGNAL alu_flags. ck : IN qit ). shu_flags. o12 : OUT twelve. -COMPONENT sr PORT (in_flags : IN nibble. END COMPONENT. alu_a.arithmetic_logic_unit (behavioral). load_offset.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE structural OF par_data_path IS -COMPONENT ac PORT (i8: IN byte. . ir_out. SIGNAL mar_bus : wired_twelve BUS. alu_add. -SIGNAL ac_out. out_status : OUT nibble.instruction_register_unit (dataflow). arith_shift_right : IN qit. -COMPONENT mar PORT (i12 : IN twelve. mar_out : twelve. FOR r3: pc USE ENTITY WORK. cm_carry.program_counter_unit (behavioral). END COMPONENT.accumulator_unit (dataflow). load. obus_side : OUT byte. FOR r4: mar USE ENTITY WORK. FOR l1 : alu USE ENTITY WORK. END COMPONENT. in_flags : IN nibble. -COMPONENT shu PORT (alu_side : IN byte. FOR r1: ac USE ENTITY WORK. load_page. PORT (a_side. out_flags : OUT nibble). o8: OUT byte. alu_sub : IN qit. o12 : OUT twelve. END COMPONENT.

zero_ac.bus connections --dbus1: alu_a_inp <= qit_vector (dbus). END BLOCK dbus2. dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus. ir_out.register connections --r1: ac PORT MAP (obus. Navabi and McGraw-Hill Inc. Z. load_ac. dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus. -databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus. clk). clk). END BLOCK obus1. ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)). ir1: ir_lines <= ir_out. -mar_bus1: mar_inp <= qit_vector (mar_bus). load_ir. . END BLOCK dbus3. ac_out. • Statement part of the par_data_path structural Architecture • Uses block statements for bussing • Register interconnections follow registers instantiation CHAPTER 10 51 © 1999. -r2: ir PORT MAP (obus. --. END BLOCK ir2. END BLOCK databus1. -obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus).DATAFLOW DESCRIPTION OF PARWAN BEGIN -.

clk). pc_out. ac_out. alu_flags). • Statement part of the par_data_path structural Architecture • Ends with logic unit instantiations CHAPTER 10 52 © 1999. END BLOCK pc2. END BLOCK pc1. pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). arith_shift_left. mar_out. Navabi and McGraw-Hill Inc.connection of logical and register structures --l1: alu PORT MAP (alu_a_inp. Z. increment_pc. alu_flags. END BLOCK mar1. sr1: status <= sr_out. obus. sr_out. sr_out. load_offset_mar. alu_add. clk). alu_and. alu_sub. alu_not. load_page_mar. -r4: mar PORT MAP (mar_inp. alu_a. END structural. clk). pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). reset_pc. alu_out. arith_shift_right. shu_flags). load_offset_pc. alu_b. mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out. l2: shu PORT MAP (alu_out. -r5: sr PORT MAP (shu_flags. cm_carry_sr. --. .DATAFLOW DESCRIPTION OF PARWAN r3: pc PORT MAP (mar_out. pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)). load_sr. END BLOCK pc3. load_page_pc.

style. • Typical hardware surrounding a control flip-flop • The logic block is designated by a bubble • Controller is built using one-hot encoding CHAPTER 10 53 © 1999. Navabi and McGraw-Hill Inc. hardware and coding will be described.DATAFLOW DESCRIPTION OF PARWAN To other control FF inputs External Signals logic block control FF i Q All Signals Activating State i 1D i C1 signals issuing control signals control signals to data section en system clock For the Parwan controller. Z. .

. Z.DATAFLOW DESCRIPTION OF PARWAN csx a b c logic block i d e logic block j csy Q 1D i C1 en 1D j C1 Q en 1D k C1 Q clock • Example for the structure of Parwan control section • Showing 3 states in a one-hot implementation CHAPTER 10 54 © 1999. Navabi and McGraw-Hill Inc.

memory control and other external signals: read_mem. load_offset_pc. cm_carry_sr. -. Z. -. BEGIN • • • • Entity declaration of Parwan control section Showing signals for the data unit Declaring states of the machine is shown Declarative part of the par_control_unit dataflow architecture CHAPTER 10 55 © 1999. load_offset_mar. arith_shift_right. load_sr. increment_pc. ir_on_mar_page_bus. -. PORT (clk : IN qit. load_page_mar. .logic unit function control outputs: arith_shift_left. load_page_pc. END par_control_unit. obus_on_dbus. alu_b. alu_a. Navabi and McGraw-Hill Inc.register control signals: load_ac. databus_on_dbus. write_delay : TIME := 3 NS). status : IN nibble. dbus_on_mar_offset_bus. write_mem : OUT ored_qit BUS. -. mar_on_adbus. reset_pc. alu_and. pc_on_mar_offset_bus. alu_sub : OUT ored_qit BUS.inputs from the data section: ir_lines : IN byte.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_control_unit IS GENERIC (read_delay. ------------------------------------------------------------------------------------------------ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. alu_add. load_ir. zero_ac. pc_offset_on_dbus. interrupt : IN qit ).bus connection control signals: pc_on_mar_page_bus. alu_not. -. dbus_on_databus.

. Navabi and McGraw-Hill Inc. Z. par_control_unit outputs CHAPTER 10 56 © 1999.DATAFLOW DESCRIPTION OF PARWAN par_control_unit control_signal_1 assignments to control_signal_1 control_signal_2 control_signal_3 oring_qit type signals • Assigning signals with implied oring.

Navabi and McGraw-Hill Inc. END BLOCK ck. s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'.goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'. load_offset_mar <= GUARDED '1'. load_page_mar <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s1: BLOCK (s(1) = '1') BEGIN -. END BLOCK s1. -. -.start of fetch -. pc_on_mar_offset_bus <= GUARDED '1'.reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'. .pc to mar pc_on_mar_page_bus <= GUARDED '1'. pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 2 reset_pc 1D 1 interrupt C1 • State 1: starting a fetch • VHDL code • Gate level hardware CHAPTER 10 57 © 1999. Z.

goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'. Navabi and McGraw-Hill Inc. databus_on_dbus <= GUARDED '1'. END BLOCK ck.increment pc increment_pc <= GUARDED '1'. alu_a <= GUARDED ‘1’. read_mem <= GUARDED '1' AFTER read_delay.read memory into ir mar_on_adbus <= GUARDED '1'.fetching continues -.DATAFLOW DESCRIPTION OF PARWAN s2: BLOCK (s(2) = '1') BEGIN -. Z. -. -. END BLOCK s2. . mar_on_adbus read_mem databus_on_dbus alu_a load_ir increment_pc 3 1D 2 C1 • State 2: completing a fetch • VHDL code • Gate level hardware CHAPTER 10 58 © 1999. load_ir <= GUARDED '1'.

load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. -. Z. load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. END BLOCK ck.pc to mar. END BLOCK s3. cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'. Navabi and McGraw-Hill Inc. • State 3: preparing for address fetch • Execution of single byte instructions • VHDL code CHAPTER 10 59 © 1999.perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not. pc_on_mar_offset_bus <= GUARDED '1'. for next read pc_on_mar_page_bus <= GUARDED '1'. arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'. arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'. . -. END BLOCK sb. load_offset_mar <= GUARDED '1'. END BLOCK ck. load_page_mar <= GUARDED '1'.goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'. zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'. alu_b) <= GUARDED qit_vector’(“10”) WHEN ir_lines (1) = ‘1’ ELSE qit_vector’( “01”).DATAFLOW DESCRIPTION OF PARWAN s3: BLOCK (s(3) = '1') BEGIN -.

.DATAFLOW DESCRIPTION OF PARWAN pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 4 1D 3 IR7 IR6 IR5 IR4 C1 2 IR3 2 1 0 IR3 2 1 0 IR1 arith_shift_left arith_shift_right alu_not alu_b IR1 IR3 IR1 cm_carry_sr IR2 IR3 1 IR3 0 zero_ac load_ac load_sr • State 3: preparing for address fetch • Execution of single byte instructions • Gate level hardware CHAPTER 10 60 © 1999. Z. Navabi and McGraw-Hill Inc.

-. -. • • • • State 4: completing address of full address instructions Branching for indirect. END BLOCK pg. 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'. -. direct. databus_on_dbus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s4: BLOCK (s(4) = '1') BEGIN -. -. -. 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'. Navabi and McGraw-Hill Inc. and offset from next memory makeup 12-bit address -.jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'. load_page_mar <= GUARDED '1'.direct END BLOCK ck.read memory into mar offset mar_on_adbus <= GUARDED '1'.indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'. -. -. -.goto 5 for indirect.page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay. jsr. Z. END BLOCK sp. dbus_on_mar_offset_bus <= GUARDED '1'.increment pc increment_pc <= GUARDED '1'. load_offset_mar <= GUARDED '1'.keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -. END BLOCK s4.completed operand (dir/indir) address -.bra END BLOCK ck.page from ir.goto 7 for jsr. . and branch VHDL code Gate level hardware CHAPTER 10 61 © 1999.

and branch • Gate level hardware CHAPTER 10 62 © 1999. Z. jsr. Navabi and McGraw-Hill Inc. .DATAFLOW DESCRIPTION OF PARWAN mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offet_bus load_offset_mar increment_pc ir_on_mar_page_bus load_page_mar IR7 1D 4 6 5 C1 IR4 6 IR5 9 7 • State 4: completing address of full address instructions • Branching for indirect. direct.

goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s5: BLOCK (s(5) = '1') BEGIN -. Z.read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'. databus_on_dbus <= GUARDED '1'. END BLOCK ck. dbus_on_mar_offset_bus <= GUARDED '1'. load_offset_mar <= GUARDED '1'. -. Navabi and McGraw-Hill Inc. mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offset_bus load_offset_mar 6 1D 5 c1 • State 5: taking care of indirect addressing • Actual address will now go in MAR CHAPTER 10 63 © 1999.indirect addressing -. read_mem <= GUARDED '1' AFTER read_delay. . END BLOCK s5.

perform lda.. END BLOCK rd. and [lda. add. sta. Reading and executing jmp... sub] CHAPTER 10 64 © 1999. and. and. jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • • • • • State 6: reading the actual operand. add. add. Navabi and McGraw-Hill Inc.. END BLOCK jm.. -. and sub instructions Outline of the VHDL code Outline of the hardware Three separate blocks for [jmp].DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN . END BLOCK st. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN . sub END BLOCK s6. Z. . lda.. [sta]. and. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN .

add. Z. load_offset_pc <= GUARDED '1'. . • • • • State 6: reading the actual operand. . -. and [lda.. END BLOCK s6. sub] CHAPTER 10 65 © 1999.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'. END BLOCK ck. Reading and executing jmp instruction VHDL code Two more blocks for [sta].. and. Navabi and McGraw-Hill Inc. END BLOCK jm.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'.

Reading and executing sta instruction Partial VHDL code Need one more block for handling [lda. .. write to memory mar_on_adbus <= GUARDED '1'. Z.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN . alu_b <= GUARDED ‘1’. ac on databus. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. END BLOCK s6.. • • • • State 6: reading the actual operand. Navabi and McGraw-Hill Inc. sub] CHAPTER 10 66 © 1999. dbus_on_databus <= GUARDED '1'.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.mar on adbus... add. obus_on_dbus <= GUARDED '1'. END BLOCK st. and. END BLOCK ck. write_mem <= GUARDED '1' AFTER write_delay. . -.

sub] CHAPTER 10 67 © 1999. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’. . alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’.. sta. load_sr <= GUARDED '1'. and sub instructions Completing the VHDL code This last block handles [lda. sub END BLOCK s6. END BLOCK rd. read_mem <= GUARDED '1' AFTER read_delay. perform operation mar_on_adbus <= GUARDED '1'.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. and. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. Navabi and McGraw-Hill Inc. load_ac <= GUARDED '1'. -. databus_on_dbus <= GUARDED '1'. Reading and executing jmp. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. lda.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN .perform lda. Z. add. END BLOCK ck. add. and.mar on adbus. and. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. read memory for operand. add.. • • • • State 6: reading the actual operand. -.

load_sr <= GUARDED '1'. read memory for operand. -. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. databus_on_dbus <= GUARDED '1'.mar on adbus.perform lda. and sub instructions • Complete VHDL code CHAPTER 10 68 © 1999. • State 6: reading the actual operand. Navabi and McGraw-Hill Inc. and executing jmp.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'. perform operation mar_on_adbus <= GUARDED '1'. END BLOCK ck. alu_b <= GUARDED ‘1’. -. read_mem <= GUARDED '1' AFTER read_delay. and. Z. . lda. obus_on_dbus <= GUARDED '1'. -.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. END BLOCK rd. dbus_on_databus <= GUARDED '1'. sub END BLOCK s6. write_mem <= GUARDED '1' AFTER write_delay. add. ac on databus. load_offset_pc <= GUARDED '1'. load_ac <= GUARDED '1'. -. write to memory mar_on_adbus <= GUARDED '1'.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. END BLOCK ck. add. END BLOCK ck.mar on adbus. END BLOCK st. sta. and. END BLOCK jm. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’.

. Navabi and McGraw-Hill Inc. sta. and executing jmp.DATAFLOW DESCRIPTION OF PARWAN jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • State 6: reading the actual operand. add. lda. and. Z. and sub instructions • Complete gate level hardware CHAPTER 10 69 © 1999.

dbus_on_databus <= GUARDED '1'. write_mem <= GUARDED '1' AFTER write_delay. Z. -.jsr -. . END BLOCK ck. -.write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'. mar_on_adbus pc_offset_on_dbus dbus_on_databus write_mem load_offset_pc 8 1D 7 c1 • • • • State 7: writing return address of subroutine Making pc point to top of subroutine Complete VHDL code Hardware CHAPTER 10 70 © 1999. pc_offset_on_dbus <= GUARDED '1'.goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'.address of subroutine to pc load_offset_pc <= GUARDED '1'. END BLOCK s7. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN s7: BLOCK (s(7) = '1') BEGIN -.

DATAFLOW DESCRIPTION OF PARWAN s8: BLOCK (s(8) = '1') BEGIN -. .increment pc increment_pc <= GUARDED '1'. END BLOCK s8. Z. -. increment_pc 9 1D 8 c1 • State 8: incrementing pc to skip location reserved for return address • VHDL code • Hardware CHAPTER 10 71 © 1999. Navabi and McGraw-Hill Inc. END BLOCK ck.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.

Z. . Navabi and McGraw-Hill Inc. END BLOCK ck. END BLOCK s9.DATAFLOW DESCRIPTION OF PARWAN s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'. ir3 status3 ir2 status2 load_offset_pc ir1 status1 ir0 status0 1 1D 9 C1 • State 9: conditional loading of pc for branch instructions • VHDL code • Gate level hardware CHAPTER 10 72 © 1999. -.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.

DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. -. END BLOCK s8. S2: BLOCK (s(2) = '1') BEGIN . Navabi and McGraw-Hill Inc. END BLOCK s2. S9: BLOCK (s(9) = '1') BEGIN .. END BLOCK ck. END BLOCK ck. END BLOCK ck. Z. END BLOCK s1. END BLOCK ck. BEGIN s(next) <= GUARDED '1'. ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000".. CHAPTER 10 73 © 1999.. BEGIN s(next) <= GUARDED '1'. • • • • Ending the dataflow description of the par_control_unit Controller outline Need to clock all states A zero driver is placed on all state. .. END BLOCK s9. BEGIN s(next) <= GUARDED '1'.. BEGIN s(next) <= GUARDED '1'.. END BLOCK ck.State blocks end here END dataflow. BEGIN S1: BLOCK (s(1) = '1') BEGIN .... OOOO S8: BLOCK (s(8) = '1') BEGIN .

Navabi and McGraw-Hill Inc. Z.DATAFLOW DESCRIPTION OF PARWAN Q 1D 1 C1 en 1D 2 C1 Q 3 C1 Q en Q 1D 4 C1 en 1D 5 C1 Q 1D 6 C1 Q en Q 1D 7 C1 1D 8 C1 Q 1D 9 C1 Q • Complete control unit • Wire individual control flip-flops • Oring is done at inputs of states when branching is done to them CHAPTER 10 74 © 1999. .

DATAFLOW DESCRIPTION OF PARWAN ENTITY par_central_processing_unit IS PORT (clk : IN qit. Z. interrupt : IN qit. write_mem : OUT qit. . read_mem. adbus : OUT twelve ). Navabi and McGraw-Hill Inc. • Entity declaration of the Parwan CPU for its dataflow description • Complete CPU wires data and control CHAPTER 10 75 © 1999. databus : INOUT wired_byte BUS := "ZZZZZZZZ". END par_central_processing_unit.

DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte. BEGIN data: par_data_path PORT MAP (databus. status ). . clk : IN qit. FOR ctrl: par_control_unit USE ENTITY WORK. FOR data: par_data_path USE ENTITY WORK. adbus : OUT twelve. ir_lines. load_ac. ir_lines : OUT byte. . load_ac. . interrupt ). status : OUT nibble ). load_ac. . -COMPONENT par_control_unit PORT (clk : IN qit. .par_data_path (structural). Navabi and McGraw-Hill Inc. . SIGNAL ir_lines : byte. interrupt : IN qit ). . END dataflow. • Data and control declarations • Data and control wiring © 1999.par_control_unit (dataflow). SIGNAL status : nibble. write_mem. . . read_mem. zero_ac. Z. -SIGNAL load_ac. ir_lines. write_mem : OUT qit. adbus. CHAPTER 10 76 . status. . END COMPONENT. ctrl: par_control_unit PORT MAP (clk. . clk. • The general outline of dataflow architectture of Parwan CPU. END COMPONENT. zero_ac. ir_lines : IN byte. . . zero_ac. load_ac. read_mem. . zero_ac. zero_ac. status : IN nibble. .

qit2int (address. nop. 26. "00100100". write. address).A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit. • A simple testbench • Include CPU instantiation. "10100000". BEGIN int : interrupt <= '1'. "00011101". write. jmp i 36 OTHERS => (OTHERS => ‘0’)). --lda i 29. WAIT UNTIL write = '0'. "00011000".. "11101001". read. "00011011". jsr 36 "11101000". -. "01011010". read_mem. "00010010". --cac. END input_output. "01011100". sub 28 "00010000". "00100100". "00000000". 29. "00000000". "11100000". "00100000". cpu : parwan PORT MAP (clock. IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". "11000000". cma. '0' AFTER 4500 NS. "00000000". "00010010". SIGNAL clock. interrupt. 25. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". ELSE data <= wired_byte ( memory (ia) ). "01100000". "10000000". "01000000". SIGNAL address : twelve. "00011100". a short memory. "00011010". --(28. --and 26. END IF. databus : INOUT wired_byte BUS. END COMPONENT. BEGIN WAIT ON read. "10010000". adbus : OUT twelve ). Navabi and McGraw-Hill Inc. asr. interrupt. 30. read. "00000000". data. jmp 32 "00000000". write_mem : OUT qit. --jmp 18 "00000000". add 27 "11100010". WAIT UNTIL read = '0'. "00011001". data <= "ZZZZZZZZ". Z. END PROCESS mem. • A simple test bench for Parwan behavioral and dataflow descriptions. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "00000000". interrupt : IN qit. TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. VARIABLE ia : INTEGER. . --(24. END IF. and read/write handshaking CHAPTER 10 77 © 1999. "11100010". "00000000". write : qit. --asl. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). --lda 24. "00011111". "01110000". "00000000". END IF. 31) "10000000". 27) "00001100". ia). sta 25 "00100000". SIGNAL data : wired_byte := "ZZZZZZZZ".

read. --jmp 18 "00000000". END input_output. "00011010". jmp i 36 OTHERS => (OTHERS => ‘0’)). "00011011". 30. --cac. address). "00011101". interrupt. • Initializing memory for Parwan instructions CHAPTER 10 78 © 1999. VARIABLE ia : INTEGER. data. --asl. cma. "00011100". SIGNAL address : twelve.. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "00010010". SIGNAL data : wired_byte := "ZZZZZZZZ". 27) "00001100". "00000000". 29. "01011100". write : qit. "00011001". read. "00000000". sub 28 "00010000". "00011000". mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". "10100000". "11100000".A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. sta 25 "00100000". cpu : parwan PORT MAP (clock. "00100100". . write. "01011010". add 27 "11100010". "11101001". '0' AFTER 4500 NS. BEGIN int : interrupt <= '1'. "00100000". "00000000". asr. "01110000".. "00011111". jsr 36 "11101000". "00000000". -. BEGIN . 31) "10000000". "11100010". "01000000".. Z.. --lda 24. "00000000". jmp 32 "00000000". "00100100". nop. --(28. "00000000". "00000000". "11000000". "10010000". "10000000". "01100000". 26.. --and 26. interrupt. --lda i 29. "00010010". --(24. 25. Navabi and McGraw-Hill Inc. SIGNAL clock.

. SIGNAL data : wired_byte := "ZZZZZZZZ". Z. write : qit. ELSE data <= wired_byte ( memory (ia) ). write. cpu : parwan PORT MAP (clock. WAIT UNTIL write = '0'. read. BEGIN int : interrupt <= '1'. '0' AFTER 4500 NS. END input_output. qit2int (address. Navabi and McGraw-Hill Inc. . BEGIN WAIT ON read. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. END IF. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). END IF. END IF.. interrupt.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . WAIT UNTIL read = '0'. IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". SIGNAL address : twelve. ia). data <= "ZZZZZZZZ". read. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := . address). write. data. • • • • Produce test waveforms on interrupt and clock signals Testing is done by modeling memory read and write operations A single process assigns values from memory to databus Same process handles memory write CHAPTER 10 79 © 1999. SIGNAL clock. VARIABLE ia : INTEGER... TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. END PROCESS mem. interrupt.

END FOR. (a) CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow. binding will be done by configuration declaration • Hold data normally at z (High Impedance) CHAPTER 10 80 © 1999. . END FOR. END behavior. END FOR. (b) • Parwan tester applies data to Parwan buses • Component is declared.A TEST BENCH FOR THE PARWAN CPU CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral.par_central_processing_unit(behavioral). END FOR. END dataflow. Navabi and McGraw-Hill Inc.par_central_processing_unit(dataflow). Z.

• Memory and bus signaling for fetch state of controller • Signals provide for slower memory handshaking • Buss access signals are included CHAPTER 10 81 © 1999. IF ready = '1' THEN databus_on_dbus <= '1'. ELSE next_state <= instr_fetch.read memory into ir read_mem <= '1'. END IF.. Navabi and McGraw-Hill Inc. IF grant = '1' THEN mar_on_adbus <= '1'. Z. ..A MORE REALISTIC PARWAN WHEN instr_fetch => ---------------------------------------2 -. WHEN do_one_bytes => --------------------------------------3 . load_ir <= '1'. increment_pc <= '1'. ELSE next_state <= instr_fetch. alu_a <= ‘1’. next_state <= do_one_bytes. END IF.

flip-flop and gate interconnections should replace the component descriptions in the Parwan dataflow model. We used one-to-one hardware correspondence so that no intelligent tools are required for the generation of hardware. The methodology presented here can be applied to designs of much larger magnitude. • End of Chapter 10 CHAPTER 10 82 © 1999. Z. Navabi and McGraw-Hill Inc.SUMMARY This chapter showed how VHDL could be used to describe a system at the behavioral level before the system is even designed. . and at the dataflow level after major design decisions have been made. A design carried to the stage where a dataflow model can be generated is only a few simple steps away from complete hardware realization. The behavioral description aids designers as they verify their understanding of the problem. while the dataflow description can be used to verify the bussing and register structure of the design. The use of VHDL as a top-down partitioning and verification tool has helped us form such a methodology for manual design. We consider the design presented here a manual design. For completing the design of Parwan.

6 CPU CACHE 11.1 SYSTEM OVERVIEW 11.2 Wait Operation 11.6.5. Navabi and McGraw-Hill Inc.2 Cache Interface 11.CHAPTER 11 INTERFACE DESIGN AND MODELING 11. Z. .5.2 Interface Through Arbiter 11.4.1 Cache Structure 11.4 SHARING SYSTEM BUSES 11.4.3 Cache Structure Modeling 11.3 Arbiter Model 11.8 SUMMARY CHAPTER 11 1 © 1999.5.6.5.4 DMA Controller 11.5 DMA DEVICE 11.4.6.7 COMPLETE SYSTEM 11.3 Interface to CPU 11.3 MEMORY SIGNALS 11.4 Controller Modeling 11.1 Serial Connection 11.2 CPU TIMING 11.1 Arbitration Operation 11.6.

Z. CHAPTER 11 2 © 1999. Navabi and McGraw-Hill Inc.SYSTEM OVERVIEW Arbiter Memory 4096*8 DMA Device Serial To Parallel serial_in DMA Controller cache memory & controller Address Decoder CPU • Bussing arrangement and system components. .

SYSTEM OVERVIEW 8 dat abu s 12 ad bu s rea gra rea w dy nt d_ rite me _m m em 8-bit CPU (Parwan) halted interrupt • CPU interface CHAPTER 11 3 © 1999. . Navabi and McGraw-Hill Inc. Z.

.MEMORY SIGNALS clock read_mem grant ready adbus valid databus valid (a) • CPU read and write requests CHAPTER 11 4 © 1999. Navabi and McGraw-Hill Inc. Z.

Z. Navabi and McGraw-Hill Inc. .MEMORY SIGNALS clock write_mem grant ready adbus valid databus valid (b) • CPU read and write requests CHAPTER 11 5 © 1999.

. Navabi and McGraw-Hill Inc. Z.MEMORY SIGNALS cs rwbar Memory 4096*8 dat abu s • Memory interface adb us CHAPTER 11 6 © 1999.

.MEMORY SIGNALS Memory Wait cs rwbar adbus databus valid • Memory read operation CHAPTER 11 7 © 1999. Z. Navabi and McGraw-Hill Inc.

.SHARING SYSTEM BUSES memsel rwbar ready gra wr nt ite rea _req d_ ue req st ue st clock Bus Arbiter and Wait Handler skip_wait port 1 port 2 port 3 port 4 • Controlling bus access CHAPTER 11 8 © 1999. Navabi and McGraw-Hill Inc. Z.

Z. . Navabi and McGraw-Hill Inc.SHARING SYSTEM BUSES clock read_request i grant i memsel rwbar ready wait for bus access wait for device wait for wait state to complete • Bus grant for read operation CHAPTER 11 9 © 1999.

grant (i) <= '1'.Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. END LOOP. ready <= '0'. PORT (read_request. skip_wait : IN qit. END IF. WAIT FOR clock_period. write_request : IN nibble. ELSE grant (i) <= '0'. END behavioral. rwbar. memsel <= '0'. memsel. ready : OUT qit). EXIT. clock_period : TIME := 1 US). END arbitrator. IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'. FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000". clock. END PROCESS wait_cycle. END IF. END IF. . • Arbiter VHDL description CHAPTER 11 10 © 1999. rwbar <= read_request (i). END LOOP wait. grant : BUFFER nibble. Navabi and McGraw-Hill Inc. ready <= '1'. Z. memsel <= '1'. WAIT ON clock.SHARING SYSTEM BUSES ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1). -ARCHITECTURE behavioral OF arbitrator IS BEGIN -.

Z.DMA DEVICE Serial To Parallel serial pa ral lel _o ut ov err u fra n m_ err or 11 8 • Interface of serial-to-parallel converter CHAPTER 11 da tar ea rec dy eiv ed © 1999. . Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z.DMA DEVICE 8 de v_ da ta er err de de ro or v_ v_ r2 1 rd rc y v read_mem write_mem databus grant DMA Controller addressbus ready status_write clk sel ect _re g status_read 4 • Interface of the DMA controller CHAPTER 11 12 © 1999. .

Navabi and McGraw-Hill Inc.DMA DEVICE Address 1111:1111_1100 1111:1111_1101 1111:1111_1110 1111:1111_1111 DMA Registers Least 8 bits of starting address Most 4 bits of start Number of bytes to transfer done ie er2 er1 ie wr rd go • DMA Registers CHAPTER 11 13 © 1999. Z. .

Navabi and McGraw-Hill Inc. . Z.DMA DEVICE 4 adbus Address Decoder active • Decoding for selecting DMA registers CHAPTER 11 14 © 1999.

DMA DEVICE ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"). selects <= "0000". END behavioral. END quad_adrdcd. selects : OUT nibble). END PROCESS. WHEN "01" => selects <= "0010". WHEN "11" => selects <= "1000". . -ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'. • VHDL description of DMA register address decoder CHAPTER 11 15 © 1999. ELSE active <= '0'. Z. END CASE. PORT (adbus : IN twelve. Navabi and McGraw-Hill Inc. END IF. WHEN OTHERS => selects <= "0000". CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001". active : OUT qit. WHEN "10" => selects <= "0100".

Z. Navabi and McGraw-Hill Inc. pa ral lel _o ut ov err u fra n m_ e da rror tar rec ead eiv y ed DMA 4 selects Decoder .DMA DEVICE S2P serial 8 de er err dev dev v_ ro r2 or1 _rdy _rcv da ta read_mem 8 write_mem databus grant ready 12 addressbus status_read status_write sel ect _re g adbus status_sel active • DMA device CHAPTER 11 16 © 1999.

status_wr : IN qit. END dma_controller. status_rd. grant : IN qit.DMA DEVICE ENTITY dma_controller IS PORT (clk : IN qit. error2. . dev_rdy : IN qit. databus : INOUT byte := "ZZZZZZZZ".cpu signals select_reg : IN nibble. adbus : INOUT twelve := "ZZZZZZZZZZZZ". dev_rcv : OUT qit. write_mem : OUT qit := '0'. --device signals error1. -. -. • DMA controller entity declaration CHAPTER 11 17 © 1999. ready. dev_data : IN byte ). Z. Navabi and McGraw-Hill Inc.memory signals read_mem.

DMA DEVICE ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11. • DMA controller declarations. . Navabi and McGraw-Hill Inc. CHAPTER 11 18 © 1999.18) -“direct CPU communications” blocks (Figure 11. ALIAS ie : qit IS rfile(3)(3).17) BEGIN “get serial.19) END behavioral. put parallel” process statement (Figure 11. ALIAS rd : qit IS rfile(3)(1). • Outline of DMA controller architecture. ALIAS wr : qit IS rfile(3)(2). SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8). ALIAS go : qit IS rfile(3)(0). TYPE r4 IS ARRAY (0 TO 3) OF byte. SIGNAL done : qit := '0'. Z.

VARIABLE pntr : twelve. Z. databus <= "ZZZZZZZZ". WAIT UNTIL clk = '1'. done <= '0'. dev_rcv <= '1'. numb := rfile(2). -. WAIT UNTIL ready = '1'. END IF.put to mem write_mem <= '1'. adbus <= pntr. VARIABLE numb : byte. END PROCESS get_put. BEGIN WAIT UNTIL go = '1'. END IF. • DMA controller “get serial and put parallel” process CHAPTER 11 19 © 1999. dev_rcv <= '0'. write_mem <= '0'.get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'. END LOOP writing. databus <= buff. buff := dev_data. WAIT UNTIL clk = '0'. pntr := pntr + 1. adbus <= "ZZZZZZZZZZZZ".1. WAIT UNTIL grant = '1'.DMA DEVICE get_put : PROCESS VARIABLE buff : byte := zero_8. Navabi and McGraw-Hill Inc. pntr := rfile(1)(3 DOWNTO 0) & rfile(0). done <= '1'. IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb . -. .

• DMA controller “direct CPU communications” blocks CHAPTER 11 20 © 1999. END GENERATE cpu_direct. Z. .DMA DEVICE cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ". ie. error2. Navabi and McGraw-Hill Inc. r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus. error1). END BLOCK. r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1'. END BLOCK.

write_mem : OUT qit. Z. dev_data : IN byte ). write_mem. serial_in : IN qit). status_wr : IN qit. dev_rcv : OUT qit.DMA DEVICE ENTITY dma_serial_device IS PORT (clk : IN qit. dev_rdy : IN qit. databus : INOUT byte := "ZZZZZZZZ". received : IN qit. . frame_error : OUT qit. adbus : INOUT twelve. END dma_serial_device. dataready : BUFFER qit. END COMPONENT dcd. s2p_rdy. selects : OUT nibble). grant. BEGIN c1 : dma PORT MAP (clk. ready. COMPONENT s2p IS GENERIC (bps : INTEGER := 9600).14 CHAPTER 11 21 © 1999. description for diagram of Figure 11. END structural. s2p_er2. select_reg. adbus. status_wr. ready. END COMPONENT s2p. -ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit. select_reg). s2p_rdy. s2p_rcv. SIGNAL cpu_mem_addr : twelve. read_mem. read_mem. status_wr : IN qit. SIGNAL cpu_mem_data : byte. status_sel : OUT qit. -. Navabi and McGraw-Hill Inc. grant : IN qit. ready. s2p_er2 : qit. adbus : INOUT twelve. PORT (serial. active : OUT qit. overrun. databus : INOUT byte := "ZZZZZZZZ". databus. s2p_par). status_rd. grant : IN qit. COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"). s2p_er2. s2p_rcv. END COMPONENT dma. SIGNAL select_reg : nibble. • DMA serial device. status_sel. select_reg : IN nibble. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). SIGNAL s2p_rdy. c2 : dcd PORT MAP (adbus. status_rd.memory signals read_mem. status_rd. s2p_par). s2p_rcv. c3 : s2p PORT MAP (serial_in. SIGNAL s2p_par : byte. s2p_er1. error1. s2p_er1. error2. PORT (adbus : IN twelve. s2p_er1. write_mem : OUT qit := '0'.

Navabi and McGraw-Hill Inc.CPU CACHE adbus valid set tag 5 To 32 tag line Way 0 Way 1 5 DCD LSB 7 MSB 8 8 v=1 & v=1 Match & Match 0 8 1 Hit • Cache Block Diagram CHAPTER 11 22 © 1999. . Z.

. DCD lru • The lru table CHAPTER 11 23 © 1999. Z. 0: If a recent data was found in Way 1.CPU CACHE adbus 5 7 MSB LSB 5 To 32 1: If a recent data was found in Way 0. Navabi and McGraw-Hill Inc.

Z. .CPU CACHE me me m_ m_ ad dat bu abu s s rea gra wr read dy nt_ ite_ _m _m m m e em em em m cache da tab us ad bu s rea dy gra nt wr ite rea d 24 clk • Cache Interface CHAPTER 11 © 1999. Navabi and McGraw-Hill Inc.

ready : OUT qit. adbus : INOUT twelve := "ZZZZZZZZZZZZ" ). write_mem : OUT qit. mem_databus : INOUT byte := "ZZZZZZZZ".memory signals read_mem. • Cache Entity Declaration CHAPTER 11 25 © 1999. Navabi and McGraw-Hill Inc. . databus : INOUT byte := "ZZZZZZZZ".cpu signals read. write : IN qit. Z. grant. END cache_system.CPU CACHE ENTITY cache_system IS PORT (clk : IN qit. -. -. ready_mem : IN qit. grant_mem. mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ".

. Navabi and McGraw-Hill Inc. write If hit: For read. write data in cache and memory For read. END PROCESS. read from memory and pass on to CPU Wait until (read OR write)=’1’. Z. write data in cache and memory If miss: Find least recently used For write. • Outline of cache VHDL description CHAPTER 11 26 © 1999. pass data to CPU For write. END control_and_memory.CPU CACHE ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read.

tag : tags. END RECORD. • Cache structure declarations VARIABLE s : sets. data : line. TYPE ww IS ARRAY(ways) OF ways. SUBTYPE tags IS qit_vector (6 DOWNTO 0). Z. TYPE lru_type IS ARRAY (sets) OF ways. ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0). SIGNAL lru : lru_type. 0). Navabi and McGraw-Hill Inc. ALIAS tag_value : tags IS adbus (11 DOWNTO 5). free : ways. TYPE cache_type IS ARRAY (ways) OF each_cache. TYPE entry IS RECORD valid : BOOLEAN. SUBTYPE sets IS INTEGER RANGE 0 TO 31. TYPE line IS ARRAY (0 TO 0) OF byte.CPU CACHE SUBTYPE ways IS INTEGER RANGE 0 TO 1. TYPE each_cache IS ARRAY (sets) OF entry. SIGNAL cache : cache_type. . VARIABLE w. CONSTANT nw : ww := (1. • Controller local declarations CHAPTER 11 27 © 1999. VARIABLE hit : BOOLEAN.

cache(w)(s). mem_databus <= "ZZZZZZZZ". ready <= '0'. WAIT UNTIL grant_mem = '1'. mem_databus <= databus. • Controller search in cache IF hit THEN lru (s) <= nw (w). FOR i IN ways LOOP IF cache(i)(s). hit := FALSE. WAIT UNTIL clk = '0'. Navabi and McGraw-Hill Inc. mem_adbus <= "ZZZZZZZZZZZZ".tag = tag_value AND cache(i)(s).CPU CACHE grant <= '1'. databus <= cache(w)(s). write_mem <= '1'. ELSIF write = '1' THEN cache(w)(s). END IF. END IF. WAIT UNTIL read = '0'. databus <= "ZZZZZZZZ".data(0). w := i.valid THEN hit := TRUE. Z. mem_adbus <= adbus. s := TO_INTEGER (set_value). . • Controller code for cache hit CHAPTER 11 28 © 1999. END LOOP. WAIT UNTIL ready_mem = '1'. IF read = '1' THEN ready <= '1'. WAIT UNTIL write = '0'.data(0) <= databus. write_mem <= '0'.valid <= TRUE. ready <= '1'. ready <= '0'.

END IF. ELSIF read = '1' THEN read_mem <= '1'. WAIT UNTIL ready_mem = '1'. Navabi and McGraw-Hill Inc. ready <= '1'. mem_adbus <= adbus.data(0) <= databus. IF write = '1' THEN cache(free)(s). cache(free)(s).tag <= tag_value. ready <= '0'. mem_databus <= "ZZZZZZZZ".tag <= tag_value. END IF.valid <= TRUE. write_mem <= '0'. cache(free)(s). mem_adbus <= "ZZZZZZZZZZZZ". lru (s) <= nw (lru (s)). WAIT UNTIL ready_mem = '1'. mem_adbus <= "ZZZZZZZZZZZZ". mem_adbus <= adbus. WAIT UNTIL write = '0'.CPU CACHE ELSE -. • Controller code for cache miss CHAPTER 11 29 © 1999. . cache(free)(s). ready <= '1'. WAIT UNTIL grant_mem = '1'. databus <= mem_databus. WAIT UNTIL grant_mem = '1'.data(0) <= mem_databus. mem_databus <= databus. Z. WAIT UNTIL read = '0'. cache(free)(s). ready <= '0'.valid <= TRUE. write_mem <= '1'. read_mem <= '0'. cache(free)(s).miss free := lru (s).

Z. Navabi and McGraw-Hill Inc. .CPU CACHE Arbiter s2p Mem DMA Cache Decoder Parwan CPU • Board level interface CHAPTER 11 30 © 1999.

halted. rwbar. cpu_read. cpu_address. cpu_read.CPU CACHE ENTITY parwan_tester IS END parwan_tester. data. rd_req(1). Z. data. period) PORT MAP (rd_req. END system. Navabi and McGraw-Hill Inc. dev : serial PORT MAP (clock. srg : sergen PORT MAP (serial_in). cpu_data. rd_req(0). -ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1'. interrupt. '0' AFTER 4500 NS. address. csh_ready. . mem : memory PORT MAP (cs. wr_req(1). wr_req(0). cpu_address). cpu_write. ready. cpu_data. data. address. grant_mem(1). clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock. cs. rwbar. cpu_write. cpu_write. • Interface board VHDL description CHAPTER 11 31 © 1999. wr_req. csh : cache PORT MAP (clock. ready). skip_wait. csh_ready. csh_grant. address). csh_grant). cpu : parwan PORT MAP (clock. skip_wait. cpu_read. grant_mem. arb : arbitr GENERIC MAP ((OTHERS => 2). grant_mem(0). serial_in). clock. ready.

We have illustrated how such handshaking schemes can be described in VHDL. Z. . As opposed to Chapter 10 in which hardware details of a design were of concern. Language constructs for behavioral descriptions and timing and control were emphasized. The interface of the memory component is non-responsive. Navabi and McGraw-Hill Inc. while other components such as the CPU and cache controller have two or three line fully-responsive or partially-responsive handshaking schemes.SUMMARY In this chapter we presented a board level design in VHDL. We illustrated the use of VHDL in a component level design environment. Several components with differing handshaking schemes were independently described. and how VHDL constructs can be used for handing communication between various devices. • End of Chapter 11 CHAPTER 11 32 © 1999. show various forms of using wait statements in describing a design. The examples presented here. this chapter presented design at a higher level of abstraction. VHDL constructs used in this chapter were primarily at the behavioral level as discussed in Chapter 9.

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