Chapter 1

Hardware design environments

1.1 DIGITAL SYSTEM DESIGN PROCESS 1.1.1 Design Automation 1.2 The Art of Modeling 1.3 HARDWARE DESCRIPTION LANGUAGES 1.3.1 A Language for Behavioral Descriptions 1.3.2 A Language for Describing Flow of Data 1.3.3 A Language for Describing Netlists 1.4 HARDWARE SIMULATION 1.4.1 Oblivious Simulation 1.4.2 Event Driven Simulation 1.5 HARDWARE SYNTHESIS TEST APPLICATIONS 1.6 LEVELS OF ABSTRACTION 1.7 SUMMARY

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© 1999, Z. Navabi and McGraw-Hill Inc.

A digital system design process

Design Idea

Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing

Chip or Board

• Top-down design process • Starting with a design idea • Generating a chip or board

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© 1999, Z. Navabi and McGraw-Hill Inc.

Result of the data path design phase.

DATA

CONTROL

REG1

REG2 Procedure for Control of Movement of Data Between Registers and Buses.

...

MAIN LOGIC UNIT

REG3

LOGIC

...

• Dataflow description • Control Data partitioning

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© 1999, Z. Navabi and McGraw-Hill Inc.

An ISPS example, a simple processor.

mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** {tc} MAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END

• Behavioral Example • Only describing functionality

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© 1999, Z. Navabi and McGraw-Hill Inc.

An AHPL example, a sequential multiplier.

AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2); 1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7]; extra <= 4$0; => ( ^dataready, dataready ) / (1, 2). 2 busy <= \1\; => ( ^ac1[3], ac1[3] ) / (4, 3). 3 extra <= ADD[1:4] (extra; ac2). 4 extra, ac1 <= \0\, extra, ac1[0:2]; count <= INC(count); => ( ^(&/count), (&/count) ) / (2, 5). 5 result = extra, ac1; done = \1\; busy <= \0\; => (1). ENDSEQUENCE CONTROLRESET(1). END.

• Dataflow description • Describing clock control timing • AHPL, A Hardware Programming Language

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© 1999, Z. Navabi and McGraw-Hill Inc.

Full-adder, logical diagram and Verilog code.
a b c g1 w1 g5 s

g2 g3 g4 w3

w2

g6 w4

co

`timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule

• Gate level structural description • Describes gate level timing • Graphical and language based descriptions
CHAPTER 1 6 © 1999, Z. Navabi and McGraw-Hill Inc.

Hardware simulation.

Hardware Description (Model)

Simulation Hardware Model

Simulation Engine Component Library (Models)

Simulation Results (Output)

Test Data (Stimuli)

• Hardware simulation process • Component models, unit model form hardware model • Testbench may provide test data

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Verifying each design stage.

Design Idea SIMULATION TOOLS Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing Product Sample. Chip or Board Final Testing Device Simulator Gate Level Simulator Dataflow Simulator Behavioral Simulator

• Simulate at each step • Simulate to verify translation into lower level • Simulation cost increases at lower levels

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© 1999, Z. Navabi and McGraw-Hill Inc.

Simulating an exclusive-OR

a

1 3

5

7 4 b 2 6

z

t a b

0

1

2

3

4

5

6

7

8

9

0

• Simulating an XOR • Apply data at given time intervals or • Apply data as events occur

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© 1999, Z. Navabi and McGraw-Hill Inc.

Oblivious simulation.

GATE 1 2 3 4 5 6 7

FUNCTION Input Input NOT NOT AND AND OR

INPUT 1 a b 2 1 1 4 5

INPUT 2 ----3 2 6

VALUE 0 0 1 1 0 0 0

• Table representation • Simulate until no changes are made • Record values at table entries

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© 1999, Z. Navabi and McGraw-Hill Inc.

Event driven simulation.

1 a Inp 0

3 -

5 0 AND 0

NOT

OR 2 b Inp 0 NOT 0 AND 0 4 6

0

Legend: In1 In2 Fnc Out In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value

• Linked list representation • Simulate links with input events • Record values at node entries

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Layout. most commercial tools are 2 CHAPTER 1 12 © 1999. . Manufacturing 2 Flow Graph..Categories of synthesis tools.. Pseudo Code.. . Data Path Design Bus & Register Structure Logic Design Chip or Board • Synthesis • Transformation from one level to another • Ideal is 6. Navabi and McGraw-Hill Inc. Design Idea Behavioral Design SYNTHESIS TOOLS 1 4 6 5 3 Physical Design Transistor List.. . Z.

Navabi and McGraw-Hill Inc. Z.Synthesis process. Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives Synthesis Engine Logic Optimization Binding Synthesized Hardware (Netlist) • Hardware description and directives are tool inputs • Three synthesis stages • Layout or netlist is generated CHAPTER 1 13 © 1999. .

Z. c <= a + b. a b a ADDER x b y ADDER c d c • Input description affects synthesis results • Explicit specification of resource sharing • Sharing without and with extra overhead CHAPTER 1 14 © 1999. Navabi and McGraw-Hill Inc. d <= a + b. c <= x + y.Resource sharing. c <= a + b. .

6 Type Declaration and Usage 2.2.6 TEGAS 2.3 VHDL REQUIREMENTS 2.3.3.2.4 THE VHDL LANGUAGE 2.4 IDL 2.7 Use of Subprograms 2.3.2.3.8 Timing Control 2.4 Sequential Statement 2. .3.2 EXISTING LANGUAGES 2.3 CONLAN 2. Navabi and McGraw-Hill Inc. Z.2.5 Generic Design 2.2 CDL 2.3 Library Support 2.2.1 General Features 2.2 Support for Design Hierarchy 2.1 VHDL INITIATION 2.7 TI-HDL 2.3.2.8 ZEUS 2.3.2.Chapter 2 VHDL Background 2.5 ISPS 2.5 SUMMARY CHAPTER 2 1 © 1999.3.3.1 AHPL 2.9 Structural Specification 2.2.

VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs • Part of VHSIC program CHAPTER 2 2 © 1999. . Z. Navabi and McGraw-Hill Inc.

Intermetrics ITAR restrictions removed from language • 1984 IBM. Intermetrics : VHDL 2. Navabi and McGraw-Hill Inc. . TI.2 was released to IEEE ITAR removed from software • May 1985 : Standard VHDL 1076/A • December 1987 : VHDL 1076-1987 became IEEE standard • 1993 : VHDL 1076-1993 was approved CHAPTER 2 3 © 1999.0 was defined • December 1984 : VHDL 6.0 was released Software development started • 1985 : VHDL 7.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions • 1983 DoD : Requirements were established Contract was awarded to IBM. Z. TI.

Navabi and McGraw-Hill Inc. . Z.Languages reviewed • AHPL • CDL • CONLAN • IDL • ISPS • TEGAS • TI-HDL • ZEUS : A Hardware Programming Language : Computer Design Language : CONsensus LANguage : Interactive Design Language : Instruction Set Processor Specification : TEst Generation And Simulation : TI Hardware Description Language : An HDL by GE corpration CHAPTER 2 4 © 1999.

. Synthesis. High level design. Automatic hardware • Design Hierarchy Multi-level description Partitioning • Library Support Standard Packages Cell based design • Sequential Statements Behavioral software-like constructs CHAPTER 2 5 © 1999.VHDL Requirements • General Features Documentation. Z. Simulation. Navabi and McGraw-Hill Inc. Test.

Z. Navabi and McGraw-Hill Inc. concurrency • Structural Specification Wiring components CHAPTER 2 6 © 1999. .VHDL Requirements • Generic Design Binding to specific libraries • Type Declaration Strongly typed language • Subprograms • Timing Delays.

Navabi and McGraw-Hill Inc. . Z.VHDL Requirements CPU STACK ALU MUX COUNTER ALU BIT n BIT n-1 BIT 0 ALU_BIT ADDER MUX LOGIC MUX AND OR NOT • Use various levels of abstraction for defining a system • Upper level systems are partitioned into lower CHAPTER 2 7 © 1999.

Z.Example for hierarchical partitioning. . CPU STA CK A LU M UX COUNTER AL U BI T n BIT n-1 BIT 0 AL U_BI T A DDER M UX L OGIC M UX AND OR NOT • Recursive partitioning • Simple components as terminals CHAPTER 2 8 © 1999. Navabi and McGraw-Hill Inc.

Z.3 VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools VHDL Input Analyzer Lib. 1 . . LIBRARY SYSTEM .An example VHDL environment.2 Design Libraries Library Management Library Environment • VHDL defines library usage • Tools define library management CHAPTER 2 9 © 1999. Navabi and McGraw-Hill Inc.

3.1 Describing Components 3.1.1.Chapter 3 Design Methodology Based on VHDL 3.5 Real World 3. .1 Verification 3.3.2 Packages 3.5 CONTROLLER DESCRIPTION 3.7 CONVENTIONS AND SYNTAX 3.3.3.4 Final Act 3.3. Navabi and McGraw-Hill Inc.3 Design Scenario 3.8 SUMMARY CHAPTER 3 1 © 1999.2 TOP-DOWN DESIGN 3.1.3 Libraries and Binding 3. Z.1 Design to Perform 3.1 ELEMENTS OF VHDL 3.2 Setting The Stage 3.2.6 VHDL OPERATORS 3.4 SUBPROGRAMS 3.3 TOP-DOWN DESIGN WITH VHDL 3.

Interface and architectural specifications. END identifier. physical and other parameters. CHAPTER 3 2 © 1999. Navabi and McGraw-Hill Inc. ARCHITECTURE identifier OF component_name IS declarations. ENTITY component_name IS input and output ports. END component_name. . BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters. Z.

. ) . Z... ENTITY component_i IS PORT (. .... . ARCHITECTURE dataflow OF component_i IS ... other ARCHITECTURES OF component_i . .. CHAPTER 3 3 © 1999.. .Multiple architectural specifications. ARCHITECTURE structural OF component_i IS .. Navabi and McGraw-Hill Inc.... . ARCHITECTURE behavioral OF component_i IS . .

PACKAGE package_name IS component declarations.Packages. sub-programs. Z. PACKAGE BODY package_name IS type definitions. END package_name. sub-program declasrations. Navabi and McGraw-Hill Inc. END package_name. CHAPTER 3 4 © 1999. .

Design binding. CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. LIBRARY library_name. END CONFIGURATION. Navabi and McGraw-Hill Inc. binding components of a library to subcomponents. Z. CHAPTER 3 5 © 1999. . specifying parameters of a design.

CHAPTER 3 6 © 1999. END Partition. . Z. END FOR. Navabi and McGraw-Hill Inc. Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i). END IF.Recursive partition procedure.

. . SUD Design Implementation SSC1 SSC2 SSC3 SSC4 SSC31 . Navabi and McGraw-Hill Inc.. SSC3n SSC41 SSC42 SSC311 SSC312 SSC3n1 SSC3n2 SUD: System Under Design SSC : System Sub-Component Shaded areas designate sub-componts with hardware implementation. bottom-up implementation.Top-down design. Z. CHAPTER 3 7 © 1999.

Z.Verifying the first level of partitioning. Navabi and McGraw-Hill Inc. Behavioral Model are mp Co SUD SSC1 SSC2 SSC3 SSC4 Interconnection of Behavioral Models CHAPTER 3 8 © 1999. .

Behavioral Model are omp C SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model CHAPTER 3 9 © 1999. Z. Navabi and McGraw-Hill Inc.Verifying hardware implementation. .

Z. . SSC3n SSC41 SSC42 SSC311 SSC312 CHAPTER 3 10 © 1999.Verifying the final design. Behavioral Model e par Com SUD SSC1 SSC2 SSC3 SSC4 Har dwa re M odel SSC31 .. Navabi and McGraw-Hill Inc..

. SSC3n SSC311 SSC312 .Verifying hardware implementation of SSC3. SSC3n1 SSC3n2 Hardware Model CHAPTER 3 11 © 1999.. Z.. Behavioral Model SSC3 Co m pa re SSC31 . Navabi and McGraw-Hill Inc.. .

an alternative to the setup of Figure 3. Z. Navabi and McGraw-Hill Inc. .Verifying the final design. CHAPTER 3 12 © 1999. p Com are SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model SSC41 SSC42 Verifying the final design.9.

Navabi and McGraw-Hill Inc. . a b start clock Synchronously add data on a and b put result on result. Z.Serial adder. result ready CHAPTER 3 13 © 1999.

. 1R S1 1D Z 1D C1 Q _ 1D (a) Multiplexer (b) Flipflop CHAPTER 3 14 © 1999. Z.Available library elements. Navabi and McGraw-Hill Inc.

VHDL model of the multiplexer library element. Z. Navabi and McGraw-Hill Inc. ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). z : OUT BIT).Multiplexer library element. CHAPTER 3 15 © 1999. data1. . PORT (sel. data0 : IN BIT. END dataflow. -ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay. END mux2_1.

Navabi and McGraw-Hill Inc. Busb Reg File Reg1 Alu Controller Reg2 Busa Dataflow descriptions. CHAPTER 3 16 © 1999. .Dataflow descriptions. Z.

CHAPTER 3 17 © 1999. Z. qout : BUFFER BIT := '0'). END IF. clk : IN BIT. END PROCESS. din. ENTITY flop IS GENERIC (td_reset. -ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset. Navabi and McGraw-Hill Inc. PORT (reset. td_in : TIME := 8 NS).Flip-flop library element. . END flop. VHDL model of the flip-flop library element. END IF. END behavioral. ELSE qout <= din AFTER td_in.

Valid ? Transmit . . Receive FOR all data : Process data : Queue data : END FOR.Behavioral descriptions. . CHAPTER 3 18 © 1999. Behavioral descriptions. . Navabi and McGraw-Hill Inc. Z.

END counter. ELSE counting <= '1' AFTER td_cnt. -ARCHITECTURE behavioral OF counter IS BEGIN PROCESS (clk) VARIABLE count : INTEGER := limit. counter. clk : IN BIT. counting : OUT BIT := '0'). END IF. CONSTANT limit : INTEGER := 8. END IF. Navabi and McGraw-Hill Inc. CHAPTER 3 19 © 1999. Z. BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0. END IF.Divide by 8. Divide by 8. . IF count = limit THEN counting <= '0' AFTER td_cnt. ELSE IF count < limit THEN count := count + 1. END PROCESS. ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS). counter. END IF. END behavioral. PORT (reset.

Z. .Design stage setting. Navabi and McGraw-Hill Inc. VHDL Boolean p r e d e s i g n e d layouts Synthesize l i b r a r y mux2-1 Count flop CMOS layout CHAPTER 3 20 © 1999.

carry : BIT. VARIABLE sum. END PROCESS. start. clock : IN BIT. carry := (a AND b) OR (a AND carry) OR (b AND carry). END IF. END serial_adder. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. Z. END IF. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) VARIABLE count : INTEGER := 8. IF count = 8 THEN ready <= '1'. ELSE IF count < 8 THEN count := count + 1. CHAPTER 3 21 © 1999. ready : OUT BIT. b.Serial adder behavioral description. END behavioral. . END IF. END IF. sum := a XOR b XOR carry. result <= sum & result (7 DOWNTO 1). ELSE ready <= '0'. ENTITY serial_adder IS PORT (a. Serial adder behavioral description. carry := '0'. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). Navabi and McGraw-Hill Inc.

CHAPTER 3 22 © 1999. Navabi and McGraw-Hill Inc.VHDL simulation results. . Z.

CHAPTER 3 23 © 1999. ELSE IF count < 8 THEN count := count + 1. sum := a XOR b XOR carry. .Partial code of serail_adder. result <= sum & result (7 DOWNTO 1). END IF. Navabi and McGraw-Hill Inc. carry := (a AND b) OR (a AND carry) OR (b AND carry ). Z.

Z. Navabi and McGraw-Hill Inc. .General layout of serial_adder. counting counter serial_sum en si a b Adder carry_out Flop result Shift Regiser carry_in clock CHAPTER 3 24 © 1999.

Navabi and McGraw-Hill Inc. serial_adder full_adder flip_flop shifter counter CHAPTER 3 25 © 1999.First level of partitioning. . Z.

END fulladder.Full_adder description. sum. END behavioral. cout <= (a AND b) OR (a AND cin) OR (b AND cin). -ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin. ENTITY fulladder IS PORT (a. cin : IN BIT. CHAPTER 3 26 © 1999. Z. cout : OUT BIT). . b. Navabi and McGraw-Hill Inc.

Shifter VHDL description. END dataflow. END shifter. reset. enable. ENTITY shifter IS PORT (sin. Navabi and McGraw-Hill Inc. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). Z. -ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED. . clk : IN BIT. CHAPTER 3 27 © 1999. END BLOCK.

Z. .Completed parts of first partitioning. Navabi and McGraw-Hill Inc. serial_adder full_adder flop shifter counter CHAPTER 3 28 © 1999.

END structural. u2 : flop PORT MAP (start. parout : BUFFER BIT_VECTOR(7 DOWNTO 0)). clock. BEGIN u1 : fulladder PORT MAP (a. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). result). END COMPONENT. cin : IN BIT. counting). clock. u4 : shifter PORT MAP (serial_sum. -SIGNAL serial_sum. carry_in). END COMPONENT. END serial_adder. b. start. ENTITY serial_adder IS PORT (a. u3 : counter PORT MAP (start. CHAPTER 3 29 © 1999. din. Navabi and McGraw-Hill Inc. b. b. END COMPONENT. PORT (reset. clk : IN BIT. carry_in. -ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS). counting : OUT BIT := '0'). END COMPONENT. COMPONENT shifter IS PORT (sin. u5 : ready <= NOT counting. qout : BUFFER BIT := '0'). carry_out). clk : IN BIT. carry_in. COMPONENT fulladder IS PORT (a. clk : IN BIT. carry_out. counting : BIT. enable. counting. COMPONENT flop IS GENERIC (td_reset. clock : IN BIT. carry_out. reset. cout : OUT BIT). sum. PORT (reset. . clock. td_in : TIME := 8 NS).Structural description of serial_adder. ready : OUT BIT. start. serial_sum. Z.

Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out a b cin sum count Signals in the interface of fulladder CHAPTER 3 30 © 1999. Z. Navabi and McGraw-Hill Inc. .Signal mapping for fulladder instantiation.

END COMPONENT. COMPONENT fulladder IS PORT (a. sum. END COMPONENT. din . PORT (reset. serial_sum. -SIGNAL serial_sum. CHAPTER 3 31 © 1999. carry_out. BEGIN u1 : fulladder PORT MAP (a. carry_in). carry_in. qout : BUFFER BIT := '0'). COMPONENT flop IS GENERIC (td_reset. Z. clock.Interconnecting ports. cout : OUT BIT). carry_out ). b. Navabi and McGraw-Hill Inc. clk : IN BIT. . carry_in. counting : BIT. td_in : TIME := 8 NS). carry_out . b. cin : IN BIT. u2 : flop PORT MAP (start.

shifter der_flop der_flop der_flop der_flop der_flop der_flop der_flop der_flop CHAPTER 3 32 © 1999. . . . . Z. Navabi and McGraw-Hill Inc.Partitioning shifter.

ENTITY der_flop IS PORT (din. END IF. . -ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'. END PROCESS. END behavioral. Navabi and McGraw-Hill Inc. END IF. END der_flop. qout : OUT BIT := '0').Behavioral model of der_flop. reset. ELSE IF enable = '1' THEN qout <= din. CHAPTER 3 33 © 1999. Z. clk : IN BIT. enable. END IF.

parout(5)). clk. enable. enable. BEGIN b7 : der_flop PORT MAP ( sin. enable. b6 : der_flop PORT MAP (parout(7). clk. clk. enable. enable. b4 : der_flop PORT MAP (parout(5). parout(7)). clk : IN BIT. . reset. enable. reset. Z. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). reset. b5 : der_flop PORT MAP (parout(6). parout(0)). parout(2)). enable. Navabi and McGraw-Hill Inc. END COMPONENT. qout : BUFFER BIT := '0'). -ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din. clk. reset. parout(1)). clk. parout(3)). CHAPTER 3 34 © 1999. END shifter. clk. b2 : der_flop PORT MAP (parout(3). b3 : der_flop PORT MAP (parout(4). parout(6)). enable. END structural. enable. parout(4)). reset. reset. clk. b1 : der_flop PORT MAP (parout(2). enable. reset. clk. ENTITY shifter IS PORT (sin. b0 : der_flop PORT MAP (parout(1). clk : IN BIT.Structural description of shifter. reset. reset. reset.

.Hardware realization of der_flop. Z. enable reset din S1 1D qout 1R 1D C1 Q dff_in _ 1D clock CHAPTER 3 35 © 1999. Navabi and McGraw-Hill Inc.

der_flop mux2_1 flop CHAPTER 3 36 © 1999. Z. Navabi and McGraw-Hill Inc.Partitioning der_flop. .

qout. . CHAPTER 3 37 © 1999. -ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset. BEGIN mx : mux2_1 PORT MAP (enable. din. clk : IN BIT. dff_in. PORT (reset. td_in : TIME := 8 NS). qout : BUFFER BIT). reset. clk. Z. z : OUT BIT). COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). enable. qout : BUFFER BIT := '0'). qout). END behavioral. dff_in). END der_flop. END COMPONENT.Structural description of der_flop. data0 : IN BIT. data1. END COMPONENT. Navabi and McGraw-Hill Inc. clk : IN BIT. ff : flop PORT MAP (reset. PORT (sel. din. ENTITY der_flop IS PORT (din. SIGNAL dff_in : BIT.

. Navabi and McGraw-Hill Inc. . mux2-1 flop . serial-adder fulladder flop shifter counter der-flop der-flop . . .Complete design of seraial_adder. CHAPTER 3 38 © 1999. . der-flop . Z. . .

Z. .Final Design. . . . 1 s1 . . a b Fulladder serial-sum 1 s1 1 1R Q 1D 1R Q 1D 1 s1 1 . CHAPTER 3 39 © 1999. Navabi and McGraw-Hill Inc. . reset Counter counting . ... 1 1R Q 1D C1 carry_in 1R 1D C1 C1 C1 Q carry_out clk .

END IF. END behavioral. ELSE IF count < 8 THEN count := count + 1. VARIABLE sum. Z.Synthesizable serial adder. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8. . b. IF count = 8 THEN ready <= '1'. CHAPTER 3 40 © 1999. result <= sum & result (7 DOWNTO 1). END IF. carry := '0'. ready : OUT BIT. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END PROCESS. END IF. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. END serial_adder. Navabi and McGraw-Hill Inc. END IF. clock : IN BIT. ELSE ready <= '0'. VARIABLE count : CNT8 := 8. ENTITY serial_adder IS PORT (a. carry := (a AND b) OR (a AND carry) OR (b AND carry). sum := a XOR b XOR carry. carry : BIT. start.

Navabi and McGraw-Hill Inc.FPGA layout of serial_adder. CHAPTER 3 41 © 1999. . Z.

. END byte_to_integer. CHAPTER 3 42 © 1999. Navabi and McGraw-Hill Inc. PROCEDURE byte_to_integer (ib : IN byte.Type conversion procedure. END LOOP. END IF. BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i. oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0. Z. oi := result. . TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT.. .

The fadd (full adder) function. BEGIN sc(1) := a XOR b XOR c. c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0). FUNCTION fadd (a. RETURN sc. sc(0) := (a AND b) OR (a AND c) OR (b AND c). END. CHAPTER 3 43 © 1999. Z. b. Navabi and McGraw-Hill Inc. .

b. cin). END fulladder. CHAPTER 3 44 © 1999. Navabi and McGraw-Hill Inc.fulladder using fadd. b. sum. -ARCHITECTURE behavioral OF fulladder IS BEGIN (sum. ENTITY fulladder IS PORT (a. . cout) <= fadd (a. cout : OUT BIT). Z. cin : IN BIT. END behavioral.

. Navabi and McGraw-Hill Inc.. x= . zn z<= ..General outline of a controller. . . xn z<= . Z. . . . .. z<= . . . . z1 . x1 x= .. clock CHAPTER 3 45 © 1999. . .

Moore machine description. . IF 110 sequence is detected on x THEN z gets '1' x ELSE z gets '0' END. Navabi and McGraw-Hill Inc. z clk CHAPTER 3 46 © 1999. Z.

Z. Navabi and McGraw-Hill Inc. .Sequence detector state machine. 0 1 1 reset 0 0 0 got1 0 1 got11 0 1 0 got110 1 CHAPTER 3 47 © 1999.

END behavioral. got1. WHEN got11 => IF x = ‘1’ THEN current <= got11. END CASE. WHEN got1 => IF x = ‘1’ THEN current <= got11. END IF. ENTITY moore_110_detector IS PORT (x. z <= ‘1’ WHEN current = got110 ELSE ‘0’. WHEN got110 => IF x = ‘1’ THEN current <= got1. clk : IN BIT . END IF. END PROCESS. END IF. ELSE current <= reset. . ELSE current <= got110.VHDL Description of 110 detector. got11. -ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset. END IF. SIGNAL current : state := reset. END IF. z : OUT BIT). got110). ELSE current <= reset. Navabi and McGraw-Hill Inc. Z. ELSE current <= reset. CHAPTER 3 48 © 1999. BEGIN PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1. END moore_110_detector.

Z. WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset.. .State transition and corresponding VHDL code. ... END IF.. Navabi and McGraw-Hill Inc. 1 reset 0 0 got1 0 got11 0 . CHAPTER 3 49 © 1999.

REAL Same Type REM INTEGER Same Type ABS MISCELLENEOUS ** Numeric Left: Numeric Right: Integer Same Type Same as Left CHAPTER 3 50 © 1999. Navabi and McGraw-Hill Inc. Operators AND NAND XOR = < > SLL SLA ROL + OR NOR XNOR /= <= >= SRL SRA ROR & Operand Type BIT or BOOLEAN All Types Left: BIT or BOOLEAN Vector Right: INTEGER Numeric Array or Array Element Numeric Result Type BIT or BOOLEAN BOOLEAN LOGICAL RELATIONAL SHIFT BOOLEAN ADDING Same Type SIGN + - Same Type * MULTIPLYING MOD / INTEGER. Z. .VHDL operators.

Syntax details of the architecture body. = O FE S c <= a AFTER 10 NS. N e o architecture declarative_part architecture body architecture statem n e t_part CHAPTER 3 51 © 1999. . A C I E T R d m O e a p IS R HT C U E e o F z m le S IGNAL a. b. IT B G E IN a <= '1' A T R1 N . c : B := '0'. Navabi and McGraw-Hill Inc. Z. E Dd m . FE 5 S b< N TaA T R5N .

3 SIGNAL ASSIGNMENTS 4.4.1. .4 Sequential Placements of Transactions 4.2 OBJECTS AND CLASSES 4. Navabi and McGraw-Hill Inc.Basic Concepts in VHDL 4.1 CHARACTERIZING HARDWARE LANGUAGES 4.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS 4.5 SUMMARY CHAPTER 4 1 © 1999.1.3. Z.3 Comparing Inertial and Transport 4.1 Timing 4.2 Events and Transactions 4.3 Modeling Hardware 4.1 Concurrent Assignments 4.3.1.3.3 Delta Delay 4.4.4.2 Transport Delay Mechanism 4.4.1 Inertial Delay Mechanism 4.2 Concurrency 4.

. Z.Value transfer through wires. Navabi and McGraw-Hill Inc. • What happens in a real hardware • Must be able to model properly CHAPTER 4 2 © 1999.

a <= x AFTER 4*unit_delay. • In one case immediate assignemnts are done • In another case scheduling is done CHAPTER 4 3 © 1999. a := x. b := x.Value transfer through wires. . b <= x AFTER 3*unit_delay. Navabi and McGraw-Hill Inc. Z.

S A B C • Hardware description requires concurrent constructs • Concurrent bodies can be described behaviorally or at the dataflow level CHAPTER 4 4 © 1999.Describing sub-components. Z. Navabi and McGraw-Hill Inc. .

Z.A VHDL concurrent body • A VHDL concurrent body • Statements are executed when events occur CHAPTER 4 5 © 1999. Navabi and McGraw-Hill Inc. .

.. Navabi and McGraw-Hill Inc.A VHDL sequential body ARCHITECTURE sequential .. IF THEN ELSE .. BEGIN . . END ARCHITECTURE • A VHDL sequential body • Statements are executed when program flow reaches them CHAPTER 4 6 © 1999... . .. BEGIN . PROCESS . Z. . . END PROCESS . . FOR LOOP .. .

Z. . a b g2 x z g4 c g1 w g3 y • Four concurrent gates • Each has a delay of 12 ns • Change in inputs may result in in output hazards CHAPTER 4 7 © 1999. Navabi and McGraw-Hill Inc.Illustrating timing and concurrency.

Navabi and McGraw-Hill Inc. g1 g2 g3 g4 R a tin e c g R a tin e c g R a tin e c g R a t e c ing R a tin e c g 0 12 24 36 Nanosecond • a changes from ‘1’ to ‘0’ • A change in the a input results in domino changes each 12 ns apart • No more events occur when output is reached CHAPTER 4 8 © 1999. .Gates reacting to changes. Z.

.a b c w x y z 0 12 24 36 Nanosecond • Timing diagram resulting from input a changing from ‘1’ to ‘0’ at time zero • A glitch appears on the output • Must model hardware to imitate this behavior • Requires timing and concurrency in the language CHAPTER 4 9 © 1999. Navabi and McGraw-Hill Inc. Z.

. w_signal v_signal concurrent_body_3 u_signal <= local_constant v_signal <= ........... u_signal concurrent_body_2 x_signal <= . b_signal y_signal <= . Z. w_signal <= .Objects and Classes del1_constant del2_constant concurrent_body_1 sequential_body_1 a_signal a_variable := .. x_signal y_signal <= . .. loop_variable_i . Navabi and McGraw-Hill Inc... y_signal z_signal <= . z_signal • Objects and classes in sequential and concurrent bodies • Foundation for modeling timing and concurrency are signals • Variables are used as software variables CHAPTER 4 10 © 1999..

Objects and Classes Using Objects In VHDL O B J E C T Signal Variable Constant File BODY Declare YES NO YES YES Concurrent Assign to YES NO --Use YES YES YES YES Declare NO YES YES YES Sequential Assign to YES YES --Use YES YES YES YES • Objects in VHDL bodies • Cannot declare signals in sequential bodies • Variable assignments are only done in sequential bodies CHAPTER 4 11 © 1999. Navabi and McGraw-Hill Inc. . Z.

Comparing targets diff12 <= target1 XOR target2. diff23 <= target2 XOR target3. target3 : BIT. ‘0’ AFTER 47 NS. SIGNAL diff12. -. ‘1’ AFTER 33 NS. Reject and Transport • Inertial: rejects anything less than its delay • Reject: rejects anything less than or equal to its reject • Transport: does not reject CHAPTER 4 12 © 1999. -.Illustrating inertial delay target1 <= waveform AFTER 5 NS. Navabi and McGraw-Hill Inc. Z. ‘0’ AFTER 27 NS. -. ‘0’ AFTER 18 NS. diff13 <= target1 XOR target3. SIGNAL target1. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. • VHDL description for the demonstration of delay mechanisms • Example shows several concurrent statements • Inertial. ‘0’ AFTER 85 NS. ‘1’ AFTER 62 NS. ‘1’ AFTER 14 NS. ‘1’ AFTER 52 NS. END delay. . -. diff23 : BIT. ‘0’ AFTER 08 NS. ‘0’ AFTER 77 NS. ‘1’ AFTER 71 NS. ‘1’ AFTER 24 NS.Delay Mechanisms ENTITY example IS END ENTITY.Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS. ‘1’ AFTER 41 NS.Creating waveform waveform <= ‘1’ AFTER 03 NS.This is a comment BEGIN -. ‘0’ AFTER 35 NS. ‘0’ AFTER 68 NS. ‘0’ AFTER 58 NS. target2. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. ‘1’ AFTER 79 NS. diff13.

Z.Delay Mechanisms R Target 1 or Target 2 C • The RC delay is best represented by inertial delay mechanism • This is a simple version of Inertial • For more accurate modeling Reject can be used CHAPTER 4 13 © 1999. Navabi and McGraw-Hill Inc. .

Navabi and McGraw-Hill Inc. .Delay Mechanisms 5 6 4 6 3 6 2 6 6 5 6 4 6 3 6 2 6 • Illustrating differences between delay mechanism in VHDL • Positive and negative pulses appear on the LHS CHAPTER 4 14 © 1999. Z.

• VHDL description for the gate level circuit for the demonstration of timing and concurrency • Four concurrent statements model gates of the circuit • Events of the RHS cause evaluation and scheduling • A scheduled value may or may not appear on the LHS • A scheduled value is a transaction on the driver of the LHS signal CHAPTER 4 15 © 1999. Z. Navabi and McGraw-Hill Inc. END concurrent. y : BIT.Concurrency ENTITY figure_5_example IS PORT (a. x <= a AND b AFTER 12 NS. x. c : IN BIT. ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w. END figure_5_example. . y <= c AND w AFTER 12 NS. z <= x OR y AFTER 12 NS. b. z : OUT BIT). BEGIN w <= NOT a AFTER 12 NS.

Concurrency Resolution Function Multiple Driving Values Signal Value • A signal may have more than one driver • Resolving a single value from multiple driving values • Each driver has its own timing • Independent handling of all drivers • A driving value that is current contributes to the resolution function CHAPTER 4 16 © 1999. . Z. Navabi and McGraw-Hill Inc.

Z. 0) now • A transaction. . d-t ) 0 EXPIRED 0 t t 0 t1 d tri = (v. d) d-t0 tri = (v.Events and Transactions transaction time component d tri = (v. from being created to being expired • A transaction that expires generates a current driving value • This value contributes to the resolution function CHAPTER 4 17 © 1999. Navabi and McGraw-Hill Inc.

b. c : BIT := '0'. Navabi and McGraw-Hill Inc. END demo.Events and Transactions ARCHITECTURE demo OF example IS SIGNAL a. . b <= NOT a AFTER 5 NS. BEGIN a <= '1' AFTER 15 NS. • A simple description for illustrating events and transactions • Transactions are scheduled on the 3 LHS signals • Order is not significant • Initial transaction are placed on all 3 signals CHAPTER 4 18 © 1999. c <= a AFTER 10 NS. Z.

10) on c 0 5 10 (b) 15 20 25 NS Transactions At 5 NS Intervals a c b a c a c b c 0 5 10 (c) 15 20 25 NS Path Of Transactions To Expiration a c b b NS c 0 5 10 15 20 25 • Events and transactions (d) CHAPTER 4 19 © 1999. Navabi and McGraw-Hill Inc. 10) on c (1. 05) on b (0.Events and Transactions a 0 0 0 b c 0 5 10 (a) 15 20 25 NS Transactions W hen They Are Placed on Signals (1. 15) on a (1. . Z. 05) on b (0.

-ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z. . • Demonstrating need for delta delay • A “hidden” delay exists between z and z_bar • Delta delay makes us believe that they take place at the same real time • The hidden delay is Delta which is not real-time CHAPTER 4 20 © 1999. zbar : BUFFER BIT). Z. Navabi and McGraw-Hill Inc. END ENTITY. z <= a AND b AFTER 10 NS. b : IN BIT.Delta Delay ENTITY timing IS PORT (a. END delta. z.

BEGIN y <= c AND w. x <= a AND b. x. END not_properly_timed.Delta Delay ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w. Navabi and McGraw-Hill Inc. • VHDL description for demonstrating the delta delay • Sequentiality in execution. w <= NOT a. . Z. z <= x OR y AFTER 36 NS. same exact real time CHAPTER 4 21 © 1999. y : BIT := '0'.

Navabi and McGraw-Hill Inc. we do not see Sequentiality CHAPTER 4 22 © 1999. Z.Delta Delay a1 b1 c1 w0 x0 y 0 z1 0 1 2δ 3δ 0 δ 12 24 36 NS • Timing diagram showing delta delays • Looking at real times. .

• Description for a chain of two inverters • Demonstrating Delta. b <= NOT a. Navabi and McGraw-Hill Inc. END concurrent. Z.Delta Delay ARCHITECTURE concurrent OF timing_demo IS SIGNAL a. BEGIN a <= '1'. . c <= NOT b. c : BIT := '0'. b. transactions and concurrency CHAPTER 4 23 © 1999.

Z. Navabi and McGraw-Hill Inc.Delta Delay a 0 b0 c 0 0 δ 1 2δ 3δ 0 NS • Timing diagram for timing_demo • Everything happens at real-time 0 CHAPTER 4 24 © 1999. .

. Z. Navabi and McGraw-Hill Inc. ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’. SIGNAL y: BIT := ‘1’. END forever. y <= NOT x. x 0 0 1δ 2δ 3δ 4δ 5δ 6δ 7δ 0 t y 1 0 1δ 2δ 3δ 4δ 5δ 6δ 0 t • Oscillation in zero real time • Don’t try this at home CHAPTER 4 25 © 1999. BEGIN x <= y.Delta Delay y x Ideal elements with zero real time delay.

END sequential. BEGIN PROCESS x<= v1 AFTER t1. Z. END PROCESS. • Sequential placement of transactions in a sequential body of VHDL • A wait.Sequential Placement of Transactions ARCHITECTURE sequential OF sequential_placement IS . Navabi and McGraw-Hill Inc. .. x<= v2 AFTER t2. WAIT. statement suspends a sequential body forever • Sequentially values are placed on the LHS CHAPTER 4 26 © 1999..

. Navabi and McGraw-Hill Inc. • Sequential placement of transaction in a concurrent body of VHDL • Same effect as the above process statement CHAPTER 4 27 © 1999. v2 AFTER t2-t1 x <= a AFTER t2. Z. BEGIN a <= v1...Sequential Placement of Transactions ARCHITECTURE concurrent OF sequential_placement IS . END concurrent.

Z. or overrides existing ones CHAPTER 4 28 © 1999. . Navabi and McGraw-Hill Inc.Sequential Placement of Transactions • Projected output waveform • A new transaction will be compared with all existing transactions • It appends.

. Z.Sequential Placement of Transactions • Multiple drivers of a resolved signal • Each driver timing is treated independently CHAPTER 4 29 © 1999. Navabi and McGraw-Hill Inc.

v = v existing new 4 Append the new transaction. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions TRANSPORT 1 New Transaction is BEFORE Already Existing Overwrite existing transaction 3 INERTIAL Overwrite existing transaction 2 New Transaction is AFTER Already Existing Append the new transaction. Difference between time of new and existing is greater than the reject value v /=v existing new 5 Append the new transaction Difference between time of new and existing is less than or equal to reject value v /=v existing new 6 Overwrite existing transaction • Effective transactions on the driver of a signal • Multiple transactions are sequentially placed on the signal driver CHAPTER 4 30 © 1999. Z. .

Z. CHAPTER 4 31 © 1999. . END PROCESS. x <= TRANSPORT ‘0’ AFTER 3 NS. WAIT. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := ‘Z’. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. END sequential.

BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. CHAPTER 4 32 © 1999. END sequential.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. Z. x z z 1 0 7 8 9 0 1 2 3 4 5 6 • Appending transactions • Delay type is transport • The new transaction is after the existing one. Navabi and McGraw-Hill Inc. . x <= TRANSPORT ‘0’ AFTER 8 NS. END PROCESS. WAIT.

END PROCESS. Navabi and McGraw-Hill Inc. x <= ‘0’ AFTER 3 NS. Z. WAIT.Sequential Placement of Transactions ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := ‘Z’. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. . x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one CHAPTER 4 33 © 1999. END sequential.

Navabi and McGraw-Hill Inc. END PROCESS. BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS. END sequential. x z z 0 7 8 9 0 1 2 3 4 5 6 • Saving previous transactions of same value • Transactions with the same value are both kept on the driver of x CHAPTER 4 34 © 1999. Z.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. WAIT. x <= ‘0’ AFTER 8 NS. .

WAIT. x Z z Z 1 0 0 1 2 3 4 5 6 7 8 9 • Appending the new transaction of different value • Time difference of new and existing is greater than reject value CHAPTER 4 35 © 1999. END PROCESS. Z. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS. Navabi and McGraw-Hill Inc. . END sequential.Sequential Placement of Transactions ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=’Z’.

WAIT. END sequential x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions of different value • The new transaction is scheduled after the existing. END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. . x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=’Z’. Navabi and McGraw-Hill Inc. and has a different value CHAPTER 4 36 © 1999. Z.

.Signal assignments target1 <= waveform AFTER 5 NS. Z.Creating waveform waveform <= '1' AFTER 03 NS. target3 <= TRANSPORT waveform AFTER 5 NS. '1' AFTER 33 NS. reject. and transport delay mechanisms • This is a result of sequential placement of transactions CHAPTER 4 37 © 1999. '0' AFTER 18 NS. '0' AFTER 35 NS. '0' AFTER 08 NS. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS.Sequential Placement of Transactions ENTITY example IS END ENTITY. target3 : BIT. END delay. SIGNAL target1. target2. -. 0 3 5 8 14 18 24 27 29 32 33 35 38 40 • Pulse rejection in inertial. '1' AFTER 14 NS. '1' AFTER 24 NS. '0' AFTER 27 NS. Navabi and McGraw-Hill Inc. BEGIN -. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT.

5) (0.2) target3 © 1999.5) (1.5) (0.5) (0.5) (0.0) (1.0) (0.5) (0.5) (0.5) (1.0) (0.0) (0.0) (1.3) (0.5) (1.5) (1.0) (0.0) (0.0) (1.5) (0.5) (0.0) (1.2) target1 (1.1) (1.5) (0.3) (0.2) target2 Sequential Placement of Transactions • New.2) (0.0) (0.5) (1.5) (1.5) (1.0) (1.5) (0.5) (0.3) (1.1) (1.5) (0.5) (0. pending. Navabi and McGraw-Hill Inc.0) (1.0) (1.3) (0.0) (1.0) (0.5) (0. 0 3 32 33 35 38 40 .5) (1.0) (1.0) (1.3) (0.2) (0.0) (1. Z.3) (1.2) (0. and expired transactions on targets of example 38 5 8 13 14 18 19 23 24 27 29 (1.CHAPTER 4 (1.3) (0.5) (1.5) (1.0) (1.5) (0.5) (1.0) (1.1) (1.

b <= '0'. all but the first are TRANSPORT CHAPTER 4 39 © 1999. '1' AFTER 15 NS. END delay. • Sequential placement of transactions by executing concurrent signal assignments • Events on a cause placement of transactions on b • In a waveform. b : BIT. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ENTITY example IS END ENTITY. a AFTER 3 NS. BEGIN -. Z. .Signal assignments a <= '1' AFTER 5 NS. '0' AFTER 10 NS. -ARCHITECTURE delay OF example IS SIGNAL a.

1 PARTS LIBRARY 5.6.1 Sequential Comparator 5.4 MODELING A TEST BENCH 5.2 VHDL Description of a 4-Bit Comparator 5.2 VHDL Description of bit_comparator 5.1 Design of a 4-Bit Comparator 5.1 Inverter Model 5.2 NAND Gate Models 5.1 Logic Design of Comparator 5.3 WIRING ITERATIVE NETWORKS 5.6.3.1.2 WIRING OF PRIMITIVES 5.7 SUMMARY CHAPTER 5 1 © 1999.1 VHDL Description of A Simple Test Bench 5.2.6 BINDING ALTERNATIVES 5.2 Byte Latch 5. Zainalabedin Navabi .3.3 Byte Comparator 5.4.4.6.2.6 TOP-DOWN WIRING 5.CHAPTER 5 STRUCTURAL SPECIFICATION OF HARDWARE 5.1.2 Simulation 5.

END single_delay. (c) inv i1 o1 (d) • • • • • Inverter Symbol Entity declaration Architecture body Notation. CHAPTER 5 2 © 1999. END inv.Parts Library (a) ENTITY inv IS PORT (i1 : IN BIT. o1 : OUT BIT). Zainalabedin Navabi . (b) ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS.

Zainalabedin Navabi .Parts Library ENTITY inv IS PORT ( entity declaration i1 : IN BIT . interface_signal_declaration interface_signal_declaration port clause • Details of the entity declaration of inverter • Port clause • Interface signal declaration CHAPTER 5 3 © 1999. o1 : OUT BIT ) . END inv.

Parts Library entity_name Interface Aspect Input Port Output Port Bidirectional Port Buffer Port • • • • • CHAPTER 5 Elements of aspect notation Input Output Inout Buffer is output that can be used on RHS 4 © 1999. Zainalabedin Navabi .

Parts Library • Using ports. Outputs. Buffers • Inout implies In and Out (two wires) • Buffer can be used inside an architecture CHAPTER 5 5 © 1999. Zainalabedin Navabi . Bi-directional ports. Inputs.

END nand2. o1 : OUT BIT).Parts Library (a) ENTITY nand2 IS PORT (i1. (b) ARCHITECTURE single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 5 NS. i2 : IN BIT. (c) nand2 i1 i2 (d) o1 • Two-input NAND symbol • Entity declaration • Architecture body uses NAND operator CHAPTER 5 6 © 1999. Zainalabedin Navabi . END single_delay.

o1 : OUT BIT ) identifier_list mode type interface signal declaration port clause interface list interface_signal_declaration • Port clause details for nand2 • Signal declaration includes identifier list • Mode and type are the same as those of the inverter CHAPTER 5 7 © 1999. Zainalabedin Navabi . i2 : IN BIT .Parts Library PORT ( i1.

o1 : OUT BIT).Parts Library (a) ENTITY nand3 IS PORT (i1. (c) i1 i2 i3 nand3 o1 • Three-input NAND symbol • Architecture body and notation are shown • Must use AND and NOT CHAPTER 5 8 © 1999. i2. (b) ARCHITECTURE single_delay OF nand3 IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS. i3 : IN BIT. Zainalabedin Navabi . END nand3. END single_delay.

Wiring Components Comparator A B A>B A=B > = < A<B • Logical symbol of a single bit comparator • Cascadable comparator • Will design one bit and cascade CHAPTER 5 9 © 1999. Zainalabedin Navabi .

b < 0 1 1 00 01 1 1 a<b 1 11 10 • Karnaugh maps for the outputs of the single bit comparator • Each output depends on data inputs and its corresponding control input CHAPTER 5 10 © 1999. Zainalabedin Navabi . b = 0 1 1 a=b 1 00 01 11 10 a.Wiring Components a. b > 0 1 1 1 a>b 00 01 11 10 1 1 a.

gt)’.Wiring Components a_gt_b = a . gt + a . b’ a_eq_b = a . Zainalabedin Navabi . b a_gt_b = ((a . b’)’)’ a_eq_b = ((a .(a’ . lt)’.(b . b)’)’ • Boolean expression for the outputs • Use DeMorgan’s for all-NAND implementation CHAPTER 5 11 © 1999. lt)’.( b’ .( a’ . b’ . lt + b . b . b’ . eq)’. eq + a’ . b . eq a_lt_b = a’ . gt)’. eq)’)’ a_lt_b = ((a’ .( a . gt + b’ . lt + a’ .

Wiring Components a gt a_gt_b b a b eq a_eq_b a a_lt_b lt b • Logic diagram of bit_comparator • Using only our primitive components CHAPTER 5 12 © 1999. Zainalabedin Navabi .

eq.greater -.less than (b) • Interface description of bit_comparator • Inputs and outputs of BIT type are declared CHAPTER 5 13 © 1999. a_gt_b.data inputs -.Wiring Components bit_comparator a b gt eq lt a_gt_b a_eq_b a_lt_b (a) ENTITY bit_comparator IS PORT (a.equal -. Zainalabedin Navabi . -.previous equal -.previous greater than -. gt. a_lt_b : OUT BIT).previous less than -. b. a_eq_b. lt : IN BIT. END bit_comparator.

CHAPTER 5 14 © 1999. Zainalabedin Navabi .Wiring Components bit_comparator (gate_level) a nand2 i1 i2 o1 im3 nand2 i1 i2 o1 im4 i1 i2 i3 nand3 o1 a_gt_b b inv i1 o1 im2 i1 i2 nand2 o1 im5 gt i1 i2 i3 nand3 o1 nand2 nand3 o1 im7 i1 i2 o1 a_eq_b im6 eq lt i1 i2 i3 nand2 i1 i2 o1 im8 inv i1 o1 im1 i1 i2 nand2 o1 im9 i1 i2 i3 nand3 o1 a_lt_b nand2 i1 i2 o1 im10 • Composition Aspect of bit_comparator.

im7. im6).inv (single_delay). -. im4). im7. im3. im4. im5). gt. g1 : n1 PORT MAP (b.a_eq_b output g6 : n3 PORT MAP (im1. im10 : BIT. im3). eq. im9. g3 : n2 PORT MAP (a. i2: IN BIT. a_lt_b). lt. FOR ALL : n3 USE ENTITY WORK. a_eq_b). g2 : n2 PORT MAP (a. im10). gt. END COMPONENT.Intermediate signals SIGNAL im1. im2). g11 : n2 PORT MAP (b.a_lt_b output g9 : n2 PORT MAP (im1. g8 : n2 PORT MAP (im6. FOR ALL : n1 USE ENTITY WORK. im7).Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT. COMPONENT n2 PORT (i1. and PORT MAP • Component declarations are local to the architecture CHAPTER 5 15 © 1999. im6. eq. FOR ALL : n2 USE ENTITY WORK. im4. g4 : n2 PORT MAP (im2.nand3 (single_delay). BEGIN -. im9). o1: OUT BIT). im8).a_gt_b output g0 : n1 PORT MAP (a.im2.nand2 (single_delay). Zainalabedin Navabi . g12 : n3 PORT MAP (im8. • Architecture body of bit_comparator identified as gate_level • Components instantiations constitute the body • Each instantiation has a label. -. END COMPONENT. END COMPONENT. lt. g10 : n2 PORT MAP (im1. g7 : n3 PORT MAP (a. im8. i3: IN BIT. END gate_level. COMPONENT n3 PORT (i1. im9. b. o1: OUT BIT). im10. im1). b. o1: OUT BIT). component name. g5 : n3 PORT MAP (im3. a_gt_b). im5. im2. -. im2. i2. im5.

FOR ALL : n3 USE ENTITY .. im7). eq. SIGNAL im1.. .. END gate_level. b. im3.. component declaration configuration specification architecture declarative part architecture body signal declaration component instantiation statement architecture statement part • Syntax details of the architecture body bit_comparator • Signals in the entity are visible to the architecture of CHAPTER 5 16 © 1999. im5. Zainalabedin Navabi .. BEGIN . im10 : BIT. im2. im4.Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n3 PORT (i1. im6. . im9.. im8.. O1: OUT BIT).. g7 : n3 PORT MAP (a. .. i3: IN BIT. END COMPONENT. im7. i2..

eq. b. instantiation_label component_name component instantiation statement association_list port map aspect • Component instantiation statement syntax details • A label is required • It includes an association list CHAPTER 5 17 © 1999. Zainalabedin Navabi .Wiring Components g7 : n3 PORT MAP ( a. im7 ) .

a_eq_b output g6 : ENTITY WORK.im2. b. g1 : ENTITY WORK. gt. a_gt_b). im7).nand2(single_delay) PORT MAP (im6. im7. g10 : ENTITY WORK. lt. im5. im2. im4).nand2(single_delay) PORT MAP (a.nand2(single_delay) PORT MAP (im1. im5. g2 : ENTITY WORK. im9. g5 : ENTITY WORK. im10 : BIT. im10. im8). g7 : ENTITY WORK. g3 : ENTITY WORK. b. Zainalabedin Navabi .nand3(single_delay) PORT MAP (im8. a_lt_b). im3).nand3(single_delay) PORT MAP (im1. END netlist. -. im6). a_eq_b). im4. eq.nand2(single_delay) PORT MAP (b.nand2(single_delay) PORT MAP (a.Wiring Components ARCHITECTURE netlist OF bit_comparator IS -. im9.nand2(single_delay) PORT MAP (im1. im5). gt. im2).a_gt_b output g0 : ENTITY WORK. lt.inv(single_delay) PORT MAP (a. • Netlist description of bit_comparator • This is direct instantiation • If architecture name is not specified.nand3(single_delay) PORT MAP (a. im3. im9).nand3(single_delay) PORT MAP (im3. g8 : ENTITY WORK.nand2(single_delay) PORT MAP (im2. im1). the most recently compiled architecture will be used CHAPTER 5 18 © 1999. g12 : ENTITY WORK. im8. eq. im2.Intermediate signals SIGNAL im1.inv(single_delay) PORT MAP (b. im10). -. im6. im4. im7. g4 : ENTITY WORK. g11 : ENTITY WORK. BEGIN -.a_lt_b output g9 : ENTITY WORK.

Zainalabedin Navabi .Wiring Components • bit_comparator simulation run • keeping control inputs at 010 CHAPTER 5 19 © 1999.

Zainalabedin Navabi .Wiring Iterative Networks 4 Data inputs 4 Four Bit Comparator A B A>B A=B Compare outputs Control inputs > = < A<B • Logical symbol of a 4-bit comparator • Same configuration as that of the one-bit comparator • This is similar to the 74LS85 magnitude comparator CHAPTER 5 20 © 1999.

Wiring Iterative Networks B3 A3 Comparator A B 3 > = < A>B A=B A<B B2 A2 Comparator A B 2 > = < A>B A=B A<B B1 A1 Comparator A B 1 > = < A>B A=B A<B B0 A0 Comparator A B 0 > = < A>B A=B A<B A>B A=B A<B < = > • A 4-bit comparator using four single bit comparators • Numbers different in MSB. Zainalabedin Navabi . produce results faster • Worst case delay for equal inputs CHAPTER 5 21 © 1999.

• Interface description of nibble_comparator.-.previous less than a_gt_b.Wiring Iterative Networks nibble_comparator a(3:0) a_gt_b b(3:0) gt eq lt a_eq_b a_lt_b (a) ENTITY nibble_comparator IS PORT (a. -. -.a < b END nibble_comparator. -. (b) entity declaration • Inputs of of BIT_VECTOR type • Can use any range (a) CHAPTER 5 22 © 1999. -.previous equal lt : IN BIT.a > b a_eq_b.a = b a_lt_b : OUT BIT). interface aspect. -. Zainalabedin Navabi .previous greater than eq.a and b data inputs gt. b : IN BIT_VECTOR (3 DOWNTO 0). -.

Zainalabedin Navabi .Wiring Iterative Networks nibble_comparator(iterative) a(3:0) b(3:0) a(3) b(3) bit_comparator a (gate_level) Bit 3 b gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a(2) b(2) bit_comparator a (gate_level) Bit 2 b gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) bit_comparator a (gate_level) Bit 1 b gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) bit_comparator a (gate_level) Bit 0 b gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect of nibble_comparator CHAPTER 5 23 © 1999.

a_lt_b : OUT BIT). lt : IN BIT. im(i*3+0). END GENERATE. lt. Zainalabedin Navabi . b. im(7). im(i*3-3). END COMPONENT. a_eq_b. b(3). im(1). im(i*3-1). gt. im(0). • Iterative architecture of nibble_comparator • Uses nested generate statements • Can easily expand by changing numbers CHAPTER 5 24 © 1999. gt. b(i). im(2)). SIGNAL im : BIT_VECTOR ( 0 TO 8). c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). a_gt_b. a_gt_b. b(0). a_eq_b. im(i*3+2) ).Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. a_lt_b). BEGIN c0: comp1 PORT MAP (a(0). im(6). im(i*3-2). FOR ALL : comp1 USE ENTITY WORK. eq.bit_comparator (gate_level). im(i*3+1). END iterative. c3: comp1 PORT MAP (a(3). im(8). eq.

im(i*3-3). im(3). im(i*3-1). im(1). im(4). im(0). im(5) ) • Association list of c instance of comp1 within generate statement • Bit 1 is configured for i value of 1 CHAPTER 5 25 © 1999. im(i*3+0). im(i*3+2) ) i=1 i=1 i=1 i=1 i=1 i=1 i=1 i=1 PORT MAP (a(1).Wiring Iterative Networks PORT MAP (a(i). b(1). Zainalabedin Navabi . im(i*3+1). b(i). im(i*3-2). im(2).

im(i*3-1). im(i*3+1). im(i*3+0). b(i). generate_label generation_scheme generate statement concurrent_statement • • • • Generate statement syntax details This is a concurrent statement The body of a generate statement is concurrent Can use FOR or IF generation scheme CHAPTER 5 26 © 1999. im(i*3-2). im(i*3+2)). im(i*3-3). END GENERATE . Zainalabedin Navabi .Wiring Iterative Networks c1to2 : FOR i IN 1 TO 2 GENERATE c: COMP1 PORT MAP (a(i).

b(i). Zainalabedin Navabi . im(i*3+2) ). use unconstrained arrays.Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. im(i*3-3). im(0). END GENERATE. END GENERATE. • A more flexible iterative architecture of nibble_comparator • Constant n sizes the comparator • There is still a better way.bit_comparator (gate_level). im(i*3+0). CONSTANT n : INTEGER := 4. eq. BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). gt. im(1). im(i*3+1). im(i*3-2). END GENERATE. b(i). lt. b. eq. FOR ALL : comp1 USE ENTITY WORK. END GENERATE. m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). im(2) ). im(i*3-1). a_gt_b. a_eq_b. im(i*3-1). lt : IN BIT. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). gt. END iterative. a_eq_b. b(i). END COMPONENT. a_lt_b : OUT BIT). a_gt_b. SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). CHAPTER 5 27 © 1999. Chap 7. im(i*3-2). im(i*3-3). a_lt_b).

im(1). im(0). lt. END GENERATE. b(i). Zainalabedin Navabi .Wiring Iterative Networks l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK. gt. im(2) ). BEGIN least: comp1 PORT MAP (a(i). • Configuration specifications create some ambiguities • Problem is corrected by Generate Statement Declarative Part • Binding indication appears here CHAPTER 5 28 © 1999. eq.bit_comparator (gate_level).

Modeling a Test Bench test_bench (input_output) nibble_comparator (iterative) a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • A test bench for nibble_comparator. Zainalabedin Navabi . the composition aspect • A test bench does not use ports • All signals used must be explicitly declared CHAPTER 5 29 © 1999.

a < b (worst case) "1110" AFTER 2500 NS. lss). best case) a3 : b <= "0000".a < b (need bit 3 only.a > b (worst case) "1110" AFTER 1500 NS. vdd.a = b (worst case) "1111" AFTER 6000 NS. -. b. -. -. a_eq_b_out. -. SIGNAL gnd : BIT := '0'. -.a < b (steady state.a = b (worst case) "0000" AFTER 5000 NS. END COMPONENT. -. -. gtr : BIT. FOR a1 : comp4 USE ENTITY WORK. Zainalabedin Navabi .a > b (need bit 3 only. best case) END input_output.a > b (need bit 1 info) "1100" AFTER 3500 NS. CHAPTER 5 30 iterative architecture of © 1999. -. gnd. gtr. -. a_eq_b. lss. gnd. -. ---. BEGIN a1: comp4 PORT MAP (a. -. -ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a. eql. SIGNAL eql. -. -. -. a_gt_b_out. SIGNAL vdd : BIT := '1'.a = b (worst case) "1111" AFTER 5000 NS. a_lt_b : IN BIT.a > b (need bit 3 only. a_gt_b.a = b (steady state) "1110" AFTER 0500 NS.a = b (worst case) "0000" AFTER 6000 NS.a < b (steady state. a_lt_b_out : OUT BIT).Modeling a Test Bench ENTITY nibble_comparator_test_bench IS END nibble_comparator_test_bench .a < b (worst case) "1100" AFTER 2500 NS.a < b (need bit 3 only. b : IN bit_vector (3 DOWNTO 0). b : BIT_VECTOR (3 DOWNTO 0). a2: a <= "0000".nibble_comparator(iterative).a > b (worst case) "1111" AFTER 1500 NS.a < b (need bit 2 info) "1111" AFTER 4000 NS. -. best case) "0000" AFTER 5500 NS.a < b (need bit 2 info) "0000" AFTER 4000 NS. prepare for next) "1111" AFTER 4500 NS. prepare for next) "1111" AFTER 4500 NS. • Test bench for nibble_comparator. SIGNAL a. ---. best case) "0000" AFTER 5500 NS. -. -.a = b (steady state) "1111" AFTER 0500 NS.a > b (need bit 1 info) "1010" AFTER 3500 NS. -.

. . "1111" ..... '1' ..... '0' ....... ...... .. .... ... Zainalabedin Navabi ... .... . ...... ... '0' ......... ... . . .. "0000" .......... ........... . ...... '0' lss '0' .. SIGNALS b(3:0) gtr "0000" .. '0' ... .. . ........ "1100" .. ... ......Modeling a Test Bench TIME (NS) 0 5 500 544 548 1500 1544 1548 2500 2533 2537 3500 3522 3526 4000 4500 4544 4548 5000 5011 5015 5500 5544 5548 6000 6011 6015 a(3:0) "0000" .. '0' ... '0' ................... "1010" ................... .. ... . . .. ..... ...... . .. .. .. "1110" . .. '0' .. .. '0' .... "1111" ...... "1110" .. .................. ......... .. '1' ......... .... .... "1111" ... ..... .. '1' ..... '1' . .. .. .... .... ...... ........ "1111" . .... ........ . ........ ... .. eql '0' '1' ... .. "0000" . . ... . . • Simulation report for simulating iterative comparator test bench • All events are observed CHAPTER 5 31 © 1999. . '1' . '1' . ........... .. ............ ......... '0' ............. ....... ... ..... '1' . ....... '1' .... ... "0000" "1111" .. ..

Zainalabedin Navabi CHAPTER 5 .Binding Alternatives C S 1 3 Q R 2 4 • • • • Logical diagram of a simple latch With equal timing this will not work Will use this example for showing binding alternatives Correct the oscillation problem by binding to NAND gates of different delay values 32 © 1999.

im2. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im2.nand2 (single_delay). END gate_level. c : IN BIT. END COMPONENT. im1). g2 : n2 PORT MAP (r. i2: IN BIT. im4. Zainalabedin Navabi . g4 : n2 PORT MAP (im3. q : OUT BIT). im3). im4). im2). SIGNAL im1. BEGIN g1 : n2 PORT MAP (s. q <= im3. g3 : n2 PORT MAP (im1. c.Binding Alternatives ENTITY sr_latch IS PORT (s. FOR ALL : n2 USE ENTITY WORK. c. o1: OUT BIT). END sr_latch. r. • • • • VHDL description of set-reset latch This is using the 2-input NAND for all four instances Signal assignment avoids use of Buffer The single_delay architecture is used CHAPTER 5 33 © 1999. im3. im4 : BIT.

FOR ALL : n2 USE ENTITY WORK. END COMPONENT. im4). im4. q). im4 : BIT. Zainalabedin Navabi . i2: IN BIT. c. g3 : n2 PORT MAP (im1. c.nand2 (single_delay). BEGIN g1 : n2 PORT MAP (s. g2 : n2 PORT MAP (r.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. END gate_level. im2). • sr_latch (gate_level) architecture using BUFFER • componet declaration and the actual entity must match is PORT MAP is not used with the configuration specification • The 2-input NAND must change to use BUFFER instead of OUT CHAPTER 5 34 © 1999. im2. im1). im2. o1: BUFFER BIT). g4 : n2 PORT MAP (q. SIGNAL im1.

Zainalabedin Navabi . • • • • A faster NAND gate The gate delay is 3 NS Uses the same entity as the single_delay NAND Using this NAND corrects the oscillation problem CHAPTER 5 35 © 1999.Binding Alternatives ARCHITECTURE fast_single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 3 NS. END fast_single_delay.

Binding Alternatives c s i1 i2 (fast_single_delay) sr_latch (gate_level) nand2 g1: im1 (fast_single_delay) nand2 g3: o1 i1 i2 o1 im3 q r i1 i2 (single_delay) nand2 g2: o1 im2 i1 i2 (single_delay) nand2 g4: o1 im4 (a) • SR-latch. composition aspect • Same wiring as the latch that oscillates CHAPTER 5 36 © 1999. using gates with different delays. Zainalabedin Navabi .

FOR g1. im4). c. g3 : n2 USE ENTITY WORK. BEGIN g1 : n2 PORT MAP (s. im3.nand2 (single_delay). Zainalabedin Navabi .Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1.nand2 (fast_single_delay). im1). im3). q <= im3. im2. g3 : n2 PORT MAP (im1. architecture body • Same wiring. o1: OUT BIT). using gates with different delays. i2: IN BIT. im2. c. • SR-latch. FOR g2. END gate_level. im4. im2). im4 : BIT. g2 : n2 PORT MAP (r. g4 : n2 PORT MAP (im3. SIGNAL im1. different binding • Fast_single_delay architecture is used for g1 and g3 CHAPTER 5 37 © 1999. g4 : n2 USE ENTITY WORK. END COMPONENT.

Binding Alternatives c s i1 i2 (single_delay) sr_latch (gate_level) nand2 g1: im1 nand2 g3: q o1 i1 i2 (single_delay) o1 im3 r i1 i2 i3 nand3 (single_delay) o1 g2: im2 i1 i2 i3 (single_delay) nand3 im4 o1 g4: (a) • SR-latch. composition aspect • This solution uses 3-input NAND gates • The 3-input gates have different delay values than the 2-input NAND gates CHAPTER 5 38 © 1999. Zainalabedin Navabi . using nand2 and nand3 gates.

using nand2 and nand3 gates. x. x. z). g3 : n2 PORT MAP (im1. g2 : n2 PORT MAP (r. y. y. END gate_level. g4 : n2 PORT MAP (im3. ALTERNATIVELY: FOR g1. Zainalabedin Navabi . y. c.nand3 (single_delay) PORT MAP (x. z: OUT BIT). FOR g2. im2. im4 : BIT. END COMPONENT. FOR OTHERS : n2 USE ENTITY WORK.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x. SIGNAL im1. z). im2). z). im4.nand2 (single_delay) PORT MAP (x. c. g4 : n2 USE ENTITY WORK. FOR g1. y. • SR-latch. im3). g3 : n2 USE ENTITY WORK. z).nand3 (single_delay) PORT MAP (x. overrides the default • Could use OTHERS CHAPTER 5 39 © 1999. y: IN BIT. im2. q <= im3. im1).nand2 (single_delay) PORT MAP (x. architecture • Configuration specification takes caring of wiring the 3-input NAND into a 2-input NAND • PORT MAP in binding. im4). im3. BEGIN g1 : n2 PORT MAP (s. g3 : n2 USE ENTITY WORK.

Binding Alternatives Signals of gate_level of sr_latch r c im2 Port map association of instantiation statement Local ports of g2 instance of n2 x y z Port map association of configuration specification Formal ports of nand3 in1 in2 in3 o1 • Two-step association • Declaration is local • Names in declaration are used only when not specified in a configuration specification CHAPTER 5 40 © 1999. Zainalabedin Navabi .

instantiation_list component_name component specification entity aspect binding indication port map aspect configuration specification • Configuration specification syntax details • Binding indication contains entity aspect.Binding Alternatives FOR g1. port map aspect. g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x. y. z) . those of the declaration will be used • Declarations are still needed unless direct instantiations are used CHAPTER 5 41 © 1999. and generic map aspect • If not specified. Zainalabedin Navabi .

Top-Down Wiring

old_new_comparator byte_comparator i di byte_latch con1 clk clk a b gt eq lt a_gt_b a_eq_b a_lt_b

• Will develop a complete example, compare old and new data, keep a count • Defaults will be used • Most recently compiled architectures are used in the absence of configuration specifications • Composition aspect of old_new_comparator
CHAPTER 5 42 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT); END old_new_comparator; -ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparator PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN); END wiring;

• • • • •
CHAPTER 5

old_new_comparator VHDL description Declarations are present Configuration specifications are missing Use OPEN for unconnected outputs OPEN inputs must have a default value
43 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0)); END byte_latch; -ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE; END iterative;

• • • •

An 8-bit latch is required for this design Use a configurable description based on D-type latch VHDL description of byte_latch. Iterative architecture is used

CHAPTER 5

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© 1999, Zainalabedin Navabi

Top-Down Wiring

c d inv i1 o1

sr_latch C S q q

R

(a)

• Build a D-latch using our sr_latch and an inverter • Composition aspect is shown

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Top-Down Wiring

ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT; BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar); END sr_based; (b)

• Design of d_latch, VHDL description • Configuration specifications are not used • Local declarations are used for ports and name of the actual entity

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Top-Down Wiring

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );

END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;

• Another necessary component for this design is an 8bit comparator • Byte comparator VHDL description • Uses 8 instances of bit_comparator • Constant n is changed to 8 • Default architectures are used
CHAPTER 5 47 © 1999, Zainalabedin Navabi

Top-Down Wiring
A structural description for a design consists of a wiring specification of its subcomponents. In this chapter, the

definition and usage of components in larger designs was illustrated. Generate statements also were introduced as a convenient way to describe repetitive hardware structures and a notation was defined for graphical representation of structural descriptions. In addition, various forms and

options in component declarations and configuration specifications were discussed. The last part of this chapter presented a top-down design using basic gates and components presented in the earlier sections. Using simple gates, the reader should now be able to design larger digital circuits with many levels of component nesting.

• End Of Chapter 5

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CHAPTER 6 DESIGN ORGANIZATION AND PARAMETERIZATION

6.1 DEFINITION AND USAGE OF SUBPROGRAMS 6.1.1 A Functional Single Bit Comparator 6.1.2 Using Procedures in a Test Bench 6.1.3 Language Aspects of Subprograms 6.1.4 Utility Procedures 6.2 PACKAGING PARTS AND UTILITIES 6.2.1 Packaging Components 6.2.2 Packaging Subprograms 6.3 DESIGN PARAMETRIZATION 6.3.1 Using Default Values 6.3.2 Using Fixed Values 6.3.3 Passing Generic Parameters 6.4 DESIGN CONFIGURATION 6.4.1 A General Purpose Test Bench 6.4.2 Configuring Nested Components 6.4.3 Incremental Binding 6.4.4 An n-bit Register Example 6.4.5 Iterative Parity Checking 6.5 DESIGN LIBRARIES 6.5.1 Existing Libraries 6.5.2 Library Management 6.6 SUMMARY

CHAPTER 6

1

© 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

GT Equation EQ Equation LT Equation

a_gt_b = a . gt + b' . gt + a . b' a_eq_b = a . b . eq + a' . b' . eq a_lt_b = b . lt + a' . lt + b . a'

ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;

An architecture for demonstrating use of subprograms

• Demonstrating the use of functions • Use functions in place of Bololean expresssions • A functional bit_comparator, using the same function for two outputs
CHAPTER 6 2 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

FUNCTION fgl ( w, x, g1 :BIT) RETURN BIT IS BEGIN RETURN (w AND g1) OR (NOT x AND g1) OR (w AND NOT x) ; END;

designator formal_parameter_list type_mark subprogram body expression return statement sequential statement subprogram statement part subprogram specification

• Function body is sequential • Use functions for utilities and coding style • Syntax details of a subprogram body, a general view
CHAPTER 6 3 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END structural;

• Using the functional bit_comparator • Structural architecture of a nibble_comparator

CHAPTER 6

4

© 1999, Zainalabedin Navabi

END IF. gnd. eq. ELSE buf (j) := '0'. CONSTANT values : IN integers. gtr : BIT. FOR a1 : comp4 USE ENTITY WORK. lss).Definition and Usage of Subprograms ARCHITECTURE procedural OF nibble_comparator_test_bench IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. SIGNAL eql. BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i). lt : IN BIT. VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). apply_data (b. lss. tmp := tmp / 2. 00&15&15&14&14&14&14&10&00&15&00&00&15. a_gt_b. b : IN bit_vector (3 DOWNTO 0). j := 0. Zainalabedin Navabi . CONSTANT period : IN TIME) IS VARIABLE j : INTEGER. PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). gnd. END apply_data. a_lt_b : OUT BIT). 500 NS). END procedural. gtr. SIGNAL a. eql. SIGNAL gnd : BIT := '0'. vdd. pos : INTEGER := 0. apply_data (a. • Defining and using a procedure • Procedural architecture of nibble_comparator • INTEGERS type is an array of 13 integers CHAPTER 6 5 © 1999. END LOOP. target <= TRANSPORT buf AFTER i * period. VARIABLE tmp. END COMPONENT. WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'. 500 NS). COMPONENT comp4 PORT (a. b. b : BIT_VECTOR (3 DOWNTO 0). a_eq_b. gt. 00&14&14&15&15&12&12&12&15&15&15&00&00.nibble_comparator(structural). j := j + 1. END LOOP. BEGIN a1: comp4 PORT MAP (a. SIGNAL vdd : BIT := '1'.

.. '1' .... "1110" .. '0' ......... • Simulation report resulting from the procedural test bench • All events are observed • Shows increments of 12 NS only CHAPTER 6 6 © 1999.. "1111" ..... Zainalabedin Navabi ............ ...... '0' . .. ... . .... ... .... . '0' . ............... "1111" .... "1100" .. .......... '1' ... . '1' ....... .. . '0' . '0' .... SIGNALS b(3:0) gtr "0000" ... . ... ..... ............... "1010" ... '1' .. "0000" "1111" ..... ..... '1' .. . ..... ............ "0000" ..... . "1111" ... ... "1110" .... '0' .................. ....... '0' .. .Definition and Usage of Subprograms TIME (NS) 0 48 500 548 1500 1548 2500 2536 3500 3524 4000 4500 4548 5000 5012 5500 5548 6000 6012 a(3:0) "0000" .... ....... "1111" ... '0' . '1' .. . ... "0000" ..... . '1' eql '0' '1' . ... '1' ...... '0' lss '0' . .

Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). END LOOP. . . VARIABLE buf: BIT_VECTOR (3 DOWNTO 0). FOR i IN 0 TO 12 LOOP . Zainalabedin Navabi . END apply_data. BEGIN. VARIABLE tmp : INTEGER := 0. subprogram specification formal parameter list subprogram declarative part subprogram body loop statement sequential statement subprogram statement part • • • • CHAPTER 6 Details of a subprogram body Function or procedure subprogram specification Subprograms are procedural bodies Nested procedural statements 7 © 1999. CONSTANT period : IN TIME ) IS VARIABLE j : INTEGER. CONSTANT values : IN integers.

Zainalabedin Navabi . .Definition and Usage of Subprograms FOR i IN 0 TO 12 LOOP . . loop parameter specification iteration scheme loop_statement sequence_of_statement • • • • CHAPTER 6 Loops are procedural Loop statement with FOR iteration scheme Can nest procedural statements Sequence_of_statements is the sequential construct 8 © 1999. END LOOP.

END IF. Zainalabedin Navabi . condition if_statement sequence_of_statements sequence_of_statements • Details of the If statement of apply_data procedure • This is a procedural statement • Sequence_of_statements is the sequential construct CHAPTER 6 9 © 1999.Definition and Usage of Subprograms IF (tmp MOD 2 = 1) THEN buf (j) := ’1’. ELSE buf (j) := ‘0’.

BEGIN result := 0. int : OUT INTEGER) IS VARIABLE result: INTEGER. int := result. END bin2int. END IF. • Can do utility procedures • ‘RANGE attribute makes this a generic procedure • Procedure for binary to integer conversion CHAPTER 6 10 © 1999. Zainalabedin Navabi . FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END LOOP.Definition and Usage of Subprograms PROCEDURE bin2int (bin : IN BIT_VECTOR.

1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. END LOOP. ELSE bin (i) := '0'. END int2bin. FOR i IN 0 TO (bin'LENGTH . END IF. • Another utility procedure • Procedure for integer to binary conversion • ‘LENGTH attribute is used here CHAPTER 6 11 © 1999. tmp := tmp / 2. BEGIN tmp := int.Definition and Usage of Subprograms PROCEDURE int2bin (int : IN INTEGER. Zainalabedin Navabi . bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER.

target <= TRANSPORT buf AFTER i * period. END LOOP. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). CONSTANT values : IN integers.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). Zainalabedin Navabi . END apply_data. • • • • CHAPTER 6 Can use procedures within procedure Another version of apply_data procedure This version takes advantage of the int2bin procedure TRASPORT delay schedules all transactions at time 0 12 © 1999. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). buf).

FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i.Definition and Usage of Subprograms FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. Zainalabedin Navabi . END to_integer. otherwise it is a generic function CHAPTER 6 13 © 1999. BEGIN result := 0. RETURN result. END LOOP. END IF. • Functions can serve as utilities • Binary to integer conversion function • Assumes lower bound of 0.

Packaging components PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT. END COMPONENT. END simple_gates. i2. END COMPONENT. Demonstrating specification and usage of packages • Component declarations as well as utilities can be packaged • A package declaration containing component declarations of simple gates • Eliminates the need for individual declarations CHAPTER 6 14 © 1999. o1: OUT BIT). Zainalabedin Navabi .Packaging Parts and Utilities -. COMPONENT n2 PORT (i1: i2: IN BIT. COMPONENT n3 PORT (i1. o1: OUT BIT). i3: IN BIT. END COMPONENT. o1: OUT BIT).

im8). g3 : n2 PORT MAP (a. im1). lt. im7. im4). END gate_level.nand3 (single_delay). a_lt_b). im7). im3. lt. im9. im4.a_lt_b output g9 : n2 PORT MAP (im1. im5. im9). b. im6. im7. FOR ALL : n2 USE ENTITY WORK. im2. g2 : n2 PORT MAP (a. a_gt_b). ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK. -. im10). same configuration CHAPTER 6 15 © 1999.a_gt_b output g0 : n1 PORT MAP (a. -.simple_gates.im2. im2). BEGIN -. im2. • Using package of simple gates in gate_level of bit_comparator • This becomes our local declarations • Same naming rules as before. g10 : n2 PORT MAP (im1. eq.Intermediate signals SIGNAL im1. im4. g7 : n3 PORT MAP (a. Zainalabedin Navabi .Packaging Parts and Utilities USE WORK. im6). FOR ALL : n3 USE ENTITY WORK. -. b. a_eq_b). g5 : n3 PORT MAP (im3. im10 : BIT. im10. g4 : n2 PORT MAP (im2.inv (single_delay). g11 : n2 PORT MAP (b. im3). g12 : n3 PORT MAP (im8.a_eq_b output g6 : n3 PORT MAP (im1. im8. gt. im5).ALL. gt. eq.nand2 (single_delay). g1 : n1 PORT MAP (b. im9. g8 : n2 PORT MAP (im6. im5.

n2 and n3 component declarations are visible .Packaging Parts and Utilities USE WORK.n2. Zainalabedin Navabi . WORK.n3. WORK.n1.n1. -.simple_gates. • An alternative application of the use clause • Can select only those needed CHAPTER 6 16 © 1999.simple_gates.simple_gates. .

Packaging Parts and Utilities PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. x. CONSTANT values : IN integers. END basic_utilities. FUNCTION feq (w. eq : BIT) RETURN BIT. gl : BIT) RETURN BIT. CONSTANT period : IN TIME). bin : OUT BIT_VECTOR). PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). x. int : OUT INTEGER). FUNCTION fgl (w. Zainalabedin Navabi . PROCEDURE int2bin (int : IN INTEGER. • The basic_utilities package declaration • Packaging subprograms replaces their declaration • Types and declarations become visible to architectures CHAPTER 6 17 © 1999. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER. PROCEDURE bin2int (bin : IN BIT_VECTOR.

eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq). x. • Package body includes body of procedures • The basic_utilities package body • Will use this package in all our examples CHAPTER 6 18 © 1999. tmp := tmp / 2. END bin2int. ELSE bin (i) := '0'. int : OUT INTEGER) IS VARIABLE result: INTEGER. gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x). Zainalabedin Navabi . END feq.1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. PROCEDURE int2bin (int : IN INTEGER. END LOOP. END int2bin. END IF. END fgl. VARIABLE buf : BIT_VECTOR (bin'RANGE). FUNCTION feq (w. int := result.Packaging Parts and Utilities PACKAGE BODY basic_utilities IS FUNCTION fgl (w. BEGIN tmp := int. FOR i IN 0 TO (bin'LENGTH . x. PROCEDURE bin2int (bin : IN BIT_VECTOR. END IF. bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. END LOOP. BEGIN result := 0.

RETURN result. END apply_data. BEGIN result := 0. END basic_utilities. END LOOP. buf).Packaging Parts and Utilities PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). • Continuation of the basic_utilities package body • New declarations in this body are visible to this body only CHAPTER 6 19 © 1999. CONSTANT values : IN integers. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. Zainalabedin Navabi . END IF. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). target <= TRANSPORT buf AFTER i * period. END LOOP. END to_integer. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i.

basic_utilities. b. lt) AFTER 12 NS. Zainalabedin Navabi CHAPTER 6 20 . a_eq_b <= feq (a. ARCHITECTURE functional OF bit_comparator IS BEGIN a_gt_b <= fgl (a.Packaging Parts and Utilities USE WORK. • Using functions of the basic_utilities package • Architecture need not include function body • The USE statement handles visibility © 1999. END functional. a. eq) AFTER 12 NS. a_lt_b <= fgl (b.ALL. b. gt) AFTER 12 NS.

15.basic_utilities. eq. a_gt_b.00. a_eq_b.14. ALTERNATIVELY: apply_data (a. b. gtr : BIT.15. SIGNAL eql. SIGNAL a. gnd. vdd.15). 500 NS).00. 500 NS). 500 NS). lss.15. apply_data (b.12.14. gnd. SIGNAL vdd : BIT := '1'. ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a.12.15.15. END procedural.ALL.14. lt : IN BIT.00. gt. Zainalabedin Navabi .00).nibble_comparator(structural).12. apply_data (b. SIGNAL gnd : BIT := '0'. FOR a1 : comp4 USE ENTITY WORK. (00.15.14. eql. b : BIT_VECTOR (3 DOWNTO 0). (00.15.Packaging Parts and Utilities USE WORK. END COMPONENT.14.10. BEGIN a1: comp4 PORT MAP (a. a_lt_b : OUT BIT). apply_data (a. lss).15. b : IN bit_vector (3 DOWNTO 0). 500 NS). 0&15&15&14&14&14&14&10&00&15&00&00&15. gtr. 0&14&14&15&15&12&12&12&15&15&15&00&00.00.14. • • • • CHAPTER 6 Using procedures of the basic_utilities package Concatenate to form 13 integers Can also use aggregate operation Aggregate for elements of the array only 21 © 1999.

o1 : OUT BIT).Design Parametrization ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. Architecture for demonstrating specification and definition of parameters • Start design parameterization examples with same simple structures CHAPTER 6 22 © 1999. PORT (i1 : IN BIT. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. Zainalabedin Navabi . tphl : TIME := 3 NS). END average_delay. END inv_t.

i3 : IN BIT. declares objects of type constant © 1999. o1 : OUT BIT). tphl : TIME := 4 NS). PORT (i1. • Parametrized gate models • GENERIC is used. END average_delay. -ARCHITECTURE average_delay OF nand3_t IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2. i2 : IN BIT. -ARCHITECTURE average_delay OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. END average_delay. Zainalabedin Navabi CHAPTER 6 23 . tphl : TIME := 5 NS). PORT (i1. END nand3_t. ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS. END nand2_t.Design Parametrization ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. o1 : OUT BIT). i2.

interface constant declaration entity declaration interface constant declaration (generic) interface list (formal) generic clause entity header (formal) port clause • Details of the entity declaration of inverter with generics • Using a default value is helpful but not required • Generic clause comes before port clause CHAPTER 6 24 © 1999.Design Parametrization ENTITY inv_t IS GENERIC ( tplh : TIME := 5 NS . Zainalabedin Navabi . o1 : OUT BIT). END inv_t. tphl : TIME := 3 NS ). PORT (i1 : IN BIT.

Design Parametrization inv_t i1 tplh o1 tphl nand2_t i1 o1 i2 tphl tplh i1 nand3_t o1 i2 i3tplh tphl • Interface aspects of inv_t. nand2_t. Zainalabedin Navabi . and nand3_t • Graphical representation with generics • Port association and generic association must be done when used CHAPTER 6 25 © 1999.

im3. Zainalabedin Navabi CHAPTER 6 26 . im3). a_gt_b). im4. im5. -. g1 : n1 PORT MAP (b. b. g7 : n3 PORT MAP (a. g5 : n3 PORT MAP (im3. o1: OUT BIT).nand2_t (average_delay).nand3_t (average_delay). i3: IN BIT. -. FOR ALL : n2 USE ENTITY WORK. im4). im2). im2.Intermediate signals SIGNAL im1. im8). g8 : n2 PORT MAP (im6. COMPONENT n2 PORT (i1. END COMPONENT. g3 : n2 PORT MAP (a. lt. BEGIN -. o1: OUT BIT). im7.im2. END COMPONENT. g4 : n2 PORT MAP (im2. im9). im8. g12 : n3 PORT MAP (im8.a_lt_b output g9 : n2 PORT MAP (im1. g10 : n2 PORT MAP (im1. FOR ALL : n3 USE ENTITY WORK. im7). im10). lt. gt. END COMPONENT. END default_delay. -. im9. im7.Design Parametrization ARCHITECTURE default_delay OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT.a_eq_b output g6 : n3 PORT MAP (im1. a_lt_b). g2 : n2 PORT MAP (a. b.inv_t (average_delay). • Many alternatives for specifying generics • Using default values for the generics of logic gates • No need to declare and specify generics if they are to use default values © 1999. g11 : n2 PORT MAP (b.a_gt_b output g0 : n1 PORT MAP (a. eq. im10 : BIT. gt. im4. im9. o1: OUT BIT). i2: IN BIT. a_eq_b). im6). i2. im10. im5). eq. im1). COMPONENT n3 PORT (i1. FOR ALL : n1 USE ENTITY WORK. im2. im5. im6.

lt. COMPONENT n2 GENERIC (tplh. a_gt_b). g7 : n3 GENERIC MAP (4 NS. im1). im4). im9. im5. g3 : n2 GENERIC MAP (3 NS. BEGIN -. b. 6 NS) PORT MAP (im1. gt. im3. im2. tphl : TIME). • If generics are declared without default values. PORT (i1: IN BIT. END COMPONENT. they have to be specified • Associating fixed values with the generics of logic gates • Generic map is shown here CHAPTER 6 27 © 1999. -. -. g1 : n1 GENERIC MAP (2 NS. o1: OUT BIT). FOR ALL : n1 USE ENTITY WORK. g2 : n2 GENERIC MAP (3 NS. 6 NS) PORT MAP (a. 5 NS) PORT MAP (a.Design Parametrization ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh. Zainalabedin Navabi .nand3_t (average_delay). lt.im2. tphl : TIME). i3: IN BIT. g11 : n2 GENERIC MAP (3 NS. g10 : n2 GENERIC MAP (3 NS.a_gt_b output g0 : n1 GENERIC MAP (2 NS. 5 NS) PORT MAP (im1. PORT (i1. i2. END fixed_delay. 6 NS) PORT MAP (im8. 5 NS) PORT MAP (im2. i2: IN BIT. im7. im7. g5 : n3 GENERIC MAP (4 NS. im8). 6 NS) PORT MAP (im3. 5 NS) PORT MAP (im1. im8. 4 NS) PORT MAP (a. 5 NS) PORT MAP (b. g12 : n3 GENERIC MAP (4 NS. tphl : TIME).a_lt_b output g9 : n2 GENERIC MAP (3 NS. b. im5. im9. im6). eq.inv_t (average_delay). gt. im10.a_eq_b output g6 : n3 GENERIC MAP (4 NS. im7). im3). im9). im6. 5 NS) PORT MAP (im6. SIGNAL im1. im5). im10 : BIT. 5 NS) PORT MAP (a. im4. eq. a_lt_b). im4. im10). im2.nand2_t (average_delay). im2). 4 NS) PORT MAP (b. FOR ALL : n2 USE ENTITY WORK. COMPONENT n3 GENERIC (tplh. PORT (i1. g4 : n2 GENERIC MAP (3 NS. o1: OUT BIT). o1: OUT BIT). FOR ALL : n3 USE ENTITY WORK. a_eq_b). END COMPONENT. g8 : n2 GENERIC MAP (3 NS. END COMPONENT.

im2 ) . Zainalabedin Navabi .Design Parametrization g1 : n1 GENERIC MAP ( 2 NS. 4 NS ) PORT MAP ( b. instantiation_label component_name generic map aspect port map aspect association_list component instantiation statement association_list • Syntax details • Component instantiation statement with generic map aspect • Generic map aspect comes first CHAPTER 6 28 © 1999.

• A bit comparator with timing parameters • Passing generics of bit comparator to its components • Bit comparator has generic parameters that must be passed to it CHAPTER 6 29 © 1999. im9.nand2_t (average_delay). tphl : TIME). o1: OUT BIT). tphl2. FOR ALL : n2 USE ENTITY WORK. PORT (i1. FOR ALL : n1 USE ENTITY WORK. -. b.data inputs gt. im5.less than END bit_comparator_t. -. -.im2. -. PORT (a. i2: IN BIT. COMPONENT n3 GENERIC (tplh. tphl : TIME). END COMPONENT. o1: OUT BIT). END COMPONENT.equal a_lt_b : OUT BIT).inv_t (average_delay).previous equal lt : IN BIT. tphl3 : TIME). COMPONENT n2 GENERIC (tplh. tplh2. -.nand3_t (average_delay).. (a) ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh. im8.previous greater than eq. tphl : TIME). tplh3. -. END COMPONENT. Zainalabedin Navabi . PORT (i1: IN BIT. BEGIN . tphl1.Intermediate signals SIGNAL im1. o1: OUT BIT). PORT (i1. im3. i3: IN BIT. i2. -..Design Parametrization ENTITY bit_comparator_t IS GENERIC (tplh1. im10 : BIT.greater a_eq_b. im4.previous less than a_gt_b. FOR ALL : n3 USE ENTITY WORK. im7. -. im6.

tphl3) PORT MAP (a. im10. g5 : n3 GENERIC MAP (tplh3. im3). im1).a_eq_b output g6 : n3 GENERIC MAP (tplh3. a_lt_b).a_lt_b output g9 : n2 GENERIC MAP (tplh2. g4 : n2 GENERIC MAP (tplh2. b. Zainalabedin Navabi . g12 : n3 GENERIC MAP (tplh3.a_gt_b output g0 : n1 GENERIC MAP (tplh1. tphl2) PORT MAP (a. lt. eq. im9). im2). im8). • A bit comparator with timing parameters • Gates require generic specification • These override the gate generics CHAPTER 6 30 © 1999. b. tphl3) PORT MAP (im3. tphl2) PORT MAP (a. tphl2) PORT MAP (im2. im4). lt. tphl1) PORT MAP (b. tphl2) PORT MAP (im1. g10 : n2 GENERIC MAP (tplh2. g7 : n3 GENERIC MAP (tplh3. tphl1) PORT MAP (a. -. gt. im5). g3 : n2 GENERIC MAP (tplh2. -. g1 : n1 GENERIC MAP (tplh1. tphl3) PORT MAP (im8. tphl2) PORT MAP (im6. a_eq_b). a_gt_b). eq.Design Parametrization . im6). im10). g8 : n2 GENERIC MAP (tplh2. im2. tphl3) PORT MAP (im1. im4. gt. tphl2) PORT MAP (b. im9... END passed_delay. g2 : n2 GENERIC MAP (tplh2. -. tphl2) PORT MAP (im1. g11 : n2 GENERIC MAP (tplh2. im5. im7). im2. im7.

Zainalabedin Navabi .Design Parametrization bit_comparator_t (passed_delay) a nand2_t i1 (average_delay) o1 i2 im3 tplh tphl nand2_t i1 i2 (average_delay) o1 im4 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_gt_b b inv_t im2 i1 (average_delay)o1 nand2_t i1 i2 (average_delay) tplh tphl o1 tplh tphl im5 gt nand3_t i1 (average_delay) o1 i2 i3 tplh tphl nand3_t i1 (average_delay) i2 o1 i3tplh tphl im6 nand2_t i1 i2 im7 (average_delay) eq lt o1 a_eq_b tplh tphl nand2_t i1 i2 inv_t i1 (average_delay)o1 (average_delay) im8 o1 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_lt_b im1 i1 i2 nand2_t (average_delay) tplh tphl o1 im9 tplh tphl nand2_t i1 i2 (average_delay) o1 tplh tplh2 tphl im10 tplh1 tphl1 tphl2 tplh3 tphl3 • Composition aspect of bit_comparator_t • Dotted lines with arrows indicate generics CHAPTER 6 31 © 1999.

PORT (a. b. im(6).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 GENERIC ( tplh1 : TIME := 2 NS. a_lt_b). a_eq_b. b(0). tplh1 : TIME := 4 NS. b(3). eq. END GENERATE. lt. BEGIN c0: comp1 PORT MAP (a(0). tplh3 : TIME := 4 ns. a_gt_b. gt. im(8). b(i). c3: comp1 PORT MAP (a(3). eq. a_eq_b. FOR ALL : comp1 USE ENTITY WORK. im(i*3+0). gt. tplh3 : TIME := 6 ns.bit_comparator_t (passed_delay). Zainalabedin Navabi . im(i*3-2). im(i*3+2) ). a_lt_b : OUT BIT). im(7). END COMPONENT. im(2)). im(i*3-1). tplh2 :TIME := 3 NS. im(i*3-3). END iterative. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). • Comp1 is declared with default values • Passing default values of local generics to the generics of bit_comparator_t • These values override at the lower levels CHAPTER 6 32 © 1999. SIGNAL im : BIT_VECTOR ( 0 TO 8). a_gt_b. im(1). tplh2 :TIME := 5 NS. im(i*3+1). lt : IN BIT. im(0).

Zainalabedin Navabi . 10 NS) PORT MAP (a(0). BEGIN c0: comp1 GENERIC MAP (OPEN. correspond in the order they are listed CHAPTER 6 33 © 1999. and using defaults for others • Association by position... im(2)). eq. gt. END iterative.Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . 8 NS. lt. OPEN... OPEN. b(0). • Some are associated with OPEN • Associating constants with some of generics of bit_comparator_t. im(0). OPEN. im(1). .

b(0). tphl3 => 10 NS) PORT MAP (a(0). b. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. b => b(0). gt. a_eq_b. a_lt_b => im(2)). inputs only if default 34 © 1999. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. eq => eq. tphl3 => 10 NS) PORT MAP (a => a(0).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . im(2)). im(0). lt : IN BIT.. ARCHITECTURE BECOMES: ARCHITECTURE iterative OF nibble_comparator IS . eq. gt => gt. lt => lt. same mapping as before It must be: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open.. Zainalabedin Navabi .. .. a_lt_b : OUT BIT).. a_gt_b... • • • • • CHAPTER 6 Using named association. END iterative. . lt. SAME FORMAT FOR THE PORTS: PORT AS DECLARED: PORT (a. im(1). gt. END iterative.. eq. a_gt_b => im(0). a_eq_b => im(1).

lss). (0.14.00. SIGNAL eql.15.15.14. a_eq_b.14.14.14.12. lss. SIGNAL a.basic_utilities. gtr. a_gt_b. Zainalabedin Navabi . a_lt_b : OUT BIT).ALL. eq.15. 500 NS). SIGNAL vdd : BIT := '1'.15. (0. b. gt.15. gnd. b : BIT_VECTOR (3 DOWNTO 0).00). eql. lt : IN BIT.10. BEGIN a1: comp4 PORT MAP (a.15.15). ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a. Customizable architecture for demonstrating configuration declarations • A customizable test bench • Configuration specification is not included • Comp4 is not in our work library CHAPTER 6 35 © 1999.15. END customizable. gtr : BIT.12. 500 NS). gnd.00. b : IN BIT_VECTOR (3 DOWNTO 0).15. vdd.14. apply_data (a. SIGNAL gnd : BIT := '0'.00.Design Configuration USE WORK. END COMPONENT.12.00. apply_data (b.

Design Configuration 1 USE WORK. Zainalabedin Navabi . • Configuring customizable for testing structural architecture of nibble_comparator • Hierarchically enter the architecture. END FOR.nibble_comparator(structural). CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 2 3 USE ENTITY WORK. END functional.ALL. perform binding CHAPTER 6 36 © 1999. END FOR.

Zainalabedin Navabi .Design Configuration functional nibble_comparator (structural) nibble_comparator_test_bench (customizable) a1: comp4 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • Graphical representation • Composition aspect for functional configuration declaration. configuring customizable test bench • Pass through hierarchies with arrows CHAPTER 6 37 © 1999.

Design Configuration USE WORK. Zainalabedin Navabi . CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.ALL. • Another configuration on top of the test bench • Configuring customizable for testing iterative architecture of nibble_comparator • No need to recompile the test bench CHAPTER 6 38 © 1999. END average_delay.nibble_comparator(iterative). END FOR. END FOR.

END FOR. END average_delay. identifier entity_name configuration declaration binding indication component configuration block configuration • Details of configuration declaration • Configuration declaration replaces or adds to a configuration specification • Includes component configuration and block configuration CHAPTER 6 39 © 1999. END FOR. nibble_comparator (iterative) .Design Configuration CONFIGURATION average_delay OF nibble_ comparator_ test_bench IS FOR customizable FOR al : comp4 USE ENTITY WORK. Zainalabedin Navabi .

eq. lt : IN BIT. im(i*3-2). Zainalabedin Navabi . b(3). c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). im(i*3-3). im(i*3+2) ). b. im(2)). a_eq_b. END COMPONENT. • A general purpose nibble_comparator • This 4-bit comparator does not use a specific bit comparator • A top-level configuration configures comp1 instantiations CHAPTER 6 40 © 1999. BEGIN c0: comp1 PORT MAP (a(0). im(8). a_gt_b. im(i*3+0). END flexible. a_gt_b. im(7). c3: comp1 PORT MAP (a(3). eq. a_lt_b : OUT BIT). SIGNAL im : BIT_VECTOR ( 0 TO 8). im(i*3+1). gt. im(1). b(i). a_eq_b.Design Configuration ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. a_lt_b). gt. im(0). lt. b(0). END GENERATE. im(6). im(i*3-1).

Zainalabedin Navabi .Design Configuration default_bit_level bit_comparator(default_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) c3: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a1: comp4 a(2) b(2) c2: comp1 a(3:0) b(3:0) gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect for configuring customizable test bench for testing default_delay bit_comparator • Graphical representation of hierarchies CHAPTER 6 41 © 1999.

END FOR.ALL.bit_comparator (default_delay). FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (default_delay). END FOR. END default_bit_level. FOR flexible FOR c0. END FOR. CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. • Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator • Binding to the default_delay architecture CHAPTER 6 42 © 1999. c3: comp1 USE ENTITY WORK. END FOR.nibble_comparator(flexible). END FOR.Design Configuration USE WORK. END FOR. Zainalabedin Navabi .

Zainalabedin Navabi . FOR c1to2 FOR c: comp1 USE ENTITY WORK. CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.bit_comparator (fixed_delay). • Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator • Binding to the fixed_delay architecture • Can use ALL or OTHERS CHAPTER 6 43 © 1999. c3: comp1 USE ENTITY WORK. END FOR. END FOR.nibble_comparator(flexible). END fixed_bit_level. END FOR. END FOR.Design Configuration USE WORK.bit_comparator (fixed_delay). FOR flexible FOR c0.ALL. END FOR. END FOR.

Design Configuration passed_bit_level bit_comparator_t(passed_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) tplh1 c3: comp1 tplh2 tplh3 a(3:0) b(3:0) gt eq lt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b 2NS 3NS 4NS 4NS 5NS 6NS a1: comp4 a(2) b(2) c2: comp1 tplh1 tplh2 tplh3 a(3:0) b(3:0) gt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(6) im(7) im(8) 2NS 3NS 4NS 4NS 5NS 6NS gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) 2NS 3NS 4NS 4NS 5NS 6NS c1to2: a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) 2NS 3NS 4NS 4NS 5NS 6NS • Composition aspect of the passed_bit_level • Configuration for test bench for testing passed_delay architecture of bit_comparator_t CHAPTER 6 44 © 1999. Zainalabedin Navabi .

END FOR. Y END FOR. tplh3 => 4 NS. tphl3 => 6 NS).ALL. tplh3 => 4 NS. tplh2 => 3 NS. tphl1 => 4 NS. END FOR.nibble_comparator(flexible). tphl2 => 5 NS. • Using configuration declarations for component bindings.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. and specification of generic parameters • Same format for generic map and port map aspects as configuration specification CHAPTER 6 45 © 1999. CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. tphl3 => 6 NS).bit_comparator_t (passed_delay) X GENERIC MAP (tplh1 => 2 NS. N FOR c1to2 T FOR c: comp1 A USE ENTITY WORK. c3: comp1 USE ENTITY WORK. END FOR. S tphl2 => 5 NS.Design Configuration USE WORK. END FOR. tphl1 => 4 NS. FOR flexible FOR c0. END passed_bit_level. tplh2 => 3 NS. Zainalabedin Navabi . END FOR.

FOR c1to2 FOR c: comp1 USE ENTITY WORK. END FOR.bit_comparator_t (passed_delay) GENERIC MAP (tphl1 => 2 NS. tplh2 => 3 NS.Design Configuration FOR flexible FOR c0. END FOR. END FOR. tphl3 => 6 NS). tplh3 => 4 NS. c3: comp1 USE ENTITY WORK. tphl1 => 4 NS. tphl2 => 5 NS. tphl1 => 4 NS. Zainalabedin Navabi . tplh2 => 3 NS. tphl2 => 5 NS. END FOR. tphl3 => 6 NS).bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. entity aspect component configuration generic map aspect block configuration component configuration block configuration • Details of a block configuration enclosing component configurations and other block configurations • Binding indication and generic map aspect CHAPTER 6 46 © 1999. tplh3 => 4 NS.

c3: comp1 PORT MAP ( . . BEGIN c0: comp1 PORT MAP ( . END COMPONENT. . lt : IN BIT. eq. . ). . gt. b. Zainalabedin Navabi . END partially_flexible. ).Design Configuration ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( .bit_comparator_t (passed_delay). FOR ALL : comp1 USE ENTITY WORK. END GENERATE. ). SIGNAL im : BIT_VECTOR ( 0 TO 8 ). • Can do incremental binding • Do some with configuration specification. . . a_lt_b : OUT BIT). and more with configuration declaration • This is an illustration for the primary binding indication CHAPTER 6 47 © 1999. a_gt_b. a_eq_b.

END FOR. c3: comp1 GENERIC MAP (tplh1 => 2 NS. END incremental.nibble_comparator (partially_flexible). END FOR. • Incremental binding indication illustration • Add generic map aspect to the existing binding • Can use different mappings CHAPTER 6 48 © 1999. tplh3 => 4 NS. CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.Design Configuration USE WORK. END FOR. tphl1 => 4 NS. tplh2 => 3 NS. END FOR. tplh2 => 3 NS. END FOR. tplh3 => 4 NS. END FOR. tphl2 => 5 NS. tphl3 => 6 NS). tphl3 => 6 NS). FOR flexible FOR c0. tphl1 => 4 NS. tphl2 => 5 NS. Zainalabedin Navabi . FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS.ALL.

im3). im2). BEGIN g1 : n2 PORT MAP (s. END gate_level. Customizable architecture. im2. several levels of hierarchy • A new example. g3 : n2 PORT MAP (im1. using a sequential example. im4). im3. r. q : OUT BIT). c. SIGNAL im1. END COMPONENT. Zainalabedin Navabi . i2: IN BIT. c. im4 : BIT. im4. o1: OUT BIT).Design Configuration ENTITY sr_latch IS PORT (s. g2 : n2 PORT MAP (r. c : IN BIT. im1). END sr_latch. illustrating configurations at several levels of depth • Unbound VHDL description of set-reset latch • Uses the same basic components CHAPTER 6 49 © 1999. im2. q <= im3. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. g4 : n2 PORT MAP (im3.

c : IN BIT. dbar. q : OUT BIT). BEGIN c1 : sr PORT MAP (d. END COMPONENT. c2 : n1 PORT MAP (d. END d_latch. q : OUT BIT). c : IN BIT.Design Configuration ENTITY d_latch IS PORT (d. r. q). COMPONENT n1 PORT (i1: IN BIT. -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr PORT (s. Zainalabedin Navabi . dbar). c. o1: OUT BIT). SIGNAL dbar : BIT. END sr_based. • • • • Building a D-latch Add an inverter to the SR-latch Unbound VHDL description of a D-latch All gate level components are unbound CHAPTER 6 50 © 1999. END COMPONENT.

END d_register. c. Zainalabedin Navabi . END GENERATE. -ARCHITECTURE latch_based OF d_register IS COMPONENT dl PORT (d.Design Configuration ENTITY d_register IS PORT (d : IN BIT_VECTOR. • Generically generate a register • Unbound VHDL description for an n-bit latch • Configuration specification is not included CHAPTER 6 51 © 1999. c : IN BIT. END latch_based. q : OUT BIT_VECTOR). BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i). END COMPONENT. q(i)). q : OUT BIT). c : IN BIT.

Design Configuration average_gate_delay d_latch(sr_based) inv_ t(average_delay) 2 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 g4: i2 o1 i1 c2: o1 i1 g2: i2 o1 o1 3 NS 5 NS 5 NS 6 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS 5 NS 6 NS nand2_t(average_delay) di: i1 i2 g1: c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS • Composition aspect for configuring the latch_based architecture of d_register • Hierarchical configuration CHAPTER 6 52 © 1999. Zainalabedin Navabi Sr_latch (gate_level) 4 NS 5 NS 6 NS 2 NS 4 NS 2 NS 4 NS 2 NS 4 NS 5 NS 6 NS .

END FOR. END FOR. END FOR. FOR gate_level FOR g2. FOR sr_based FOR c1 : sr USE ENTITY WORK.nand2_t(average_delay) 10 GENERIC MAP (2 NS. FOR g1.nand2_t(average_delay) 9 GENERIC MAP (5 NS.sr_latch(gate_level). 5 NS). END FOR. END FOR. END FOR. g4 : n2 USE ENTITY WORK.Design Configuration 1 USE WORK. 4 NS).inv_t(average_delay) 7 GENERIC MAP (3 NS. Zainalabedin Navabi .d_latch(sr_based). END FOR. END FOR. FOR c2 : n1 USE ENTITY WORK.ALL. END FOR. 6 NS). CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK. • Configuring d_register for using average_delay gates CHAPTER 6 53 © 1999. g3 : n2 2 3 4 5 6 8 USE ENTITY WORK. END average_gate_delay.

g3 of n2 Figure 6. 6 9 Binding 1.44 instances g1. 2. 5 7 Binding 1. 4 6 Binding 1. 2. 4. 2. Zainalabedin Navabi . 5 8 Visibility 1.44 instances g2.44 Becomes Visible by: - 2 Visibility 1 3 Visibility 1.46 dr GENERATE STATEMENT Figure 6.Design Configuration Block No.46 sr_based ARCHITECTURE Figure 6.45 c2 instance of sr Figure 6. 4. g4 of n2 Figure 6. 3.45 gate_level ARCHITECTURE Figure 6. 3 5 Visibility 1. 1 Configuration Type Configuration Declaration Block Configuration Block Configuration Component Configuration Block Configuration Component Configuration Component Configuration Block Configuration Component Configuration Component Configuration PURPOSE Visibility or Binding to: Main latch_based ARCHITECTURE Figure 6. 5. 3. 3. 2. 2. 4. 6. 3. 2. 2 4 Binding 1. 5. 5. 4.45 c1 instance of sr Figure 6.46 di instance of dl Figure 6. 8 • Analyzing configuration constructs of the average_gate_delay configuration of d_register • Configuration declaration includes component configurations and block configurations CHAPTER 6 54 © 1999. 4. 3. 3. 2. 6. 8 10 Binding 1.

END FOR. END FOR. END FOR. Zainalabedin Navabi . END FOR. END FOR. FOR g1. END FOR. FOR sr_based FOR c1 : sr USE ENTITY WORK. • Configuring d_register for using single_delay architectures of inv and nand2 • Deep inside to reach basic gates and their generic parameters CHAPTER 6 55 © 1999. g4 : n2 USE ENTITY WORK. END FOR.nand2(single_delay). END FOR. END single_gate_delay. i2. FOR c2 : n1 USE ENTITY WORK. o1). FOR gate_level FOR g2.d_latch(sr_based). i1.sr_latch(gate_level).ALL. g3 : n2 USE ENTITY WORK.inv(single_delay).nand3(single_delay) PORT MAP (i1. CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.Design Configuration USE WORK. END FOR.

• Demonstrating the use of configurations in configuration specifications • Test bench for the single_delay architecture of d_register CHAPTER 6 56 © 1999. BEGIN r8: reg PORT MAP (data. c : IN BIT. X"55" AFTER 1500 NS. outdata). '0' AFTER 0800 NS. Zainalabedin Navabi . '1' AFTER 0700 NS.single_gate_delay. clk <= '0'. END COMPONENT. X"AA" AFTER 0500 NS. SIGNAL clk : BIT. clk. SIGNAL data. '0' AFTER 1800 NS. outdata : BIT_VECTOR (7 DOWNTO 0).Design Configuration ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0). data <= X"00". FOR r8 : reg USE CONFIGURATION WORK. '1' AFTER 0200 NS. '1' AFTER 1700 NS. END single. q : OUT BIT_VECTOR (7 DOWNTO 0) ). '0' AFTER 0300 NS.

Design Configuration a(0) im(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) im(1) im(2) im(3) im(4) im(5) im(6) odd even One more configuration declaration example. Zainalabedin Navabi . iterative hardware • The final example • Will illustrate indexing for alternative binding • Parity generator/checker circuit CHAPTER 6 57 © 1999.

-ARCHITECTURE average_delay OF xor2_t IS BEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2. END inv_t. Zainalabedin Navabi . PORT (i1. tphl : TIME := 3 NS). PORT (i1 : IN BIT. tphl : TIME := 7 NS). i2 : IN BIT. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. END average_delay. ---ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. o1 : OUT BIT).Design Configuration ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS. END average_delay. END xor2_t. • Components needed for this design • Timed XOR and INV gates needed for the design of the parity circuit CHAPTER 6 58 © 1999. o1 : OUT BIT).

END parity. a(i+1). even). a(1). END GENERATE. i2: IN BIT. BEGIN first: x2 PORT MAP (a(0). inv: n1 PORT MAP (im(6). im(0)). END COMPONENT. Zainalabedin Navabi . SIGNAL im : BIT_VECTOR ( 0 TO 6 ). last: odd <= im(6). o1: OUT BIT). END COMPONENT. END iterative. middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1). -ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT (i1. o1: OUT BIT). im(i)). even : OUT BIT). COMPONENT n1 PORT (i1: IN BIT. • Parity circuit description • No configuration specification for the inverter and the exclusive OR gate CHAPTER 6 59 © 1999. odd.Design Configuration ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0).

END FOR. FOR middle ( 6) FOR m : x2 USE ENTITY WORK. Zainalabedin Navabi . and OTHERS the rest CHAPTER 6 60 © 1999. • Parity circuit configuration declaration • Index label of the generate statement • Can use OTHERS. 5 NS).xor2_t (average_delay) GENERIC MAP (6 NS.xor2_t (average_delay) GENERIC MAP (5 NS. END FOR. FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK. FOR inv : n1 USE ENTITY WORK. pick some. END FOR. END FOR. END FOR. END parity_binding. END FOR. 5 NS).Design Configuration CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK.inv_t (average_delay) GENERIC MAP (5 NS. 7 NS). END FOR.xor2_t (average_delay) GENERIC MAP (5 NS. 5 NS).

Zainalabedin Navabi .Use of Libraries Value 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' Representing Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care Standard and user libraries. start with the nine-value standard logic • None standard values • Std_logic logic value system • Satisfies most hardware design needs CHAPTER 6 61 © 1999.

Use of Libraries . Zainalabedin Navabi . U X 0 1 Z W L H - U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U' X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' 0 '0' '0' '0' '0' '0' '0' '0' '0' '0' 1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' L '0' '0' '0' '0' '0' '0' '0' '0' '0' H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' 'U’ 'X' '0' 'X’ 'X' 'X' '0' 'X' 'X' • AND table for std_logic type • All logic tables are defined and available • Changing BIT to std_logic works in most cases CHAPTER 6 62 © 1999.

-ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. PORT (i1.std_logic_1164. END average_delay_mvla.ALL. -ARCHITECTURE average_delay_mvla OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. • A two-input NAND gate in std_logic value system • Specify library and package • All basic functions are available in this package CHAPTER 6 63 © 1999. Zainalabedin Navabi . USE IEEE. tphl : TIME := 4 NS). o1 : OUT std_logic). i2 : IN std_logic.Use of Libraries LIBRARY IEEE. END nand2_t.

1997 June 8. 1997 June 6. 1997 June 6. 1997 June 6. Zainalabedin Navabi . 1997 June 8.Use of Libraries LIBRARY ls7400 simple_gates inv inv(single_delay) nand2 nand2(single_delay) nand3 nand3(single_delay) User: John Designer PACKAGE DECLARATION ENTITY ARCHITECTURE ENTITY ARCHITECTURE ENTITY ARCHITECTURE Date June 9. entities and architectures CHAPTER 6 64 © 1999. 1997 June 6. 1997 • Other libraries • Can define our own • Directory of ls7400 library containing package declarations.

USE ls7400. • Visibility of user libraries and packages • Making all declarations of simple_gates package of ls7400 library available CHAPTER 6 65 © 1999. Zainalabedin Navabi . STD is the standard library that includes the STANDARD and TEXTIO packages All other libraries and packages must be explicitly specified Use ls7400 as a user defined library LIBRARY ls7400.ALL.simple_gates.Use of Libraries • • • • WORK is the default library.

q <= im3. im4 : BIT. im3. END gate_level.simple_gates. im4. g2 : n2 PORT MAP (r. USE ls7400. Zainalabedin Navabi . im2).Use of Libraries LIBRARY ls7400. • Using user libraries • Using component declarations of simple_gates package of ls7400 library for description of set-reset latch CHAPTER 6 66 © 1999. im2. c. im3). im2. im1). im4). BEGIN g1 : n2 PORT MAP (s.ALL. -ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1. g3 : n2 PORT MAP (im1. c. g4 : n2 PORT MAP (im3.

Zainalabedin Navabi .Use of Libraries LIBRARY ls7400. • Visibility into libraries • Making all entities and architectures of the ls7400 library available CHAPTER 6 67 © 1999. USE ls7400.ALL.

• Binding indication needs library name • Using a component configuration for associating g1 and g3 instances of n2 of Figure 661 with nand2 of ls7400 CHAPTER 6 68 © 1999. … FOR g1.nand2 (single_delay). Zainalabedin Navabi . .Use of Libraries LIBRARY ls7400.ALL. USE ls7400. … END FOR. g3 : n2 … USE ENTITY ls7400. .

We believe VHDL is very strong in this area and serious designers should learn to take advantage of such capabilities of the language. Although simple examples and college level exercises can avoid some of these language issues. the subject of packaging utilities and components was addressed.Summary This chapter provides tools for better hardware descriptions and design organization. this topic is used mainly for the organization of a design. design parameterization methods save many compilation runs. a large design environment with many logic families and technologies to choose from requires a great deal of library management and parameter specification. Next. We began with the definition of subprograms and emphasized on the use of functions and procedures for simplifying descriptions. Design parameterization and configuration of designs were also discussed in great detail. • End Of Chapter 6 CHAPTER 6 69 © 1999. As stated earlier. For small circuits and experimental models. Zainalabedin Navabi .

8 Aggregate Operation 7.2.1.6 USER-DEFINED ATTRIBUTES 7.3 Signal Attributes 7.2.4 Entity Attributes 7.4.1 TYPE DECLARATIONS AND USAGE 7. Z.5.3 Alias Declaration 7.2 Record Types 7. Navabi and McGraw-Hill Inc.4.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING 7. Global Objects 7.5.1 Array Attributes 7.CHAPTER 7 UTILITIES FOR HIGH LEVEL DESCRIPTIONS 7.6 Type Conversions 7.4 Access Types 7.1.5.4.2.2. .4.3 Physical Types and RC Timing 7.1 Logical Operators 7.4 OTHER TYPES AND TYPE RELATED ISSUES 7.4 Array Declarations 7.4.1 Subtypes 7.7 PACKAGING BASIC UTILITIES 7.2 Relational Operators 7.2 Using Real Numbers For Timing Calculations 7.1.5 PREDEFINED ATTRIBUTES 7.2 VHDL OPERATORS 7.4.1.3 Shift Operators 7.2.4 Adding Operators 7.2.2.2 Type Attributes 7.1 Enumeration Type for Multi-Value Logic 7.1.5.8 SUMMARY CHAPTER 7 1 © 1999.2.7 Nota Operators 7.5 Sign Operators 7.6 Multiplying Operators 7.5.5 File Type and External File I/O 7.

TYPE DECLARATIONS AND USAGE TYPE qit IS ('0'. 'X'). . ‘X’ ) . identifier enumeration element enumeration element enumeration element enumeration element enumeration type definition type definition type declaration Will use an enumeration type for demonstrating type declarations • 4-value qit type will be used • Enumeration type declaration • Initial value of objects of this type is the left-most enumeration element of the base type CHAPTER 7 2 © 1999. Navabi and McGraw-Hill Inc. ‘1’ . '1'. 'Z'. initial TYPE qit IS ( ‘0’ . Z. ‘Z’ .

Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE In: 0 1 Z X 1 0 0 X Out • Will develop basic logic gates based on this type • Input-Output mapping of an inverter in qit logic value system CHAPTER 7 3 © 1999. . Z.

-. PORT (i1 : IN qit. END double_delay. tphl : TIME := 3 NS).basic_utilities. Navabi and McGraw-Hill Inc.ALL. o1 : OUT qit). END inv_q. . Z. • VHDL description of an inverter in qit logic value system • Inputs and outputs are of type qit • Assumes out package contains this type definition CHAPTER 7 4 © 1999. -ARCHITECTURE double_delay OF inv_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh.From PACKAGE USE : qit ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS.TYPE DECLARATIONS AND USAGE USE WORK.

Z. or o1 <= a WHEN cond =’1’ ELSE UNAFFECTED. • • • • A new construct is presented This is conditional signal assignment Several alternatives exist in its usage Can use unaffected for assignments to outputs CHAPTER 7 5 © 1999. Navabi and McGraw-Hill Inc. o1<= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE UNAFFECTED. . o1 <= a WHEN cond =’1’ ELSE o1.TYPE DECLARATIONS AND USAGE Z <= a AFTER 5 NS WHEN d = ’1’ ELSE UNAFFECTED WHEN e = ’1’ ELSE b AFTER 5 NS WHEN f = ’1’ ELSE c AFTER 5 NS.

. target waveform condition waveform condition waveform condition waveform conditional signal assignment • Syntax details of a conditional signal assignment • Condition waveform has a series of waveforms with or without condition CHAPTER 7 6 © 1999. Navabi and McGraw-Hill Inc. Z.TYPE DECLARATIONS AND USAGE o1 <= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE ‘X’ AFTER tplh .

Z.TYPE DECLARATIONS AND USAGE In1: In2: 0 1 Z X 0 1 1 1 1 1 1 0 0 X Out Z 1 0 0 X 1 X X X X • We will develop more basic structures in this 4-value logic system • Input-Output mapping of a NAND gate in qit logic value system • Here we assume 1 for high impedance © 1999. CHAPTER 7 7 . Navabi and McGraw-Hill Inc.

• • • • VHDL description of a NAND gate in qit logic system A conditional signal assignment is used This is a concurrent statement Conditions are checked sequentially from left to right CHAPTER 7 8 © 1999. PORT (i1. -. END double_delay. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE USE WORK. .FROM PACKAGE USE : qit ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS. Z. -ARCHITECTURE double_delay OF nand2_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh. tphl : TIME := 5 NS). -.Can Use: UNAFFECTED. o1 : OUT qit). i2 : IN qit.ALL.basic_utilities. END nand2_q.

TYPE DECLARATIONS AND USAGE inv_rc(double_delay) c_load 25K Ω i1 15K Ω o1 A CMOS inverter example for demonstrating floating point and physical types • • • • Composition aspect of an inverter with RC timing Timing depends on the R and C values Exponential timing is ≅ 3RC Will first demonstrate floating point numbers CHAPTER 7 9 © 1999. Z. . Navabi and McGraw-Hill Inc.

basic_utilities. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1.0E15) * 3 FS. -. o1 : OUT qit).0. Navabi and McGraw-Hill Inc. .FROM PACKAGE USE: qit ENTITY inv_rc IS GENERIC (c_load : REAL := 0. oull-down and load capacitance • Constant values are used in the conditional signal assignment CHAPTER 7 10 © 1999.0. CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1. -.0E15) * 3 FS. -.066E-12). • An inverter model with RC timing parameters • Delay cannot be a fraction of FS • Delay values are calculated based on pull-up. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. Z. CONSTANT rpu : REAL := 25000.TYPE DECLARATIONS AND USAGE USE WORK.Farads PORT (i1 : IN qit.ALL.Ohms END inv_rc. -.Ohms CONSTANT rpd : REAL := 15000. END double_delay.

-. ufr = 1000 nfr. nfr = 1000 pfr. END UNITS. . kfr = 1000 far. mfr = 1000 ufr. • • • • Type definition for defining the capacitance physical type Use physical types instead of floating point Base unit must be there All others are then defined CHAPTER 7 11 © 1999.Femto Farads (base unit) pfr = 1000 ffr. far = 1000 mfr.TYPE DECLARATIONS AND USAGE TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr. Z. Navabi and McGraw-Hill Inc.

• Type definition for defining the resistance physical type • Another physical type • RANGE specifies the largest value in terms of base units that an object of this type can get • Intermediate values can take larger values CHAPTER 7 12 © 1999. Navabi and McGraw-Hill Inc. END UNITS.TYPE DECLARATIONS AND USAGE TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o. Z.Milli-Ohms (base unit) ohms = 1000 l_o. . -. m_o = 1000 k_o. k_o = 1000 ohms. g_o = 1000 m_o.

END inv_rc.ALL. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000. Navabi and McGraw-Hill Inc. capacitance ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). . CONSTANT rpd : resistance := 15000 ohms.basic_utilities. -. END double_delay. resistance. o1 : OUT qit).FROM PACKAGE USE: qit. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000.TYPE DECLARATIONS AND USAGE USE WORK. PORT (i1 : IN qit. CONSTANT rpu : resistance := 25000 ohms. • Using resistance and capacitance physical types in the description of an inverter • Resolutions of Millie-ohms and Femto-farads are taken into account • Divide by 1000 adjusts the time units to FS • Will do it with a better style later CHAPTER 7 13 © 1999. Z.

Z.TYPE DECLARATIONS AND USAGE TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit. 0 TO 7 ) OF qit. TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit. . Demonstrating array definition and object declaration • • • • Declaring array types Arrays may be ascending or descending Objects can be indexed as declared n-dimensional arrays may be declared CHAPTER 7 14 © 1999. TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble. TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0. TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit. Navabi and McGraw-Hill Inc.

Z.TYPE DECLARATIONS AND USAGE TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit . . Navabi and McGraw-Hill Inc. identifier range discrete range index constrained constraint array definition type declaration element_subtype_indication • Syntax details of an array type declaration • This is a type declaration • Contains constraint array definition CHAPTER 7 15 © 1999.

association by name CHAPTER 7 16 © 1999. all elements are initialized to left-most of array element • Can form a vector of initial values • Can use aggregate operation. ‘1’. OTHERS => ‘1’). ‘1’. • Objects of array type may be initialized when declared • If explicit initialization is missing. SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. Navabi and McGraw-Hill Inc. OTHERS => ‘1’). ‘1’). Z. 3 TO 4 => ‘X’.TYPE DECLARATIONS AND USAGE SIGNAL sq8 : qit_byte := "ZZZZZZZZ". ‘Z’. ‘Z’. . association by position • Can use aggregate operation. OTHERS => ‘1’). SIGNAL sq8 : qit_byte := (5 => ‘Z’. SIGNAL sq8 : qit_byte := (‘Z’. ‘1’. ‘Z’.

third nibble (number 2) of sq_nibble_8 into sq4. sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5). -. Z. sq4(2). -.TYPE DECLARATIONS AND USAGE Signal Declarations: SIGNAL sq1 : qit. sq4 <= (sq8(2). sq8(4). sq8 <= sq8(0) & sq8 (7 DOWNTO 1). -. SIGNAL sq8 : qit_byte.reversing sq8 into sq4. . sq8(3). Valid Operations: sq8 <= sq16 (11 DOWNTO 4). SIGNAL sq16 : qit_word.middle 8 bit slice of sq16 to sq8. sq1 <= sq_4_8 (0. -.right rotate sq8.nibble 2. SIGNAL sq_nibble_8 : qit_nibble_by_8.reversing sq8 into sq4. 7). Navabi and McGraw-Hill Inc. sq4(1). (sq4(0). • • • • • Signal declarations and signal assignments Arrays may be sliced and used on RHS or LHS Aggregate may be used on RHS and LHS Can concatenate any length or slice size Aggregates operation works with array elements only CHAPTER 7 17 © 1999. -. sq4(3)) <= sq8 (5 DOWNTO 2). SIGNAL sq4 : qit_nibble.reversing sq8 into sq4. -. sq8(5)).sq4 into left 4 bit slice of sq16. sq1 <= sq_nibble_8(2)(3).lower right bit of sq_4_8 into sq1. sq4 <= sq_nibble_8 (2). SIGNAL sq_4_8 : qit_4by_8. sq16 (15 DOWNTO 12) <= sq4. -. -.-. bit 3 of sq_nibble_8 into sq1.

Slice example: sq_nibble_8(2)(3 DOWN To 2) • Referencing bits of a vector. . Navabi and McGraw-Hill Inc. reversing bits of sq8 and assigning them to sq4 • Cannot index opposite to what the type is defined as. Nice try! • An slicing example is also shown here CHAPTER 7 18 © 1999. Z.TYPE DECLARATIONS AND USAGE Concatenation example: sq4: 3 2 1 0 sq8: 7 6 5 4 3 2 1 0 sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5).

'Z'. 'X' ). OTHERS =>’0’)). ( '1'. 'Z' ). 'X'. '1'. . 'X'. • Initializing or assignment to a two dimensional array • Right most index applies to deepest set of parenthesis • Can initialize the same way as signal and variable assignment • Constants must have static values CHAPTER 7 19 © 1999. 'X'. 'Z'. 'Z'. 'X'. '1'. 7 => ‘X’. ( 'Z'. '1'. '1'. ( 'X'. '0'. '0'. SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := (OTHERS => “11000000”). (OTHERS => (0 TO 1 => ‘1’. 0 => (OTHERS => ‘X’). OTHERS =>’1’). '1'. '0'. (OTHERS => (0 TO 1 => ‘1’. Z. '0' ) ). 'Z'. OTHERS => (0 => ‘X’. 'Z'. Navabi and McGraw-Hill Inc. (OTHERS => (OTHERS => ‘Z’)). '1' ). OTHERS =>’0’)). '0'. … := (OTHERS => (OTHERS => ‘0’)) sq_4_8 <= ( 3 => (OTHERS => ‘X’). 'X'. '0'. '0'. '1'. 'Z'.TYPE DECLARATIONS AND USAGE SIGNAL sq_4_8 : qit_4by8 := ( ( '0'. 'X'.

Demonstrating non-integer RANGE and index specification • Instead of integers.TYPE DECLARATIONS AND USAGE TYPE qit_2d IS ARRAY (qit. ‘X’ => (‘0’ => ‘1’. OTHERS => (‘0’ => ‘1’. ‘X’ => ‘1’. OTHERS =>’0’)). CONSTANT qit_nand2_table : qit_2d := ( ‘0’ => (OTHERS => ‘1’). . can use other types for array range specification • Then an object of this type may be indexed by enumeration elements of the type in the array range specification CHAPTER 7 20 © 1999. Navabi and McGraw-Hill Inc. qit) OF qit. Z. OTHERS => ‘X’).

'1'. ('1'.'0'. END nand2_q.'X'). PORT (i1.ALL. -. qit_2d ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS.TYPE DECLARATIONS AND USAGE USE WORK. • Using qit enumeration type for the discrete range of a two-dimensional array • The constant table is an array qit qit if qit elements CHAPTER 7 21 © 1999. . tphl : TIME := 5 NS).'1'). ('1'.basic_utilities. o1 : OUT qit). END average_delay. -ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1'. i2) AFTER (tplh + tphl) / 2.'X'. Navabi and McGraw-Hill Inc. ('1'. i2 : IN qit. BEGIN o1 <= qit_nand2_table (i1.'0'.'0'.'X')).'X').FROM PACKAGE USE: qit.'1'.'X'. Z.'0'.

. TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER.TYPE DECLARATIONS AND USAGE TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT. Unconstrained array declarations. usage and definition • BIT_VECTOR is a predefined unconstrained array of BITs • STRING is that of CHARACTERS • Can define our own • This is read as RANGE Box CHAPTER 7 22 © 1999. TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER. Z. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE integer_vector IS ARRAY ( NATURAL RANGE <> ) OF INTEGER . . identifier type_mark index_subtype definition unconstrained array definition type declaration element_subtype_indication • Syntax details of an unconstrained array declaration • We will use this array in our basic utilities • Cannot have unconstrained array of an unconstrained array. Z. Nice try! CHAPTER 7 23 © 1999.

Navabi and McGraw-Hill Inc. target <= TRANSPORT buf AFTER i * period. BEGIN FOR i IN values'RANGE LOOP int2bin (values(i). Z. END LOOP. buf).TYPE DECLARATIONS AND USAGE PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE). . target. • • • • A generic version of the apply_data procedure Uses our own integer_vector from basic_utilities Procedure output. END apply_data. CONSTANT values : IN integer_vector. is also unconstrained All will be known when procedure is called CHAPTER 7 24 © 1999.

BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). im(i*3-1). im(i*3-2). • • • • Keeping our promise of a better n-bit comparator An n-bit comparator Wiring n number of one-bit comparators The integer n depends on the size of a CHAPTER 7 25 © 1999. b(i). a_lt_b). im(1). b(i). gt. Z. END GENERATE. im(i*3-1). END COMPONENT. im(i*3+2) ). lt. a_eq_b. eq. Navabi and McGraw-Hill Inc. a_eq_b. eq. gt. b(i). b. a_lt_b : OUT BIT).TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator IS PORT (a. a_gt_b. a_gt_b. lt : IN BIT. im(i*3-2). a_gt_b. im(i*3+0). END GENERATE. b : IN BIT_VECTOR. im(i*3-3). eq. im(i*3-3). gt. im(2) ). -ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a. END GENERATE. . a_lt_b : OUT BIT). lt : IN BIT. im(i*3+1). im(0). FOR ALL : comp1 USE ENTITY WORK. a_eq_b. END GENERATE. SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). CONSTANT n : INTEGER := a'LENGTH. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). END n_bit_comparator. END structural.bit_comparator (functional).

eql. apply_data (b. gnd. FOR a1 : comp_n USE ENTITY WORK. • Using generic apply_data procedure for testing n_bit_comparator • All unconstrained arrays are fixed according to the parameters passed to them • Can use different size integer vectors CHAPTER 7 26 © 1999. a_eq_b.FROM PACKAGE USE: apply_data which uses integer_vector ARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a. b. SIGNAL vdd : BIT := '1'.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator_test_bench IS END n_bit_comparator_test_bench . 00&43&14&45&11&21&44&11. -. 00&15&57&17. a_gt_b. gtr. lss). Navabi and McGraw-Hill Inc. 500 NS). lt : IN BIT. SIGNAL a. END procedural. 500 NS). END COMPONENT. a_lt_b : OUT BIT). SIGNAL gnd : BIT := '0'. lss.basic_utilities. gtr : BIT.ALL. gnd. b : IN bit_vector. Z. vdd. eq. BEGIN a1: comp_n PORT MAP (a. . gt.n_bit_comparator(structural). b : BIT_VECTOR (5 DOWNTO 0). SIGNAL eql. apply_data (a. -USE WORK.

--Just declare a logical file FILE input_logic_value_file2: logic_data IS “input.TYPE DECLARATIONS AND USAGE First. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER.dat”. Then a logical file name must be declared FILE input_logic_value_file1: logic_data. . Navabi and McGraw-Hill Inc. --Declare a logical file and open in READ_MODE FILE input_logic_value_file3: logic_data OPEN READ_MODE IS “input.dat”. Z. --Declare a logical file and open with the specified mode Primitive utilities for file declaration and file specification • input_logic_value_file: logical name for file of logic_data type • An explicit OPEN statement must be used for opening • Can open a file in READ_MODE. WRITE_MODE or APPEND_MODE CHAPTER 7 27 © 1999.

Z. .TYPE DECLARATIONS AND USAGE First. WRITE_MODE or APPEND_MODE CHAPTER 7 28 © 1999. Then a logical file name must be declared FILE output_logic_value_file1: logic_data. Navabi and McGraw-Hill Inc.dat”. --Just declare a logical file. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER. open later FILE output_logic_value_file2: logic_data OPEN WRITE_MODE IS “input. --Declare a logical file and open with the specified mode OUPUT FILE : WRITE_MODE or APPEND MODE • An explicit OPEN statement must be used for opening the file in the first alternative • Can open a file in READ_MODE.

NAME_ERROR. FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS. .dat”. The standard package includes: TYPE FILE_OPEN_STATUS IS (OPEN_OK. Z. MODE_ERROR) Closing a file: FILE_CLOSE (input_logic_value_file). “output. Navabi and McGraw-Hill Inc. READ_MODE). STATUS_ERROR.dat”.TYPE DECLARATIONS AND USAGE An explicit OPEN is needed if file is not implicitly opened FILE_OPEN (input_logic_value_file. output_logic_value_file. WRITE_MODE). FILE_CLOSE (output_logic_value_file). FILE_OPEN (output_logic_value_file. “input. “output. WRITE_MODE). • File open alternatives • Status parameter must be declared first • Close a file using its logical name CHAPTER 7 29 © 1999.dat”.

FILE input_value_file : logic_data. END assign_bits. END LOOP. Z. BEGIN FILE_OPEN (input_value_file. "unix_file. 1500 NS). WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. Navabi and McGraw-Hill Inc. file_name : IN STRING. VARIABLE current : TIME := 0 NS. END IF. . • file_name is a string input containing physical file name • A procedure for reading characters from a file and assigning them to a BIT type • File type is declared in the procedure • En explicit open statement is used CHAPTER 7 30 © 1999. ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current.TYPE DECLARATIONS AND USAGE PROCEDURE assign_bits ( SIGNAL s : OUT BIT. period : IN TIME) IS VARIABLE char : CHARACTER. READ_MODE). Calling this procedure: assign_bits (a_signal. IF char = '0' OR char = '1' THEN current := current + period. END IF. char). file_name.bit". IF char = '0' THEN s <= TRANSPORT '0' AFTER current.

bit • Each time reading begins from the top of the file.TYPE DECLARATIONS AND USAGE Declare in an architecture: FILE input_value_file: logic_data IS “my_file. Call the pocedure: read_from_file (SIGNAL target : OUT BIT. Navabi and McGraw-Hill Inc. . because a new file object is declared each time it is called • To avoid. it reads the entire unix_file. Z.bit”. • In the previous example. when assign_bits is called. declare a file object outside of the procedure CHAPTER 7 31 © 1999. this_file : IN FILE).

x <= “XOR” (a. NAND. x_vector <= “AND” (a_vector. OR. Z. Navabi and McGraw-Hill Inc. b_vector). XOR. . NOR. b). NOT Examples of use: x <= a XNOR b. Outlining VHDL operators and their format of use • Logical operators • Order of operand must remain the same • The second format makes operands appear as functions CHAPTER 7 32 © 1999. x_vector <= a_vector AND b_vector. XNOR.VHDL OPERATORS Logical Operators: AND.

<. and ‘X’ is larger all the rest --for BIT: ‘1’ is greater than ‘0’ • = and /= operate on operands of any type • (<. /=. b_boolean <= i1 /= i2. <=. . Z. and >=) when used with array operands perform ordering operations • These return TRUE or FALSE based on values of array elements starting from the left CHAPTER 7 33 © 1999. >.VHDL OPERATORS Relational operators: =. --if a_bit_vector is “00011” and b_bit_vector is “00100” a_bit_vector < b_bit_vector returns TRUE --for qitt: ‘0’ is less than ‘1’. <=. >= Examples of use: a_boolean <= i1 > i2. Navabi and McGraw-Hill Inc. >.

Z. Navabi and McGraw-Hill Inc.VHDL OPERATORS SLL SLA SRL SRA ROL ROR Shift/Rotate Shift Shift Shift Shift Rotate Rotate Left/Right Left Left Right Right Left Right Logical/Arithmetic Logical Arithmetic Logical Arithmetic Logical Logical VHDL operators are formally presented in the next few slides • Shift operators • operand SIFT_OPERATOR number_of_shifts • fill value is the left-most enumeration element CHAPTER 7 34 © 1999. .

VHDL OPERATORS Start with aq aq SLL 1 aq SLA 1 aq SRL 1 aq SRA 1 aq ROL 1 aq ROR 1 Z 0 0 0 Z 0 X 0 1 1 Z Z 1 Z 1 X X 0 0 X 0 X Z Z 1 1 Z 1 Z 1 1 X X 1 X 1 0 0 Z Z 0 Z 0 X X 1 1 X 1 X 0 X 0 0 Z 0 • Application of shift operators • The result must be placed in a LHS • Left operand remains unchanged CHAPTER 7 35 © 1999. . Z. Navabi and McGraw-Hill Inc.

returns remainder of absolute value division (a. like concatenation. Navabi and McGraw-Hill Inc. ABS Examples of use: a+b “+” (a. /. c) – aggregate. but allows only elements • Adding. MOD. .both integers a_int REM b_int -. Z. -. & Multiplying operators: *. aggregate and other operators • Format of use is shown for each operator CHAPTER 7 36 © 1999. b. REM Other operators: (). b) a_int MOD b_int -. multiplying. **.VHDL OPERATORS Adding operators: +.

SUBPROGRAM PARAMETER TYPES AND OVERLOADING a: b: 0 1 Z X 0 0 0 0 0 1 0 1 1 X z = a. and NOT for qit as easily as for BIT • Tables for the basic logic functions in the qit four value logic system CHAPTER 7 37 © 1999. OR.b (a) a: b: 0 1 Z X 0 0 1 1 X 1 1 1 1 1 Z 1 1 1 1 X X 1 1 X Z 0 1 1 X 0 X X X X z=a+b (b) a: 0 1 Z X 1 0 0 X z = a' Demonstrating overloading VHDL operators and subprograms (c) • Want to use AND. . Z. Navabi and McGraw-Hill Inc.

. 'Z'. TYPE qit_1d IS ARRAY (qit) OF qit. TYPE qit_2d IS ARRAY (qit. b : qit) RETURN qit. FUNCTION "OR" (a. Z. FUNCTION "NOT" (a : qit) RETURN qit. b : qit) RETURN qit. -- FUNCTION "AND" (a. 'X'). qit) OF qit. '1'. • In a package declare qit and arrays based on this type • Declare functions to be overloaded • Overloading: identify a function with its operands and name CHAPTER 7 38 © 1999.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. Navabi and McGraw-Hill Inc.

'1'.'0'.'1'.'1'.'1'.'X'). • Overloading basic logical functions for the qit four value logic system • Definition of functions CHAPTER 7 39 © 1999. END "NOT". Navabi and McGraw-Hill Inc.'1'. BEGIN RETURN qit_or_table (a. b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0'.'1'. ('0'.'X')). ('0'. ('X'. FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1'.'1').'0'.'X').'1'.'0'.SUBPROGRAM PARAMETER TYPES AND OVERLOADING FUNCTION "AND" (a. b). ('1'. Z. ('1'.'1'.'X'. b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0'.'1').'1'. BEGIN RETURN qit_not_table (a). b).'X'. .'X'). END "AND".'X').'1'. END "OR".'0').'0'.'1'.'1'. ('0'.'X')). BEGIN RETURN qit_and_table (a. FUNCTION "OR" (a.

"AND" ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS. i2 : IN qit. PORT (i1.ALL. -.ALL. END nand2_q. o1 : OUT qit). "NOT" ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS. -.FROM PACKAGE USE: qit. END average_delay. USE WORK. tphl : TIME := 3 NS). tphl : TIME := 4 NS).basic_utilities. o1 : OUT qit). -ARCHITECTURE average_delay OF nand2_q IS BEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2. Z.FROM PACKAGE USE: qit. END average_delay. . • Using overloaded operators • Cannot use NAND since it is only defined for BIT CHAPTER 7 40 © 1999. PORT (i1 : IN qit. END inv_q.basic_utilities. -ARCHITECTURE average_delay OF inv_q IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. Navabi and McGraw-Hill Inc.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK.

Z. -ARCHITECTURE average_delay OF nand3_q IS BEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2.basic_utilities. PORT (i1.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. tphl : TIME := 5 NS).ALL. Navabi and McGraw-Hill Inc. . END nand3_q. i2. -. "AND" ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS. i3 : IN qit. • Basic gates in the qit logic value system using overloaded AND operators • Can also overload NAND and other operators • Std_logic has done this for its types CHAPTER 7 41 © 1999.FROM PACKAGE USE: qit. o1 : OUT qit). END average_delay.

SUBPROGRAM PARAMETER TYPES AND OVERLOADING In the declaration: FUNCTION "*" (a : resistance. Navabi and McGraw-Hill Inc. • Overloading the multiplication operator • Returns TIME when multiplying resistance capacitance physical types • Function declaration. the "*" subprogram body and CHAPTER 7 42 © 1999. . In a package body: FUNCTION "*" (a : resistance. b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000. Z. b : capacitance) RETURN TIME. END "*".

• Using the overloaded multiplication operator • The double_delay architecture of inv_rc CHAPTER 7 43 © 1999. END double_delay. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. CONSTANT rpd : resistance := 15 k_o. resistance.FROM PACKAGE USE: qit. capacitance. CONSTANT tphl : TIME := rpd * c_load * 3.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. PORT (i1 : IN qit. CONSTANT rpu : resistance := 25 k_o. "*" ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). Navabi and McGraw-Hill Inc. Z.ALL. -. .basic_utilities. o1 : OUT qit). END inv_rc. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3.

file_name : IN STRING. BEGIN FILE_OPEN (input_value_file. TYPE logic_data IS FILE OF CHARACTER. READ_MODE). WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. END LOOP. 'Z'. 'X'). WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. FILE input_value_file : logic_data. char). PROCEDURE assign_bits ( SIGNAL s : OUT qit. CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current. . VARIABLE current : TIME := 0 NS. period : IN TIME). END CASE. END assign_bits. WHEN OTHERS => current := current . '1'.period. PROCEDURE assign_bits ( SIGNAL s : OUT qit. period : IN TIME) IS VARIABLE char : CHARACTER. Z. file_name. • Overloading the assign_bits procedure for accepting and producing qit data • Procedure and other necessary declarations • Subprogram body uses a case statement CHAPTER 7 44 © 1999. file_name : IN STRING. WHEN '1' => s <= TRANSPORT '1' AFTER current. Navabi and McGraw-Hill Inc. current := current + period.

Z. WHEN ‘X’  ‘x’ => target <= TRANSPORT ‘X’ AFTER current.SUBPROGRAM PARAMETER TYPES AND OVERLOADING CASE char IS WHEN ‘0’ => target <= TRANSPORT ‘0’ AFTER current. WHEN ‘Z’  ‘z’ => target <= TRANSPORT ‘Z’ AFTER current. WHEN OTHERS => current := current – period. END CASE. . WHEN ‘1’ => target <= TRANSPORT ‘1’ AFTER current. Navabi and McGraw-Hill Inc. sequence_of statements case_statement alternative expression choice case_statement alternative sequence_of statements sequence_of statements choices case_statement alternative case_statement alternative sequence_of statements choice sequence_of statements case_statement alternative • Syntax details of a sequential case statement • Consists of several case alternatives • All choices must be filled CHAPTER 7 45 © 1999.

"data. END COMPONENT. FOR ALL : inv USE ENTITY WORK. • Calling the overloaded assign_bits for testing an inverter • The inverter with RC delay is being tested • Type qit operand of the procedure causes the new assign_bits to be called CHAPTER 7 46 © 1999. capacitance. resistance. o1 : OUT qit).FROM PACKAGE: qit.qit". END input_output. z). i1 : inv PORT MAP (a. -.ALL. assign_bits ENTITY tester IS END tester. . Navabi and McGraw-Hill Inc. BEGIN assign_bits (a. Z.inv_rc(double_delay). PORT (i1 : IN qit. 500 NS). z : qit. -ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr).SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK.basic_utilities. SIGNAL a.

Navabi and McGraw-Hill Inc. SUBTYPE bin IS qit RANGE '0' TO '1'. and aliases are discussed • • • • Subtypes are used for compatibility Base type of a subtype is the original type nibble_bits is not compatible with any BIT_VECTOR rit and bin are fully compatible with qit CHAPTER 7 47 © 1999. SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9. .OTHER TYPES AND RELATED ISSUES SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0). Z. TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT. SUBTYPE rit IS qit RANGE '0' TO 'Z'. records. subtypes. Other type related issues.

nop. instr. sub. TYPE address IS BIT_VECTOR (10 DOWNTO 0).OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode address Instruction format TYPE opcode IS (sta.mde <= 2. instr. SIGNAL instr : instruction_format := (nop.adr <= "00011110000". instr <= (adr => (OTHERS => ‘1’). jsr).opc <= lda. add. END RECORD. jmp. adr : address. and. Z. TYPE mode IS RANGE 0 TO 3. "00000000000"). lda. 0. mde : mode. opc => sub) • • • • • • Record Type Three fields of an instruction Declaration of instruction format A signal of record type Referencing fields of a record type signal Record aggregate 48 © 1999. TYPE instruction_format IS RECORD opc : opcode. Navabi and McGraw-Hill Inc. CHAPTER 7 . instr. mde => 2.

Navabi and McGraw-Hill Inc. page <= "001". Z. ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr. . • Alias declaration. page and offset addresses • Alias declaration for the page and offset parts of the address • Assignments to page and offset parts of address CHAPTER 7 49 © 1999. offset <= X"F1".adr (7 DOWNTO 0).adr (10 DOWNTO 8).OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode page address offset ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr.

OTHER TYPES AND RELATED ISSUES head link node data link node data link node data NULL data Integer Type link Pointer Type TYPE node. ACCESS type and implementation and usage of linked lists is demonstrated • Linked list graphical representation • Definition in VHDL starts with an incomplete type definition CHAPTER 7 50 © 1999. END RECORD. link : pointer. TYPE pointer IS ACCESS node. Navabi and McGraw-Hill Inc. TYPE node IS RECORD data : INTEGER. . Z.

Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES Declaration of head as the head of a linked list to be created: VARIABLE head : pointer := NULL. Linking the next node: head. • Using the above linked list • Declaring head and linking to it CHAPTER 7 51 © 1999. head := NEW node. . Assigning the first node to head. Z.link := NEW node.

(25. 12. 19. • • • • Creating a linked list and entering data into it Head is returned as the first node of the linked list A new node of type node is obtained and assigned to head Fields of node are accessed and data is entered into them CHAPTER 7 52 © 1999. int : integer_vector) IS VARIABLE t1 : pointer. END LOOP. cache : pointer := NULL. 20)). Z. 18.OTHER TYPES AND RELATED ISSUES PROCEDURE lineup (VARIABLE head : INOUT pointer. ELSE t1.link. IF i = int'RIGHT THEN t1. BEGIN -. Inserting integers into the mem linked list: lineup (mem. t1 := t1. Navabi and McGraw-Hill Inc. t1 := head.link := NEW node. FOR i IN int'RANGE LOOP t1. . END IF.link := NULL. Declare mem: VARIABLE mem.Insert data in the linked list head := NEW node.data := int(i). END lineup. 17.

BEGIN -.link. t1 := t1. v : IN INTEGER) IS VARIABLE t1. END LOOP. Navabi and McGraw-Hill Inc.link := t2.link. WHILE t1 /= NULL LOOP IF t1. Z.OTHER TYPES AND RELATED ISSUES PROCEDURE remove (VARIABLE head : INOUT pointer. • Removing an item from a linked list • The head of the linked list is passed • Node that follows node with value v is removed CHAPTER 7 53 © 1999. END remove. END IF.Remove node following that with value v t1 := head. t1.link. t2 : pointer. DEALLOCATE (t2). .data = v THEN t2 := t1.

t2 : pointer. BEGIN -. Z. DEALLOCATE (t2).link. END ll_utilities. Navabi and McGraw-Hill Inc. END clear.OTHER TYPES AND RELATED ISSUES PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1.Free all the linked list t1 := head. head := NULL. t1 := t1. • Freeing a linked list • Start with he head of a linked list and clear it • All nodes must be deallocated CHAPTER 7 54 © 1999. WHILE t1 /= NULL LOOP t2 := t1. END LOOP. .

v : IN INTEGER). Z. head := NULL.OTHER TYPES AND RELATED ISSUES PACKAGE ll_utilities IS TYPE node. TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER. WHILE t1 /= NULL LOOP IF t1.link.link. t2 : pointer. Navabi and McGraw-Hill Inc. int : integer_vector) IS VARIABLE t1 : pointer. END ll_utilities. PROCEDURE remove (VARIABLE head : INOUT pointer. END remove.link := t2. END LOOP. link : pointer. ELSE t1. BEGIN -. END IF.data = v THEN t2 := t1. -PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer. FOR i IN int'RANGE LOOP t1. DEALLOCATE (t2). END RECORD. END LOOP. TYPE pointer IS ACCESS node. -PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. t1 := head. WHILE t1 /= NULL LOOP t2 := t1. int : integer_vector).link := NEW node. END LOOP. -PROCEDURE remove (VARIABLE head : INOUT pointer. t1. t1 := t1. t1 := t1. t2 : pointer. TYPE node IS RECORD data : INTEGER.data := int(i). .link := NULL. DEALLOCATE (t2). v : IN INTEGER) IS VARIABLE t1.link. END lineup.link. BEGIN -.link. IF i = int'RIGHT THEN t1.Free all the linked list t1 := head. END clear. END IF. PROCEDURE clear (VARIABLE head : INOUT pointer). • Linked list utilities CHAPTER 7 55 © 1999. BEGIN -. t1 := t1. PROCEDURE lineup (VARIABLE head : INOUT pointer.Remove node following that with value v t1 := head.Insert data in the linked list head := NEW node. END ll_utilities.

In the assignment: (sq4(0).g.. requires a qualifier: (sq4(0). qb <= qo. -. e. sq4(1). sq4(3)) <= qit_nibble’ (OTHERS => ‘X’). -. Z. TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit. sq4(1). . sq4(2).. Now ‘X’s are qualified for size and element type Explicit type conversions for closely related types. sq4(2).Must do explicit type conversion • Share variables • Using qualifiers • Explicit type conversion between closely related types CHAPTER 7 56 © 1999. SIGNAL qb : qit_byte. INTEGER and REAL TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit. ‘X’ can be interpreted as character ‘X’. ..CANNOT DO qb <= qit_byte (qo). sq4(3)) <= (OTHER => ‘X’). SIGNAL qo : qit_octal. Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES SHARED VARIABLE dangerous : INTEGER := 0.

Navabi and McGraw-Hill Inc. Z.std_logic_1164. USE IEEE. std_logic is an enumeration type with nine logic values ‘U’ is the default initial value std_logic_vector is an unconstraned array of std_logic All logical and shift operators are overloaded for std_logic and std_logic_vector Conversion functions for all subtypes and the BIT type to and from std_logic std_logic.OTHER TYPES AND RELATED ISSUES LIBRARY IEEE.ALL. . its overloading and its subtypes is a good example of the above topics • Provides types for most applications • Overloading is done for all operators • Includes conversion functions where needed CHAPTER 7 57 © 1999.

‘U’. Navabi and McGraw-Hill Inc. ‘0’. different initial values CHAPTER 7 58 © 1999. ‘U’. ‘Z’ • std_logic subtypes • Enumeration elements are arranged for such subtypes • Our qit is like UX01 or X01Z. ‘0’. ‘X’.OTHER TYPES AND RELATED ISSUES TYPE X01 X01Z UX01 UX01Z ‘X’. ‘X’. ‘1’ ‘1’. ‘0’. ‘0’. . Z. ‘X’. ‘Z’ ‘1’ ‘1’.

Array. Z. and Entity • Predefined Array Attributes • Type of sq_4_8 is qit_4by8 CHAPTER 7 59 © 1999. Signal. . Type. Navabi and McGraw-Hill Inc.PREDEFINED ATTRIBUTES Attribute ‘LEFT ‘RIGHT Description Left bound Right bound Example sq_4_8’LEFT(1) sq_4_8’RIGHT sq_4_8’RIGHT(2) sq_4_8’HIGH(2) sq_4_8’LOW(2) sq_4_8’RANGE(2) sq_4_8’RANGE(1) sq_4_8’REVERSE_RANGE(2) sq_4_8’REVERSE_RANGE(1) sq_4_8’LENGTH sq_4_8’ASCENDING(2) sq_4_8’ASCENDING(1) 3 0 7 7 0 Result ‘HIGH ‘LOW ‘RANGE Upper bound Lower bound Range 0 TO 7 3 DOWNTO 0 7 DOWNTO 0 0 TO 3 4 TRUE FALSE ‘REVERSE_RANGE Reverse range ‘LENGTH ‘ASCENDING Length TRUE If Ascending Predefined attributes are demonstrated here.

. .. . after value V in base of type. Value. before value V in base of type. .. Z.. Value at Position P in base of type... Navabi and McGraw-Hill Inc.. . Value. . Example rit’BASE rit’LEFT qit’LEFT rit’RIGHT qit’RIGHT INTEGER’HIGH rit’HIGH POSITIVE’LOW qit’LOW qit’POS(‘Z’) rit’POS(‘X’) qit’VAL(3) rit’VAL(3) rit’SUCC(‘Z’) Result qit ‘0’ ‘0’ ‘Z’ ‘X’ Large ‘Z’ 1 ‘0’ 2 3 ‘X’ ‘X’ ‘X’ ‘HIGH ‘LOW ‘POS(V) ‘VAL(P) ‘SUCC(V) ‘PRED(V) rit’PRED(‘1’) ‘0’ .PREDEFINED ATTRIBUTES Attribute ‘BASE ‘LEFT ‘RIGHT Description Base of type Left bound of type or subtype Right bound of type or subtype Upper bound of type or subtype Lower bound of type or subtype Position of value V in base of type. .. CHAPTER 7 60 © 1999. • Predefined type attributes • The type of qit and rit are enumeration types • More follows .

‘LEFTOF(V) .. . Converts string S to value of type. rit’LEFTOF(‘1’) rit’LEFTOF(‘0’) rit’RIGHTOF(‘1’) rit’RIGHTOF(‘Z’) qit’ASCENDING qqit’ASCENDING qit’IMAGE(‘Z’) qqit’IMAGE(qZ) qqit’VALUE(“qZ”) ‘RIGHTOF(V) ‘ASCENDING ‘IMAGE (V) ‘VALUE(S) • Predefined type attributes • The type of qit and rit are enumeration types • Note type versus base of type CHAPTER 7 61 © 1999.. TRUE if range is ascending Converts value V of type to string. ‘0’ Error ‘Z’ ‘X’ TRUE TRUE “’Z’” “qZ” qZ Value. Example Result .. Navabi and McGraw-Hill Inc.PREDEFINED ATTRIBUTES Attribute .. Description .. Z. left of value V in base of type. Value.. right of value V in base of type...

delayed by delta. this attribute becomes TRUE.. . Equivalent to TRANSPORT delay of s1. . ‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1 The value of s1 before the most recent event occurred on this signal. CHAPTER 7 62 © 1999. the value of s1’LAST_VALUE is 0. If s1’EVENT is TRUE. the resulting signal is TRUE if s1 has not changed in the current simulation time. . If no parameter or 0. . but delayed by 5 NS. If no parameter or 0. ‘EVENT EV s1’EVENT VALUE BOOLEAN In a simulation cycle.PREDEFINED ATTRIBUTES Attribute T/E Example Kind Type Attribute description for the specified example ‘DELAYED s1’DELAYED (5 NS) SIGNAL As s1 A copy of s1. ‘LAST_EVENT EV s1’LAST_VALUE VALUE TIME The amount of time since the last value change on s1. Z. Navabi and McGraw-Hill Inc. • Predefined signal attributes • Signal s is assumed to be of type BIT • More follows .. ‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN A signal that is TRUE if s1 has not changed in the last 5 NS. if s1 changes.

PREDEFINED ATTRIBUTES Attribute T/E Example . s1’LAST_ACTIVE is 0. ‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN If s1 has had a transaction in the current simulation cycle. ‘DRIVING s1’DRIVING VALUE BOOLEAN If s1is being driven in a process. If s1’ACTIVE is TRUE. ‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME The amount of time since the last transaction occurred on s1. . Z.. ‘DRIVING_VALUE s1’DRIVING_VALUE VALUE As s1 The driving value of s1 from within the process this attribute is being applied. If no parameter or 0. • Predefined signal attributes • Signal s is assumed to be of type BIT CHAPTER 7 63 © 1999. s1’DRIVING is TRUE in the same process. Navabi and McGraw-Hill Inc. ‘TRANSACTION TR s1’TRANACTION SIGNAL BIT A signal that toggles each time a transaction occurs on s1. Kind Type ‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS. for delta time. the current simulation cycle is assumed. Initial value of this attribute is not defined.. s1’ACTIVE will be TRUE for this simulation cycle.

Z.PREDEFINED ATTRIBUTES 15 TIME (NS) 30 45 60 s1 s1'DELAYED (5NS) s1'STABLE s1'EVENT 10 s1'LAST_EVENT s1'LAST_VALUE s1'QUIET (5NS) 15 20 25 0 5 10 0 5 10 15 s1'ACTIVE 10 s1'LAST_ACTIVE 0 5 10 0 5 10 0 5 10 0 s1'TRANSACTION • Results of signal attributes when applied to the BIT type signal. Navabi and McGraw-Hill Inc. . s1 • Blocks show Boolean results CHAPTER 7 64 © 1999.

END brief_d_flip_flop. Z. END falling_edge. Navabi and McGraw-Hill Inc. • A simple falling edge Flip-Flop using signal attributes • Two events occur when c changes • Cannot delay the first statement CHAPTER 7 65 © 1999. c : IN BIT. BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp. -ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT. q : OUT BIT).PREDEFINED ATTRIBUTES ENTITY brief_d_flip_flop IS PORT (d. q <= tmp AFTER 8 NS. .

• A simple toggle Flip-Flop using signal attributes • Combining several signal attributes • Can only apply if result of an attribute is signal CHAPTER 7 66 © 1999. q <= tmp AFTER 8 NS. -ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT. . END toggle. BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp. Navabi and McGraw-Hill Inc. q : OUT BIT).PREDEFINED ATTRIBUTES ENTITY brief_t_flip_flop IS PORT (t : IN BIT. END brief_t_flip_flop. Z.

architecture. labels. architectures. Z. constants. packages. components. • Entity attributes • Generate a string for the name for an entity class CHAPTER 7 67 © 1999. units. Navabi and McGraw-Hill Inc. groups. . literals. variables. and instantiation labels leading to the design entity. ‘INSTANCE_NAME: Generates a name that contains entity. configurations.PREDEFINED ATTRIBUTES Entity Attributes generate a string corresponding to the name of an entity class “entity_class” entities. signals. procedures. functions. types. and files ‘SIMPLE_NAME: Generates simple name of a named entity ‘PATH_NAME : Generates a string containing entity names and labels from the top of hierarchy leading to the named entity. subtypes.

o1 : OUT BIT). SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH) := (OTHERS => '. o1 : OUT BIT). SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH) := (OTHERS => '. . c). END ENTITY. u2 : ENTITY WORK. -ARCHITECTURE single_delay OF nand2 IS SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH) := (OTHERS => '. i2. b.nand2 PORT MAP (i1. -ARCHITECTURE gate_level OF xoring IS SIGNAL a. i2.nand2 PORT MAP (i1. i2 : IN BIT. i2 : IN BIT. c. simple <= nand2'SIMPLE_NAME. a.PREDEFINED ATTRIBUTES ENTITY nand2 IS PORT (i1.nand2 PORT MAP (a. c : BIT.'). instance <= nand2'INSTANCE_NAME. BEGIN u1 : ENTITY WORK. o1). a). and instance attributes CHAPTER 7 68 © 1999. path <= nand2'PATH_NAME.'). END single_delay. Z. b). END gate_level. u3 : ENTITY WORK. • Examples for entity attributes • Simple.nand2 PORT MAP (b. END ENTITY. Navabi and McGraw-Hill Inc. u4 : ENTITY WORK.'). -ENTITY xoring IS PORT (i1. BEGIN o1 <= i1 NAND i2 AFTER 3 NS. path.

. Z. path. and instance strings • Results from simulation of the above nand2 CHAPTER 7 69 © 1999. Navabi and McGraw-Hill Inc.PREDEFINED ATTRIBUTES Simple: Path: Instance: nand2 :xoring:u1: “xoring(gate_level):u1@nand2(single_delay): • Simple.

USER-DEFINED ATTRIBUTES

User-defined attributes may be applied to the elements of an entity class

Must declare first: ATTRIBUTE sub_dir : STRING;

Then attribute specification: ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS “/user/vhdl”;

brief_d_flip_flop’sub_dir evaluates to “/user/vhdl”.

User-defined attributes are demonstrated here.

• User defined attributes • No simulation semantics

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USER-DEFINED ATTRIBUTES

PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING; END utility_attributes; -USE WORK.utility_attributes.ALL; -- FROM PACKAGE USE: delay, sub_dir ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS); END brief_d_flip_flop; -ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall; END attributed_falling_edge;

• • • •

Associating attributes to entities and signals A package declares attributes An entity defines An architecture uses attributes

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PACKAGING BASIC UTILITIES

PACKAGE basic_utilities IS ... TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL; ... FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; FUNCTION to_integer (qin : qit_vector) RETURN INTEGER; FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector; ... FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector; ... END basic_utilities;

• Adding what was done to our basic utilities package • Will use this package for homeworks and in other chapters

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PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;

• Complete package declaration

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PACKAGING BASIC UTILITIES
PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;

• Package body
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PACKAGING BASIC UTILITIES
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;®BB¯

• Package body

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PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits; END basic_utilities;

• The basic_utilities package as will be used in the examples in the chapters that follow

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Summary This chapter presented tools for high level descriptions. Declaration of types and the usage of objects of various types were covered in the first part of the chapter. In the context of describing type-related issues, we introduced the unconstrained array and file type. The basic I/O presented in this chapter showed a simple way to read or write from files. The overloading which is related to types was discussed next. Predefined attributes in VHDL can be looked upon as operators or predefined functions. In modeling, hardware behavior attributes are very useful, as we will see in the following, chapters. Finally in this chapter, we presented the Elements of this package are

basic_utilities package.

useful for hardware modeling and the creation of the package demonstrates the importance of packaging capability in VHDL.

• End Of Chapter 7

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CHAPTER 8 DATAFLOW DESCRIPTIONS IN VHDL

8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals 8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine 8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING 8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY

• • • • • • •

Constructs for dataflow descriptions Multiplexing and clocking, selection constructs; guarded assignments Multiple assignments; Resolutions: anding, oring, wiring Guarded signals State machines, simple sequence detector, multiple active states Open collectors using resolution functions A complete dataflow example

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION
select1

data1

out select2

data2

(a)

1D 2D y S1 S2

D1

Y D2

S1 S2

Will use VHDL for modeling various selection logic implementations

• Basic data selection hardware, logic diagram, symbols • Multiplexers are used for data selection

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION

Q

enable

data

1D C1

clk

• Flip flop clocking selects data • Various forms of data selection may be combined • Will show language constructs for such selections

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© 1999, Z. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. . Z.MULTIPLEXING AND DATA SELECTION data1 data2 1D 2D Y 1D Q select1 select2 S1 S2 C1 enable clk • Multiplexing and clock enabling. CHAPTER 8 4 © 1999.

MULTIPLEXING AND DATA SELECTION G0 G1 select lines G2 G3 G4 G5 G6 G7 MUX Z 0 1 2 data inputs 3 4 5 6 7 • An eight-to-one multiplexer. Navabi and McGraw-Hill Inc. . CHAPTER 8 5 © 1999. Z.

s0 : IN qit. i3. i5.FROM PACKAGE USE: qit. i0 : IN qit. s1. qit_vector ENTITY mux_8_to_1 IS PORT ( i7. Z. s3. i3 AFTER 3 NS WHEN "00001000" | "0000Z000". s5. z : OUT qit ). s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000". i1. s4. • • • • Description of a simple multiplexer Selected signal assignment is used Dataflow multiplexing Selected waveforms use choice or choices CHAPTER 8 6 © 1999. i0 AFTER 3 NS WHEN "00000001" | "0000000Z". . END dataflow. s2. s6. END mux_8_to_1. -. i5 AFTER 3 NS WHEN "00100000" | "00Z00000". s1. 'X' WHEN OTHERS.ALL. -ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector’(s7. s6. s3. s4.MULTIPLEXING AND DATA SELECTION USE WORK. s5.basic_utilities. i1 AFTER 3 NS WHEN "00000010" | "000000Z0". i2 AFTER 3 NS WHEN "00000100" | "00000Z00". s2. i7 AFTER 3 NS WHEN "10000000" | "Z0000000". i6. i4. i2. i6 AFTER 3 NS WHEN "01000000" | "0Z000000". s7. Navabi and McGraw-Hill Inc. i4 AFTER 3 NS WHEN "00010000" | "000Z0000".

Z. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • Syntax details of a selected signal assignment. CHAPTER 8 7 © 1999. .

which we will model in VHDL • Decoder description uses selected signal assignment • A three-to-eight decoder.MULTIPLEXING AND DATA SELECTION A0 A1 A2 DCD S0 S1 S2 S3 S4 S5 S6 S7 Another form of selection is a decoder. Z. . CHAPTER 8 8 © 1999. Navabi and McGraw-Hill Inc.

"00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" . • VHDL description for the three-to-eight decoder. so : OUT qit_vector (7 DOWNTO 0)).FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0). "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110". "XXXXXXXX" WHEN OTHERS. Z. Navabi and McGraw-Hill Inc.basic_utilities. "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011". "00010000" AFTER 2 NS WHEN "100" | "Z00". -ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000".ALL.MULTIPLEXING AND DATA SELECTION USE WORK. • All possibilities must be considered CHAPTER 8 9 © 1999. "00000100" AFTER 2 NS WHEN "0Z0" | "010". "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111". . END dcd_3_to_8. "00000010" AFTER 2 NS WHEN "00Z" | "001". -. END dataflow.

PORT (d. qb <= NOT internal_state AFTER delay2. q. . Navabi and McGraw-Hill Inc. c : IN BIT. qb : OUT BIT). q <= internal_state AFTER delay1. BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state. delay2 : TIME := 5 NS). -ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT. END d_flipflop. END assigning. Z. 1D Q Q C1 • A simple flip-flop uses internal_state • On clock edge d is transferred to internal_state • Events on internal_state cause assignments to q and qb CHAPTER 8 10 © 1999.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS.

qb <= GUARDED NOT d AFTER delay2. . END BLOCK ff. Z. Better representation of clocking disconnects d from q Disconnection is specified by GUARDED GUARDED assignments are guarded by guard expression Can also guard selected and conditional signal assignments CHAPTER 8 11 © 1999. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms. END guarding. 1D Q Q C1 Several examples will demonstrate guarded blocks and assignments • • • • • The guarding architecture for the d_flipflop entity. ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1.

. END BLOCK ff. Navabi and McGraw-Hill Inc. qb <= GUARDED NOT d AFTER delay2.MULTIPLEXING AND DATA SELECTION ff : BLOCK ( block_label Concurrent statement c = ‘1’ AND NOT c’STABLE ) BEGIN q <= GUARDED d AFTER delay1. guard_expression concurrent statement block statement part block statement concurrent statement • Syntax details of a guarded block statement with guarded signal assignments • Label is mandatory • Use GUARDED for guard to apply CHAPTER 8 12 © 1999. Z.

cc. qb2 : BIT. q1. cc. SIGNAL dd. q. Z. cc.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d. dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd. END COMPONENT. . q2. FOR c1 : flop USE ENTITY WORK. qb1. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc.d_flipflop (assigning). • A test bench for testing assigning and guarding architectures of d_flipflop • Testbench tests and verifies both descriptions • A simple method for generation of periodic signals CHAPTER 8 13 © 1999. qb2). Navabi and McGraw-Hill Inc. q1. q2. c2: flop PORT MAP (dd. c1: flop PORT MAP (dd.d_flipflop (guarding). qb1). c : IN BIT. END input_output. FOR c2 : flop USE ENTITY WORK. qb : OUT BIT).

'0' .... .... ... .. ... . ....... . ..... .. . .... ... '0' . .. . '0' '0' ..... ........... TRUE FALSE . .... ..... . .. ....... ..... '1' ..... '1' qb2 '0' . . . '1' c1: state '0' '0' .. is due to initialization In guarding:c2..... '0' ... . '1' '1' .... .. '0' .. ... ...... ... '0' ... ... ..... .. . ........... ..... .... .. . .. . .... ... '0' ......... . .... . '1' .. ... .. . ...... .. ....... .. . . .. . . . ... . . .... . ...... . ... .. . ... ....... '1' . • • • • • • Simulation results of the input_output architecture of the flipflop_test All transactions are observed In assigning:Two transactions on internal_state for every clock edge Transaction on q1 at time 0004. .. '0' '0' ... .... '0' . . ... ...... qb1 '0' ..... FALSE FALSE . ... '0' ...... . . Navabi and McGraw-Hill Inc. .. '1' ... . '1' .. . q2 '0' ........... ....... ... TRUE FALSE ... ... .... ... '0' .... '1' . .... . FALSE FALSE . ... . ..... . ....... ... ... Z.......... . . ..... . . ... ... . ...... .. ...... . '1' '1' ...... ..... . . .... . .......... . '0' '0' ........ ..... .. . ..... .ff : GUARD sees GUARD inside guarding Guard expression is only TRUE for 1 delta © 1999. q1 '0' .. .. .... CHAPTER 8 14 ..... . ........................ TRUE FALSE . .. ...... c2:ff GUARD FALSE .. '0' '0' . .... ..... dd '0' .MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0004 0005 0400 +1δ δ +2δ δ 0404 0405 0800 +1δ δ +2δ δ 1000 +1δ δ 1200 +1δ δ +2δ δ 1204 1205 1600 +1δ δ +2δ δ 2000 +1δ δ +2δ δ 2004 2005 cc '0' .. . ... '1' .. '1' '1' ... .

6) (d) Value = s Value = d s • Events on edge detection expression • Demonstrating difference between ‘EVENT and NOT ‘STABLE CHAPTER 8 15 © 1999. Navabi and McGraw-Hill Inc. c Scheduling on S (d. 0) (c) Value = s s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND c’EVENT) ELSE s. Z. c Scheduling on S (d. 0) (b) Value = d s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND NOT c’STABLE) ELSE s. c Scheduling on S (d. 0) UNAFFECTED (a) Value = d s Value = s s <= d WHEN (c= ‘1’ AND c’EVENT) ELSE UNAFFECTED.MULTIPLEXING AND DATA SELECTION s <= d WHEN (c= ‘1’ AND NOT c’STABLE) ELSE UNAFFECTED. c Scheduling on S (d. 6) (s. .

BEGIN qout <= GUARDED din AFTER delay1. qout => q. -ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT. qb : OUT BIT). delay2 : TIME := 5 NS). . qbar : OUT BIT). PORT (d. • • • • Using declarative part of a block statement PORT specifies signals on the outside PORT MAP maps outside signals with those inside Association format is used as expected CHAPTER 8 16 © 1999. END guarding. END BLOCK ff. PORT MAP (din => d. q. qbar <= GUARDED NOT din AFTER delay2. END ENTITY. qbar => qb). qout. c : IN BIT.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS. Z. Navabi and McGraw-Hill Inc.

. Z. . Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION ff : BLOCK ( . . . . . ).. ) PORT ( . END BLOCK ff. . .. . BEGIN qout <= . qbar <= . . ). PORT MAP ( . . block_statement port_clause port_map_aspect block_header block_statement_part • Syntax details for block statement with header • Uses this to draw a dashed line around a section of your hardware CHAPTER 8 17 © 1999.

2D Q E2 C1 Q • A positive edge trigger flip-flop with enable input • Can nest block statements • Combining guard expressions must be done explicitly CHAPTER 8 18 © 1999.MULTIPLEXING AND DATA SELECTION 1. Z. . Navabi and McGraw-Hill Inc.

END de_flipflop. END BLOCK edge. qb <= GUARDED NOT d AFTER delay2. PORT (d. END BLOCK gate. e. Z. Navabi and McGraw-Hill Inc. c : IN BIT.MULTIPLEXING AND DATA SELECTION ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS. . delay2 : TIME := 5 NS). q. • VHDL description for the positive edge trigger flip-flop with enable input • Implicit GUARD signals in each block • Useful if different second conditions were used CHAPTER 8 19 © 1999. END guarding. qb : OUT BIT). -ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1.

3D Q E2 E3 C1 Q • A positive edge trigger. -ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1.MULTIPLEXING AND DATA SELECTION ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS. Z. Navabi and McGraw-Hill Inc. 1. END BLOCK gate2. d3. c : IN BIT. qb : OUT BIT). e2. PORT (d2. qb <= GUARDED NOT d3 AFTER delay2. END BLOCK edge. e3. END BLOCK gate3. . double d flip-flop with independent enable inputs • Clock expression is specified only once CHAPTER 8 20 © 1999. END dee_flipflop. gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1. END guarding. delay2 : TIME := 5 NS). 2D 1. qb <= GUARDED NOT d2 AFTER delay2. q.

qb1). ee <= '1'. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d. q.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. ee. cc. . END COMPONENT. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc. cc. c : IN BIT. • A test bench for testing the guarding architectures of de_flipflop • Testbench verifies operation of de_flipflop • After 2200 q1 is disconnected from d CHAPTER 8 21 © 1999. Z. q1.de_flipflop (guarding). END input_output. FOR c1 : ff1 USE ENTITY WORK. qb : OUT BIT). dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd. qb1 : BIT. q1. Navabi and McGraw-Hill Inc. ee. SIGNAL dd. c1: ff1 PORT MAP (dd. e. '0' AFTER 2200 NS.

.. .. . '0' ... '0' .. . .... dd '0' ..... ... . '0' . . .. . . Navabi and McGraw-Hill Inc... .... .. .... '1' . qb1 '0' .. . ... . . .... ...... ..... .... • Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • No transactions on the outputs after 2200 NS CHAPTER 8 22 © 1999. . .. .... . '1' '1' ..... .... .. . . '1' .. .......... q1 '0' . ..MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0400 0404 0405 0800 1000 1200 1204 1205 1600 2000 2004 2005 2200 2400 2800 3000 +1δ δ 3200 +1δ δ cc '0' . ... ....... '1' . .. .. '0' .... '1' ....... '1' ... ..... ...... .. ...... '0' . ..... . . . .. .. '0' '1' .. .... '0' ..... . .. . ........ ..... Z. .... . '0' '1' ......... .... ... . .... ... '1' .... '0' '0' ee '0' '1' ... ... ...

. Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION RHS Activation GUARD 0 Driving Value Projected Output Waveform • Symbolizing guarded signal assignments • Disconnection in a guarded signal assignment • Driving value continues to be updated even if the guard expression is false CHAPTER 8 23 © 1999.

MULTIPLEXING AND DATA SELECTION What follows concentrates on definition & applications of resolution functions • Normally several sources cannot drive a signal • Real circuits smoke. Z. . Navabi and McGraw-Hill Inc. • So does VHDL CHAPTER 8 24 © 1999.

-.FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a. • Multiple sources for a simple signal • This results in an error message CHAPTER 8 25 © 1999. circuit_node <= d. END smoke_generator.MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities. END y_circuit. -ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit. circuit_node <= b. . c.ALL. b. z : OUT qit). Z. z <= circuit_node. d : IN qit. Navabi and McGraw-Hill Inc. BEGIN circuit_node <= a. circuit_node <= c.

Z. a happy VHDL simulator • Multiple drivers is possible only if a resolution exists • Example in hardware is "open collector" • Pull_up provides resolution CHAPTER 8 26 © 1999. .MULTIPLEXING AND DATA SELECTION A happy circuit. Navabi and McGraw-Hill Inc.

USE qit. Z. Navabi and McGraw-Hill Inc. END LOOP. a b anding c d circuit_node • • • • The anding resolution function. RETURN accumulate.MULTIPLEXING AND DATA SELECTION -. ANDs all its drivers Performs the AND function two operand at a time Collect all ANDs and return A notation that we will use CHAPTER 8 27 © 1999. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). END anding. . “AND” from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'. qit_vector.

BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). SIGNAL circuit_node : anding qit. END LOOP. Z. circuit_node <= c. Navabi and McGraw-Hill Inc.ALL. END wired_and.FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'. • • • • • • Multiple sources for a simple signal The difference is in the declaration of the left-hand-side This results in ANDing all sources Specify anding for the resolution on circuit_node Type of circuit_node is a subtype of qit ANDing simultaneously receives all drivers 28 © 1999. CHAPTER 8 . RETURN accumulate. BEGIN circuit_node <= a. circuit_node <= b. -.MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities. z <= circuit_node. END anding. circuit_node <= d.

. Z. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION t4 v4 t4 v4 t4 v4 t3 v3 t3 v3 t3 t3 t2 v2 t2 v2 t2 t2 t1 v1 t1 v1 t1 t1 0 0 lhs_signal 0 • • • • Projected output waveforms and resolution functions Every assignment in a concurrent body creates a driver All assignments is a sequential body create only one driver Resolution functions act on expired values CHAPTER 8 29 © 1999.

Navabi and McGraw-Hill Inc. .MULTIPLEXING AND DATA SELECTION RHS Activation GUARD t4 v4 Driver 1 t3 v3 t2 v2 t1 v1 0 RHS Activation lhs_signal GUARD t4 v4 Driver 2 t3 v3 t2 v2 t1 v1 0 • Guarded signal assignments into resolved signals • Drivers continue to perform normal in spite of disconnection • Resolution function cannot tell the difference. Z. it only sees the driving value CHAPTER 8 30 © 1999.

ALL. t <= i5 AND s5.basic_utilities. t <= i6 AND s6.MULTIPLEXING AND DATA SELECTION USE WORK. • Implementing the eight-to-one multiplexer using eight concurrent assignments • ORing resolution function is used CHAPTER 8 31 © 1999. . BEGIN t <= i7 AND s7. -. Navabi and McGraw-Hill Inc. t <= i0 AND s0. END oring. SIGNAL t : oring qit. END LOOP. t <= i1 AND s1. z <= t. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). t <= i2 AND s2. t <= i4 AND s4. RETURN accumulate. t <= i3 AND s3.FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. Z. END multiple_assignments.

'1'.MULTIPLEXING AND DATA SELECTION FUNCTION wire (a.'X')). Navabi and McGraw-Hill Inc.'X'). ('0'. ('X'.'X'. BEGIN RETURN qit_wire_table (a.'X').'1'. b). . In1: In2: 0 1 Z X 0 0 X 0 X 1 X 1 1 X Out Z 0 1 Z X X X In1 X Out X In2 X • The wire function for modeling wiring two qit type nodes.'X'. b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'. Z.'0'. END wire.'X').'X'. ('X'.'1'.'Z'. • Input-output mapping • Circuit notation CHAPTER 8 32 © 1999.

TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. RETURN accumulate. FUNCTION wiring ( drivers : qit_vector) RETURN qit. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. END LOOP. END wiring. • The wiring resolution function for qit type operands • Necessary declarations for visibility of the wiring resolution function and its related types and subtypes • If no drivers exist. drivers(i)). SUBTYPE wired_qit IS wiring qit. .MULTIPLEXING AND DATA SELECTION FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. Z. ‘Z’ will be returned • To declare an array of this resolution CHAPTER 8 33 © 1999. Navabi and McGraw-Hill Inc.

SUBTYPE ored_bit IS oring BIT. Navabi and McGraw-Hill Inc. END oring. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). END LOOP. RETURN accumulate.MULTIPLEXING AND DATA SELECTION FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. Z. FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 ). CHAPTER 8 34 . '0' is returned Necessary type and subtype definitions for the basic_utilities package Example signal declaration © 1999. • • • • • • Another complete example The oring resolution function for the BIT type operands OR for BIT is already defined If no drivers. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit.

Z. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • Will now model this circuit • An NMOS eight-to-one multiplexer • The CMOS version uses transmission gates instead of pass transistors CHAPTER 8 35 © 1999. .

. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION si ii t bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii. A block statement modeling a transmission gate • Disconnection is realized by block statements • If all drivers are disconnected actual hardware returns to 'Z' CHAPTER 8 36 © 1999. Z. END BLOCK.

ii is disconnected from t if si is '0' Use BUS to implement this behavior Default in wire function is specified as 'Z' This default is used if wiring is called with Null Last disconnection causes call to wiring with Null CHAPTER 8 37 © 1999. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK.MULTIPLEXING AND DATA SELECTION USE WORK. t <= GUARDED i3. Navabi and McGraw-Hill Inc. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK.FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS SIGNAL t : wired_qit BUS. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. Z. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK.basic_utilities. t <= GUARDED i5.ALL. . z <= t. END multiple_guarded_assignments. t <= GUARDED i0. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. t <= GUARDED i4. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. t <= GUARDED i6. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. t <= GUARDED i7. -. t <= GUARDED i1. t <= GUARDED i2. • • • • • Each ii connects to t if si is '1'.

. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • An NMOS half-register with multiplexed input • Modeling this circuit must take inverter input capacitance into account • t holds charge if all are disconnected • Circuit shows a register effect CHAPTER 8 38 © 1999. Z.

i4. Z. t <= GUARDED i3. i6. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK.ALL. t <= GUARDED i2. wired_qit ENTITY multiplexed_half_register IS PORT (i7.basic_utilities. t <= GUARDED i7. END multiplexed_half_register. END guarded_assignments. s4. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. -. i3. • • • • • • Use REGISTER to model retaining of last value No call is made to wiring upon last disconnection BUS and REGISTER are kind specification Signals with kind are guarded signals Guarded signals must be used on LHS of guarded assignments Ok to use unguarded signals on LHS of guarded assignments 39 © 1999.MULTIPLEXING AND DATA SELECTION USE WORK. i2. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. s7. z <= NOT t AFTER 8 NS. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. s6. t <= GUARDED i0. Navabi and McGraw-Hill Inc. s0 : IN qit. i0 : IN qit. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK.FROM PACKAGE USE: qit. -ARCHITECTURE guarded_assignments OF multiplexed_half_register IS SIGNAL t : wired_qit REGISTER. s1. t <= GUARDED i6. s5. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. z : OUT qit ). t <= GUARDED i1. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. i5. s3. s2. CHAPTER 8 . b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. t <= GUARDED i5. t <= GUARDED i4. i1.

--------------------------------------------------------------------------------------------- BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values. END. RHS Activation guard_expression t4 v4 Driver i t3 v3 t2 v2 t1 v1 0 guarded_lhs_signal • Turning off drivers from guarded signals • Guard expression controls driver contribution to the resolution function • Continuous contribution stops. . Navabi and McGraw-Hill Inc. END. even if a static value remains (if unguarded LHS) CHAPTER 8 40 © 1999. Z.MULTIPLEXING AND DATA SELECTION BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values.

Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION Before Last Disconnection After Last Disconnection v v f(v) v null v f(null) (a) BUS Kind v v f(v) v null f(v) (b) REGISTER Kind v v f(v) v v f(v) (c) Not Guarded Last disconnections: BUS kind. REGISTER kind. but holds static value at the time of disconnection • For unguarded. last disconnection calls resolution function with Null REGISTER. last disconnection is no different than others CHAPTER 8 41 © 1999. . last disconnection does not call the resolution function Unguarded. unguarded • • • • Disconnection disconnects if guarded BUS kind. disconnection disconnects.

z : OUT wired_qit BUS). END BLOCK. END GENERATE.ALL. qit_vector. .basic_utilities. END mux_n_to_1. wired_qit ENTITY mux_n_to_1 IS PORT (i. • • • • mutliple_guarded_assignments architecture of the mux_n_to_1 A general n-bit multiplexer Ports can be resolved signals BUS kind can also be specified. not REGISTER CHAPTER 8 42 © 1999. -ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j). Navabi and McGraw-Hill Inc.FROM PACKAGE USE: qit. END multiple_guarded_assignments. -. Z.MULTIPLEXING AND DATA SELECTION USE WORK. s : IN qit_vector.

END input_output. . ss. zz).MULTIPLEXING AND DATA SELECTION USE WORK. "000Z" AFTER 25 US. -ARCHITECTURE input_output OF mux_tester IS COMPONENT mux PORT (i. • A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1 • This entity is used as a four bit multiplexer CHAPTER 8 43 © 1999. END COMPONENT. Z. Navabi and McGraw-Hill Inc. s : IN qit_vector.ALL. BEGIN ii <= "1010" AFTER 10 US. "Z100" AFTER 20 US. ENTITY mux_tester IS END mux_tester.basic_utilities. FOR ALL : mux USE ENTITY WORK. ss <= "0010" AFTER 05 US. SIGNAL ii. mm : mux PORT MAP (ii. z : OUT wired_qit BUS).mux_n_to_1 (multiple_guarded_assignments). "0011" AFTER 30 US. SIGNAL zz : qit. ss : qit_vector (3 DOWNTO 0) := "0000". "1100" AFTER 15 US.

... "1100" . "0010" ....... ..... zz '0' 'Z' .. "000Z" ........ .. . '1' • Simulation results of the input_output architecture of the mux_tester • Simulation produces 'X' for two conflicting enabled inputs • Produces 'Z' when no inputs are enabled CHAPTER 8 44 © 1999. Z.. Navabi and McGraw-Hill Inc....... ... '0' .... "Z100" ................... ....... .. ss(3:0) "0000" .....MULTIPLEXING AND DATA SELECTION TIME (ns) 00000 +1δ δ 05000 +1δ δ 10000 +1δ δ 15000 +1δ δ 20000 +1δ δ 25000 +1δ δ 30000 +1δ δ ii(3:0) "0000" . ....................... . "0011" .. ...... '1' .... . '0' . .. 'X' ... ... '1' .... ........ "1010" ....

then will start using resolved.MULTIPLEXING AND DATA SELECTION Remaining issues: Disconnection Right and left INOUT More issues on resolutions. guarded. Z. Navabi and McGraw-Hill Inc. and other signal types • Several examples will follow CHAPTER 8 45 © 1999. guarded signals & resolved signals will de discussed • Will discuss other issues. .

t Connection is timed: After connection. t <= GUARDED ii AFTER n NS. Navabi and McGraw-Hill Inc. END ARCHITECTURE. .. SIGNAL t : wired_qit.MULTIPLEXING AND DATA SELECTION si ii ARCHITECTURE .... . DISCONNECT t : wired_qit AFTER 6 NS.. END ARCHITECTURE. BEGIN . Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE • Specify disconnection in the declaration • Use ALL for all signals of that type • Use OTHERS if some specified otherwise CHAPTER 8 46 © 1999.. t <= GUARDED ii AFTER n NS. . . . Z. . . SIGNAL t : wired_qit... it takes n NS for t to get ii ARCHITECTURE . BEGIN .

MULTIPLEXING AND DATA SELECTION Value used on the right hand side Value placed on driver of a t4 v4 t3 v3 t2 v2 t1 v1 0 Other Drivers a <= a AND b AFTER delay. Navabi and McGraw-Hill Inc. • Resolved signals on right and left hand sides • What you get is not what you put in • Others contribute to a resolved signal CHAPTER 8 47 © 1999. Z. .

x a z oring y b • Connecting INOUT ports require resolved signals • There are two drivers for each interconnection CHAPTER 8 48 © 1999. x : INOUT BIT) … ENTITY two (b : IN BIT. . .two PORT MAP (b. z). BEGIN c1 : ENTITY WORK. z).one PORT MAP (a. Navabi and McGraw-Hill Inc. . END connecting. c2 : ENTITY WORK. . . Z. ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT. y : INOUT BIT) … -ENTITY three IS END three. .MULTIPLEXING AND DATA SELECTION ENTITY one (a : IN BIT.

Navabi and McGraw-Hill Inc.STATE MACHINE DESCRIPTION Will use resolutions and guarded assignments in several examples • • • • State names indicate detected sequences Use resolutions & guarded blocks A simple 1011 Mealy detector A block statement for each state CHAPTER 8 49 © 1999. . Z.

ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset. z : OUT BIT). s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1.STATE MACHINE DESCRIPTION ENTITY detector IS PORT (x. Z. Navabi and McGraw-Hill Inc. END BLOCK s4. clk : IN BIT. END singular_state_machine. got1. SIGNAL current : one_of state REGISTER := reset. END BLOCK s2. use one_of CHAPTER 8 50 © 1999. FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT). s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset. END BLOCK clocking. END one_of. END detector. got101). • • • • VHDL description of 1011 detector Only one simultaneous active state Current receives four concurrent assignments Current must be resolved. . END BLOCK s1. got10. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10. END BLOCK s3. z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'.

END BLOCK s3. z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. goes to 4 when x = '1' CHAPTER 8 51 © 1999. END BLOCK clocking. END BLOCK s1. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. . s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. END BLOCK s4.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". END BLOCK s2. Navabi and McGraw-Hill Inc. Z. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'.ALL. s <= GUARDED "0000". • • • • • VHDL description of 1011 detector More than one state can simultaneously be active The last description does not allows multiple active states To remedy: use a signal for each state State 3 : goes to 1 when x = '0'.STATE MACHINE DESCRIPTION USE WORK. -.basic_utilities. END multiple_state_machine.

END BLOCK clocking...FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". s <= GUARDED "0000". s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'. goes to 4 when x = '1' • S must be resolved vector REGISTER kind • S <= GUARDED "0000". END BLOCK s3. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. END multiple_state_machine. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. END BLOCK s2. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN . s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. • State 3 : goes to 1 when x = '0'.ALL. Z. -. . .. Navabi and McGraw-Hill Inc.basic_utilities.. Causes removal of retained value upon last disconnection CHAPTER 8 52 © 1999.STATE MACHINE DESCRIPTION USE WORK.

z : OUT BIT). Navabi and McGraw-Hill Inc. Z. s(next_val(i. o <= GUARDED out_val(i.'0')) <= GUARDED '1' WHEN x='0' ELSE '0'. BIT) OF BIT. out_val. -ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. END oring. END BLOCK si. TYPE next_table IS ARRAY (1 TO n. x). BIT) OF INTEGER.STATE MACHINE DESCRIPTION ENTITY detector_m IS PORT (x. BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i. TYPE out_table IS ARRAY (1 TO n. s (i) <= GUARDED '0'. END BLOCK clocking. END LOOP.Fill in next_val. END multiple_moore_machine_1. END GENERATE.'1')) <= GUARDED '1' WHEN x='1' ELSE '0'. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). z <= o. RETURN accumulate. END detector_m. -. and s arrays SIGNAL o : ored_bit REGISTER. SUBTYPE ored_bit IS oring BIT. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. . • • • • A generic state machine A Moore sequence detector Specify transitions & outputting in constant tables Allows multiple machines in one CHAPTER 8 53 © 1999. GENERIC (n : INTEGER).clk : IN BIT.

--S6: -> S5. 6). --S1: -> S1. --S2: == z=0. '0'). --S5: == z=0. --S5: -> S5. S2 -(1 . x=1 -CONSTANT next_val : next_table := ( (1 . '0'). S6 -----.--S6: == z=1.Initial Active States: -SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010". 0 -('0' . ---------------------------------------------------------------------------------------------------------------------------------- • • • • Next state and output tables The next_val constant holds next state values The out_val constant holds the output values on the z output Initial starting states are set to '1' in the s vector CHAPTER 8 54 © 1999. 1 ----.STATE MACHINE DESCRIPTION ------------------------------------------------------------------Tables for programming the configurable Moore description -------------------------------------------------------------------. .Output Values: ----x=0. 4). --S4: -> S1. 3). --S3: == z=0. --S1: == z=0. S4 -(1 . --S3: -> S1. x=1 -CONSTANT out_val : out_table := ( ('0' . Navabi and McGraw-Hill Inc. S1 -(5 . --S4: == z=1. 6) ). '0').Next States: ----x=0. 0 -('0' . '1') ). 0 -('1' . 2). 1 -('0' . '1'). Z. --S2: -> S1. '0'). S3 -(1 . S6 -(5 . 0 -('1' . 1).

OPEN COLLECTOR GATES

VCC

a y b

GND

• • • •

Open collector NAND gate A two-input NAND gate, TTL 74LS03 SSI package Resolution functions are used in bussing Will use open collector to illustrate

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;

• VHDL description of a NAND gate with open collector output • Use qit type • Output is ‘Z’ and not ‘1’

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OPEN COLLECTOR GATES
ENTITY test_nand2 IS END test_nand2; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; TIME BEGIN (ns) aa bb assign_bits (aa, "qit_data", 500 NS); 0000 '0' '0' assign_bits (bb, "qit_data", 750 NS); 0010 ... ... c1: nand2 PORT MAP (aa, bb, yy); 1000 '1' ... 1500 ... '1' END input_output;
1512 2500 2510 3000 3012 3750 3760 4000 4500 4512 5000 5010 5500 5512 6000 6010 6750 6762 7500 7510 8250 8262 ... '0' ... 'Z' ... ... ... '0' '1' ... '0' ... 'Z' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... 'Z' ... ... ... ... ... '0' ... '1' ... '0' ... 'Z' ...

yy '0' 'Z' ... ... '0’ ... 'Z' ... '0' ... 'Z' ... ... '0' ... 'Z' ... '0' ... 'Z' ... '0' ... 'Z' ... '0'

• Testing the open-collector NAND gate • Test bench uses external data file • Output is either ‘0’ or ‘Z’, never ‘1’

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;

• VHDL description of TTL 74LS03 • Contains four open collector NAND gates • Will use in a design

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OPEN COLLECTOR GATES

a1 b1

a4 aa pull_up_1 y1 g4 a2 bb b2 pull_up_3 y4 yy g2 pull_up_2 y2 g3 a3 b3 g1 b4

y3

yy = (aa' . bb)’ . (bb' . aa)' = ( aa ⊕ bb )'

• • • •

Implementing XNOR logic using open collector NAND gates Using 74LS03 for implementing an XNOR pull_up3 has two drivers pull_up1 and pull_up2 must be turned to ‘0’, ‘1’ logic

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US, '0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;

• Wiring and testing XNOR function implemented by four open collector AND gates • pull_up_1 and pull_up_2 turn 0,Z to 0,1 • anded_qit resolution function implements wired logic

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OPEN COLLECTOR GATES
TIME (us) 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 aa '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' 'Z' 'Z' 'Z' 'Z' 'Z' 'Z' bb '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' 'Z' pull_up_1 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' pull_up_2 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' pull_up_3 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0'

• Results are observed at 2 us intervals • Simulation shows XNOR implementation • Pull up resolutions turn gate output 'Z' values to '1'

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THREE STATE BUSSING

u1 :

alu

u2 :

reg1

u3 : bus1 8

8 8

bus a

u4 :

unit1

u5 :

unit2

• • • •

A bussing system (bus_sys) Will use resolution functions for describing it A very common hardware for RT level descriptions Some components have three-state outputs some do not

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THREE STATE BUSSING

ENTITY alu IS PORT (… ; zout : out qit_vector (7 DOWNTO 0)); END alu; -ENTITY reg1 IS PORT (… ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); …); END unit1; -ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); …); END unit2;

• Interface of bus sources and destinations • Wired_qit_vector is used for those with three-state outputs • Connection of others must be through three-state constructs

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THREE STATE BUSSING

ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (…; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (…; busa); … u3 : busa <= bus1; … unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;…); … u5 : ENTITY WORK.unit2 PORT MAP (busa;…); … END partial;

• • • •

Partial VHDL description for bussing system example reg1 with three-state output directly drives the bus aluout goes through three-state constructs All required hardware structures are explicitly coded

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Std_logic BUSSING

std_ulogic for “standard unresolved logic” A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms

• Std_logic provides multi-value logic for most applications • No need for new user types • Most designers use the resolved type

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Z. Navabi and McGraw-Hill Inc.A GENERAL DATAFLOW CIRCUIT 8-bit Parallel data Count equal sequential data on parallel input lines. . 4-bit Count output Reset input • Seen dataflow primitives • Use dataflow for system description • A sequential comparator example CHAPTER 8 66 © 1999.

END sequential_comparator. BEGIN bin2int (x. VARIABLE t : BIT_VECTOR (x'RANGE). i := i + 1. END dataflow. IF i >= 2**x'LENGTH THEN i := 0.A GENERAL DATAFLOW CIRCUIT USE WORK. matches <= count. END inc. t). Z. RETURN t. SIGNAL count : BIT_VECTOR (3 DOWNTO 0). i). END BLOCK. int2bin (i. -. matches : OUT BIT_VECTOR (3 DOWNTO 0)). • • • • Dataflow description of the sequential comparator circuit inc function is unconstrained Save old data in buff Compares old and new CHAPTER 8 67 © 1999.basic_utilities. Navabi and McGraw-Hill Inc. END IF. int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0). clk. SIGNAL buff : BIT_VECTOR (7 DOWNTO 0). . BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data. -ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count.FROM PACKAGE USE: bin2int. reset : IN BIT.ALL.

'1' .. ...A GENERAL DATAFLOW CIRCUIT TIME (ns) 0000 +1δ δ 0200 0500 1000 +1δ δ 1200 1500 1700 2000 +1δ δ 2500 3000 +1δ δ +2δ δ 3200 3500 3700 4000 +1δ δ 4200 4500 5000 +1δ δ 5500 6000 +1δ δ +2δ δ 6500 7000 +1δ δ +2δ δ 7500 8000 +1δ δ +2δ δ 8500 reset '0' ..... ..... ....... .. '1' '0' ........ . ........ .............. .. ............. ...... ......... '1' '0' ..... "0010" ........... ........ ... ................................ "11111110" . . ....... ......... '1' '0' ...... ....... ....... ........... .......... ........ ... ........ ........ '1' data(7:0) "00000000" . "11110101" ............. . count(3:0) "0000" .. .............. .. "00010001" ... .. ........ ......... ... Z...... ............ . ..... ............. .. . ................... .. .... ..................................... ........ . ...... ... . . ..... ........ ...... ........ ... "0100" .... .. . . ... .......... ........... "11111110" ........ '0' .............. .. .......... ..... "00010001" .. '0' .... ....... . "10010110" .... "0000" .............. "0100" ... ............ ......... ............ "0001" .. ......................... .. "10010110" . ........ "0001" .... .... . clk '0' ....... ........ . ................................................ .. '1' '0' ... . . ... .. .... ... .. .... .... "10010110" .. '1' '0' ................ ............ ......... ........ . ...... ...... "0001" .... ..... ... ... . ......... . "11110101" ................... "0001" ... "11111110" ................................ . ............................... ... ........ "0011" . . ..... ... ... .. '1' '0' ..... . ..... "0010" ......... Navabi and McGraw-Hill Inc.. ... ... .... ..... "01010110" .. . .... "10010110" . . • matches shows count of matching data CHAPTER 8 68 © 1999... ............ ..... ....... ...... . ..... "0000" ............... "01010100" . .... ................. ....... .. "10010110" ......... ... ..... "0011" . ............... ...... ... buff(7:0) "00000000" .. matches "0000" "0000" ......... . '1' .

b : qit) RETURN qit. SUBTYPE wired_qit IS wiring qit. FUNCTION wire (a. SUBTYPE ored_qit IS oring qit. . TYPE anded_qit_vector IS ARRAY (NATURAL RANGE <>) OF anded_qit. -FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR. Navabi and McGraw-Hill Inc. TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit. TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. Z. SUBTYPE anded_bit IS anding bit. SUBTYPE anded_qit IS anding qit. -FUNCTION oring ( drivers : qit_vector) RETURN qit. SUBTYPE ored_bit IS oring BIT. -FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT. TYPE anded_bit_vector IS ARRAY (NATURAL RANGE <>) OF anded_bit. -FUNCTION wiring ( drivers : qit_vector) RETURN qit. -FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT.UPDATING BASIC UTILITIES PACKAGE basic_utilities IS . END basic_utilities. . TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. CHAPTER 8 69 © 1999. -FUNCTION anding ( drivers : qit_vector) RETURN qit.

RETURN accumulate. END LOOP. BEGIN RETURN qit_wire_table (a. FUNCTION wire (a. drivers(i)). END wiring. .'X'. FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. CHAPTER 8 70 © 1999. ('X'.'X'). BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. b). b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.'X'). Navabi and McGraw-Hill Inc. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i).'X'. Z. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). RETURN accumulate.'X'.'1'. END LOOP. END LOOP.'1'. END anding. RETURN accumulate.'1'. FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'. END wire.'Z'.'X')). .'X'). END oring. ('X'. . ('0'.UPDATING BASIC UTILITIES PACKAGE BODY basic_utilities IS .'0'.

END basic_utilities.UPDATING BASIC UTILITIES FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'. int2bin (i. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). END inc. END LOOP. END anding. END IF. RETURN accumulate. t). IF i >= 2**x'LENGTH THEN i := 0. . RETURN t. END oring. BEGIN bin2int (x. Navabi and McGraw-Hill Inc. i := i + 1. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). VARIABLE t : BIT_VECTOR (x'RANGE). FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. RETURN accumulate. • Resolution functions and inc function added to basic_utilities CHAPTER 8 71 © 1999. Z. END LOOP. i).

which are considered to be among the most important hardware related constructs in the VHDL language.SUMMARY This chapter presented signal assignment. and guarded signals. . guarded assignments. The resolution functions developed in this chapter are typical of the way buses function in a digital system. multiple drivers of signals. in general a resolved signal is a better representation of a circuit node. Navabi and McGraw-Hill Inc. A resolution function for a node can be written to match its technology-dependent behavior. were presented. or turning off a source. Guarded signal assignment and the concept of disconnection. • End Of Chapter 8 CHAPTER 8 72 © 1999. Z. and resolution functions. Although VHDL only requires resolution of signals with multiple concurrent sources. This prepared the way for describing resolution functions.

3 Simulation Report 9.1.4 A First Process Example 9.2 A Display Procedure 9.2. .5 MSI BASED DESIGN 9.5 Syntax Details of Process Statements 9.6 Postponed Processes 9.1.1.1 Declarative Part of a Process 9.5.2 Statement Part of a Process 9.1.4 Interface Handshaking 9. Z.3 Sensitivity List 9.7 Passive Processes 9.3 SEQUENTIAL WAIT STATEMENTS 9.1.6 SUMMARY • • • • • • Constructs for sequential descriptions Process statement is a key construct Assertion for behavioral checks Handshaking constructs Timing control Formatted I/O CHAPTER 9 1 © 1999.1.3.1 A Behavioral State Machine 9.2 Description of Components 9.5.3.3 Design Implementation 9.2.1.3 Implementing Handshaking 9.CHAPTER 9 BEHAVIORAL DESCRIPTION OF HARDWARE 9.1.3.1 Top Level Partitioning 9.2 ASSERTION STATEMENT 9.4.1 Sequential Use of Assertion Statements 9.4.4 FORMATTED ASCII I/O OPERATIONS 9.5.4.1 Basic Screen Output 9.8 Behavioral Flow Control Constructs 9. Navabi and McGraw-Hill Inc.2 Concurrent Assertion Statements 9.2 Two Phase Clocking 9.3.1 PROCESS STATEMENT 9.

PROCESS STATEMENT
Concurrent process statement PROCESS Always alive process declarative_part (non-signal) ...

BEGIN

Always active process statement_part (sequential) ...

END PROCESS;

Process statements describe hardware without much hardware details

• • • •

PROCESS: A concurrent statement, enclosing sequential statements Declarative part contains only variables and constants Use only sequential constructs

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PROCESS BEGIN Reapets forever,
S e q u e n t i a l

In zero time,

Unless suspended

END PROCESS;

• Unless a sequential body is suspended • It executes in zero real and delta time • It repeats itself forever

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ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;

• • • • •

First: a is scheduled for x Next: b is scheduled for y x and y receive values at the same time Both assignments occur a delta later Zero time between both scheduling

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ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;

• First: a is scheduled for x • Next: b is scheduled for y • y receives b sooner than x receiving a

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ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;

• • • • •

Assume x_sig is initially '0' Assignment of '1' to x_sig takes a delta Action_2 will be taken Variable x_var had to be declared inside the Process statement If x_var was used instead of x_sig, action_1 would be taken

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PROCESS STATEMENT

ARCHITECTURE … BEGIN … a <= b; … c <= d; … END …;

ARCHITECTURE … BEGIN … PROCESS (b) … a <= b; END PROCESS; … c <= d; … END …;

Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation Any signal assignment can be expressed by a process statement

• • • • • •

Can use a signal assignment in a sequential body On the left: events on b cause assignment Process is executed when an event occurs on b On the right: (b) is sensitivity list of process Process statement executes only once for every event on b Process suspends till next event on b occurs
© 1999, Z. Navabi and McGraw-Hill Inc.

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PROCESS STATEMENT

R 1D Q

C1 S

Q

A flip-flop will demonstrate assignments and flow in process statements

• Have modeled flip-flops with concurrent statements • A process statement is a powerful construct for such descriptions

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PROCESS STATEMENT

ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• • • •

Three concurrent processes dff process is sensitive to (rst, set, clk) Internal state receives proper value Events on state cause events on q and qb

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ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;

• Single process assigns values to q and qb • This description eliminates the δ delay of the last description • Less precise timing

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TIME (NS) 0 +1δ δ 6 200 206 +1δ δ 500 1000 1200 1400 1406 +1δ δ 1500 2000 2200 2400 2500 2506 +1δ δ 3000 3300 3500 3506 +1δ δ 4000

ss '0' ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

rr '0' ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ...

cc '0' ... ... ... ... ... '1' '0' ... ... ... ... '1' '0' ... ... '1' ... ... '0' ... '1' ... ... '0'

dd '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ...

q1 '0' ... ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ...

q2 '0' ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ... ...

qb1 '0' '1' ... ... ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ...

qb2 '0' ... '1' ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ... ...

• Simulation run compares flip-flop descriptions • The 3 process description has a δ delay • However, potential of more precise timing

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;

• This example uses a record for delay and flip-flop values • Logic value and delay are assigned to variables • Assignment to variables are done in zero time without the δ delay

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clk) VARIABLE state : BIT := ‘0’ BEGIN IF set = ‘1’ THEN state := ‘1’. Z. ELSEIF clk = -‘1’ AND clk’EVENT THEN state := d.PROCESS STATEMENT dff: PROCESS (rst. . sensitivity_list variable declaration process declarative part process statement ELSEIF rst = ‘1’ THEN state := ‘0’. qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3. END PROCESS dff. Navabi and McGraw-Hill Inc. set. sequential statement process statement part sequential statement sequential statement • Syntax details include sensitivity list CHAPTER 9 13 © 1999. q <= state AFTER (sq_delay + rq_delay + cq_delay)/3. END IF.

clk) BEGIN . dff : POSTPONED PROCESS(rst. becomes active becomes active clk set rst t1+1δ δ δ t1+2δ t1+3δ δ • Postponed process • Wait until the last event in a real time increment • Signal assignments can become postponed CHAPTER 9 14 © 1999. END. Z. set. . clk) BEGIN . . Navabi and McGraw-Hill Inc.PROCESS STATEMENT dff : PROCESS(rst. . END. . set. .

rst. Navabi and McGraw-Hill Inc. -USE WORK. set. BEGIN dff: PROCESS (rst.state AFTER sd. SHARED VARIABLE sd : bit_time := ('0'. . END PROCESS dff. rq_delay. cq_delay : TIME := 6 NS). sq_delay).PROCESS STATEMENT PACKAGE bt IS TYPE bit_time IS RECORD state : BIT.delay. END behavioral. ELSIF clk = '1' AND clk'EVENT THEN sd := (d. qb : OUT BIT). END IF. END PACKAGE bt.state AFTER sd. cq_delay). clk : IN BIT. q. clk) BEGIN q <= sd. PORT (d. • A passive process statement may appear in the entity statement part • Cannot make assignments to signals • This models the same flip-flop CHAPTER 9 15 © 1999. clk) BEGIN IF set = '1' THEN sd := ('1'. END ENTITY. set. qb <= NOT sd.ALL. 0 NS).delay.bt. END PROCESS dff_arch. rq_delay). set. Z. -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst. ENTITY d_sr_flipflop IS GENERIC (sq_delay. END RECORD. delay : TIME. ELSIF rst = '1' THEN sd := ('0'.

NEXT loop_label WHEN condition. Navabi and McGraw-Hill Inc. END IF.. Z. • • • • Loop is a sequential statement Example runs forever unless exited EXIT & NEXT control flow of loops EXIT & NEXT can be conditioned CHAPTER 9 16 © 1999... . . EXIT WHEN condition. END LOOP long_runing.PROCESS STATEMENT long_runing : LOOP .. IF x = 25 THEN EXIT.

. Z. sequential_statement_2.... sequential_statement_1. Navabi and McGraw-Hill Inc. CHAPTER 9 . . sequential_statement_5. END LOOP loop_1.PROCESS STATEMENT loop_1 : FOR i IN 5 TO 25 LOOP . sequential_statement_6. sequential_statement_3.. .... loop_2 : WHILE j <= 90 LOOP .. . WHILE are controlled forms of loop Can still use NEXT and EXIT The above NEXT statement causes looping to continue with statements 1 17 © 1999. . • • • • Conditional Next Statements in a Loop FOR. ... NEXT loop_1 WHEN condition_1. sequential_statement_4.... END LOOP loop_2. ...

MAKE SURE THAT assertion_condition IS TRUE. OTHERWISE REPORT "reporting_message". • • • • Use assert to flag violations Use assert to report events Can be sequential or concurrent Severity: FAILURE ERROR WARNING NOTE CHAPTER 9 18 © 1999. MAKE SURE THAT false IS TRUE. REPORT “reporting_message” SEVERITY severity_level. Navabi and McGraw-Hill Inc. Z. OTHERWISE REPORT "reporting_message" AND TAKE THE ACTION AT THIS severity_level. .ASSERTION STATEMENT ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level.

Navabi and McGraw-Hill Inc. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. qb <= NOT state. . q <= state. END IF.ASSERTION STATEMENT ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. set. • Conditions are checked only when process is activated • Make sure that set='1' AND rst='1' does not happen • Severity NOTE issues message CHAPTER 9 19 © 1999. END behavioral. END PROCESS dff. BEGIN dff: PROCESS (rst. Z. ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. IF set = '1' THEN state <= '1' AFTER sq_delay.

ASSERTION STATEMENT ASSERT Good conditions REPORT Violation of good conditions SEVERITY Level. • Good conditions may be too many to list • Good conditions = NOT (Bad conditions) • Easier to use NOT of unwanted cases CHAPTER 9 20 © 1999. ASSERT NOT things_that_should_not_happen REPORT a_message_that_bad_things_have_happened SEVIRITY action_to_take. Z. Navabi and McGraw-Hill Inc. .

. CHAPTER 9 21 © 1999... Navabi and McGraw-Hill Inc.ASSERTION STATEMENT clock setup time data hold time Setup and Hold time checks use assert statement and signal attributes • Use ASSERT to check setup and hold • ASSERT set_up_violation check REPORT.. • ASSERT hold_violation check REPORT. Z..

Navabi and McGraw-Hill Inc. then a setup time violation has occurred. Setup Check in VHDL (clock = '1' AND NOT clock'STABLE) AND (NOT data'STABLE (setup_time)) • When the clock changes. check for stable data • Check is placed after clock changes CHAPTER 9 22 © 1999. Z.ASSERTION STATEMENT clock setup time data hold time Setup Check in English When (clock changes from zero to 1). if (data input has not been stable at least for the amount of the setup time). .

Hold Check in VHDL (data'EVENT) AND (clock = '1') AND (NOT clock'STABLE (hold_time)) • When data changes while clock is '1'. Navabi and McGraw-Hill Inc. Z. check for stable clock • Check is placed after data changes CHAPTER 9 23 © 1999.ASSERTION STATEMENT clock setup time data hold time Hold Check in English When (there is a change on the data input) if the (logic value on the clock is '1') and the (clock has got a new value more recent than the amount of hold time). then hold time violation has occurred. .

ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. END d_sr_flipflop. qb <= NOT state. Navabi and McGraw-Hill Inc. rq_delay.ASSERTION STATEMENT ENTITY d_sr_flipflop IS GENERIC (sq_delay. clk : IN BIT. BEGIN dff: PROCESS (rst. PORT (d. rst. END PROCESS dff. BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING. END IF. qb : OUT BIT). set. • Using assertion statements for illegal Set-Reset combinations • Setup and Hold time violations • Concurrent and sequential assertion statements CHAPTER 9 24 © 1999. q <= state. ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING. set. END behavioral. cq_delay : TIME := 6 NS. . ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. hold : TIME := 4 NS). clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. IF set = '1' THEN state <= '1' AFTER sq_delay. Z. q. setup. -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'.

WAIT FOR 0 NS. WAIT UNTIL waiting_condition. WAIT statements for flow control of sequential statements • • • • • • Sequential statements. Is the same as WAIT ON a_signal UNTIL signal_is_true. Navabi and McGraw-Hill Inc. WAIT UNTIL event makes condition true. WAIT. Used for handshaking and delay modeling WAIT FOR real_time. Is the same as WAIT ON the_signal UNTIL expression_is_true. CHAPTER 9 25 . Z. WAIT UNTIL a_signal_is_true.SEQUENTIAL WAIT STATEMENTS WAIT FOR waiting_time. WAIT FOR. WAIT ON waiting_sensitivity_list. WAIT ON some_event UNTIL a_condition FOR some_time. WAIT. WAIT UNTIL expression_with_signal_and_variable_is_true. --"a long time" WAIT ON (event on a signal). --"forever" © 1999.

BEGIN … … … … END PROCESS. ARCHITECTURE … … BEGIN … PROCESS (a.. . b. b. c) . Z. Navabi and McGraw-Hill Inc. END ARCHITECTURE.SEQUENTIAL WAIT STATEMENTS ARCHITECTURE … … BEGIN … PROCESS . A process with sensitivity behaves as A process with WAIT ON at the end • WAIT ON at the end is equivalent to using sensitivity list • Cannot use WAIT in a process with sensitivity list • WAIT suspends a Process CHAPTER 9 26 © 1999. END PROCESS. c)... END ARCHITECTURE. BEGIN … … … WAIT ON (a..

SEQUENTIAL WAIT STATEMENTS Several examples will demonstrate WAIT statements in processes • A Moore 1011 detector • Can use WAIT in a Process statement CHAPTER 9 27 © 1999. . Z. Navabi and McGraw-Hill Inc.

END CASE. ELSE current <= got10. IF x = '0' THEN current <= got10. END moore_detector. clk : IN BIT. IF x = '1' THEN current <= got1. ELSE current <= reset. END behavioral_state_machine. WAIT FOR 1 NS. ELSE current <= reset. WHEN got1 => WAIT UNTIL clk = '1'. END IF. Z. IF x = '1' THEN current <= got1011. WHEN got10 => WAIT UNTIL clk = '1'. END IF. WHEN got101 => WAIT UNTIL clk = '1'. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. SIGNAL current : state := reset. ELSE current <= got1. . got101. ELSE current <= got10. and clocked CHAPTER 9 28 © 1999. got1011). • • • • VHDL Description of the 1011 Sequence Detector Using Process and Wait Statements Each choice corresponds to a state Each state can be independently timed. IF x = '1' THEN current <= got101. IF x = '1' THEN current <= got1. got10. WAIT UNTIL clk = '1'. Navabi and McGraw-Hill Inc. z : OUT BIT). END IF. END PROCESS. WHEN got1011 => z <= '1'. z <= '0'. got1. BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. END IF. END IF.

BEGIN PROCESS BEGIN CASE current IS . • • • • • WAIT for rising edge of clk Assign new state to current Wait for transaction on current Can use WAIT ON current 'TRANSACTION instead Timing check flexibility in each state CHAPTER 9 29 © 1999.. Navabi and McGraw-Hill Inc.. END PROCESS. END IF. END moore_detector.. z : OUT BIT).. got1011). SIGNAL current : state := reset. clk : IN BIT. got10. . END CASE.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. Z. . WHEN got1 => WAIT UNTIL clk = '1'. END behavioral_state_machine. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. ELSE current <= got1. WAIT FOR 1 NS. got1. IF x = '0' THEN current <= got10. got101. z <= '0'.

END behavioral_state_machine. ELSE current <= got10. ELSE current <= got1. got1. ELSE current <= reset. clk : IN BIT. . WHEN got10 => IF x = '1' THEN current <= got101. END PROCESS. got101. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. WHEN got101 => IF x = '1' THEN current <= got1011. END IF. BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. got10. WHEN got1011 => IF x = '1' THEN current <= got1. ELSE current <= got10. END CASE. got1011). END IF. WHEN got1 => IF x = '0' THEN current <= got10. SIGNAL current : state := reset. z : OUT BIT). Z. END moore_detector. z <= '1' WHEN current = got1011 ELSE '0'. END IF. END IF. Navabi and McGraw-Hill Inc. • A simple state machine description • Not much timing flexibility • Allows a single clock • But easy and covers most cases CHAPTER 9 30 © 1999. ELSE current <= reset. END IF. END IF.

.SEQUENTIAL WAIT STATEMENTS outputs next state Logic REG present state • Mealy machine detecting 101 • Use a style that separates logic and register parts • Also use an asynchronous reset CHAPTER 9 31 © 1999. Z. Navabi and McGraw-Hill Inc.

• VHDL description for a state machine with asynchronous reset • Most synthesis tools accept this style • Flexible in register part control CHAPTER 9 32 © 1999. r) BEGIN IF r = '1' THEN present <= a. ELSE nxt <= b. z : OUT BIT). SIGNAL nxt. Navabi and McGraw-Hill Inc. IF present = c AND x = '1' THEN z <= '1'. WHEN c => IF x = '0' THEN nxt <= a. . clk : IN BIT. END IF. END ENTITY. BEGIN reg : PROCESS (clk.SEQUENTIAL WAIT STATEMENTS ENTITY asynch_reset_detector IS PORT (x. -ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a. -logic : PROCESS (present. ELSE nxt <= b. END IF. ELSE nxt <= b. r. END IF. END behavioral. present : state. CASE present IS WHEN a => IF x = '0' THEN nxt <= a. END PROCESS. x) BEGIN z <= '0'. b. END IF. END IF. Z. WHEN b => IF x = '0' THEN nxt <= c. END PROCESS. c). END CASE. ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt.

. WAIT FOR 10 NS. WAIT FOR 480 NS.5 1. c2 <= '0'..5 2. Time 0. Navabi and McGraw-Hill Inc. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. END PROCESS phase2.. . Z.0 1.0 US c1 c2 10NS 10NS • Generation of the second phase of a two phase non-overlapping clocking • c2 is generated by phase2 process CHAPTER 9 33 © 1999.SEQUENTIAL WAIT STATEMENTS . . c2 <= '1'..

WAIT UNTIL accepted = '1'. accepted <= '1'. accepted <= '0'.start the following when ready to send data_lines <= newly_prepared_data. B accepts data • B releases A when data is picked CHAPTER 9 34 © 1999. • Systems A & B talk • A prepares data.start the following when ready to accept data WAIT UNTIL data_ready = '1'. -. --can use data_lines for other purposes System B: -. .SEQUENTIAL WAIT STATEMENTS data_lines system A data_ready valid data accepted system B Process Data System A: -. Z. data_ready <= '1'. Navabi and McGraw-Hill Inc. data_ready <= '0'.start processing the newly received data WAIT UNTIL data_ready = '0'.

. Z. Navabi and McGraw-Hill Inc.SEQUENTIAL WAIT STATEMENTS 4 SYSTEM I in_data in_ready 16 out_data A in_received out_ready out_received B • • • • Use handshaking mechanism in an interface A prepares 4 bit data. B needs 16 bit data Create interface system I Talk to A to get data. talk to B to put data CHAPTER 9 35 © 1999.

. and word_buffer for a_talk and b_talk communication CHAPTER 9 36 © 1999. -..SEQUENTIAL WAIT STATEMENTS ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0). -ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full.. buffer_picked : BIT := '0'. out_data : OUT BIT_VECTOR (15 DOWNTO 0). END waiting.When data is received. out_ready : OUT BIT)..When ready. • a_talk process & b_talk process also talk to each other • Use buffer_full. b_talk: PROCESS BEGIN . keep a count -. pass 16-bit data to b_talk . -. in_received. . END PROCESS b_talk. Navabi and McGraw-Hill Inc. in_ready.. collect 4 4-bit data.. END PROCESS a_talk. buffer_picked. send to B using proper handshaking .Wait for 16-bit data from a_talk -. SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0).Talk to A. Z. BEGIN a_talk: PROCESS BEGIN .. out_received : IN BIT. END system_i..

WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data. BEGIN WAIT UNTIL in_ready = '1'. buffer_full <= '1'. out_data <= word_buffer. b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'. WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data. END PROCESS b_talk. WAIT UNTIL out_received = '1'. WAIT UNTIL buffer_full = '0'. WAIT UNTIL buffer_picked = '1'. • a_talk gets data from A and talks to b_talk • b_talk talks to a_talk and sends data to B CHAPTER 9 37 © 1999. WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data. in_received <= '0'. buffer_picked <= '0'. buffer_full <= '0'. count := count + 1. Z. WAIT UNTIL in_ready = '0'. END CASE. buffer_picked <= '1'. . END PROCESS a_talk. in_received <= '1'.SEQUENTIAL WAIT STATEMENTS a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0. count := 0. out_ready <= '1'. WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data. CASE count IS WHEN 0 => NULL. Navabi and McGraw-Hill Inc. out_ready <= '0'. END IF.

Navabi and McGraw-Hill Inc. req ues t3 gra nt3 . Z.SEQUENTIAL WAIT STATEMENTS clock Arbiter req ues t1 gra nt1 req ues t2 gra nt2 38 • • • • • req ues t0 gra nt0 Bus arbiter interface Simplified for this first example Synchronized arbitration A request input stays asserted until granted A request input is granted only one clock cycle of bus use CHAPTER 9 © 1999.

clock : IN BIT). END PROCESS wait_cycle. Z. FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000". END behavioral. • Bus arbiter description • Check all requests after the falling edge of the clock • Because of the 20 NS wait. END IF. ELSE grant (i) <= '0'.SEQUENTIAL WAIT STATEMENTS ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0). -ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. grant (i) <= '1'. grant : BUFFER BIT_VECTOR (3 DOWNTO 0). END arbiter. WAIT ON clock. END LOOP. process sensitivity cannot be used CHAPTER 9 39 © 1999. END IF. Navabi and McGraw-Hill Inc. .

g. clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk. END GENERATE. CONSTANT t : TIME := 1 US. END io. r(i) <= '1'. . 15 US. WAIT UNTIL clk = '0'. CONSTANT delays : time_array := (4 US. 3 US. SIGNAL r. Navabi and McGraw-Hill Inc. clk). r(i) <= '0'.arbiter PORT MAP (r. sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i). • Testing the arbiter • Four processes for generating data are generated • The time_array constant specifies timing requests coming from a source CHAPTER 9 40 © 1999. Z. TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME. -ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT. BEGIN arb : ENTITY WORK. 8 US). WAIT UNTIL g(i) = '1'. g : BIT_VECTOR (3 DOWNTO 0).SEQUENTIAL WAIT STATEMENTS ENTITY arbtest IS END arbtest. END PROCESS.

. Z.SEQUENTIAL WAIT STATEMENTS S2P da tar ea dy ov err un fra me _e rro r pa ral lel _o ut serial rec eiv ed 8 A 10 bit frame reading begins start bit data bits stop bit • • • • • Another example using WAIT statements Serial_to_parallel interface RS232 frame with one start bit and one stop bit Framing error. Navabi and McGraw-Hill Inc. if stop bit is not seen Overrun error if start bit appears too soon CHAPTER 9 41 © 1999.

parallel_out <= buff. • • • • • Serial2parallel VHDL description Two concurrent processes One waits for prepared data to be picked up (collect). WAIT FOR full_bit. dataready : BUFFER qit. IF dataready = '1' THEN dataready <= '1'. buff (count) := serial. dataready <= '0'. FOR count IN 0 TO 7 LOOP WAIT FOR full_bit. END waiting. WAIT ON dataready. WAIT FOR half_bit. Z. overrun <= '0'. BEGIN WAIT UNTIL serial = '0'. END LOOP. overrun <= '1'. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US. received : IN qit. ELSE WAIT UNTIL received = '0'. IF serial = '0' THEN too_fast : PROCESS frame_error <= '1'.SEQUENTIAL WAIT STATEMENTS ENTITY serial2parallel IS GENERIC (bps : INTEGER). END PROCESS too_fast. WAIT UNTIL received = '1'. CONSTANT half_bit : TIME := (1E6/REAL(bps))/2. PORT (serial. IF dataready = '1' THEN ELSE WAIT UNTIL serial = '0'. END IF.0 * 1 US. while The other waits for untimely serial data to arrive (too_fast) WAIT statements are used in both processes 42 © 1999. frame_error <= '0'. Navabi and McGraw-Hill Inc. BEGIN WAIT UNTIL serial = '1'. overrun. END IF. CHAPTER 9 . END IF. END PROCESS collect. -ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS --VARIABLE buff : qit_vector (7 DOWNTO 0). frame_error : OUT qit. END serial2parallel.

Z. to write data into a WRITELINE procedure. . to check the end of a file Examples will demonstrate TEXTIO package and its applications • Only CHARACTERS are handled • All predefined standard types are converted to CHARACTERS • Subprograms are overloaded for all standard types CHAPTER 9 43 © 1999.FORMATTED ASCII I/O OPERATIONS TEXTIO package is in the STD library TEXTIO contains: LINE type. a pointer to STRING TEXT file type. to read data from a line a line WRITE procedure. of CHARACTER type INPUT. to read a line from file READ procedure. Navabi and McGraw-Hill Inc. to write line to file READ procedure. OUTPUT files for standard device IO READLINE procedure. to read data from a line a line ENDFILE function.

read a line of file f into buffer l READ(l. -. APPEND_MODE).writes the value v to LINE l WRITELINE(f.. FILE_OPEN (f. REAL.. FILE f : TEXT IS “input. FILE_OPEN (f.). STRING. “input.returns TRUE if the end of f • READ and WRITE procedures are valid for: BIT.. Navabi and McGraw-Hill Inc. “output. and unit if v is of type TIME CHAPTER 9 44 © 1999. FILE_CLOSE (f). and TIME • Other parameters of these procedures include orientation. v. .writes l to file f ENDFILE(f) -.txt”.txt”.. CHARACTER. INTEGER. -. Z. WRITE_MODE). “output. BIT_VECTOR.FORMATTED ASCII I/O OPERATIONS VARIALE I : LINE. . l).txt”. READ_MODE). .txt”. BOOLEAN. FILE_OPEN (f. FILE f : TEXT OPEN READ_MODE IS “input. l) -.reads a value v of its type from l WRITE(l.) -.txt”. v. size. READLINE(f. FILE f : TEXT.

• A resolution function that writes its active drivers each time it is called • New code is highlighted • Unix device tty is the standard output • Can use OUTPUT. got101). . FUNCTION one_of (sources : state_vector) RETURN state IS VARIABLE l : LINE.. END LOOP.TEXTIO. WRITELINE (flush. defined in VHDL for the standard output • INPUT and OUTPUT work in all operating systems CHAPTER 9 45 © 1999. got10. Z. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. 7). TYPE state IS (reset. FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty".ALL..FORMATTED ASCII I/O OPERATIONS USE STD. Navabi and McGraw-Hill Inc. LEFT. l). . got1. RETURN sources(sources'LEFT). BEGIN FOR i IN sources'RANGE LOOP WRITE (l. END one_of. state'IMAGE(sources(i)).

BEGIN WRITE (l. 3). WRITELINE (flush. END display. value1. value2. value2. RIGHT. 8. 0). IF value1'EVENT AND value2'EVENT THEN WRITE (l. filler. WRITE (l. 3). Z. LEFT. VARIABLE filler : STRING (1 TO 3) := " . WRITE (l.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. VARIABLE l : LINE. Navabi and McGraw-Hill Inc. l). RIGHT. RIGHT. ELSIF value1'EVENT THEN WRITE (l. NS). END IF.. RIGHT. . RIGHT. value1. 3). ELSE WRITE (l. NOW. LEFT. 3). filler. 0).". • A display procedure for writing time and events • New values are listed • Filler is used for signal values that do not change CHAPTER 9 46 © 1999. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". WRITE (l.

Navabi and McGraw-Hill Inc. END PROCESS phase2. RIGHT.ALL. ELSE WRITE (l. VARIABLE filler : STRING (1 TO 3) := " . c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. USE STD. RIGHT. RIGHT. 3). 0). LEFT. • Call the display procedure anytime a clock phase changes • This procedure is also called once at the beginning of simulation CHAPTER 9 47 © 1999. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. IF value1'EVENT AND value2'EVENT THEN WRITE (l. filler. END IF.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. WAIT FOR 480 NS. ELSIF value1'EVENT THEN WRITE (l. 0). END display. display (c1. c2 <= '1'. END input_output. WRITE (l. c2 <= '0'. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". . RIGHT. value1. BEGIN SIGNAL c2 : BIT := '0'. NS).. LEFT. 3). filler.".TEXTIO. 3). value2. NOW. WRITE (l. BEGIN WRITE (l. WAIT FOR 10 NS. 8. Z. RIGHT. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. value2. WRITELINE (flush. c2). l). value1. 3). WRITE (l. VARIABLE l : LINE. ENTITY two_phase_clock IS END two_phase_clock.

. 3). END displaying. RIGHT. 0). END IF. value1. 3). l). WRITELINE (flush. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. ELSIF value1'EVENT THEN WRITE (l. BEGIN WRITE (l. value2. Navabi and McGraw-Hill Inc.FORMATTED ASCII I/O OPERATIONS PACKAGE displaying IS PROCEDURE display (SIGNAL value1. 3).". FILE flush : TEXT). LEFT. filler. END displaying. value2. LEFT. NOW. value2 : BIT. END display. value1. RIGHT. WRITE (l. RIGHT. RIGHT. IF value1'EVENT AND value2'EVENT THEN WRITE (l. NS). Z. 0). WRITE (l. . VARIABLE l : LINE. 8. value2 : BIT. filler. FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " . RIGHT. ELSE WRITE (l. • A procedure for writing in an already open file • A file of type TEXT is passed to this procedure • This goes in our new displaying package CHAPTER 9 48 © 1999. 3). WRITE (l.

c2. USE STD. END display.. value2 : BIT. END displaying. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. SIGNAL c2 : BIT := '0'. Z. data).ALL. END displaying. FILE flush : TEXT). WAIT FOR 480 NS.displaying. END PROCESS phase2. value2 : BIT. USE WORK. • Passing an open file to a procedure • File declaration takes place in the declarative part of an architecture • File remains open after being written into • Writing can continue elsewhere CHAPTER 9 49 © 1999. ENTITY two_phase_clock IS END two_phase_clock. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. .TEXTIO..out". c2 <= '0'. BEGIN display (c1. PACKAGE displaying IS PROCEDURE display (SIGNAL value1. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1.TEXTIO. FILE flush : TEXT) IS . c2 <= '1'. FILE data : TEXT OPEN WRITE_MODE IS "clock.FORMATTED ASCII I/O OPERATIONS USE STD. END input_output.ALL.ALL. WAIT FOR 10 NS. Navabi and McGraw-Hill Inc.

. 1 0 . 1 0 . • Output file generated by the input_output architecture • File closes at the end of simulation CHAPTER 9 50 © 1999... . Navabi and McGraw-Hill Inc.... 1 0 . . ..FORMATTED ASCII I/O OPERATIONS 0 500 510 990 1000 1500 1510 1990 2000 2500 2510 2990 3000 3500 3510 3990 4000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns . . 1 0 ... 1 0 ...... . . 0 .. . 1 0 .. Z. . 1 0 . 1 0 ..

hi_value. SIGNAL print_tick : BIT := '0'. WRITELINE (flush. IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN append_wave_slice (c1). IS WAIT FOR 10 NS. RIGHT. calls the append_wave_slice procedure Buffer l is visible in the procedure. RIGHT. c2 <= '1'. c1.ALL.FORMATTED ASCII I/O OPERATIONS c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US USE STD. l). VARIABLE header : STRING (1 TO 18) := " c1 c2 ". c2 <= '0'. WRITELINE (flush. 5). VARIABLE hi_to_lo : STRING (1 TO 3) := "+-. RIGHT. append_wave_slice (c2). NS). IF NOW = 0 US THEN VARIABLE lo_to_hi : STRING (1 TO 3) := ". print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED. appending is done to this line CHAPTER 9 51 © 1999. lo_value. hi_to_lo. NOW. lo_to_hi. IF s = '1' THEN WRITE (l. RIGHT.". 5).-+". CONSTANT print_resolution : TIME := 5 NS. END IF. SIGNAL c1 : BIT := '1'. BEGIN VARIABLE hi_value : STRING (1 TO 3) := " |". SIGNAL c2 : BIT := '0'. Navabi and McGraw-Hill Inc. WRITE (l. END IF. LEFT. header. END IF. VARIABLE l : LINE. FILE flush : TEXT OPEN WRITE_MODE IS "clock4. ELSE END input_output. ELSE ENTITY two_phase_clock IS END two_phase_clock. . writing: PROCESS (print_tick. 0). c2) • • • • Generating an ASCII plot file 5 NS print resolution reports of the two-phase clock description Process wakes up. Z. 8. BEGIN END PROCESS phase2. BEGIN END IF.out". END PROCESS writing. c1. WRITE (l. WAIT FOR 480 NS. l). END PROCEDURE append_wave_slice. PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| ". phase2: PROCESS -BEGIN ARCHITECTURE input_output OF two_phase_clock WAIT UNTIL c1 = '0'. ELSE WRITE (l. 5).TEXTIO. RIGHT. ELSE WRITE (l. 5). IF s = '1' THEN WRITE (l.

Navabi and McGraw-Hill Inc.. | | | | | | c2 | | | | | | | .FORMATTED ASCII I/O OPERATIONS c1 480 485 490 495 500 505 510 510 515 520 525 .. . Z. "| " for '0' Write "+-. ns ns ns ns ns ns ns ns ns ns ns | | | | +-." for 1 to 0 Write ".-+ | | | • • • • • Plot generated by the ploting process Plotting is activated every 5 NS Write " |" for '1'.-+" for 0 to 1 CHAPTER 9 52 © 1999.

74LS85. Navabi and McGraw-Hill Inc. will present a top-down design with MSI parts • • • • Sequential comparator circuit Design based on MSI parts 74LS377. . 74LS163 Assume these parts are available CHAPTER 9 53 © 1999.MSI BASED DESIGN 8 data_in clk clear_bar load_bar count_in 4 sequential comparator 4 count Produces modulo-16 count of consecutive matching data Closing the chapter. Z.

Navabi and McGraw-Hill Inc. Z.MSI BASED DESIGN sequential comparator 8-bit register 8-bit comparator 4-bit counter 4-bit comparator 4-bit comparator • Partition the circuit into smaller components • Partition until library components or synthesizable parts are reached • Will use top-down technique in designing a CPU in Chapter 10 CHAPTER 9 54 © 1999. .

Navabi and McGraw-Hill Inc. comparator. . Z. 5D [1] [2] [4] [8] • Standard MSI parts • Register.3. counter CHAPTER 9 55 © 1999.MSI BASED DESIGN 74LS377 74LS85 74LS163 5CT=0 CTRDIV16 M1 M2 3CT=15 G3 G4 C5/2.4+ GI 1C2 < = > P P<Q P=Q P>Q Q 2D 1.

a_lt_b <= lt AFTER prop_delay. END ls85_comparator. ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay. a_eq_b. a_gt_b. PORT (a.MSI BASED DESIGN USE WORK.basic_utilities. Z. . a_lt_b <= '0' AFTER prop_delay. • 74LS85. Navabi and McGraw-Hill Inc. a_eq_b <= eq AFTER prop_delay. a_eq_b <= '0' AFTER prop_delay. -ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a. b : IN qit_vector (3 DOWNTO 0). eq.ALL. END PROCESS. a_eq_b <= '0' AFTER prop_delay. ordering for array operands • Default delays can be configured later CHAPTER 9 56 © 1999. four bit comparator • Relational operators. lt : IN qit. END behavioral. ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay. gt. a_lt_b : OUT qit). eq. END IF. a_lt_b <= '1' AFTER prop_delay. gt. ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS). b. lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay.

ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS). .basic_utilities. -ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN. Z. d8 : IN qit_vector (7 DOWNTO 0). BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0').MSI BASED DESIGN USE WORK. Navabi and McGraw-Hill Inc. END ls377_register. q8 : OUT qit_vector (7 DOWNTO 0)). END dataflow. q8 <= GUARDED d8 AFTER prop_delay. clocked register • Default delays can be used or reconfigured CHAPTER 9 57 © 1999.ALL. g_bar : IN qit. PORT (clk. • 74LS377.

MSI BASED DESIGN USE WORK. END behavioral. IF (internal_count = "1111" AND ent = ‘1’) THEN rco <= '1' AFTER prop_delay. abcd : IN qit_vector (3 DOWNTO 0). BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000". rco : OUT qit). Navabi and McGraw-Hill Inc. q_abcd : OUT qit_vector (3 DOWNTO 0). ELSE rco <= '0'. END IF. -ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000". END PROCESS counting. ent : IN qit. enp. PORT (clk. . ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS).basic_utilities. q_abcd <= internal_count AFTER prop_delay. ELSIF (ld_bar = '0') THEN internal_count := abcd. END IF. END ls163_counter. clr_bar. END IF. • 74LS163. ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count). ld_bar.ALL. four bit synchronous counter • Default delays can be overwritten CHAPTER 9 58 © 1999. Z.

MSI BASED DESIGN LS377_register(behavioral) clk clear_bar load_bar data_in 8 4 8 clk d8 reg: d_register 4 q8 4 standard sequential comparator(structural) LS163_counter(behavioral) a b gt eq lt cmp_hi: comparator a_gt_b a_eq_b a_lt_b clk clr_bar load_bar enp ent abcd cnt: counter rco 4 q_abcd count g_bar prop_delay prop_delay 4 a b count_in gt eq lt 4 cmp_lo: comparator a_gt_b a_eq_b prop_delay a_lt_b prop_delay 15NS 18NS LS85_comparator(behavioral) 22NS • Design is based on available parts • Configure to use LS library. specify delay CHAPTER 9 59 © 1999. Z. Navabi and McGraw-Hill Inc. .

ld_bar. clear_bar. BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING. lt_i. cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0). count. END COMPONENT. old_data (7 DOWNTO 4). SIGNAL old_data : qit_vector (7 DOWNTO 0). b : IN qit_vector (3 DOWNTO 0). clear_bar. Navabi and McGraw-Hill Inc.MSI BASED DESIGN USE WORK. SIGNAL vdd : qit := '1'. lt_i). lt : IN qit. END COMPONENT. clr_bar. a_lt_b : OUT qit). OPEN. SIGNAL compare_out : qit. eq. a_eq_b. END structural. compare_out. COMPONENT counter PORT (clk. enp. OPEN).basic_utilities. count_in : IN qit_vector (3 DOWNTO 0). END sequential_comparator. SIGNAL gnd : qit := '0'. eq_i. gnd. eq_i. OPEN). END COMPONENT. abcd : IN qit_vector (3 DOWNTO 0).ALL. BEGIN reg: d_register PORT MAP (clk. old_data). -ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk. old_data (3 DOWNTO 0). rco : OUT qit). lt_i : qit. • Design is based on available parts • Assert statement in the entity declaration • Configure to use LS library. gt_i. load_bar : IN qit. eq_i. COMPONENT comparator PORT (a. d8 : IN qit_vector (7 DOWNTO 0). Z. q_abcd : OUT qit_vector (3 DOWNTO 0). vdd. vdd. cnt: counter PORT MAP (clk. clk. count : OUT qit_vector (3 DOWNTO 0) ). gt_i. ent : IN qit. . g_bar : IN qit. load_bar. q8 : OUT qit_vector (7 DOWNTO 0)). SIGNAL gt_i. a_gt_b. ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0). specify delay CHAPTER 9 60 © 1999. count_in. gnd. data_in. compare_out. cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4). gt. gnd.

. FOR ALL : comparator USE ENTITY WORK.MSI BASED DESIGN USE WORK. CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK. END standard.ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS). Navabi and McGraw-Hill Inc. END FOR.ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS). END FOR. Z. END FOR. • Configuring the structural architecture of the sequential_comparator • Configuration declaration binds to 74LS parts • Generic values overwrite those of the 74LS parts CHAPTER 9 61 © 1999. END FOR.ALL.ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS). FOR cnt : counter USE ENTITY WORK.

ENTITY test_sequential_comparator IS END test_sequential_comparator. END COMPONENT. Z. "1011" AFTER 40 US. SIGNAL cnt_out : qit_vector (3 DOWNTO 0). clear_bar. mfi : seq_comp PORT MAP (data. '0' AFTER 50 US. ld_bar : qit. cl_bar. SIGNAL cnt : qit_vector (3 DOWNTO 0). ld_bar. • Testbench verifies behavior • Configuration specification associates mfi: seq_comp with the standard configuration declaration CHAPTER 9 62 © 1999. load_bar : IN qit. count : OUT qit_vector (3 DOWNTO 0) ). SIGNAL ck. cl_bar. count_in : IN qit_vector (3 DOWNTO 0). Navabi and McGraw-Hill Inc. cnt. ld_bar <= '1'. . "10101100" AFTER 5 US. "01010100" AFTER 25 US. "01110111" AFTER 3 US. "0111" AFTER 55 US. data <= "00000000". clk. SIGNAL data : qit_vector (7 DOWNTO 0). FOR mfi : seq_comp USE CONFIGURATION WORK.standard.ALL.MSI BASED DESIGN USE WORK. '0' AFTER 60 US. ck. '1' AFTER 55 US. -ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0). cnt_out). END input_output. BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck. cnt <= "1111".basic_utilities. cl_bar <= '1'.

Navabi and McGraw-Hill Inc. • End Of Chapter 9 CHAPTER 9 63 © 1999. Various forms of wait statements were extensively used in these descriptions. Z. and file I/O. Although behavioral level constructs of VHDL provide a convenient method of describing very complex hardware. We then showed how process statements are used to describe controlling hardware. . In the first part of the chapter. handshaking. syntax and semantics for various forms of this construct were described. Behavioral descriptions can be read and understood by non-technical managers and others who are not very familiar with VHDL.SUMMARY This chapter presented descriptions of hardware at the behavioral level and discussed how a process statement can be used to describe the main functionality of a module. a hardware designer can completely describe a digital circuit without having to use these constructs.

1 Timing and Clocking 10.2 Global View of Parwan Components 10.3 BEHAVIORAL DESCRIPTION OF PARWAN 10.3 General Description Methodology 10.2 Synthesizability 10.1 CPU Control Signals 10.3.6 A TEST BENCH FOR THE PARWAN CPU 10.2.5.5 Data Section of Parwan 10.2 Instruction Set 10.4 Programming in Parwan Assembly 10.2.5. Z.4 Description of Components 10.5 DATAFLOW DESCRIPTION OF PARWAN 10.2 Packages 10.7.4.3 Interface Description of Parwan 10.7 A MORE REALISTIC PARWAN 10.6 Control Section of Parwan 10.5.3.3. .4 Parwan Behavioral Architecture 10.1 Data and Control Partitioning 10.2 Timing of Data and Control Events 10.1 Interconnection of Components 10.4.7.4 PARWAN BUSSING STRUCTURE 10.4.3.8 SUMMARY CHAPTER 10 1 © 1999.5.2 PARWAN CPU 10.1 DEFINING A COMPREHENSIVE EXAMPLE 10.1 Memory Organization of Parwan 10.2.3 Instruction Format 10.CHAPTER 10 CPU MODELING AND DESIGN 10.3 Instruction Execution 10.3 Hardware Modifications 10. Navabi and McGraw-Hill Inc.7 Wiring Data and Control Sections 10.5.7.2.5.5.

and show its hardware details • • • • • General Layout of Parwan PARWAN. Z. 12-bit Address Primarily designed for educational purposes Includes most common instructions CHAPTER 10 2 © 1999. PAR_1.DEFINING A COMPREHENSIVE EXAMPLE MAR PC IR SR AC ALU SHU Controller Will define a CPU describe it in VHDL. 8-bit Data. A Reduced Processor Simple 8-bit CPU. . Navabi and McGraw-Hill Inc.

page 1 .2:FF MEMORY: 5 4 3 2 page 0 .0:FF 1:00 .F:FF page 14 . . Z. Navabi and McGraw-Hill Inc. . page 15 .1:FF 2:00 . . . . .E:FF F:00 . 1 0 Offset E:00 .PARWAN CPU 7 6 1 1 1 0 0 9 Page 0 8 0 0 7 6 0 5 0 4 0 0 3 2 0 1 0 0 0:00 . • • • • • Page and Offset Parts of Parwan addresses Memory divided into pages Pages of 256 bytes Address has page and offset part Uses memory mapped IO CHAPTER 10 3 © 1999. page 2 .

(12 bits) direct/indirect LDA. BRA_V. CMA. STA PAGE Address. ADD. ASR • • • • Three groups of instructions Full Address instructions include page and offset Page address instructions include offset No Address instructions occupy a single byte CHAPTER 10 4 © 1999. CLA. . ASL. AND. CMC. (8 bit) JSR. SUB. BRA_C.PARWAN CPU FULL Address. Z. Navabi and McGraw-Hill Inc. BRA_Z. JMP. BRA_N NO Address NOP.

Navabi and McGraw-Hill Inc. Z. Load and store operations Arithmetic & logical operations jmp and branch instructions CHAPTER 10 5 © 1999. .Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Brief Description Load AC w/(loc) AND AC w/(loc) Add (loc) to AC Sub (loc) from AC Jump to adr Store AC in loc Subroutine to tos Branch to adr if V Branch to adr if C Branch to adr if Z Branch to adr if N No operation Clear AC Complement AC Complement carry Arith shift left Arith shift right Address Bits 12 12 12 12 12 12 8 8 8 8 8 - Address Scheme FULL FULL FULL FULL FULL FULL PAGE PAGE PAGE PAGE PAGE NONE NONE NONE NONE NONE NONE Indirect Address YES YES YES YES YES YES NO NO NO NO NO NO NO NO NO NO NO Flags Use -------c--c----------v---c---z---n ----------c-------- Flags Set --zn --zn vczn vczn -----------------------------zn -c-vczn --zn • • • • Summary of Parwan instructions.

.PARWAN CPU Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Opcode Bits 765 000 001 010 011 100 101 110 111 111 111 111 111 111 111 111 111 111 D/I Bit 4 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 0 0 0 0 0 0 Bits 3210 Page adr Page adr Page adr Page adr Page adr Page adr ---1000 0100 0010 0001 0000 0001 0010 0100 1000 1001 • Parwan instruction opcodes • CPU contains V C Z N flags • Instructions use and/or influence these flags CHAPTER 10 6 © 1999. Z. Navabi and McGraw-Hill Inc.

SUB. AND. SUB. CMA. LDA. ASR ADD. CMC BRA_Z BRA_N • Arithmetic instructions influence all flags • Branch instructions use corresponding flags • Shift instructions influence all flags CHAPTER 10 7 © 1999. ASL. AND. SUB. ASL. Navabi and McGraw-Hill Inc. Z.PARWAN CPU influence ADD. SUB. . ASL. CMC ADD. LDA. ASL ADD. SUB. ASR use V C Z N BRA_V BRA_C. ADD. CMA.

Z. .complete address pg: loc opc page pg: loc+1 offset • • • • • Addressing in full-address instructions Full address instructions use two bytes Right hand side of first byte is page Second byte contains offset Bit 4 is direct/indirect [0/1] indicator CHAPTER 10 8 © 1999. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z. .PARWAN CPU complete address pg: loc jsr or branch pg: loc+1 offset • • • • • Addressing in page-address instructions Page address instructions use two bytes All of first byte is used by opcode Page part of address uses current page Second byte is the offset CHAPTER 10 9 © 1999.

Navabi and McGraw-Hill Inc.. BRANCH TO 6A if carry is set c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A • Branching is done within current page only • A branch instruction CHAPTER 10 10 © 1999.PARWAN CPU MEMORY .... BRA_C 6A 5:0D 5:0E 5:0F 11110100 6A . . Z.

Z.... before and after jsr Store jsr return address at tos Begin subroutine at tos+1 Use indirect jmp to tos for return from subroutine CHAPTER 10 11 © 1999. ..PARWAN CPU MEMORY PC-> 5:11 5:12 5:13 MEMORY 5:11 5:12 5:13 . 5:33 PC-> 5:34 . 5:33 5:34 00000000 SUBROUTINE CODE ..... Navabi and McGraw-Hill Inc... JSR 3 3 INSTR AFTER JSR .. A F T E R J S R • • • • • An example for the execution of jsr Memory and pc. 1 3 SUBROUTINE CODE .. JSR 3 3 INSTR AFTER JSR ... . . 5:55 5:56 5:57 JMP Indirect 3 3 B E F O R E J S R 5:55 5:56 5:57 JMP Indirect 3 3 .....

Z. Navabi and McGraw-Hill Inc. Indirect addressing affects offset only To obtain actual address full addressing is used To obtain data page addressing is used CHAPTER 10 12 © 1999. .PARWAN CPU Indirect address Actual address Data Any page and offset Same page Indirecting effects offset operand 0:25 opc 1 6 6:1F 1 8 0:26 3 5 6:35 1 F • • • • An example for indirect addressing in Parwan.

get partial sum -.go for next byte -.add bytes -.load count -.store count back -. Z.load 25 in 4:00 -. . Navabi and McGraw-Hill Inc.increment pointer -.load 10 in 4:01 -.load pointer -.adding completed • • • • • An example program for Parwan CPU A program to add 10 bytes Use location 4:00 for data pointer Use location 4:01 for counter Constant 1 in 4:02 is used for +1 and -1 CHAPTER 10 13 © 1999.store partial sum -. i sta 4:03 lda 4:00 add 4:02 sta 4:00 lda 4:01 sub 4:02 bra_z sta 4:01 lda 4:03 jmp 0:17 nop -.clear accumulator -.decrement count :2D -.PARWAN CPU 0:15 0:16 0:17 0:19 0:1B 0:1D 0:1F 0:21 0:23 0:25 0:27 0:29 0:2B 0:2D cla asl add.load 01 in 4:02 -.clears carry 4:00 -.store pointer back -.end if zero count -.

USE par_library. -ENTITY par_central_processing_unit IS .. USE cmos.basic_utilities. Z.ALL.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos..ALL. Coding for the behavioral description of Parwan will be presented. -LIBRARY par_library.par_parameters. • Packages used will be described • A single component will describe all of Parwan CHAPTER 10 14 © 1999. -ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral.par_utilities. . Navabi and McGraw-Hill Inc. END par_central_processing_unit. USE par_library.ALL.

FUNCTION "NOT" (a : qit_vector) RETURN qit_vector. SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0). -FUNCTION add_cv (a. b : qit_vector.ALL. cin : qit) RETURN qit_vector. CONSTANT zero_12 : twelve := "000000000000". -FUNCTION set_if_zero (a : qit_vector) RETURN qit. -SUBTYPE nibble IS qit_vector (3 DOWNTO 0). SUBTYPE byte IS qit_vector (7 DOWNTO 0). Z. -SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0). SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0). CONSTANT zero_8 : byte := "00000000". SUBTYPE twelve IS qit_vector (11 DOWNTO 0).basic_utilities.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. Navabi and McGraw-Hill Inc. USE cmos. b : qit_vector) RETURN qit_vector. SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0). b : qit_vector) RETURN qit_vector. b : qit_vector. -END par_utilities. . FUNCTION sub_cv (a. SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0). FUNCTION "AND" (a. b : qit) RETURN qit . FUNCTION "OR" (a. cin : qit) RETURN qit_vector. -CONSTANT zero_4 : nibble := "0000". -PACKAGE par_utilities IS FUNCTION "XOR" (a. • • • • Declarations of par_utilities package of par_library Machine descriptions require utilities Use basic_utilities Additional utilities are included in par_utilities CHAPTER 10 15 © 1999. -SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0).

RETURN r.BEHAVIORAL DESCRIPTION OF PARWAN PACKAGE BODY par_utilities IS FUNCTION "XOR" (a. FUNCTION "AND" (a.b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE). END LOOP loop1. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i). END "XOR".'0'.'0'. -FUNCTION "OR" (a.'1'. END "NOT". -FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE).'0'. ('X'. Navabi and McGraw-Hill Inc. END "AND". b). b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0'.'X'.'X'). BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i). RETURN r. Z.'X'). END LOOP loop1. END "OR". . END LOOP loop1.'1'. ('1'. RETURN r.'X'. BEGIN RETURN qit_xor_table (a.'X')). ('1'. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i).'0'.'X').b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE). • Body of par_utilities package of par_library library • Define XOR in qit • Overload logical operators with qit_vector CHAPTER 10 16 © 1999.

r(a'LEFT+1) := c(a'LEFT). END set_if_zero. FUNCTION sub_cv (a. VARIABLE not_c : qit. END add_cv. b_sign := b(b'LEFT). b : qit_vector. CHAPTER 10 17 . END par_utilities. not_c). IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'. Navabi and McGraw-Hill Inc. -. END IF. Z. not_c := NOT cin. BEGIN a_sign := a(a'LEFT). b_sign: qit. END LOOP. END IF. b : qit_vector. cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0). RETURN r. FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1).extra r bits : msb: overflow. not_b. c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)). next to msb: carry VARIABLE a_sign. BEGIN not_b := NOT b. r := add_cv (a. VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0). RETURN r. FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'. cin : qit) RETURN qit_vector IS VARIABLE r. r(0) := a(0) XOR b(0) XOR cin. RETURN zero. c: qit_vector (a'LEFT + 2 DOWNTO 0). • • • • Body of the par_utilities package of par_library library add_cv adds its operands creates c and v bits Put overflow in leftmost result bit Put carry to the right of overflow © 1999. BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'. END LOOP. c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)).BEHAVIORAL DESCRIPTION OF PARWAN FUNCTION add_cv (a. EXIT. END sub_cv. --overflow ELSE r(a'LEFT+2) := '0'.

CONSTANT lda : qit_vector (2 DOWNTO 0) := "000". Z.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010". CONSTANT ann : qit_vector (2 DOWNTO 0) := "001". CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001". CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011". -PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110". CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100". CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100".ALL. CONSTANT sta : qit_vector (2 DOWNTO 0) := "101". CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001". CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110". END par_parameters. Navabi and McGraw-Hill Inc. USE cmos. CONSTANT indirect : qit := '1'. CONSTANT add : qit_vector (2 DOWNTO 0) := "010". • Declaration of par_parameters Package of par_library • Assign appropriate names to opcodes • par_parameters is used for readability CHAPTER 10 18 © 1999. CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000". CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11".basic_utilities. . CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111".

adbus : OUT twelve ). read_mem. USE par_library. -LIBRARY par_library. USE par_library. • Interface description of Parwan CHAPTER 10 19 © 1999.par_utilities. write_low_time : TIME := 2 US. cycle_time : TIME := 4 US). -ENTITY par_central_processing_unit IS GENERIC (read_high_time. END par_central_processing_unit. USE cmos.ALL. . write_high_time.ALL. read_low_time.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. interrupt : IN qit.ALL.par_parameters.basic_utilities. Navabi and McGraw-Hill Inc. databus : INOUT wired_byte BUS := "ZZZZZZZZ". Z. write_mem : OUT qit. PORT (clk : IN qit.

ELSE -. increment pc. END behavioral. END IF. sub END IF.jmp / sta / lda. Figure 10. ELSE -.18.two-byte instructions Read second byte into byte2.23. -. and. Figure 10. Figure 10. Figure 10. byte2 has address. IF byte1 (7 DOWNTO 5) = jsr THEN Execute jsr instruction. Figure 10. END IF. Execute lda. and. -. address in byte2. top. write ac. ELSE -.all other two-byte instructions IF byte1 (4) = indirect THEN Use byte1 and byte2 to get address. Figure 10. IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN Execute single-byte instructions.25.BEHAVIORAL DESCRIPTION OF PARWAN ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS Declare necessary variables.no interrupt Read first byte into byte1.20.single-byte / double-byte END IF. -. Figure 10.16. add.read operand for lda. Figure 10. Z.26.ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN Execute jmp instruction. • Outline of the Behavioral Description of Parwan CHAPTER 10 20 © 1999. and. add. Figure 10.jsr / bra / other double-byte instructions END IF. -. sub Read memory onto databus.19. ELSE -. Figure 10. Remove memory from databus. add.21. -. Figure 10. BEGIN IF interrupt = '1' THEN Handle interrupt. Figure 10. middle. ELSIF byte1 (7 DOWNTO 4) = bra THEN Execute bra instructions. ELSIF byte1 (7 DOWNTO 5) = sta THEN Execute sta instruction.17. . increment pc.26.24. and sub. Navabi and McGraw-Hill Inc. bottom.22.interrupt / otherwise END PROCESS. Figure 10.26.

WAIT FOR cycle_time. part of Parwan behavioral model • Filling the outline of the behavioral description of Parwan • Declarations. byte1 := byte (databus). • Variable declarations of Parwan behavioral model pc := zero_12. Reading the first byte CHAPTER 10 21 © 1999. Interrupt handling. • Interrupt handling of Parwan behavioral model adbus <= pc. VARIABLE temp : qit_vector (9 DOWNTO 0). byte1.BEHAVIORAL DESCRIPTION OF PARWAN VARIABLE pc : twelve. VARIABLE ac. pc := inc (pc). • Reading the first byte from the memory. Z. WAIT FOR read_high_time. c. n : qit. read_mem <= '0'. WAIT FOR read_low_time. VARIABLE v. Navabi and McGraw-Hill Inc. . z. byte2 : byte. read_mem <= '1'.

WHEN asl => c := ac (7). n := ac (7). END IF. WHEN cma => ac := NOT ac. IF ac = zero_8 THEN z := ‘1’. cma. cmc. IF ac = zero_8 THEN z := '1'. cla. asr CHAPTER 10 22 © 1999. • Executing single-byte instructions in the behavioral model of Parwan • Using the least significant nibble for decoding instructions • Decoding instructions.BEHAVIORAL DESCRIPTION OF PARWAN CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8. asl. IF ac = zero_8 THEN z := '1'. END CASE. WHEN cmc => c := NOT c. n := ac (7). n := ac (7). Navabi and McGraw-Hill Inc. WHEN OTHERS => NULL. IF c /= n THEN v := '1'. . Z. WHEN asr => ac := ac (7) & ac (7 DOWNTO 1). END IF. END IF. END IF. ac := ac (6 DOWNTO 0) & '0'.

Z. • Reading the second byte from the memory. Navabi and McGraw-Hill Inc. byte2 := byte (databus). WAIT FOR read_low_time. read_mem <= '0'. WAIT FOR write_low_time. write_mem <= '0'. WAIT FOR write_high_time. Executing jsr CHAPTER 10 23 © 1999. pc := inc (pc). . pc (7 DOWNTO 0) := inc (byte2).BEHAVIORAL DESCRIPTION OF PARWAN adbus <= pc. read_mem <= '1'. WAIT FOR read_high_time. adbus (7 DOWNTO 0) <= byte2. part of Parwan behavioral model databus <= wired_byte (pc (7 DOWNTO 0) ). databus <= "ZZZZZZZZ". write_mem <= '1'. • Execution of the jsr instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Reading the second byte.

WAIT FOR read_high_time. adbus (7 DOWNTO 0) <= byte2. . WAIT FOR read_low_time. Handling indirect addressing CHAPTER 10 24 © 1999. END IF. byte2 := byte (databus). Navabi and McGraw-Hill Inc. Z. read_mem <= '1'. read_mem <= '0'. • Execution of branch instructions in the behavioral model of Parwan adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). • Handling indirect addressing by the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Branch instruction.BEHAVIORAL DESCRIPTION OF PARWAN IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2.

Z. • Execution of jmp instruction in the behavioral model of Parwan adbus <= byte1 (3 DOWNTO 0) & byte2. write_mem <= '0'.BEHAVIORAL DESCRIPTION OF PARWAN pc := byte1 (3 DOWNTO 0) & byte2. write_mem <= '1'. databus <= "ZZZZZZZZ". • Execution of sta instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Handling jmp and sta instructions CHAPTER 10 25 © 1999. WAIT FOR write_low_time. databus <= wired_byte (ac). . Navabi and McGraw-Hill Inc. WAIT FOR write_high_time.

and. END CASE. IF ac = zero_8 THEN z := '1'. WAIT FOR read_high_time. byte (databus). read_mem <= '0'. Navabi and McGraw-Hill Inc. WHEN OTHERS => NULL. c := temp (8). v := temp (9). c := temp (8). read_mem <= '1'. byte (databus). c). • Execution of lda. WHEN add => temp := add_cv (ac. and sub instructions in the behavioral model of Parwan CHAPTER 10 26 © 1999. Z. ac := temp (7 DOWNTO 0). c). n := ac (7). CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus). END IF. add. WAIT FOR read_low_time. adbus (7 DOWNTO 0) <= byte2. v := temp (9). WHEN ann => ac := ac AND byte (databus). WHEN sbb => temp := sub_cv (ac. . ac := temp (7 DOWNTO 0).BEHAVIORAL DESCRIPTION OF PARWAN adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0).

Z. Navabi and McGraw-Hill Inc. ADBUS obus_on_dbus 8 8 4 8 AC ac_out a_side ALU b_side IR ir_out PC_PAGE pc_out PC_OFFSET CONTROLLER alu_flags 4 8 mar_page_bus mar_inp MAR_PAGE OBUS 4 mar_offset_bus alu_out SHU 4 8 MAR_OFFSET 8 mar_out SR 4 read_mem write_mem interrupt ADBUS 12 • Bussing structure of Parwan CHAPTER 10 27 © 1999..PARWAN BUSSING STRUCTURE databus_on_dbus DATABUS dbus_on_databus DBUS 8 4096 byte memory .. .

Navabi and McGraw-Hill Inc.PARWAN BUSSING STRUCTURE Component AC IR PC MAR SR ALU SHU Type Register Register Loadable Up Counter Register Register Arithmetic Unit Shifter Logic Bits 8 8 12 12 4 8 8 • • • • Machine has 7 components Behavioral description helps partitioning the circuit Circuit components will be identified Bussing specifies interconnection of these components CHAPTER 10 28 © 1999. . Z.

Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac . Z. Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir Pc_on_mar_page_bus Get Address Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus Get Operand.PARWAN BUSSING STRUCTURE LDA Instruction: Cycle 1 Begin Fetch Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Pc_on_mar_page_bus. Next Fetch • Steps for execution of lda CHAPTER 10 29 © 1999. Navabi and McGraw-Hill Inc. ...

. Z.PARWAN BUSSING STRUCTURE Data Signals DATA SECTION Data Components and Buses CONTROL SECTION Control Signals • Data and control sections of Parwan CPU • 31 control signals from the controller to the data unit CHAPTER 10 30 © 1999. Navabi and McGraw-Hill Inc.

ir_on_mar_page_bus. databus_on_dbus ADBUS DATABUS SHU ALU Bus Control Bus Control Logic Units Logic Units mar_on_adbus dbus_on_databus arith_shift_left. Z. alu_a. zero_ac load_ir increment_pc. alu_not. load_offset_pc. dbus_on_mar_offset_bus DBUS Bus Control pc_offset_on_dbus. load_page_pc. obus_on_dbus. alu_b. alu_add. Navabi and McGraw-Hill Inc. arith_shift_right alu_and.DATAFLOW DESCRIPTION OF PARWAN Applies To AC IR PC Category Register Control Register Control Register Control Signal Name load_ac. interrupt • Inputs and outputs of Parwan control section • Signals for flow of data and data clocking CHAPTER 10 31 © 1999. . load_offset_mar load_sr. pc_on_mar_offset_bus. write_mem. alu_sub Others I/O read_mem. cm_carry_sr pc_on_mar_page_bus. reset_pc Loads ac Resets ac Loads ir Increments pc Functionality Loads page part of pc Loads offset part of pc Resets pc Loads page part of mar Loads offset part of mar Loads sr Complements carry flag of sr Puts page part of pc on mar page bus Puts 4 bits of ir on mar page bus Puts offset part of pc on mar offset bus Puts dbus on mar offset bus Puts offset part of pc on dbus Puts obus on dbus Puts external databus on internal dbus Puts all of mar on adbus Puts internal dbus on external databus Shifter shifts its input one place to the left Shifter shifts its input one place to the right Output of alu becomes and of its two inputs Output of alu becomes complement of its b input Output of alu becomes the same as its a input alu perfporms add operation on its two inputs Output of alu becomes the same as its b input alu perfporms subtraction of its two inputs Starts a memory read operation Starts a memory write operation Interrupts CPU MAR SR MAR_BUS Register Control Register Control Bus Control load_page_mar.

. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN System Clock Control Signal 1 Control Signal 2 Control signals remain asserted for a complete clock cycle Allows logic unit propagation Clock data and control at the same time Clock data while control signals are still valid • Timing of control signals • Assume falling edge trigger data and control CHAPTER 10 32 © 1999. Z.

Navabi and McGraw-Hill Inc. Will also show hardware. . Z. • Operations and flags of alu • A control signal for each operation CHAPTER 10 33 © 1999.DATAFLOW DESCRIPTION OF PARWAN Id 0 1 2 3 4 5 Opcode line alu_and alu_not alu_a alu_add alu_b alu_sub Operation a AND b NOT b a b PLUS a b b MINUS a Flags zn zn zn vczn zn vczn Individual data components will be described in VHDL.

. 5) NO alu_a alu_add [0] [1] [2] [3] [4] [5] [6] [7] alu_sub + alu_b - • Parwan alu • Logic symbol • One bit gate level hardware CHAPTER 10 34 © 1999. 4. Navabi and McGraw-Hill Inc. 1. 5) VO (3. 5) CO (0. 3. 3. 1. 2. 4. Z.DATAFLOW DESCRIPTION OF PARWAN ai bi alu_and alu_not 0 1 2 3 4 5 VI CI ZI NI A B A B A B A B A B A B A B A B ALU (3. 2. 5) ZO (0.

ALL. CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000". CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010". CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000". Z.DATAFLOW DESCRIPTION OF PARWAN LIBRARY cmos. Navabi and McGraw-Hill Inc. CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000".basic_utilities. END alu_operations. CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100". . -PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001". USE cmos. • Package declaration for the alu_operations package • Simplify code and add readability CHAPTER 10 35 © 1999.

WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side. ALIAS n_flag_in : qit IS in_flags(0). END behavioral. -ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side. ALIAS z_flag_in : qit IS in_flags(1). alu_and) IS • Behavioral description of arithmetic logic unit of Parwan CHAPTER 10 36 © 1999. v := v_flag_in. v := v_flag_in. c. n). z_out : OUT byte. v := v_flag_in. -. END PROCESS coding. Navabi and McGraw-Hill Inc. c := c_flag_in. a_side. z_out <= t (7 DOWNTO 0). c := c_flag_in. WHEN OTHERS => NULL. z := set_if_zero (t (7 DOWNTO 0)). c_flag_in). alu_a. v := t(9). WHEN b_input => t (7 DOWNTO 0) := b_side. alu_not. .DATAFLOW DESCRIPTION OF PARWAN ENTITY arithmetic_logic_unit IS PORT (a_side. alu_b. c := c_flag_in. VARIABLE v. z. alu_add. alu_sub : IN qit. CASE qit_vector (5 DOWNTO 0)’ (alu_sub. out_flags <= (v. b_side. WHEN a_input => t (7 DOWNTO 0) := a_side. a_side. alu_and. n : qit. ALIAS c_flag_in : qit IS in_flags(2). alu_b. alu_not. z. END arithmetic_logic_unit. in_flags : IN nibble. c_flag_in). BEGIN WHEN a_add_b => t := add_cv (b_side. v := t(9). alu_a. c := c_flag_in. alu_and. alu_add. b_side : IN byte. ALIAS v_flag_in : qit IS in_flags(3).other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side. END CASE. c. alu_b. n := t(7). c := t(8). alu_add. c := t(8). alu_not. out_flags : OUT nibble). alu_a. v := v_flag_in. WHEN b_compl => t (7 DOWNTO 0) := NOT b_side. alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0). Z.

DATAFLOW DESCRIPTION OF PARWAN L R Input Output SHU L R VI CI ZI NI [0] [1] [2] [3] [4] [5] [6] [7] i+1 i i ( L) VO (L) CO (L. . Navabi and McGraw-Hill Inc. R) ZO (L. R) NO i-1 • Parwan shu • Logic symbol • One bit hardware CHAPTER 10 37 © 1999. Z.

n) := in_flags. out_flags : OUT nibble). • Behavioral Description of the Shifter Unit of Parwan CHAPTER 10 38 © 1999. Z. c. z. arith_shift_left.DATAFLOW DESCRIPTION OF PARWAN ENTITY shifter_unit IS PORT (alu_side : IN byte. . v := alu_side (6) XOR alu_side (7). obus_side <= t. n := t (7). z := set_if_zero (t). c := alu_side (7). arith_shift_left. END behavioral. n : qit. END PROCESS coding. in_flags : IN nibble. n). z. c := c_flag_in. ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'. out_flags <= (v. c. c. (v. ALIAS c_flag_in : qit IS in_flags(2). ALIAS n_flag_in : qit IS in_flags(0). BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0). arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0). z := set_if_zero (t). VARIABLE v. z. END IF. Navabi and McGraw-Hill Inc. END shifter_unit. v := v_flag_in. -ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side. ALIAS v_flag_in : qit IS in_flags(3). ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1). obus_side : OUT byte. ALIAS z_flag_in : qit IS in_flags(1). n := t (7). arith_shift_right : IN qit.

3D [0] [1] [2] [3] N Z C V input c 2D Q output c load G1 cm_carry 1C2 • The status register • Logic symbol • One bit hardware CHAPTER 10 39 © 1999. 3D 2. 3D 1. 3D 1. Z. 3D 1. .DATAFLOW DESCRIPTION OF PARWAN load cm_carry G1 G2 C3 SR N Z C V 1. Navabi and McGraw-Hill Inc.

out_status <= internal_state. ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c. cm_carry. out_status : OUT nibble. Navabi and McGraw-Hill Inc. ALIAS internal_c : qit IS internal_state (2). -ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000". • Behavioral description of the status register of Parwan CHAPTER 10 40 © 1999. . Z. BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags. ck : IN qit ). END IF. END status_register_unit. END IF.DATAFLOW DESCRIPTION OF PARWAN ENTITY status_register_unit IS PORT (in_flags : IN nibble. END behavioral. load. END PROCESS.

4D 2. 4D 2. 4D 3. 4D 3. 4D 2. Navabi and McGraw-Hill Inc. Z.DATAFLOW DESCRIPTION OF PARWAN load zero G1 M2 M3 1C4 AC zero '0' I0 '0' I1 '0' I2 '0' I3 '0' I4 '0' I5 '0' I6 '0' I7 2. 4D 3. 4D 2. 4D 3. 4D 3. . 4D 2. 4D 3. 4D 3. 4D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 2D Q Oi I o2 o3 o4 o5 o6 o7 i G1 1C2 • Parwan accumulator • Logic symbol • One bit hardware CHAPTER 10 41 © 1999. 4D 2. 4D 2. 4D 3.

. END BLOCK clocking. Z. ck : IN qit). END accumulator_unit.DATAFLOW DESCRIPTION OF PARWAN ENTITY accumulator_unit IS PORT (i8 : IN byte. • Dataflow description of Parwan accumulator CHAPTER 10 42 © 1999. o8 : OUT byte. -ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8. zero. END BLOCK enable. load. Navabi and McGraw-Hill Inc. END dataflow.

DATAFLOW DESCRIPTION OF PARWAN IR LOAD CI 1C2 I I0 I1 I2 I3 I4 I5 I6 I7 2D 2D 2D 2D 2D 2D 2D 2D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 o2 o3 o4 i 2D Q Oi load o5 o6 o7 G1 1C2 • The Parwan instruction register • Logic symbol • One bit hardware CHAPTER 10 43 © 1999. Navabi and McGraw-Hill Inc. . Z.

END instruction_register_unit. END BLOCK enable. load.DATAFLOW DESCRIPTION OF PARWAN ENTITY instruction_register_unit IS PORT (i8 : IN byte. • Dataflow description of the instruction register of Parwan CHAPTER 10 44 © 1999. END BLOCK clocking. ck : IN qit). Z. o8 : OUT byte. -ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8. END dataflow. . Navabi and McGraw-Hill Inc.

DATAFLOW DESCRIPTION OF PARWAN reset load_page load_offset increment 3R G1 G2 G4 C3/4+ PC I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 2. 3D 2. Navabi and McGraw-Hill Inc. 3D 1. 3D 1. . Z. 3D 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 O i-1 reset o4 o5 o6 o7 o8 o9 o10 o11 2R Q Oi G1 1T C2 load_pc_offset clock • Parwan program counter • Logic symbol • One bit hardware CHAPTER 10 45 © 1999. 3D 1. 3D 1. 3D 2. 3D 2. 3D 2. 3D 2.

END IF. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). END IF. load_offset. END IF. reset. load_page. Z. ck : IN qit). END behavioral. • Behavioral description of the program counter of Parwan CHAPTER 10 46 © 1999. END PROCESS.DATAFLOW DESCRIPTION OF PARWAN ENTITY program_counter_unit IS PORT (i12 : IN twelve. increment. o12 : OUT twelve. ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). o12 <= internal_state. ELSIF increment = '1' THEN internal_state := inc (internal_state). Navabi and McGraw-Hill Inc. . END program_counter_unit. BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12. -ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. END IF.

3D 2. 3D 1. 3D 1. 3D 2.DATAFLOW DESCRIPTION OF PARWAN MAR load_page load_offset G1 G2 C3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 2. Z. 3D 2. . 3D 2. 3D 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 I i 2D Q Oi load G1 1C2 • Logic symbol for the memory address register of Parwan CHAPTER 10 47 © 1999. 3D 1. 3D 1. Navabi and McGraw-Hill Inc. 3D 2.

load_page. Navabi and McGraw-Hill Inc. -ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. . END behavioral. o12 : OUT twelve. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). o12 <= internal_state. END IF. END IF.DATAFLOW DESCRIPTION OF PARWAN ENTITY memory_address_register_unit IS PORT (i12 : IN twelve. END memory_address_register_unit. • Behavioral description of the memory address register of Parwan CHAPTER 10 48 © 1999. ck : IN qit). Z. END IF. END PROCESS. BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). load_offset.

load_page_pc. -.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_data_path IS PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ". alu_a. databus_on_dbus. • Entity Declaration of the Data Section of Parwan • Wires all components • Specifies bussing CHAPTER 10 49 © 1999. alu_sub : IN qit. .outputs to the controller: ir_lines : OUT byte. dbus_on_mar_offset_bus. pc_offset_on_dbus. Navabi and McGraw-Hill Inc. load_offset_pc. status : OUT nibble ). arith_shift_right. alu_not. load_ir. adbus : OUT twelve. reset_pc. END par_data_path. load_offset_mar. dbus_on_databus. load_sr. clk : IN qit. ir_on_mar_page_bus. load_page_mar. Z. increment_pc.bus connections: pc_on_mar_page_bus. cm_carry_sr. alu_and. -. alu_add.logic unit function control inputs: arith_shift_left. obus_on_dbus. zero_ac. mar_on_adbus. alu_b. -.register controls: load_ac. pc_on_mar_offset_bus. -.

END COMPONENT. obus : byte. alu_out. PORT (a_side. shu_flags. cm_carry. SIGNAL alu_a_inp : byte. -SIGNAL ac_out. -COMPONENT alu in_flags : IN nibble.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE structural OF par_data_path IS -COMPONENT ac PORT (i8: IN byte. zero. arith_shift_left. load. alu_sub : IN qit. -COMPONENT mar PORT (i12 : IN twelve. mar_out : twelve. END COMPONENT. ck : IN qit). -COMPONENT sr PORT (in_flags : IN nibble. o12 : OUT twelve. FOR l1 : alu USE ENTITY WORK. o12 : OUT twelve. alu_a. reset. ck : IN qit ).accumulator_unit (dataflow). arith_shift_right : IN qit. FOR r3: pc USE ENTITY WORK. alu_b. ir_out. alu_add. obus_side : OUT byte. alu_and.status_register_unit (behavioral). SIGNAL dbus : wired_byte BUS. FOR r2: ir USE ENTITY WORK. FOR r4: mar USE ENTITY WORK. out_flags : OUT nibble). sr_out : nibble. FOR r1: ac USE ENTITY WORK. Z.program_counter_unit (behavioral). in_flags : IN nibble. -COMPONENT ir PORT (i8: IN byte. FOR r5 : sr USE ENTITY WORK. ck: IN qit). Navabi and McGraw-Hill Inc. out_status : OUT nibble.shifter_unit (behavioral). END COMPONENT. -COMPONENT shu PORT (alu_side : IN byte. ck: IN qit). alu_not. load_offset. load. SIGNAL pc_out. ck : IN qit). out_flags : OUT nibble). FOR l2 : shu USE ENTITY WORK. SIGNAL mar_inp : twelve. SIGNAL mar_bus : wired_twelve BUS. END COMPONENT.arithmetic_logic_unit (behavioral). load. o8: OUT byte.memory_address_register_unit (behavioral). load_offset. b_side : IN byte. o8: OUT byte. . END COMPONENT. load_page.instruction_register_unit (dataflow). • Declarative Part of the structural Architecture of par_data_path • Components are declared • Busses and signals are declared CHAPTER 10 50 © 1999. increment. -COMPONENT pc PORT (i12 : IN twelve. SIGNAL alu_flags. END COMPONENT. load_page. z_out : OUT byte. END COMPONENT.

-obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus). END BLOCK ir2. dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus. -r2: ir PORT MAP (obus. • Statement part of the par_data_path structural Architecture • Uses block statements for bussing • Register interconnections follow registers instantiation CHAPTER 10 51 © 1999. ir1: ir_lines <= ir_out.register connections --r1: ac PORT MAP (obus. --. load_ac. -mar_bus1: mar_inp <= qit_vector (mar_bus). ac_out. ir_out. END BLOCK databus1.bus connections --dbus1: alu_a_inp <= qit_vector (dbus). dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus. END BLOCK dbus2.DATAFLOW DESCRIPTION OF PARWAN BEGIN -. . END BLOCK obus1. -databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus. ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)). zero_ac. load_ir. Navabi and McGraw-Hill Inc. clk). END BLOCK dbus3. Z. clk).

pc_out. pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)). shu_flags). sr_out. -r5: sr PORT MAP (shu_flags. END BLOCK pc1. -r4: mar PORT MAP (mar_inp. END BLOCK mar1. mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out. increment_pc. alu_sub. pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). alu_a. clk). load_offset_mar. cm_carry_sr. load_sr. . arith_shift_right. ac_out.DATAFLOW DESCRIPTION OF PARWAN r3: pc PORT MAP (mar_out. Z. arith_shift_left. alu_out. alu_flags). load_page_mar.connection of logical and register structures --l1: alu PORT MAP (alu_a_inp. • Statement part of the par_data_path structural Architecture • Ends with logic unit instantiations CHAPTER 10 52 © 1999. sr1: status <= sr_out. obus. Navabi and McGraw-Hill Inc. alu_and. alu_not. END BLOCK pc3. clk). sr_out. alu_b. load_offset_pc. l2: shu PORT MAP (alu_out. END structural. --. load_page_pc. reset_pc. alu_flags. END BLOCK pc2. alu_add. clk). mar_out. pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)).

Z. • Typical hardware surrounding a control flip-flop • The logic block is designated by a bubble • Controller is built using one-hot encoding CHAPTER 10 53 © 1999. hardware and coding will be described. Navabi and McGraw-Hill Inc. style.DATAFLOW DESCRIPTION OF PARWAN To other control FF inputs External Signals logic block control FF i Q All Signals Activating State i 1D i C1 signals issuing control signals control signals to data section en system clock For the Parwan controller. .

Navabi and McGraw-Hill Inc. . Z.DATAFLOW DESCRIPTION OF PARWAN csx a b c logic block i d e logic block j csy Q 1D i C1 en 1D j C1 Q en 1D k C1 Q clock • Example for the structure of Parwan control section • Showing 3 states in a one-hot implementation CHAPTER 10 54 © 1999.

load_page_mar.register control signals: load_ac. write_delay : TIME := 3 NS). arith_shift_right.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_control_unit IS GENERIC (read_delay. load_page_pc.inputs from the data section: ir_lines : IN byte. Navabi and McGraw-Hill Inc. obus_on_dbus. -. PORT (clk : IN qit. alu_sub : OUT ored_qit BUS. load_ir. alu_add. alu_not.bus connection control signals: pc_on_mar_page_bus. mar_on_adbus. increment_pc. pc_offset_on_dbus. load_sr. dbus_on_mar_offset_bus. ir_on_mar_page_bus. ------------------------------------------------------------------------------------------------ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. cm_carry_sr. alu_b. -. pc_on_mar_offset_bus. write_mem : OUT ored_qit BUS. Z. databus_on_dbus. -. END par_control_unit. load_offset_mar. status : IN nibble.logic unit function control outputs: arith_shift_left. . load_offset_pc.memory control and other external signals: read_mem. interrupt : IN qit ). dbus_on_databus. reset_pc. zero_ac. alu_and. -. BEGIN • • • • Entity declaration of Parwan control section Showing signals for the data unit Declaring states of the machine is shown Declarative part of the par_control_unit dataflow architecture CHAPTER 10 55 © 1999. alu_a. -.

Navabi and McGraw-Hill Inc. par_control_unit outputs CHAPTER 10 56 © 1999. .DATAFLOW DESCRIPTION OF PARWAN par_control_unit control_signal_1 assignments to control_signal_1 control_signal_2 control_signal_3 oring_qit type signals • Assigning signals with implied oring. Z.

-. Navabi and McGraw-Hill Inc. . Z. pc_on_mar_offset_bus <= GUARDED '1'. -. END BLOCK ck.pc to mar pc_on_mar_page_bus <= GUARDED '1'. END BLOCK s1. load_offset_mar <= GUARDED '1'. load_page_mar <= GUARDED '1'. s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'.start of fetch -.goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'.DATAFLOW DESCRIPTION OF PARWAN s1: BLOCK (s(1) = '1') BEGIN -. pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 2 reset_pc 1D 1 interrupt C1 • State 1: starting a fetch • VHDL code • Gate level hardware CHAPTER 10 57 © 1999.reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'.

load_ir <= GUARDED '1'.increment pc increment_pc <= GUARDED '1'. Navabi and McGraw-Hill Inc. alu_a <= GUARDED ‘1’. -.goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'. mar_on_adbus read_mem databus_on_dbus alu_a load_ir increment_pc 3 1D 2 C1 • State 2: completing a fetch • VHDL code • Gate level hardware CHAPTER 10 58 © 1999. END BLOCK ck. -. .fetching continues -.DATAFLOW DESCRIPTION OF PARWAN s2: BLOCK (s(2) = '1') BEGIN -. Z. END BLOCK s2.read memory into ir mar_on_adbus <= GUARDED '1'. databus_on_dbus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay.

load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. pc_on_mar_offset_bus <= GUARDED '1'. Z.pc to mar. END BLOCK sb. END BLOCK s3.goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'. -. . arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'. END BLOCK ck.perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not. load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN s3: BLOCK (s(3) = '1') BEGIN -. load_page_mar <= GUARDED '1'. END BLOCK ck. load_offset_mar <= GUARDED '1'. ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. for next read pc_on_mar_page_bus <= GUARDED '1'. zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'. cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'. alu_b) <= GUARDED qit_vector’(“10”) WHEN ir_lines (1) = ‘1’ ELSE qit_vector’( “01”). arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'. -. • State 3: preparing for address fetch • Execution of single byte instructions • VHDL code CHAPTER 10 59 © 1999.

Navabi and McGraw-Hill Inc. .DATAFLOW DESCRIPTION OF PARWAN pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 4 1D 3 IR7 IR6 IR5 IR4 C1 2 IR3 2 1 0 IR3 2 1 0 IR1 arith_shift_left arith_shift_right alu_not alu_b IR1 IR3 IR1 cm_carry_sr IR2 IR3 1 IR3 0 zero_ac load_ac load_sr • State 3: preparing for address fetch • Execution of single byte instructions • Gate level hardware CHAPTER 10 60 © 1999. Z.

Z. -. databus_on_dbus <= GUARDED '1'.goto 5 for indirect. -.direct END BLOCK ck. direct. END BLOCK sp. -. jsr. -. and offset from next memory makeup 12-bit address -. END BLOCK s4.bra END BLOCK ck. 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'.read memory into mar offset mar_on_adbus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay. -.increment pc increment_pc <= GUARDED '1'. load_page_mar <= GUARDED '1'. 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'.page from ir. -. dbus_on_mar_offset_bus <= GUARDED '1'.goto 7 for jsr.indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'.jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'.DATAFLOW DESCRIPTION OF PARWAN s4: BLOCK (s(4) = '1') BEGIN -. END BLOCK pg. and branch VHDL code Gate level hardware CHAPTER 10 61 © 1999. -.completed operand (dir/indir) address -.keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -. Navabi and McGraw-Hill Inc. load_offset_mar <= GUARDED '1'. -. • • • • State 4: completing address of full address instructions Branching for indirect. .page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'.

DATAFLOW DESCRIPTION OF PARWAN mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offet_bus load_offset_mar increment_pc ir_on_mar_page_bus load_page_mar IR7 1D 4 6 5 C1 IR4 6 IR5 9 7 • State 4: completing address of full address instructions • Branching for indirect. direct. . jsr. Navabi and McGraw-Hill Inc. Z. and branch • Gate level hardware CHAPTER 10 62 © 1999.

mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offset_bus load_offset_mar 6 1D 5 c1 • State 5: taking care of indirect addressing • Actual address will now go in MAR CHAPTER 10 63 © 1999. -.indirect addressing -. END BLOCK ck. dbus_on_mar_offset_bus <= GUARDED '1'.read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'. . END BLOCK s5.DATAFLOW DESCRIPTION OF PARWAN s5: BLOCK (s(5) = '1') BEGIN -.goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'. Navabi and McGraw-Hill Inc. Z. databus_on_dbus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay. load_offset_mar <= GUARDED '1'.

. and sub instructions Outline of the VHDL code Outline of the hardware Three separate blocks for [jmp]. .. and [lda.perform lda. and. jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • • • • • State 6: reading the actual operand. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN . Z.. sub END BLOCK s6. and. Navabi and McGraw-Hill Inc. sub] CHAPTER 10 64 © 1999. sta. END BLOCK jm... Reading and executing jmp.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN . and. lda. -. add. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN . add. END BLOCK rd. END BLOCK st. add. [sta]..

END BLOCK s6. END BLOCK jm. .DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'. • • • • State 6: reading the actual operand. load_offset_pc <= GUARDED '1'.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. and. .. Z. Navabi and McGraw-Hill Inc.. and [lda. add. -. END BLOCK ck. sub] CHAPTER 10 65 © 1999. Reading and executing jmp instruction VHDL code Two more blocks for [sta].

goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.mar on adbus. • • • • State 6: reading the actual operand.. . add. Reading and executing sta instruction Partial VHDL code Need one more block for handling [lda. Z. sub] CHAPTER 10 66 © 1999. alu_b <= GUARDED ‘1’. write_mem <= GUARDED '1' AFTER write_delay. END BLOCK ck. END BLOCK s6. obus_on_dbus <= GUARDED '1'. ac on databus.. dbus_on_databus <= GUARDED '1'. Navabi and McGraw-Hill Inc. END BLOCK st.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN ... st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. and. -. . write to memory mar_on_adbus <= GUARDED '1'.

-. add. END BLOCK ck. add. END BLOCK rd. Navabi and McGraw-Hill Inc. load_sr <= GUARDED '1'. sub] CHAPTER 10 67 © 1999. -. lda.. load_ac <= GUARDED '1'.perform lda. and. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. and. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’.mar on adbus.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN . sta. sub END BLOCK s6. perform operation mar_on_adbus <= GUARDED '1'. • • • • State 6: reading the actual operand. and sub instructions Completing the VHDL code This last block handles [lda. databus_on_dbus <= GUARDED '1'. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. Z.. and. read memory for operand. Reading and executing jmp. add. read_mem <= GUARDED '1' AFTER read_delay. . alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’.

sub END BLOCK s6. and. -. END BLOCK ck. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. add.mar on adbus. write_mem <= GUARDED '1' AFTER write_delay. and. alu_b <= GUARDED ‘1’. Z.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. . st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. END BLOCK st. load_ac <= GUARDED '1'.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. perform operation mar_on_adbus <= GUARDED '1'. • State 6: reading the actual operand. load_offset_pc <= GUARDED '1'. END BLOCK ck. Navabi and McGraw-Hill Inc. lda.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. dbus_on_databus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay.perform lda. END BLOCK rd. and sub instructions • Complete VHDL code CHAPTER 10 68 © 1999. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’. databus_on_dbus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'. END BLOCK ck. -. and executing jmp. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. sta. ac on databus. load_sr <= GUARDED '1'. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -. obus_on_dbus <= GUARDED '1'. add. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. read memory for operand.mar on adbus. write to memory mar_on_adbus <= GUARDED '1'. -. END BLOCK jm. -.

and sub instructions • Complete gate level hardware CHAPTER 10 69 © 1999. . sta. Navabi and McGraw-Hill Inc. and executing jmp. and. add.DATAFLOW DESCRIPTION OF PARWAN jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • State 6: reading the actual operand. lda. Z.

mar_on_adbus pc_offset_on_dbus dbus_on_databus write_mem load_offset_pc 8 1D 7 c1 • • • • State 7: writing return address of subroutine Making pc point to top of subroutine Complete VHDL code Hardware CHAPTER 10 70 © 1999.jsr -. END BLOCK s7. pc_offset_on_dbus <= GUARDED '1'. -. .goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'. dbus_on_databus <= GUARDED '1'. END BLOCK ck. Z. Navabi and McGraw-Hill Inc.write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s7: BLOCK (s(7) = '1') BEGIN -. write_mem <= GUARDED '1' AFTER write_delay. -.address of subroutine to pc load_offset_pc <= GUARDED '1'.

.DATAFLOW DESCRIPTION OF PARWAN s8: BLOCK (s(8) = '1') BEGIN -.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.increment pc increment_pc <= GUARDED '1'. END BLOCK ck. -. END BLOCK s8. Navabi and McGraw-Hill Inc. increment_pc 9 1D 8 c1 • State 8: incrementing pc to skip location reserved for return address • VHDL code • Hardware CHAPTER 10 71 © 1999. Z.

. END BLOCK ck. END BLOCK s9. -. Z.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. ir3 status3 ir2 status2 load_offset_pc ir1 status1 ir0 status0 1 1D 9 C1 • State 9: conditional loading of pc for branch instructions • VHDL code • Gate level hardware CHAPTER 10 72 © 1999.DATAFLOW DESCRIPTION OF PARWAN s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'. Navabi and McGraw-Hill Inc.

. END BLOCK s8. END BLOCK ck. BEGIN s(next) <= GUARDED '1'. Z. END BLOCK s2.. . -.State blocks end here END dataflow. ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000".. CHAPTER 10 73 © 1999. BEGIN s(next) <= GUARDED '1'. BEGIN s(next) <= GUARDED '1'.. • • • • Ending the dataflow description of the par_control_unit Controller outline Need to clock all states A zero driver is placed on all state. END BLOCK s9. END BLOCK s1.. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. END BLOCK ck.. S2: BLOCK (s(2) = '1') BEGIN . END BLOCK ck. OOOO S8: BLOCK (s(8) = '1') BEGIN . BEGIN s(next) <= GUARDED '1'. BEGIN S1: BLOCK (s(1) = '1') BEGIN .. END BLOCK ck. S9: BLOCK (s(9) = '1') BEGIN ... END BLOCK ck.

Z. .DATAFLOW DESCRIPTION OF PARWAN Q 1D 1 C1 en 1D 2 C1 Q 3 C1 Q en Q 1D 4 C1 en 1D 5 C1 Q 1D 6 C1 Q en Q 1D 7 C1 1D 8 C1 Q 1D 9 C1 Q • Complete control unit • Wire individual control flip-flops • Oring is done at inputs of states when branching is done to them CHAPTER 10 74 © 1999. Navabi and McGraw-Hill Inc.

• Entity declaration of the Parwan CPU for its dataflow description • Complete CPU wires data and control CHAPTER 10 75 © 1999. write_mem : OUT qit. interrupt : IN qit. read_mem.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_central_processing_unit IS PORT (clk : IN qit. . adbus : OUT twelve ). Navabi and McGraw-Hill Inc. databus : INOUT wired_byte BUS := "ZZZZZZZZ". Z. END par_central_processing_unit.

zero_ac. read_mem. . zero_ac. load_ac. adbus. . status : IN nibble. .par_control_unit (dataflow). read_mem. load_ac. write_mem. FOR ctrl: par_control_unit USE ENTITY WORK. . load_ac. END COMPONENT. Z.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte. . END COMPONENT. BEGIN data: par_data_path PORT MAP (databus. • Data and control declarations • Data and control wiring © 1999. ctrl: par_control_unit PORT MAP (clk. . END dataflow. -COMPONENT par_control_unit PORT (clk : IN qit. . Navabi and McGraw-Hill Inc. . • The general outline of dataflow architectture of Parwan CPU. . interrupt ). FOR data: par_data_path USE ENTITY WORK. . . status : OUT nibble ). SIGNAL status : nibble. . zero_ac. status.par_data_path (structural). clk : IN qit. zero_ac. ir_lines. CHAPTER 10 76 . status ). clk. SIGNAL ir_lines : byte. . load_ac. ir_lines : IN byte. zero_ac. adbus : OUT twelve. write_mem : OUT qit. interrupt : IN qit ). -SIGNAL load_ac. . ir_lines. ir_lines : OUT byte. .

write. 31) "10000000". --(28. VARIABLE ia : INTEGER. "00000000". • A simple testbench • Include CPU instantiation. END input_output. jsr 36 "11101000". ia). sta 25 "00100000". 29. "00100100". BEGIN WAIT ON read. WAIT UNTIL write = '0'. "00011001". nop. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". --lda i 29. Z. jmp i 36 OTHERS => (OTHERS => ‘0’)). cpu : parwan PORT MAP (clock. END PROCESS mem. data <= "ZZZZZZZZ". 25. data. -. WAIT UNTIL read = '0'. "01000000". "00000000". END IF. --lda 24. 30. --jmp 18 "00000000". read. "00010010". write : qit. "00000000". • A simple test bench for Parwan behavioral and dataflow descriptions. "00011011". "01011100". "00011100". "11000000". "00000000". write_mem : OUT qit. "00000000". ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. BEGIN int : interrupt <= '1'. "00100100". --cac. cma. --asl. SIGNAL clock. address). "11100010". --and 26. "00011111". "11101001". interrupt. asr. "00011000". END IF. "00000000". '0' AFTER 4500 NS. read. SIGNAL address : twelve.. ELSE data <= wired_byte ( memory (ia) ). interrupt : IN qit. "01100000". jmp 32 "00000000". --(24. and read/write handshaking CHAPTER 10 77 © 1999. "00100000". 27) "00001100". Navabi and McGraw-Hill Inc. databus : INOUT wired_byte BUS. add 27 "11100010". "00011101". write. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "11100000". . "10100000". interrupt. SIGNAL data : wired_byte := "ZZZZZZZZ". END COMPONENT. qit2int (address. read_mem. "00010010". END IF. "00011010". "01110000". sub 28 "00010000". a short memory. "10000000". adbus : OUT twelve ). IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". "10010000".A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit. "00000000". 26. "01011010".

cpu : parwan PORT MAP (clock. "01100000". "00000000". "11000000". address). "10100000". cma. '0' AFTER 4500 NS. data. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "00000000". 29. --lda 24. "01000000". interrupt. "00010010".. "00011101". "00011010". write. TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. 26. "11100000". . nop. 25. sub 28 "00010000". BEGIN . "00000000". "00000000". "00011111". 30.. SIGNAL clock. jsr 36 "11101000". • Initializing memory for Parwan instructions CHAPTER 10 78 © 1999. SIGNAL address : twelve. interrupt. --asl.. "00100100". "11100010".. --(28. jmp i 36 OTHERS => (OTHERS => ‘0’)). 31) "10000000". "11101001". write : qit. "01110000". VARIABLE ia : INTEGER. "01011010". "00011000". -. "00100100". read. --cac. --(24. "10010000".. "00000000". mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". Z. "00011100". Navabi and McGraw-Hill Inc. BEGIN int : interrupt <= '1'. jmp 32 "00000000". add 27 "11100010". "00000000". "00100000". read. "00010010". --and 26. --jmp 18 "00000000". sta 25 "00100000". "10000000".A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . "00000000". 27) "00001100". "01011100". asr. "00011011". END input_output. "00011001". SIGNAL data : wired_byte := "ZZZZZZZZ". --lda i 29.

data <= "ZZZZZZZZ". mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := . write : qit.. END IF. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). . BEGIN int : interrupt <= '1'. SIGNAL address : twelve.. interrupt. cpu : parwan PORT MAP (clock. END IF. read. WAIT UNTIL read = '0'. BEGIN WAIT ON read. VARIABLE ia : INTEGER. qit2int (address. '0' AFTER 4500 NS.. END input_output. read. Z. • • • • Produce test waveforms on interrupt and clock signals Testing is done by modeling memory read and write operations A single process assigns values from memory to databus Same process handles memory write CHAPTER 10 79 © 1999. END PROCESS mem. Navabi and McGraw-Hill Inc. WAIT UNTIL write = '0'. ia). data.. SIGNAL data : wired_byte := "ZZZZZZZZ". IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". interrupt. write. TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. write. SIGNAL clock. address). END IF. ELSE data <= wired_byte ( memory (ia) ).

END FOR.par_central_processing_unit(dataflow). END behavior. (b) • Parwan tester applies data to Parwan buses • Component is declared. END dataflow. Navabi and McGraw-Hill Inc. binding will be done by configuration declaration • Hold data normally at z (High Impedance) CHAPTER 10 80 © 1999. END FOR.par_central_processing_unit(behavioral). (a) CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow. Z. END FOR. . END FOR.A TEST BENCH FOR THE PARWAN CPU CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral.

next_state <= do_one_bytes. ELSE next_state <= instr_fetch.read memory into ir read_mem <= '1'. alu_a <= ‘1’. • Memory and bus signaling for fetch state of controller • Signals provide for slower memory handshaking • Buss access signals are included CHAPTER 10 81 © 1999. END IF. IF ready = '1' THEN databus_on_dbus <= '1'. ELSE next_state <= instr_fetch. Navabi and McGraw-Hill Inc. increment_pc <= '1'. END IF. . WHEN do_one_bytes => --------------------------------------3 . Z. load_ir <= '1'.A MORE REALISTIC PARWAN WHEN instr_fetch => ---------------------------------------2 -.. IF grant = '1' THEN mar_on_adbus <= '1'..

We used one-to-one hardware correspondence so that no intelligent tools are required for the generation of hardware. For completing the design of Parwan. The behavioral description aids designers as they verify their understanding of the problem. Z. We consider the design presented here a manual design. Navabi and McGraw-Hill Inc. . • End of Chapter 10 CHAPTER 10 82 © 1999. The methodology presented here can be applied to designs of much larger magnitude. while the dataflow description can be used to verify the bussing and register structure of the design. The use of VHDL as a top-down partitioning and verification tool has helped us form such a methodology for manual design.SUMMARY This chapter showed how VHDL could be used to describe a system at the behavioral level before the system is even designed. A design carried to the stage where a dataflow model can be generated is only a few simple steps away from complete hardware realization. flip-flop and gate interconnections should replace the component descriptions in the Parwan dataflow model. and at the dataflow level after major design decisions have been made.

6.1 Arbitration Operation 11.8 SUMMARY CHAPTER 11 1 © 1999.6.4 Controller Modeling 11.2 Cache Interface 11.6.3 MEMORY SIGNALS 11. .4 DMA Controller 11.6 CPU CACHE 11.5 DMA DEVICE 11.4.3 Cache Structure Modeling 11.2 Interface Through Arbiter 11.2 CPU TIMING 11.4 SHARING SYSTEM BUSES 11.6.5.1 Serial Connection 11.7 COMPLETE SYSTEM 11.1 Cache Structure 11.4. Navabi and McGraw-Hill Inc.3 Interface to CPU 11.5.4.2 Wait Operation 11.3 Arbiter Model 11.5.1 SYSTEM OVERVIEW 11.5.CHAPTER 11 INTERFACE DESIGN AND MODELING 11. Z.

Z.SYSTEM OVERVIEW Arbiter Memory 4096*8 DMA Device Serial To Parallel serial_in DMA Controller cache memory & controller Address Decoder CPU • Bussing arrangement and system components. CHAPTER 11 2 © 1999. . Navabi and McGraw-Hill Inc.

Z. . Navabi and McGraw-Hill Inc.SYSTEM OVERVIEW 8 dat abu s 12 ad bu s rea gra rea w dy nt d_ rite me _m m em 8-bit CPU (Parwan) halted interrupt • CPU interface CHAPTER 11 3 © 1999.

MEMORY SIGNALS clock read_mem grant ready adbus valid databus valid (a) • CPU read and write requests CHAPTER 11 4 © 1999. Navabi and McGraw-Hill Inc. . Z.

MEMORY SIGNALS clock write_mem grant ready adbus valid databus valid (b) • CPU read and write requests CHAPTER 11 5 © 1999. . Navabi and McGraw-Hill Inc. Z.

Navabi and McGraw-Hill Inc. .MEMORY SIGNALS cs rwbar Memory 4096*8 dat abu s • Memory interface adb us CHAPTER 11 6 © 1999. Z.

.MEMORY SIGNALS Memory Wait cs rwbar adbus databus valid • Memory read operation CHAPTER 11 7 © 1999. Z. Navabi and McGraw-Hill Inc.

Z. Navabi and McGraw-Hill Inc. .SHARING SYSTEM BUSES memsel rwbar ready gra wr nt ite rea _req d_ ue req st ue st clock Bus Arbiter and Wait Handler skip_wait port 1 port 2 port 3 port 4 • Controlling bus access CHAPTER 11 8 © 1999.

SHARING SYSTEM BUSES clock read_request i grant i memsel rwbar ready wait for bus access wait for device wait for wait state to complete • Bus grant for read operation CHAPTER 11 9 © 1999. . Navabi and McGraw-Hill Inc. Z.

SHARING SYSTEM BUSES ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1). IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'. ready <= '1'. clock_period : TIME := 1 US). WAIT FOR clock_period. EXIT. END LOOP. ready : OUT qit). FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000". rwbar. WAIT ON clock. END behavioral. END IF. memsel. skip_wait : IN qit. PORT (read_request. ELSE grant (i) <= '0'. Z. END IF. clock. grant (i) <= '1'. rwbar <= read_request (i). • Arbiter VHDL description CHAPTER 11 10 © 1999. END IF. memsel <= '0'. END PROCESS wait_cycle. -ARCHITECTURE behavioral OF arbitrator IS BEGIN -. . write_request : IN nibble. END LOOP wait. END arbitrator. grant : BUFFER nibble. Navabi and McGraw-Hill Inc. memsel <= '1'.Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. ready <= '0'.

DMA DEVICE Serial To Parallel serial pa ral lel _o ut ov err u fra n m_ err or 11 8 • Interface of serial-to-parallel converter CHAPTER 11 da tar ea rec dy eiv ed © 1999. Z. . Navabi and McGraw-Hill Inc.

Z.DMA DEVICE 8 de v_ da ta er err de de ro or v_ v_ r2 1 rd rc y v read_mem write_mem databus grant DMA Controller addressbus ready status_write clk sel ect _re g status_read 4 • Interface of the DMA controller CHAPTER 11 12 © 1999. Navabi and McGraw-Hill Inc. .

Navabi and McGraw-Hill Inc. Z. .DMA DEVICE Address 1111:1111_1100 1111:1111_1101 1111:1111_1110 1111:1111_1111 DMA Registers Least 8 bits of starting address Most 4 bits of start Number of bytes to transfer done ie er2 er1 ie wr rd go • DMA Registers CHAPTER 11 13 © 1999.

Navabi and McGraw-Hill Inc. Z. .DMA DEVICE 4 adbus Address Decoder active • Decoding for selecting DMA registers CHAPTER 11 14 © 1999.

selects : OUT nibble). END behavioral. PORT (adbus : IN twelve. . END IF. END quad_adrdcd. WHEN OTHERS => selects <= "0000".DMA DEVICE ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"). END CASE. • VHDL description of DMA register address decoder CHAPTER 11 15 © 1999. active : OUT qit. WHEN "11" => selects <= "1000". END PROCESS. Z. -ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'. CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001". WHEN "01" => selects <= "0010". WHEN "10" => selects <= "0100". selects <= "0000". Navabi and McGraw-Hill Inc. ELSE active <= '0'.

DMA DEVICE S2P serial 8 de er err dev dev v_ ro r2 or1 _rdy _rcv da ta read_mem 8 write_mem databus grant ready 12 addressbus status_read status_write sel ect _re g adbus status_sel active • DMA device CHAPTER 11 16 © 1999. pa ral lel _o ut ov err u fra n m_ e da rror tar rec ead eiv y ed DMA 4 selects Decoder . Navabi and McGraw-Hill Inc. Z.

cpu signals select_reg : IN nibble. -. adbus : INOUT twelve := "ZZZZZZZZZZZZ". ready. Navabi and McGraw-Hill Inc. dev_rdy : IN qit. -. error2. Z. dev_rcv : OUT qit.DMA DEVICE ENTITY dma_controller IS PORT (clk : IN qit.memory signals read_mem. grant : IN qit. --device signals error1. write_mem : OUT qit := '0'. . • DMA controller entity declaration CHAPTER 11 17 © 1999. dev_data : IN byte ). status_rd. databus : INOUT byte := "ZZZZZZZZ". END dma_controller. status_wr : IN qit.

put parallel” process statement (Figure 11. ALIAS rd : qit IS rfile(3)(1).17) BEGIN “get serial. ALIAS wr : qit IS rfile(3)(2). • DMA controller declarations. ALIAS go : qit IS rfile(3)(0). TYPE r4 IS ARRAY (0 TO 3) OF byte. Z. ALIAS ie : qit IS rfile(3)(3). Navabi and McGraw-Hill Inc. • Outline of DMA controller architecture. SIGNAL done : qit := '0'.18) -“direct CPU communications” blocks (Figure 11.19) END behavioral. SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8). CHAPTER 11 18 © 1999. .DMA DEVICE ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11.

1. IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb . END IF. adbus <= "ZZZZZZZZZZZZ". Navabi and McGraw-Hill Inc. done <= '1'.DMA DEVICE get_put : PROCESS VARIABLE buff : byte := zero_8. WAIT UNTIL clk = '1'. write_mem <= '0'.put to mem write_mem <= '1'. dev_rcv <= '0'.get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'. END LOOP writing. -. pntr := rfile(1)(3 DOWNTO 0) & rfile(0). adbus <= pntr. databus <= buff. WAIT UNTIL clk = '0'. databus <= "ZZZZZZZZ". • DMA controller “get serial and put parallel” process CHAPTER 11 19 © 1999. done <= '0'. numb := rfile(2). Z. VARIABLE numb : byte. pntr := pntr + 1. . buff := dev_data. WAIT UNTIL grant = '1'. BEGIN WAIT UNTIL go = '1'. END IF. dev_rcv <= '1'. WAIT UNTIL ready = '1'. END PROCESS get_put. -. VARIABLE pntr : twelve.

r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus. Navabi and McGraw-Hill Inc. ie.DMA DEVICE cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ". error2. • DMA controller “direct CPU communications” blocks CHAPTER 11 20 © 1999. error1). Z. r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1'. END BLOCK. . END BLOCK. END GENERATE cpu_direct.

select_reg). active : OUT qit. ready. BEGIN c1 : dma PORT MAP (clk. select_reg. END COMPONENT s2p. dev_rdy : IN qit. status_wr. s2p_er2. -. c3 : s2p PORT MAP (serial_in. COMPONENT s2p IS GENERIC (bps : INTEGER := 9600). SIGNAL cpu_mem_data : byte. description for diagram of Figure 11. status_wr : IN qit. read_mem. . PORT (adbus : IN twelve. status_sel. s2p_rcv. status_rd. select_reg : IN nibble. s2p_er2. databus. SIGNAL s2p_par : byte. END dma_serial_device. s2p_par). status_rd. received : IN qit. s2p_rdy. END structural. status_wr : IN qit. adbus. databus : INOUT byte := "ZZZZZZZZ". END COMPONENT dma. write_mem : OUT qit := '0'. c2 : dcd PORT MAP (adbus. SIGNAL cpu_mem_addr : twelve. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). adbus : INOUT twelve. databus : INOUT byte := "ZZZZZZZZ". adbus : INOUT twelve. overrun. Z. grant. s2p_er1. selects : OUT nibble).memory signals read_mem. s2p_er1. serial_in : IN qit). ready. dev_rcv : OUT qit. Navabi and McGraw-Hill Inc. status_rd. s2p_rcv.14 CHAPTER 11 21 © 1999. grant : IN qit. s2p_rdy. frame_error : OUT qit. s2p_rcv. read_mem. END COMPONENT dcd. ready. write_mem. grant : IN qit. SIGNAL select_reg : nibble. error1. SIGNAL s2p_rdy. error2. COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"). dev_data : IN byte ). status_sel : OUT qit. s2p_er2 : qit. s2p_er1. s2p_par). • DMA serial device. write_mem : OUT qit. -ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit. PORT (serial. dataready : BUFFER qit.DMA DEVICE ENTITY dma_serial_device IS PORT (clk : IN qit.

Navabi and McGraw-Hill Inc. .CPU CACHE adbus valid set tag 5 To 32 tag line Way 0 Way 1 5 DCD LSB 7 MSB 8 8 v=1 & v=1 Match & Match 0 8 1 Hit • Cache Block Diagram CHAPTER 11 22 © 1999. Z.

Z. DCD lru • The lru table CHAPTER 11 23 © 1999.CPU CACHE adbus 5 7 MSB LSB 5 To 32 1: If a recent data was found in Way 0. . Navabi and McGraw-Hill Inc. 0: If a recent data was found in Way 1.

CPU CACHE me me m_ m_ ad dat bu abu s s rea gra wr read dy nt_ ite_ _m _m m m e em em em m cache da tab us ad bu s rea dy gra nt wr ite rea d 24 clk • Cache Interface CHAPTER 11 © 1999. Z. . Navabi and McGraw-Hill Inc.

. write : IN qit. grant. ready_mem : IN qit. END cache_system. databus : INOUT byte := "ZZZZZZZZ".cpu signals read. -.memory signals read_mem. -.CPU CACHE ENTITY cache_system IS PORT (clk : IN qit. mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ". adbus : INOUT twelve := "ZZZZZZZZZZZZ" ). mem_databus : INOUT byte := "ZZZZZZZZ". Navabi and McGraw-Hill Inc. Z. • Cache Entity Declaration CHAPTER 11 25 © 1999. ready : OUT qit. write_mem : OUT qit. grant_mem.

pass data to CPU For write. END PROCESS. END control_and_memory. write If hit: For read. • Outline of cache VHDL description CHAPTER 11 26 © 1999. write data in cache and memory If miss: Find least recently used For write. . read from memory and pass on to CPU Wait until (read OR write)=’1’. Navabi and McGraw-Hill Inc.CPU CACHE ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read. write data in cache and memory For read. Z.

Z. free : ways. tag : tags. Navabi and McGraw-Hill Inc. ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0). SIGNAL lru : lru_type. TYPE lru_type IS ARRAY (sets) OF ways. CONSTANT nw : ww := (1.CPU CACHE SUBTYPE ways IS INTEGER RANGE 0 TO 1. • Controller local declarations CHAPTER 11 27 © 1999. TYPE cache_type IS ARRAY (ways) OF each_cache. ALIAS tag_value : tags IS adbus (11 DOWNTO 5). TYPE line IS ARRAY (0 TO 0) OF byte. END RECORD. VARIABLE hit : BOOLEAN. SUBTYPE sets IS INTEGER RANGE 0 TO 31. • Cache structure declarations VARIABLE s : sets. VARIABLE w. . TYPE entry IS RECORD valid : BOOLEAN. SIGNAL cache : cache_type. 0). TYPE ww IS ARRAY(ways) OF ways. SUBTYPE tags IS qit_vector (6 DOWNTO 0). TYPE each_cache IS ARRAY (sets) OF entry. data : line.

• Controller code for cache hit CHAPTER 11 28 © 1999. FOR i IN ways LOOP IF cache(i)(s). Z. mem_adbus <= "ZZZZZZZZZZZZ". WAIT UNTIL grant_mem = '1'. ready <= '1'. ready <= '0'. hit := FALSE. . databus <= cache(w)(s).valid <= TRUE. cache(w)(s). write_mem <= '1'. s := TO_INTEGER (set_value). WAIT UNTIL ready_mem = '1'. • Controller search in cache IF hit THEN lru (s) <= nw (w). mem_databus <= "ZZZZZZZZ". databus <= "ZZZZZZZZ". write_mem <= '0'. ELSIF write = '1' THEN cache(w)(s).tag = tag_value AND cache(i)(s). WAIT UNTIL clk = '0'. w := i.valid THEN hit := TRUE.data(0) <= databus. ready <= '0'. Navabi and McGraw-Hill Inc.CPU CACHE grant <= '1'. END LOOP. END IF.data(0). WAIT UNTIL write = '0'. IF read = '1' THEN ready <= '1'. mem_databus <= databus. END IF. mem_adbus <= adbus. WAIT UNTIL read = '0'.

data(0) <= databus. write_mem <= '0'. mem_adbus <= "ZZZZZZZZZZZZ". WAIT UNTIL ready_mem = '1'. • Controller code for cache miss CHAPTER 11 29 © 1999.tag <= tag_value. END IF. ELSIF read = '1' THEN read_mem <= '1'. cache(free)(s). IF write = '1' THEN cache(free)(s). mem_adbus <= adbus. WAIT UNTIL grant_mem = '1'. END IF. ready <= '0'. Z. lru (s) <= nw (lru (s)). WAIT UNTIL write = '0'. ready <= '0'. cache(free)(s). read_mem <= '0'. write_mem <= '1'.valid <= TRUE. WAIT UNTIL ready_mem = '1'. cache(free)(s). WAIT UNTIL read = '0'. cache(free)(s).tag <= tag_value. WAIT UNTIL grant_mem = '1'. .data(0) <= mem_databus.miss free := lru (s). ready <= '1'. mem_databus <= databus. mem_adbus <= "ZZZZZZZZZZZZ".CPU CACHE ELSE -. mem_adbus <= adbus. ready <= '1'. databus <= mem_databus.valid <= TRUE. Navabi and McGraw-Hill Inc. mem_databus <= "ZZZZZZZZ". cache(free)(s).

CPU CACHE Arbiter s2p Mem DMA Cache Decoder Parwan CPU • Board level interface CHAPTER 11 30 © 1999. Z. Navabi and McGraw-Hill Inc. .

ready). csh_ready. -ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1'. csh_grant. grant_mem. rd_req(1). srg : sergen PORT MAP (serial_in). cpu_write. . interrupt. cpu_data. dev : serial PORT MAP (clock. csh : cache PORT MAP (clock. cs. ready. '0' AFTER 4500 NS. csh_ready. skip_wait. cpu_read. data. clock. cpu_read. data. Navabi and McGraw-Hill Inc. grant_mem(0). rwbar. clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock. rd_req(0). skip_wait. Z.CPU CACHE ENTITY parwan_tester IS END parwan_tester. address. • Interface board VHDL description CHAPTER 11 31 © 1999. serial_in). rwbar. arb : arbitr GENERIC MAP ((OTHERS => 2). cpu_data. wr_req(1). grant_mem(1). cpu : parwan PORT MAP (clock. mem : memory PORT MAP (cs. address). wr_req(0). wr_req. END system. data. cpu_read. address. ready. cpu_address. period) PORT MAP (rd_req. halted. cpu_address). cpu_write. csh_grant). cpu_write.

SUMMARY In this chapter we presented a board level design in VHDL. Navabi and McGraw-Hill Inc. As opposed to Chapter 10 in which hardware details of a design were of concern. Language constructs for behavioral descriptions and timing and control were emphasized. We illustrated the use of VHDL in a component level design environment. The interface of the memory component is non-responsive. show various forms of using wait statements in describing a design. Several components with differing handshaking schemes were independently described. The examples presented here. VHDL constructs used in this chapter were primarily at the behavioral level as discussed in Chapter 9. . • End of Chapter 11 CHAPTER 11 32 © 1999. this chapter presented design at a higher level of abstraction. and how VHDL constructs can be used for handing communication between various devices. Z. We have illustrated how such handshaking schemes can be described in VHDL. while other components such as the CPU and cache controller have two or three line fully-responsive or partially-responsive handshaking schemes.

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