Chapter 1

Hardware design environments

1.1 DIGITAL SYSTEM DESIGN PROCESS 1.1.1 Design Automation 1.2 The Art of Modeling 1.3 HARDWARE DESCRIPTION LANGUAGES 1.3.1 A Language for Behavioral Descriptions 1.3.2 A Language for Describing Flow of Data 1.3.3 A Language for Describing Netlists 1.4 HARDWARE SIMULATION 1.4.1 Oblivious Simulation 1.4.2 Event Driven Simulation 1.5 HARDWARE SYNTHESIS TEST APPLICATIONS 1.6 LEVELS OF ABSTRACTION 1.7 SUMMARY

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© 1999, Z. Navabi and McGraw-Hill Inc.

A digital system design process

Design Idea

Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing

Chip or Board

• Top-down design process • Starting with a design idea • Generating a chip or board

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© 1999, Z. Navabi and McGraw-Hill Inc.

Result of the data path design phase.

DATA

CONTROL

REG1

REG2 Procedure for Control of Movement of Data Between Registers and Buses.

...

MAIN LOGIC UNIT

REG3

LOGIC

...

• Dataflow description • Control Data partitioning

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© 1999, Z. Navabi and McGraw-Hill Inc.

An ISPS example, a simple processor.

mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** {tc} MAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END

• Behavioral Example • Only describing functionality

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© 1999, Z. Navabi and McGraw-Hill Inc.

An AHPL example, a sequential multiplier.

AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2); 1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7]; extra <= 4$0; => ( ^dataready, dataready ) / (1, 2). 2 busy <= \1\; => ( ^ac1[3], ac1[3] ) / (4, 3). 3 extra <= ADD[1:4] (extra; ac2). 4 extra, ac1 <= \0\, extra, ac1[0:2]; count <= INC(count); => ( ^(&/count), (&/count) ) / (2, 5). 5 result = extra, ac1; done = \1\; busy <= \0\; => (1). ENDSEQUENCE CONTROLRESET(1). END.

• Dataflow description • Describing clock control timing • AHPL, A Hardware Programming Language

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© 1999, Z. Navabi and McGraw-Hill Inc.

Full-adder, logical diagram and Verilog code.
a b c g1 w1 g5 s

g2 g3 g4 w3

w2

g6 w4

co

`timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule

• Gate level structural description • Describes gate level timing • Graphical and language based descriptions
CHAPTER 1 6 © 1999, Z. Navabi and McGraw-Hill Inc.

Hardware simulation.

Hardware Description (Model)

Simulation Hardware Model

Simulation Engine Component Library (Models)

Simulation Results (Output)

Test Data (Stimuli)

• Hardware simulation process • Component models, unit model form hardware model • Testbench may provide test data

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Verifying each design stage.

Design Idea SIMULATION TOOLS Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing Product Sample. Chip or Board Final Testing Device Simulator Gate Level Simulator Dataflow Simulator Behavioral Simulator

• Simulate at each step • Simulate to verify translation into lower level • Simulation cost increases at lower levels

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© 1999, Z. Navabi and McGraw-Hill Inc.

Simulating an exclusive-OR

a

1 3

5

7 4 b 2 6

z

t a b

0

1

2

3

4

5

6

7

8

9

0

• Simulating an XOR • Apply data at given time intervals or • Apply data as events occur

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Oblivious simulation.

GATE 1 2 3 4 5 6 7

FUNCTION Input Input NOT NOT AND AND OR

INPUT 1 a b 2 1 1 4 5

INPUT 2 ----3 2 6

VALUE 0 0 1 1 0 0 0

• Table representation • Simulate until no changes are made • Record values at table entries

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© 1999, Z. Navabi and McGraw-Hill Inc.

Event driven simulation.

1 a Inp 0

3 -

5 0 AND 0

NOT

OR 2 b Inp 0 NOT 0 AND 0 4 6

0

Legend: In1 In2 Fnc Out In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value

• Linked list representation • Simulate links with input events • Record values at node entries

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. Z..Categories of synthesis tools... most commercial tools are 2 CHAPTER 1 12 © 1999. . .. Design Idea Behavioral Design SYNTHESIS TOOLS 1 4 6 5 3 Physical Design Transistor List. Navabi and McGraw-Hill Inc. Pseudo Code. Data Path Design Bus & Register Structure Logic Design Chip or Board • Synthesis • Transformation from one level to another • Ideal is 6. Manufacturing 2 Flow Graph. Layout.

Synthesis process. . Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives Synthesis Engine Logic Optimization Binding Synthesized Hardware (Netlist) • Hardware description and directives are tool inputs • Three synthesis stages • Layout or netlist is generated CHAPTER 1 13 © 1999. Z. Navabi and McGraw-Hill Inc.

d <= a + b.Resource sharing. a b a ADDER x b y ADDER c d c • Input description affects synthesis results • Explicit specification of resource sharing • Sharing without and with extra overhead CHAPTER 1 14 © 1999. Navabi and McGraw-Hill Inc. Z. c <= x + y. c <= a + b. c <= a + b. .

2 EXISTING LANGUAGES 2.5 Generic Design 2.2.8 Timing Control 2.3.7 TI-HDL 2.2.3.1 VHDL INITIATION 2.3.9 Structural Specification 2.3 Library Support 2.1 AHPL 2.3.4 Sequential Statement 2.6 TEGAS 2.2.3 CONLAN 2.2.2 Support for Design Hierarchy 2.5 ISPS 2.4 IDL 2.Chapter 2 VHDL Background 2. Navabi and McGraw-Hill Inc.3.3.3.3.8 ZEUS 2. .5 SUMMARY CHAPTER 2 1 © 1999.4 THE VHDL LANGUAGE 2.2 CDL 2.3. Z.2.3 VHDL REQUIREMENTS 2.2.2.7 Use of Subprograms 2.1 General Features 2.2.6 Type Declaration and Usage 2.

. Z. Navabi and McGraw-Hill Inc.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs • Part of VHSIC program CHAPTER 2 2 © 1999.

2 was released to IEEE ITAR removed from software • May 1985 : Standard VHDL 1076/A • December 1987 : VHDL 1076-1987 became IEEE standard • 1993 : VHDL 1076-1993 was approved CHAPTER 2 3 © 1999. . Intermetrics : VHDL 2.VHDL Initiation • 1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions • 1983 DoD : Requirements were established Contract was awarded to IBM. TI.0 was defined • December 1984 : VHDL 6. Intermetrics ITAR restrictions removed from language • 1984 IBM. Navabi and McGraw-Hill Inc.0 was released Software development started • 1985 : VHDL 7. TI. Z.

Navabi and McGraw-Hill Inc.Languages reviewed • AHPL • CDL • CONLAN • IDL • ISPS • TEGAS • TI-HDL • ZEUS : A Hardware Programming Language : Computer Design Language : CONsensus LANguage : Interactive Design Language : Instruction Set Processor Specification : TEst Generation And Simulation : TI Hardware Description Language : An HDL by GE corpration CHAPTER 2 4 © 1999. Z. .

Z. Simulation. Synthesis. Automatic hardware • Design Hierarchy Multi-level description Partitioning • Library Support Standard Packages Cell based design • Sequential Statements Behavioral software-like constructs CHAPTER 2 5 © 1999. Navabi and McGraw-Hill Inc. High level design.VHDL Requirements • General Features Documentation. . Test.

concurrency • Structural Specification Wiring components CHAPTER 2 6 © 1999.VHDL Requirements • Generic Design Binding to specific libraries • Type Declaration Strongly typed language • Subprograms • Timing Delays. Navabi and McGraw-Hill Inc. . Z.

Navabi and McGraw-Hill Inc.VHDL Requirements CPU STACK ALU MUX COUNTER ALU BIT n BIT n-1 BIT 0 ALU_BIT ADDER MUX LOGIC MUX AND OR NOT • Use various levels of abstraction for defining a system • Upper level systems are partitioned into lower CHAPTER 2 7 © 1999. . Z.

. Navabi and McGraw-Hill Inc.Example for hierarchical partitioning. Z. CPU STA CK A LU M UX COUNTER AL U BI T n BIT n-1 BIT 0 AL U_BI T A DDER M UX L OGIC M UX AND OR NOT • Recursive partitioning • Simple components as terminals CHAPTER 2 8 © 1999.

Z.An example VHDL environment. LIBRARY SYSTEM .2 Design Libraries Library Management Library Environment • VHDL defines library usage • Tools define library management CHAPTER 2 9 © 1999. . 1 .3 VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools VHDL Input Analyzer Lib. Navabi and McGraw-Hill Inc.

5 CONTROLLER DESCRIPTION 3.4 SUBPROGRAMS 3.3.Chapter 3 Design Methodology Based on VHDL 3.1.2 TOP-DOWN DESIGN 3.3.2 Setting The Stage 3.3.1.7 CONVENTIONS AND SYNTAX 3.1.6 VHDL OPERATORS 3.3 Libraries and Binding 3.2.3 TOP-DOWN DESIGN WITH VHDL 3.3. . Navabi and McGraw-Hill Inc.1 Design to Perform 3.1 ELEMENTS OF VHDL 3. Z.1 Describing Components 3.2 Packages 3.1 Verification 3.8 SUMMARY CHAPTER 3 1 © 1999.5 Real World 3.3 Design Scenario 3.3.4 Final Act 3.

END component_name. Z.Interface and architectural specifications. physical and other parameters. CHAPTER 3 2 © 1999. ARCHITECTURE identifier OF component_name IS declarations. ENTITY component_name IS input and output ports. BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters. Navabi and McGraw-Hill Inc. . END identifier.

..Multiple architectural specifications. . CHAPTER 3 3 © 1999. ARCHITECTURE structural OF component_i IS .. .. other ARCHITECTURES OF component_i .. .. Navabi and McGraw-Hill Inc. ENTITY component_i IS PORT (. ... ARCHITECTURE behavioral OF component_i IS .. Z.. ..... . ) . ARCHITECTURE dataflow OF component_i IS .

END package_name. CHAPTER 3 4 © 1999. PACKAGE BODY package_name IS type definitions. Z.Packages. sub-program declasrations. Navabi and McGraw-Hill Inc. PACKAGE package_name IS component declarations. sub-programs. . END package_name.

LIBRARY library_name. END CONFIGURATION.Design binding. binding components of a library to subcomponents. CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. . Z. CHAPTER 3 5 © 1999. Navabi and McGraw-Hill Inc. specifying parameters of a design.

Z. . END Partition. END IF. CHAPTER 3 6 © 1999.Recursive partition procedure. END FOR. Navabi and McGraw-Hill Inc. Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i).

Navabi and McGraw-Hill Inc. CHAPTER 3 7 © 1999.Top-down design. Z. . SUD Design Implementation SSC1 SSC2 SSC3 SSC4 SSC31 . SSC3n SSC41 SSC42 SSC311 SSC312 SSC3n1 SSC3n2 SUD: System Under Design SSC : System Sub-Component Shaded areas designate sub-componts with hardware implementation... bottom-up implementation.

Verifying the first level of partitioning. Z. Behavioral Model are mp Co SUD SSC1 SSC2 SSC3 SSC4 Interconnection of Behavioral Models CHAPTER 3 8 © 1999. Navabi and McGraw-Hill Inc. .

Navabi and McGraw-Hill Inc. Z. Behavioral Model are omp C SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model CHAPTER 3 9 © 1999. .Verifying hardware implementation.

. Behavioral Model e par Com SUD SSC1 SSC2 SSC3 SSC4 Har dwa re M odel SSC31 . Z. SSC3n SSC41 SSC42 SSC311 SSC312 CHAPTER 3 10 © 1999.. .Verifying the final design. Navabi and McGraw-Hill Inc.

Z. Behavioral Model SSC3 Co m pa re SSC31 . Navabi and McGraw-Hill Inc.. SSC3n SSC311 SSC312 .. . SSC3n1 SSC3n2 Hardware Model CHAPTER 3 11 © 1999..Verifying hardware implementation of SSC3..

CHAPTER 3 12 © 1999. an alternative to the setup of Figure 3. Z. Navabi and McGraw-Hill Inc. .9. p Com are SUD SSC1 SSC2 SSC3 SSC4 Mixed Level Model SSC41 SSC42 Verifying the final design.Verifying the final design.

Z. Navabi and McGraw-Hill Inc. a b start clock Synchronously add data on a and b put result on result.Serial adder. . result ready CHAPTER 3 13 © 1999.

1R S1 1D Z 1D C1 Q _ 1D (a) Multiplexer (b) Flipflop CHAPTER 3 14 © 1999. Navabi and McGraw-Hill Inc.Available library elements. . Z.

. -ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay. data0 : IN BIT. Navabi and McGraw-Hill Inc. END dataflow. VHDL model of the multiplexer library element. z : OUT BIT). END mux2_1.Multiplexer library element. Z. PORT (sel. ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). data1. CHAPTER 3 15 © 1999.

Dataflow descriptions. CHAPTER 3 16 © 1999. . Busb Reg File Reg1 Alu Controller Reg2 Busa Dataflow descriptions. Z. Navabi and McGraw-Hill Inc.

CHAPTER 3 17 © 1999. END flop. VHDL model of the flip-flop library element. END PROCESS. Navabi and McGraw-Hill Inc. td_in : TIME := 8 NS). Z. ELSE qout <= din AFTER td_in. END IF. -ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset. . clk : IN BIT. PORT (reset. ENTITY flop IS GENERIC (td_reset. qout : BUFFER BIT := '0').Flip-flop library element. din. END behavioral. END IF.

. Behavioral descriptions. Valid ? Transmit . CHAPTER 3 18 © 1999. . Navabi and McGraw-Hill Inc. Z.Behavioral descriptions. Receive FOR all data : Process data : Queue data : END FOR. .

PORT (reset. END counter. counter. END PROCESS. ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS). counting : OUT BIT := '0'). END IF. counter. END IF. CHAPTER 3 19 © 1999. BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0. ELSE counting <= '1' AFTER td_cnt. ELSE IF count < limit THEN count := count + 1. END IF.Divide by 8. Z. -ARCHITECTURE behavioral OF counter IS BEGIN PROCESS (clk) VARIABLE count : INTEGER := limit. IF count = limit THEN counting <= '0' AFTER td_cnt. END behavioral. Navabi and McGraw-Hill Inc. Divide by 8. END IF. . CONSTANT limit : INTEGER := 8. clk : IN BIT.

Navabi and McGraw-Hill Inc. VHDL Boolean p r e d e s i g n e d layouts Synthesize l i b r a r y mux2-1 Count flop CMOS layout CHAPTER 3 20 © 1999.Design stage setting. Z. .

BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. . END IF. END IF. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END behavioral. carry : BIT. ELSE ready <= '0'. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) VARIABLE count : INTEGER := 8. Serial adder behavioral description. sum := a XOR b XOR carry. Z. CHAPTER 3 21 © 1999. END serial_adder. start.Serial adder behavioral description. END IF. clock : IN BIT. ready : OUT BIT. carry := (a AND b) OR (a AND carry) OR (b AND carry). END PROCESS. carry := '0'. ENTITY serial_adder IS PORT (a. result <= sum & result (7 DOWNTO 1). IF count = 8 THEN ready <= '1'. END IF. ELSE IF count < 8 THEN count := count + 1. Navabi and McGraw-Hill Inc. VARIABLE sum. b.

VHDL simulation results. CHAPTER 3 22 © 1999. Navabi and McGraw-Hill Inc. . Z.

result <= sum & result (7 DOWNTO 1). END IF.Partial code of serail_adder. Navabi and McGraw-Hill Inc. CHAPTER 3 23 © 1999. Z. sum := a XOR b XOR carry. . ELSE IF count < 8 THEN count := count + 1. carry := (a AND b) OR (a AND carry) OR (b AND carry ).

. counting counter serial_sum en si a b Adder carry_out Flop result Shift Regiser carry_in clock CHAPTER 3 24 © 1999. Z.General layout of serial_adder. Navabi and McGraw-Hill Inc.

Z.First level of partitioning. Navabi and McGraw-Hill Inc. . serial_adder full_adder flip_flop shifter counter CHAPTER 3 25 © 1999.

. CHAPTER 3 26 © 1999. cout : OUT BIT).Full_adder description. cin : IN BIT. Navabi and McGraw-Hill Inc. ENTITY fulladder IS PORT (a. END behavioral. Z. cout <= (a AND b) OR (a AND cin) OR (b AND cin). b. END fulladder. sum. -ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin.

Z. END shifter. END BLOCK.Shifter VHDL description. CHAPTER 3 27 © 1999. ENTITY shifter IS PORT (sin. -ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED. reset. clk : IN BIT. enable. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). Navabi and McGraw-Hill Inc. END dataflow. .

.Completed parts of first partitioning. Navabi and McGraw-Hill Inc. serial_adder full_adder flop shifter counter CHAPTER 3 28 © 1999. Z.

Structural description of serial_adder. -ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS). ENTITY serial_adder IS PORT (a. COMPONENT flop IS GENERIC (td_reset. carry_in. counting : BIT. result : BUFFER BIT_VECTOR (7 DOWNTO 0)). END serial_adder. carry_out. start. u4 : shifter PORT MAP (serial_sum. u5 : ready <= NOT counting. clock. td_in : TIME := 8 NS). clk : IN BIT. sum. Z. -SIGNAL serial_sum. PORT (reset. END COMPONENT. start. result). carry_out). END COMPONENT. b. END COMPONENT. CHAPTER 3 29 © 1999. b. END structural. COMPONENT fulladder IS PORT (a. parout : BUFFER BIT_VECTOR(7 DOWNTO 0)). clk : IN BIT. counting). counting. enable. carry_out. BEGIN u1 : fulladder PORT MAP (a. serial_sum. counting : OUT BIT := '0'). clock. cout : OUT BIT). b. ready : OUT BIT. u2 : flop PORT MAP (start. qout : BUFFER BIT := '0'). cin : IN BIT. din. . reset. clock : IN BIT. carry_in). clock. clk : IN BIT. Navabi and McGraw-Hill Inc. END COMPONENT. u3 : counter PORT MAP (start. carry_in. COMPONENT shifter IS PORT (sin. PORT (reset.

Navabi and McGraw-Hill Inc. Z. Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out a b cin sum count Signals in the interface of fulladder CHAPTER 3 30 © 1999. .Signal mapping for fulladder instantiation.

carry_out ). b. . CHAPTER 3 31 © 1999. sum. carry_in. COMPONENT fulladder IS PORT (a. carry_out.Interconnecting ports. BEGIN u1 : fulladder PORT MAP (a. carry_in. counting : BIT. cin : IN BIT. b. carry_in). COMPONENT flop IS GENERIC (td_reset. clock. u2 : flop PORT MAP (start. din . serial_sum. clk : IN BIT. Z. cout : OUT BIT). carry_out . END COMPONENT. td_in : TIME := 8 NS). Navabi and McGraw-Hill Inc. PORT (reset. qout : BUFFER BIT := '0'). -SIGNAL serial_sum. END COMPONENT.

. shifter der_flop der_flop der_flop der_flop der_flop der_flop der_flop der_flop CHAPTER 3 32 © 1999. . .Partitioning shifter. Navabi and McGraw-Hill Inc. . Z.

END der_flop. Z. END IF. ENTITY der_flop IS PORT (din. . clk : IN BIT. qout : OUT BIT := '0'). reset. ELSE IF enable = '1' THEN qout <= din. END behavioral. END PROCESS. CHAPTER 3 33 © 1999. -ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'. END IF. Navabi and McGraw-Hill Inc. enable. END IF.Behavioral model of der_flop.

parout(4)). qout : BUFFER BIT := '0'). b2 : der_flop PORT MAP (parout(3). clk. reset. clk. parout(5)). b3 : der_flop PORT MAP (parout(4). parout(0)). . enable. Navabi and McGraw-Hill Inc. reset. END COMPONENT. END shifter. parout(6)). clk. END structural. clk : IN BIT. parout(1)). BEGIN b7 : der_flop PORT MAP ( sin. CHAPTER 3 34 © 1999. reset. b6 : der_flop PORT MAP (parout(7). reset. enable. reset. parout(7)). clk. Z. b0 : der_flop PORT MAP (parout(1). enable. enable. enable. reset. b5 : der_flop PORT MAP (parout(6). enable. clk. enable. parout(3)).Structural description of shifter. reset. clk. clk. reset. -ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din. reset. clk : IN BIT. b1 : der_flop PORT MAP (parout(2). parout(2)). clk. b4 : der_flop PORT MAP (parout(5). ENTITY shifter IS PORT (sin. parout : BUFFER BIT_VECTOR (7 DOWNTO 0)). enable. reset. enable. enable.

. enable reset din S1 1D qout 1R 1D C1 Q dff_in _ 1D clock CHAPTER 3 35 © 1999.Hardware realization of der_flop. Navabi and McGraw-Hill Inc. Z.

Partitioning der_flop. der_flop mux2_1 flop CHAPTER 3 36 © 1999. Z. Navabi and McGraw-Hill Inc. .

clk : IN BIT. END der_flop. BEGIN mx : mux2_1 PORT MAP (enable. COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS). din. -ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset. qout. dff_in. END COMPONENT. qout : BUFFER BIT). qout). SIGNAL dff_in : BIT. dff_in). data0 : IN BIT. Navabi and McGraw-Hill Inc. qout : BUFFER BIT := '0'). ENTITY der_flop IS PORT (din. ff : flop PORT MAP (reset. enable. z : OUT BIT). END behavioral. reset. PORT (sel. data1. clk. td_in : TIME := 8 NS). clk : IN BIT. din. CHAPTER 3 37 © 1999.Structural description of der_flop. . PORT (reset. Z. END COMPONENT.

. . . der-flop . mux2-1 flop . . serial-adder fulladder flop shifter counter der-flop der-flop . . CHAPTER 3 38 © 1999. Navabi and McGraw-Hill Inc. . Z. .Complete design of seraial_adder.

Navabi and McGraw-Hill Inc. . . a b Fulladder serial-sum 1 s1 1 1R Q 1D 1R Q 1D 1 s1 1 . reset Counter counting . 1 1R Q 1D C1 carry_in 1R 1D C1 C1 C1 Q carry_out clk . 1 s1 . . .. . Z. ..Final Design. . CHAPTER 3 39 © 1999.

END IF. carry := (a AND b) OR (a AND carry) OR (b AND carry). VARIABLE sum. b. BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0. END IF. sum := a XOR b XOR carry. END IF. IF count = 8 THEN ready <= '1'. END IF. ELSE ready <= '0'. result <= sum & result (7 DOWNTO 1). ELSE IF count < 8 THEN count := count + 1. END behavioral. VARIABLE count : CNT8 := 8. -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8.Synthesizable serial adder. END serial_adder. Z. start. . result : BUFFER BIT_VECTOR (7 DOWNTO 0)). carry := '0'. ENTITY serial_adder IS PORT (a. Navabi and McGraw-Hill Inc. carry : BIT. CHAPTER 3 40 © 1999. ready : OUT BIT. END PROCESS. clock : IN BIT.

. CHAPTER 3 41 © 1999. Z. Navabi and McGraw-Hill Inc.FPGA layout of serial_adder.

END byte_to_integer. oi := result.. . TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT. Z. BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i. CHAPTER 3 42 © 1999.. END LOOP. . PROCEDURE byte_to_integer (ib : IN byte. END IF. Navabi and McGraw-Hill Inc.Type conversion procedure. oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0.

FUNCTION fadd (a.The fadd (full adder) function. c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0). CHAPTER 3 43 © 1999. Z. RETURN sc. Navabi and McGraw-Hill Inc. b. . sc(0) := (a AND b) OR (a AND c) OR (b AND c). END. BEGIN sc(1) := a XOR b XOR c.

sum. b.fulladder using fadd. END behavioral. END fulladder. -ARCHITECTURE behavioral OF fulladder IS BEGIN (sum. CHAPTER 3 44 © 1999. . Navabi and McGraw-Hill Inc. b. cin). cin : IN BIT. Z. cout : OUT BIT). cout) <= fadd (a. ENTITY fulladder IS PORT (a.

Navabi and McGraw-Hill Inc. . . z<= .. . . .. . clock CHAPTER 3 45 © 1999. x1 x= . . . . z1 . xn z<= . .General outline of a controller. zn z<= . . x= .. .. Z.

Moore machine description. Z. z clk CHAPTER 3 46 © 1999. . Navabi and McGraw-Hill Inc. IF 110 sequence is detected on x THEN z gets '1' x ELSE z gets '0' END.

Z.Sequence detector state machine. . Navabi and McGraw-Hill Inc. 0 1 1 reset 0 0 0 got1 0 1 got11 0 1 0 got110 1 CHAPTER 3 47 © 1999.

Z. BEGIN PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1. END IF. z : OUT BIT). END IF. END CASE. END PROCESS. z <= ‘1’ WHEN current = got110 ELSE ‘0’. ELSE current <= reset. got110).VHDL Description of 110 detector. got11. ENTITY moore_110_detector IS PORT (x. ELSE current <= reset. END moore_110_detector. WHEN got11 => IF x = ‘1’ THEN current <= got11. END behavioral. . WHEN got1 => IF x = ‘1’ THEN current <= got11. END IF. Navabi and McGraw-Hill Inc. ELSE current <= got110. got1. clk : IN BIT . CHAPTER 3 48 © 1999. END IF. SIGNAL current : state := reset. ELSE current <= reset. -ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset. END IF. WHEN got110 => IF x = ‘1’ THEN current <= got1.

.. . 1 reset 0 0 got1 0 got11 0 .. END IF.State transition and corresponding VHDL code. WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset. Navabi and McGraw-Hill Inc.. Z. CHAPTER 3 49 © 1999. .

REAL Same Type REM INTEGER Same Type ABS MISCELLENEOUS ** Numeric Left: Numeric Right: Integer Same Type Same as Left CHAPTER 3 50 © 1999. Operators AND NAND XOR = < > SLL SLA ROL + OR NOR XNOR /= <= >= SRL SRA ROR & Operand Type BIT or BOOLEAN All Types Left: BIT or BOOLEAN Vector Right: INTEGER Numeric Array or Array Element Numeric Result Type BIT or BOOLEAN BOOLEAN LOGICAL RELATIONAL SHIFT BOOLEAN ADDING Same Type SIGN + - Same Type * MULTIPLYING MOD / INTEGER. . Z. Navabi and McGraw-Hill Inc.VHDL operators.

IT B G E IN a <= '1' A T R1 N . E Dd m . . Z. FE 5 S b< N TaA T R5N . b. = O FE S c <= a AFTER 10 NS. N e o architecture declarative_part architecture body architecture statem n e t_part CHAPTER 3 51 © 1999. c : B := '0'. A C I E T R d m O e a p IS R HT C U E e o F z m le S IGNAL a.Syntax details of the architecture body. Navabi and McGraw-Hill Inc.

3.3 SIGNAL ASSIGNMENTS 4. .1 Concurrent Assignments 4.4 Sequential Placements of Transactions 4.4.1.3 Modeling Hardware 4. Z.2 Transport Delay Mechanism 4.4.2 Concurrency 4.2 Events and Transactions 4.4.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS 4.1 Inertial Delay Mechanism 4.Basic Concepts in VHDL 4.5 SUMMARY CHAPTER 4 1 © 1999.2 OBJECTS AND CLASSES 4.1 CHARACTERIZING HARDWARE LANGUAGES 4. Navabi and McGraw-Hill Inc.3.3 Comparing Inertial and Transport 4.1.1.1 Timing 4.4.3 Delta Delay 4.3.

Value transfer through wires. . • What happens in a real hardware • Must be able to model properly CHAPTER 4 2 © 1999. Navabi and McGraw-Hill Inc. Z.

b := x. Navabi and McGraw-Hill Inc. . a := x. Z. b <= x AFTER 3*unit_delay. • In one case immediate assignemnts are done • In another case scheduling is done CHAPTER 4 3 © 1999.Value transfer through wires. a <= x AFTER 4*unit_delay.

Navabi and McGraw-Hill Inc. Z.Describing sub-components. . S A B C • Hardware description requires concurrent constructs • Concurrent bodies can be described behaviorally or at the dataflow level CHAPTER 4 4 © 1999.

A VHDL concurrent body • A VHDL concurrent body • Statements are executed when events occur CHAPTER 4 5 © 1999. Z. . Navabi and McGraw-Hill Inc.

. . FOR LOOP ... IF THEN ELSE . . BEGIN . PROCESS .. . Navabi and McGraw-Hill Inc. . BEGIN . ... END ARCHITECTURE • A VHDL sequential body • Statements are executed when program flow reaches them CHAPTER 4 6 © 1999... Z. .A VHDL sequential body ARCHITECTURE sequential . END PROCESS . .

Navabi and McGraw-Hill Inc.Illustrating timing and concurrency. a b g2 x z g4 c g1 w g3 y • Four concurrent gates • Each has a delay of 12 ns • Change in inputs may result in in output hazards CHAPTER 4 7 © 1999. . Z.

Gates reacting to changes. . Navabi and McGraw-Hill Inc. Z. g1 g2 g3 g4 R a tin e c g R a tin e c g R a tin e c g R a t e c ing R a tin e c g 0 12 24 36 Nanosecond • a changes from ‘1’ to ‘0’ • A change in the a input results in domino changes each 12 ns apart • No more events occur when output is reached CHAPTER 4 8 © 1999.

Z.a b c w x y z 0 12 24 36 Nanosecond • Timing diagram resulting from input a changing from ‘1’ to ‘0’ at time zero • A glitch appears on the output • Must model hardware to imitate this behavior • Requires timing and concurrency in the language CHAPTER 4 9 © 1999. Navabi and McGraw-Hill Inc. .

Z... y_signal z_signal <= .... u_signal concurrent_body_2 x_signal <= . . w_signal <= .. w_signal v_signal concurrent_body_3 u_signal <= local_constant v_signal <= .. b_signal y_signal <= .Objects and Classes del1_constant del2_constant concurrent_body_1 sequential_body_1 a_signal a_variable := ....... loop_variable_i .. Navabi and McGraw-Hill Inc... x_signal y_signal <= . z_signal • Objects and classes in sequential and concurrent bodies • Foundation for modeling timing and concurrency are signals • Variables are used as software variables CHAPTER 4 10 © 1999.

. Z. Navabi and McGraw-Hill Inc.Objects and Classes Using Objects In VHDL O B J E C T Signal Variable Constant File BODY Declare YES NO YES YES Concurrent Assign to YES NO --Use YES YES YES YES Declare NO YES YES YES Sequential Assign to YES YES --Use YES YES YES YES • Objects in VHDL bodies • Cannot declare signals in sequential bodies • Variable assignments are only done in sequential bodies CHAPTER 4 11 © 1999.

target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT.Illustrating inertial delay target1 <= waveform AFTER 5 NS. diff23 : BIT. Navabi and McGraw-Hill Inc. ‘0’ AFTER 68 NS. . END delay. ‘1’ AFTER 71 NS. target3 : BIT. ‘1’ AFTER 14 NS. ‘1’ AFTER 24 NS. Z. ‘0’ AFTER 77 NS. -. SIGNAL target1.Creating waveform waveform <= ‘1’ AFTER 03 NS. ‘1’ AFTER 79 NS. -. diff13.Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS. Reject and Transport • Inertial: rejects anything less than its delay • Reject: rejects anything less than or equal to its reject • Transport: does not reject CHAPTER 4 12 © 1999. SIGNAL diff12.Comparing targets diff12 <= target1 XOR target2. ‘0’ AFTER 58 NS. target2.This is a comment BEGIN -. -. ‘1’ AFTER 41 NS. diff13 <= target1 XOR target3. diff23 <= target2 XOR target3. ‘1’ AFTER 52 NS. ‘0’ AFTER 27 NS. ‘1’ AFTER 62 NS. ‘0’ AFTER 18 NS.Delay Mechanisms ENTITY example IS END ENTITY. ‘0’ AFTER 85 NS. -. ‘1’ AFTER 33 NS. • VHDL description for the demonstration of delay mechanisms • Example shows several concurrent statements • Inertial. ‘0’ AFTER 47 NS. ‘0’ AFTER 35 NS. ‘0’ AFTER 08 NS.

. Navabi and McGraw-Hill Inc.Delay Mechanisms R Target 1 or Target 2 C • The RC delay is best represented by inertial delay mechanism • This is a simple version of Inertial • For more accurate modeling Reject can be used CHAPTER 4 13 © 1999. Z.

. Navabi and McGraw-Hill Inc.Delay Mechanisms 5 6 4 6 3 6 2 6 6 5 6 4 6 3 6 2 6 • Illustrating differences between delay mechanism in VHDL • Positive and negative pulses appear on the LHS CHAPTER 4 14 © 1999. Z.

c : IN BIT. x. END concurrent. • VHDL description for the gate level circuit for the demonstration of timing and concurrency • Four concurrent statements model gates of the circuit • Events of the RHS cause evaluation and scheduling • A scheduled value may or may not appear on the LHS • A scheduled value is a transaction on the driver of the LHS signal CHAPTER 4 15 © 1999. ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w. b. . Z. z : OUT BIT). BEGIN w <= NOT a AFTER 12 NS. x <= a AND b AFTER 12 NS. Navabi and McGraw-Hill Inc. z <= x OR y AFTER 12 NS. y : BIT.Concurrency ENTITY figure_5_example IS PORT (a. END figure_5_example. y <= c AND w AFTER 12 NS.

Concurrency Resolution Function Multiple Driving Values Signal Value • A signal may have more than one driver • Resolving a single value from multiple driving values • Each driver has its own timing • Independent handling of all drivers • A driving value that is current contributes to the resolution function CHAPTER 4 16 © 1999. Z. . Navabi and McGraw-Hill Inc.

0) now • A transaction. d) d-t0 tri = (v. d-t ) 0 EXPIRED 0 t t 0 t1 d tri = (v. Navabi and McGraw-Hill Inc. Z. from being created to being expired • A transaction that expires generates a current driving value • This value contributes to the resolution function CHAPTER 4 17 © 1999. .Events and Transactions transaction time component d tri = (v.

Z. Navabi and McGraw-Hill Inc. c : BIT := '0'.Events and Transactions ARCHITECTURE demo OF example IS SIGNAL a. END demo. b. BEGIN a <= '1' AFTER 15 NS. . b <= NOT a AFTER 5 NS. c <= a AFTER 10 NS. • A simple description for illustrating events and transactions • Transactions are scheduled on the 3 LHS signals • Order is not significant • Initial transaction are placed on all 3 signals CHAPTER 4 18 © 1999.

Events and Transactions a 0 0 0 b c 0 5 10 (a) 15 20 25 NS Transactions W hen They Are Placed on Signals (1. Navabi and McGraw-Hill Inc. 10) on c (1. . 05) on b (0. Z. 05) on b (0. 10) on c 0 5 10 (b) 15 20 25 NS Transactions At 5 NS Intervals a c b a c a c b c 0 5 10 (c) 15 20 25 NS Path Of Transactions To Expiration a c b b NS c 0 5 10 15 20 25 • Events and transactions (d) CHAPTER 4 19 © 1999. 15) on a (1.

Z. END delta. zbar : BUFFER BIT). Navabi and McGraw-Hill Inc. • Demonstrating need for delta delay • A “hidden” delay exists between z and z_bar • Delta delay makes us believe that they take place at the same real time • The hidden delay is Delta which is not real-time CHAPTER 4 20 © 1999. z. -ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z. .Delta Delay ENTITY timing IS PORT (a. b : IN BIT. z <= a AND b AFTER 10 NS. END ENTITY.

x. BEGIN y <= c AND w. Navabi and McGraw-Hill Inc. • VHDL description for demonstrating the delta delay • Sequentiality in execution. y : BIT := '0'. x <= a AND b. END not_properly_timed. same exact real time CHAPTER 4 21 © 1999. w <= NOT a.Delta Delay ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w. Z. . z <= x OR y AFTER 36 NS.

Navabi and McGraw-Hill Inc.Delta Delay a1 b1 c1 w0 x0 y 0 z1 0 1 2δ 3δ 0 δ 12 24 36 NS • Timing diagram showing delta delays • Looking at real times. we do not see Sequentiality CHAPTER 4 22 © 1999. . Z.

• Description for a chain of two inverters • Demonstrating Delta. Z. . b.Delta Delay ARCHITECTURE concurrent OF timing_demo IS SIGNAL a. b <= NOT a. c : BIT := '0'. BEGIN a <= '1'. END concurrent. c <= NOT b. transactions and concurrency CHAPTER 4 23 © 1999. Navabi and McGraw-Hill Inc.

Z.Delta Delay a 0 b0 c 0 0 δ 1 2δ 3δ 0 NS • Timing diagram for timing_demo • Everything happens at real-time 0 CHAPTER 4 24 © 1999. . Navabi and McGraw-Hill Inc.

SIGNAL y: BIT := ‘1’. ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’. BEGIN x <= y. END forever. . x 0 0 1δ 2δ 3δ 4δ 5δ 6δ 7δ 0 t y 1 0 1δ 2δ 3δ 4δ 5δ 6δ 0 t • Oscillation in zero real time • Don’t try this at home CHAPTER 4 25 © 1999. Navabi and McGraw-Hill Inc. y <= NOT x. Z.Delta Delay y x Ideal elements with zero real time delay.

Navabi and McGraw-Hill Inc.. statement suspends a sequential body forever • Sequentially values are placed on the LHS CHAPTER 4 26 © 1999. x<= v2 AFTER t2. BEGIN PROCESS x<= v1 AFTER t1. Z. END sequential.Sequential Placement of Transactions ARCHITECTURE sequential OF sequential_placement IS . . • Sequential placement of transactions in a sequential body of VHDL • A wait. WAIT.. END PROCESS.

v2 AFTER t2-t1 x <= a AFTER t2. BEGIN a <= v1. Navabi and McGraw-Hill Inc. • Sequential placement of transaction in a concurrent body of VHDL • Same effect as the above process statement CHAPTER 4 27 © 1999. .Sequential Placement of Transactions ARCHITECTURE concurrent OF sequential_placement IS . END concurrent... Z.

Sequential Placement of Transactions • Projected output waveform • A new transaction will be compared with all existing transactions • It appends. Navabi and McGraw-Hill Inc. Z. or overrides existing ones CHAPTER 4 28 © 1999. .

. Z.Sequential Placement of Transactions • Multiple drivers of a resolved signal • Each driver timing is treated independently CHAPTER 4 29 © 1999. Navabi and McGraw-Hill Inc.

Difference between time of new and existing is greater than the reject value v /=v existing new 5 Append the new transaction Difference between time of new and existing is less than or equal to reject value v /=v existing new 6 Overwrite existing transaction • Effective transactions on the driver of a signal • Multiple transactions are sequentially placed on the signal driver CHAPTER 4 30 © 1999. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions TRANSPORT 1 New Transaction is BEFORE Already Existing Overwrite existing transaction 3 INERTIAL Overwrite existing transaction 2 New Transaction is AFTER Already Existing Append the new transaction. Z. v = v existing new 4 Append the new transaction. .

END sequential. Z. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := ‘Z’. CHAPTER 4 31 © 1999. END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. x <= TRANSPORT ‘0’ AFTER 3 NS. . Navabi and McGraw-Hill Inc. WAIT.

END PROCESS. CHAPTER 4 32 © 1999. WAIT. . x <= TRANSPORT ‘0’ AFTER 8 NS. END sequential. Navabi and McGraw-Hill Inc. x z z 1 0 7 8 9 0 1 2 3 4 5 6 • Appending transactions • Delay type is transport • The new transaction is after the existing one. Z. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’.

WAIT. END sequential. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. Z. END PROCESS. x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions • The new transaction is scheduled before the existing one CHAPTER 4 33 © 1999. Navabi and McGraw-Hill Inc.Sequential Placement of Transactions ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := ‘Z’. . x <= ‘0’ AFTER 3 NS.

Z. Navabi and McGraw-Hill Inc. END sequential. WAIT. x <= ‘0’ AFTER 8 NS. BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS. x z z 0 7 8 9 0 1 2 3 4 5 6 • Saving previous transactions of same value • Transactions with the same value are both kept on the driver of x CHAPTER 4 34 © 1999.Sequential Placement of Transactions ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’. . END PROCESS.

Sequential Placement of Transactions ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=’Z’. x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS. Z. WAIT. Navabi and McGraw-Hill Inc. END PROCESS. x Z z Z 1 0 0 1 2 3 4 5 6 7 8 9 • Appending the new transaction of different value • Time difference of new and existing is greater than reject value CHAPTER 4 35 © 1999. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. . END sequential.

and has a different value CHAPTER 4 36 © 1999. WAIT. END PROCESS. BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS. END sequential x z z 0 7 8 9 0 1 2 3 4 5 6 • Discarding previous transactions of different value • The new transaction is scheduled after the existing.Sequential Placement of Transactions ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=’Z’. . Navabi and McGraw-Hill Inc. x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS. Z.

. reject. '0' AFTER 35 NS. '1' AFTER 33 NS. target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS. Z. target3 : BIT. SIGNAL target1. '1' AFTER 14 NS. END delay. 0 3 5 8 14 18 24 27 29 32 33 35 38 40 • Pulse rejection in inertial. '0' AFTER 08 NS. target3 <= TRANSPORT waveform AFTER 5 NS. '0' AFTER 18 NS.Creating waveform waveform <= '1' AFTER 03 NS.Sequential Placement of Transactions ENTITY example IS END ENTITY.Signal assignments target1 <= waveform AFTER 5 NS. target2. and transport delay mechanisms • This is a result of sequential placement of transactions CHAPTER 4 37 © 1999. -. -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT. '1' AFTER 24 NS. BEGIN -. '0' AFTER 27 NS. Navabi and McGraw-Hill Inc.

0) (1.0) (0.0) (1.3) (1.0) (1.5) (1.5) (1.5) (1.2) (0.5) (1. Z.5) (1.0) (1.5) (0.5) (0.5) (1.5) (0.5) (0.3) (1.3) (0.3) (0.0) (0.5) (0.0) (1.2) target3 © 1999.5) (0.3) (0.5) (1.1) (1.5) (0.2) (0.1) (1.CHAPTER 4 (1.0) (1.2) (0.0) (0.0) (1.5) (0.0) (1.0) (1.3) (0.1) (1.5) (1.5) (0.0) (1.5) (0. 0 3 32 33 35 38 40 .0) (0.2) target1 (1. Navabi and McGraw-Hill Inc.3) (0.5) (0.0) (1. pending.0) (1.5) (1.0) (0.2) target2 Sequential Placement of Transactions • New. and expired transactions on targets of example 38 5 8 13 14 18 19 23 24 27 29 (1.5) (1.5) (0.5) (0.5) (0.0) (1.0) (0.5) (1.0) (0.5) (0.

Sequential Placement of Transactions ENTITY example IS END ENTITY. a AFTER 3 NS. Z. Navabi and McGraw-Hill Inc. -ARCHITECTURE delay OF example IS SIGNAL a. b <= '0'. • Sequential placement of transactions by executing concurrent signal assignments • Events on a cause placement of transactions on b • In a waveform. '0' AFTER 10 NS. b : BIT. '1' AFTER 15 NS. all but the first are TRANSPORT CHAPTER 4 39 © 1999. .Signal assignments a <= '1' AFTER 5 NS. BEGIN -. END delay.

6.2 Simulation 5.3 Byte Comparator 5.6 TOP-DOWN WIRING 5.3.4.2.2 VHDL Description of bit_comparator 5.2 WIRING OF PRIMITIVES 5.CHAPTER 5 STRUCTURAL SPECIFICATION OF HARDWARE 5.2.1 Design of a 4-Bit Comparator 5.2 Byte Latch 5.6 BINDING ALTERNATIVES 5.3.2 NAND Gate Models 5.1 Inverter Model 5.3 WIRING ITERATIVE NETWORKS 5.1 Logic Design of Comparator 5.4 MODELING A TEST BENCH 5.6.1 Sequential Comparator 5.2 VHDL Description of a 4-Bit Comparator 5.6.1 PARTS LIBRARY 5.4.7 SUMMARY CHAPTER 5 1 © 1999.1. Zainalabedin Navabi .1 VHDL Description of A Simple Test Bench 5.1.

CHAPTER 5 2 © 1999. (c) inv i1 o1 (d) • • • • • Inverter Symbol Entity declaration Architecture body Notation. END inv. (b) ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS. o1 : OUT BIT). Zainalabedin Navabi . END single_delay.Parts Library (a) ENTITY inv IS PORT (i1 : IN BIT.

END inv. o1 : OUT BIT ) . interface_signal_declaration interface_signal_declaration port clause • Details of the entity declaration of inverter • Port clause • Interface signal declaration CHAPTER 5 3 © 1999.Parts Library ENTITY inv IS PORT ( entity declaration i1 : IN BIT . Zainalabedin Navabi .

Zainalabedin Navabi .Parts Library entity_name Interface Aspect Input Port Output Port Bidirectional Port Buffer Port • • • • • CHAPTER 5 Elements of aspect notation Input Output Inout Buffer is output that can be used on RHS 4 © 1999.

Outputs. Inputs. Zainalabedin Navabi . Bi-directional ports. Buffers • Inout implies In and Out (two wires) • Buffer can be used inside an architecture CHAPTER 5 5 © 1999.Parts Library • Using ports.

i2 : IN BIT. END single_delay. END nand2. Zainalabedin Navabi . o1 : OUT BIT).Parts Library (a) ENTITY nand2 IS PORT (i1. (b) ARCHITECTURE single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 5 NS. (c) nand2 i1 i2 (d) o1 • Two-input NAND symbol • Entity declaration • Architecture body uses NAND operator CHAPTER 5 6 © 1999.

Zainalabedin Navabi .Parts Library PORT ( i1. o1 : OUT BIT ) identifier_list mode type interface signal declaration port clause interface list interface_signal_declaration • Port clause details for nand2 • Signal declaration includes identifier list • Mode and type are the same as those of the inverter CHAPTER 5 7 © 1999. i2 : IN BIT .

i3 : IN BIT. (c) i1 i2 i3 nand3 o1 • Three-input NAND symbol • Architecture body and notation are shown • Must use AND and NOT CHAPTER 5 8 © 1999. o1 : OUT BIT). END nand3. Zainalabedin Navabi .Parts Library (a) ENTITY nand3 IS PORT (i1. (b) ARCHITECTURE single_delay OF nand3 IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS. END single_delay. i2.

Zainalabedin Navabi .Wiring Components Comparator A B A>B A=B > = < A<B • Logical symbol of a single bit comparator • Cascadable comparator • Will design one bit and cascade CHAPTER 5 9 © 1999.

Zainalabedin Navabi . b = 0 1 1 a=b 1 00 01 11 10 a.Wiring Components a. b < 0 1 1 00 01 1 1 a<b 1 11 10 • Karnaugh maps for the outputs of the single bit comparator • Each output depends on data inputs and its corresponding control input CHAPTER 5 10 © 1999. b > 0 1 1 1 a>b 00 01 11 10 1 1 a.

b’)’)’ a_eq_b = ((a . gt)’. eq)’)’ a_lt_b = ((a’ .(a’ . gt + a . eq)’. b’ . b .( a . lt + a’ . b’ a_eq_b = a .( a’ .(b .( b’ .Wiring Components a_gt_b = a . b)’)’ • Boolean expression for the outputs • Use DeMorgan’s for all-NAND implementation CHAPTER 5 11 © 1999. eq + a’ . gt + b’ . lt)’. Zainalabedin Navabi . lt)’. b . b a_gt_b = ((a . lt + b . b’ . gt)’. eq a_lt_b = a’ .

Zainalabedin Navabi .Wiring Components a gt a_gt_b b a b eq a_eq_b a a_lt_b lt b • Logic diagram of bit_comparator • Using only our primitive components CHAPTER 5 12 © 1999.

previous equal -. a_eq_b.less than (b) • Interface description of bit_comparator • Inputs and outputs of BIT type are declared CHAPTER 5 13 © 1999.equal -.previous less than -.greater -. lt : IN BIT. END bit_comparator. Zainalabedin Navabi . -.Wiring Components bit_comparator a b gt eq lt a_gt_b a_eq_b a_lt_b (a) ENTITY bit_comparator IS PORT (a.previous greater than -.data inputs -. eq. a_lt_b : OUT BIT). b. gt. a_gt_b.

Wiring Components bit_comparator (gate_level) a nand2 i1 i2 o1 im3 nand2 i1 i2 o1 im4 i1 i2 i3 nand3 o1 a_gt_b b inv i1 o1 im2 i1 i2 nand2 o1 im5 gt i1 i2 i3 nand3 o1 nand2 nand3 o1 im7 i1 i2 o1 a_eq_b im6 eq lt i1 i2 i3 nand2 i1 i2 o1 im8 inv i1 o1 im1 i1 i2 nand2 o1 im9 i1 i2 i3 nand3 o1 a_lt_b nand2 i1 i2 o1 im10 • Composition Aspect of bit_comparator. CHAPTER 5 14 © 1999. Zainalabedin Navabi .

im2). i3: IN BIT. FOR ALL : n2 USE ENTITY WORK. g3 : n2 PORT MAP (a. END COMPONENT. eq. eq.a_lt_b output g9 : n2 PORT MAP (im1. im3). lt. g1 : n1 PORT MAP (b. o1: OUT BIT). -. im8). im5. g8 : n2 PORT MAP (im6. im1). Zainalabedin Navabi . g7 : n3 PORT MAP (a. i2: IN BIT. im7. -. im4. END COMPONENT. COMPONENT n2 PORT (i1. g2 : n2 PORT MAP (a. im10 : BIT. im9. im3.a_eq_b output g6 : n3 PORT MAP (im1.inv (single_delay). FOR ALL : n1 USE ENTITY WORK. im4). g5 : n3 PORT MAP (im3. im8. im9. im9). END gate_level. • Architecture body of bit_comparator identified as gate_level • Components instantiations constitute the body • Each instantiation has a label. o1: OUT BIT).Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT.nand3 (single_delay). BEGIN -. im7. o1: OUT BIT). and PORT MAP • Component declarations are local to the architecture CHAPTER 5 15 © 1999. COMPONENT n3 PORT (i1.Intermediate signals SIGNAL im1. g11 : n2 PORT MAP (b. im10). lt. a_gt_b). g4 : n2 PORT MAP (im2.a_gt_b output g0 : n1 PORT MAP (a. b. im2. FOR ALL : n3 USE ENTITY WORK. a_eq_b). i2. im7). im6).im2. component name. im5. im4. im5). END COMPONENT. g12 : n3 PORT MAP (im8. g10 : n2 PORT MAP (im1. b. gt. -. im2.nand2 (single_delay). im10. a_lt_b). im6. gt.

BEGIN ... im8.. .Wiring Components ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n3 PORT (i1. O1: OUT BIT).. i2. im7). component declaration configuration specification architecture declarative part architecture body signal declaration component instantiation statement architecture statement part • Syntax details of the architecture body bit_comparator • Signals in the entity are visible to the architecture of CHAPTER 5 16 © 1999. SIGNAL im1... END COMPONENT.. im10 : BIT. . im7. FOR ALL : n3 USE ENTITY . . Zainalabedin Navabi . im5. eq.. im6. i3: IN BIT. im2. g7 : n3 PORT MAP (a. im3. im4. END gate_level.. b. im9..

Zainalabedin Navabi . im7 ) . instantiation_label component_name component instantiation statement association_list port map aspect • Component instantiation statement syntax details • A label is required • It includes an association list CHAPTER 5 17 © 1999. eq.Wiring Components g7 : n3 PORT MAP ( a. b.

g11 : ENTITY WORK. g12 : ENTITY WORK. im8). im2). gt.nand2(single_delay) PORT MAP (im1.nand2(single_delay) PORT MAP (a. g8 : ENTITY WORK.im2.nand3(single_delay) PORT MAP (im1. im10). im7). a_gt_b). im2. im6). im10. im9. g2 : ENTITY WORK. im3. b. lt.a_lt_b output g9 : ENTITY WORK. eq.inv(single_delay) PORT MAP (a. BEGIN -. im1).nand2(single_delay) PORT MAP (b. g10 : ENTITY WORK. END netlist.nand3(single_delay) PORT MAP (a. im5). im5.nand3(single_delay) PORT MAP (im3.Wiring Components ARCHITECTURE netlist OF bit_comparator IS -. im7. g1 : ENTITY WORK. -. gt. im2. b.nand2(single_delay) PORT MAP (im1. im10 : BIT. a_lt_b). g7 : ENTITY WORK. im4.Intermediate signals SIGNAL im1.a_gt_b output g0 : ENTITY WORK. im7. im9).nand2(single_delay) PORT MAP (im6. im4). im4. Zainalabedin Navabi .a_eq_b output g6 : ENTITY WORK. g4 : ENTITY WORK. -. g3 : ENTITY WORK.inv(single_delay) PORT MAP (b. im8. • Netlist description of bit_comparator • This is direct instantiation • If architecture name is not specified. im9.nand2(single_delay) PORT MAP (im2.nand2(single_delay) PORT MAP (a. the most recently compiled architecture will be used CHAPTER 5 18 © 1999. im5. lt. im3). a_eq_b). eq. im6.nand3(single_delay) PORT MAP (im8. g5 : ENTITY WORK.

Zainalabedin Navabi .Wiring Components • bit_comparator simulation run • keeping control inputs at 010 CHAPTER 5 19 © 1999.

Wiring Iterative Networks 4 Data inputs 4 Four Bit Comparator A B A>B A=B Compare outputs Control inputs > = < A<B • Logical symbol of a 4-bit comparator • Same configuration as that of the one-bit comparator • This is similar to the 74LS85 magnitude comparator CHAPTER 5 20 © 1999. Zainalabedin Navabi .

Wiring Iterative Networks B3 A3 Comparator A B 3 > = < A>B A=B A<B B2 A2 Comparator A B 2 > = < A>B A=B A<B B1 A1 Comparator A B 1 > = < A>B A=B A<B B0 A0 Comparator A B 0 > = < A>B A=B A<B A>B A=B A<B < = > • A 4-bit comparator using four single bit comparators • Numbers different in MSB. produce results faster • Worst case delay for equal inputs CHAPTER 5 21 © 1999. Zainalabedin Navabi .

-.a < b END nibble_comparator.previous less than a_gt_b.previous equal lt : IN BIT.a and b data inputs gt. interface aspect.a > b a_eq_b. -.previous greater than eq.-. Zainalabedin Navabi . -.Wiring Iterative Networks nibble_comparator a(3:0) a_gt_b b(3:0) gt eq lt a_eq_b a_lt_b (a) ENTITY nibble_comparator IS PORT (a. -. • Interface description of nibble_comparator. -.a = b a_lt_b : OUT BIT). b : IN BIT_VECTOR (3 DOWNTO 0). (b) entity declaration • Inputs of of BIT_VECTOR type • Can use any range (a) CHAPTER 5 22 © 1999. -.

Wiring Iterative Networks nibble_comparator(iterative) a(3:0) b(3:0) a(3) b(3) bit_comparator a (gate_level) Bit 3 b gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a(2) b(2) bit_comparator a (gate_level) Bit 2 b gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) bit_comparator a (gate_level) Bit 1 b gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) bit_comparator a (gate_level) Bit 0 b gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect of nibble_comparator CHAPTER 5 23 © 1999. Zainalabedin Navabi .

b(i). lt : IN BIT. im(8). b. c3: comp1 PORT MAP (a(3). a_eq_b. SIGNAL im : BIT_VECTOR ( 0 TO 8). END iterative. im(i*3-3). im(2)). END GENERATE. a_gt_b. b(0). Zainalabedin Navabi . im(7). gt. im(i*3-2). im(i*3+1). • Iterative architecture of nibble_comparator • Uses nested generate statements • Can easily expand by changing numbers CHAPTER 5 24 © 1999. a_lt_b : OUT BIT). BEGIN c0: comp1 PORT MAP (a(0). a_lt_b).bit_comparator (gate_level). lt. gt.Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. im(i*3+0). im(1). eq. im(i*3-1). a_eq_b. eq. im(i*3+2) ). im(6). END COMPONENT. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). b(3). FOR ALL : comp1 USE ENTITY WORK. a_gt_b. im(0).

im(1).Wiring Iterative Networks PORT MAP (a(i). Zainalabedin Navabi . im(i*3+0). im(3). im(i*3-3). im(i*3-2). b(1). im(i*3-1). im(2). im(i*3+1). im(i*3+2) ) i=1 i=1 i=1 i=1 i=1 i=1 i=1 i=1 PORT MAP (a(1). im(4). im(0). im(5) ) • Association list of c instance of comp1 within generate statement • Bit 1 is configured for i value of 1 CHAPTER 5 25 © 1999. b(i).

END GENERATE . b(i). Zainalabedin Navabi . im(i*3-3). im(i*3+0). im(i*3-1). im(i*3+2)). im(i*3-2).Wiring Iterative Networks c1to2 : FOR i IN 1 TO 2 GENERATE c: COMP1 PORT MAP (a(i). im(i*3+1). generate_label generation_scheme generate statement concurrent_statement • • • • Generate statement syntax details This is a concurrent statement The body of a generate statement is concurrent Can use FOR or IF generation scheme CHAPTER 5 26 © 1999.

Wiring Iterative Networks ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a. b(i). a_gt_b. lt. im(2) ). im(i*3-2). m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). a_lt_b). im(i*3+2) ). b(i). SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1). im(i*3-2). eq. im(1). gt. im(i*3+0). BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). CHAPTER 5 27 © 1999. END GENERATE. a_lt_b : OUT BIT). im(i*3-1). END GENERATE. END COMPONENT. b(i). a_gt_b. gt.bit_comparator (gate_level). eq. im(i*3-3). END GENERATE. • A more flexible iterative architecture of nibble_comparator • Constant n sizes the comparator • There is still a better way. a_eq_b. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). END GENERATE. b. use unconstrained arrays. Chap 7. im(i*3-3). END iterative. im(i*3+1). im(i*3-1). CONSTANT n : INTEGER := 4. a_eq_b. lt : IN BIT. Zainalabedin Navabi . FOR ALL : comp1 USE ENTITY WORK. im(0).

Zainalabedin Navabi . b(i). BEGIN least: comp1 PORT MAP (a(i). lt.Wiring Iterative Networks l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK. END GENERATE. im(1). gt. im(2) ). eq. im(0). • Configuration specifications create some ambiguities • Problem is corrected by Generate Statement Declarative Part • Binding indication appears here CHAPTER 5 28 © 1999.bit_comparator (gate_level).

the composition aspect • A test bench does not use ports • All signals used must be explicitly declared CHAPTER 5 29 © 1999.Modeling a Test Bench test_bench (input_output) nibble_comparator (iterative) a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • A test bench for nibble_comparator. Zainalabedin Navabi .

a < b (worst case) "1100" AFTER 2500 NS. best case) a3 : b <= "0000". -. b : IN bit_vector (3 DOWNTO 0). -ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a. -. -. best case) "0000" AFTER 5500 NS.a < b (steady state. BEGIN a1: comp4 PORT MAP (a. SIGNAL eql. a_lt_b : IN BIT. lss). -.a > b (need bit 1 info) "1010" AFTER 3500 NS. -. -.a = b (worst case) "0000" AFTER 6000 NS. SIGNAL a. ---.a < b (need bit 2 info) "1111" AFTER 4000 NS. a_gt_b. gtr : BIT. b. a2: a <= "0000".nibble_comparator(iterative).Modeling a Test Bench ENTITY nibble_comparator_test_bench IS END nibble_comparator_test_bench . gnd. -. a_gt_b_out. -. a_eq_b_out. a_lt_b_out : OUT BIT). eql. -. lss. -.a < b (worst case) "1110" AFTER 2500 NS.a > b (need bit 3 only. prepare for next) "1111" AFTER 4500 NS.a = b (worst case) "1111" AFTER 6000 NS. gnd. prepare for next) "1111" AFTER 4500 NS. -. FOR a1 : comp4 USE ENTITY WORK. CHAPTER 5 30 iterative architecture of © 1999. END COMPONENT. gtr.a = b (worst case) "1111" AFTER 5000 NS.a = b (steady state) "1111" AFTER 0500 NS.a = b (worst case) "0000" AFTER 5000 NS.a < b (steady state. a_eq_b. -. • Test bench for nibble_comparator.a = b (steady state) "1110" AFTER 0500 NS. -.a > b (need bit 1 info) "1100" AFTER 3500 NS. -. best case) "0000" AFTER 5500 NS. best case) END input_output. -.a < b (need bit 3 only. SIGNAL vdd : BIT := '1'. ---.a > b (worst case) "1110" AFTER 1500 NS. SIGNAL gnd : BIT := '0'.a < b (need bit 3 only.a > b (need bit 3 only. -. -. b : BIT_VECTOR (3 DOWNTO 0). Zainalabedin Navabi .a > b (worst case) "1111" AFTER 1500 NS.a < b (need bit 2 info) "0000" AFTER 4000 NS. vdd. -.

..... ... '1' .. . "0000" . '0' lss '0' . .. . ....... .... '1' ............ .... .. .. '1' .................... .... SIGNALS b(3:0) gtr "0000" .. ............... .... "1100" ................ . "0000" "1111" . • Simulation report for simulating iterative comparator test bench • All events are observed CHAPTER 5 31 © 1999......... . ...... ..... ... .... ..... ... ......... "0000" .. ..... . . ... .. . ...... eql '0' '1' ..... .... . '0' .. .................... .. . ................ ...... . .. "1111" ...... '0' . "1110" ... . ... . .......... .. . .... '1' .... ......... ..... '0' .. ..... "1110" ... '0' . .. ........ '1' .. ... ... "1111" . "1111" ... .... . . ... .. . ................. . ..... . Zainalabedin Navabi .Modeling a Test Bench TIME (NS) 0 5 500 544 548 1500 1544 1548 2500 2533 2537 3500 3522 3526 4000 4500 4544 4548 5000 5011 5015 5500 5544 5548 6000 6011 6015 a(3:0) "0000" ......... '0' .... '0' . '0' .. "1111" ... "1010" ... .. .. '1' .. '1' ..... . . '0' ............... .. '1' . ........ ...... ..

Zainalabedin Navabi CHAPTER 5 .Binding Alternatives C S 1 3 Q R 2 4 • • • • Logical diagram of a simple latch With equal timing this will not work Will use this example for showing binding alternatives Correct the oscillation problem by binding to NAND gates of different delay values 32 © 1999.

• • • • VHDL description of set-reset latch This is using the 2-input NAND for all four instances Signal assignment avoids use of Buffer The single_delay architecture is used CHAPTER 5 33 © 1999. im3.nand2 (single_delay). g3 : n2 PORT MAP (im1. o1: OUT BIT). Zainalabedin Navabi . q <= im3. q : OUT BIT). r. c. im1).Binding Alternatives ENTITY sr_latch IS PORT (s. im2. g4 : n2 PORT MAP (im3. im4 : BIT. BEGIN g1 : n2 PORT MAP (s. im3). END COMPONENT. i2: IN BIT. g2 : n2 PORT MAP (r. c : IN BIT. c. im2). END sr_latch. FOR ALL : n2 USE ENTITY WORK. im2. SIGNAL im1. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im4). im4. END gate_level.

SIGNAL im1. im2. g3 : n2 PORT MAP (im1.nand2 (single_delay). im4). i2: IN BIT. FOR ALL : n2 USE ENTITY WORK. Zainalabedin Navabi . q). o1: BUFFER BIT). g4 : n2 PORT MAP (q. im2). c. END gate_level.Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im1). g2 : n2 PORT MAP (r. • sr_latch (gate_level) architecture using BUFFER • componet declaration and the actual entity must match is PORT MAP is not used with the configuration specification • The 2-input NAND must change to use BUFFER instead of OUT CHAPTER 5 34 © 1999. im4. im2. im4 : BIT. c. BEGIN g1 : n2 PORT MAP (s. END COMPONENT.

• • • • A faster NAND gate The gate delay is 3 NS Uses the same entity as the single_delay NAND Using this NAND corrects the oscillation problem CHAPTER 5 35 © 1999. Zainalabedin Navabi . END fast_single_delay.Binding Alternatives ARCHITECTURE fast_single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 3 NS.

Binding Alternatives c s i1 i2 (fast_single_delay) sr_latch (gate_level) nand2 g1: im1 (fast_single_delay) nand2 g3: o1 i1 i2 o1 im3 q r i1 i2 (single_delay) nand2 g2: o1 im2 i1 i2 (single_delay) nand2 g4: o1 im4 (a) • SR-latch. composition aspect • Same wiring as the latch that oscillates CHAPTER 5 36 © 1999. using gates with different delays. Zainalabedin Navabi .

SIGNAL im1. i2: IN BIT. im4 : BIT. im3). o1: OUT BIT). im3. q <= im3. g4 : n2 USE ENTITY WORK. im4).Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. im1). using gates with different delays.nand2 (single_delay). different binding • Fast_single_delay architecture is used for g1 and g3 CHAPTER 5 37 © 1999.nand2 (fast_single_delay). im2. Zainalabedin Navabi . im2. g3 : n2 PORT MAP (im1. architecture body • Same wiring. g3 : n2 USE ENTITY WORK. • SR-latch. im2). c. BEGIN g1 : n2 PORT MAP (s. END COMPONENT. g2 : n2 PORT MAP (r. im4. FOR g2. c. END gate_level. g4 : n2 PORT MAP (im3. FOR g1.

composition aspect • This solution uses 3-input NAND gates • The 3-input gates have different delay values than the 2-input NAND gates CHAPTER 5 38 © 1999.Binding Alternatives c s i1 i2 (single_delay) sr_latch (gate_level) nand2 g1: im1 nand2 g3: q o1 i1 i2 (single_delay) o1 im3 r i1 i2 i3 nand3 (single_delay) o1 g2: im2 i1 i2 i3 (single_delay) nand3 im4 o1 g4: (a) • SR-latch. Zainalabedin Navabi . using nand2 and nand3 gates.

im2. im3). y. z). im4. Zainalabedin Navabi . • SR-latch.nand2 (single_delay) PORT MAP (x. im2.nand2 (single_delay) PORT MAP (x. FOR g2. BEGIN g1 : n2 PORT MAP (s. z). im4). c. im2). END gate_level. x. z: OUT BIT).nand3 (single_delay) PORT MAP (x. z).Binding Alternatives ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x. y. z). im1). x. y. q <= im3. g4 : n2 PORT MAP (im3. g4 : n2 USE ENTITY WORK. FOR OTHERS : n2 USE ENTITY WORK. using nand2 and nand3 gates. im3. SIGNAL im1. y: IN BIT. g3 : n2 USE ENTITY WORK. g3 : n2 USE ENTITY WORK. overrides the default • Could use OTHERS CHAPTER 5 39 © 1999. g2 : n2 PORT MAP (r. END COMPONENT. g3 : n2 PORT MAP (im1. y. ALTERNATIVELY: FOR g1. c. im4 : BIT. architecture • Configuration specification takes caring of wiring the 3-input NAND into a 2-input NAND • PORT MAP in binding.nand3 (single_delay) PORT MAP (x. FOR g1.

Binding Alternatives Signals of gate_level of sr_latch r c im2 Port map association of instantiation statement Local ports of g2 instance of n2 x y z Port map association of configuration specification Formal ports of nand3 in1 in2 in3 o1 • Two-step association • Declaration is local • Names in declaration are used only when not specified in a configuration specification CHAPTER 5 40 © 1999. Zainalabedin Navabi .

instantiation_list component_name component specification entity aspect binding indication port map aspect configuration specification • Configuration specification syntax details • Binding indication contains entity aspect. y.Binding Alternatives FOR g1. and generic map aspect • If not specified. those of the declaration will be used • Declarations are still needed unless direct instantiations are used CHAPTER 5 41 © 1999. g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x. Zainalabedin Navabi . port map aspect. z) .

Top-Down Wiring

old_new_comparator byte_comparator i di byte_latch con1 clk clk a b gt eq lt a_gt_b a_eq_b a_lt_b

• Will develop a complete example, compare old and new data, keep a count • Defaults will be used • Most recently compiled architectures are used in the absence of configuration specifications • Composition aspect of old_new_comparator
CHAPTER 5 42 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT); END old_new_comparator; -ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparator PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN); END wiring;

• • • • •
CHAPTER 5

old_new_comparator VHDL description Declarations are present Configuration specifications are missing Use OPEN for unconnected outputs OPEN inputs must have a default value
43 © 1999, Zainalabedin Navabi

Top-Down Wiring

ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0)); END byte_latch; -ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE; END iterative;

• • • •

An 8-bit latch is required for this design Use a configurable description based on D-type latch VHDL description of byte_latch. Iterative architecture is used

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© 1999, Zainalabedin Navabi

Top-Down Wiring

c d inv i1 o1

sr_latch C S q q

R

(a)

• Build a D-latch using our sr_latch and an inverter • Composition aspect is shown

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Top-Down Wiring

ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT; BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar); END sr_based; (b)

• Design of d_latch, VHDL description • Configuration specifications are not used • Local declarations are used for ports and name of the actual entity

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Top-Down Wiring

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );

END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;

• Another necessary component for this design is an 8bit comparator • Byte comparator VHDL description • Uses 8 instances of bit_comparator • Constant n is changed to 8 • Default architectures are used
CHAPTER 5 47 © 1999, Zainalabedin Navabi

Top-Down Wiring
A structural description for a design consists of a wiring specification of its subcomponents. In this chapter, the

definition and usage of components in larger designs was illustrated. Generate statements also were introduced as a convenient way to describe repetitive hardware structures and a notation was defined for graphical representation of structural descriptions. In addition, various forms and

options in component declarations and configuration specifications were discussed. The last part of this chapter presented a top-down design using basic gates and components presented in the earlier sections. Using simple gates, the reader should now be able to design larger digital circuits with many levels of component nesting.

• End Of Chapter 5

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CHAPTER 6 DESIGN ORGANIZATION AND PARAMETERIZATION

6.1 DEFINITION AND USAGE OF SUBPROGRAMS 6.1.1 A Functional Single Bit Comparator 6.1.2 Using Procedures in a Test Bench 6.1.3 Language Aspects of Subprograms 6.1.4 Utility Procedures 6.2 PACKAGING PARTS AND UTILITIES 6.2.1 Packaging Components 6.2.2 Packaging Subprograms 6.3 DESIGN PARAMETRIZATION 6.3.1 Using Default Values 6.3.2 Using Fixed Values 6.3.3 Passing Generic Parameters 6.4 DESIGN CONFIGURATION 6.4.1 A General Purpose Test Bench 6.4.2 Configuring Nested Components 6.4.3 Incremental Binding 6.4.4 An n-bit Register Example 6.4.5 Iterative Parity Checking 6.5 DESIGN LIBRARIES 6.5.1 Existing Libraries 6.5.2 Library Management 6.6 SUMMARY

CHAPTER 6

1

© 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

GT Equation EQ Equation LT Equation

a_gt_b = a . gt + b' . gt + a . b' a_eq_b = a . b . eq + a' . b' . eq a_lt_b = b . lt + a' . lt + b . a'

ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;

An architecture for demonstrating use of subprograms

• Demonstrating the use of functions • Use functions in place of Bololean expresssions • A functional bit_comparator, using the same function for two outputs
CHAPTER 6 2 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

FUNCTION fgl ( w, x, g1 :BIT) RETURN BIT IS BEGIN RETURN (w AND g1) OR (NOT x AND g1) OR (w AND NOT x) ; END;

designator formal_parameter_list type_mark subprogram body expression return statement sequential statement subprogram statement part subprogram specification

• Function body is sequential • Use functions for utilities and coding style • Syntax details of a subprogram body, a general view
CHAPTER 6 3 © 1999, Zainalabedin Navabi

Definition and Usage of Subprograms

ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END structural;

• Using the functional bit_comparator • Structural architecture of a nibble_comparator

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© 1999, Zainalabedin Navabi

END COMPONENT. b : IN bit_vector (3 DOWNTO 0). WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'. COMPONENT comp4 PORT (a. 00&15&15&14&14&14&14&10&00&15&00&00&15. VARIABLE tmp. END apply_data. a_eq_b. SIGNAL a. SIGNAL eql. b : BIT_VECTOR (3 DOWNTO 0). 500 NS). gt. SIGNAL vdd : BIT := '1'. eql. CONSTANT period : IN TIME) IS VARIABLE j : INTEGER. • Defining and using a procedure • Procedural architecture of nibble_comparator • INTEGERS type is an array of 13 integers CHAPTER 6 5 © 1999. pos : INTEGER := 0. BEGIN a1: comp4 PORT MAP (a. vdd. CONSTANT values : IN integers. END LOOP.nibble_comparator(structural). lss. SIGNAL gnd : BIT := '0'. lss). apply_data (a. a_lt_b : OUT BIT). PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). gnd. gtr : BIT. eq. FOR a1 : comp4 USE ENTITY WORK.Definition and Usage of Subprograms ARCHITECTURE procedural OF nibble_comparator_test_bench IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). END LOOP. target <= TRANSPORT buf AFTER i * period. j := j + 1. END IF. gtr. ELSE buf (j) := '0'. a_gt_b. b. 00&14&14&15&15&12&12&12&15&15&15&00&00. gnd. j := 0. lt : IN BIT. apply_data (b. Zainalabedin Navabi . 500 NS). END procedural. tmp := tmp / 2. BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i).

...... '0' . '0' .. .. "1111" . . ..... "0000" "1111" ....... .... ..... '1' eql '0' '1' .. . . '1' . . . . '1' ... '0' ........ "1111" ...... . .... "0000" .............. '1' ....... ..... '0' .. "1110" .............. "1010" ...... "1111" ..... ...... ......... "0000" ....... ....... ...... '1' ... . . '1' ... "1110" . "1100" . '1' .... ..... ......... ... .... Zainalabedin Navabi ............... • Simulation report resulting from the procedural test bench • All events are observed • Shows increments of 12 NS only CHAPTER 6 6 © 1999.. . '0' ... ........ '0' . '0' ...... '0' ..... ... .. . . ..Definition and Usage of Subprograms TIME (NS) 0 48 500 548 1500 1548 2500 2536 3500 3524 4000 4500 4548 5000 5012 5500 5548 6000 6012 a(3:0) "0000" . '0' lss '0' . "1111" ..... ....... '1' .... SIGNALS b(3:0) gtr "0000" ..

END apply_data. CONSTANT values : IN integers. END LOOP. . CONSTANT period : IN TIME ) IS VARIABLE j : INTEGER. VARIABLE buf: BIT_VECTOR (3 DOWNTO 0). FOR i IN 0 TO 12 LOOP . subprogram specification formal parameter list subprogram declarative part subprogram body loop statement sequential statement subprogram statement part • • • • CHAPTER 6 Details of a subprogram body Function or procedure subprogram specification Subprograms are procedural bodies Nested procedural statements 7 © 1999. Zainalabedin Navabi . BEGIN.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). VARIABLE tmp : INTEGER := 0. .

. END LOOP. loop parameter specification iteration scheme loop_statement sequence_of_statement • • • • CHAPTER 6 Loops are procedural Loop statement with FOR iteration scheme Can nest procedural statements Sequence_of_statements is the sequential construct 8 © 1999. Zainalabedin Navabi .Definition and Usage of Subprograms FOR i IN 0 TO 12 LOOP . .

Definition and Usage of Subprograms IF (tmp MOD 2 = 1) THEN buf (j) := ’1’. Zainalabedin Navabi . ELSE buf (j) := ‘0’. END IF. condition if_statement sequence_of_statements sequence_of_statements • Details of the If statement of apply_data procedure • This is a procedural statement • Sequence_of_statements is the sequential construct CHAPTER 6 9 © 1999.

• Can do utility procedures • ‘RANGE attribute makes this a generic procedure • Procedure for binary to integer conversion CHAPTER 6 10 © 1999. BEGIN result := 0. END LOOP. Zainalabedin Navabi .Definition and Usage of Subprograms PROCEDURE bin2int (bin : IN BIT_VECTOR. END bin2int. int : OUT INTEGER) IS VARIABLE result: INTEGER. END IF. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. int := result.

1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. END LOOP.Definition and Usage of Subprograms PROCEDURE int2bin (int : IN INTEGER. • Another utility procedure • Procedure for integer to binary conversion • ‘LENGTH attribute is used here CHAPTER 6 11 © 1999. Zainalabedin Navabi . END IF. bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. ELSE bin (i) := '0'. FOR i IN 0 TO (bin'LENGTH . END int2bin. BEGIN tmp := int. tmp := tmp / 2.

• • • • CHAPTER 6 Can use procedures within procedure Another version of apply_data procedure This version takes advantage of the int2bin procedure TRASPORT delay schedules all transactions at time 0 12 © 1999. Zainalabedin Navabi . END apply_data. BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). target <= TRANSPORT buf AFTER i * period. buf). CONSTANT values : IN integers.Definition and Usage of Subprograms PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). END LOOP.

Zainalabedin Navabi . END to_integer.Definition and Usage of Subprograms FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. END IF. • Functions can serve as utilities • Binary to integer conversion function • Assumes lower bound of 0. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. BEGIN result := 0. RETURN result. otherwise it is a generic function CHAPTER 6 13 © 1999. END LOOP.

i3: IN BIT. Demonstrating specification and usage of packages • Component declarations as well as utilities can be packaged • A package declaration containing component declarations of simple gates • Eliminates the need for individual declarations CHAPTER 6 14 © 1999. i2.Packaging components PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT. COMPONENT n2 PORT (i1: i2: IN BIT. END simple_gates. END COMPONENT. o1: OUT BIT). o1: OUT BIT). END COMPONENT.Packaging Parts and Utilities -. COMPONENT n3 PORT (i1. o1: OUT BIT). END COMPONENT. Zainalabedin Navabi .

END gate_level. im7). im8. im9). gt. -. im4). eq. • Using package of simple gates in gate_level of bit_comparator • This becomes our local declarations • Same naming rules as before. im8). g12 : n3 PORT MAP (im8.nand2 (single_delay). g10 : n2 PORT MAP (im1. im5). Zainalabedin Navabi .a_gt_b output g0 : n1 PORT MAP (a. im6.a_eq_b output g6 : n3 PORT MAP (im1. -. g5 : n3 PORT MAP (im3. im6). a_gt_b). im7.nand3 (single_delay). lt. im5. -. im9. g1 : n1 PORT MAP (b. im1). b. eq. im2). BEGIN -. im10 : BIT. FOR ALL : n3 USE ENTITY WORK.inv (single_delay). im7. ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK.simple_gates. b. gt. same configuration CHAPTER 6 15 © 1999. im5. im10.a_lt_b output g9 : n2 PORT MAP (im1. im9. im4.Packaging Parts and Utilities USE WORK. im2.im2. g11 : n2 PORT MAP (b. g7 : n3 PORT MAP (a. im3).ALL. im2. g3 : n2 PORT MAP (a. g4 : n2 PORT MAP (im2. FOR ALL : n2 USE ENTITY WORK. lt. g2 : n2 PORT MAP (a. a_eq_b). im10). a_lt_b). im3. im4.Intermediate signals SIGNAL im1. g8 : n2 PORT MAP (im6.

WORK.n1.simple_gates. -. . n2 and n3 component declarations are visible .n2.n1. WORK.simple_gates.n3.Packaging Parts and Utilities USE WORK. Zainalabedin Navabi . • An alternative application of the use clause • Can select only those needed CHAPTER 6 16 © 1999.simple_gates.

CONSTANT values : IN integers.Packaging Parts and Utilities PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER. END basic_utilities. x. • The basic_utilities package declaration • Packaging subprograms replaces their declaration • Types and declarations become visible to architectures CHAPTER 6 17 © 1999. eq : BIT) RETURN BIT. PROCEDURE int2bin (int : IN INTEGER. gl : BIT) RETURN BIT. PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). PROCEDURE bin2int (bin : IN BIT_VECTOR. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER. FUNCTION fgl (w. x. bin : OUT BIT_VECTOR). CONSTANT period : IN TIME). FUNCTION feq (w. Zainalabedin Navabi . int : OUT INTEGER).

Packaging Parts and Utilities PACKAGE BODY basic_utilities IS FUNCTION fgl (w. END LOOP. FOR i IN 0 TO (bin'LENGTH . • Package body includes body of procedures • The basic_utilities package body • Will use this package in all our examples CHAPTER 6 18 © 1999. gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x). x. BEGIN tmp := int. BEGIN result := 0. END feq. tmp := tmp / 2. END IF. END fgl. PROCEDURE bin2int (bin : IN BIT_VECTOR. ELSE bin (i) := '0'. x. END LOOP. Zainalabedin Navabi .1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'. bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER. FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i. END int2bin. int : OUT INTEGER) IS VARIABLE result: INTEGER. eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq). VARIABLE buf : BIT_VECTOR (bin'RANGE). PROCEDURE int2bin (int : IN INTEGER. END bin2int. int := result. END IF. FUNCTION feq (w.

Zainalabedin Navabi . BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i). END apply_data. RETURN result. END LOOP. END basic_utilities. FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER. END to_integer. target <= TRANSPORT buf AFTER i * period. BEGIN result := 0.Packaging Parts and Utilities PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0). END IF. buf). CONSTANT values : IN integers. • Continuation of the basic_utilities package body • New declarations in this body are visible to this body only CHAPTER 6 19 © 1999. END LOOP. CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0). FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i.

ARCHITECTURE functional OF bit_comparator IS BEGIN a_gt_b <= fgl (a. b. a_eq_b <= feq (a. gt) AFTER 12 NS. END functional. • Using functions of the basic_utilities package • Architecture need not include function body • The USE statement handles visibility © 1999. Zainalabedin Navabi CHAPTER 6 20 .Packaging Parts and Utilities USE WORK.basic_utilities.ALL. lt) AFTER 12 NS. a. eq) AFTER 12 NS. a_lt_b <= fgl (b. b.

12. END COMPONENT. END procedural. a_eq_b.15. • • • • CHAPTER 6 Using procedures of the basic_utilities package Concatenate to form 13 integers Can also use aggregate operation Aggregate for elements of the array only 21 © 1999.14.15.14.basic_utilities. 0&14&14&15&15&12&12&12&15&15&15&00&00. 0&15&15&14&14&14&14&10&00&15&00&00&15.12. 500 NS). SIGNAL a. eql.00).14. apply_data (b. gnd. 500 NS).15. ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a.12.15.00. gnd. lt : IN BIT. 500 NS).ALL. ALTERNATIVELY: apply_data (a. Zainalabedin Navabi .15. lss. SIGNAL vdd : BIT := '1'. FOR a1 : comp4 USE ENTITY WORK. gtr. gtr : BIT.00. (00. eq.00.15). a_gt_b.15. b. vdd.14.14.nibble_comparator(structural). SIGNAL gnd : BIT := '0'. apply_data (a.15. SIGNAL eql.00. lss).15. b : IN bit_vector (3 DOWNTO 0). a_lt_b : OUT BIT). BEGIN a1: comp4 PORT MAP (a. apply_data (b.14. gt.10.Packaging Parts and Utilities USE WORK. 500 NS). (00. b : BIT_VECTOR (3 DOWNTO 0).

Zainalabedin Navabi .Design Parametrization ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. END inv_t. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. PORT (i1 : IN BIT. END average_delay. o1 : OUT BIT). Architecture for demonstrating specification and definition of parameters • Start design parameterization examples with same simple structures CHAPTER 6 22 © 1999. tphl : TIME := 3 NS).

o1 : OUT BIT). tphl : TIME := 5 NS). -ARCHITECTURE average_delay OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. declares objects of type constant © 1999. END average_delay. END nand3_t. i2 : IN BIT. -ARCHITECTURE average_delay OF nand3_t IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2. o1 : OUT BIT). END nand2_t. PORT (i1. PORT (i1. tphl : TIME := 4 NS). Zainalabedin Navabi CHAPTER 6 23 . ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS. i2.Design Parametrization ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS. • Parametrized gate models • GENERIC is used. END average_delay. i3 : IN BIT.

tphl : TIME := 3 NS ).Design Parametrization ENTITY inv_t IS GENERIC ( tplh : TIME := 5 NS . Zainalabedin Navabi . o1 : OUT BIT). interface constant declaration entity declaration interface constant declaration (generic) interface list (formal) generic clause entity header (formal) port clause • Details of the entity declaration of inverter with generics • Using a default value is helpful but not required • Generic clause comes before port clause CHAPTER 6 24 © 1999. END inv_t. PORT (i1 : IN BIT.

nand2_t. and nand3_t • Graphical representation with generics • Port association and generic association must be done when used CHAPTER 6 25 © 1999. Zainalabedin Navabi .Design Parametrization inv_t i1 tplh o1 tphl nand2_t i1 o1 i2 tphl tplh i1 nand3_t o1 i2 i3tplh tphl • Interface aspects of inv_t.

COMPONENT n3 PORT (i1. END COMPONENT.inv_t (average_delay). b. im3. FOR ALL : n3 USE ENTITY WORK. im9. g10 : n2 PORT MAP (im1. im4.a_lt_b output g9 : n2 PORT MAP (im1. im4. im2). im4). im6. FOR ALL : n2 USE ENTITY WORK. im8.nand2_t (average_delay). g1 : n1 PORT MAP (b. im3). Zainalabedin Navabi CHAPTER 6 26 . lt. g8 : n2 PORT MAP (im6. END COMPONENT. eq.Design Parametrization ARCHITECTURE default_delay OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT. lt.nand3_t (average_delay). im7. im9. g11 : n2 PORT MAP (b. im5.a_eq_b output g6 : n3 PORT MAP (im1. END default_delay. END COMPONENT. o1: OUT BIT). -.Intermediate signals SIGNAL im1. im2. im2. BEGIN -. o1: OUT BIT). g7 : n3 PORT MAP (a. g2 : n2 PORT MAP (a.im2. • Many alternatives for specifying generics • Using default values for the generics of logic gates • No need to declare and specify generics if they are to use default values © 1999. im8). im7. b. gt. im7). im10). im9). im10. o1: OUT BIT). COMPONENT n2 PORT (i1. g12 : n3 PORT MAP (im8. gt. -. a_eq_b).a_gt_b output g0 : n1 PORT MAP (a. im6). g4 : n2 PORT MAP (im2. i2. a_gt_b). im10 : BIT. im5. a_lt_b). g3 : n2 PORT MAP (a. i3: IN BIT. -. im5). im1). eq. g5 : n3 PORT MAP (im3. FOR ALL : n1 USE ENTITY WORK. i2: IN BIT.

END fixed_delay. lt. 5 NS) PORT MAP (im1. gt. END COMPONENT. Zainalabedin Navabi . im2. im1). FOR ALL : n2 USE ENTITY WORK.a_gt_b output g0 : n1 GENERIC MAP (2 NS. g12 : n3 GENERIC MAP (4 NS. 5 NS) PORT MAP (im6. 5 NS) PORT MAP (im2. im7. tphl : TIME). lt. a_lt_b).Design Parametrization ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh. im3. 5 NS) PORT MAP (b. im2). eq. • If generics are declared without default values. they have to be specified • Associating fixed values with the generics of logic gates • Generic map is shown here CHAPTER 6 27 © 1999. 6 NS) PORT MAP (a.nand2_t (average_delay). END COMPONENT. 4 NS) PORT MAP (b. g10 : n2 GENERIC MAP (3 NS. -. 5 NS) PORT MAP (im1. g8 : n2 GENERIC MAP (3 NS. 5 NS) PORT MAP (a. gt. i3: IN BIT. tphl : TIME). g3 : n2 GENERIC MAP (3 NS. im10). im5. im8. g2 : n2 GENERIC MAP (3 NS. g11 : n2 GENERIC MAP (3 NS. im9). im5). eq. im2. im4. im10. PORT (i1. im7. FOR ALL : n1 USE ENTITY WORK. PORT (i1: IN BIT. g5 : n3 GENERIC MAP (4 NS. im9.a_lt_b output g9 : n2 GENERIC MAP (3 NS. g1 : n1 GENERIC MAP (2 NS. -. im10 : BIT. im9.im2. im5. 6 NS) PORT MAP (im3. 4 NS) PORT MAP (a. END COMPONENT. a_gt_b). im6.nand3_t (average_delay). tphl : TIME). im7). 6 NS) PORT MAP (im1. COMPONENT n2 GENERIC (tplh. im6). g7 : n3 GENERIC MAP (4 NS. o1: OUT BIT). BEGIN -. 6 NS) PORT MAP (im8. FOR ALL : n3 USE ENTITY WORK. im8). COMPONENT n3 GENERIC (tplh. a_eq_b). 5 NS) PORT MAP (a. o1: OUT BIT). o1: OUT BIT). i2. b. im4. im3). PORT (i1. b.inv_t (average_delay). g4 : n2 GENERIC MAP (3 NS.a_eq_b output g6 : n3 GENERIC MAP (4 NS. i2: IN BIT. SIGNAL im1. im4).

4 NS ) PORT MAP ( b. Zainalabedin Navabi .Design Parametrization g1 : n1 GENERIC MAP ( 2 NS. im2 ) . instantiation_label component_name generic map aspect port map aspect association_list component instantiation statement association_list • Syntax details • Component instantiation statement with generic map aspect • Generic map aspect comes first CHAPTER 6 28 © 1999.

-. -. im4.previous greater than eq. FOR ALL : n1 USE ENTITY WORK. b. tphl : TIME). im9.previous less than a_gt_b.inv_t (average_delay). Zainalabedin Navabi . im8.. COMPONENT n2 GENERIC (tplh. BEGIN . END COMPONENT. tphl1. tphl : TIME). tphl2. (a) ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh. END COMPONENT. -. o1: OUT BIT). i2: IN BIT. tplh3.nand3_t (average_delay). PORT (a.equal a_lt_b : OUT BIT).previous equal lt : IN BIT. -. END COMPONENT. -. -. im3. tphl3 : TIME). FOR ALL : n3 USE ENTITY WORK. im7.data inputs gt. tplh2. -. PORT (i1: IN BIT. i3: IN BIT.Intermediate signals SIGNAL im1. im10 : BIT. i2. FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay). o1: OUT BIT). -.greater a_eq_b. tphl : TIME). • A bit comparator with timing parameters • Passing generics of bit comparator to its components • Bit comparator has generic parameters that must be passed to it CHAPTER 6 29 © 1999. im6. o1: OUT BIT). PORT (i1. im5. COMPONENT n3 GENERIC (tplh.Design Parametrization ENTITY bit_comparator_t IS GENERIC (tplh1.im2.less than END bit_comparator_t.. PORT (i1.

tphl2) PORT MAP (im1. Zainalabedin Navabi . b. a_eq_b). g4 : n2 GENERIC MAP (tplh2. g12 : n3 GENERIC MAP (tplh3. im3). im5). im4). im7. im2. a_gt_b). tphl3) PORT MAP (a. g11 : n2 GENERIC MAP (tplh2. im10). eq. tphl2) PORT MAP (a. b. im8). g2 : n2 GENERIC MAP (tplh2. g5 : n3 GENERIC MAP (tplh3. lt. im10.a_gt_b output g0 : n1 GENERIC MAP (tplh1. im2.a_lt_b output g9 : n2 GENERIC MAP (tplh2. tphl2) PORT MAP (b. im7). tphl2) PORT MAP (im2. g10 : n2 GENERIC MAP (tplh2.. g8 : n2 GENERIC MAP (tplh2. • A bit comparator with timing parameters • Gates require generic specification • These override the gate generics CHAPTER 6 30 © 1999. im5. im2). tphl2) PORT MAP (a. im4. -. im9.a_eq_b output g6 : n3 GENERIC MAP (tplh3. g1 : n1 GENERIC MAP (tplh1. im6). gt. im9). g7 : n3 GENERIC MAP (tplh3. -.Design Parametrization . tphl2) PORT MAP (im1. tphl3) PORT MAP (im1. lt. tphl1) PORT MAP (b. g3 : n2 GENERIC MAP (tplh2. tphl1) PORT MAP (a. eq. tphl3) PORT MAP (im3. tphl3) PORT MAP (im8. gt. im1). -. tphl2) PORT MAP (im6.. END passed_delay. a_lt_b).

Zainalabedin Navabi .Design Parametrization bit_comparator_t (passed_delay) a nand2_t i1 (average_delay) o1 i2 im3 tplh tphl nand2_t i1 i2 (average_delay) o1 im4 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_gt_b b inv_t im2 i1 (average_delay)o1 nand2_t i1 i2 (average_delay) tplh tphl o1 tplh tphl im5 gt nand3_t i1 (average_delay) o1 i2 i3 tplh tphl nand3_t i1 (average_delay) i2 o1 i3tplh tphl im6 nand2_t i1 i2 im7 (average_delay) eq lt o1 a_eq_b tplh tphl nand2_t i1 i2 inv_t i1 (average_delay)o1 (average_delay) im8 o1 tplh tphl nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_lt_b im1 i1 i2 nand2_t (average_delay) tplh tphl o1 im9 tplh tphl nand2_t i1 i2 (average_delay) o1 tplh tplh2 tphl im10 tplh1 tphl1 tphl2 tplh3 tphl3 • Composition aspect of bit_comparator_t • Dotted lines with arrows indicate generics CHAPTER 6 31 © 1999.

c3: comp1 PORT MAP (a(3). FOR ALL : comp1 USE ENTITY WORK. a_lt_b). im(i*3-3). tplh3 : TIME := 6 ns. im(i*3+0).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 GENERIC ( tplh1 : TIME := 2 NS. tplh2 :TIME := 3 NS. im(i*3-2). gt. END COMPONENT.bit_comparator_t (passed_delay). Zainalabedin Navabi . • Comp1 is declared with default values • Passing default values of local generics to the generics of bit_comparator_t • These values override at the lower levels CHAPTER 6 32 © 1999. tplh3 : TIME := 4 ns. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). END iterative. im(i*3-1). END GENERATE. b(3). b(0). im(7). a_eq_b. im(i*3+2) ). a_gt_b. im(8). b. im(i*3+1). im(0). tplh2 :TIME := 5 NS. eq. eq. im(6). tplh1 : TIME := 4 NS. im(2)). a_lt_b : OUT BIT). a_eq_b. BEGIN c0: comp1 PORT MAP (a(0). lt. lt : IN BIT. PORT (a. im(1). b(i). a_gt_b. SIGNAL im : BIT_VECTOR ( 0 TO 8). gt.

eq.. correspond in the order they are listed CHAPTER 6 33 © 1999. im(1). 8 NS. and using defaults for others • Association by position.. END iterative. . 10 NS) PORT MAP (a(0). Zainalabedin Navabi .Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS .. OPEN. im(2)).. b(0). gt. OPEN. OPEN. • Some are associated with OPEN • Associating constants with some of generics of bit_comparator_t. im(0). BEGIN c0: comp1 GENERIC MAP (OPEN. lt.

eq => eq. • • • • • CHAPTER 6 Using named association. END iterative.. b(0). ARCHITECTURE BECOMES: ARCHITECTURE iterative OF nibble_comparator IS . BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS. im(1). a_gt_b => im(0). lt : IN BIT. a_lt_b : OUT BIT).Design Parametrization ARCHITECTURE iterative OF nibble_comparator IS . lt. a_gt_b. . im(0). eq. a_eq_b => im(1). inputs only if default 34 © 1999.. b => b(0).. im(2)). eq.. gt. gt => gt. lt => lt. tphl3 => 10 NS) PORT MAP (a(0). END iterative. b. a_lt_b => im(2)). tphl3 => 10 NS) PORT MAP (a => a(0). same mapping as before It must be: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open. .. SAME FORMAT FOR THE PORTS: PORT AS DECLARED: PORT (a. gt. a_eq_b. Zainalabedin Navabi .. BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS...

12. SIGNAL a.15.15. SIGNAL eql. SIGNAL gnd : BIT := '0'.15). a_lt_b : OUT BIT). SIGNAL vdd : BIT := '1'. eql.00. ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a.00. vdd. gtr.ALL.14. lss.14.14. b. 500 NS).14. a_eq_b. Zainalabedin Navabi .15.00. gnd. a_gt_b.14. gt.00. END COMPONENT.15. (0. BEGIN a1: comp4 PORT MAP (a.14. apply_data (b. (0.10.15. END customizable. lt : IN BIT. b : IN BIT_VECTOR (3 DOWNTO 0).15.Design Configuration USE WORK. b : BIT_VECTOR (3 DOWNTO 0).12.00). gtr : BIT.15. Customizable architecture for demonstrating configuration declarations • A customizable test bench • Configuration specification is not included • Comp4 is not in our work library CHAPTER 6 35 © 1999. apply_data (a. lss). gnd. 500 NS). eq.12.basic_utilities.15.

END FOR. END FOR. • Configuring customizable for testing structural architecture of nibble_comparator • Hierarchically enter the architecture. END functional. Zainalabedin Navabi . CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 2 3 USE ENTITY WORK. perform binding CHAPTER 6 36 © 1999.ALL.Design Configuration 1 USE WORK.nibble_comparator(structural).

Design Configuration functional nibble_comparator (structural) nibble_comparator_test_bench (customizable) a1: comp4 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b • Graphical representation • Composition aspect for functional configuration declaration. Zainalabedin Navabi . configuring customizable test bench • Pass through hierarchies with arrows CHAPTER 6 37 © 1999.

• Another configuration on top of the test bench • Configuring customizable for testing iterative architecture of nibble_comparator • No need to recompile the test bench CHAPTER 6 38 © 1999. END FOR.ALL. CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR.nibble_comparator(iterative). Zainalabedin Navabi . END average_delay.Design Configuration USE WORK.

nibble_comparator (iterative) . identifier entity_name configuration declaration binding indication component configuration block configuration • Details of configuration declaration • Configuration declaration replaces or adds to a configuration specification • Includes component configuration and block configuration CHAPTER 6 39 © 1999. END FOR. END average_delay.Design Configuration CONFIGURATION average_delay OF nibble_ comparator_ test_bench IS FOR customizable FOR al : comp4 USE ENTITY WORK. END FOR. Zainalabedin Navabi .

im(i*3+0). im(i*3+2) ). SIGNAL im : BIT_VECTOR ( 0 TO 8). gt. Zainalabedin Navabi . lt. lt : IN BIT. im(i*3-2). im(i*3-1). • A general purpose nibble_comparator • This 4-bit comparator does not use a specific bit comparator • A top-level configuration configures comp1 instantiations CHAPTER 6 40 © 1999. im(7). eq. c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i). b(i).Design Configuration ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. a_lt_b : OUT BIT). im(i*3+1). gt. a_gt_b. END flexible. b. END COMPONENT. b(3). eq. im(i*3-3). a_eq_b. im(8). b(0). END GENERATE. im(2)). im(0). a_lt_b). im(6). a_eq_b. BEGIN c0: comp1 PORT MAP (a(0). c3: comp1 PORT MAP (a(3). im(1). a_gt_b.

Design Configuration default_bit_level bit_comparator(default_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) c3: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b a1: comp4 a(2) b(2) c2: comp1 a(3:0) b(3:0) gt a_gt_b a_eq_b a_lt_b c1to2: im(6) im(7) im(8) gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) • Composition aspect for configuring customizable test bench for testing default_delay bit_comparator • Graphical representation of hierarchies CHAPTER 6 41 © 1999. Zainalabedin Navabi .

END FOR.bit_comparator (default_delay). END FOR. CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR.bit_comparator (default_delay). Zainalabedin Navabi . FOR c1to2 FOR c: comp1 USE ENTITY WORK.Design Configuration USE WORK.nibble_comparator(flexible). END FOR. • Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator • Binding to the default_delay architecture CHAPTER 6 42 © 1999. END FOR. END FOR. FOR flexible FOR c0. END default_bit_level. c3: comp1 USE ENTITY WORK.ALL.

END FOR.nibble_comparator(flexible). Zainalabedin Navabi .bit_comparator (fixed_delay). END FOR. FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (fixed_delay). END fixed_bit_level. END FOR.ALL.Design Configuration USE WORK. END FOR. END FOR. • Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator • Binding to the fixed_delay architecture • Can use ALL or OTHERS CHAPTER 6 43 © 1999. FOR flexible FOR c0. CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR. c3: comp1 USE ENTITY WORK.

Zainalabedin Navabi .Design Configuration passed_bit_level bit_comparator_t(passed_delay) nibble_comparator(flexible) nibble_comparator_test_bench (customizable) a(3:0) b(3:0) a(3) b(3) tplh1 c3: comp1 tplh2 tplh3 a(3:0) b(3:0) gt eq lt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b 2NS 3NS 4NS 4NS 5NS 6NS a1: comp4 a(2) b(2) c2: comp1 tplh1 tplh2 tplh3 a(3:0) b(3:0) gt tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(6) im(7) im(8) 2NS 3NS 4NS 4NS 5NS 6NS gt eq lt eq lt a(1) b(1) c1: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(3) im(4) im(5) 2NS 3NS 4NS 4NS 5NS 6NS c1to2: a(0) b(0) c0: comp1 a(3:0) b(3:0) gt eq lt tplh1 tplh2 tplh3 tphl1 tphl2 tphl3 a_gt_b a_eq_b a_lt_b im(0) im(1) im(2) 2NS 3NS 4NS 4NS 5NS 6NS • Composition aspect of the passed_bit_level • Configuration for test bench for testing passed_delay architecture of bit_comparator_t CHAPTER 6 44 © 1999.

END FOR.nibble_comparator(flexible). END passed_bit_level.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. tphl3 => 6 NS). tplh2 => 3 NS. FOR flexible FOR c0. c3: comp1 USE ENTITY WORK. • Using configuration declarations for component bindings. Zainalabedin Navabi .bit_comparator_t (passed_delay) X GENERIC MAP (tplh1 => 2 NS. END FOR. Y END FOR.ALL. and specification of generic parameters • Same format for generic map and port map aspects as configuration specification CHAPTER 6 45 © 1999. tphl3 => 6 NS). tphl1 => 4 NS. tplh3 => 4 NS. tplh3 => 4 NS. S tphl2 => 5 NS. CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR. tphl2 => 5 NS. tplh2 => 3 NS. tphl1 => 4 NS. N FOR c1to2 T FOR c: comp1 A USE ENTITY WORK. END FOR.Design Configuration USE WORK. END FOR.

FOR c1to2 FOR c: comp1 USE ENTITY WORK. END FOR. tphl2 => 5 NS. tplh2 => 3 NS. entity aspect component configuration generic map aspect block configuration component configuration block configuration • Details of a block configuration enclosing component configurations and other block configurations • Binding indication and generic map aspect CHAPTER 6 46 © 1999. END FOR. tplh3 => 4 NS. tphl3 => 6 NS). tplh2 => 3 NS. tplh3 => 4 NS.bit_comparator_t (passed_delay) GENERIC MAP (tphl1 => 2 NS.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS. END FOR. tphl3 => 6 NS). tphl2 => 5 NS. c3: comp1 USE ENTITY WORK. END FOR. Zainalabedin Navabi . tphl1 => 4 NS. tphl1 => 4 NS.Design Configuration FOR flexible FOR c0.

END GENERATE. ). BEGIN c0: comp1 PORT MAP ( . . . b. • Can do incremental binding • Do some with configuration specification. Zainalabedin Navabi . END COMPONENT. and more with configuration declaration • This is an illustration for the primary binding indication CHAPTER 6 47 © 1999. a_lt_b : OUT BIT). lt : IN BIT. eq. FOR ALL : comp1 USE ENTITY WORK. c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( . . . gt. SIGNAL im : BIT_VECTOR ( 0 TO 8 ). . ). END partially_flexible. ). a_gt_b. . a_eq_b.Design Configuration ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a. c3: comp1 PORT MAP ( .bit_comparator_t (passed_delay).

tphl3 => 6 NS). CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK. END FOR. tphl3 => 6 NS).ALL. tplh3 => 4 NS. tphl1 => 4 NS. tphl2 => 5 NS. tplh2 => 3 NS.nibble_comparator (partially_flexible). tplh2 => 3 NS. • Incremental binding indication illustration • Add generic map aspect to the existing binding • Can use different mappings CHAPTER 6 48 © 1999. c3: comp1 GENERIC MAP (tplh1 => 2 NS. tplh3 => 4 NS. END FOR. tphl2 => 5 NS. END FOR. END FOR. tphl1 => 4 NS. FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS.Design Configuration USE WORK. END incremental. END FOR. END FOR. Zainalabedin Navabi . FOR flexible FOR c0.

illustrating configurations at several levels of depth • Unbound VHDL description of set-reset latch • Uses the same basic components CHAPTER 6 49 © 1999. BEGIN g1 : n2 PORT MAP (s. g3 : n2 PORT MAP (im1. Customizable architecture. c. im2. END COMPONENT. using a sequential example. im3. END sr_latch. o1: OUT BIT). several levels of hierarchy • A new example. END gate_level. c : IN BIT. im3). im4. c. im1). SIGNAL im1. im2. -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1. Zainalabedin Navabi . i2: IN BIT. q <= im3. r. q : OUT BIT). im4). g4 : n2 PORT MAP (im3. g2 : n2 PORT MAP (r.Design Configuration ENTITY sr_latch IS PORT (s. im2). im4 : BIT.

q). END COMPONENT. c : IN BIT. • • • • Building a D-latch Add an inverter to the SR-latch Unbound VHDL description of a D-latch All gate level components are unbound CHAPTER 6 50 © 1999. dbar. END d_latch. END COMPONENT. q : OUT BIT). -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr PORT (s. COMPONENT n1 PORT (i1: IN BIT. c. BEGIN c1 : sr PORT MAP (d. Zainalabedin Navabi . END sr_based. r. o1: OUT BIT).Design Configuration ENTITY d_latch IS PORT (d. dbar). c2 : n1 PORT MAP (d. q : OUT BIT). SIGNAL dbar : BIT. c : IN BIT.

q(i)). c : IN BIT. END latch_based.Design Configuration ENTITY d_register IS PORT (d : IN BIT_VECTOR. END d_register. c : IN BIT. END GENERATE. -ARCHITECTURE latch_based OF d_register IS COMPONENT dl PORT (d. BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i). q : OUT BIT). • Generically generate a register • Unbound VHDL description for an n-bit latch • Configuration specification is not included CHAPTER 6 51 © 1999. q : OUT BIT_VECTOR). c. Zainalabedin Navabi . END COMPONENT.

Design Configuration average_gate_delay d_latch(sr_based) inv_ t(average_delay) 2 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 g4: i2 o1 i1 c2: o1 i1 g2: i2 o1 o1 3 NS 5 NS 5 NS 6 NS di: i1 g1: i2 c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS 5 NS 6 NS nand2_t(average_delay) di: i1 i2 g1: c1: o1 i1 g3: i2 i1 i2 o1 i1 c2: o1 i1 g2: i2 o1 g4: o1 3 NS 5 NS • Composition aspect for configuring the latch_based architecture of d_register • Hierarchical configuration CHAPTER 6 52 © 1999. Zainalabedin Navabi Sr_latch (gate_level) 4 NS 5 NS 6 NS 2 NS 4 NS 2 NS 4 NS 2 NS 4 NS 5 NS 6 NS .

• Configuring d_register for using average_delay gates CHAPTER 6 53 © 1999.ALL. CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK. g3 : n2 2 3 4 5 6 8 USE ENTITY WORK. END FOR. END FOR. 5 NS). FOR c2 : n1 USE ENTITY WORK.nand2_t(average_delay) 9 GENERIC MAP (5 NS.sr_latch(gate_level).inv_t(average_delay) 7 GENERIC MAP (3 NS. END FOR. END FOR.Design Configuration 1 USE WORK. FOR gate_level FOR g2. END average_gate_delay. 6 NS). END FOR. FOR g1.nand2_t(average_delay) 10 GENERIC MAP (2 NS.d_latch(sr_based). END FOR. 4 NS). END FOR. g4 : n2 USE ENTITY WORK. Zainalabedin Navabi . END FOR. END FOR. FOR sr_based FOR c1 : sr USE ENTITY WORK.

6. g4 of n2 Figure 6. 1 Configuration Type Configuration Declaration Block Configuration Block Configuration Component Configuration Block Configuration Component Configuration Component Configuration Block Configuration Component Configuration Component Configuration PURPOSE Visibility or Binding to: Main latch_based ARCHITECTURE Figure 6. 3. 5.46 di instance of dl Figure 6. 5.46 dr GENERATE STATEMENT Figure 6. 4. 3. 4. 5 8 Visibility 1. 2. 2. 6. 2. 3. Zainalabedin Navabi .44 instances g2. 3. g3 of n2 Figure 6.45 c1 instance of sr Figure 6. 2 4 Binding 1.45 c2 instance of sr Figure 6. 4 6 Binding 1. 3. 2.44 Becomes Visible by: - 2 Visibility 1 3 Visibility 1. 2. 8 10 Binding 1. 6 9 Binding 1. 4.Design Configuration Block No. 4. 3.44 instances g1. 4. 8 • Analyzing configuration constructs of the average_gate_delay configuration of d_register • Configuration declaration includes component configurations and block configurations CHAPTER 6 54 © 1999.46 sr_based ARCHITECTURE Figure 6.45 gate_level ARCHITECTURE Figure 6. 2. 2. 3 5 Visibility 1. 5 7 Binding 1. 5.

ALL. END FOR. g4 : n2 USE ENTITY WORK. CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.nand2(single_delay). END FOR. END FOR.sr_latch(gate_level). END FOR. o1). END FOR. END FOR. FOR gate_level FOR g2. END FOR. FOR sr_based FOR c1 : sr USE ENTITY WORK.nand3(single_delay) PORT MAP (i1. END FOR.inv(single_delay). i1. END single_gate_delay. END FOR.Design Configuration USE WORK. FOR c2 : n1 USE ENTITY WORK. • Configuring d_register for using single_delay architectures of inv and nand2 • Deep inside to reach basic gates and their generic parameters CHAPTER 6 55 © 1999. i2.d_latch(sr_based). Zainalabedin Navabi . FOR g1. g3 : n2 USE ENTITY WORK.

clk. '1' AFTER 0700 NS. • Demonstrating the use of configurations in configuration specifications • Test bench for the single_delay architecture of d_register CHAPTER 6 56 © 1999. '0' AFTER 0300 NS. END single. data <= X"00". SIGNAL data. Zainalabedin Navabi . clk <= '0'. c : IN BIT. FOR r8 : reg USE CONFIGURATION WORK.single_gate_delay. X"AA" AFTER 0500 NS. q : OUT BIT_VECTOR (7 DOWNTO 0) ). END COMPONENT. '0' AFTER 0800 NS.Design Configuration ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0). '1' AFTER 0200 NS. outdata). outdata : BIT_VECTOR (7 DOWNTO 0). '1' AFTER 1700 NS. X"55" AFTER 1500 NS. SIGNAL clk : BIT. BEGIN r8: reg PORT MAP (data. '0' AFTER 1800 NS.

Design Configuration a(0) im(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) im(1) im(2) im(3) im(4) im(5) im(6) odd even One more configuration declaration example. Zainalabedin Navabi . iterative hardware • The final example • Will illustrate indexing for alternative binding • Parity generator/checker circuit CHAPTER 6 57 © 1999.

END xor2_t. tphl : TIME := 7 NS). PORT (i1 : IN BIT. END average_delay. -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2.Design Configuration ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS. ---ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS. Zainalabedin Navabi . END average_delay. i2 : IN BIT. PORT (i1. -ARCHITECTURE average_delay OF xor2_t IS BEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2. • Components needed for this design • Timed XOR and INV gates needed for the design of the parity circuit CHAPTER 6 58 © 1999. o1 : OUT BIT). END inv_t. tphl : TIME := 3 NS). o1 : OUT BIT).

Design Configuration ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0). o1: OUT BIT). last: odd <= im(6). END COMPONENT. END COMPONENT. inv: n1 PORT MAP (im(6). a(1). a(i+1). Zainalabedin Navabi . even). END iterative. im(i)). odd. COMPONENT n1 PORT (i1: IN BIT. im(0)). o1: OUT BIT). even : OUT BIT). i2: IN BIT. • Parity circuit description • No configuration specification for the inverter and the exclusive OR gate CHAPTER 6 59 © 1999. END GENERATE. -ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT (i1. BEGIN first: x2 PORT MAP (a(0). END parity. SIGNAL im : BIT_VECTOR ( 0 TO 6 ). middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1).

5 NS). 7 NS). END FOR.Design Configuration CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK. END FOR. FOR middle ( 6) FOR m : x2 USE ENTITY WORK. FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK. Zainalabedin Navabi .xor2_t (average_delay) GENERIC MAP (5 NS. END FOR. and OTHERS the rest CHAPTER 6 60 © 1999.inv_t (average_delay) GENERIC MAP (5 NS.xor2_t (average_delay) GENERIC MAP (6 NS. FOR inv : n1 USE ENTITY WORK. END FOR.xor2_t (average_delay) GENERIC MAP (5 NS. END parity_binding. END FOR. 5 NS). 5 NS). END FOR. pick some. • Parity circuit configuration declaration • Index label of the generate statement • Can use OTHERS. END FOR.

Zainalabedin Navabi . start with the nine-value standard logic • None standard values • Std_logic logic value system • Satisfies most hardware design needs CHAPTER 6 61 © 1999.Use of Libraries Value 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' Representing Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care Standard and user libraries.

Use of Libraries . U X 0 1 Z W L H - U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U' X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' 0 '0' '0' '0' '0' '0' '0' '0' '0' '0' 1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X' L '0' '0' '0' '0' '0' '0' '0' '0' '0' H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X' 'U’ 'X' '0' 'X’ 'X' 'X' '0' 'X' 'X' • AND table for std_logic type • All logic tables are defined and available • Changing BIT to std_logic works in most cases CHAPTER 6 62 © 1999. Zainalabedin Navabi .

END average_delay_mvla. tphl : TIME := 4 NS). -ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS.ALL. • A two-input NAND gate in std_logic value system • Specify library and package • All basic functions are available in this package CHAPTER 6 63 © 1999.std_logic_1164.Use of Libraries LIBRARY IEEE. USE IEEE. i2 : IN std_logic. o1 : OUT std_logic). -ARCHITECTURE average_delay_mvla OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2. PORT (i1. END nand2_t. Zainalabedin Navabi .

1997 June 8. 1997 June 6. Zainalabedin Navabi . 1997 June 6. entities and architectures CHAPTER 6 64 © 1999. 1997 June 6. 1997 • Other libraries • Can define our own • Directory of ls7400 library containing package declarations.Use of Libraries LIBRARY ls7400 simple_gates inv inv(single_delay) nand2 nand2(single_delay) nand3 nand3(single_delay) User: John Designer PACKAGE DECLARATION ENTITY ARCHITECTURE ENTITY ARCHITECTURE ENTITY ARCHITECTURE Date June 9. 1997 June 8. 1997 June 6.

ALL. STD is the standard library that includes the STANDARD and TEXTIO packages All other libraries and packages must be explicitly specified Use ls7400 as a user defined library LIBRARY ls7400. USE ls7400. • Visibility of user libraries and packages • Making all declarations of simple_gates package of ls7400 library available CHAPTER 6 65 © 1999. Zainalabedin Navabi .Use of Libraries • • • • WORK is the default library.simple_gates.

im4 : BIT. q <= im3. im4. c. im3.Use of Libraries LIBRARY ls7400.ALL. c. g4 : n2 PORT MAP (im3. im4). USE ls7400. im3). Zainalabedin Navabi . im2). im2. -ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1. g2 : n2 PORT MAP (r. im1). • Using user libraries • Using component declarations of simple_gates package of ls7400 library for description of set-reset latch CHAPTER 6 66 © 1999. g3 : n2 PORT MAP (im1. END gate_level.simple_gates. BEGIN g1 : n2 PORT MAP (s. im2.

• Visibility into libraries • Making all entities and architectures of the ls7400 library available CHAPTER 6 67 © 1999.Use of Libraries LIBRARY ls7400.ALL. USE ls7400. Zainalabedin Navabi .

USE ls7400. … END FOR. … FOR g1.nand2 (single_delay). • Binding indication needs library name • Using a component configuration for associating g1 and g3 instances of n2 of Figure 661 with nand2 of ls7400 CHAPTER 6 68 © 1999. Zainalabedin Navabi .ALL. g3 : n2 … USE ENTITY ls7400.Use of Libraries LIBRARY ls7400. . .

Design parameterization and configuration of designs were also discussed in great detail. Zainalabedin Navabi . a large design environment with many logic families and technologies to choose from requires a great deal of library management and parameter specification. Next. the subject of packaging utilities and components was addressed. As stated earlier. this topic is used mainly for the organization of a design. design parameterization methods save many compilation runs. • End Of Chapter 6 CHAPTER 6 69 © 1999. Although simple examples and college level exercises can avoid some of these language issues. We believe VHDL is very strong in this area and serious designers should learn to take advantage of such capabilities of the language.Summary This chapter provides tools for better hardware descriptions and design organization. For small circuits and experimental models. We began with the definition of subprograms and emphasized on the use of functions and procedures for simplifying descriptions.

1.5.2.1 Array Attributes 7.5.8 SUMMARY CHAPTER 7 1 © 1999. .4 Access Types 7.2.1.2.3 Signal Attributes 7.4 OTHER TYPES AND TYPE RELATED ISSUES 7.4.1.4.2.4.5 Sign Operators 7.4 Array Declarations 7.8 Aggregate Operation 7.2 Using Real Numbers For Timing Calculations 7.7 Nota Operators 7.4 Entity Attributes 7.2.2.4.3 Shift Operators 7.6 Multiplying Operators 7.4. Navabi and McGraw-Hill Inc.2.2.1 Subtypes 7.1.5 PREDEFINED ATTRIBUTES 7.2 Relational Operators 7.2 VHDL OPERATORS 7.1 Logical Operators 7.1 TYPE DECLARATIONS AND USAGE 7.2 Type Attributes 7.CHAPTER 7 UTILITIES FOR HIGH LEVEL DESCRIPTIONS 7.3 Alias Declaration 7.6 Type Conversions 7.1.2 Record Types 7.7 PACKAGING BASIC UTILITIES 7.5.4 Adding Operators 7. Z.5.1 Enumeration Type for Multi-Value Logic 7.5.3 Physical Types and RC Timing 7.5 File Type and External File I/O 7. Global Objects 7.4.6 USER-DEFINED ATTRIBUTES 7.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING 7.

'Z'.TYPE DECLARATIONS AND USAGE TYPE qit IS ('0'. identifier enumeration element enumeration element enumeration element enumeration element enumeration type definition type definition type declaration Will use an enumeration type for demonstrating type declarations • 4-value qit type will be used • Enumeration type declaration • Initial value of objects of this type is the left-most enumeration element of the base type CHAPTER 7 2 © 1999. Z. initial TYPE qit IS ( ‘0’ . 'X'). ‘X’ ) . . Navabi and McGraw-Hill Inc. ‘Z’ . '1'. ‘1’ .

. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE In: 0 1 Z X 1 0 0 X Out • Will develop basic logic gates based on this type • Input-Output mapping of an inverter in qit logic value system CHAPTER 7 3 © 1999. Z.

o1 : OUT qit). END double_delay. END inv_q. PORT (i1 : IN qit.ALL. • VHDL description of an inverter in qit logic value system • Inputs and outputs are of type qit • Assumes out package contains this type definition CHAPTER 7 4 © 1999. -. Z.From PACKAGE USE : qit ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS.TYPE DECLARATIONS AND USAGE USE WORK. tphl : TIME := 3 NS). Navabi and McGraw-Hill Inc.basic_utilities. -ARCHITECTURE double_delay OF inv_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. .

or o1 <= a WHEN cond =’1’ ELSE UNAFFECTED. Z. Navabi and McGraw-Hill Inc. • • • • A new construct is presented This is conditional signal assignment Several alternatives exist in its usage Can use unaffected for assignments to outputs CHAPTER 7 5 © 1999. o1<= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE UNAFFECTED.TYPE DECLARATIONS AND USAGE Z <= a AFTER 5 NS WHEN d = ’1’ ELSE UNAFFECTED WHEN e = ’1’ ELSE b AFTER 5 NS WHEN f = ’1’ ELSE c AFTER 5 NS. . o1 <= a WHEN cond =’1’ ELSE o1.

. Navabi and McGraw-Hill Inc. target waveform condition waveform condition waveform condition waveform conditional signal assignment • Syntax details of a conditional signal assignment • Condition waveform has a series of waveforms with or without condition CHAPTER 7 6 © 1999.TYPE DECLARATIONS AND USAGE o1 <= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE ‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSE ‘X’ AFTER tplh . Z.

Z.TYPE DECLARATIONS AND USAGE In1: In2: 0 1 Z X 0 1 1 1 1 1 1 0 0 X Out Z 1 0 0 X 1 X X X X • We will develop more basic structures in this 4-value logic system • Input-Output mapping of a NAND gate in qit logic value system • Here we assume 1 for high impedance © 1999. Navabi and McGraw-Hill Inc. CHAPTER 7 7 .

o1 : OUT qit).Can Use: UNAFFECTED. i2 : IN qit.FROM PACKAGE USE : qit ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS.TYPE DECLARATIONS AND USAGE USE WORK. END nand2_q. • • • • VHDL description of a NAND gate in qit logic system A conditional signal assignment is used This is a concurrent statement Conditions are checked sequentially from left to right CHAPTER 7 8 © 1999.ALL. END double_delay. -ARCHITECTURE double_delay OF nand2_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh.basic_utilities. tphl : TIME := 5 NS). -. . -. Z. Navabi and McGraw-Hill Inc. PORT (i1.

TYPE DECLARATIONS AND USAGE inv_rc(double_delay) c_load 25K Ω i1 15K Ω o1 A CMOS inverter example for demonstrating floating point and physical types • • • • Composition aspect of an inverter with RC timing Timing depends on the R and C values Exponential timing is ≅ 3RC Will first demonstrate floating point numbers CHAPTER 7 9 © 1999. . Z. Navabi and McGraw-Hill Inc.

-. END double_delay.0E15) * 3 FS.0. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1. • An inverter model with RC timing parameters • Delay cannot be a fraction of FS • Delay values are calculated based on pull-up. -. -.TYPE DECLARATIONS AND USAGE USE WORK. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh.066E-12).Ohms CONSTANT rpd : REAL := 15000. CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1. o1 : OUT qit). oull-down and load capacitance • Constant values are used in the conditional signal assignment CHAPTER 7 10 © 1999.0.ALL.basic_utilities. Navabi and McGraw-Hill Inc.Ohms END inv_rc. Z. CONSTANT rpu : REAL := 25000.Farads PORT (i1 : IN qit. -.FROM PACKAGE USE: qit ENTITY inv_rc IS GENERIC (c_load : REAL := 0.0E15) * 3 FS. .

END UNITS. -.Femto Farads (base unit) pfr = 1000 ffr. mfr = 1000 ufr. Z. Navabi and McGraw-Hill Inc. ufr = 1000 nfr. kfr = 1000 far. • • • • Type definition for defining the capacitance physical type Use physical types instead of floating point Base unit must be there All others are then defined CHAPTER 7 11 © 1999. .TYPE DECLARATIONS AND USAGE TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr. nfr = 1000 pfr. far = 1000 mfr.

TYPE DECLARATIONS AND USAGE TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o. • Type definition for defining the resistance physical type • Another physical type • RANGE specifies the largest value in terms of base units that an object of this type can get • Intermediate values can take larger values CHAPTER 7 12 © 1999. END UNITS. . Z. g_o = 1000 m_o.Milli-Ohms (base unit) ohms = 1000 l_o. Navabi and McGraw-Hill Inc. m_o = 1000 k_o. k_o = 1000 ohms. -.

o1 : OUT qit). BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh.FROM PACKAGE USE: qit. Navabi and McGraw-Hill Inc. CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000. Z. capacitance ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr). PORT (i1 : IN qit.TYPE DECLARATIONS AND USAGE USE WORK. -. CONSTANT rpu : resistance := 25000 ohms.basic_utilities. resistance. . END double_delay.ALL. • Using resistance and capacitance physical types in the description of an inverter • Resolutions of Millie-ohms and Femto-farads are taken into account • Divide by 1000 adjusts the time units to FS • Will do it with a better style later CHAPTER 7 13 © 1999. END inv_rc. CONSTANT rpd : resistance := 15000 ohms.

TYPE DECLARATIONS AND USAGE TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit. Demonstrating array definition and object declaration • • • • Declaring array types Arrays may be ascending or descending Objects can be indexed as declared n-dimensional arrays may be declared CHAPTER 7 14 © 1999. . TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0. 0 TO 7 ) OF qit. TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit. Navabi and McGraw-Hill Inc. TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble. TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit. Z.

identifier range discrete range index constrained constraint array definition type declaration element_subtype_indication • Syntax details of an array type declaration • This is a type declaration • Contains constraint array definition CHAPTER 7 15 © 1999. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit . . Z.

‘1’. SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. ‘Z’. association by position • Can use aggregate operation. OTHERS => ‘1’). Z. ‘1’). SIGNAL sq8 : qit_byte := (5 => ‘Z’. ‘Z’. ‘1’.TYPE DECLARATIONS AND USAGE SIGNAL sq8 : qit_byte := "ZZZZZZZZ". Navabi and McGraw-Hill Inc. SIGNAL sq8 : qit_byte := (‘Z’. • Objects of array type may be initialized when declared • If explicit initialization is missing. . OTHERS => ‘1’). 3 TO 4 => ‘X’. ‘Z’. SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’. association by name CHAPTER 7 16 © 1999. ‘1’. all elements are initialized to left-most of array element • Can form a vector of initial values • Can use aggregate operation. OTHERS => ‘1’).

• • • • • Signal declarations and signal assignments Arrays may be sliced and used on RHS or LHS Aggregate may be used on RHS and LHS Can concatenate any length or slice size Aggregates operation works with array elements only CHAPTER 7 17 © 1999. bit 3 of sq_nibble_8 into sq1. sq8(3). SIGNAL sq8 : qit_byte.sq4 into left 4 bit slice of sq16.reversing sq8 into sq4. 7).third nibble (number 2) of sq_nibble_8 into sq4. (sq4(0). -.reversing sq8 into sq4. Navabi and McGraw-Hill Inc.nibble 2.right rotate sq8. Z. SIGNAL sq4 : qit_nibble. sq1 <= sq_4_8 (0. sq16 (15 DOWNTO 12) <= sq4. SIGNAL sq_nibble_8 : qit_nibble_by_8. sq8(4).-. -. sq4(2). sq8 <= sq8(0) & sq8 (7 DOWNTO 1).reversing sq8 into sq4. -. sq4(3)) <= sq8 (5 DOWNTO 2). -. SIGNAL sq_4_8 : qit_4by_8. -. sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5). -.lower right bit of sq_4_8 into sq1.middle 8 bit slice of sq16 to sq8. sq8(5)). . sq4 <= sq_nibble_8 (2). SIGNAL sq16 : qit_word. -.TYPE DECLARATIONS AND USAGE Signal Declarations: SIGNAL sq1 : qit. sq4 <= (sq8(2). Valid Operations: sq8 <= sq16 (11 DOWNTO 4). sq1 <= sq_nibble_8(2)(3). sq4(1). -.

TYPE DECLARATIONS AND USAGE Concatenation example: sq4: 3 2 1 0 sq8: 7 6 5 4 3 2 1 0 sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5). Z. . Nice try! • An slicing example is also shown here CHAPTER 7 18 © 1999. reversing bits of sq8 and assigning them to sq4 • Cannot index opposite to what the type is defined as. Navabi and McGraw-Hill Inc. Slice example: sq_nibble_8(2)(3 DOWN To 2) • Referencing bits of a vector.

… := (OTHERS => (OTHERS => ‘0’)) sq_4_8 <= ( 3 => (OTHERS => ‘X’). • Initializing or assignment to a two dimensional array • Right most index applies to deepest set of parenthesis • Can initialize the same way as signal and variable assignment • Constants must have static values CHAPTER 7 19 © 1999.TYPE DECLARATIONS AND USAGE SIGNAL sq_4_8 : qit_4by8 := ( ( '0'. '0'. 'X'. 'Z'. 'X'. '0'. '0'. SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := (OTHERS => “11000000”). '1' ). . (OTHERS => (0 TO 1 => ‘1’. (OTHERS => (0 TO 1 => ‘1’. '1'. 'Z'. OTHERS =>’0’)). '1'. '1'. 'X'. '0'. OTHERS =>’1’). '1'. 7 => ‘X’. OTHERS => (0 => ‘X’. '0'. '1'. OTHERS =>’0’)). ( 'X'. 'X'. (OTHERS => (OTHERS => ‘Z’)). 'Z' ). 'Z'. 'Z'. '1'. 'X'. 'X' ). Navabi and McGraw-Hill Inc. '0'. 0 => (OTHERS => ‘X’). ( 'Z'. 'Z'. '0' ) ). ( '1'. 'Z'. 'X'. Z.

Z. can use other types for array range specification • Then an object of this type may be indexed by enumeration elements of the type in the array range specification CHAPTER 7 20 © 1999.TYPE DECLARATIONS AND USAGE TYPE qit_2d IS ARRAY (qit. ‘X’ => ‘1’. qit) OF qit. ‘X’ => (‘0’ => ‘1’. CONSTANT qit_nand2_table : qit_2d := ( ‘0’ => (OTHERS => ‘1’). Navabi and McGraw-Hill Inc. OTHERS => (‘0’ => ‘1’. Demonstrating non-integer RANGE and index specification • Instead of integers. OTHERS => ‘X’). . OTHERS =>’0’)).

'X'). o1 : OUT qit).'0'. qit_2d ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS.TYPE DECLARATIONS AND USAGE USE WORK.ALL.'X'. ('1'. -. PORT (i1. Navabi and McGraw-Hill Inc. i2 : IN qit.'X'). Z.'X')). . tphl : TIME := 5 NS).'1'.'0'.'X'. ('1'.'1'). END nand2_q. END average_delay. BEGIN o1 <= qit_nand2_table (i1. • Using qit enumeration type for the discrete range of a two-dimensional array • The constant table is an array qit qit if qit elements CHAPTER 7 21 © 1999.'0'.basic_utilities. -ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1'. i2) AFTER (tplh + tphl) / 2. ('1'.'1'.FROM PACKAGE USE: qit.'0'.

Unconstrained array declarations. Navabi and McGraw-Hill Inc. .TYPE DECLARATIONS AND USAGE TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT. Z. TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER. TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER. usage and definition • BIT_VECTOR is a predefined unconstrained array of BITs • STRING is that of CHARACTERS • Can define our own • This is read as RANGE Box CHAPTER 7 22 © 1999.

Z. . identifier type_mark index_subtype definition unconstrained array definition type declaration element_subtype_indication • Syntax details of an unconstrained array declaration • We will use this array in our basic utilities • Cannot have unconstrained array of an unconstrained array. Nice try! CHAPTER 7 23 © 1999. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE TYPE integer_vector IS ARRAY ( NATURAL RANGE <> ) OF INTEGER .

CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE). is also unconstrained All will be known when procedure is called CHAPTER 7 24 © 1999.TYPE DECLARATIONS AND USAGE PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR. . END LOOP. END apply_data. target <= TRANSPORT buf AFTER i * period. BEGIN FOR i IN values'RANGE LOOP int2bin (values(i). Z. target. CONSTANT values : IN integer_vector. Navabi and McGraw-Hill Inc. • • • • A generic version of the apply_data procedure Uses our own integer_vector from basic_utilities Procedure output. buf).

a_gt_b. Z. lt : IN BIT. a_lt_b : OUT BIT). a_lt_b). a_gt_b. BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i). a_lt_b : OUT BIT). im(i*3-1). END COMPONENT. eq. gt.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator IS PORT (a. END structural. END GENERATE. im(i*3+1). im(2) ). im(i*3+2) ). gt. -ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a. im(0). gt. im(i*3+0). b : IN BIT_VECTOR. lt : IN BIT. eq. b(i). b(i). lt. r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i). im(i*3-1). FOR ALL : comp1 USE ENTITY WORK. a_eq_b. m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i). im(i*3-2). b(i). b. a_eq_b. END GENERATE. END GENERATE. a_eq_b. SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1).bit_comparator (functional). im(1). Navabi and McGraw-Hill Inc. im(i*3-2). im(i*3-3). im(i*3-3). END n_bit_comparator. a_gt_b. CONSTANT n : INTEGER := a'LENGTH. END GENERATE. eq. . • • • • Keeping our promise of a better n-bit comparator An n-bit comparator Wiring n number of one-bit comparators The integer n depends on the size of a CHAPTER 7 25 © 1999.

SIGNAL vdd : BIT := '1'. eql. 500 NS). apply_data (b. Navabi and McGraw-Hill Inc. gtr : BIT. gnd. BEGIN a1: comp_n PORT MAP (a. END procedural. b : BIT_VECTOR (5 DOWNTO 0). SIGNAL eql. lt : IN BIT. apply_data (a. .basic_utilities. Z.TYPE DECLARATIONS AND USAGE ENTITY n_bit_comparator_test_bench IS END n_bit_comparator_test_bench . 00&15&57&17. vdd. -USE WORK. FOR a1 : comp_n USE ENTITY WORK.FROM PACKAGE USE: apply_data which uses integer_vector ARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a. a_gt_b. 00&43&14&45&11&21&44&11. gtr. a_lt_b : OUT BIT). gt. SIGNAL gnd : BIT := '0'. • Using generic apply_data procedure for testing n_bit_comparator • All unconstrained arrays are fixed according to the parameters passed to them • Can use different size integer vectors CHAPTER 7 26 © 1999. lss).n_bit_comparator(structural). eq. SIGNAL a. b : IN bit_vector. 500 NS).ALL. b. -. a_eq_b. gnd. END COMPONENT. lss.

Z. Navabi and McGraw-Hill Inc.TYPE DECLARATIONS AND USAGE First. Then a logical file name must be declared FILE input_logic_value_file1: logic_data.dat”. --Declare a logical file and open with the specified mode Primitive utilities for file declaration and file specification • input_logic_value_file: logical name for file of logic_data type • An explicit OPEN statement must be used for opening • Can open a file in READ_MODE. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER. --Declare a logical file and open in READ_MODE FILE input_logic_value_file3: logic_data OPEN READ_MODE IS “input. WRITE_MODE or APPEND_MODE CHAPTER 7 27 © 1999. . --Just declare a logical file FILE input_logic_value_file2: logic_data IS “input.dat”.

Z. Then a logical file name must be declared FILE output_logic_value_file1: logic_data.TYPE DECLARATIONS AND USAGE First. open later FILE output_logic_value_file2: logic_data OPEN WRITE_MODE IS “input. --Just declare a logical file. --Declare a logical file and open with the specified mode OUPUT FILE : WRITE_MODE or APPEND MODE • An explicit OPEN statement must be used for opening the file in the first alternative • Can open a file in READ_MODE.dat”. the file has to be declared as what goes into a file TYPE logic_data IS FILE OF CHARACTER. Navabi and McGraw-Hill Inc. . WRITE_MODE or APPEND_MODE CHAPTER 7 28 © 1999.

The standard package includes: TYPE FILE_OPEN_STATUS IS (OPEN_OK. NAME_ERROR. FILE_CLOSE (output_logic_value_file). WRITE_MODE). “input. • File open alternatives • Status parameter must be declared first • Close a file using its logical name CHAPTER 7 29 © 1999. output_logic_value_file. MODE_ERROR) Closing a file: FILE_CLOSE (input_logic_value_file). . READ_MODE).dat”. FILE_OPEN (output_logic_value_file. STATUS_ERROR. “output.dat”. “output. WRITE_MODE). Z. Navabi and McGraw-Hill Inc. FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS.TYPE DECLARATIONS AND USAGE An explicit OPEN is needed if file is not implicitly opened FILE_OPEN (input_logic_value_file.dat”.

END assign_bits. END IF. END IF.TYPE DECLARATIONS AND USAGE PROCEDURE assign_bits ( SIGNAL s : OUT BIT. file_name : IN STRING. .bit". Navabi and McGraw-Hill Inc. FILE input_value_file : logic_data. ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current. file_name. IF char = '0' THEN s <= TRANSPORT '0' AFTER current. Z. • file_name is a string input containing physical file name • A procedure for reading characters from a file and assigning them to a BIT type • File type is declared in the procedure • En explicit open statement is used CHAPTER 7 30 © 1999. READ_MODE). END LOOP. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. 1500 NS). Calling this procedure: assign_bits (a_signal. "unix_file. period : IN TIME) IS VARIABLE char : CHARACTER. char). VARIABLE current : TIME := 0 NS. IF char = '0' OR char = '1' THEN current := current + period. BEGIN FILE_OPEN (input_value_file.

TYPE DECLARATIONS AND USAGE Declare in an architecture: FILE input_value_file: logic_data IS “my_file. declare a file object outside of the procedure CHAPTER 7 31 © 1999. Z.bit”. this_file : IN FILE). it reads the entire unix_file. because a new file object is declared each time it is called • To avoid.bit • Each time reading begins from the top of the file. Call the pocedure: read_from_file (SIGNAL target : OUT BIT. Navabi and McGraw-Hill Inc. . when assign_bits is called. • In the previous example.

Navabi and McGraw-Hill Inc. x_vector <= a_vector AND b_vector. . b_vector). XNOR. XOR. x <= “XOR” (a.VHDL OPERATORS Logical Operators: AND. x_vector <= “AND” (a_vector. Z. NAND. NOT Examples of use: x <= a XNOR b. Outlining VHDL operators and their format of use • Logical operators • Order of operand must remain the same • The second format makes operands appear as functions CHAPTER 7 32 © 1999. NOR. OR. b).

>.VHDL OPERATORS Relational operators: =. --if a_bit_vector is “00011” and b_bit_vector is “00100” a_bit_vector < b_bit_vector returns TRUE --for qitt: ‘0’ is less than ‘1’. Navabi and McGraw-Hill Inc. . /=. b_boolean <= i1 /= i2. <=. <. and >=) when used with array operands perform ordering operations • These return TRUE or FALSE based on values of array elements starting from the left CHAPTER 7 33 © 1999. and ‘X’ is larger all the rest --for BIT: ‘1’ is greater than ‘0’ • = and /= operate on operands of any type • (<. Z. <=. >. >= Examples of use: a_boolean <= i1 > i2.

. Navabi and McGraw-Hill Inc.VHDL OPERATORS SLL SLA SRL SRA ROL ROR Shift/Rotate Shift Shift Shift Shift Rotate Rotate Left/Right Left Left Right Right Left Right Logical/Arithmetic Logical Arithmetic Logical Arithmetic Logical Logical VHDL operators are formally presented in the next few slides • Shift operators • operand SIFT_OPERATOR number_of_shifts • fill value is the left-most enumeration element CHAPTER 7 34 © 1999. Z.

Z.VHDL OPERATORS Start with aq aq SLL 1 aq SLA 1 aq SRL 1 aq SRA 1 aq ROL 1 aq ROR 1 Z 0 0 0 Z 0 X 0 1 1 Z Z 1 Z 1 X X 0 0 X 0 X Z Z 1 1 Z 1 Z 1 1 X X 1 X 1 0 0 Z Z 0 Z 0 X X 1 1 X 1 X 0 X 0 0 Z 0 • Application of shift operators • The result must be placed in a LHS • Left operand remains unchanged CHAPTER 7 35 © 1999. . Navabi and McGraw-Hill Inc.

b) a_int MOD b_int -. . **. REM Other operators: (). /. Navabi and McGraw-Hill Inc. & Multiplying operators: *.both integers a_int REM b_int -. -. like concatenation. b. MOD. c) – aggregate.VHDL OPERATORS Adding operators: +. ABS Examples of use: a+b “+” (a. Z. but allows only elements • Adding. multiplying.returns remainder of absolute value division (a. aggregate and other operators • Format of use is shown for each operator CHAPTER 7 36 © 1999.

and NOT for qit as easily as for BIT • Tables for the basic logic functions in the qit four value logic system CHAPTER 7 37 © 1999. Navabi and McGraw-Hill Inc.b (a) a: b: 0 1 Z X 0 0 1 1 X 1 1 1 1 1 Z 1 1 1 1 X X 1 1 X Z 0 1 1 X 0 X X X X z=a+b (b) a: 0 1 Z X 1 0 0 X z = a' Demonstrating overloading VHDL operators and subprograms (c) • Want to use AND. OR. Z.SUBPROGRAM PARAMETER TYPES AND OVERLOADING a: b: 0 1 Z X 0 0 0 0 0 1 0 1 1 X z = a. .

TYPE qit_2d IS ARRAY (qit. FUNCTION "OR" (a. 'Z'. b : qit) RETURN qit. Navabi and McGraw-Hill Inc. 'X').SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. FUNCTION "NOT" (a : qit) RETURN qit. b : qit) RETURN qit. -- FUNCTION "AND" (a. . '1'. Z. TYPE qit_1d IS ARRAY (qit) OF qit. qit) OF qit. • In a package declare qit and arrays based on this type • Declare functions to be overloaded • Overloading: identify a function with its operands and name CHAPTER 7 38 © 1999.

'1'. END "OR".'1'). BEGIN RETURN qit_and_table (a.'1'.'1'.'X')).'0'. BEGIN RETURN qit_not_table (a).'X'. FUNCTION "OR" (a.'1'.'1').'X').'X')). FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1'. b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0'. ('0'. Z. b).'1'. END "NOT".'1'.'1'. ('X'.'0'.'X'. ('1'. . • Overloading basic logical functions for the qit four value logic system • Definition of functions CHAPTER 7 39 © 1999.'1'.'0'). ('1'.'1'. ('0'. Navabi and McGraw-Hill Inc.'1'.'1'. END "AND". b).'1'. b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0'.SUBPROGRAM PARAMETER TYPES AND OVERLOADING FUNCTION "AND" (a.'0'.'0'. BEGIN RETURN qit_or_table (a.'X').'X'). ('0'.'X').

ALL. -. END nand2_q.FROM PACKAGE USE: qit. "AND" ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS. o1 : OUT qit). • Using overloaded operators • Cannot use NAND since it is only defined for BIT CHAPTER 7 40 © 1999. i2 : IN qit. END average_delay. PORT (i1.basic_utilities. "NOT" ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS. o1 : OUT qit). tphl : TIME := 4 NS).ALL. tphl : TIME := 3 NS).FROM PACKAGE USE: qit. PORT (i1 : IN qit.basic_utilities. . END average_delay. -ARCHITECTURE average_delay OF inv_q IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2. USE WORK.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. -. Navabi and McGraw-Hill Inc. -ARCHITECTURE average_delay OF nand2_q IS BEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2. END inv_q. Z.

-.ALL. END nand3_q. o1 : OUT qit). • Basic gates in the qit logic value system using overloaded AND operators • Can also overload NAND and other operators • Std_logic has done this for its types CHAPTER 7 41 © 1999. -ARCHITECTURE average_delay OF nand3_q IS BEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2. Navabi and McGraw-Hill Inc. END average_delay.basic_utilities.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. PORT (i1.FROM PACKAGE USE: qit. "AND" ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS. Z. tphl : TIME := 5 NS). i3 : IN qit. i2. .

Navabi and McGraw-Hill Inc.SUBPROGRAM PARAMETER TYPES AND OVERLOADING In the declaration: FUNCTION "*" (a : resistance. . In a package body: FUNCTION "*" (a : resistance. b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000. END "*". Z. the "*" subprogram body and CHAPTER 7 42 © 1999. b : capacitance) RETURN TIME. • Overloading the multiplication operator • Returns TIME when multiplying resistance capacitance physical types • Function declaration.

. Z. Navabi and McGraw-Hill Inc. CONSTANT tphl : TIME := rpd * c_load * 3. -. CONSTANT rpu : resistance := 25 k_o. BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh. END inv_rc. -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3. END double_delay. "*" ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr).FROM PACKAGE USE: qit. resistance. o1 : OUT qit).ALL.SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. • Using the overloaded multiplication operator • The double_delay architecture of inv_rc CHAPTER 7 43 © 1999. PORT (i1 : IN qit.basic_utilities. CONSTANT rpd : resistance := 15 k_o. capacitance.

period. period : IN TIME) IS VARIABLE char : CHARACTER. END assign_bits. READ_MODE). Navabi and McGraw-Hill Inc. 'X'). WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current. • Overloading the assign_bits procedure for accepting and producing qit data • Procedure and other necessary declarations • Subprogram body uses a case statement CHAPTER 7 44 © 1999. current := current + period. WHEN '1' => s <= TRANSPORT '1' AFTER current. . WHEN OTHERS => current := current . PROCEDURE assign_bits ( SIGNAL s : OUT qit. END CASE. VARIABLE current : TIME := 0 NS. WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file. TYPE logic_data IS FILE OF CHARACTER. FILE input_value_file : logic_data. '1'. char). BEGIN FILE_OPEN (input_value_file.SUBPROGRAM PARAMETER TYPES AND OVERLOADING TYPE qit IS ('0'. Z. 'Z'. END LOOP. WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current. CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current. PROCEDURE assign_bits ( SIGNAL s : OUT qit. file_name. file_name : IN STRING. file_name : IN STRING. period : IN TIME).

SUBPROGRAM PARAMETER TYPES AND OVERLOADING CASE char IS WHEN ‘0’ => target <= TRANSPORT ‘0’ AFTER current. Z. . END CASE. WHEN ‘Z’  ‘z’ => target <= TRANSPORT ‘Z’ AFTER current. WHEN ‘X’  ‘x’ => target <= TRANSPORT ‘X’ AFTER current. WHEN OTHERS => current := current – period. WHEN ‘1’ => target <= TRANSPORT ‘1’ AFTER current. Navabi and McGraw-Hill Inc. sequence_of statements case_statement alternative expression choice case_statement alternative sequence_of statements sequence_of statements choices case_statement alternative case_statement alternative sequence_of statements choice sequence_of statements case_statement alternative • Syntax details of a sequential case statement • Consists of several case alternatives • All choices must be filled CHAPTER 7 45 © 1999.

SIGNAL a. "data. FOR ALL : inv USE ENTITY WORK. capacitance.basic_utilities. Z.ALL. -. -ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr). i1 : inv PORT MAP (a. 500 NS). Navabi and McGraw-Hill Inc. resistance. z : qit. END COMPONENT. assign_bits ENTITY tester IS END tester.inv_rc(double_delay). o1 : OUT qit). z). PORT (i1 : IN qit. • Calling the overloaded assign_bits for testing an inverter • The inverter with RC delay is being tested • Type qit operand of the procedure causes the new assign_bits to be called CHAPTER 7 46 © 1999. END input_output.qit".SUBPROGRAM PARAMETER TYPES AND OVERLOADING USE WORK. BEGIN assign_bits (a.FROM PACKAGE: qit. .

Z.OTHER TYPES AND RELATED ISSUES SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0). . SUBTYPE rit IS qit RANGE '0' TO 'Z'. Other type related issues. SUBTYPE bin IS qit RANGE '0' TO '1'. and aliases are discussed • • • • Subtypes are used for compatibility Base type of a subtype is the original type nibble_bits is not compatible with any BIT_VECTOR rit and bin are fully compatible with qit CHAPTER 7 47 © 1999. TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT. Navabi and McGraw-Hill Inc. subtypes. records. SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9.

END RECORD. SIGNAL instr : instruction_format := (nop. nop. jsr). "00000000000"). sub. TYPE address IS BIT_VECTOR (10 DOWNTO 0). lda. TYPE mode IS RANGE 0 TO 3.adr <= "00011110000". instr <= (adr => (OTHERS => ‘1’). CHAPTER 7 . Navabi and McGraw-Hill Inc.OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode address Instruction format TYPE opcode IS (sta. 0. opc => sub) • • • • • • Record Type Three fields of an instruction Declaration of instruction format A signal of record type Referencing fields of a record type signal Record aggregate 48 © 1999. TYPE instruction_format IS RECORD opc : opcode.opc <= lda. add. mde => 2. adr : address. and. mde : mode. Z. instr. instr.mde <= 2. jmp. instr.

adr (7 DOWNTO 0). .OTHER TYPES AND RELATED ISSUES 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opcode mode page address offset ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr.adr (10 DOWNTO 8). • Alias declaration. Navabi and McGraw-Hill Inc. offset <= X"F1". Z. page and offset addresses • Alias declaration for the page and offset parts of the address • Assignments to page and offset parts of address CHAPTER 7 49 © 1999. page <= "001". ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr.

link : pointer. TYPE node IS RECORD data : INTEGER.OTHER TYPES AND RELATED ISSUES head link node data link node data link node data NULL data Integer Type link Pointer Type TYPE node. TYPE pointer IS ACCESS node. Navabi and McGraw-Hill Inc. ACCESS type and implementation and usage of linked lists is demonstrated • Linked list graphical representation • Definition in VHDL starts with an incomplete type definition CHAPTER 7 50 © 1999. . END RECORD. Z.

link := NEW node. head := NEW node. Linking the next node: head. Navabi and McGraw-Hill Inc. . Z. • Using the above linked list • Declaring head and linking to it CHAPTER 7 51 © 1999.OTHER TYPES AND RELATED ISSUES Declaration of head as the head of a linked list to be created: VARIABLE head : pointer := NULL. Assigning the first node to head.

Z. BEGIN -. END lineup.link := NEW node.link. (25. 12. t1 := t1.Insert data in the linked list head := NEW node. FOR i IN int'RANGE LOOP t1. 20)).OTHER TYPES AND RELATED ISSUES PROCEDURE lineup (VARIABLE head : INOUT pointer. cache : pointer := NULL. Inserting integers into the mem linked list: lineup (mem. 19. int : integer_vector) IS VARIABLE t1 : pointer. 17. Navabi and McGraw-Hill Inc.link := NULL.data := int(i). . t1 := head. Declare mem: VARIABLE mem. • • • • Creating a linked list and entering data into it Head is returned as the first node of the linked list A new node of type node is obtained and assigned to head Fields of node are accessed and data is entered into them CHAPTER 7 52 © 1999. 18. END IF. ELSE t1. IF i = int'RIGHT THEN t1. END LOOP.

END remove.link := t2. t1 := t1. BEGIN -.OTHER TYPES AND RELATED ISSUES PROCEDURE remove (VARIABLE head : INOUT pointer. END LOOP. DEALLOCATE (t2). .data = v THEN t2 := t1. t1. END IF.link. v : IN INTEGER) IS VARIABLE t1. Z.Remove node following that with value v t1 := head.link. WHILE t1 /= NULL LOOP IF t1.link. • Removing an item from a linked list • The head of the linked list is passed • Node that follows node with value v is removed CHAPTER 7 53 © 1999. t2 : pointer. Navabi and McGraw-Hill Inc.

• Freeing a linked list • Start with he head of a linked list and clear it • All nodes must be deallocated CHAPTER 7 54 © 1999. WHILE t1 /= NULL LOOP t2 := t1. . t1 := t1.link. DEALLOCATE (t2). END clear. Navabi and McGraw-Hill Inc. END ll_utilities.Free all the linked list t1 := head. Z. BEGIN -. END LOOP. head := NULL. t2 : pointer.OTHER TYPES AND RELATED ISSUES PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1.

END ll_utilities. END clear. END LOOP. WHILE t1 /= NULL LOOP t2 := t1. v : IN INTEGER) IS VARIABLE t1. BEGIN -. -PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1. t1. t2 : pointer.OTHER TYPES AND RELATED ISSUES PACKAGE ll_utilities IS TYPE node. END remove. t1 := t1. ELSE t1. END RECORD. END IF. Z. head := NULL. DEALLOCATE (t2). TYPE node IS RECORD data : INTEGER.link := NEW node.Free all the linked list t1 := head.Remove node following that with value v t1 := head. • Linked list utilities CHAPTER 7 55 © 1999. t1 := t1. IF i = int'RIGHT THEN t1. TYPE pointer IS ACCESS node.link := NULL.link. t2 : pointer. END lineup. t1 := t1.Insert data in the linked list head := NEW node. PROCEDURE clear (VARIABLE head : INOUT pointer). PROCEDURE lineup (VARIABLE head : INOUT pointer.data = v THEN t2 := t1. -PROCEDURE remove (VARIABLE head : INOUT pointer. t1 := head.link.link. . END LOOP. FOR i IN int'RANGE LOOP t1.link. TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER. END ll_utilities. PROCEDURE remove (VARIABLE head : INOUT pointer. link : pointer. -PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer. v : IN INTEGER).link := t2. BEGIN -. DEALLOCATE (t2). int : integer_vector). BEGIN -. Navabi and McGraw-Hill Inc. END LOOP. END IF.link. WHILE t1 /= NULL LOOP IF t1. int : integer_vector) IS VARIABLE t1 : pointer.data := int(i).

sq4(2). sq4(1). Navabi and McGraw-Hill Inc. SIGNAL qo : qit_octal. qb <= qo.g. SIGNAL qb : qit_byte. ‘X’ can be interpreted as character ‘X’. -.. e. .Must do explicit type conversion • Share variables • Using qualifiers • Explicit type conversion between closely related types CHAPTER 7 56 © 1999. In the assignment: (sq4(0). .CANNOT DO qb <= qit_byte (qo).. sq4(2). sq4(3)) <= qit_nibble’ (OTHERS => ‘X’). requires a qualifier: (sq4(0). Z. Now ‘X’s are qualified for size and element type Explicit type conversions for closely related types. TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit. sq4(3)) <= (OTHER => ‘X’). INTEGER and REAL TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit.OTHER TYPES AND RELATED ISSUES SHARED VARIABLE dangerous : INTEGER := 0. sq4(1). -..

std_logic is an enumeration type with nine logic values ‘U’ is the default initial value std_logic_vector is an unconstraned array of std_logic All logical and shift operators are overloaded for std_logic and std_logic_vector Conversion functions for all subtypes and the BIT type to and from std_logic std_logic.OTHER TYPES AND RELATED ISSUES LIBRARY IEEE.std_logic_1164. its overloading and its subtypes is a good example of the above topics • Provides types for most applications • Overloading is done for all operators • Includes conversion functions where needed CHAPTER 7 57 © 1999. Z. USE IEEE. Navabi and McGraw-Hill Inc. .ALL.

Navabi and McGraw-Hill Inc. ‘Z’ • std_logic subtypes • Enumeration elements are arranged for such subtypes • Our qit is like UX01 or X01Z. ‘U’.OTHER TYPES AND RELATED ISSUES TYPE X01 X01Z UX01 UX01Z ‘X’. ‘1’ ‘1’. ‘Z’ ‘1’ ‘1’. ‘0’. ‘U’. . ‘X’. different initial values CHAPTER 7 58 © 1999. ‘X’. ‘0’. ‘0’. ‘X’. ‘0’. Z.

Array. Signal. Navabi and McGraw-Hill Inc. Z. and Entity • Predefined Array Attributes • Type of sq_4_8 is qit_4by8 CHAPTER 7 59 © 1999. .PREDEFINED ATTRIBUTES Attribute ‘LEFT ‘RIGHT Description Left bound Right bound Example sq_4_8’LEFT(1) sq_4_8’RIGHT sq_4_8’RIGHT(2) sq_4_8’HIGH(2) sq_4_8’LOW(2) sq_4_8’RANGE(2) sq_4_8’RANGE(1) sq_4_8’REVERSE_RANGE(2) sq_4_8’REVERSE_RANGE(1) sq_4_8’LENGTH sq_4_8’ASCENDING(2) sq_4_8’ASCENDING(1) 3 0 7 7 0 Result ‘HIGH ‘LOW ‘RANGE Upper bound Lower bound Range 0 TO 7 3 DOWNTO 0 7 DOWNTO 0 0 TO 3 4 TRUE FALSE ‘REVERSE_RANGE Reverse range ‘LENGTH ‘ASCENDING Length TRUE If Ascending Predefined attributes are demonstrated here. Type.

. after value V in base of type.. Value. Navabi and McGraw-Hill Inc. Z. • Predefined type attributes • The type of qit and rit are enumeration types • More follows ... . CHAPTER 7 60 © 1999. . before value V in base of type. Value. . .PREDEFINED ATTRIBUTES Attribute ‘BASE ‘LEFT ‘RIGHT Description Base of type Left bound of type or subtype Right bound of type or subtype Upper bound of type or subtype Lower bound of type or subtype Position of value V in base of type. Value at Position P in base of type.... ... Example rit’BASE rit’LEFT qit’LEFT rit’RIGHT qit’RIGHT INTEGER’HIGH rit’HIGH POSITIVE’LOW qit’LOW qit’POS(‘Z’) rit’POS(‘X’) qit’VAL(3) rit’VAL(3) rit’SUCC(‘Z’) Result qit ‘0’ ‘0’ ‘Z’ ‘X’ Large ‘Z’ 1 ‘0’ 2 3 ‘X’ ‘X’ ‘X’ ‘HIGH ‘LOW ‘POS(V) ‘VAL(P) ‘SUCC(V) ‘PRED(V) rit’PRED(‘1’) ‘0’ .

. Converts string S to value of type. ‘LEFTOF(V) ... Value. Z.. . left of value V in base of type. rit’LEFTOF(‘1’) rit’LEFTOF(‘0’) rit’RIGHTOF(‘1’) rit’RIGHTOF(‘Z’) qit’ASCENDING qqit’ASCENDING qit’IMAGE(‘Z’) qqit’IMAGE(qZ) qqit’VALUE(“qZ”) ‘RIGHTOF(V) ‘ASCENDING ‘IMAGE (V) ‘VALUE(S) • Predefined type attributes • The type of qit and rit are enumeration types • Note type versus base of type CHAPTER 7 61 © 1999.. TRUE if range is ascending Converts value V of type to string.PREDEFINED ATTRIBUTES Attribute . Description .. right of value V in base of type.. Navabi and McGraw-Hill Inc. Example Result .. ‘0’ Error ‘Z’ ‘X’ TRUE TRUE “’Z’” “qZ” qZ Value.

Navabi and McGraw-Hill Inc. If no parameter or 0. . ‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN A signal that is TRUE if s1 has not changed in the last 5 NS. Z. .PREDEFINED ATTRIBUTES Attribute T/E Example Kind Type Attribute description for the specified example ‘DELAYED s1’DELAYED (5 NS) SIGNAL As s1 A copy of s1. ‘EVENT EV s1’EVENT VALUE BOOLEAN In a simulation cycle. the value of s1’LAST_VALUE is 0. but delayed by 5 NS. if s1 changes. • Predefined signal attributes • Signal s is assumed to be of type BIT • More follows . If s1’EVENT is TRUE. .. Equivalent to TRANSPORT delay of s1. . ‘LAST_EVENT EV s1’LAST_VALUE VALUE TIME The amount of time since the last value change on s1. ‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1 The value of s1 before the most recent event occurred on this signal. delayed by delta. If no parameter or 0. CHAPTER 7 62 © 1999.. the resulting signal is TRUE if s1 has not changed in the current simulation time. this attribute becomes TRUE.

If no parameter or 0.. Kind Type ‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS. s1’DRIVING is TRUE in the same process. If s1’ACTIVE is TRUE.PREDEFINED ATTRIBUTES Attribute T/E Example . ‘DRIVING s1’DRIVING VALUE BOOLEAN If s1is being driven in a process. Initial value of this attribute is not defined. . ‘TRANSACTION TR s1’TRANACTION SIGNAL BIT A signal that toggles each time a transaction occurs on s1. ‘DRIVING_VALUE s1’DRIVING_VALUE VALUE As s1 The driving value of s1 from within the process this attribute is being applied. • Predefined signal attributes • Signal s is assumed to be of type BIT CHAPTER 7 63 © 1999. ‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME The amount of time since the last transaction occurred on s1. Navabi and McGraw-Hill Inc.. the current simulation cycle is assumed. s1’LAST_ACTIVE is 0. ‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN If s1 has had a transaction in the current simulation cycle. s1’ACTIVE will be TRUE for this simulation cycle. Z. for delta time.

. s1 • Blocks show Boolean results CHAPTER 7 64 © 1999. Navabi and McGraw-Hill Inc.PREDEFINED ATTRIBUTES 15 TIME (NS) 30 45 60 s1 s1'DELAYED (5NS) s1'STABLE s1'EVENT 10 s1'LAST_EVENT s1'LAST_VALUE s1'QUIET (5NS) 15 20 25 0 5 10 0 5 10 15 s1'ACTIVE 10 s1'LAST_ACTIVE 0 5 10 0 5 10 0 5 10 0 s1'TRANSACTION • Results of signal attributes when applied to the BIT type signal. Z.

PREDEFINED ATTRIBUTES ENTITY brief_d_flip_flop IS PORT (d. • A simple falling edge Flip-Flop using signal attributes • Two events occur when c changes • Cannot delay the first statement CHAPTER 7 65 © 1999. -ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT. Navabi and McGraw-Hill Inc. BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp. END falling_edge. END brief_d_flip_flop. . q : OUT BIT). q <= tmp AFTER 8 NS. c : IN BIT. Z.

-ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT. q : OUT BIT). END brief_t_flip_flop. q <= tmp AFTER 8 NS. . END toggle. Navabi and McGraw-Hill Inc. • A simple toggle Flip-Flop using signal attributes • Combining several signal attributes • Can only apply if result of an attribute is signal CHAPTER 7 66 © 1999. BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp.PREDEFINED ATTRIBUTES ENTITY brief_t_flip_flop IS PORT (t : IN BIT. Z.

Z. types. . groups. architecture. constants. Navabi and McGraw-Hill Inc. signals. variables. literals.PREDEFINED ATTRIBUTES Entity Attributes generate a string corresponding to the name of an entity class “entity_class” entities. configurations. and files ‘SIMPLE_NAME: Generates simple name of a named entity ‘PATH_NAME : Generates a string containing entity names and labels from the top of hierarchy leading to the named entity. labels. components. ‘INSTANCE_NAME: Generates a name that contains entity. subtypes. packages. functions. • Entity attributes • Generate a string for the name for an entity class CHAPTER 7 67 © 1999. architectures. units. and instantiation labels leading to the design entity. procedures.

'). i2 : IN BIT. c : BIT. path. END ENTITY.nand2 PORT MAP (b. i2 : IN BIT. Z. simple <= nand2'SIMPLE_NAME. -ARCHITECTURE gate_level OF xoring IS SIGNAL a. Navabi and McGraw-Hill Inc. END gate_level. path <= nand2'PATH_NAME. instance <= nand2'INSTANCE_NAME. u3 : ENTITY WORK. i2. c).PREDEFINED ATTRIBUTES ENTITY nand2 IS PORT (i1. u2 : ENTITY WORK. -ARCHITECTURE single_delay OF nand2 IS SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH) := (OTHERS => '.'). SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH) := (OTHERS => '. o1 : OUT BIT). • Examples for entity attributes • Simple. a). i2.nand2 PORT MAP (i1. BEGIN o1 <= i1 NAND i2 AFTER 3 NS. BEGIN u1 : ENTITY WORK. a. END ENTITY.').nand2 PORT MAP (a. o1 : OUT BIT). b). c.nand2 PORT MAP (i1. -ENTITY xoring IS PORT (i1. b. . END single_delay. u4 : ENTITY WORK. and instance attributes CHAPTER 7 68 © 1999. SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH) := (OTHERS => '. o1).

PREDEFINED ATTRIBUTES Simple: Path: Instance: nand2 :xoring:u1: “xoring(gate_level):u1@nand2(single_delay): • Simple. . path. Navabi and McGraw-Hill Inc. Z. and instance strings • Results from simulation of the above nand2 CHAPTER 7 69 © 1999.

USER-DEFINED ATTRIBUTES

User-defined attributes may be applied to the elements of an entity class

Must declare first: ATTRIBUTE sub_dir : STRING;

Then attribute specification: ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS “/user/vhdl”;

brief_d_flip_flop’sub_dir evaluates to “/user/vhdl”.

User-defined attributes are demonstrated here.

• User defined attributes • No simulation semantics

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PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING; END utility_attributes; -USE WORK.utility_attributes.ALL; -- FROM PACKAGE USE: delay, sub_dir ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS); END brief_d_flip_flop; -ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall; END attributed_falling_edge;

• • • •

Associating attributes to entities and signals A package declares attributes An entity defines An architecture uses attributes

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PACKAGING BASIC UTILITIES

PACKAGE basic_utilities IS ... TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL; ... FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; FUNCTION to_integer (qin : qit_vector) RETURN INTEGER; FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector; ... FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector; ... END basic_utilities;

• Adding what was done to our basic utilities package • Will use this package for homeworks and in other chapters

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PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;

• Complete package declaration

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PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;

• Package body
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PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;®BB¯

• Package body

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PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits; END basic_utilities;

• The basic_utilities package as will be used in the examples in the chapters that follow

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Summary This chapter presented tools for high level descriptions. Declaration of types and the usage of objects of various types were covered in the first part of the chapter. In the context of describing type-related issues, we introduced the unconstrained array and file type. The basic I/O presented in this chapter showed a simple way to read or write from files. The overloading which is related to types was discussed next. Predefined attributes in VHDL can be looked upon as operators or predefined functions. In modeling, hardware behavior attributes are very useful, as we will see in the following, chapters. Finally in this chapter, we presented the Elements of this package are

basic_utilities package.

useful for hardware modeling and the creation of the package demonstrates the importance of packaging capability in VHDL.

• End Of Chapter 7

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CHAPTER 8 DATAFLOW DESCRIPTIONS IN VHDL

8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals 8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine 8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING 8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY

• • • • • • •

Constructs for dataflow descriptions Multiplexing and clocking, selection constructs; guarded assignments Multiple assignments; Resolutions: anding, oring, wiring Guarded signals State machines, simple sequence detector, multiple active states Open collectors using resolution functions A complete dataflow example

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION
select1

data1

out select2

data2

(a)

1D 2D y S1 S2

D1

Y D2

S1 S2

Will use VHDL for modeling various selection logic implementations

• Basic data selection hardware, logic diagram, symbols • Multiplexers are used for data selection

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© 1999, Z. Navabi and McGraw-Hill Inc.

MULTIPLEXING AND DATA SELECTION

Q

enable

data

1D C1

clk

• Flip flop clocking selects data • Various forms of data selection may be combined • Will show language constructs for such selections

CHAPTER 8

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© 1999, Z. Navabi and McGraw-Hill Inc.

Z. Navabi and McGraw-Hill Inc. CHAPTER 8 4 © 1999. .MULTIPLEXING AND DATA SELECTION data1 data2 1D 2D Y 1D Q select1 select2 S1 S2 C1 enable clk • Multiplexing and clock enabling.

Z. . CHAPTER 8 5 © 1999. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION G0 G1 select lines G2 G3 G4 G5 G6 G7 MUX Z 0 1 2 data inputs 3 4 5 6 7 • An eight-to-one multiplexer.

i1 AFTER 3 NS WHEN "00000010" | "000000Z0". i0 AFTER 3 NS WHEN "00000001" | "0000000Z". i1. Navabi and McGraw-Hill Inc. s2. i0 : IN qit. • • • • Description of a simple multiplexer Selected signal assignment is used Dataflow multiplexing Selected waveforms use choice or choices CHAPTER 8 6 © 1999. i3 AFTER 3 NS WHEN "00001000" | "0000Z000". 'X' WHEN OTHERS. i6 AFTER 3 NS WHEN "01000000" | "0Z000000". s1. -. s3. i2. s5. -ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector’(s7. z : OUT qit ). i3. s4.FROM PACKAGE USE: qit. qit_vector ENTITY mux_8_to_1 IS PORT ( i7. . s2. s6. i6. i5.MULTIPLEXING AND DATA SELECTION USE WORK. i2 AFTER 3 NS WHEN "00000100" | "00000Z00".ALL. s7. i5 AFTER 3 NS WHEN "00100000" | "00Z00000". Z.basic_utilities. s3. s1. i4 AFTER 3 NS WHEN "00010000" | "000Z0000". s0 : IN qit. i7 AFTER 3 NS WHEN "10000000" | "Z0000000". s6. s5. i4. END dataflow. s4. END mux_8_to_1. s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000".

Navabi and McGraw-Hill Inc. . Z. CHAPTER 8 7 © 1999.MULTIPLEXING AND DATA SELECTION • Syntax details of a selected signal assignment.

Navabi and McGraw-Hill Inc. which we will model in VHDL • Decoder description uses selected signal assignment • A three-to-eight decoder. .MULTIPLEXING AND DATA SELECTION A0 A1 A2 DCD S0 S1 S2 S3 S4 S5 S6 S7 Another form of selection is a decoder. Z. CHAPTER 8 8 © 1999.

"00010000" AFTER 2 NS WHEN "100" | "Z00". "XXXXXXXX" WHEN OTHERS. "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011".ALL. END dcd_3_to_8. -ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000". END dataflow. • All possibilities must be considered CHAPTER 8 9 © 1999. • VHDL description for the three-to-eight decoder. so : OUT qit_vector (7 DOWNTO 0)). -. Navabi and McGraw-Hill Inc. "00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" . Z. "00000010" AFTER 2 NS WHEN "00Z" | "001".MULTIPLEXING AND DATA SELECTION USE WORK.FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0). . "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110".basic_utilities. "00000100" AFTER 2 NS WHEN "0Z0" | "010". "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111".

END d_flipflop. q <= internal_state AFTER delay1. END assigning. PORT (d. . q. Z. BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state. delay2 : TIME := 5 NS). qb <= NOT internal_state AFTER delay2. Navabi and McGraw-Hill Inc. -ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT. 1D Q Q C1 • A simple flip-flop uses internal_state • On clock edge d is transferred to internal_state • Events on internal_state cause assignments to q and qb CHAPTER 8 10 © 1999. c : IN BIT. qb : OUT BIT).MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS.

ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1. Z. 1D Q Q C1 Several examples will demonstrate guarded blocks and assignments • • • • • The guarding architecture for the d_flipflop entity. END guarding. Navabi and McGraw-Hill Inc. Better representation of clocking disconnects d from q Disconnection is specified by GUARDED GUARDED assignments are guarded by guard expression Can also guard selected and conditional signal assignments CHAPTER 8 11 © 1999. . qb <= GUARDED NOT d AFTER delay2. END BLOCK ff.MULTIPLEXING AND DATA SELECTION target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms.

Z. guard_expression concurrent statement block statement part block statement concurrent statement • Syntax details of a guarded block statement with guarded signal assignments • Label is mandatory • Use GUARDED for guard to apply CHAPTER 8 12 © 1999. qb <= GUARDED NOT d AFTER delay2.MULTIPLEXING AND DATA SELECTION ff : BLOCK ( block_label Concurrent statement c = ‘1’ AND NOT c’STABLE ) BEGIN q <= GUARDED d AFTER delay1. END BLOCK ff. . Navabi and McGraw-Hill Inc.

q. q2. END COMPONENT. qb1). END input_output. q1. . cc. Navabi and McGraw-Hill Inc. dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd. c2: flop PORT MAP (dd. qb : OUT BIT).MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. • A test bench for testing assigning and guarding architectures of d_flipflop • Testbench tests and verifies both descriptions • A simple method for generation of periodic signals CHAPTER 8 13 © 1999. FOR c2 : flop USE ENTITY WORK. qb2). qb2 : BIT. c : IN BIT. cc. q1. q2.d_flipflop (assigning).d_flipflop (guarding). FOR c1 : flop USE ENTITY WORK. Z. SIGNAL dd. qb1. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc. cc. c1: flop PORT MAP (dd. -ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d.

.. '1' . ... . .... . ..... TRUE FALSE .... . ..... ... ......... FALSE FALSE ...... .. .. . q1 '0' ........ '0' . ..... ...... ......... .......... '1' c1: state '0' '0' ... . .. . '0' .... .. '1' qb2 '0' ... .... . . ...... .... '0' . . . '0' ..... . '1' ... . '0' ..... .. . . ....... . .... ... Navabi and McGraw-Hill Inc. .. . .. ..... '0' .... . '1' . . . ... ..... . .. ...... '1' '1' ..... '1' . .. '0' ...... . '0' ............................ . .. ...... .. '1' . qb1 '0' .... '0' '0' . '0' '0' .... . . '1' '1' . .... . . .. . '1' '1' . ........... '1' ......... . .. .... FALSE FALSE . ... ........ . c2:ff GUARD FALSE ... .. .. ..... ....... • • • • • • Simulation results of the input_output architecture of the flipflop_test All transactions are observed In assigning:Two transactions on internal_state for every clock edge Transaction on q1 at time 0004.... ...... ..... .... . . .... ... . TRUE FALSE ...... ... .. .. .. .. ........ '1' ... .....MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0004 0005 0400 +1δ δ +2δ δ 0404 0405 0800 +1δ δ +2δ δ 1000 +1δ δ 1200 +1δ δ +2δ δ 1204 1205 1600 +1δ δ +2δ δ 2000 +1δ δ +2δ δ 2004 2005 cc '0' . ... .. . .. TRUE FALSE ... ... .. . . .. . . ... '0' ....... ....... .............. .... .. '0' '0' ...... . .. . ......ff : GUARD sees GUARD inside guarding Guard expression is only TRUE for 1 delta © 1999.... . '0' '0' ....... .. .. . Z. ... .. ...... . ... . . . .. is due to initialization In guarding:c2.... ... . dd '0' . ... CHAPTER 8 14 . . . . q2 '0' . .. ..... ...

c Scheduling on S (d. 0) UNAFFECTED (a) Value = d s Value = s s <= d WHEN (c= ‘1’ AND c’EVENT) ELSE UNAFFECTED. c Scheduling on S (d. 0) (c) Value = s s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND c’EVENT) ELSE s.MULTIPLEXING AND DATA SELECTION s <= d WHEN (c= ‘1’ AND NOT c’STABLE) ELSE UNAFFECTED. 6) (d) Value = s Value = d s • Events on edge detection expression • Demonstrating difference between ‘EVENT and NOT ‘STABLE CHAPTER 8 15 © 1999. c Scheduling on S (d. Navabi and McGraw-Hill Inc. 0) (b) Value = d s Value = s s <= d AFTER 6 NS WHEN (c= ‘1’ AND NOT c’STABLE) ELSE s. c Scheduling on S (d. 6) (s. Z. .

Z. PORT MAP (din => d. c : IN BIT. -ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT. END guarding. q. END BLOCK ff. qout. qout => q. END ENTITY. qbar => qb). BEGIN qout <= GUARDED din AFTER delay1. qbar <= GUARDED NOT din AFTER delay2. . qbar : OUT BIT). • • • • Using declarative part of a block statement PORT specifies signals on the outside PORT MAP maps outside signals with those inside Association format is used as expected CHAPTER 8 16 © 1999. PORT (d. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS. delay2 : TIME := 5 NS). qb : OUT BIT).

. . . Z. ) PORT ( . block_statement port_clause port_map_aspect block_header block_statement_part • Syntax details for block statement with header • Uses this to draw a dashed line around a section of your hardware CHAPTER 8 17 © 1999.. ). . . PORT MAP ( .. . . . qbar <= . BEGIN qout <= . . ). . . Navabi and McGraw-Hill Inc. END BLOCK ff.MULTIPLEXING AND DATA SELECTION ff : BLOCK ( .

MULTIPLEXING AND DATA SELECTION 1. . Navabi and McGraw-Hill Inc. 2D Q E2 C1 Q • A positive edge trigger flip-flop with enable input • Can nest block statements • Combining guard expressions must be done explicitly CHAPTER 8 18 © 1999. Z.

qb <= GUARDED NOT d AFTER delay2.MULTIPLEXING AND DATA SELECTION ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS. q. END guarding. Navabi and McGraw-Hill Inc. PORT (d. END BLOCK gate. END de_flipflop. END BLOCK edge. • VHDL description for the positive edge trigger flip-flop with enable input • Implicit GUARD signals in each block • Useful if different second conditions were used CHAPTER 8 19 © 1999. . Z. e. delay2 : TIME := 5 NS). qb : OUT BIT). c : IN BIT. -ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1.

gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1. c : IN BIT. END BLOCK gate3. qb : OUT BIT). e3. 3D Q E2 E3 C1 Q • A positive edge trigger. END guarding. e2.MULTIPLEXING AND DATA SELECTION ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS. . END BLOCK gate2. qb <= GUARDED NOT d3 AFTER delay2. double d flip-flop with independent enable inputs • Clock expression is specified only once CHAPTER 8 20 © 1999. PORT (d2. d3. Z. Navabi and McGraw-Hill Inc. q. END dee_flipflop. delay2 : TIME := 5 NS). -ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1. 1. qb <= GUARDED NOT d2 AFTER delay2. 2D 1. END BLOCK edge.

-ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d. Navabi and McGraw-Hill Inc. q1. e. ee <= '1'. c1: ff1 PORT MAP (dd. END input_output.de_flipflop (guarding). cc. BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc. • A test bench for testing the guarding architectures of de_flipflop • Testbench verifies operation of de_flipflop • After 2200 q1 is disconnected from d CHAPTER 8 21 © 1999. cc. Z. dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd. q.MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test. ee. qb1). ee. SIGNAL dd. qb : OUT BIT). END COMPONENT. qb1 : BIT. FOR c1 : ff1 USE ENTITY WORK. '0' AFTER 2200 NS. . c : IN BIT. q1.

... ... . Navabi and McGraw-Hill Inc.. ......... '1' .. ... .. ...... .. .. ... .. '0' '0' ee '0' '1' . ... '1' .. ...... .MULTIPLEXING AND DATA SELECTION TIME (ns) 0000 +1δ δ 0400 0404 0405 0800 1000 1200 1204 1205 1600 2000 2004 2005 2200 2400 2800 3000 +1δ δ 3200 +1δ δ cc '0' .. . ........... ... ..... '0' .... ....... '1' .. .. . .. .. . ....... ... .. .... '0' ....... q1 '0' ....... '0' '1' . .... '0' ..... . .. '0' .. ...... . .. . '1' '1' . .. ... qb1 '0' .. .. . '1' ............ .... dd '0' . . '1' .. . .. ...... '1' .. . .. . .. ........ .. Z. '0' '1' . ........ • Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • No transactions on the outputs after 2200 NS CHAPTER 8 22 © 1999. .. ... . .... . . . '0' . . .. . '0' ...

Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION RHS Activation GUARD 0 Driving Value Projected Output Waveform • Symbolizing guarded signal assignments • Disconnection in a guarded signal assignment • Driving value continues to be updated even if the guard expression is false CHAPTER 8 23 © 1999. .

MULTIPLEXING AND DATA SELECTION What follows concentrates on definition & applications of resolution functions • Normally several sources cannot drive a signal • Real circuits smoke. Z. • So does VHDL CHAPTER 8 24 © 1999. Navabi and McGraw-Hill Inc. .

FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a. circuit_node <= c. -ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit.basic_utilities. circuit_node <= d.ALL. z : OUT qit). Navabi and McGraw-Hill Inc. -. c. circuit_node <= b. . b. END y_circuit. • Multiple sources for a simple signal • This results in an error message CHAPTER 8 25 © 1999. d : IN qit.MULTIPLEXING AND DATA SELECTION USE WORK. z <= circuit_node. END smoke_generator. BEGIN circuit_node <= a. Z.

a happy VHDL simulator • Multiple drivers is possible only if a resolution exists • Example in hardware is "open collector" • Pull_up provides resolution CHAPTER 8 26 © 1999. . Z. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION A happy circuit.

ANDs all its drivers Performs the AND function two operand at a time Collect all ANDs and return A notation that we will use CHAPTER 8 27 © 1999. END LOOP. qit_vector. a b anding c d circuit_node • • • • The anding resolution function.MULTIPLEXING AND DATA SELECTION -. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). “AND” from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'. . END anding.USE qit. RETURN accumulate. Z. Navabi and McGraw-Hill Inc.

BEGIN circuit_node <= a. SIGNAL circuit_node : anding qit. END LOOP. RETURN accumulate. circuit_node <= c. -. Z. END anding.ALL. • • • • • • Multiple sources for a simple signal The difference is in the declaration of the left-hand-side This results in ANDing all sources Specify anding for the resolution on circuit_node Type of circuit_node is a subtype of qit ANDing simultaneously receives all drivers 28 © 1999. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i).MULTIPLEXING AND DATA SELECTION USE WORK.FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'. CHAPTER 8 . circuit_node <= d. circuit_node <= b. z <= circuit_node. END wired_and.basic_utilities. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z.MULTIPLEXING AND DATA SELECTION t4 v4 t4 v4 t4 v4 t3 v3 t3 v3 t3 t3 t2 v2 t2 v2 t2 t2 t1 v1 t1 v1 t1 t1 0 0 lhs_signal 0 • • • • Projected output waveforms and resolution functions Every assignment in a concurrent body creates a driver All assignments is a sequential body create only one driver Resolution functions act on expired values CHAPTER 8 29 © 1999. .

Z. Navabi and McGraw-Hill Inc. . it only sees the driving value CHAPTER 8 30 © 1999.MULTIPLEXING AND DATA SELECTION RHS Activation GUARD t4 v4 Driver 1 t3 v3 t2 v2 t1 v1 0 RHS Activation lhs_signal GUARD t4 v4 Driver 2 t3 v3 t2 v2 t1 v1 0 • Guarded signal assignments into resolved signals • Drivers continue to perform normal in spite of disconnection • Resolution function cannot tell the difference.

t <= i4 AND s4. t <= i2 AND s2. t <= i3 AND s3. t <= i0 AND s0. END multiple_assignments.ALL. Z.MULTIPLEXING AND DATA SELECTION USE WORK. END oring. t <= i5 AND s5. t <= i1 AND s1. BEGIN t <= i7 AND s7. SIGNAL t : oring qit. t <= i6 AND s6. • Implementing the eight-to-one multiplexer using eight concurrent assignments • ORing resolution function is used CHAPTER 8 31 © 1999. RETURN accumulate. END LOOP. .basic_utilities. Navabi and McGraw-Hill Inc.FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. z <= t. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). -.

END wire.'X'. ('0'. b).'X'. . b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.'X').'X')). BEGIN RETURN qit_wire_table (a. Navabi and McGraw-Hill Inc. Z. ('X'.MULTIPLEXING AND DATA SELECTION FUNCTION wire (a. In1: In2: 0 1 Z X 0 0 X 0 X 1 X 1 1 X Out Z 0 1 Z X X X In1 X Out X In2 X • The wire function for modeling wiring two qit type nodes.'0'.'Z'.'X').'X'.'X').'1'.'1'. • Input-output mapping • Circuit notation CHAPTER 8 32 © 1999. ('X'.'1'.

BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. END wiring. RETURN accumulate. FUNCTION wiring ( drivers : qit_vector) RETURN qit. TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. SUBTYPE wired_qit IS wiring qit. . drivers(i)). END LOOP. Z.MULTIPLEXING AND DATA SELECTION FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'. Navabi and McGraw-Hill Inc. ‘Z’ will be returned • To declare an array of this resolution CHAPTER 8 33 © 1999. • The wiring resolution function for qit type operands • Necessary declarations for visibility of the wiring resolution function and its related types and subtypes • If no drivers exist.

Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. END LOOP. '0' is returned Necessary type and subtype definitions for the basic_utilities package Example signal declaration © 1999. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). RETURN accumulate. FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. Z. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. END oring. SUBTYPE ored_bit IS oring BIT. CHAPTER 8 34 . • • • • • • Another complete example The oring resolution function for the BIT type operands OR for BIT is already defined If no drivers. SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 ).

. Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • Will now model this circuit • An NMOS eight-to-one multiplexer • The CMOS version uses transmission gates instead of pass transistors CHAPTER 8 35 © 1999. Z.

MULTIPLEXING AND DATA SELECTION si ii t bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii. END BLOCK. Z. A block statement modeling a transmission gate • Disconnection is realized by block statements • If all drivers are disconnected actual hardware returns to 'Z' CHAPTER 8 36 © 1999. Navabi and McGraw-Hill Inc. .

t <= GUARDED i6. END multiple_guarded_assignments. .MULTIPLEXING AND DATA SELECTION USE WORK. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. z <= t. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. -. t <= GUARDED i3. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. ii is disconnected from t if si is '0' Use BUS to implement this behavior Default in wire function is specified as 'Z' This default is used if wiring is called with Null Last disconnection causes call to wiring with Null CHAPTER 8 37 © 1999. t <= GUARDED i0. Z. t <= GUARDED i1.FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS SIGNAL t : wired_qit BUS. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. • • • • • Each ii connects to t if si is '1'.basic_utilities. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. t <= GUARDED i2.ALL. t <= GUARDED i5. Navabi and McGraw-Hill Inc. t <= GUARDED i7. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. t <= GUARDED i4.

Z. . Navabi and McGraw-Hill Inc.MULTIPLEXING AND DATA SELECTION • An NMOS half-register with multiplexed input • Modeling this circuit must take inverter input capacitance into account • t holds charge if all are disconnected • Circuit shows a register effect CHAPTER 8 38 © 1999.

END guarded_assignments. t <= GUARDED i2. s1. b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK. t <= GUARDED i7. b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK. s7. s4. i4. s5. i0 : IN qit. i1.FROM PACKAGE USE: qit. b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK. END multiplexed_half_register. b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK. s2. CHAPTER 8 . i6. t <= GUARDED i1. b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK. i2. i3. -ARCHITECTURE guarded_assignments OF multiplexed_half_register IS SIGNAL t : wired_qit REGISTER. t <= GUARDED i4. t <= GUARDED i6.ALL. -.MULTIPLEXING AND DATA SELECTION USE WORK. BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK. z : OUT qit ). t <= GUARDED i0. t <= GUARDED i5. i5. z <= NOT t AFTER 8 NS. wired_qit ENTITY multiplexed_half_register IS PORT (i7.basic_utilities. Z. s0 : IN qit. s6. Navabi and McGraw-Hill Inc. b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK. b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK. s3. • • • • • • Use REGISTER to model retaining of last value No call is made to wiring upon last disconnection BUS and REGISTER are kind specification Signals with kind are guarded signals Guarded signals must be used on LHS of guarded assignments Ok to use unguarded signals on LHS of guarded assignments 39 © 1999. t <= GUARDED i3.

END. even if a static value remains (if unguarded LHS) CHAPTER 8 40 © 1999. --------------------------------------------------------------------------------------------- BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values. RHS Activation guard_expression t4 v4 Driver i t3 v3 t2 v2 t1 v1 0 guarded_lhs_signal • Turning off drivers from guarded signals • Guard expression controls driver contribution to the resolution function • Continuous contribution stops. Navabi and McGraw-Hill Inc. END. .MULTIPLEXING AND DATA SELECTION BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values. Z.

but holds static value at the time of disconnection • For unguarded. REGISTER kind. disconnection disconnects.MULTIPLEXING AND DATA SELECTION Before Last Disconnection After Last Disconnection v v f(v) v null v f(null) (a) BUS Kind v v f(v) v null f(v) (b) REGISTER Kind v v f(v) v v f(v) (c) Not Guarded Last disconnections: BUS kind. last disconnection does not call the resolution function Unguarded. last disconnection calls resolution function with Null REGISTER. Z. . last disconnection is no different than others CHAPTER 8 41 © 1999. Navabi and McGraw-Hill Inc. unguarded • • • • Disconnection disconnects if guarded BUS kind.

MULTIPLEXING AND DATA SELECTION USE WORK. Navabi and McGraw-Hill Inc. Z. s : IN qit_vector. not REGISTER CHAPTER 8 42 © 1999.ALL. -ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j). z : OUT wired_qit BUS). END GENERATE. wired_qit ENTITY mux_n_to_1 IS PORT (i. -. qit_vector.FROM PACKAGE USE: qit.basic_utilities. • • • • mutliple_guarded_assignments architecture of the mux_n_to_1 A general n-bit multiplexer Ports can be resolved signals BUS kind can also be specified. END mux_n_to_1. END multiple_guarded_assignments. END BLOCK. .

END input_output. SIGNAL ii. "Z100" AFTER 20 US. -ARCHITECTURE input_output OF mux_tester IS COMPONENT mux PORT (i. mm : mux PORT MAP (ii. ss <= "0010" AFTER 05 US. zz). Z. z : OUT wired_qit BUS). "000Z" AFTER 25 US.mux_n_to_1 (multiple_guarded_assignments). ENTITY mux_tester IS END mux_tester. "0011" AFTER 30 US. END COMPONENT.basic_utilities. FOR ALL : mux USE ENTITY WORK. BEGIN ii <= "1010" AFTER 10 US. SIGNAL zz : qit. ss : qit_vector (3 DOWNTO 0) := "0000".ALL. Navabi and McGraw-Hill Inc. s : IN qit_vector.MULTIPLEXING AND DATA SELECTION USE WORK. "1100" AFTER 15 US. • A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1 • This entity is used as a four bit multiplexer CHAPTER 8 43 © 1999. ss. .

..... ................ "Z100" ... "1010" . .. ..... '1' .... . Z.......... ..MULTIPLEXING AND DATA SELECTION TIME (ns) 00000 +1δ δ 05000 +1δ δ 10000 +1δ δ 15000 +1δ δ 20000 +1δ δ 25000 +1δ δ 30000 +1δ δ ii(3:0) "0000" .............. "1100" ...... . 'X' .. '1' • Simulation results of the input_output architecture of the mux_tester • Simulation produces 'X' for two conflicting enabled inputs • Produces 'Z' when no inputs are enabled CHAPTER 8 44 © 1999.............. '1' . .......... .. . '0' . .. '0' .... zz '0' 'Z' . "0010" .... ... ss(3:0) "0000" . "0011" .. Navabi and McGraw-Hill Inc.... "000Z" . ......... ..........

Navabi and McGraw-Hill Inc. . then will start using resolved. and other signal types • Several examples will follow CHAPTER 8 45 © 1999. Z.MULTIPLEXING AND DATA SELECTION Remaining issues: Disconnection Right and left INOUT More issues on resolutions. guarded. guarded signals & resolved signals will de discussed • Will discuss other issues.

SIGNAL t : wired_qit. Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE • Specify disconnection in the declaration • Use ALL for all signals of that type • Use OTHERS if some specified otherwise CHAPTER 8 46 © 1999.. SIGNAL t : wired_qit. . t <= GUARDED ii AFTER n NS.. . BEGIN . .MULTIPLEXING AND DATA SELECTION si ii ARCHITECTURE . DISCONNECT t : wired_qit AFTER 6 NS. Z. END ARCHITECTURE. Navabi and McGraw-Hill Inc. .... . BEGIN ... it takes n NS for t to get ii ARCHITECTURE . . t <= GUARDED ii AFTER n NS.. t Connection is timed: After connection. . END ARCHITECTURE.

• Resolved signals on right and left hand sides • What you get is not what you put in • Others contribute to a resolved signal CHAPTER 8 47 © 1999.MULTIPLEXING AND DATA SELECTION Value used on the right hand side Value placed on driver of a t4 v4 t3 v3 t2 v2 t1 v1 0 Other Drivers a <= a AND b AFTER delay. . Z. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. Z. x a z oring y b • Connecting INOUT ports require resolved signals • There are two drivers for each interconnection CHAPTER 8 48 © 1999. .two PORT MAP (b. ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT. . z). . . y : INOUT BIT) … -ENTITY three IS END three.MULTIPLEXING AND DATA SELECTION ENTITY one (a : IN BIT. c2 : ENTITY WORK.one PORT MAP (a. . END connecting. z). . x : INOUT BIT) … ENTITY two (b : IN BIT. BEGIN c1 : ENTITY WORK.

Z.STATE MACHINE DESCRIPTION Will use resolutions and guarded assignments in several examples • • • • State names indicate detected sequences Use resolutions & guarded blocks A simple 1011 Mealy detector A block statement for each state CHAPTER 8 49 © 1999. . Navabi and McGraw-Hill Inc.

clk : IN BIT. END BLOCK s1. ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset. Navabi and McGraw-Hill Inc.STATE MACHINE DESCRIPTION ENTITY detector IS PORT (x. got101). z : OUT BIT). TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state. SIGNAL current : one_of state REGISTER := reset. FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT). END singular_state_machine. got10. END BLOCK s4. • • • • VHDL description of 1011 detector Only one simultaneous active state Current receives four concurrent assignments Current must be resolved. use one_of CHAPTER 8 50 © 1999. END BLOCK clocking. got1. Z. END BLOCK s3. s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10. z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'. END detector. END BLOCK s2. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset. s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset. END one_of. . s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1.

END BLOCK s1. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. . s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s <= GUARDED "0000". s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. END BLOCK s3. END BLOCK s4. goes to 4 when x = '1' CHAPTER 8 51 © 1999. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. END BLOCK s2.FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000". s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'.ALL. -. • • • • • VHDL description of 1011 detector More than one state can simultaneously be active The last description does not allows multiple active states To remedy: use a signal for each state State 3 : goes to 1 when x = '0'. END multiple_state_machine. BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'.basic_utilities. END BLOCK clocking. z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'.STATE MACHINE DESCRIPTION USE WORK. Z. Navabi and McGraw-Hill Inc. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'.

FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000".. • State 3 : goes to 1 when x = '0'. goes to 4 when x = '1' • S must be resolved vector REGISTER kind • S <= GUARDED "0000". END BLOCK s3.STATE MACHINE DESCRIPTION USE WORK. Causes removal of retained value upon last disconnection CHAPTER 8 52 © 1999.basic_utilities. END BLOCK clocking. END BLOCK s2.. END multiple_state_machine.ALL. . -. s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'. s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'.. Z. . BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN .. s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'. s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'. Navabi and McGraw-Hill Inc. s <= GUARDED "0000".

TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. and s arrays SIGNAL o : ored_bit REGISTER. BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i. . s (i) <= GUARDED '0'. z <= o. s(next_val(i. out_val. Z. TYPE out_table IS ARRAY (1 TO n.'1')) <= GUARDED '1' WHEN x='1' ELSE '0'. -ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. GENERIC (n : INTEGER). o <= GUARDED out_val(i.'0')) <= GUARDED '1' WHEN x='0' ELSE '0'. END oring.Fill in next_val.STATE MACHINE DESCRIPTION ENTITY detector_m IS PORT (x. BIT) OF INTEGER. Navabi and McGraw-Hill Inc. END BLOCK si. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). -. END BLOCK clocking. TYPE next_table IS ARRAY (1 TO n. END multiple_moore_machine_1. x). • • • • A generic state machine A Moore sequence detector Specify transitions & outputting in constant tables Allows multiple machines in one CHAPTER 8 53 © 1999. SUBTYPE ored_bit IS oring BIT.clk : IN BIT. END GENERATE. END detector_m. END LOOP. RETURN accumulate. z : OUT BIT). BIT) OF BIT.

1 -('0' .STATE MACHINE DESCRIPTION ------------------------------------------------------------------Tables for programming the configurable Moore description -------------------------------------------------------------------. 6) ). '0'). --S5: == z=0. --S4: -> S1. S1 -(5 . 6). x=1 -CONSTANT next_val : next_table := ( (1 . . --S2: -> S1. S2 -(1 . --S2: == z=0. '0'). --S5: -> S5. S6 -(5 .Next States: ----x=0. --S4: == z=1.Output Values: ----x=0. 0 -('0' . Z. 4). Navabi and McGraw-Hill Inc. ---------------------------------------------------------------------------------------------------------------------------------- • • • • Next state and output tables The next_val constant holds next state values The out_val constant holds the output values on the z output Initial starting states are set to '1' in the s vector CHAPTER 8 54 © 1999. 2). S4 -(1 .--S6: == z=1. 1 ----. '0'). '1'). S3 -(1 . '1') ). --S3: -> S1. 3).Initial Active States: -SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010". --S1: == z=0.--S6: -> S5. --S1: -> S1. S6 -----. 0 -('0' . x=1 -CONSTANT out_val : out_table := ( ('0' . '0'). 0 -('1' . 0 -('1' . 1). --S3: == z=0.

OPEN COLLECTOR GATES

VCC

a y b

GND

• • • •

Open collector NAND gate A two-input NAND gate, TTL 74LS03 SSI package Resolution functions are used in bussing Will use open collector to illustrate

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;

• VHDL description of a NAND gate with open collector output • Use qit type • Output is ‘Z’ and not ‘1’

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OPEN COLLECTOR GATES
ENTITY test_nand2 IS END test_nand2; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; TIME BEGIN (ns) aa bb assign_bits (aa, "qit_data", 500 NS); 0000 '0' '0' assign_bits (bb, "qit_data", 750 NS); 0010 ... ... c1: nand2 PORT MAP (aa, bb, yy); 1000 '1' ... 1500 ... '1' END input_output;
1512 2500 2510 3000 3012 3750 3760 4000 4500 4512 5000 5010 5500 5512 6000 6010 6750 6762 7500 7510 8250 8262 ... '0' ... 'Z' ... ... ... '0' '1' ... '0' ... 'Z' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... 'Z' ... ... ... ... ... '0' ... '1' ... '0' ... 'Z' ...

yy '0' 'Z' ... ... '0’ ... 'Z' ... '0' ... 'Z' ... ... '0' ... 'Z' ... '0' ... 'Z' ... '0' ... 'Z' ... '0'

• Testing the open-collector NAND gate • Test bench uses external data file • Output is either ‘0’ or ‘Z’, never ‘1’

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;

• VHDL description of TTL 74LS03 • Contains four open collector NAND gates • Will use in a design

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OPEN COLLECTOR GATES

a1 b1

a4 aa pull_up_1 y1 g4 a2 bb b2 pull_up_3 y4 yy g2 pull_up_2 y2 g3 a3 b3 g1 b4

y3

yy = (aa' . bb)’ . (bb' . aa)' = ( aa ⊕ bb )'

• • • •

Implementing XNOR logic using open collector NAND gates Using 74LS03 for implementing an XNOR pull_up3 has two drivers pull_up1 and pull_up2 must be turned to ‘0’, ‘1’ logic

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OPEN COLLECTOR GATES

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US, '0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;

• Wiring and testing XNOR function implemented by four open collector AND gates • pull_up_1 and pull_up_2 turn 0,Z to 0,1 • anded_qit resolution function implements wired logic

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OPEN COLLECTOR GATES
TIME (us) 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 aa '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' 'Z' 'Z' 'Z' 'Z' 'Z' 'Z' bb '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' 'Z' pull_up_1 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' pull_up_2 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' pull_up_3 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0'

• Results are observed at 2 us intervals • Simulation shows XNOR implementation • Pull up resolutions turn gate output 'Z' values to '1'

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THREE STATE BUSSING

u1 :

alu

u2 :

reg1

u3 : bus1 8

8 8

bus a

u4 :

unit1

u5 :

unit2

• • • •

A bussing system (bus_sys) Will use resolution functions for describing it A very common hardware for RT level descriptions Some components have three-state outputs some do not

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THREE STATE BUSSING

ENTITY alu IS PORT (… ; zout : out qit_vector (7 DOWNTO 0)); END alu; -ENTITY reg1 IS PORT (… ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); …); END unit1; -ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); …); END unit2;

• Interface of bus sources and destinations • Wired_qit_vector is used for those with three-state outputs • Connection of others must be through three-state constructs

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THREE STATE BUSSING

ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (…; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (…; busa); … u3 : busa <= bus1; … unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;…); … u5 : ENTITY WORK.unit2 PORT MAP (busa;…); … END partial;

• • • •

Partial VHDL description for bussing system example reg1 with three-state output directly drives the bus aluout goes through three-state constructs All required hardware structures are explicitly coded

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Std_logic BUSSING

std_ulogic for “standard unresolved logic” A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms

• Std_logic provides multi-value logic for most applications • No need for new user types • Most designers use the resolved type

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Navabi and McGraw-Hill Inc. 4-bit Count output Reset input • Seen dataflow primitives • Use dataflow for system description • A sequential comparator example CHAPTER 8 66 © 1999. .A GENERAL DATAFLOW CIRCUIT 8-bit Parallel data Count equal sequential data on parallel input lines. Z.

Z. SIGNAL count : BIT_VECTOR (3 DOWNTO 0).ALL. int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0). RETURN t. -. VARIABLE t : BIT_VECTOR (x'RANGE). END sequential_comparator. BEGIN bin2int (x. SIGNAL buff : BIT_VECTOR (7 DOWNTO 0). END IF. IF i >= 2**x'LENGTH THEN i := 0. Navabi and McGraw-Hill Inc. BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data.FROM PACKAGE USE: bin2int. matches <= count. t). int2bin (i. END inc. reset : IN BIT. matches : OUT BIT_VECTOR (3 DOWNTO 0)).A GENERAL DATAFLOW CIRCUIT USE WORK. .basic_utilities. i := i + 1. clk. -ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. i). count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count. END BLOCK. • • • • Dataflow description of the sequential comparator circuit inc function is unconstrained Save old data in buff Compares old and new CHAPTER 8 67 © 1999. END dataflow.

.. .. ...... .... "0000" ........ ........................A GENERAL DATAFLOW CIRCUIT TIME (ns) 0000 +1δ δ 0200 0500 1000 +1δ δ 1200 1500 1700 2000 +1δ δ 2500 3000 +1δ δ +2δ δ 3200 3500 3700 4000 +1δ δ 4200 4500 5000 +1δ δ 5500 6000 +1δ δ +2δ δ 6500 7000 +1δ δ +2δ δ 7500 8000 +1δ δ +2δ δ 8500 reset '0' .... ........ .... ... .................. ..... ....... . . ...... .............. "0001" . ... . .......... ...... ... .... ......... .. ..... "11110101" ......... count(3:0) "0000" ... .. "0000" . matches "0000" "0000" ....... "10010110" . ....... ........ ........... ... .... ... .. . "0001" ............. ..... ..... .. ... ......... ...... . "11111110" ... '1' '0' ........ ........... • matches shows count of matching data CHAPTER 8 68 © 1999....... . . ............ .... ........ ... .. '1' .. ..... . ..... "10010110" ......... ................ "11111110" .. ... ......................... ..... "0001" ... .. "10010110" ........ .. ....... ....... "0100" . ........... ..... "00010001" . ........ .................. .... .. . buff(7:0) "00000000" . "0010" ............. .......... ...... ............ ...... ...... . ......... ..... "10010110" ....................... '1' '0' . . "0011" .. ......... .. .......... "11110101" ........ ... ... .. ...... "00010001" ....... "11111110" .. ........... ...... ..... . '1' '0' ............................ .... ............................... .... "01010100" . .................. ..... Z....... ....... .......... '1' '0' .... ............. ......... "0001" .... ... Navabi and McGraw-Hill Inc................ . .. ........................... ..... "0010" ...... ........ '1' '0' .... "01010110" . . '1' '0' ............... ...... ... ................. '0' ...... '1' data(7:0) "00000000" ........ .... "0100" ... . '1' .............................. . "10010110" .............. ... . .. ... ........... . ... clk '0' . ...... ......... ........... ....... .. ... '0' ...... ......... .. .. . "0011" ............. ... ...... .... ..... ...... .... .

-FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT. SUBTYPE wired_qit IS wiring qit.UPDATING BASIC UTILITIES PACKAGE basic_utilities IS . . . Z. SUBTYPE anded_bit IS anding bit. TYPE anded_qit_vector IS ARRAY (NATURAL RANGE <>) OF anded_qit. TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit. -FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR. Navabi and McGraw-Hill Inc. b : qit) RETURN qit. TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit. TYPE anded_bit_vector IS ARRAY (NATURAL RANGE <>) OF anded_bit. SUBTYPE anded_qit IS anding qit. FUNCTION wire (a. SUBTYPE ored_qit IS oring qit. -FUNCTION oring ( drivers : qit_vector) RETURN qit. -FUNCTION wiring ( drivers : qit_vector) RETURN qit. END basic_utilities. CHAPTER 8 69 © 1999. TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit. SUBTYPE ored_bit IS oring BIT. -FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT. -FUNCTION anding ( drivers : qit_vector) RETURN qit.

'X'. FUNCTION wire (a.'X'.'1'. END LOOP. END anding. FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'.'1'. END LOOP.'0'. drivers(i)). FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i).'X'). END oring. RETURN accumulate. .'Z'. END LOOP.'X').'X'. RETURN accumulate.'X')). Z. FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'.'X'). CHAPTER 8 70 © 1999. ('X'. Navabi and McGraw-Hill Inc. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0'.UPDATING BASIC UTILITIES PACKAGE BODY basic_utilities IS . .'1'. BEGIN RETURN qit_wire_table (a. ('X'. ('0'. b). END wiring. BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate. . RETURN accumulate. END wire.

Z. • Resolution functions and inc function added to basic_utilities CHAPTER 8 71 © 1999. BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i). RETURN accumulate. FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'. END inc. END IF. FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER. i := i + 1. t). int2bin (i. RETURN accumulate. END LOOP. RETURN t. VARIABLE t : BIT_VECTOR (x'RANGE). BEGIN bin2int (x. END oring. . BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i). Navabi and McGraw-Hill Inc. END basic_utilities.UPDATING BASIC UTILITIES FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'. END LOOP. i). IF i >= 2**x'LENGTH THEN i := 0. END anding.

or turning off a source. Z. Navabi and McGraw-Hill Inc. This prepared the way for describing resolution functions. and guarded signals. Guarded signal assignment and the concept of disconnection. and resolution functions. A resolution function for a node can be written to match its technology-dependent behavior. . • End Of Chapter 8 CHAPTER 8 72 © 1999.SUMMARY This chapter presented signal assignment. which are considered to be among the most important hardware related constructs in the VHDL language. The resolution functions developed in this chapter are typical of the way buses function in a digital system. multiple drivers of signals. in general a resolved signal is a better representation of a circuit node. guarded assignments. Although VHDL only requires resolution of signals with multiple concurrent sources. were presented.

2 Two Phase Clocking 9.1 Top Level Partitioning 9.6 Postponed Processes 9.4 A First Process Example 9.5 MSI BASED DESIGN 9.2.3 Simulation Report 9.5.CHAPTER 9 BEHAVIORAL DESCRIPTION OF HARDWARE 9.1.7 Passive Processes 9. Z.1.2 Concurrent Assertion Statements 9.3.3 Design Implementation 9.4 Interface Handshaking 9.5 Syntax Details of Process Statements 9.4.2 Statement Part of a Process 9.1.4.1 Basic Screen Output 9.3.1 Sequential Use of Assertion Statements 9.2 ASSERTION STATEMENT 9. Navabi and McGraw-Hill Inc.1.2 Description of Components 9.1 PROCESS STATEMENT 9.3 SEQUENTIAL WAIT STATEMENTS 9.2.1.1 Declarative Part of a Process 9.4 FORMATTED ASCII I/O OPERATIONS 9.2 A Display Procedure 9.4.3.5.3 Sensitivity List 9.3 Implementing Handshaking 9.1.8 Behavioral Flow Control Constructs 9.5. .3.1.6 SUMMARY • • • • • • Constructs for sequential descriptions Process statement is a key construct Assertion for behavioral checks Handshaking constructs Timing control Formatted I/O CHAPTER 9 1 © 1999.1.1 A Behavioral State Machine 9.

PROCESS STATEMENT
Concurrent process statement PROCESS Always alive process declarative_part (non-signal) ...

BEGIN

Always active process statement_part (sequential) ...

END PROCESS;

Process statements describe hardware without much hardware details

• • • •

PROCESS: A concurrent statement, enclosing sequential statements Declarative part contains only variables and constants Use only sequential constructs

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PROCESS BEGIN Reapets forever,
S e q u e n t i a l

In zero time,

Unless suspended

END PROCESS;

• Unless a sequential body is suspended • It executes in zero real and delta time • It repeats itself forever

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ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;

• • • • •

First: a is scheduled for x Next: b is scheduled for y x and y receive values at the same time Both assignments occur a delta later Zero time between both scheduling

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ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;

• First: a is scheduled for x • Next: b is scheduled for y • y receives b sooner than x receiving a

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ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;

• • • • •

Assume x_sig is initially '0' Assignment of '1' to x_sig takes a delta Action_2 will be taken Variable x_var had to be declared inside the Process statement If x_var was used instead of x_sig, action_1 would be taken

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PROCESS STATEMENT

ARCHITECTURE … BEGIN … a <= b; … c <= d; … END …;

ARCHITECTURE … BEGIN … PROCESS (b) … a <= b; END PROCESS; … c <= d; … END …;

Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation Any signal assignment can be expressed by a process statement

• • • • • •

Can use a signal assignment in a sequential body On the left: events on b cause assignment Process is executed when an event occurs on b On the right: (b) is sensitivity list of process Process statement executes only once for every event on b Process suspends till next event on b occurs
© 1999, Z. Navabi and McGraw-Hill Inc.

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PROCESS STATEMENT

R 1D Q

C1 S

Q

A flip-flop will demonstrate assignments and flow in process statements

• Have modeled flip-flops with concurrent statements • A process statement is a powerful construct for such descriptions

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• • • •

Three concurrent processes dff process is sensitive to (rst, set, clk) Internal state receives proper value Events on state cause events on q and qb

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ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;

• Single process assigns values to q and qb • This description eliminates the δ delay of the last description • Less precise timing

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TIME (NS) 0 +1δ δ 6 200 206 +1δ δ 500 1000 1200 1400 1406 +1δ δ 1500 2000 2200 2400 2500 2506 +1δ δ 3000 3300 3500 3506 +1δ δ 4000

ss '0' ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

rr '0' ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ...

cc '0' ... ... ... ... ... '1' '0' ... ... ... ... '1' '0' ... ... '1' ... ... '0' ... '1' ... ... '0'

dd '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ...

q1 '0' ... ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ...

q2 '0' ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ... ...

qb1 '0' '1' ... ... ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ...

qb2 '0' ... '1' ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ... ...

• Simulation run compares flip-flop descriptions • The 3 process description has a δ delay • However, potential of more precise timing

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ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;

• This example uses a record for delay and flip-flop values • Logic value and delay are assigned to variables • Assignment to variables are done in zero time without the δ delay

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sensitivity_list variable declaration process declarative part process statement ELSEIF rst = ‘1’ THEN state := ‘0’. END PROCESS dff. Navabi and McGraw-Hill Inc. Z. . clk) VARIABLE state : BIT := ‘0’ BEGIN IF set = ‘1’ THEN state := ‘1’. qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3. ELSEIF clk = -‘1’ AND clk’EVENT THEN state := d. q <= state AFTER (sq_delay + rq_delay + cq_delay)/3. sequential statement process statement part sequential statement sequential statement • Syntax details include sensitivity list CHAPTER 9 13 © 1999.PROCESS STATEMENT dff: PROCESS (rst. set. END IF.

. Z. becomes active becomes active clk set rst t1+1δ δ δ t1+2δ t1+3δ δ • Postponed process • Wait until the last event in a real time increment • Signal assignments can become postponed CHAPTER 9 14 © 1999. END. Navabi and McGraw-Hill Inc. . . dff : POSTPONED PROCESS(rst. . clk) BEGIN . . set.PROCESS STATEMENT dff : PROCESS(rst. clk) BEGIN . set. END.

qb <= NOT sd. rq_delay. END behavioral. q. END RECORD. 0 NS). • A passive process statement may appear in the entity statement part • Cannot make assignments to signals • This models the same flip-flop CHAPTER 9 15 © 1999.state AFTER sd. qb : OUT BIT). delay : TIME. set. ENTITY d_sr_flipflop IS GENERIC (sq_delay. END IF. sq_delay). END PROCESS dff. set. BEGIN dff: PROCESS (rst. SHARED VARIABLE sd : bit_time := ('0'.delay. cq_delay). Navabi and McGraw-Hill Inc.PROCESS STATEMENT PACKAGE bt IS TYPE bit_time IS RECORD state : BIT. cq_delay : TIME := 6 NS). ELSIF rst = '1' THEN sd := ('0'. -USE WORK. rq_delay).delay. END PACKAGE bt.state AFTER sd. clk) BEGIN IF set = '1' THEN sd := ('1'. rst. ELSIF clk = '1' AND clk'EVENT THEN sd := (d. PORT (d. clk) BEGIN q <= sd. set.ALL. -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst. END ENTITY. END PROCESS dff_arch. clk : IN BIT.bt. . Z.

. NEXT loop_label WHEN condition.PROCESS STATEMENT long_runing : LOOP .. END IF. Navabi and McGraw-Hill Inc... IF x = 25 THEN EXIT. END LOOP long_runing. • • • • Loop is a sequential statement Example runs forever unless exited EXIT & NEXT control flow of loops EXIT & NEXT can be conditioned CHAPTER 9 16 © 1999. . Z.. EXIT WHEN condition.

END LOOP loop_2. . sequential_statement_4.. sequential_statement_2. . sequential_statement_6.. Z. • • • • Conditional Next Statements in a Loop FOR.. WHILE are controlled forms of loop Can still use NEXT and EXIT The above NEXT statement causes looping to continue with statements 1 17 © 1999... .. loop_2 : WHILE j <= 90 LOOP . sequential_statement_5.. sequential_statement_3..... END LOOP loop_1...PROCESS STATEMENT loop_1 : FOR i IN 5 TO 25 LOOP ... sequential_statement_1.. . . . Navabi and McGraw-Hill Inc. CHAPTER 9 . NEXT loop_1 WHEN condition_1.

ASSERTION STATEMENT ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level. . Z. • • • • Use assert to flag violations Use assert to report events Can be sequential or concurrent Severity: FAILURE ERROR WARNING NOTE CHAPTER 9 18 © 1999. Navabi and McGraw-Hill Inc. OTHERWISE REPORT "reporting_message". MAKE SURE THAT assertion_condition IS TRUE. OTHERWISE REPORT "reporting_message" AND TAKE THE ACTION AT THIS severity_level. MAKE SURE THAT false IS TRUE. REPORT “reporting_message” SEVERITY severity_level.

• Conditions are checked only when process is activated • Make sure that set='1' AND rst='1' does not happen • Severity NOTE issues message CHAPTER 9 19 © 1999. . ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. END PROCESS dff. q <= state. set. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. Navabi and McGraw-Hill Inc. END behavioral. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. Z. BEGIN dff: PROCESS (rst.ASSERTION STATEMENT ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. IF set = '1' THEN state <= '1' AFTER sq_delay. END IF. qb <= NOT state.

• Good conditions may be too many to list • Good conditions = NOT (Bad conditions) • Easier to use NOT of unwanted cases CHAPTER 9 20 © 1999. Z.ASSERTION STATEMENT ASSERT Good conditions REPORT Violation of good conditions SEVERITY Level. ASSERT NOT things_that_should_not_happen REPORT a_message_that_bad_things_have_happened SEVIRITY action_to_take. . Navabi and McGraw-Hill Inc.

.. • ASSERT hold_violation check REPORT.. . Navabi and McGraw-Hill Inc. Z. CHAPTER 9 21 © 1999..ASSERTION STATEMENT clock setup time data hold time Setup and Hold time checks use assert statement and signal attributes • Use ASSERT to check setup and hold • ASSERT set_up_violation check REPORT.

. Navabi and McGraw-Hill Inc. Z.ASSERTION STATEMENT clock setup time data hold time Setup Check in English When (clock changes from zero to 1). check for stable data • Check is placed after clock changes CHAPTER 9 22 © 1999. if (data input has not been stable at least for the amount of the setup time). Setup Check in VHDL (clock = '1' AND NOT clock'STABLE) AND (NOT data'STABLE (setup_time)) • When the clock changes. then a setup time violation has occurred.

ASSERTION STATEMENT clock setup time data hold time Hold Check in English When (there is a change on the data input) if the (logic value on the clock is '1') and the (clock has got a new value more recent than the amount of hold time). . check for stable clock • Check is placed after data changes CHAPTER 9 23 © 1999. Hold Check in VHDL (data'EVENT) AND (clock = '1') AND (NOT clock'STABLE (hold_time)) • When data changes while clock is '1'. then hold time violation has occurred. Navabi and McGraw-Hill Inc. Z.

PORT (d. clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE. setup. set. Z. qb : OUT BIT). q <= state. -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'. ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay. rq_delay. hold : TIME := 4 NS). qb <= NOT state.ASSERTION STATEMENT ENTITY d_sr_flipflop IS GENERIC (sq_delay. . BEGIN dff: PROCESS (rst. END behavioral. ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING. clk : IN BIT. BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING. q. set. END PROCESS dff. rst. END IF. • Using assertion statements for illegal Set-Reset combinations • Setup and Hold time violations • Concurrent and sequential assertion statements CHAPTER 9 24 © 1999. cq_delay : TIME := 6 NS. Navabi and McGraw-Hill Inc. IF set = '1' THEN state <= '1' AFTER sq_delay. ELSIF rst = '1' THEN state <= '0' AFTER rq_delay. END d_sr_flipflop.

Used for handshaking and delay modeling WAIT FOR real_time. WAIT UNTIL a_signal_is_true.SEQUENTIAL WAIT STATEMENTS WAIT FOR waiting_time. WAIT statements for flow control of sequential statements • • • • • • Sequential statements. WAIT UNTIL event makes condition true. WAIT UNTIL waiting_condition. Is the same as WAIT ON the_signal UNTIL expression_is_true. WAIT FOR 0 NS. WAIT ON waiting_sensitivity_list. WAIT FOR. WAIT UNTIL expression_with_signal_and_variable_is_true. WAIT. Navabi and McGraw-Hill Inc. --"a long time" WAIT ON (event on a signal). CHAPTER 9 25 . --"forever" © 1999. Z. WAIT. Is the same as WAIT ON a_signal UNTIL signal_is_true. WAIT ON some_event UNTIL a_condition FOR some_time.

END ARCHITECTURE. Navabi and McGraw-Hill Inc... b. END ARCHITECTURE.. END PROCESS.. c). BEGIN … … … WAIT ON (a.SEQUENTIAL WAIT STATEMENTS ARCHITECTURE … … BEGIN … PROCESS . BEGIN … … … … END PROCESS. . c) . b. A process with sensitivity behaves as A process with WAIT ON at the end • WAIT ON at the end is equivalent to using sensitivity list • Cannot use WAIT in a process with sensitivity list • WAIT suspends a Process CHAPTER 9 26 © 1999. ARCHITECTURE … … BEGIN … PROCESS (a. Z.

Z.SEQUENTIAL WAIT STATEMENTS Several examples will demonstrate WAIT statements in processes • A Moore 1011 detector • Can use WAIT in a Process statement CHAPTER 9 27 © 1999. Navabi and McGraw-Hill Inc. .

• • • • VHDL Description of the 1011 Sequence Detector Using Process and Wait Statements Each choice corresponds to a state Each state can be independently timed. z : OUT BIT). got1011). ELSE current <= got10. END PROCESS. END IF. IF x = '1' THEN current <= got1. . IF x = '0' THEN current <= got10. ELSE current <= got1. IF x = '1' THEN current <= got1011. END moore_detector.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. WAIT FOR 1 NS. BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'. IF x = '1' THEN current <= got1. got1. z <= '0'. WAIT UNTIL clk = '1'. got101. got10. ELSE current <= got10. END IF. Navabi and McGraw-Hill Inc. Z. WHEN got1 => WAIT UNTIL clk = '1'. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. WHEN got10 => WAIT UNTIL clk = '1'. IF x = '1' THEN current <= got101. clk : IN BIT. END CASE. ELSE current <= reset. SIGNAL current : state := reset. END IF. WHEN got1011 => z <= '1'. WHEN got101 => WAIT UNTIL clk = '1'. END IF. ELSE current <= reset. and clocked CHAPTER 9 28 © 1999. END IF. END behavioral_state_machine.

-ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. Navabi and McGraw-Hill Inc. got1. BEGIN PROCESS BEGIN CASE current IS . END behavioral_state_machine. clk : IN BIT. got101. IF x = '0' THEN current <= got10. END IF. . END PROCESS.. • • • • • WAIT for rising edge of clk Assign new state to current Wait for transaction on current Can use WAIT ON current 'TRANSACTION instead Timing check flexibility in each state CHAPTER 9 29 © 1999. got1011). z : OUT BIT). SIGNAL current : state := reset.. ELSE current <= got1. Z. END CASE. WAIT FOR 1 NS. WHEN got1 => WAIT UNTIL clk = '1'. . z <= '0'. END moore_detector... got10.

Navabi and McGraw-Hill Inc. END IF. z : OUT BIT). • A simple state machine description • Not much timing flexibility • Allows a single clock • But easy and covers most cases CHAPTER 9 30 © 1999. WHEN got101 => IF x = '1' THEN current <= got1011. -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset. WHEN got10 => IF x = '1' THEN current <= got101. . got10. WHEN got1 => IF x = '0' THEN current <= got10. END IF. clk : IN BIT. got1. z <= '1' WHEN current = got1011 ELSE '0'. END PROCESS. END IF. END CASE. ELSE current <= reset. ELSE current <= reset. END moore_detector. WHEN got1011 => IF x = '1' THEN current <= got1. ELSE current <= got10. END IF. END IF. BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1.SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x. ELSE current <= got10. END behavioral_state_machine. Z. END IF. ELSE current <= got1. got1011). SIGNAL current : state := reset. got101.

Navabi and McGraw-Hill Inc. Z.SEQUENTIAL WAIT STATEMENTS outputs next state Logic REG present state • Mealy machine detecting 101 • Use a style that separates logic and register parts • Also use an asynchronous reset CHAPTER 9 31 © 1999. .

ELSE nxt <= b. END IF. WHEN c => IF x = '0' THEN nxt <= a. . END behavioral. r) BEGIN IF r = '1' THEN present <= a. ELSE nxt <= b. END PROCESS. END IF. x) BEGIN z <= '0'. END CASE. BEGIN reg : PROCESS (clk. b. END PROCESS. END IF. ELSE nxt <= b. c). r. present : state. SIGNAL nxt. ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt. Navabi and McGraw-Hill Inc. END IF. END ENTITY. CASE present IS WHEN a => IF x = '0' THEN nxt <= a. -logic : PROCESS (present. Z. clk : IN BIT.SEQUENTIAL WAIT STATEMENTS ENTITY asynch_reset_detector IS PORT (x. z : OUT BIT). IF present = c AND x = '1' THEN z <= '1'. • VHDL description for a state machine with asynchronous reset • Most synthesis tools accept this style • Flexible in register part control CHAPTER 9 32 © 1999. WHEN b => IF x = '0' THEN nxt <= c. END IF. -ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a.

c2 <= '1'. .5 2.5 1.. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. Time 0. ... WAIT FOR 10 NS.0 US c1 c2 10NS 10NS • Generation of the second phase of a two phase non-overlapping clocking • c2 is generated by phase2 process CHAPTER 9 33 © 1999. END PROCESS phase2.. c2 <= '0'.SEQUENTIAL WAIT STATEMENTS . Z. Navabi and McGraw-Hill Inc.0 1. WAIT FOR 480 NS.

accepted <= '0'.start processing the newly received data WAIT UNTIL data_ready = '0'. Z. WAIT UNTIL accepted = '1'. . B accepts data • B releases A when data is picked CHAPTER 9 34 © 1999. accepted <= '1'.start the following when ready to send data_lines <= newly_prepared_data. data_ready <= '1'. data_ready <= '0'. -. --can use data_lines for other purposes System B: -.start the following when ready to accept data WAIT UNTIL data_ready = '1'. • Systems A & B talk • A prepares data.SEQUENTIAL WAIT STATEMENTS data_lines system A data_ready valid data accepted system B Process Data System A: -. Navabi and McGraw-Hill Inc.

SEQUENTIAL WAIT STATEMENTS 4 SYSTEM I in_data in_ready 16 out_data A in_received out_ready out_received B • • • • Use handshaking mechanism in an interface A prepares 4 bit data. Z. talk to B to put data CHAPTER 9 35 © 1999. . Navabi and McGraw-Hill Inc. B needs 16 bit data Create interface system I Talk to A to get data.

collect 4 4-bit data. SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0). END waiting.. in_received. buffer_picked. send to B using proper handshaking .Wait for 16-bit data from a_talk -.When ready. BEGIN a_talk: PROCESS BEGIN .. Z. • a_talk process & b_talk process also talk to each other • Use buffer_full. END PROCESS b_talk. in_ready. pass 16-bit data to b_talk . .. b_talk: PROCESS BEGIN . out_ready : OUT BIT)..... END PROCESS a_talk.Talk to A. out_received : IN BIT.When data is received. -ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full. END system_i. and word_buffer for a_talk and b_talk communication CHAPTER 9 36 © 1999. out_data : OUT BIT_VECTOR (15 DOWNTO 0). -. -. Navabi and McGraw-Hill Inc. keep a count -. buffer_picked : BIT := '0'.SEQUENTIAL WAIT STATEMENTS ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0)..

WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data. END CASE. buffer_full <= '1'. . Navabi and McGraw-Hill Inc. CASE count IS WHEN 0 => NULL. out_ready <= '0'. out_data <= word_buffer. in_received <= '0'. count := 0.SEQUENTIAL WAIT STATEMENTS a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0. END PROCESS b_talk. BEGIN WAIT UNTIL in_ready = '1'. count := count + 1. END IF. buffer_full <= '0'. WAIT UNTIL buffer_full = '0'. in_received <= '1'. WAIT UNTIL in_ready = '0'. Z. END PROCESS a_talk. out_ready <= '1'. WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data. WAIT UNTIL out_received = '1'. • a_talk gets data from A and talks to b_talk • b_talk talks to a_talk and sends data to B CHAPTER 9 37 © 1999. b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'. buffer_picked <= '0'. buffer_picked <= '1'. WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data. WAIT UNTIL buffer_picked = '1'. WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data.

req ues t3 gra nt3 . Navabi and McGraw-Hill Inc.SEQUENTIAL WAIT STATEMENTS clock Arbiter req ues t1 gra nt1 req ues t2 gra nt2 38 • • • • • req ues t0 gra nt0 Bus arbiter interface Simplified for this first example Synchronized arbitration A request input stays asserted until granted A request input is granted only one clock cycle of bus use CHAPTER 9 © 1999. Z.

END IF. -ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. Navabi and McGraw-Hill Inc. END PROCESS wait_cycle. grant (i) <= '1'.SEQUENTIAL WAIT STATEMENTS ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0). . END LOOP. END behavioral. FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000". WAIT ON clock. END arbiter. END IF. clock : IN BIT). process sensitivity cannot be used CHAPTER 9 39 © 1999. Z. ELSE grant (i) <= '0'. grant : BUFFER BIT_VECTOR (3 DOWNTO 0). • Bus arbiter description • Check all requests after the falling edge of the clock • Because of the 20 NS wait.

END io. SIGNAL r. . Navabi and McGraw-Hill Inc. g : BIT_VECTOR (3 DOWNTO 0). CONSTANT t : TIME := 1 US.SEQUENTIAL WAIT STATEMENTS ENTITY arbtest IS END arbtest. • Testing the arbiter • Four processes for generating data are generated • The time_array constant specifies timing requests coming from a source CHAPTER 9 40 © 1999. 15 US. sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i). clk). END GENERATE. g. WAIT UNTIL g(i) = '1'. clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk. 8 US). CONSTANT delays : time_array := (4 US. 3 US. BEGIN arb : ENTITY WORK. -ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT. TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME. END PROCESS. Z. r(i) <= '0'.arbiter PORT MAP (r. r(i) <= '1'. WAIT UNTIL clk = '0'.

SEQUENTIAL WAIT STATEMENTS S2P da tar ea dy ov err un fra me _e rro r pa ral lel _o ut serial rec eiv ed 8 A 10 bit frame reading begins start bit data bits stop bit • • • • • Another example using WAIT statements Serial_to_parallel interface RS232 frame with one start bit and one stop bit Framing error. . Z. Navabi and McGraw-Hill Inc. if stop bit is not seen Overrun error if start bit appears too soon CHAPTER 9 41 © 1999.

overrun. IF dataready = '1' THEN ELSE WAIT UNTIL serial = '0'. PORT (serial. while The other waits for untimely serial data to arrive (too_fast) WAIT statements are used in both processes 42 © 1999. dataready : BUFFER qit. BEGIN WAIT UNTIL serial = '1'. END PROCESS too_fast.SEQUENTIAL WAIT STATEMENTS ENTITY serial2parallel IS GENERIC (bps : INTEGER). ELSE WAIT UNTIL received = '0'. CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US. IF dataready = '1' THEN dataready <= '1'. dataready <= '0'. received : IN qit. overrun <= '1'. END IF. CHAPTER 9 . WAIT ON dataready. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). END serial2parallel. END LOOP. END IF. IF serial = '0' THEN too_fast : PROCESS frame_error <= '1'. frame_error <= '0'. END IF. CONSTANT half_bit : TIME := (1E6/REAL(bps))/2. WAIT FOR half_bit. parallel_out <= buff. overrun <= '0'. WAIT FOR full_bit. END PROCESS collect. FOR count IN 0 TO 7 LOOP WAIT FOR full_bit. Navabi and McGraw-Hill Inc. • • • • • Serial2parallel VHDL description Two concurrent processes One waits for prepared data to be picked up (collect).0 * 1 US. frame_error : OUT qit. -ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS --VARIABLE buff : qit_vector (7 DOWNTO 0). BEGIN WAIT UNTIL serial = '0'. END waiting. buff (count) := serial. Z. WAIT UNTIL received = '1'.

to read data from a line a line ENDFILE function. to check the end of a file Examples will demonstrate TEXTIO package and its applications • Only CHARACTERS are handled • All predefined standard types are converted to CHARACTERS • Subprograms are overloaded for all standard types CHAPTER 9 43 © 1999. to write data into a WRITELINE procedure. of CHARACTER type INPUT. a pointer to STRING TEXT file type. Z. .FORMATTED ASCII I/O OPERATIONS TEXTIO package is in the STD library TEXTIO contains: LINE type. Navabi and McGraw-Hill Inc. OUTPUT files for standard device IO READLINE procedure. to read data from a line a line WRITE procedure. to read a line from file READ procedure. to write line to file READ procedure.

l) -.writes l to file f ENDFILE(f) -. FILE f : TEXT OPEN READ_MODE IS “input. FILE_OPEN (f. READLINE(f.txt”.read a line of file f into buffer l READ(l. INTEGER. size. READ_MODE). FILE_CLOSE (f).txt”. and unit if v is of type TIME CHAPTER 9 44 © 1999.). FILE_OPEN (f.. REAL. Z.writes the value v to LINE l WRITELINE(f.reads a value v of its type from l WRITE(l.txt”.. . Navabi and McGraw-Hill Inc. l). FILE_OPEN (f. -. BIT_VECTOR.) -. -.returns TRUE if the end of f • READ and WRITE procedures are valid for: BIT.. . FILE f : TEXT.txt”. APPEND_MODE). CHARACTER. FILE f : TEXT IS “input. BOOLEAN. STRING. WRITE_MODE). “input. v. .. “output.FORMATTED ASCII I/O OPERATIONS VARIALE I : LINE. v.txt”. and TIME • Other parameters of these procedures include orientation. “output.

BEGIN FOR i IN sources'RANGE LOOP WRITE (l. 7). Z. state'IMAGE(sources(i)). defined in VHDL for the standard output • INPUT and OUTPUT work in all operating systems CHAPTER 9 45 © 1999. TYPE state IS (reset.ALL.. l). FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". RETURN sources(sources'LEFT).TEXTIO.FORMATTED ASCII I/O OPERATIONS USE STD. TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state.. Navabi and McGraw-Hill Inc. FUNCTION one_of (sources : state_vector) RETURN state IS VARIABLE l : LINE. got101). got1. END one_of. WRITELINE (flush. . got10. . LEFT. END LOOP. • A resolution function that writes its active drivers each time it is called • New code is highlighted • Unix device tty is the standard output • Can use OUTPUT.

". RIGHT. • A display procedure for writing time and events • New values are listed • Filler is used for signal values that do not change CHAPTER 9 46 © 1999. Navabi and McGraw-Hill Inc. 0). value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". WRITE (l. IF value1'EVENT AND value2'EVENT THEN WRITE (l. filler. RIGHT. WRITE (l. filler. LEFT. RIGHT. END display. WRITELINE (flush.. 0). 3). value2. RIGHT. value2. BEGIN WRITE (l.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. LEFT. VARIABLE filler : STRING (1 TO 3) := " . ELSE WRITE (l. . NS). Z. 8. END IF. value1. NOW. ELSIF value1'EVENT THEN WRITE (l. 3). 3). RIGHT. 3). WRITE (l. value1. l). VARIABLE l : LINE.

WRITELINE (flush. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. Z. 8. RIGHT. ELSIF value1'EVENT THEN WRITE (l. IF value1'EVENT AND value2'EVENT THEN WRITE (l. RIGHT. RIGHT. NS). . filler. l). c2 <= '1'. WAIT FOR 10 NS. WRITE (l. END PROCESS phase2. WAIT FOR 480 NS. filler. 0). LEFT.. BEGIN SIGNAL c2 : BIT := '0'. value2. 3).TEXTIO. VARIABLE filler : STRING (1 TO 3) := " . value1.FORMATTED ASCII I/O OPERATIONS PROCEDURE display (SIGNAL value1. ELSE WRITE (l. ENTITY two_phase_clock IS END two_phase_clock. END input_output. VARIABLE l : LINE. WRITE (l. USE STD. RIGHT. LEFT. Navabi and McGraw-Hill Inc. END IF. 3). • Call the display procedure anytime a clock phase changes • This procedure is also called once at the beginning of simulation CHAPTER 9 47 © 1999. BEGIN WRITE (l.ALL. c2). NOW. value2. display (c1. RIGHT. value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty". value1.". WRITE (l. END display. 0). -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1. 3). 3). c2 <= '0'.

value2 : BIT. WRITE (l. value2.". RIGHT. END displaying. VARIABLE l : LINE. RIGHT. END displaying. NS). ELSE WRITE (l. FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " . 3). -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. WRITE (l. RIGHT. filler. 3). 8. RIGHT. 0). NOW. LEFT. l). value2 : BIT. Z. 0). ELSIF value1'EVENT THEN WRITE (l. END display. value2. value1. LEFT.FORMATTED ASCII I/O OPERATIONS PACKAGE displaying IS PROCEDURE display (SIGNAL value1. IF value1'EVENT AND value2'EVENT THEN WRITE (l. . • A procedure for writing in an already open file • A file of type TEXT is passed to this procedure • This goes in our new displaying package CHAPTER 9 48 © 1999. Navabi and McGraw-Hill Inc. END IF. WRITELINE (flush. value1. FILE flush : TEXT). RIGHT.. WRITE (l. 3). BEGIN WRITE (l. filler. 3).

USE WORK.FORMATTED ASCII I/O OPERATIONS USE STD. . ENTITY two_phase_clock IS END two_phase_clock. END display. END PROCESS phase2. value2 : BIT. c2. Navabi and McGraw-Hill Inc. data). END displaying.ALL. c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1.ALL. value2 : BIT. FILE data : TEXT OPEN WRITE_MODE IS "clock. -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'. • Passing an open file to a procedure • File declaration takes place in the declarative part of an architecture • File remains open after being written into • Writing can continue elsewhere CHAPTER 9 49 © 1999. FILE flush : TEXT) IS . c2 <= '1'. -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1. END input_output. END displaying.. FILE flush : TEXT).out". PACKAGE displaying IS PROCEDURE display (SIGNAL value1. phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'. WAIT FOR 480 NS. BEGIN display (c1.TEXTIO. SIGNAL c2 : BIT := '0'..ALL. Z.TEXTIO.displaying. USE STD. c2 <= '0'. WAIT FOR 10 NS.

. .. 1 0 .. . 1 0 ..FORMATTED ASCII I/O OPERATIONS 0 500 510 990 1000 1500 1510 1990 2000 2500 2510 2990 3000 3500 3510 3990 4000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ... • Output file generated by the input_output architecture • File closes at the end of simulation CHAPTER 9 50 © 1999. Navabi and McGraw-Hill Inc. ... . . . 1 0 ........ 1 0 .. 1 0 . 1 0 .. 0 . .. Z. 1 0 . 1 0 .

appending is done to this line CHAPTER 9 51 © 1999. header. l). lo_value. . END IF. SIGNAL c1 : BIT := '1'. NOW. WRITE (l. RIGHT. FILE flush : TEXT OPEN WRITE_MODE IS "clock4. IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN append_wave_slice (c1). IF NOW = 0 US THEN VARIABLE lo_to_hi : STRING (1 TO 3) := ". WRITELINE (flush.". 8. ELSE WRITE (l. 5). RIGHT. c2) • • • • Generating an ASCII plot file 5 NS print resolution reports of the two-phase clock description Process wakes up. Navabi and McGraw-Hill Inc. END PROCESS writing. WRITE (l. NS). c1. lo_to_hi. append_wave_slice (c2). BEGIN END IF. IS WAIT FOR 10 NS. c2 <= '0'. VARIABLE header : STRING (1 TO 18) := " c1 c2 ".ALL. WRITELINE (flush.-+". hi_to_lo. ELSE ENTITY two_phase_clock IS END two_phase_clock. END IF. l). PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| ". CONSTANT print_resolution : TIME := 5 NS. IF s = '1' THEN WRITE (l. writing: PROCESS (print_tick. SIGNAL print_tick : BIT := '0'. RIGHT. 5). c2 <= '1'. END IF. VARIABLE l : LINE.out". SIGNAL c2 : BIT := '0'. ELSE END input_output. calls the append_wave_slice procedure Buffer l is visible in the procedure. END PROCEDURE append_wave_slice. BEGIN VARIABLE hi_value : STRING (1 TO 3) := " |". RIGHT.TEXTIO. phase2: PROCESS -BEGIN ARCHITECTURE input_output OF two_phase_clock WAIT UNTIL c1 = '0'. LEFT. 5). ELSE WRITE (l. Z. hi_value. WAIT FOR 480 NS. IF s = '1' THEN WRITE (l. RIGHT. print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED. 5). c1.FORMATTED ASCII I/O OPERATIONS c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US USE STD. BEGIN END PROCESS phase2. 0). VARIABLE hi_to_lo : STRING (1 TO 3) := "+-.

FORMATTED ASCII I/O OPERATIONS c1 480 485 490 495 500 505 510 510 515 520 525 . Navabi and McGraw-Hill Inc. ns ns ns ns ns ns ns ns ns ns ns | | | | +-. .-+" for 0 to 1 CHAPTER 9 52 © 1999." for 1 to 0 Write ".-+ | | | • • • • • Plot generated by the ploting process Plotting is activated every 5 NS Write " |" for '1'. | | | | | | c2 | | | | | | | .. "| " for '0' Write "+-.. Z.

74LS85. Z.MSI BASED DESIGN 8 data_in clk clear_bar load_bar count_in 4 sequential comparator 4 count Produces modulo-16 count of consecutive matching data Closing the chapter. Navabi and McGraw-Hill Inc. . 74LS163 Assume these parts are available CHAPTER 9 53 © 1999. will present a top-down design with MSI parts • • • • Sequential comparator circuit Design based on MSI parts 74LS377.

MSI BASED DESIGN sequential comparator 8-bit register 8-bit comparator 4-bit counter 4-bit comparator 4-bit comparator • Partition the circuit into smaller components • Partition until library components or synthesizable parts are reached • Will use top-down technique in designing a CPU in Chapter 10 CHAPTER 9 54 © 1999. Navabi and McGraw-Hill Inc. . Z.

3.4+ GI 1C2 < = > P P<Q P=Q P>Q Q 2D 1.MSI BASED DESIGN 74LS377 74LS85 74LS163 5CT=0 CTRDIV16 M1 M2 3CT=15 G3 G4 C5/2. Navabi and McGraw-Hill Inc. Z. . comparator. 5D [1] [2] [4] [8] • Standard MSI parts • Register. counter CHAPTER 9 55 © 1999.

• 74LS85. eq. PORT (a. END behavioral. gt. a_lt_b <= lt AFTER prop_delay. eq. ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay. a_lt_b : OUT qit). b : IN qit_vector (3 DOWNTO 0). gt. a_lt_b <= '1' AFTER prop_delay. four bit comparator • Relational operators. Navabi and McGraw-Hill Inc. END IF. . lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay. END ls85_comparator. lt : IN qit.basic_utilities. a_gt_b. ordering for array operands • Default delays can be configured later CHAPTER 9 56 © 1999. -ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a. ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay. a_eq_b <= '0' AFTER prop_delay. ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS). a_eq_b <= eq AFTER prop_delay. a_eq_b <= '0' AFTER prop_delay. END PROCESS. a_lt_b <= '0' AFTER prop_delay. Z.ALL.MSI BASED DESIGN USE WORK. b. a_eq_b.

.MSI BASED DESIGN USE WORK. q8 : OUT qit_vector (7 DOWNTO 0)). BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0'). END dataflow. Z. q8 <= GUARDED d8 AFTER prop_delay. -ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN. d8 : IN qit_vector (7 DOWNTO 0).basic_utilities. g_bar : IN qit.ALL. Navabi and McGraw-Hill Inc. PORT (clk. END ls377_register. • 74LS377. clocked register • Default delays can be used or reconfigured CHAPTER 9 57 © 1999. ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS).

q_abcd : OUT qit_vector (3 DOWNTO 0). ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS). ent : IN qit. Z. END IF. four bit synchronous counter • Default delays can be overwritten CHAPTER 9 58 © 1999. BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000". rco : OUT qit). ELSIF (ld_bar = '0') THEN internal_count := abcd. ELSE rco <= '0'. .MSI BASED DESIGN USE WORK. END IF. END ls163_counter. ld_bar. abcd : IN qit_vector (3 DOWNTO 0). Navabi and McGraw-Hill Inc. clr_bar. END behavioral. END IF. END PROCESS counting. ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count). • 74LS163. enp.basic_utilities. IF (internal_count = "1111" AND ent = ‘1’) THEN rco <= '1' AFTER prop_delay. PORT (clk. -ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000".ALL. q_abcd <= internal_count AFTER prop_delay.

specify delay CHAPTER 9 59 © 1999. Z.MSI BASED DESIGN LS377_register(behavioral) clk clear_bar load_bar data_in 8 4 8 clk d8 reg: d_register 4 q8 4 standard sequential comparator(structural) LS163_counter(behavioral) a b gt eq lt cmp_hi: comparator a_gt_b a_eq_b a_lt_b clk clr_bar load_bar enp ent abcd cnt: counter rco 4 q_abcd count g_bar prop_delay prop_delay 4 a b count_in gt eq lt 4 cmp_lo: comparator a_gt_b a_eq_b prop_delay a_lt_b prop_delay 15NS 18NS LS85_comparator(behavioral) 22NS • Design is based on available parts • Configure to use LS library. Navabi and McGraw-Hill Inc. .

clk. lt_i : qit. END sequential_comparator. eq_i. -ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk. compare_out. clear_bar. gt. eq_i. clr_bar. SIGNAL gnd : qit := '0'.ALL. gnd.MSI BASED DESIGN USE WORK. eq. enp. specify delay CHAPTER 9 60 © 1999. ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0). a_eq_b. q_abcd : OUT qit_vector (3 DOWNTO 0). . count_in. lt_i. OPEN). data_in. compare_out. END COMPONENT. gt_i. SIGNAL compare_out : qit. b : IN qit_vector (3 DOWNTO 0). g_bar : IN qit. rco : OUT qit). ent : IN qit. eq_i. old_data (3 DOWNTO 0). BEGIN reg: d_register PORT MAP (clk. COMPONENT comparator PORT (a. SIGNAL vdd : qit := '1'. clear_bar. count_in : IN qit_vector (3 DOWNTO 0). • Design is based on available parts • Assert statement in the entity declaration • Configure to use LS library. vdd. count. BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING. lt_i). Navabi and McGraw-Hill Inc. lt : IN qit. END structural. gnd. gt_i. abcd : IN qit_vector (3 DOWNTO 0). gnd. SIGNAL old_data : qit_vector (7 DOWNTO 0). END COMPONENT. OPEN. vdd. load_bar : IN qit. cnt: counter PORT MAP (clk. SIGNAL gt_i. OPEN). cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0). COMPONENT counter PORT (clk. old_data).basic_utilities. d8 : IN qit_vector (7 DOWNTO 0). a_lt_b : OUT qit). a_gt_b. count : OUT qit_vector (3 DOWNTO 0) ). END COMPONENT. cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4). q8 : OUT qit_vector (7 DOWNTO 0)). load_bar. old_data (7 DOWNTO 4). Z. ld_bar.

ALL. END FOR. FOR ALL : comparator USE ENTITY WORK. FOR cnt : counter USE ENTITY WORK. Z. CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK.ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS).ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS). . END FOR. END FOR.MSI BASED DESIGN USE WORK.ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS). END FOR. END standard. • Configuring the structural architecture of the sequential_comparator • Configuration declaration binds to 74LS parts • Generic values overwrite those of the 74LS parts CHAPTER 9 61 © 1999. Navabi and McGraw-Hill Inc.

BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck. cl_bar. .standard. "01110111" AFTER 3 US. Navabi and McGraw-Hill Inc. cl_bar <= '1'. '0' AFTER 50 US.ALL. count_in : IN qit_vector (3 DOWNTO 0). cl_bar. FOR mfi : seq_comp USE CONFIGURATION WORK. cnt <= "1111".basic_utilities. count : OUT qit_vector (3 DOWNTO 0) ). END input_output. • Testbench verifies behavior • Configuration specification associates mfi: seq_comp with the standard configuration declaration CHAPTER 9 62 © 1999. -ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0). clk. cnt_out). "01010100" AFTER 25 US. ld_bar : qit. ck. clear_bar. '1' AFTER 55 US. SIGNAL ck. SIGNAL cnt_out : qit_vector (3 DOWNTO 0). ENTITY test_sequential_comparator IS END test_sequential_comparator. cnt. "0111" AFTER 55 US. ld_bar <= '1'. data <= "00000000". END COMPONENT. load_bar : IN qit. Z. '0' AFTER 60 US. ld_bar.MSI BASED DESIGN USE WORK. mfi : seq_comp PORT MAP (data. "10101100" AFTER 5 US. SIGNAL data : qit_vector (7 DOWNTO 0). SIGNAL cnt : qit_vector (3 DOWNTO 0). "1011" AFTER 40 US.

. handshaking. Behavioral descriptions can be read and understood by non-technical managers and others who are not very familiar with VHDL. syntax and semantics for various forms of this construct were described. We then showed how process statements are used to describe controlling hardware. Navabi and McGraw-Hill Inc. Various forms of wait statements were extensively used in these descriptions. Although behavioral level constructs of VHDL provide a convenient method of describing very complex hardware. and file I/O.SUMMARY This chapter presented descriptions of hardware at the behavioral level and discussed how a process statement can be used to describe the main functionality of a module. • End Of Chapter 9 CHAPTER 9 63 © 1999. Z. In the first part of the chapter. a hardware designer can completely describe a digital circuit without having to use these constructs.

1 Interconnection of Components 10.3 Instruction Format 10.5.7.3 Interface Description of Parwan 10.8 SUMMARY CHAPTER 10 1 © 1999.5.3 BEHAVIORAL DESCRIPTION OF PARWAN 10.4.5.7.4.3.1 CPU Control Signals 10.4 Description of Components 10.1 Data and Control Partitioning 10. Navabi and McGraw-Hill Inc.6 A TEST BENCH FOR THE PARWAN CPU 10.5 DATAFLOW DESCRIPTION OF PARWAN 10.2 Global View of Parwan Components 10.2 PARWAN CPU 10.3 Instruction Execution 10.7 Wiring Data and Control Sections 10.2.5 Data Section of Parwan 10.3 General Description Methodology 10.5.3. .3 Hardware Modifications 10.1 DEFINING A COMPREHENSIVE EXAMPLE 10.2.3.7 A MORE REALISTIC PARWAN 10.CHAPTER 10 CPU MODELING AND DESIGN 10.2 Packages 10.1 Memory Organization of Parwan 10.2.5.5.4.2.6 Control Section of Parwan 10.2 Synthesizability 10.2 Timing of Data and Control Events 10.7.4 PARWAN BUSSING STRUCTURE 10.3.2 Instruction Set 10.5.1 Timing and Clocking 10.4 Parwan Behavioral Architecture 10. Z.4 Programming in Parwan Assembly 10.

DEFINING A COMPREHENSIVE EXAMPLE MAR PC IR SR AC ALU SHU Controller Will define a CPU describe it in VHDL. . 8-bit Data. and show its hardware details • • • • • General Layout of Parwan PARWAN. Navabi and McGraw-Hill Inc. PAR_1. Z. A Reduced Processor Simple 8-bit CPU. 12-bit Address Primarily designed for educational purposes Includes most common instructions CHAPTER 10 2 © 1999.

2:FF MEMORY: 5 4 3 2 page 0 .F:FF page 14 .E:FF F:00 . Navabi and McGraw-Hill Inc. .1:FF 2:00 . • • • • • Page and Offset Parts of Parwan addresses Memory divided into pages Pages of 256 bytes Address has page and offset part Uses memory mapped IO CHAPTER 10 3 © 1999. .0:FF 1:00 . page 2 .PARWAN CPU 7 6 1 1 1 0 0 9 Page 0 8 0 0 7 6 0 5 0 4 0 0 3 2 0 1 0 0 0:00 . . page 1 . Z. page 15 . . . . 1 0 Offset E:00 .

CMC. ASL. BRA_C. CLA. BRA_V. BRA_N NO Address NOP. . (12 bits) direct/indirect LDA. SUB.PARWAN CPU FULL Address. AND. (8 bit) JSR. ADD. JMP. ASR • • • • Three groups of instructions Full Address instructions include page and offset Page address instructions include offset No Address instructions occupy a single byte CHAPTER 10 4 © 1999. CMA. STA PAGE Address. BRA_Z. Navabi and McGraw-Hill Inc. Z.

Z.Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Brief Description Load AC w/(loc) AND AC w/(loc) Add (loc) to AC Sub (loc) from AC Jump to adr Store AC in loc Subroutine to tos Branch to adr if V Branch to adr if C Branch to adr if Z Branch to adr if N No operation Clear AC Complement AC Complement carry Arith shift left Arith shift right Address Bits 12 12 12 12 12 12 8 8 8 8 8 - Address Scheme FULL FULL FULL FULL FULL FULL PAGE PAGE PAGE PAGE PAGE NONE NONE NONE NONE NONE NONE Indirect Address YES YES YES YES YES YES NO NO NO NO NO NO NO NO NO NO NO Flags Use -------c--c----------v---c---z---n ----------c-------- Flags Set --zn --zn vczn vczn -----------------------------zn -c-vczn --zn • • • • Summary of Parwan instructions. Navabi and McGraw-Hill Inc. Load and store operations Arithmetic & logical operations jmp and branch instructions CHAPTER 10 5 © 1999. .

. Navabi and McGraw-Hill Inc.PARWAN CPU Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR Opcode Bits 765 000 001 010 011 100 101 110 111 111 111 111 111 111 111 111 111 111 D/I Bit 4 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 0 0 0 0 0 0 Bits 3210 Page adr Page adr Page adr Page adr Page adr Page adr ---1000 0100 0010 0001 0000 0001 0010 0100 1000 1001 • Parwan instruction opcodes • CPU contains V C Z N flags • Instructions use and/or influence these flags CHAPTER 10 6 © 1999. Z.

CMA. ASL. Navabi and McGraw-Hill Inc. CMA. Z. ASR ADD. SUB.PARWAN CPU influence ADD. SUB. LDA. AND. ADD. LDA. ASL ADD. SUB. SUB. ASL. ASL. CMC ADD. ASR use V C Z N BRA_V BRA_C. SUB. . CMC BRA_Z BRA_N • Arithmetic instructions influence all flags • Branch instructions use corresponding flags • Shift instructions influence all flags CHAPTER 10 7 © 1999. AND.

. Z.complete address pg: loc opc page pg: loc+1 offset • • • • • Addressing in full-address instructions Full address instructions use two bytes Right hand side of first byte is page Second byte contains offset Bit 4 is direct/indirect [0/1] indicator CHAPTER 10 8 © 1999. Navabi and McGraw-Hill Inc.

Navabi and McGraw-Hill Inc. .PARWAN CPU complete address pg: loc jsr or branch pg: loc+1 offset • • • • • Addressing in page-address instructions Page address instructions use two bytes All of first byte is used by opcode Page part of address uses current page Second byte is the offset CHAPTER 10 9 © 1999. Z.

. Navabi and McGraw-Hill Inc... BRA_C 6A 5:0D 5:0E 5:0F 11110100 6A .PARWAN CPU MEMORY .. . Z. BRANCH TO 6A if carry is set c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A • Branching is done within current page only • A branch instruction CHAPTER 10 10 © 1999.

1 3 SUBROUTINE CODE .. before and after jsr Store jsr return address at tos Begin subroutine at tos+1 Use indirect jmp to tos for return from subroutine CHAPTER 10 11 © 1999. Navabi and McGraw-Hill Inc. A F T E R J S R • • • • • An example for the execution of jsr Memory and pc..... 5:33 5:34 00000000 SUBROUTINE CODE . JSR 3 3 INSTR AFTER JSR .... 5:55 5:56 5:57 JMP Indirect 3 3 B E F O R E J S R 5:55 5:56 5:57 JMP Indirect 3 3 . .. .... JSR 3 3 INSTR AFTER JSR .PARWAN CPU MEMORY PC-> 5:11 5:12 5:13 MEMORY 5:11 5:12 5:13 .. Z...... . 5:33 PC-> 5:34 .

PARWAN CPU Indirect address Actual address Data Any page and offset Same page Indirecting effects offset operand 0:25 opc 1 6 6:1F 1 8 0:26 3 5 6:35 1 F • • • • An example for indirect addressing in Parwan. Navabi and McGraw-Hill Inc. Z. . Indirect addressing affects offset only To obtain actual address full addressing is used To obtain data page addressing is used CHAPTER 10 12 © 1999.

load pointer -.increment pointer -.add bytes -.load count -.clears carry 4:00 -.load 10 in 4:01 -.store pointer back -. Z.store partial sum -.load 25 in 4:00 -.store count back -.adding completed • • • • • An example program for Parwan CPU A program to add 10 bytes Use location 4:00 for data pointer Use location 4:01 for counter Constant 1 in 4:02 is used for +1 and -1 CHAPTER 10 13 © 1999.PARWAN CPU 0:15 0:16 0:17 0:19 0:1B 0:1D 0:1F 0:21 0:23 0:25 0:27 0:29 0:2B 0:2D cla asl add.get partial sum -.load 01 in 4:02 -.end if zero count -.decrement count :2D -.clear accumulator -. Navabi and McGraw-Hill Inc. i sta 4:03 lda 4:00 add 4:02 sta 4:00 lda 4:01 sub 4:02 bra_z sta 4:01 lda 4:03 jmp 0:17 nop -. .go for next byte -.

• Packages used will be described • A single component will describe all of Parwan CHAPTER 10 14 © 1999. USE par_library. END par_central_processing_unit.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. Coding for the behavioral description of Parwan will be presented. Navabi and McGraw-Hill Inc. -ENTITY par_central_processing_unit IS .ALL.ALL.par_utilities. USE cmos. .. Z. -LIBRARY par_library.ALL..basic_utilities. -ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral.par_parameters. USE par_library.

Navabi and McGraw-Hill Inc. b : qit_vector. . SUBTYPE twelve IS qit_vector (11 DOWNTO 0). b : qit_vector) RETURN qit_vector. b : qit_vector) RETURN qit_vector. -PACKAGE par_utilities IS FUNCTION "XOR" (a. -SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0).ALL. -END par_utilities. b : qit_vector. SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0).basic_utilities. FUNCTION "AND" (a. -CONSTANT zero_4 : nibble := "0000". SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0). Z.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT zero_12 : twelve := "000000000000". cin : qit) RETURN qit_vector. CONSTANT zero_8 : byte := "00000000". -SUBTYPE nibble IS qit_vector (3 DOWNTO 0). FUNCTION "NOT" (a : qit_vector) RETURN qit_vector. cin : qit) RETURN qit_vector. -FUNCTION add_cv (a. USE cmos. SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0). FUNCTION sub_cv (a. SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0). SUBTYPE byte IS qit_vector (7 DOWNTO 0). FUNCTION "OR" (a. -FUNCTION set_if_zero (a : qit_vector) RETURN qit. -SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0). b : qit) RETURN qit . • • • • Declarations of par_utilities package of par_library Machine descriptions require utilities Use basic_utilities Additional utilities are included in par_utilities CHAPTER 10 15 © 1999.

('X'. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i). -FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE).'X').'1'.'X'. . b). END "NOT". BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i).'1'. RETURN r. -FUNCTION "OR" (a.BEHAVIORAL DESCRIPTION OF PARWAN PACKAGE BODY par_utilities IS FUNCTION "XOR" (a. END "XOR".'0'. END LOOP loop1. END "AND".'X')). FUNCTION "AND" (a. END LOOP loop1.'X'). BEGIN RETURN qit_xor_table (a.'0'. END LOOP loop1. ('1'. Navabi and McGraw-Hill Inc. ('1'.b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE).b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE). END "OR".'0'.'X'. Z. • Body of par_utilities package of par_library library • Define XOR in qit • Overload logical operators with qit_vector CHAPTER 10 16 © 1999. RETURN r. b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0'. RETURN r. BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i).'0'.'X').

b_sign: qit. FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'. c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)). b_sign := b(b'LEFT). r(0) := a(0) XOR b(0) XOR cin. RETURN zero. FUNCTION sub_cv (a. --overflow ELSE r(a'LEFT+2) := '0'. END IF. BEGIN a_sign := a(a'LEFT). BEGIN not_b := NOT b. -. RETURN r. END IF. BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'. b : qit_vector. END add_cv. b : qit_vector. cin : qit) RETURN qit_vector IS VARIABLE r. c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)). not_c). • • • • Body of the par_utilities package of par_library library add_cv adds its operands creates c and v bits Put overflow in leftmost result bit Put carry to the right of overflow © 1999.extra r bits : msb: overflow. Navabi and McGraw-Hill Inc. next to msb: carry VARIABLE a_sign. Z. END set_if_zero.BEHAVIORAL DESCRIPTION OF PARWAN FUNCTION add_cv (a. not_c := NOT cin. not_b. END LOOP. r(a'LEFT+1) := c(a'LEFT). c: qit_vector (a'LEFT + 2 DOWNTO 0). r := add_cv (a. EXIT. END LOOP. VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0). END par_utilities. VARIABLE not_c : qit. END sub_cv. RETURN r. FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1). cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0). CHAPTER 10 17 . IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'.

BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001".ALL. CONSTANT ann : qit_vector (2 DOWNTO 0) := "001". CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111".basic_utilities. Navabi and McGraw-Hill Inc. CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100". CONSTANT sta : qit_vector (2 DOWNTO 0) := "101". . • Declaration of par_parameters Package of par_library • Assign appropriate names to opcodes • par_parameters is used for readability CHAPTER 10 18 © 1999. CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011". CONSTANT add : qit_vector (2 DOWNTO 0) := "010". -PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110". CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010". CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000". END par_parameters. CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001". Z. CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100". USE cmos. CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110". CONSTANT indirect : qit := '1'. CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11". CONSTANT lda : qit_vector (2 DOWNTO 0) := "000".

par_parameters. Z. .par_utilities.ALL. Navabi and McGraw-Hill Inc.BEHAVIORAL DESCRIPTION OF PARWAN LIBRARY cmos. adbus : OUT twelve ). read_low_time.basic_utilities. END par_central_processing_unit. read_mem. databus : INOUT wired_byte BUS := "ZZZZZZZZ". • Interface description of Parwan CHAPTER 10 19 © 1999. USE par_library. write_high_time.ALL. cycle_time : TIME := 4 US). USE par_library. PORT (clk : IN qit.ALL. USE cmos. -LIBRARY par_library. -ENTITY par_central_processing_unit IS GENERIC (read_high_time. write_mem : OUT qit. write_low_time : TIME := 2 US. interrupt : IN qit.

address in byte2.20.18. -. sub END IF.26. IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN Execute single-byte instructions. ELSE -.interrupt / otherwise END PROCESS. END IF. Figure 10. . Navabi and McGraw-Hill Inc.BEHAVIORAL DESCRIPTION OF PARWAN ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS Declare necessary variables. BEGIN IF interrupt = '1' THEN Handle interrupt. and. write ac. Figure 10. END IF. Figure 10. Figure 10. and.22. ELSE -. -. ELSIF byte1 (7 DOWNTO 4) = bra THEN Execute bra instructions. middle. ELSIF byte1 (7 DOWNTO 5) = sta THEN Execute sta instruction. add.single-byte / double-byte END IF.no interrupt Read first byte into byte1.19. Figure 10.17.jsr / bra / other double-byte instructions END IF. add. Figure 10. Figure 10.all other two-byte instructions IF byte1 (4) = indirect THEN Use byte1 and byte2 to get address. top. END behavioral.read operand for lda. increment pc.26. -. -. Figure 10. and sub. Figure 10.21. IF byte1 (7 DOWNTO 5) = jsr THEN Execute jsr instruction. Remove memory from databus. ELSE -. Z.25. byte2 has address.23. ELSE -. sub Read memory onto databus. add. Figure 10. bottom.16. Figure 10.jmp / sta / lda. • Outline of the Behavioral Description of Parwan CHAPTER 10 20 © 1999.24.two-byte instructions Read second byte into byte2.26. and.ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN Execute jmp instruction. increment pc. Execute lda. -. Figure 10. Figure 10.

n : qit. part of Parwan behavioral model • Filling the outline of the behavioral description of Parwan • Declarations.BEHAVIORAL DESCRIPTION OF PARWAN VARIABLE pc : twelve. Z. Reading the first byte CHAPTER 10 21 © 1999. VARIABLE v. read_mem <= '0'. c. byte1. read_mem <= '1'. WAIT FOR cycle_time. • Reading the first byte from the memory. WAIT FOR read_high_time. Navabi and McGraw-Hill Inc. pc := inc (pc). VARIABLE temp : qit_vector (9 DOWNTO 0). Interrupt handling. . z. VARIABLE ac. byte2 : byte. • Variable declarations of Parwan behavioral model pc := zero_12. byte1 := byte (databus). WAIT FOR read_low_time. • Interrupt handling of Parwan behavioral model adbus <= pc.

• Executing single-byte instructions in the behavioral model of Parwan • Using the least significant nibble for decoding instructions • Decoding instructions. WHEN asl => c := ac (7). n := ac (7). . IF ac = zero_8 THEN z := ‘1’.BEHAVIORAL DESCRIPTION OF PARWAN CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8. END IF. END IF. WHEN OTHERS => NULL. cla. IF c /= n THEN v := '1'. END IF. asl. IF ac = zero_8 THEN z := '1'. END CASE. WHEN cmc => c := NOT c. n := ac (7). WHEN cma => ac := NOT ac. WHEN asr => ac := ac (7) & ac (7 DOWNTO 1). ac := ac (6 DOWNTO 0) & '0'. asr CHAPTER 10 22 © 1999. IF ac = zero_8 THEN z := '1'. n := ac (7). cmc. Navabi and McGraw-Hill Inc. Z. cma. END IF.

read_mem <= '1'. pc := inc (pc). byte2 := byte (databus). part of Parwan behavioral model databus <= wired_byte (pc (7 DOWNTO 0) ). read_mem <= '0'.BEHAVIORAL DESCRIPTION OF PARWAN adbus <= pc. Navabi and McGraw-Hill Inc. write_mem <= '0'. Executing jsr CHAPTER 10 23 © 1999. Z. adbus (7 DOWNTO 0) <= byte2. write_mem <= '1'. pc (7 DOWNTO 0) := inc (byte2). . WAIT FOR read_high_time. WAIT FOR write_low_time. • Reading the second byte from the memory. databus <= "ZZZZZZZZ". WAIT FOR read_low_time. • Execution of the jsr instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Reading the second byte. WAIT FOR write_high_time.

• Execution of branch instructions in the behavioral model of Parwan adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). read_mem <= '0'. Z. . read_mem <= '1'. • Handling indirect addressing by the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Branch instruction. END IF. WAIT FOR read_low_time.BEHAVIORAL DESCRIPTION OF PARWAN IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2. WAIT FOR read_high_time. Navabi and McGraw-Hill Inc. Handling indirect addressing CHAPTER 10 24 © 1999. adbus (7 DOWNTO 0) <= byte2. byte2 := byte (databus).

WAIT FOR write_high_time. • Execution of jmp instruction in the behavioral model of Parwan adbus <= byte1 (3 DOWNTO 0) & byte2. databus <= "ZZZZZZZZ". databus <= wired_byte (ac). Z. Navabi and McGraw-Hill Inc. WAIT FOR write_low_time. write_mem <= '0'. • Execution of sta instruction in the behavioral model of Parwan • Filling the outline of the behavioral description of Parwan • Handling jmp and sta instructions CHAPTER 10 25 © 1999. write_mem <= '1'. .BEHAVIORAL DESCRIPTION OF PARWAN pc := byte1 (3 DOWNTO 0) & byte2.

BEHAVIORAL DESCRIPTION OF PARWAN adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0). c). read_mem <= '0'. and. ac := temp (7 DOWNTO 0). byte (databus). • Execution of lda. n := ac (7). END IF. WAIT FOR read_low_time. Z. WHEN OTHERS => NULL. END CASE. byte (databus). WHEN ann => ac := ac AND byte (databus). v := temp (9). WHEN sbb => temp := sub_cv (ac. c := temp (8). add. and sub instructions in the behavioral model of Parwan CHAPTER 10 26 © 1999. IF ac = zero_8 THEN z := '1'. c := temp (8). c). WHEN add => temp := add_cv (ac. ac := temp (7 DOWNTO 0). Navabi and McGraw-Hill Inc. WAIT FOR read_high_time. read_mem <= '1'. CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus). . v := temp (9). adbus (7 DOWNTO 0) <= byte2.

Navabi and McGraw-Hill Inc. Z.. ADBUS obus_on_dbus 8 8 4 8 AC ac_out a_side ALU b_side IR ir_out PC_PAGE pc_out PC_OFFSET CONTROLLER alu_flags 4 8 mar_page_bus mar_inp MAR_PAGE OBUS 4 mar_offset_bus alu_out SHU 4 8 MAR_OFFSET 8 mar_out SR 4 read_mem write_mem interrupt ADBUS 12 • Bussing structure of Parwan CHAPTER 10 27 © 1999.PARWAN BUSSING STRUCTURE databus_on_dbus DATABUS dbus_on_databus DBUS 8 4096 byte memory .. .

PARWAN BUSSING STRUCTURE Component AC IR PC MAR SR ALU SHU Type Register Register Loadable Up Counter Register Register Arithmetic Unit Shifter Logic Bits 8 8 12 12 4 8 8 • • • • Machine has 7 components Behavioral description helps partitioning the circuit Circuit components will be identified Bussing specifies interconnection of these components CHAPTER 10 28 © 1999. . Z. Navabi and McGraw-Hill Inc.

PARWAN BUSSING STRUCTURE LDA Instruction: Cycle 1 Begin Fetch Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Pc_on_mar_page_bus. Navabi and McGraw-Hill Inc. Next Fetch • Steps for execution of lda CHAPTER 10 29 © 1999... Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir Pc_on_mar_page_bus Get Address Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus Get Operand. Z. Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac . .

PARWAN BUSSING STRUCTURE Data Signals DATA SECTION Data Components and Buses CONTROL SECTION Control Signals • Data and control sections of Parwan CPU • 31 control signals from the controller to the data unit CHAPTER 10 30 © 1999. Z. Navabi and McGraw-Hill Inc. .

alu_not. .DATAFLOW DESCRIPTION OF PARWAN Applies To AC IR PC Category Register Control Register Control Register Control Signal Name load_ac. write_mem. Z. pc_on_mar_offset_bus. alu_sub Others I/O read_mem. dbus_on_mar_offset_bus DBUS Bus Control pc_offset_on_dbus. cm_carry_sr pc_on_mar_page_bus. arith_shift_right alu_and. zero_ac load_ir increment_pc. alu_a. databus_on_dbus ADBUS DATABUS SHU ALU Bus Control Bus Control Logic Units Logic Units mar_on_adbus dbus_on_databus arith_shift_left. alu_add. load_page_pc. reset_pc Loads ac Resets ac Loads ir Increments pc Functionality Loads page part of pc Loads offset part of pc Resets pc Loads page part of mar Loads offset part of mar Loads sr Complements carry flag of sr Puts page part of pc on mar page bus Puts 4 bits of ir on mar page bus Puts offset part of pc on mar offset bus Puts dbus on mar offset bus Puts offset part of pc on dbus Puts obus on dbus Puts external databus on internal dbus Puts all of mar on adbus Puts internal dbus on external databus Shifter shifts its input one place to the left Shifter shifts its input one place to the right Output of alu becomes and of its two inputs Output of alu becomes complement of its b input Output of alu becomes the same as its a input alu perfporms add operation on its two inputs Output of alu becomes the same as its b input alu perfporms subtraction of its two inputs Starts a memory read operation Starts a memory write operation Interrupts CPU MAR SR MAR_BUS Register Control Register Control Bus Control load_page_mar. load_offset_mar load_sr. obus_on_dbus. load_offset_pc. Navabi and McGraw-Hill Inc. alu_b. ir_on_mar_page_bus. interrupt • Inputs and outputs of Parwan control section • Signals for flow of data and data clocking CHAPTER 10 31 © 1999.

DATAFLOW DESCRIPTION OF PARWAN System Clock Control Signal 1 Control Signal 2 Control signals remain asserted for a complete clock cycle Allows logic unit propagation Clock data and control at the same time Clock data while control signals are still valid • Timing of control signals • Assume falling edge trigger data and control CHAPTER 10 32 © 1999. Z. Navabi and McGraw-Hill Inc. .

. • Operations and flags of alu • A control signal for each operation CHAPTER 10 33 © 1999.DATAFLOW DESCRIPTION OF PARWAN Id 0 1 2 3 4 5 Opcode line alu_and alu_not alu_a alu_add alu_b alu_sub Operation a AND b NOT b a b PLUS a b b MINUS a Flags zn zn zn vczn zn vczn Individual data components will be described in VHDL. Navabi and McGraw-Hill Inc. Will also show hardware. Z.

4. 3. 4. . 1. Navabi and McGraw-Hill Inc. 5) ZO (0. 5) NO alu_a alu_add [0] [1] [2] [3] [4] [5] [6] [7] alu_sub + alu_b - • Parwan alu • Logic symbol • One bit gate level hardware CHAPTER 10 34 © 1999. 5) CO (0.DATAFLOW DESCRIPTION OF PARWAN ai bi alu_and alu_not 0 1 2 3 4 5 VI CI ZI NI A B A B A B A B A B A B A B A B ALU (3. 5) VO (3. Z. 2. 3. 1. 2.

Navabi and McGraw-Hill Inc. • Package declaration for the alu_operations package • Simplify code and add readability CHAPTER 10 35 © 1999.DATAFLOW DESCRIPTION OF PARWAN LIBRARY cmos. CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010". CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000". CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000". USE cmos. CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000". Z. CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100".ALL. -PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001". .basic_utilities. END alu_operations.

c := c_flag_in. alu_sub : IN qit. v := v_flag_in. out_flags : OUT nibble). a_side. a_side. b_side. END behavioral. alu_b. alu_not. alu_add. END arithmetic_logic_unit. z_out : OUT byte. -.DATAFLOW DESCRIPTION OF PARWAN ENTITY arithmetic_logic_unit IS PORT (a_side. in_flags : IN nibble. WHEN a_input => t (7 DOWNTO 0) := a_side. WHEN OTHERS => NULL. alu_add. BEGIN WHEN a_add_b => t := add_cv (b_side. alu_a. . v := v_flag_in. alu_b. ALIAS c_flag_in : qit IS in_flags(2). alu_not. alu_and) IS • Behavioral description of arithmetic logic unit of Parwan CHAPTER 10 36 © 1999. alu_not. alu_add. v := t(9). c := c_flag_in. v := v_flag_in. END CASE. b_side : IN byte. Navabi and McGraw-Hill Inc. ALIAS z_flag_in : qit IS in_flags(1). alu_and. z. n := t(7). CASE qit_vector (5 DOWNTO 0)’ (alu_sub. v := v_flag_in. Z. c := c_flag_in. c. out_flags <= (v. -ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side.other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side. n). alu_a. z := set_if_zero (t (7 DOWNTO 0)). z. VARIABLE v. c_flag_in). c := c_flag_in. alu_b. alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0). n : qit. WHEN b_input => t (7 DOWNTO 0) := b_side. c_flag_in). alu_a. ALIAS n_flag_in : qit IS in_flags(0). c := t(8). z_out <= t (7 DOWNTO 0). c. ALIAS v_flag_in : qit IS in_flags(3). c := t(8). END PROCESS coding. WHEN b_compl => t (7 DOWNTO 0) := NOT b_side. v := t(9). WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side. alu_and.

R) NO i-1 • Parwan shu • Logic symbol • One bit hardware CHAPTER 10 37 © 1999. . Navabi and McGraw-Hill Inc. Z. R) ZO (L.DATAFLOW DESCRIPTION OF PARWAN L R Input Output SHU L R VI CI ZI NI [0] [1] [2] [3] [4] [5] [6] [7] i+1 i i ( L) VO (L) CO (L.

c. VARIABLE v. out_flags <= (v.DATAFLOW DESCRIPTION OF PARWAN ENTITY shifter_unit IS PORT (alu_side : IN byte. -ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side. z := set_if_zero (t). z. ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1). z. ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'. • Behavioral Description of the Shifter Unit of Parwan CHAPTER 10 38 © 1999. obus_side <= t. (v. ALIAS z_flag_in : qit IS in_flags(1). END IF. c. v := alu_side (6) XOR alu_side (7). v := v_flag_in. ALIAS c_flag_in : qit IS in_flags(2). obus_side : OUT byte. arith_shift_left. BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0). END PROCESS coding. c. ALIAS n_flag_in : qit IS in_flags(0). END behavioral. n : qit. . z := set_if_zero (t). n) := in_flags. c := c_flag_in. ALIAS v_flag_in : qit IS in_flags(3). z. in_flags : IN nibble. n := t (7). Navabi and McGraw-Hill Inc. c := alu_side (7). arith_shift_left. Z. END shifter_unit. n). arith_shift_right : IN qit. arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0). n := t (7). out_flags : OUT nibble).

3D [0] [1] [2] [3] N Z C V input c 2D Q output c load G1 cm_carry 1C2 • The status register • Logic symbol • One bit hardware CHAPTER 10 39 © 1999. 3D 1. .DATAFLOW DESCRIPTION OF PARWAN load cm_carry G1 G2 C3 SR N Z C V 1. Z. 3D 2. Navabi and McGraw-Hill Inc. 3D 1. 3D 1.

load. • Behavioral description of the status register of Parwan CHAPTER 10 40 © 1999. -ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000". END PROCESS. out_status <= internal_state. BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags.DATAFLOW DESCRIPTION OF PARWAN ENTITY status_register_unit IS PORT (in_flags : IN nibble. ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c. . END IF. cm_carry. Z. ALIAS internal_c : qit IS internal_state (2). END IF. out_status : OUT nibble. Navabi and McGraw-Hill Inc. END behavioral. END status_register_unit. ck : IN qit ).

. 4D 3.DATAFLOW DESCRIPTION OF PARWAN load zero G1 M2 M3 1C4 AC zero '0' I0 '0' I1 '0' I2 '0' I3 '0' I4 '0' I5 '0' I6 '0' I7 2. Navabi and McGraw-Hill Inc. 4D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 2D Q Oi I o2 o3 o4 o5 o6 o7 i G1 1C2 • Parwan accumulator • Logic symbol • One bit hardware CHAPTER 10 41 © 1999. 4D 3. 4D 2. 4D 2. 4D 3. 4D 3. 4D 3. 4D 2. 4D 3. 4D 3. Z. 4D 2. 4D 2. 4D 3. 4D 2. 4D 2.

Z. END dataflow. END BLOCK enable. • Dataflow description of Parwan accumulator CHAPTER 10 42 © 1999. END accumulator_unit. o8 : OUT byte. Navabi and McGraw-Hill Inc. load.DATAFLOW DESCRIPTION OF PARWAN ENTITY accumulator_unit IS PORT (i8 : IN byte. ck : IN qit). . -ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8. zero. END BLOCK clocking.

Navabi and McGraw-Hill Inc. Z. .DATAFLOW DESCRIPTION OF PARWAN IR LOAD CI 1C2 I I0 I1 I2 I3 I4 I5 I6 I7 2D 2D 2D 2D 2D 2D 2D 2D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 o2 o3 o4 i 2D Q Oi load o5 o6 o7 G1 1C2 • The Parwan instruction register • Logic symbol • One bit hardware CHAPTER 10 43 © 1999.

DATAFLOW DESCRIPTION OF PARWAN ENTITY instruction_register_unit IS PORT (i8 : IN byte. Z. load. • Dataflow description of the instruction register of Parwan CHAPTER 10 44 © 1999. ck : IN qit). END BLOCK enable. Navabi and McGraw-Hill Inc. -ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8. . o8 : OUT byte. END dataflow. END BLOCK clocking. END instruction_register_unit.

3D 2. 3D 1. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 O i-1 reset o4 o5 o6 o7 o8 o9 o10 o11 2R Q Oi G1 1T C2 load_pc_offset clock • Parwan program counter • Logic symbol • One bit hardware CHAPTER 10 45 © 1999. Z. Navabi and McGraw-Hill Inc. 3D 1. 3D 2. 3D 1. 3D 2. 3D 2. 3D 2.DATAFLOW DESCRIPTION OF PARWAN reset load_page load_offset increment 3R G1 G2 G4 C3/4+ PC I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 1. . 3D 2. 3D 2.

END IF. Z. BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12. increment. load_page. reset. END IF. END IF. END IF. END behavioral.DATAFLOW DESCRIPTION OF PARWAN ENTITY program_counter_unit IS PORT (i12 : IN twelve. • Behavioral description of the program counter of Parwan CHAPTER 10 46 © 1999. ELSIF increment = '1' THEN internal_state := inc (internal_state). ck : IN qit). Navabi and McGraw-Hill Inc. . load_offset. ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). o12 <= internal_state. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). END PROCESS. END program_counter_unit. o12 : OUT twelve. -ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12.

3D 1. 3D 2. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN MAR load_page load_offset G1 G2 C3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 2. 3D 2. 3D 2. 3D [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 I i 2D Q Oi load G1 1C2 • Logic symbol for the memory address register of Parwan CHAPTER 10 47 © 1999. 3D 2. 3D 1. 3D 2. 3D 1. . 3D 1. 3D 2. Z. 3D 2.

Navabi and McGraw-Hill Inc. Z. END IF. o12 <= internal_state.DATAFLOW DESCRIPTION OF PARWAN ENTITY memory_address_register_unit IS PORT (i12 : IN twelve. BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8). ck : IN qit). o12 : OUT twelve. IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0). END IF. END PROCESS. END IF. load_page. . END behavioral. END memory_address_register_unit. load_offset. -ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12. • Behavioral description of the memory address register of Parwan CHAPTER 10 48 © 1999.

cm_carry_sr. load_sr.outputs to the controller: ir_lines : OUT byte. -. load_page_mar. Z. status : OUT nibble ). ir_on_mar_page_bus. Navabi and McGraw-Hill Inc. . load_offset_mar. arith_shift_right. mar_on_adbus.register controls: load_ac. increment_pc. databus_on_dbus. obus_on_dbus. alu_sub : IN qit. load_offset_pc.logic unit function control inputs: arith_shift_left. pc_offset_on_dbus. reset_pc. load_ir. alu_a. -. alu_add. zero_ac. alu_and.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_data_path IS PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ". -. alu_not. pc_on_mar_offset_bus. alu_b. adbus : OUT twelve. clk : IN qit. END par_data_path. • Entity Declaration of the Data Section of Parwan • Wires all components • Specifies bussing CHAPTER 10 49 © 1999. -. dbus_on_databus. load_page_pc. dbus_on_mar_offset_bus.bus connections: pc_on_mar_page_bus.

out_status : OUT nibble. SIGNAL mar_bus : wired_twelve BUS.shifter_unit (behavioral). FOR r4: mar USE ENTITY WORK.arithmetic_logic_unit (behavioral). SIGNAL mar_inp : twelve. END COMPONENT. in_flags : IN nibble. . SIGNAL dbus : wired_byte BUS.memory_address_register_unit (behavioral). ck : IN qit ). z_out : OUT byte. load_page. Navabi and McGraw-Hill Inc. -SIGNAL ac_out. o8: OUT byte. alu_add. END COMPONENT. Z. ir_out. END COMPONENT. increment. ck : IN qit). alu_a.program_counter_unit (behavioral). END COMPONENT. alu_and. alu_out. load. FOR r1: ac USE ENTITY WORK. ck: IN qit). arith_shift_left. out_flags : OUT nibble). zero. alu_b. cm_carry. load. • Declarative Part of the structural Architecture of par_data_path • Components are declared • Busses and signals are declared CHAPTER 10 50 © 1999. reset. o8: OUT byte.accumulator_unit (dataflow). SIGNAL pc_out. END COMPONENT. obus : byte. arith_shift_right : IN qit. -COMPONENT ir PORT (i8: IN byte. -COMPONENT shu PORT (alu_side : IN byte. FOR l2 : shu USE ENTITY WORK. -COMPONENT pc PORT (i12 : IN twelve. load_page. load. b_side : IN byte. SIGNAL alu_a_inp : byte. -COMPONENT alu in_flags : IN nibble. -COMPONENT sr PORT (in_flags : IN nibble. obus_side : OUT byte. load_offset. mar_out : twelve. shu_flags. END COMPONENT. -COMPONENT mar PORT (i12 : IN twelve. alu_not. alu_sub : IN qit.status_register_unit (behavioral). ck: IN qit). ck : IN qit). o12 : OUT twelve. o12 : OUT twelve. FOR l1 : alu USE ENTITY WORK. load_offset. FOR r2: ir USE ENTITY WORK.instruction_register_unit (dataflow). END COMPONENT. PORT (a_side. sr_out : nibble.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE structural OF par_data_path IS -COMPONENT ac PORT (i8: IN byte. out_flags : OUT nibble). SIGNAL alu_flags. FOR r3: pc USE ENTITY WORK. FOR r5 : sr USE ENTITY WORK.

-obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus). END BLOCK dbus3. clk). END BLOCK databus1. ir_out. • Statement part of the par_data_path structural Architecture • Uses block statements for bussing • Register interconnections follow registers instantiation CHAPTER 10 51 © 1999. END BLOCK ir2. -r2: ir PORT MAP (obus. Z. --. ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)). -mar_bus1: mar_inp <= qit_vector (mar_bus). END BLOCK dbus2. -databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus. dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus.bus connections --dbus1: alu_a_inp <= qit_vector (dbus). ac_out. ir1: ir_lines <= ir_out. . dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus. load_ac.DATAFLOW DESCRIPTION OF PARWAN BEGIN -. END BLOCK obus1. clk). zero_ac.register connections --r1: ac PORT MAP (obus. Navabi and McGraw-Hill Inc. load_ir.

pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). reset_pc. load_page_mar. END BLOCK pc2.DATAFLOW DESCRIPTION OF PARWAN r3: pc PORT MAP (mar_out. clk). alu_b. -r5: sr PORT MAP (shu_flags. sr_out.connection of logical and register structures --l1: alu PORT MAP (alu_a_inp. alu_sub. . END BLOCK pc1. Z. clk). Navabi and McGraw-Hill Inc. arith_shift_right. -r4: mar PORT MAP (mar_inp. load_offset_pc. END BLOCK pc3. alu_flags. mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out. sr_out. l2: shu PORT MAP (alu_out. obus. sr1: status <= sr_out. clk). alu_not. cm_carry_sr. increment_pc. --. arith_shift_left. alu_and. pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)). load_sr. alu_flags). load_page_pc. mar_out. alu_a. END BLOCK mar1. • Statement part of the par_data_path structural Architecture • Ends with logic unit instantiations CHAPTER 10 52 © 1999. load_offset_mar. shu_flags). END structural. pc_out. alu_add. ac_out. pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)). alu_out.

DATAFLOW DESCRIPTION OF PARWAN To other control FF inputs External Signals logic block control FF i Q All Signals Activating State i 1D i C1 signals issuing control signals control signals to data section en system clock For the Parwan controller. hardware and coding will be described. . • Typical hardware surrounding a control flip-flop • The logic block is designated by a bubble • Controller is built using one-hot encoding CHAPTER 10 53 © 1999. style. Navabi and McGraw-Hill Inc. Z.

DATAFLOW DESCRIPTION OF PARWAN csx a b c logic block i d e logic block j csy Q 1D i C1 en 1D j C1 Q en 1D k C1 Q clock • Example for the structure of Parwan control section • Showing 3 states in a one-hot implementation CHAPTER 10 54 © 1999. Navabi and McGraw-Hill Inc. Z. .

register control signals: load_ac. load_page_pc. arith_shift_right. mar_on_adbus. -. pc_on_mar_offset_bus. -. alu_add. cm_carry_sr. . pc_offset_on_dbus. load_offset_mar. -. load_ir. dbus_on_mar_offset_bus. ir_on_mar_page_bus. zero_ac. END par_control_unit. interrupt : IN qit ).bus connection control signals: pc_on_mar_page_bus.logic unit function control outputs: arith_shift_left. dbus_on_databus. write_mem : OUT ored_qit BUS. increment_pc. BEGIN • • • • Entity declaration of Parwan control section Showing signals for the data unit Declaring states of the machine is shown Declarative part of the par_control_unit dataflow architecture CHAPTER 10 55 © 1999. databus_on_dbus.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_control_unit IS GENERIC (read_delay. alu_b. alu_sub : OUT ored_qit BUS.memory control and other external signals: read_mem. reset_pc. status : IN nibble.inputs from the data section: ir_lines : IN byte. -. load_page_mar. alu_and. write_delay : TIME := 3 NS). -. alu_not. ------------------------------------------------------------------------------------------------ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. obus_on_dbus. Z. Navabi and McGraw-Hill Inc. load_offset_pc. PORT (clk : IN qit. load_sr. alu_a.

. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN par_control_unit control_signal_1 assignments to control_signal_1 control_signal_2 control_signal_3 oring_qit type signals • Assigning signals with implied oring. par_control_unit outputs CHAPTER 10 56 © 1999. Z.

start of fetch -. Z. load_page_mar <= GUARDED '1'. load_offset_mar <= GUARDED '1'.goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'. END BLOCK ck.pc to mar pc_on_mar_page_bus <= GUARDED '1'. pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 2 reset_pc 1D 1 interrupt C1 • State 1: starting a fetch • VHDL code • Gate level hardware CHAPTER 10 57 © 1999. -. . END BLOCK s1. s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'. -.DATAFLOW DESCRIPTION OF PARWAN s1: BLOCK (s(1) = '1') BEGIN -.reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'. Navabi and McGraw-Hill Inc. pc_on_mar_offset_bus <= GUARDED '1'.

alu_a <= GUARDED ‘1’. END BLOCK ck. Navabi and McGraw-Hill Inc. END BLOCK s2. Z.fetching continues -.goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'. mar_on_adbus read_mem databus_on_dbus alu_a load_ir increment_pc 3 1D 2 C1 • State 2: completing a fetch • VHDL code • Gate level hardware CHAPTER 10 58 © 1999. -. .DATAFLOW DESCRIPTION OF PARWAN s2: BLOCK (s(2) = '1') BEGIN -. databus_on_dbus <= GUARDED '1'.read memory into ir mar_on_adbus <= GUARDED '1'. read_mem <= GUARDED '1' AFTER read_delay. load_ir <= GUARDED '1'. -.increment pc increment_pc <= GUARDED '1'.

pc to mar. cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'. arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'.goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'. arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'. Navabi and McGraw-Hill Inc. -. load_offset_mar <= GUARDED '1'. END BLOCK ck. alu_b) <= GUARDED qit_vector’(“10”) WHEN ir_lines (1) = ‘1’ ELSE qit_vector’( “01”). . pc_on_mar_offset_bus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s3: BLOCK (s(3) = '1') BEGIN -. load_page_mar <= GUARDED '1'. Z. • State 3: preparing for address fetch • Execution of single byte instructions • VHDL code CHAPTER 10 59 © 1999. ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. END BLOCK s3. zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'. load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'. -. END BLOCK sb. END BLOCK ck. for next read pc_on_mar_page_bus <= GUARDED '1'. load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'.perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not.

. Z.DATAFLOW DESCRIPTION OF PARWAN pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar 4 1D 3 IR7 IR6 IR5 IR4 C1 2 IR3 2 1 0 IR3 2 1 0 IR1 arith_shift_left arith_shift_right alu_not alu_b IR1 IR3 IR1 cm_carry_sr IR2 IR3 1 IR3 0 zero_ac load_ac load_sr • State 3: preparing for address fetch • Execution of single byte instructions • Gate level hardware CHAPTER 10 60 © 1999. Navabi and McGraw-Hill Inc.

jsr. and branch VHDL code Gate level hardware CHAPTER 10 61 © 1999. load_page_mar <= GUARDED '1'. END BLOCK s4.page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'.direct END BLOCK ck. load_offset_mar <= GUARDED '1'. .read memory into mar offset mar_on_adbus <= GUARDED '1'. END BLOCK sp. Z.page from ir. dbus_on_mar_offset_bus <= GUARDED '1'.bra END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s4: BLOCK (s(4) = '1') BEGIN -.completed operand (dir/indir) address -.indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'. -.increment pc increment_pc <= GUARDED '1'. • • • • State 4: completing address of full address instructions Branching for indirect. 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'.goto 5 for indirect. -. read_mem <= GUARDED '1' AFTER read_delay. -. and offset from next memory makeup 12-bit address -. -. -. direct. 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'. databus_on_dbus <= GUARDED '1'. -. END BLOCK pg. -. Navabi and McGraw-Hill Inc.goto 7 for jsr.keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -.jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'. -.

jsr. Z. direct. and branch • Gate level hardware CHAPTER 10 62 © 1999. Navabi and McGraw-Hill Inc. .DATAFLOW DESCRIPTION OF PARWAN mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offet_bus load_offset_mar increment_pc ir_on_mar_page_bus load_page_mar IR7 1D 4 6 5 C1 IR4 6 IR5 9 7 • State 4: completing address of full address instructions • Branching for indirect.

indirect addressing -. -. databus_on_dbus <= GUARDED '1'. Z. read_mem <= GUARDED '1' AFTER read_delay.goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'. mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offset_bus load_offset_mar 6 1D 5 c1 • State 5: taking care of indirect addressing • Actual address will now go in MAR CHAPTER 10 63 © 1999. . dbus_on_mar_offset_bus <= GUARDED '1'. load_offset_mar <= GUARDED '1'.read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'. Navabi and McGraw-Hill Inc. END BLOCK s5.DATAFLOW DESCRIPTION OF PARWAN s5: BLOCK (s(5) = '1') BEGIN -. END BLOCK ck.

and. Reading and executing jmp. and [lda. add.. sub END BLOCK s6... Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN . and sub instructions Outline of the VHDL code Outline of the hardware Three separate blocks for [jmp]. END BLOCK jm. sub] CHAPTER 10 64 © 1999. sta. and. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN . jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • • • • • State 6: reading the actual operand.perform lda. END BLOCK rd. . -. and. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN . add.. [sta].. add.. Z. lda. END BLOCK st.

END BLOCK s6.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. Navabi and McGraw-Hill Inc. and. -. load_offset_pc <= GUARDED '1'. add. sub] CHAPTER 10 65 © 1999. • • • • State 6: reading the actual operand. END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'. END BLOCK jm. Reading and executing jmp instruction VHDL code Two more blocks for [sta].. and [lda. Z. .. .

. . and. END BLOCK st.mar on adbus. . obus_on_dbus <= GUARDED '1'. sub] CHAPTER 10 66 © 1999.. Navabi and McGraw-Hill Inc. write to memory mar_on_adbus <= GUARDED '1'. -.. alu_b <= GUARDED ‘1’. add.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN . END BLOCK s6. Reading and executing sta instruction Partial VHDL code Need one more block for handling [lda. ac on databus. dbus_on_databus <= GUARDED '1'. • • • • State 6: reading the actual operand.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. Z.. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. write_mem <= GUARDED '1' AFTER write_delay. END BLOCK ck.

alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. and sub instructions Completing the VHDL code This last block handles [lda. • • • • State 6: reading the actual operand. read_mem <= GUARDED '1' AFTER read_delay.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.perform lda. sub END BLOCK s6.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN . Z. add. Navabi and McGraw-Hill Inc. and. -. read memory for operand. END BLOCK rd.mar on adbus. add. perform operation mar_on_adbus <= GUARDED '1'. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’.. . sta. END BLOCK ck. add. load_sr <= GUARDED '1'. Reading and executing jmp. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. databus_on_dbus <= GUARDED '1'.. and. -. and. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. load_ac <= GUARDED '1'. lda. sub] CHAPTER 10 67 © 1999. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -.

END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'. st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -. read memory for operand. and.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. lda. alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’. alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’. and. -. END BLOCK st. -. END BLOCK jm. and executing jmp. alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’. load_sr <= GUARDED '1'.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. obus_on_dbus <= GUARDED '1'. ac on databus. perform operation mar_on_adbus <= GUARDED '1'. write_mem <= GUARDED '1' AFTER write_delay.mar on adbus. databus_on_dbus <= GUARDED '1'. sub END BLOCK s6. END BLOCK rd. load_ac <= GUARDED '1'. add.mar on adbus. -. alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’. load_offset_pc <= GUARDED '1'.perform lda. • State 6: reading the actual operand. Navabi and McGraw-Hill Inc. Z. END BLOCK ck.goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'. . sta. read_mem <= GUARDED '1' AFTER read_delay. END BLOCK ck. add. dbus_on_databus <= GUARDED '1'. alu_b <= GUARDED ‘1’. -. and sub instructions • Complete VHDL code CHAPTER 10 68 © 1999. write to memory mar_on_adbus <= GUARDED '1'. rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -.

and executing jmp. Z. and. and sub instructions • Complete gate level hardware CHAPTER 10 69 © 1999.DATAFLOW DESCRIPTION OF PARWAN jm ir7 6 5 2 load_page_pc load_offset_pc 1D 6 C1 st ir7 6 5 1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem rd ir7 1 mar_on_adbus read_mem databus_on_dbus load_sr load_ac ir6 ir5 alu_a alu_and alu_add alu_sub • State 6: reading the actual operand. Navabi and McGraw-Hill Inc. lda. add. . sta.

Z. write_mem <= GUARDED '1' AFTER write_delay. dbus_on_databus <= GUARDED '1'.jsr -. END BLOCK s7. -.address of subroutine to pc load_offset_pc <= GUARDED '1'. pc_offset_on_dbus <= GUARDED '1'.DATAFLOW DESCRIPTION OF PARWAN s7: BLOCK (s(7) = '1') BEGIN -. Navabi and McGraw-Hill Inc.write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'. . -. END BLOCK ck.goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'. mar_on_adbus pc_offset_on_dbus dbus_on_databus write_mem load_offset_pc 8 1D 7 c1 • • • • State 7: writing return address of subroutine Making pc point to top of subroutine Complete VHDL code Hardware CHAPTER 10 70 © 1999.

increment_pc 9 1D 8 c1 • State 8: incrementing pc to skip location reserved for return address • VHDL code • Hardware CHAPTER 10 71 © 1999.DATAFLOW DESCRIPTION OF PARWAN s8: BLOCK (s(8) = '1') BEGIN -. Navabi and McGraw-Hill Inc.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'.increment pc increment_pc <= GUARDED '1'. Z. . END BLOCK ck. END BLOCK s8. -.

END BLOCK ck.DATAFLOW DESCRIPTION OF PARWAN s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'.goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'. ir3 status3 ir2 status2 load_offset_pc ir1 status1 ir0 status0 1 1D 9 C1 • State 9: conditional loading of pc for branch instructions • VHDL code • Gate level hardware CHAPTER 10 72 © 1999. Z. -. . END BLOCK s9. Navabi and McGraw-Hill Inc.

• • • • Ending the dataflow description of the par_control_unit Controller outline Need to clock all states A zero driver is placed on all state. END BLOCK ck. -. Z. CHAPTER 10 73 © 1999. Navabi and McGraw-Hill Inc. OOOO S8: BLOCK (s(8) = '1') BEGIN . S9: BLOCK (s(9) = '1') BEGIN . END BLOCK s8. BEGIN s(next) <= GUARDED '1'. BEGIN s(next) <= GUARDED '1'.. BEGIN s(next) <= GUARDED '1'.. END BLOCK ck. END BLOCK ck.. END BLOCK s2. S2: BLOCK (s(2) = '1') BEGIN . ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000". END BLOCK ck.State blocks end here END dataflow. END BLOCK s9..... .DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”. BEGIN s(next) <= GUARDED '1'.. BEGIN S1: BLOCK (s(1) = '1') BEGIN .. END BLOCK ck. END BLOCK s1.

Z. Navabi and McGraw-Hill Inc.DATAFLOW DESCRIPTION OF PARWAN Q 1D 1 C1 en 1D 2 C1 Q 3 C1 Q en Q 1D 4 C1 en 1D 5 C1 Q 1D 6 C1 Q en Q 1D 7 C1 1D 8 C1 Q 1D 9 C1 Q • Complete control unit • Wire individual control flip-flops • Oring is done at inputs of states when branching is done to them CHAPTER 10 74 © 1999. .

Navabi and McGraw-Hill Inc. databus : INOUT wired_byte BUS := "ZZZZZZZZ". adbus : OUT twelve ). Z. write_mem : OUT qit.DATAFLOW DESCRIPTION OF PARWAN ENTITY par_central_processing_unit IS PORT (clk : IN qit. • Entity declaration of the Parwan CPU for its dataflow description • Complete CPU wires data and control CHAPTER 10 75 © 1999. interrupt : IN qit. . read_mem. END par_central_processing_unit.

.par_control_unit (dataflow). . END COMPONENT. . BEGIN data: par_data_path PORT MAP (databus. Z. CHAPTER 10 76 . FOR ctrl: par_control_unit USE ENTITY WORK. write_mem : OUT qit. zero_ac. . interrupt : IN qit ). . status. . zero_ac. adbus : OUT twelve. ir_lines. write_mem. ir_lines : OUT byte. END COMPONENT. -SIGNAL load_ac. load_ac. -COMPONENT par_control_unit PORT (clk : IN qit. read_mem. zero_ac. • The general outline of dataflow architectture of Parwan CPU. Navabi and McGraw-Hill Inc. load_ac.par_data_path (structural). SIGNAL status : nibble. . . • Data and control declarations • Data and control wiring © 1999.DATAFLOW DESCRIPTION OF PARWAN ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte. status : OUT nibble ). . load_ac. zero_ac. END dataflow. ir_lines. adbus. FOR data: par_data_path USE ENTITY WORK. clk : IN qit. status ). ctrl: par_control_unit PORT MAP (clk. ir_lines : IN byte. zero_ac. load_ac. . status : IN nibble. interrupt ). . read_mem. . . SIGNAL ir_lines : byte. . clk. .

Navabi and McGraw-Hill Inc. interrupt : IN qit. read. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". "00010010". 25. "11100010". write_mem : OUT qit.. '0' AFTER 4500 NS. "01110000". qit2int (address. "00000000". • A simple testbench • Include CPU instantiation. adbus : OUT twelve ). "00011010". --cac. END input_output. "01011010". Z. . interrupt. --lda i 29. "00000000". sta 25 "00100000". ELSE data <= wired_byte ( memory (ia) ). "00100100". "10000000". 29. write : qit. "00011101". END IF. "00000000". "00011001". read. "10010000". sub 28 "00010000". "10100000". 31) "10000000". • A simple test bench for Parwan behavioral and dataflow descriptions. and read/write handshaking CHAPTER 10 77 © 1999. 27) "00001100". "01000000". "00011000". "00000000". data <= "ZZZZZZZZ". SIGNAL clock. --(28. END COMPONENT. "11101001". "00000000". data. write. "00011111". asr. "11000000". END IF. SIGNAL data : wired_byte := "ZZZZZZZZ". VARIABLE ia : INTEGER. 30. "00011100". add 27 "11100010". TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). WAIT UNTIL write = '0'. interrupt. "00100000". jsr 36 "11101000". BEGIN WAIT ON read. END IF. "11100000". a short memory. cpu : parwan PORT MAP (clock. --and 26. END PROCESS mem. "00000000". databus : INOUT wired_byte BUS. ia). SIGNAL address : twelve. IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". --asl. "00100100". "00000000". cma. --lda 24. write. read_mem.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit. WAIT UNTIL read = '0'. --jmp 18 "00000000". jmp i 36 OTHERS => (OTHERS => ‘0’)). -. 26. "01100000". clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "00010010". jmp 32 "00000000". address). "00011011". --(24. nop. BEGIN int : interrupt <= '1'. "01011100".

"00100100". "10100000". --(28. --lda 24..A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . 30. mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000". TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. "00000000". "00000000". SIGNAL address : twelve. write : qit. --and 26. --lda i 29. interrupt. "01011100". 26. "00011111". "00000000". "00011000". interrupt. "00010010". "00000000". BEGIN int : interrupt <= '1'. "00011011". data. . "01011010". BEGIN . "11100000". jmp 32 "00000000". --cac. "10010000". "00100000". -. "00100100". "00010010". --jmp 18 "00000000". nop. "01000000". 25. "01110000". "01100000". "10000000". Navabi and McGraw-Hill Inc. sub 28 "00010000". read. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. "11000000". address). jmp i 36 OTHERS => (OTHERS => ‘0’)). cpu : parwan PORT MAP (clock. write. --(24. Z. "00000000". add 27 "11100010". VARIABLE ia : INTEGER. "11101001". END input_output. --asl. '0' AFTER 4500 NS. "00000000". • Initializing memory for Parwan instructions CHAPTER 10 78 © 1999. cma.. jsr 36 "11101000"... "00011101". 31) "10000000". read. SIGNAL clock. asr. "00011100". SIGNAL data : wired_byte := "ZZZZZZZZ". sta 25 "00100000". "00011010". "00000000". 29.. 27) "00001100". "00011001". "11100010".

write. '0' AFTER 4500 NS.. WAIT UNTIL write = '0'.. data. write. SIGNAL address : twelve. END IF. interrupt. ia). read.. END input_output. SIGNAL clock. write : qit. . interrupt. END IF.A TEST BENCH FOR THE PARWAN CPU ARCHITECTURE input_output OF parwan_tester IS . IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ". mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := . WAIT UNTIL read = '0'. read. data <= "ZZZZZZZZ". BEGIN WAIT ON read.. Z. cpu : parwan PORT MAP (clock. Navabi and McGraw-Hill Inc. qit2int (address. • • • • Produce test waveforms on interrupt and clock signals Testing is done by modeling memory read and write operations A single process assigns values from memory to databus Same process handles memory write CHAPTER 10 79 © 1999. END IF. address). TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte. ELSE data <= wired_byte ( memory (ia) ). BEGIN int : interrupt <= '1'. clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock. VARIABLE ia : INTEGER. END PROCESS mem. ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ). SIGNAL data : wired_byte := "ZZZZZZZZ".

(b) • Parwan tester applies data to Parwan buses • Component is declared. END FOR. (a) CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow. END FOR. END FOR. Navabi and McGraw-Hill Inc. END dataflow. END FOR.par_central_processing_unit(dataflow). binding will be done by configuration declaration • Hold data normally at z (High Impedance) CHAPTER 10 80 © 1999. Z. END behavior. .par_central_processing_unit(behavioral).A TEST BENCH FOR THE PARWAN CPU CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral.

ELSE next_state <= instr_fetch.A MORE REALISTIC PARWAN WHEN instr_fetch => ---------------------------------------2 -. END IF. IF ready = '1' THEN databus_on_dbus <= '1'. load_ir <= '1'.. WHEN do_one_bytes => --------------------------------------3 . Navabi and McGraw-Hill Inc. END IF. increment_pc <= '1'.read memory into ir read_mem <= '1'.. alu_a <= ‘1’. . IF grant = '1' THEN mar_on_adbus <= '1'. ELSE next_state <= instr_fetch. Z. • Memory and bus signaling for fetch state of controller • Signals provide for slower memory handshaking • Buss access signals are included CHAPTER 10 81 © 1999. next_state <= do_one_bytes.

Navabi and McGraw-Hill Inc. The behavioral description aids designers as they verify their understanding of the problem. The methodology presented here can be applied to designs of much larger magnitude. The use of VHDL as a top-down partitioning and verification tool has helped us form such a methodology for manual design. For completing the design of Parwan. Z. and at the dataflow level after major design decisions have been made. We used one-to-one hardware correspondence so that no intelligent tools are required for the generation of hardware. . We consider the design presented here a manual design. A design carried to the stage where a dataflow model can be generated is only a few simple steps away from complete hardware realization. while the dataflow description can be used to verify the bussing and register structure of the design. flip-flop and gate interconnections should replace the component descriptions in the Parwan dataflow model. • End of Chapter 10 CHAPTER 10 82 © 1999.SUMMARY This chapter showed how VHDL could be used to describe a system at the behavioral level before the system is even designed.

4.8 SUMMARY CHAPTER 11 1 © 1999.CHAPTER 11 INTERFACE DESIGN AND MODELING 11.6.5. Navabi and McGraw-Hill Inc.6.3 Cache Structure Modeling 11.4.5.3 Arbiter Model 11. Z.2 Interface Through Arbiter 11.3 MEMORY SIGNALS 11.2 Wait Operation 11.4.4 Controller Modeling 11.2 Cache Interface 11. .5.4 SHARING SYSTEM BUSES 11.4 DMA Controller 11.6.2 CPU TIMING 11.1 SYSTEM OVERVIEW 11.1 Arbitration Operation 11.5.7 COMPLETE SYSTEM 11.3 Interface to CPU 11.5 DMA DEVICE 11.1 Cache Structure 11.6 CPU CACHE 11.6.1 Serial Connection 11.

Navabi and McGraw-Hill Inc. CHAPTER 11 2 © 1999. Z.SYSTEM OVERVIEW Arbiter Memory 4096*8 DMA Device Serial To Parallel serial_in DMA Controller cache memory & controller Address Decoder CPU • Bussing arrangement and system components. .

Navabi and McGraw-Hill Inc. . Z.SYSTEM OVERVIEW 8 dat abu s 12 ad bu s rea gra rea w dy nt d_ rite me _m m em 8-bit CPU (Parwan) halted interrupt • CPU interface CHAPTER 11 3 © 1999.

. Navabi and McGraw-Hill Inc.MEMORY SIGNALS clock read_mem grant ready adbus valid databus valid (a) • CPU read and write requests CHAPTER 11 4 © 1999. Z.

Navabi and McGraw-Hill Inc. .MEMORY SIGNALS clock write_mem grant ready adbus valid databus valid (b) • CPU read and write requests CHAPTER 11 5 © 1999. Z.

Navabi and McGraw-Hill Inc.MEMORY SIGNALS cs rwbar Memory 4096*8 dat abu s • Memory interface adb us CHAPTER 11 6 © 1999. Z. .

MEMORY SIGNALS Memory Wait cs rwbar adbus databus valid • Memory read operation CHAPTER 11 7 © 1999. Z. Navabi and McGraw-Hill Inc. .

. Z. Navabi and McGraw-Hill Inc.SHARING SYSTEM BUSES memsel rwbar ready gra wr nt ite rea _req d_ ue req st ue st clock Bus Arbiter and Wait Handler skip_wait port 1 port 2 port 3 port 4 • Controlling bus access CHAPTER 11 8 © 1999.

SHARING SYSTEM BUSES clock read_request i grant i memsel rwbar ready wait for bus access wait for device wait for wait state to complete • Bus grant for read operation CHAPTER 11 9 © 1999. Z. Navabi and McGraw-Hill Inc. .

WAIT FOR clock_period. END PROCESS wait_cycle. skip_wait : IN qit. END IF. rwbar. Z. grant (i) <= '1'. END LOOP. END IF.SHARING SYSTEM BUSES ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1). FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000". ready <= '1'. memsel <= '0'. memsel. grant : BUFFER nibble. clock_period : TIME := 1 US). ELSE grant (i) <= '0'. memsel <= '1'. END IF. rwbar <= read_request (i). END arbitrator. EXIT. • Arbiter VHDL description CHAPTER 11 10 © 1999. -ARCHITECTURE behavioral OF arbitrator IS BEGIN -.Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS. clock. write_request : IN nibble. WAIT ON clock. ready : OUT qit). END LOOP wait. ready <= '0'. END behavioral. . IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'. Navabi and McGraw-Hill Inc. PORT (read_request.

Navabi and McGraw-Hill Inc.DMA DEVICE Serial To Parallel serial pa ral lel _o ut ov err u fra n m_ err or 11 8 • Interface of serial-to-parallel converter CHAPTER 11 da tar ea rec dy eiv ed © 1999. Z. .

Navabi and McGraw-Hill Inc.DMA DEVICE 8 de v_ da ta er err de de ro or v_ v_ r2 1 rd rc y v read_mem write_mem databus grant DMA Controller addressbus ready status_write clk sel ect _re g status_read 4 • Interface of the DMA controller CHAPTER 11 12 © 1999. Z. .

. Z. Navabi and McGraw-Hill Inc.DMA DEVICE Address 1111:1111_1100 1111:1111_1101 1111:1111_1110 1111:1111_1111 DMA Registers Least 8 bits of starting address Most 4 bits of start Number of bytes to transfer done ie er2 er1 ie wr rd go • DMA Registers CHAPTER 11 13 © 1999.

. Z. Navabi and McGraw-Hill Inc.DMA DEVICE 4 adbus Address Decoder active • Decoding for selecting DMA registers CHAPTER 11 14 © 1999.

Navabi and McGraw-Hill Inc. WHEN OTHERS => selects <= "0000". END PROCESS. • VHDL description of DMA register address decoder CHAPTER 11 15 © 1999. WHEN "01" => selects <= "0010". ELSE active <= '0'.DMA DEVICE ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"). selects <= "0000". active : OUT qit. WHEN "11" => selects <= "1000". . selects : OUT nibble). -ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'. CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001". END IF. Z. END quad_adrdcd. END behavioral. PORT (adbus : IN twelve. END CASE. WHEN "10" => selects <= "0100".

Navabi and McGraw-Hill Inc.DMA DEVICE S2P serial 8 de er err dev dev v_ ro r2 or1 _rdy _rcv da ta read_mem 8 write_mem databus grant ready 12 addressbus status_read status_write sel ect _re g adbus status_sel active • DMA device CHAPTER 11 16 © 1999. pa ral lel _o ut ov err u fra n m_ e da rror tar rec ead eiv y ed DMA 4 selects Decoder . Z.

• DMA controller entity declaration CHAPTER 11 17 © 1999. Navabi and McGraw-Hill Inc. databus : INOUT byte := "ZZZZZZZZ". ready. -. dev_rcv : OUT qit.DMA DEVICE ENTITY dma_controller IS PORT (clk : IN qit.cpu signals select_reg : IN nibble.memory signals read_mem. grant : IN qit. status_wr : IN qit. write_mem : OUT qit := '0'. adbus : INOUT twelve := "ZZZZZZZZZZZZ". error2. dev_rdy : IN qit. --device signals error1. dev_data : IN byte ). -. . status_rd. END dma_controller. Z.

• DMA controller declarations. SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8). • Outline of DMA controller architecture.19) END behavioral. ALIAS rd : qit IS rfile(3)(1). TYPE r4 IS ARRAY (0 TO 3) OF byte.DMA DEVICE ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11. ALIAS wr : qit IS rfile(3)(2). . ALIAS ie : qit IS rfile(3)(3). Z.18) -“direct CPU communications” blocks (Figure 11. SIGNAL done : qit := '0'. Navabi and McGraw-Hill Inc. CHAPTER 11 18 © 1999. ALIAS go : qit IS rfile(3)(0).17) BEGIN “get serial. put parallel” process statement (Figure 11.

VARIABLE pntr : twelve. -.put to mem write_mem <= '1'. adbus <= "ZZZZZZZZZZZZ". BEGIN WAIT UNTIL go = '1'. pntr := rfile(1)(3 DOWNTO 0) & rfile(0). . VARIABLE numb : byte. done <= '1'. END PROCESS get_put. buff := dev_data. write_mem <= '0'. Z. dev_rcv <= '0'. dev_rcv <= '1'. END IF. END LOOP writing. WAIT UNTIL grant = '1'. WAIT UNTIL clk = '0'.DMA DEVICE get_put : PROCESS VARIABLE buff : byte := zero_8. adbus <= pntr.get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'. databus <= buff. databus <= "ZZZZZZZZ". • DMA controller “get serial and put parallel” process CHAPTER 11 19 © 1999. -. numb := rfile(2). WAIT UNTIL clk = '1'. END IF. done <= '0'.1. Navabi and McGraw-Hill Inc. pntr := pntr + 1. IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb . WAIT UNTIL ready = '1'.

• DMA controller “direct CPU communications” blocks CHAPTER 11 20 © 1999. Z. r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus. END BLOCK. END BLOCK. r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1'. error1).DMA DEVICE cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ". ie. Navabi and McGraw-Hill Inc. error2. END GENERATE cpu_direct. .

databus : INOUT byte := "ZZZZZZZZ". . -ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit. PORT (serial. status_rd. s2p_er1. databus : INOUT byte := "ZZZZZZZZ". adbus. databus. active : OUT qit. error1.DMA DEVICE ENTITY dma_serial_device IS PORT (clk : IN qit. COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"). SIGNAL cpu_mem_data : byte. END COMPONENT s2p. PORT (adbus : IN twelve. serial_in : IN qit). s2p_er1. ready. c3 : s2p PORT MAP (serial_in. status_rd. ready. COMPONENT s2p IS GENERIC (bps : INTEGER := 9600). s2p_rdy. s2p_rcv.memory signals read_mem. s2p_rcv. s2p_er2. SIGNAL select_reg : nibble. END dma_serial_device. dev_data : IN byte ). status_wr. s2p_rdy. SIGNAL s2p_rdy. write_mem. write_mem : OUT qit. dataready : BUFFER qit. read_mem. status_wr : IN qit. grant. parallel_out : BUFFER qit_vector (7 DOWNTO 0)). select_reg : IN nibble. adbus : INOUT twelve. dev_rcv : OUT qit. END COMPONENT dma. END structural. adbus : INOUT twelve. s2p_er2. status_sel. BEGIN c1 : dma PORT MAP (clk. received : IN qit. grant : IN qit. Navabi and McGraw-Hill Inc. dev_rdy : IN qit. status_wr : IN qit. read_mem. ready. overrun. description for diagram of Figure 11. END COMPONENT dcd.14 CHAPTER 11 21 © 1999. -. error2. status_rd. SIGNAL s2p_par : byte. status_sel : OUT qit. s2p_par). • DMA serial device. s2p_rcv. select_reg. Z. selects : OUT nibble). grant : IN qit. frame_error : OUT qit. select_reg). s2p_er2 : qit. c2 : dcd PORT MAP (adbus. s2p_par). SIGNAL cpu_mem_addr : twelve. write_mem : OUT qit := '0'. s2p_er1.

. Z. Navabi and McGraw-Hill Inc.CPU CACHE adbus valid set tag 5 To 32 tag line Way 0 Way 1 5 DCD LSB 7 MSB 8 8 v=1 & v=1 Match & Match 0 8 1 Hit • Cache Block Diagram CHAPTER 11 22 © 1999.

CPU CACHE adbus 5 7 MSB LSB 5 To 32 1: If a recent data was found in Way 0. Z. 0: If a recent data was found in Way 1. Navabi and McGraw-Hill Inc. . DCD lru • The lru table CHAPTER 11 23 © 1999.

CPU CACHE me me m_ m_ ad dat bu abu s s rea gra wr read dy nt_ ite_ _m _m m m e em em em m cache da tab us ad bu s rea dy gra nt wr ite rea d 24 clk • Cache Interface CHAPTER 11 © 1999. Navabi and McGraw-Hill Inc. . Z.

ready_mem : IN qit.cpu signals read. grant. grant_mem. write_mem : OUT qit.memory signals read_mem. mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ". -.CPU CACHE ENTITY cache_system IS PORT (clk : IN qit. mem_databus : INOUT byte := "ZZZZZZZZ". END cache_system. databus : INOUT byte := "ZZZZZZZZ". adbus : INOUT twelve := "ZZZZZZZZZZZZ" ). . Navabi and McGraw-Hill Inc. write : IN qit. Z. -. ready : OUT qit. • Cache Entity Declaration CHAPTER 11 25 © 1999.

read from memory and pass on to CPU Wait until (read OR write)=’1’. Navabi and McGraw-Hill Inc. write data in cache and memory If miss: Find least recently used For write. Z. END control_and_memory. write If hit: For read. pass data to CPU For write.CPU CACHE ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read. END PROCESS. write data in cache and memory For read. . • Outline of cache VHDL description CHAPTER 11 26 © 1999.

TYPE ww IS ARRAY(ways) OF ways. TYPE cache_type IS ARRAY (ways) OF each_cache. . free : ways. TYPE entry IS RECORD valid : BOOLEAN. data : line. Z. VARIABLE hit : BOOLEAN. VARIABLE w. END RECORD. ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0). tag : tags. Navabi and McGraw-Hill Inc. ALIAS tag_value : tags IS adbus (11 DOWNTO 5). SIGNAL cache : cache_type. TYPE each_cache IS ARRAY (sets) OF entry. • Controller local declarations CHAPTER 11 27 © 1999. SIGNAL lru : lru_type. SUBTYPE sets IS INTEGER RANGE 0 TO 31. SUBTYPE tags IS qit_vector (6 DOWNTO 0). 0). • Cache structure declarations VARIABLE s : sets. CONSTANT nw : ww := (1. TYPE lru_type IS ARRAY (sets) OF ways.CPU CACHE SUBTYPE ways IS INTEGER RANGE 0 TO 1. TYPE line IS ARRAY (0 TO 0) OF byte.

valid <= TRUE. • Controller search in cache IF hit THEN lru (s) <= nw (w). mem_databus <= databus. Navabi and McGraw-Hill Inc.valid THEN hit := TRUE. . hit := FALSE. write_mem <= '1'. cache(w)(s). databus <= cache(w)(s). ready <= '1'. write_mem <= '0'. mem_adbus <= "ZZZZZZZZZZZZ". WAIT UNTIL clk = '0'.data(0) <= databus. databus <= "ZZZZZZZZ". ELSIF write = '1' THEN cache(w)(s). WAIT UNTIL write = '0'. WAIT UNTIL grant_mem = '1'.data(0). • Controller code for cache hit CHAPTER 11 28 © 1999. IF read = '1' THEN ready <= '1'. ready <= '0'. FOR i IN ways LOOP IF cache(i)(s). Z. WAIT UNTIL read = '0'. END IF. w := i. END LOOP. END IF. mem_adbus <= adbus. mem_databus <= "ZZZZZZZZ". WAIT UNTIL ready_mem = '1'.tag = tag_value AND cache(i)(s). ready <= '0'. s := TO_INTEGER (set_value).CPU CACHE grant <= '1'.

ELSIF read = '1' THEN read_mem <= '1'. mem_databus <= databus.tag <= tag_value. WAIT UNTIL grant_mem = '1'.data(0) <= mem_databus. cache(free)(s).CPU CACHE ELSE -. . IF write = '1' THEN cache(free)(s).valid <= TRUE. WAIT UNTIL ready_mem = '1'. ready <= '1'. databus <= mem_databus.tag <= tag_value. mem_adbus <= adbus. cache(free)(s). write_mem <= '1'. mem_adbus <= "ZZZZZZZZZZZZ". WAIT UNTIL grant_mem = '1'. END IF. END IF. lru (s) <= nw (lru (s)). cache(free)(s). read_mem <= '0'.miss free := lru (s). Navabi and McGraw-Hill Inc. cache(free)(s). ready <= '0'. ready <= '1'. mem_adbus <= adbus. ready <= '0'. mem_adbus <= "ZZZZZZZZZZZZ". cache(free)(s). WAIT UNTIL write = '0'. WAIT UNTIL ready_mem = '1'. WAIT UNTIL read = '0'.data(0) <= databus. • Controller code for cache miss CHAPTER 11 29 © 1999. mem_databus <= "ZZZZZZZZ".valid <= TRUE. Z. write_mem <= '0'.

Navabi and McGraw-Hill Inc.CPU CACHE Arbiter s2p Mem DMA Cache Decoder Parwan CPU • Board level interface CHAPTER 11 30 © 1999. Z. .

cpu_read. address). csh_grant). Navabi and McGraw-Hill Inc. serial_in). cpu_address. cpu_data. wr_req. cpu_read. address. clock. grant_mem. Z. rd_req(0). ready. wr_req(1). cpu_write. data. csh_grant. csh_ready. rwbar. cpu_write. data. cpu_write. cs. END system. period) PORT MAP (rd_req. rwbar. address. • Interface board VHDL description CHAPTER 11 31 © 1999. -ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1'. cpu_read. cpu_data. skip_wait. '0' AFTER 4500 NS. data. wr_req(0). . clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock. cpu_address). rd_req(1). ready). srg : sergen PORT MAP (serial_in).CPU CACHE ENTITY parwan_tester IS END parwan_tester. csh_ready. csh : cache PORT MAP (clock. grant_mem(0). ready. halted. interrupt. cpu : parwan PORT MAP (clock. grant_mem(1). dev : serial PORT MAP (clock. mem : memory PORT MAP (cs. arb : arbitr GENERIC MAP ((OTHERS => 2). skip_wait.

this chapter presented design at a higher level of abstraction. . The examples presented here. • End of Chapter 11 CHAPTER 11 32 © 1999. Navabi and McGraw-Hill Inc. We illustrated the use of VHDL in a component level design environment. while other components such as the CPU and cache controller have two or three line fully-responsive or partially-responsive handshaking schemes. We have illustrated how such handshaking schemes can be described in VHDL. and how VHDL constructs can be used for handing communication between various devices. As opposed to Chapter 10 in which hardware details of a design were of concern. VHDL constructs used in this chapter were primarily at the behavioral level as discussed in Chapter 9.SUMMARY In this chapter we presented a board level design in VHDL. Language constructs for behavioral descriptions and timing and control were emphasized. show various forms of using wait statements in describing a design. The interface of the memory component is non-responsive. Several components with differing handshaking schemes were independently described. Z.

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