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Volume II
LESSONS IN DIGITAL ELECTRONICS
By JeanPaul NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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FOREWORD
The need of pedagogical resources in the domain of the teaching of Engineering Sciences is a great challenge in Cameroon. Many efforts have been made through the contribution of teachers, and also through the policy of promotion of technical education led by the government. However, much work is still to be done in order to build a real culture of Engineering in our country. This document is a contribution for the achievement of that goal. The course in digital electronics presented in this document is made up of nine chapters prepared following the official program in digital circuits of class six F3 and F2 series in Cameroon. However some extra material is added in order to open the mind of students to the world of digital electronics and computer science. This course is being taught by me (Mr. NGOUNE JeanPaul) in the Government Technical High School, KUMBO, Republic of Cameroon. Some amelioration may be brought to it along the years, according to the suggestions of readers and users of this course. ‘Courses In Electrical Engineering’ is a series of courses in various subjects of electronics and electrotechnics. This is the volume II of the series; the volume I treating the matter of the Analysis of electrical circuits (Class five F3 and F2 syllabus) is to be published very soon. This course and many other pedagogical documents produced by me are available and freely downloadable at the following address: www.scibd.com/jngoune.
JeanPaul NGOUNE (12 Sep. 11, 03:45).
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CONTENTS
Topic
Page
Chapter One: Numeration systems and codes
4
Chapter Two: Logic gates
25
Chapter Three: Boolean algebra
44
Chapter Four: Karnaugh mapping
58
Chapter Five: Digital arithmetic
69
Chapter Six: Combinatory logic
82
Chapter Seven: Multivibrators
111
Chapter Eight: Counters
133
Chapter Nine: Digital storage
148
About the Author
158
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER ONE: NUMERATION SYSTEMS AND CODES
By JP. NGOUNE DIPET I ( Electrotechnics), DIPET II (Electrotechnics) DEA ( Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter One
NUMERATION SYSTEMS AND CODES
1.0 Specific objectives: At the end of this chapter, the student will be able to: know binary, hexadecimal and octal numeration systems; Know Gray, BCD and ASCII codes; Master the principle of conversion from each numeration system to another.
1.1 Introduction: Numbers are used to express quantities. There are many numerations systems used in the field of digital electronics, one of the most important being the binary system of numeration on which is based the computer science. Each of the various numerations systems and codes has its advantages but also inconvenient. The aim of this chapter is to present and explain the most common numeration systems and codes used in the conception of digital circuits.
1.2 Digital versus Analogue representation: There are two basic ways we can represent quantities: Analogue representation and digital representation. With analogue representation, the quantity is symbolised in a way that is infinitely divisible. With digital representation, the quantity is symbolised in a way that is discretely packaged.
Example 1.1: • • The height of the red column which indicates the temperature measured by a thermometer is an analogue representation. An electronic watch whose digits changes second after second, minute after minute, shows a digital representation.
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The comparison between digital and analogue representations can be given as in the following chart:
Analogue representation Infinitely divisible Prone to errors of precision
Digital representation Discrete (Step by step) Absolute precision
1.3 Systems of numeration: To represent quantities in the different systems of numeration, specific symbols are used, which are also called ciphers.
1.3.1 Decimal numeration system: Decimal system is the most common numeration system for daily uses. It is constituted by 10 symbols or ciphers: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Each cipher represents an integer quantity and each place from right to left in a decimal notation represents a weight for each integer quantity.
Example 1.2: Let’s consider the decimal notation 1253. This number can be broken into its constituent weightproducts as such: 1253 = 1000 + 200 + 50 + 3 1253 = 1 × 1000 + 2 × 100 + 5 × 10 + 3 × 1 1253 = 1 × 103 + 2 × 10 2 + 5 × 101 + 3 × 100 We can easily notice that the cipher 1 is more weighted than the cipher 2 which in his turn is more weighted than the cipher 5. The cipher 3 is the less weighted.
In the decimal numeration system, each cipher is called a digit. Each weight or place value is ten that of the one to the immediate right. The less weighted cipher carries the One place, the cipher at the immediate left carries the Tens place, the follower carries the Hundreds place, thousands place, and so on…
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1.3.2 Binary numeration system: The binary numeration system uses only two ciphers instead of ten as the decimal numeration system. Those two ciphers are “0” and “1”. In binary system of numeration, ciphers are called bit (Binary Digit). Cipher are arranged right to left in doubling values of weight ( instead of multiplying the weight by 10 as in the case of decimal system).
Example 1.3: Let’s consider the following binary number
Weights
543210 A = 1 0 1 1 0 12
Base 2
A = 1 × 25 + 0 × 2 4 + 1 × 23 + 1 × 2 2 + 0 × 21 + 1 × 20 A = 32 + 0 + 8 + 4 + 1 A = 4510
Each weight is 2 that of the one in the immediate right. The less weighted cipher carries the Ones place (20), the cipher at the immediate left carries the twos place (21), the following cipher carries the fourth place (22)…
Exercise 1.1: Convert the following binary numbers to decimal numbers: A = 110101 B = 100110101 C = 11110111101 D = 101100001111
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1.3.3 Binary versus decimal numeration system: Let us count from 0 to 15 using binary and decimal systems of numeration Binary D(MSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A(LSB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
It is obvious that the representation of a quantity in binary numeration system takes mores ciphers than in decimal system. We can therefore ask ourselves why the binary system is preferred to decimal system in computer sciences. The reason is that in electronics, it is easier to materialise two quantities“0” and “1”(by two different voltages for example) than to materialises 10 different quantities – “0” ,”1” ,”2”,”3”,”4”,”5”,”6”,”7”,”8”, and”9” (by 10 different voltages). In fact, in digital circuits, 0 and 1 are materialised by specific ranges of voltages or current; this will be discussed later. Remark 1.1: With n bits we can represent 2 n different binary numbers. The higher H number is given using the following formula. H = 2n − 1
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Example 1.4: With 4 bits we can represent 24 = 16 different binary numbers (from 0 to 15), and the higher number is H = 24 – 1 = 15.
Remark 1.2: Conversion from binary to decimal To convert a number written in binary numeration system to its equivalent in decimal, we just have to calculate the products of the bits with their respective weights, as in example 1.3 above. For binary numbers with “binary point” (equivalent of decimal point for decimal numbers), the conversion is done as follow. 2 1 0 1 2 3 A = 1 0 1. 1 0 1 A = 1 × 2 2 + 0 × 21 + 1 × 20 + 1 × 2 −1 + 0 × 2 −2 + 1 × 2 −3 A = 4 + 0 +1+ A = 5.62510 1 0 1 + 2+ 3 1 2 2 2
Exercise 1.2: Convert from binary to decimal: A = 10110.01 B = 111.111 C = 11110111.1011 D = 10110101101.111101
1.3.4 Octal numeration system: The octal numeration system is a place weighted system with a base of eight. Valid ciphers include the symbols “0”,”1”,”2”,”3”,”4”,”5”,”6”, andf”7”. To convert from binary to octal numeration system, we just have to divide the number into groups of binary numbers having 3 bits each. And each group of 3 bits is replaced by its equivalent in octal.
Example 1.5: Let’s convert the following binary numbers in octal: A = 10110101 B = 11010111.01
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A = 010 110 101 2 6 58
101101012 = 2658
The bits are grouped from the right to the left. A zero has been added to the two firs bits to form a group of 3 bits. That zero is called an implied zero.
B = 011 010 111 . 010 3 2 7 . 28
11010111.012 = 327.28
Two implied zeros have been added to the number to form groups of 3 bits.
1.3.5 Hexadecimal numeration system: The hexadecimal numeration system is a place weighted system with a base of sixteen. Valid ciphers include the normal decimal symbols
“0”,”1”,”2”,”3”,”4”,”5”,”6”,”7”;”8”;9” plus six alphabetical characters A, B, C, D, E, and F. The following table summarises the equivalence between decimal, binary, octal and hexadecimal systems.
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Octal 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17
Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F
To convert from binary to hexadecimal numeration, we group bits in fours. Each group of four bit is replaced by its hexadecimal equivalent.
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Example 1.6: Convert the following binary numbers in hexadecimal. A = 1101011101 B = 11101011101.11 As explained above, we just have to group the binary number in groups of four bits each: A =0011 0101 1101 3 5 D16 11010111012 = 35D16
The binary number has been grouped is groups of four bits each, from the right to the left two implied zeros have been added at the extreme left. In the same way the number B can also be converted. B =0111 0101 1101 . 1100 7 5 D C16 11101011101.112 = 75DC16
1.4 Changing of base: We have already seen in the previous section how to change from binary to decimal, octal or hexadecimal systems of numeration. The present section is intended to show how to move from a given system of numeration to any other system.
1.4.1 From octal and hexadecimal to binary and decimal: The octal and hexadecimal systems are actually used by computer engineer just to obtain a “shorthand” representation of binary numbers (because octal and hexadecimal representations take a few numbers of ciphers or symbols as compared to binary system). It should therefore be understood that only binary system is implemented in the electronic circuits of digital systems (through two levels of voltages or currents: high (1) and low (0)), the others systems being used by engineers just for simplification issues. However, we sometimes have the need to convert either of those systems to binary or decimal forms.
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1.4.1.1 Octal and hexadecimal to binary: It is obvious that, to convert from octal to binary, we just have to convert each octal cipher to its binary equivalent in 3 bits. In the same way, to convert from hexadecimal to binary, we should convert each hexadecimal symbol into its binary equivalent in 4 bits.
Example 1.7: a) Convert the following octal number to digital 5238. b) Convert the following hexadecimal number to binary 4DC216. 5238 = 101 010 0112 5 2 3 4DC216 = 1001101110000102
5238 = 1010100112
4DC216 = 0100 1101 1100 00102 4 D C 2
1.4.1.2 Octal to decimal: Because octal is a base of eight numeration system, each place weight value differs from either adjacent place by factor of eight.
Example 1.8: Let us convert the following octal number to decimal: A = 264.748 2 1 0 1 2 A = 2 6 4. 7 48 A = 2 × 82 + 6 × 81 + 4 × 80 + 7 × 8−1 + 4 × 8−2 1 1 A = 2 × 64 + 6 × 8 + 4 × 1 + 7 × + 4 × 8 64 A = 180.937510
Exercise 1.3: Convert the following octal number to decimal: A = 4562.368 B = 523411.2328 C = 264.3658 D = 4516328
Is the number 12586 an octal number?
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1.4.1.3 Hexadecimal to decimal: The technique for converting hexadecimal notation to decimal is the same as the one used above, except that each successive place weight changes by a factor of sixteen. Example 1.9: Let us convert the following hexadecimal number to decimal: A = 34DF.AC216 3 2 1 0 123 A = 3 4 D F.A C 216
A = 3 × 163 + 4 × 16 2 + 13 × 161 + 15 × 160 + 10 × 16 −1 + 12 × 16−2 + 2 × 16 −3 A = 12288 + 1024 + 208 + 15 + 0.625 + 0.046875 + 0.000488281 A = 13535.6723610
Exercise 1.4: Convert from hexadecimal to decimal. X = A23C.DF16 Y = 7D3E16 Z = D96EC.FA16 1.4.2 Conversion from decimal numeration system to others systems: The conversion from decimal numeration system to others systems of numeration is an important task for everyone dealing with computer science, because it permits to move from daily world to digital world. 1.4.2.1 General method: To convert a number from decimal numeration system to binary, octal or hexadecimal, we use repeated cycles of divisions to break the decimal numeration down into multiples of binary, octal or hexadecimal place weight values. In the first cycle of division, we take the original decimal number and divide it by the base of the numeration system that we are converting to: It meant that for binary, we should divide by 2, for octal we should divide by 8, for hexadecimal we should divide by 16. Then we take the whole number portion of the division result and divide it by the result again, and so on, until we end up with a quotient of less than the base value.
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1.4.2.1 Decimal to binary conversion: Let us convert the decimal number 8710 to binary, using the principle described above. It meant that the decimal number should be repeatedly divided by 2. 87 43 21 10 5 2 1 2 2 2 2 2 2 1 1 1 0 1 0
The coloured ciphers are the reminders of repeated division of the decimal number by 2. To obtain the binary number, we just have to take those reminders, beginning with the last one, as indicated by the arrow. Then we have: 8710 = 10101112 In short, the binary bits are assembled from the reminders of the successive division steps, beginning with the LSB (Least Significant Bit) and proceeding to the MSB (Most significant Bit). Exercise 1.5: Convert the following decimal numbers to binary A = 15310 B = 25510 C = 4610 D = 3810
1.4.2.2 Conversion of decimal numbers less than 1 to binary: For converting a decimal number less than 1 to binary, we use repeated multiplication by 2, taking the integer portion of the product in each step as the next digit of our converted number. Let us convert the decimal number 0.37510 to binary: 0.375x2 = 0.75 0.75x2 = 1.5 0.5x2 = 1 Integer portion of the product = 0 Integer portion of the product = 1 Integer portion of the product = 1 (we stop when the product is a pure integer)
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Each step gives us the next bit further away from the binary point, so the binary number is obtained taking the bits from up to down. 0.37510 = 0.0112 Remark 1.3: With integer division, worked from the LSB to the MSB (down to up), but with repeated multiplication, we worked from up to down. Exercise 1.6: Convert from decimal to binary: A = 0.812510 B = 0.62510 Remark 1.4: To convert a decimal number greater than 1 with a less than 1 component, we should use both techniques, one at time. Let us convert the decimal number 23.12510 to binary. Step one: repeated division for the integer portion 2310. 23 11 5 2 1 2 2 2 2 1 1 1 0 C = 0.87510 D = 0.4062510
Partial answer: 2310 = 101112 Step two: repeated multiplication for the less than 1 portion 0.12510. 0.125x2 = 0.25 0.25x2 = 0.5 0.5x2 = 1 Integer portion of the product = 0 Integer portion of the product = 0 Integer portion of the product = 1
Partial answer: 0.12510 = 0.0012 Complete answer: 101112 + 0.0012 = 10111.0012
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Exercise 1.7: Convert from decimal to binary A = 17.37510 B = 43.62510 C = 27.87510 D = 49.4062510
1.4.2.3 Decimal to octal conversion: Let us convert the number 12310 from decimal to octal numeration system. As explained before, we just have to divide the decimal number successively by 8. 123 8 15 1 8 3 7
12310 = 1738 The octal digits are determined by the reminders left over by each division step. These reminders are between 0 and 7. Exercise 1.7: Convert the following numbers from decimal to octal: A = 32310 B = 45210 C = 12810 D = 9910
1.4.2.4 Decimal to hexadecimal conversion: Let us convert the number 45616 from decimal to hexadecimal. This conversion is obtained by repeated division of the decimal number by 16. 456 16 28 1 16 8 12 (C16)
45616 = 1C816
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Exercise 1.8: Convert from decimal to hexadecimal: A = 452310 B = 86710 1.5 Codes: A code is a system of letters, numbers or symbols that represent information. We have seen in previous sections that every decimal number can be converted in binary; by so doing, we can say that we are achieving a pure binary codification. There are many codes used in computer science to facilitate the operation of certain digital circuits. Some of those codes are: BCD code, Gray code, and alphanumerical codes. 1.5.1 Binary coded decimal (BCB) code: The BCD code of a decimal number is obtained by replacing each digit of the number by its equivalent in four bits, within the interval 0000 to 1001. Because of the fact that the maximal digit of the decimal numeration system is 9, the allowable codes goes from 0 (0000) to 9 (1001). So, the BCD code does not use the codes 1010, 1011, 1100, 1101, and 1111. Let us convert the number A = 45610 to BCD. A= 4 5 6 Decimal C = 99710 D = 123810
0100 0101 0110 A = 010001010110BCD Example 1.10:
BCD
Convert the following BCD number in decimal: X = 0110100000111001. Can the following series of bits be the BCD code of a decimal number? Y = 011111000001. X = 0110 6 X = 683910 Y =0111 1100 0001 7 ? 1 17 1000 0011 1001 8 3 9
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The second group of bit (1100) is not allowable in the BCD code, so the number Y cannot be the BCD code of a decimal number.
Exercise 1.9: Determine the equivalent BCD code of the following decimal numbers: A = 153610 B = 8975610 numbers: A = 100101110110 B = 110111100111 C = 5698910 D = 23569810
Determine if possible the decimal numbers corresponding to the following BCD
Remark 1.5: Difference between BCD code and binary number It is important to realise that the BCD code is not a numeration system as binary, octal or hexadecimal numerations systems. In fact, it is just a decimal system whose digits have been replaced by their binary equivalent in four bits. On the other hand it should be noticed that a BCD number is not a binary number. When we are to convert a decimal number to binary, the whole number is taken into consideration meanwhile to convert from decimal to BCD, each individual digit is replaced by its binary equivalent in four bits. For example, let us convert 1910 to binary and to BCD: 3510 = 1000112 3510 = 0011 0101 (BCD). It is obvious that the conversion from binary to BCD takes more bits than the conversion from decimal to binary. So the BCD code is not as efficient as the binary system. The advantage of the BCD code is just the fact that it is very easy to convert from decimal to BCD and vice versa. The BCD code is found in digital systems using 7 segments displays like digital voltmeters, digital watch…
1.5.2 Gray code: The Gray code is a non weighted code in which each coded representation differs from the previous representation only by one bit. It is not the case for binary system where many bits can change when we move from a number to the following
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number. For example, when we move from 0111 (710) to 1000 (810), all the four bits of the representation are changed. The Gray code is not suitable for arithmetical calculations (because it is not weighted); it is used in the determination of outputs equations of digital circuits (Karnaugh mapping) and in the design of Analog – Digital Converters. The following table gives us the equivalence between binary representation and Gray code. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Gray 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000
Remark 1.6: How to generate a Gray sequence If you observe attentively the Gray sequence above, you will notice that: • For the first column of ciphers (coming from the right to the left), the first zero is followed by two ones, which are followed by two zeros, two ones, two zeros… • For the next column of ciphers you can notice that the two first zeros are followed by four ones, which are followed by four zeros, four ones…
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•
For the third column of ciphers, the four first zeros are followed by eight ones, which are followed by eight zeros, eight ones…
This is the principle to be used in order to generate a Gray sequence.
1.5.3 Alphanumerical codes A computer would have been useless if it wasn’t able to treat non numerical information. In fact, a computer should be able to recognize codes corresponding to numbers, letters or some special characters. Such codes are called alphanumerical codes. Generally the keyboard of a computer should contain the following symbols: • • • The 26 letters of the alphabet (capital and small letters); The 10 ciphers of the decimal numeration system, Almost 25 special characters like +, /,>, <, @, %... There are almost 87 characters and to represent those characters, we need at least 7 bits because with 7 bit, we can have up to 27 = 128 different binary numbers. So, we use 87 of those binary numbers to codify the 87 characters. The most known alphanumerical code is called American Standard code for Information Interchange (ASCII). This code is used by almost all the computer constructors. The following table gives the ASCII code corresponding to some of the characters.
Character A B C D E F G H I J K
ASCII code 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011
Octal 101 102 103 104 105 106 107 110
Hexadecimal 41 42 43 44 45 46 47 48
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L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9 Blank . ( + $ * ) 
100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 010 0000 010 1110 010 1000 010 1011 010 0100 010 1010 010 1001 010 1101 21
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/ , =
010 1111 010 1100 011 1101
Exercise 1.10: • • Give the octal and hexadecimal equivalent for all the ASCII codes given above. The following instruction coded in ASCII is composed on the keyboard of a computer. Give its signification: 101 0011, 101 0100, 100 1111, 101 0000.
Answer: Using the table above we find that the instruction is STOP.
1.6 Conclusion This chapter has permitted us to study and to master (I hope so) the most common numeration systems and codes. We have also studied methods of conversion from each numeration system to another. In the next chapter, we will study the behaviour of logic gates, which can be considered as elementary ‘bricks’ used in the construction of any digital circuit.
REVIEW QUESTIONS
1. Give the difference between analogue and digital representations.
2. Convert from binary to decimal: A = 110112 B = 10111012 C = 10111112 D = 10010.0112 E = 101001111112 F = 1110111.00012
3. Convert from binary to octal: A = 111011.011012 B = 101101112 C = 11011110.01012 D = 111011111012 E = 10011101.1102 F = 100111101011112
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4. Convert from binary to hexadecimal. A = 1111010.11102 B = 101111101111012 C = 111010111.112 D = 10110110.1111012
5 Convert from octal to binary: A = 1238 B = 6538 C = 3578 D = 5478
6 Convert from hexadecimal to binary. X = F47B16 Y = 5FD316 Z = 8CE016 P = FFFC16
7 Convert from octal to decimal : A = 1258 B = 2568 C = 5638 D = 4538
8. Convert from hexadecimal to decimal: X = F47B16 Y = 5FD.316 Z = 8CE016 P = FFF.C16
9. Convert from decimal to binary: A = 2310 B = 25.37510 C = 5310 D = 101.2510
10. Convert from decimal to octal: A = 42310 B = 126410 C = 43810 D = 342310
11. Convert from decimal to hexadecimal: A = 126210 B = 356210 C = 256310 D = 56423610
12. Convert from octal to hexadecimal: A = 123.628 B = 432.58 23
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13 Determine the highest decimal number that can be represented using 8bits, 16 bits.
14 In most of the computers, the addresses of memory locations are expressed in hexadecimal. Those addresses are sequential numbers that identify each memory location. a) A computer can store data of 8 bits (1byte) in each of his memory location. If the addresses of the memory locations run from 000016 to FFFF16, then give the number of memory locations of that computer. Deduce the capacity of its memory. b) Another computer has 4096 memory locations. Give the interval of their addresses starting from 000016. 15 Determine the number of bits to be used to represent the decimal numbers from 00010 to 99910: a) using pure binary code b) using BCD code. 16 Express in ASCII the following instruction: “X = 25/Y”
17 Convert from BCD to binary: A = 01110100 (BCD).
References: 1. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 2. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER TWO : LOGIC GATES
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Two
LOGIC GATES
2.0 Specific objectives: At the end of this chapter, the student will be able to: Understand the functioning of the logic gates; Draw the truth table of simple logic circuits; Know logic voltage levels for TTL and CMOS technologies; Design a simple logic circuit using logic gates.
2.1 Introduction: Logic gates are “elementary bricks” used in the construction of digital circuits. While the binary numeration system studied in the precedent chapter was an interesting mathematical abstraction, we have not yet seen its practical application to electronics. This chapter is devoted to practically apply the concept of binary digits to circuits. A logic gate is a special type of circuit designed to accept (inputs) and generate (outputs) voltages signals corresponding to binary digits (1 and 0).
2.2 Digital signals and gates: Let us consider the following circuit:
Vcc
1
S R
LED
0
Figure 2.1: Logic circuit.
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When the switch is connected to the ground (0V), the light emitting diode (LED) does not shine. If we were using this circuit to represent binary digits, we would say that the input signal is a binary “0” and that the output is a binary “0” or that the output is at the low logic level. Moving the switch to the other position (Vcc), we apply a binary “1” to the input and receive a binary “1” at the output. The output is also said to be at the high logic level. The gate shown by this simple circuit is a “buffer” or “yes” gate, because the logic state of its input is identical to that of its output. Many types of gates are used in digital electronics: single input gates like the buffer and the NOT gates; multiple inputs gates like AND, NAND, OR, NOR, and XOR gates. The aim of this chapter is to study the functioning of each of those logic gates and also how they can be combined to design a simple logic function.
2.3 The NOT gate: The NOT gate or Inverter is a logic gate which functions in such a way that the logic state of the output is exactly the opposite of that of the input. Remark 2.1: The truth table A truth table is a standard way of representing the Inputs/outputs relationships of a digital circuit, listing all the possible input logic level combinations with their respective output logic levels. • The NOT gate truth table: Input 0 1 • Output 1 0
Symbol
Input
Output
Remark 2.2: the buffer gate If we were to connect two inverter gates together so that the output of one fed into the input of another, the two inversion functions would “cancel” each other out so that there would be no inversion from input to final output.
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1 0 0
Figure 2.2: Principle of the buffer gate
A buffer is a special logic gate manufactured to perform the same function as two inverters connected together. Buffer gates serve to amplify signals, taking a weak signal source that is not capable of providing much current, and boosting the current capacity of the signal so as to be able to drive a load. •
Input
Symbol of a buffer gate:
Output
•
Truth table of the buffer gate: Input 0 1 Output 0 1
2.4 Multiple input gates: With a single input gate such as the inverter or buffer, there can only be two possible input states: either 1 or 0. With multiple input gates, many possibilities are available for input states. The number of possible input states is equal to two to the power of the number of inputs. So, if a gate has n inputs, therefore there are 2n possible input combinations. 2.4.1 The AND gate: The output of the AND gate is high if and only if all inputs are high. If any input is low, the output is guaranteed to be in a low state as well. • Truth table:
Let us draw the truth table of a two inputs AND gate. A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1
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As you can notice on the truth table above, the output is high only when all the two inputs are high. •
A B
Symbol
Output
Exercise 2.1: Draw the truth table of a three inputs AND gate. Exercise 2.2: Complete the chronogram of the output Q of a two inputs AND gate.
A
B
t
Q
t
t
The following solution can be given for the exercise 2.2 above:
A
1
0
B
1
t
0
Q
1 0
t
t
2.4.2 The NAND gate: The word NAND is a verbal contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as an AND gate with a not gate connected to the output terminal. •
A B
Symbol
Output
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•
Truth table:
Let us draw the truth table of a two inputs NAND gate. A 0 0 1 1 B 0 1 0 1
A.B
1 1 1 0
As with AND gates, NAND gates can be made with more than two inputs.
Exercise 2.3: Complete the chronogram of the output Q of a two inputs NAND gate.
A
B
t
Q
t
t
2.4.3 The OR gate: The output of the OR gate is high if any of the inputs is high. The output of an OR gate goes low if and only if all inputs are low. • Truth table: A 0 0 1 1 •
A B
B 0 1 0 1
A+B 0 1 1 1
Symbol:
Output
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Exercise 2.4: Draw the truth table of a three inputs OR gate. Exercise 2.5: Complete the chronogram of the output Q of a two inputs OR gate.
A
B
t
Q
t
t
Exercise 2.6: Let us consider the following digital circuit:
A B C X E
a. Give the expression of the output X. b. Draw the truth table of the digital circuit.
Exercise 2.7: Draw the truth table of the digital circuit described by the following equation:
X = AB + ABC + AC
Exercise 2.8: Let us consider the following digital circuit:
A B C D E X
a. Give the expression of the output X.
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b. Draw the truth table of the circuit. c. Answer the two previous questions considering the following digital circuit:
A B X
C
2.4.4 The NOR gate: The NOR gate is an OR gate with its output inverted. • Truth table: A 0 0 1 1
•
A B
B 0 1 0 1
A+ B
1 0 0 0
Symbol:
Output
The NOR gate can also be manufactured with more than two inputs.
Exercise 2.9: Let us consider the following digital circuit:
A B C D E X
a. Give the expression of the output X. b. Draw the truth table of the circuit.
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Remark 2.3: The negative AND gate, the negative OR gate. Let us consider the following digital circuit:
A X B
a. Draw the truth table of this circuit. b. Show that this circuit is equivalent to a NOR gate. The expression of the output X can be written as follow: X = A.B . Therefore, the truth table of the circuit can be easily deduced: A 0 0 1 1 B 0 1 0 1 X 1 0 0 0
We can notice that the truth table of this circuit is identical to that of a NOR gate. The gate described in this exercise is called the negative AND gate and its symbol is given as follow:
A B Output
Let us consider the following gate circuit:
A X B
a. Draw the truth table of the circuit. b. Show that the circuit is equivalent to a NAND gate.
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The expression of the output X can be written as follow: X = A. + B . Therefore, the truth table of the circuit can be easily deduced: A 0 0 1 1 B 0 1 0 1 X 1 1 1 0
We can notice that the truth table of this circuit is identical to that of a NAND gate. The circuit described in this exercise is called the negative OR gate. Its symbol is given as follow:
A B
1 3 2
Output
Remark 2.4: The previous remark leads us to two important theorems of the Boolean algebra (the Boolean algebra will be studied in detail in the next chapter). Those theorems are called De Morgan’s theorems:
A + B = A..B A.B = A + B
Where A and B are two Boolean variables (A Boolean variable is that which can only take values 0 and 1).
2.4.5 The exclusiveOR gate: The exclusiveOR gate outputs a high level only if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, its output is low if the inputs are at the same logic levels. The exclusiveOR gate is sometimes called XOR gate. • Truth table: A 0 0 1 1 B 0 1 0 1
A⊕ B
0 1 1 0 34
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Symbol:
A B
Output
Exercise 2.10: Let us consider following gate circuit:
A B
a. Determine the expression of the output. b. Deduce the truth table. c. Conclude. Remark 2.5:
Y
From the exercise above the following property can be deduced:
A.B + A.B = A ⊕ B
2.4.6 The exclusiveNOR gate: The exclusiveNOR gate is equivalent to an exclusive OR gate with an inverted output. The truth table is exactly opposite as for the exclusiveOR gate. The exclusiveNOR gate also known as the XNOR gate. •
Truth table: A 0 0 1 1 B 0 1 0 1
A⊕ B
1 0 0 1
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•
A B
1 2
Symbol:
3
Output
Exercise 2.11: Let us consider the following gate circuit:
A B
X
a. Determine the expression of the output. b. Deduce the truth table. c. Conclude.
Remark 2.6: From the previous exercise, the following property can be deduced:
A..B + A.B = A ⊕ B
The exclusiveOR and exclusiveNOR gates are very useful for circuits where two or more binary numbers are to be compared bitforbit, and also for error detection (parity check).
2.5 Gate universality: NAND and NOR gates posses a special property: they are universal. That is, given enough gates, either type of gate is able to mimic the operation of any other gate type. This ability for a single gate type to be able to mimic any other gate type is enjoyed only by the NAND and the NOR gate.
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2.5.1 Constructing the NOT function:
Vcc Input
Output Input
Output
Input
Input Output
Output
2.5.2 Constructing the buffer function:
Vcc Vcc
Output Input
Input Output
2.5.3 Constructing the AND function:
A B Output
A
Output B
2.5.4 Constructing the NAND function:
A
Output B
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2.5.5 constructing the OR function:
Vcc
A
Vcc
Output
B
A B
Output
2.5.6 Constructing the NOR function:
Vcc
Vcc A
Vcc
Output
B
2.6 Voltages for logic states: Logic gate circuits are designed to input and output only two types of signals; ‘high’ (1) and ‘low’ (0), as represented by a variable voltage: Full power supply voltage for a high state and zero voltage for a low state. However, in reality, logic state voltage levels rarely attain these perfect limits. TTL gates (Transistor Transistor Logic) operate on a nominal power supply voltage of 5 volts+/ 0.25 volts. Acceptable input signal voltages range from 0 volt to 0.8 volt for low logic state, and 2 volts to 5 volts for high logic state. Acceptable output signal voltages range from 0 volt to 0.5 volt for low logic state and 2.7 volts to 5 volts for high logic state.
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High
High
High level noise margin
Low
Low level noise margin
low
Figure 2.3: Voltage levels for TTL gates
The noise margin of a gate is the difference between the tolerable output and input ranges. For CMOS gates (Complementary Metal Oxide Semiconductor) operating at a power supply of 5 volts, the acceptable input signal voltages range from 0 volt to 1.5 volts for low logic state, and 3.5 volts to 5 volts for a high logic state. Acceptable output signal voltages range from 0 volt to 0.05 volt for a low logic state and 4.95 volts to 5 volts for a high logic state. Exercise 2.12: Calculate the high level noise margin and the low level noise margin for CMOS circuits operating at a power supply of 5 volts. Compare that noise margin with that of a TTL circuit. Remark 2.7: Unlike TTL, which is restricted to a power supply voltage of 5 V, CMOS may be powered by voltages as high as 15 volts or 18 volts.
2.7 DIP gate packaging: Digital logic gates are manufactured as integrated circuits: all the constituent transistors and resistor built on a single piece of semiconductor material. The technicians and engineers find logic gates enclosed in DIP (Dual Inline Package) housing. Part numbers given to these DIP packages specify what type of gates are enclosed, and how many. These part numbers are industry standards.
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A ‘74LS02’ manufactured by Motorola will be identical in function to a ‘74LS02’ manufactured by Fairchild or by other manufacturers. Letter codes added to the part number are unique to the manufacturer and are not industry standard codes. For instance, a ‘SN74LS02’ is a quad2 inputs TTL NOR gate manufactured by Motorola while a ‘DM74LS02’ is the exact same circuit manufactured by Fairchild. Logic circuit part numbers beginning with ‘74’ are commercialgrad TTL. If the part number begins with the number ‘54’, the chip is a military grad unit having a greater operating temperature range, and typically more robust in regard to allowable power supply and signal voltage levels. The letters ‘LS’ immediately following the 74 or 54 prefix indicate low power shottky circuitry.
Figure 2.4: Examples of TTL DIP circuit packages:
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Figure 2.5: Examples of CMOS DIP circuit package
2.8 Conclusion: In this chapter, we have studied the functioning of logic gates which are basic tools used in the design of any logic circuit. An introduction has also been made concerning the input and output voltage levels for TTL and CMOS circuits. The aim of the next chapter is the study of the Boolean algebra. It is a set of mathematical properties and identities governing the functioning of logic circuits.
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REVIEW QUESTIONS
1. Consider the following gate circuit:
A X
B C
D
a. Give the expression of the output X. b. Draw the truth table of the circuit.
2. Draw the gate circuits corresponding to the following expressions:
X = A.B(C + D) Y = A + B + C D E + BC D Z = A + B + PQ ⊕ C D
(
)
3. For each of the following circuits, give the expression of the output and draw the truth table.
A
B
C
X
A B
Y
C
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A
B
C
Z
D
References: 3. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 4. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER THREE : BOOLEAN ALGEBRA
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Three
BOOLEAN ALGEBRA
3.0 Specific objectives: At the end of this chapter, the student will be able to: Master the rules of Boolean arithmetic; Master Boolean algebraic identities and properties; Convert truth tables of logic circuits into Boolean expressions.
3.1 Introduction: The Boolean algebra was created by the English mathematician George Boole (18151864). The Boolean algebra codifies rules of relationship between
mathematical quantities to one of two possible values: true or false, 1 or 0. So, all arithmetic operations performed with Boolean quantities have but one of two possible outcomes: either 1 or 0. There are three basic Boolean arithmetic operations: • • • Boolean addition which is equivalent to the OR logic function, as well as parallel switch contacts; Boolean multiplication, which is equivalent to the AND function as well as series switch contacts; Boolean complementation which is equivalent to the NOT logic function.
3.2 Boolean arithmetic: This section presents the basic relationship concerning the three basic Boolean arithmetic operations. 3.2.1 Boolean addition: As we have already said, Boolean addition is equivalent to the OR logic function. Therefore, we have the following relationships: 0+0=0 0+1=1 1+0=1 1+1=1
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0+0=0
0 0 0
0 0
0
0+1=1
U1
0 1 1
1
0 1
1+0=1
U2
1 1 0
1
1 0
1+1=1
U3
1 1 1
1
1 1
Remark 3.1: There is a difference between Boolean addition and binary addition; for binary addition we have the following relationships. 0+0=0 0+1=1 1+0=1 1 + 1 = 10 (1 + 1 = 0 + report of 1).
3.2.2 Boolean multiplication: The Boolean multiplication is equivalent to the AND logic function: 0x0=0 0x1=0 1x0=0 1x1=1
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0x0=0
0 0 0 0 0 0
0x1=0
0 1 0 0 1
1
0
1x0=0
1 0 0 1 0 0
1x1=1
1 1 1 1 1 1
3.2.3 Boolean complementation: The Boolean complementation is equivalent to the NOT logic function.
/0 = 1
0 1
/1 = 0
1
0
3.3 Boolean algebraic identities: An identity is a statement that is true for all possible values of its variables. There are two groups of Boolean algebraic identities: additive identities and multiplicative identities. 3.3.1 Additive identities If A is a Boolean variable, then the following statements are always true. A+0=A A+1=1 A+A=A A + /A = 1
A+0=A A 0 A 0 A A
A+1=1 A 1 1
A
1
1
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A+A=A A A A
A
A
A
A + /A = 1 A /A 1
A
1
/A
3.3.2 Multiplicative identities: A being a Boolean variable, the following statements are always true. 0xA=0 1xA=A AxA=A A x/A = 0
0xA=0
0 0 A 0 A 0
1xA=0
1 1 A A A A
AxA=A
A A A A A A
A x /A = 0
A A /A 0 /A 0
Remark 3.2: Double complementation Complementing a variable twice results in the original Boolean value.
A
/A
//A = A
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3.4 Boolean algebraic properties: Let us consider three Boolean variables A, B and C. The following properties are true. • Commutative property: Addition:
A+B=B+A • Multiplication:
AxB=BxA Associative property: Addition:
A + (B + C) = (A + B) + C • Multiplication:
A(B.C) = (A.B)C Distributive property:
A(B + C) = A.B + A.C
3.5 Boolean rules for simplification: There are several rules for Boolean algebra intended to be used in reducing complex Boolean expressions to their simplest forms. The simplification of the Boolean expressions of logic circuits brings many advantages: Higher operating speed (less delay time from input signal transition to output signal transition). Less power consumption (few IC used). Less cost. Greater reliability.
3.5.1 Rule n° A + AB = A 1: A + AB = A (1 + B) = A (1) =A 3.5.2 Rule n° A + AB = A + B 2:
A + AB = A + AB + AB (Apply the previous rule to expand A term to A + AB)
= A + B A + A (Factorising B)
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)
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= A + B(1) (Applying identity A + A = 1 )
= A+ B
3.5.3 Rule n° 3:
( A + B )( A + C ) = A + BC
(Distributing terms)
( A + B )( A + C ) = A. A + A.C + A.B + B.C
= A + AC + AB + BC (Applying identity AA = A) = A + AB + BC (Applying A + AC = A) = A + BC (Applying A + AB = A)
3.6 Circuit simplification example: Let us consider the following logic circuit.
A B Q
C
1. Write the Boolean expression of the output Q:
Q = AB + BC (B + C ) )
2. Reduce this expression to its simplest form using the rules of Boolean algebra.
Q = AB + BCB + BCC = AB + BC + BC (Using the identity A.A =A) = AB + BC (Identity A.A = A)
Q = B( A + C )
3. Generate the schematic diagram of the simplest expression
B
Q
A C
Remark 3.3 To convert Boolean expression to a gate circuit, you should evaluate the expression using standard order of operation: Multiplication before addition, Operation within parenthesis before anything else. 50
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Exercise 3.1: Simplify the following expressions using Boolean algebra and generate the schematic diagrams of the simplest expressions. X = A.B.C + A.BC + ABC + AB.C + A.B.C
Y = B+C B+C + A+ B+C
( )( ) Z = (C + D ) + AC D + AB.C + A..BCD + A.C.D
A⊕ B
3.7 The exclusiveOR function
A B
A ⊕ B = A.B + A.B
3.8 DeMorgan’s theorem
AB = A + B A + B = A..B
DeMorgan’s theorem may be thought in terms of breaking a long bar symbol. When a long bar is broken, the operation directly imply the changes from addition to multiplication or vice versa, and the broken bar pieces remains over the individual variables. Remark 3.4: When multiple layers of bar exists in an expression, you may only break one bar at a time. Example 3.1: Let us simplify the following expressions:
A + BC = A.BC (The superior bar broken) = A.BC A + B + C = A.B.C = A.BC
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3.9 Converting truth table into Boolean expression: We can convert truth table into Boolean expression using one of the following methods: Sum of products (SOP) Product of sums (POS)
3.9.1 Sum of products: Boolean expressions may be generated from truth table quite easily using the following steps: Determine which rows of the table have an output of 1; Write one product for each raw; Sum all the product terms.
This creates a Boolean expression representing the truth table as a whole. Example 3.2: Let’s consider a logic circuit having the following truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Q 0 0 0 1 0 1 1 1 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8
The rows 4, 6, 7 and 8 have an output of 1, each raw gives us a product. By summing those products, we obtain the following Boolean expression which is that of the output Q.
Q = ABC + A BC + ABC + ABC
Exercise 3.2: Simplify the expression of the output Q treated in the example above using Boolean algebra and generate the schematic diagram of the simplest expression.
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3.9.2 Product of sums: Boolean expression may be also generated from truth table quite easily by determining which rows of the table have an output of 0, writing one sum term for each row and finally multiplying all the terms. Example 3.3: Let us consider a logic circuit having the following truth table. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Q 0 1 1 1 1 1 1 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8
The rows 1 and 8 have an output of 0; each row gives us a sum. The product of those sums gives us a Boolean expression which is that of the output of the logic circuit. In fact, we have:
Q = A.B.C + ABC
Q=Q
( ) = (A..B..C ). A.B.C = A + B + C (A + B + C ) = ( A + B + C )(A + B + C )
= A..B..C + ABC Q = ( A + B + C ).( A + B + C ) In reality for each row having an output of 0, we should notice that we have but the inverted output product ( Q ). By inverting that output ( Q ), we obtain a sum using DeMorgan’s theorem. Finally, the product of all those sums gives us the output of the logic circuit.
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Remark: Generally, the sum of products is more used than the product of sums to convert a truth table into Boolean expression. However, when a few number of rows have an output of 0, it is preferable to use the POS than to use the SOP. Exercise 3.3: Generate the logic diagram of the circuit treated the example 3.3. Exercise 3.4: Assuming that A ⊕ B = A.B + A.B , proof that A ⊕ B = A.B + A..B 3.10 Conclusion: This chapter has permitted us to study the identities and the properties of the Boolean algebra. Those are tools used for the simplification of the Boolean expressions. However, this simplification is sometime very difficult to carry out, especially for logic circuit having complex Boolean expression. To solve this problem, another method of simplification has been proposed: that is Karnaugh mapping. It is the topic of the next chapter.
REVIEW QUESTIONS
1. Simplify the following expressions using Boolean algebra:
X = ABCD + A..B.C.D + A.B.C D + A.B.C.D + A.BCD + ABC.D + ABC D + ABC D + ABCD Y = ABC + ABC + ABC + ABC
2. Simplify the following circuit using the Boolean algebra.
A B C
X
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3. Conceive de logic circuit corresponding to the following truth table. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 X 1 0 1 1 1 0 0 1
4. Logic gates can be realised using diodes and resistors. Consider the following circuits:
Vcc
Va S Vb
Va S Vb
a. Analyse the functioning of each circuit by filling the following truth table. Va 0 0 1 1 Vb 0 1 0 1 Vs
b. Deduce the logic gate described by those circuits
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5. Logic gates can also be realised using resistor and transistor: That is resistor transistor logic (RTL). Consider the following circuits:
Vcc Vcc
Vout Va Vout Va
Vb Vb
Vcc
Vout Vin
Study the functioning of each of those circuits and determine the logic gate described by each of them.
6. Logic gates can also be realised using diodes and transistors.
Vcc
Va Vb
Vout
Study the functioning of the circuit and deduce the logic gate that it describes.
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7. A3A2A1A0 is a binary number having four bits. A3 is the MSB and A0 is the LSB. Conceive a logic circuit that produces an output of 1 when the binary number is superior to 0010 and inferior to 1000. 8. A logic circuit has 4 inputs A, B, C and D, and one output X. The output X is high only if C and D are low while A or B or both (A and B) are high. Conceive the logic circuit so described.
NB: The conception of a logic circuit requires the following steps: Truth table; Determination of the simplified expression of the output; Logic diagram of the circuit using logic gates.
References: 5. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 6. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER FOUR: KARNAUGH MAPPING
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Four
KARNAUGH MAPPING
4.0 Specific objectives: At the end of this chapter, the student will be able to simplify Boolean expressions using Karnaugh mapping.
4.1 Introduction: Karnaugh map, like Boolean algebra is a simplification tool applicable to digital logic. Maurice Karnaugh, a telecommunication engineer developed the kmap at Bell labs in 1953 while designing digital logic based telephone switching circuits. Kmap reduces logic functions more quickly and easily compared to Boolean algebra. By reduce we mean simplify, reducing the number of gates and inputs. Kmap works well for up to six input variables (in this course we will study up to 4 input variables). For more than six variables, simplification should be done by CAD (Computer Automated Design). 4.2 Karnaugh maps, truth tables and Boolean expression: Karnaugh map is filled using Gray code. As we have already seen in the first chapter, Gray code is a numeration code which is such that, in a given Gray sequence, each number differs from the next or the previous number only with one bit. In order to know how to generate a Gray sequence of number, please go back to the first chapter which treated the matter of numeration systems and codes.
4.2.1 Transferring the content of a truth table into a kmap: Let us consider the following truth table: A 0 0 1 1 B 0 1 0 1 X 0 1 0 1
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The content of the truth table can be transferred to the truth table as follow: X
B A
0 0 0
1 1 1
Top
0 1 Side
The logic states of the output are written in the table according to the combination of the input variable A and B. Each location of the table corresponds to one logic state of the output. So we have four locations here because we have four output combinations according to our truth table. The logic states of the inputs A and B are filled using Gray code. To determine the simplified Boolean expression of the output, we should follow the following steps: • • • Look for adjacent cells; that is above or to the side of a cell. Diagonal cells are not adjacent. Circle the two adjacent ones. Find the variables top and/or side which are the same for the group. It is the variable B in our case. It means that, as we can notice, for the group of ones, the variables B remains unchanged and equal to 1. Write this as the Boolean result. • Ignore variables which are not the same for the cell group. In our case, A varies. It is both 1 and 0. So A should be ignored; it cannot be written as Boolean result. • • Ignore any variable not associated with cells containing ones. Then the Boolean expression of the output is: X = B
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Exercise 4.1: Consider the following logic diagram:
A B
X
a. Establish the truth table of the circuit. b. Give the Boolean expression of the output using SOP (Sum of products) method. c. Give the simplified Boolean expression of the output using Kmap.
Exercise 4.2: For each of the following truth table, write the Boolean expression of the output using kmaps. A 0 0 1 1 B 0 1 0 1 X 1 1 0 0 A 0 0 1 1 B 0 1 0 1 X 0 1 1 1
A 0 0 1 1
B 0 1 0 1
X 1 0 1 1
A 0 0 1 1
B 0 1 0 1
X 1 1 0 1
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Remark 4.1: How to determine the Boolean expression of a gate circuit. • • • • • Write the Boolean expression of the output using SOP method; Transfer the product terms to the kmap; Form groups of adjacent cells; Deduce simplified Boolean expression of the output. Draw the simplified logic circuit.
Example 4.1: Let us determine the simplified Boolean expression of the following circuit using kmap.
A B
X
•
Using the SOP method the Boolean expression of the output can be written as follow:
X = A B + AB •
The expression can then be transfer in a kmap:
X
B A
0 0 1
1 1 0
0 1
• •
It is not possible to form groups of adjacent ones. The two ones of the kmap are isolated. No simplification is therefore possible. The Boolean expression should be left as it is.
X = AB + AB = A ⊕ B
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This is not a simplified expression. This ‘simplification’ is just intended to make a schematic diagram look nicer. In fact exclusiveor function is a combination of other functions. 4.2.2 Logic simplification with Karnaugh map: Boolean simplification that we have done above could be achieved with Boolean algebra quickly. Real world logic simplification problems call for larger kmaps so that we may do serious work. We will now develop tools that we need for more complex application in combinatory logic. 4.2.2.1 General method These are the steps which should be followed for the simplification of a Boolean expression using Karnaugh mapping. • • • • • • Draw the kmap filling the ones and the zeros in the corresponding cells; Observe with attention the kmap and detect the ones which are isolated: those are the ones that are not adjacent to another one. Circle them. Find the ones which are adjacent only to one another one. Circle them to form groups of two ones. Find groups one eight ones which are adjacent and circle them, even if among them there are ones belonging already to a group of two ones. Find groups of four adjacent ones and circle them. Among the four ones there should be at least one one which has not yet been grouped. Then deduce the simplified Boolean expression.
The following sizes of kmap will be used
X
CD AB
00
01
11
10
X
A
BC
00 00 01 11 10 01 11 10
0 1
Kmap for 3 Boolean input variables
Kmap for four Boolean input variables
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As we have already said, the input logic states are filled using Gray code, so for instance, if we have two variables A and B, the Gray sequence will be: 00,01,11,10 (a binary sequence would have been 00,01,10,11!).
4.2.2.2 Kmap for three input Boolean variables: Let us consider the following three variables Boolean expression.
X = A.B.C + A.B.C
This expression can be transferred in a kmap as follow: X
A BC
00 1 0
01 1 0
11 0 0
10 0 0
0 1
The simplified Boolean expression of the output can therefore be determined.
X = A.B
Exercise4.3: Simplify the following Boolean expressions using kmaps:
X = A.B.C + A.B.C + A.BC + A.B.C Y = A.B.C + A.BC + ABC + ABC Z = A.B.C + A.B.C + ABC + A.BC + ABC + ABC
Example 4.2: Let us simplify the following Boolean expression using kmap.
X = A.B.C + A.B.C + A.BC + A.B.C + A.B.C + ABC
The first step consists of filling the kmap. X
A BC
00 1 1
01 1 0
11 1 0
10 1 1
0 1
After grouping the ones, we can now deduce the simplified expression of the output:
X = A+C
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4.2.2.3 Kmap for four input Boolean variables: Let us consider the following Boolean expression:
X = A.BCD + A.BCD + ABCD + ABCD + ABC.D + ABC D + ABC D
This expression can be transferred in the kmap as follows:
X
CD AB
00 0 0 1 0
01 0 0 1 0
11 1 1 1 1
10 0 0 1 0
00 01 11 10
The simplified Boolean expression of the output can therefore be deduced:
X = AB + CD
Example 4.3: Consider the kmap bellow and give the simplified Boolean expression the output X:
X
CD AB
00 1 1 1 1
01 1 0 0 1
11 1 0 0 1
10 1 1 1 1
00 01 11 10
The simplified Boolean expression of the output is therefore determined:
X = B+D
Exercise 4.4: Simplify the following Boolean expression using kmap:
X = A.B.C.D + A..B.C.D + AB.C.D + A.B.C.D Y = A.B.C.D + A.B.C.D + A.B.CD + A.B.C.D + A.B..C.D + A.B.C.D + AB.CD + A.B.C.D
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Remark 4.2: Condition of indifference Some logic circuits are conceived in such a way that for certain combination of input variables, the output is neither high nor low. In fact, those input combinations should never occur. In the kmaps, the cells representing those combinations are filled with a X. Let us consider for instance the following truth table:
X
A
BC
00 0 0
01 0 X
11 1 1
10 We deduce that X 1 X=B
0 1
4.3 Conclusion: This chapter has permitted us to study Karnaugh mapping which is used for an easier simplification of Boolean expression. It is one of the most important tools that should be deeply understood in order to succeed in the study of combinatory logic circuit. The next chapter will be focused on the study of digital arithmetic. That is, on how digital systems perform arithmetical operations such as addition, subtraction, multiplication and division.
REVIEW QUESTIONS
1. Simplify the following Boolean expressions using kmaps:
Y = B+C B+C + A+ B+C
( )( ) Z = (C + D ) + AC D + AB.C + A..BCD + A.C.D
X = A.B.C + A.BC + ABC + AB.C + A.B.C
S = ABCD + A..B.C.D + A.B.C D + A.B.C.D + A.BCD + ABC.D + ABC D + ABC D + ABCD T = ABC + ABC + ABC + ABC
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2. For each of the following kmaps, determine the Boolean expression of the output X.
X
CD AB
X
CD
00 1 0 0 0
01 1 1 1 0
11 0 1 1 0
10 1 0 0 1
AB
00 1 1 1 1
01 1 1 1 1
11 1 0 0 0
10 1 1 1 1
00 01 11 10
00 01 11 10
X
CD AB
X
CD
00 0 0 1 0
01 0 0 1 1
11 1 0 1 1
10 0 0 1 0
AB
00 1 0 0 1
01 1 1 0 0
11 1 1 0 0
10 1 0 0 1
00 01 11 10
00 01 11 10
X
A
BC
X
00 0 0
01 1 1
11 1 1
10 0 0
BC A
00 0 0
01 0 1
11 1 1
10 0 1
0 1
0 1
X
A
BC
X
00 1 1
01 1 0
11 1 0
10 1 1
BC A
00 1 0
01 0 1
11 1 0
10 0 1
0 1
0 1
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References: 7. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 8. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits. 9. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER FIVE: DIGITAL ARITHMETIC
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Five
DIGITAL ARITHMETIC
5.0 Specific objectives: At the end of this chapter, the student will be able to perform arithmetical operations such as addition, subtraction, and multiplication using binary numbers
5.1 Introduction: Many arithmetical operations are carried out in digital systems like computers and calculators. The most common of these operations are addition, subtraction and multiplication. The aim of this chapter is to understand the principle used by digital systems to perform those operations.
5.2 Binary addition: The addition of two binary numbers is similar to that of two decimal numbers. Let us consider the following case: 354 +663 10 1 7 This operation is performed using the following steps: • • • We begin by adding the two less significant digits of the two decimal numbers: 3 + 4 =7. There is no carry out. Then we proceed by adding the two digits situated directly at the left: 5 + 6 = 11. We write 1 and the carry out is 1. We add the two next digits: 3 + 6 = 9; the carry out is added: 9 + 1 = 10. So the result of the addition is 1017. For binary number, the principle is the same. However, only four cases can be met while adding binary numbers: 0+0=0 1+0=1
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1 + 1 = 0 + a carry out of 1 1 + 1 + 1 = 1 + a carry out of 1.
Example 5.1: Let us add the following binary numbers: A = 1001 (910), B = 1111 (1510). 1001 +1111 11000 • • • • •
We begin by adding the two LSB (Least Significant Bit): 1 + 1 = 0 + carry out of 1. Then we add that carry to the two bits situated directly at the left: 0 + 1 + 1(Carry) = 0 + carry out of 1. The same operation is performed for the next rank. Then for the most significant bits, we have:
1 +1 + 1(Carry from the previous rank) = 11. Finally, the result of the operation gives us 11000 (2410).
Exercise 5.1: For each of the following cases, add the binary numbers A and B. a) A = 11101; B = 1001. b) A = 101111; B = 11111. c) A = 11101; B = 11111. 5.3 Signed numbers: In order to differentiate positive numbers to negative numbers, a specific bit can be added in front of the binary number. That bit is called bit of sign. The bit of sign is 0 for positive numbers and 1 for negative numbers. Example 5.2:
+9 = 01001 24 = 111000
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For negative binary numbers, there are two other types of notation: • • The one’s complement notation; The two’s complement notation.
5.3.1 The one’s complement notation: The one’s complement notation of a binary number is simply obtained by complementing each bit of the number. Let us write for example the one’s complement of the following binary number: 10010110 10010110 01101001 Exact notation One’s complement notation
Remark 5.1: For negative binary numbers, we should not forget the bit of sign: 11101 10010 Exact notation One’s complement notation.
Notice that the bit of sign is not complemented. Exercise 5.2: Give the one’s complement of the following binary numbers. a) 101101; b) 1101101 (signed number); c) 011101011 (signed number).
5.3.2 The two’s complement notation The two’s complement notation of a binary number is obtained by adding 1 to the one’s complement notation of that number. 110110 001001 + 1 Two’s complement notation Exact notation One’s complement notation
001010
For signed number, remember that the bit of sign remain unchanged. Exercise 5.3: Give the two’s complement of the following binary numbers. b) 101101; b) 1101101 (signed number); c) 011101011 (signed number).
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We can recapitulate all what we have studied concerning one’s and two’s complementation in the following table: Decimal +24 24 Exact notation 011000 111000 One’s complement 011000 100111 Two’s complement 011000 101000
Notice that for positive numbers, exact notation does not differ from one’s complement and two’s complement notation. 5.3.3 Conversion from one’s complement and two’s complement notation to exact notation: To convert from the one’s complement notation to the exact notation, each bit of the one’s complement notation should just be complemented back. 111000 100111 111000 Exact notation. One’s complement notation. Exact notation.
Notice that the bit of sign does not change. To convert from two’s complement notation to the exact notation, the two’s complemented number should just be two’s complemented back. 1001 0110 + 1 Two’s complement notation Exact notation
0111 1000 + 1
1001
Exact notation
5.4 Addition of two signed numbers: Depending on the sign of the two numbers to be added, many cases can be studied. Case 1: Two positive numbers: Let us add +4 to +9. +9 = 01001 +4 = 00100
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+9 +4 +13
01001 +00100 01101 The two numbers to be added should have the same number of bit and they
should also be written in two’s complement notation. Exercise 5.4: In each of the following cases add numbers A and B after having converted them in binary: a) A = +10; B = +12; b) A = +3; B = +20; c) A = +45, B = 19.
Case 2: Positive number and negative number (less than the positive number). Let us add +9 and 4. Decimal +9 4 Exact notation 01001 10100 2’s complement 01001 + 11100 100101
The result gives us 100101: The first bit 1 is not taken in consideration. The second bit 0 is the bit of sign, so the result of the operation is 00101 = 510. Case 3: Positive number and negative number greater (greater than the positive number) The result of this operation should give a negative number written in two’s complement notation. Therefore, that result should later on be converted from two’s complement notation to exact notation. Decimal 9 +4 Exact notation 11001 00100 2’s complement 10111 + 00100 11011 Result in 2’s complement notation
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Let us convert now the result from two’s complement to exact notation 11011 10100 + 1 Final result The final result is 10101= 510. Exercise 5.5: Solve the following operations in binary: a) 810  510 b) 1210  610 c) 610  1210 d) 510  1210 Case 4: Two negative numbers Let us add 9 and 4: Decimal 9 4 Exact notation 11001 10100 2’s complement 10111 + 11100 110011 Result in 2’s complement notation
10101
The first bit of the result in two’s complement is not taken in consideration. Let us convert the result from two’s complement notation to exact notation: 10011 11100 + 1 Final result
11101
The final result is 111012=  1310.
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Case 5: Two opposite numbers Let us add 9 and +9 Decimal 9 +9 Exact notation 11001 01001 2’s complement 10111 + 01001 100000 Result in 2’s complement notation
The first bit of the result in two’s complement is not to be taken in consideration. By converting the result from two’s complement notation to the exact notation, we stiil obtain 0. 00000 01111 + 1 Final result
10000
The result in exact notation gives us 100002 = 010. Remark 5.2: Subtraction of binary numbers The subtraction of two binary numbers can easily be transform into addition, for example: +9 – (+4) = +9 + (4) +9 – (4) = +9 + (+4) Remark 5.3: Overtaking Let us add +9 and +8 Decimal +9 +8 Exact notation 01001 01000 2’s complement 01001 + 01000 10001=1710 Result in 2’s complement notation
The first bit of the result should be normally considered as the bit of sign. But if we do so, it means that there is an error (because the result will be 110 Iinstead of 1710). That error is called overtaking error because we need one more bit (over bit) to well represent the result of the operation which is 0100012 = +1710.
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In digital systems, there are special circuits intended to detect overtaking errors during calculations. 5.5 Multiplication of binary numbers: The multiplication of two binary numbers is similar to that of two decimal numbers. Let us multiply 910 (10012) and 310(00112). Decimal +9 +3 Exact notation 01001 00011 2’s complement 01001 x 00011 01001 01001 011011
The final result gives us 0110112 = 2710. The bits of first number (9) have just been multiplied by each of those of the second number (3), beginning from the right to the left. It should also be noticed that, while passing from one line to the next, we should shift from one position to the left. Let us multiply 5 and +4: Decimal 5 4 Exact notation 1011 0100 2’s complement 1011 x 0100 0000 0000 1011 101100 Result in 2’s complement notation
Let us convert the result from 2’s complement notation to the exact notation: 101100 110011 +1 110100 Final result
The final result gives us 1101002 = 2010.
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Exercise 5.6: Calculate the following: a) 6 x 4 b) 3 x +5 c) 5 x +6
5.6 Addition of DCB numbers: As we have already seen in the first chapter, to convert a number from decimal system of numeration to DCB code, each digit of the decimal number should be replaced by its binary equivalent in four bits. Valid DCB codes go from 0000 (010) to 1001(910). The addition of two DCB numbers is almost similar to that of binary numbers. However, when the result of the operation gives us numbers that do not belong to DCB range of valid codes, a correction should be done on the found result by adding 1102 to it. 4510 3310 0100 0101 + 0011 0011 0111 1000 7 8
The final result gives us 0111 1000(DCB) = 7810 610 710 0110 + 0111 1101 13 (invalid DCB code)
The result gives us 1101 = 1310 (in four bits) which is an invalid DCB code. To correct this result, 110 should be added to it. 1101 + 110
0001 0011 1 3
The final result gives us 0001 0011(DCB) = 1310
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Exercise 5.7: Add the following number after converting them in DCB: a) 5410 + 2310 b) 4910 + 25 10 c) 5510 + 6910 5.7 Addition and subtraction of hexadecimal numbers: • 58 +24 7C16 In fact, 8 + 4 = 12 (C16) 58 +4B A316 In fact, 8 + B = 1910 (1316). We write 3 and the carry out (which is 1) is added to the rank directly at the left. Addition:
Let us add the following hexadecimal numbers:
Exercise 5.8: Add the following: a) 2A + 56 b) 3AF + 5EB c) F8C + 7B • 1A  CF The first step of the solution is to determine the two’s complement of CF. Subtraction
Let us solve the following:
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CF
1100 1111 0011 0000 + 1
0011 0001 3 1
Then the operation can be solved just as a simple addition: 1A +31 4B
5.8 Conclusion The present chapter has permitted us to know how to perform basic arithmetical operations such as addition, subtraction and multiplication involving binary numbers. Operations with hexadecimal and DCB numbers have also been introduced. The next chapter is focused on the study of basic combinatory logic circuits. Those circuits are elements used in the conception of complex logic systems.
REVIEW QUESTIONS
1. Determine the one’s complement of the following binary numbers: a) 1100101.11 b) 100101011 c) 0110110.11 (signed number) d) 1110111.1101 (Signed numbers) 2. Determine the two’s complement of the binary numbers given in the exercise above (exercise 1). 3. Perform the following operation after converting each number involved to binary: a) +9 + (+4) b) 9 + (5)
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c) +29 + (+7) d) +3 + (21) e) +14  (45) f) 22 – (+12) g) +12 x (+4) h) – 5 x ( 4) 4. Add the following DCB number and correct the result if necessary: a) 0110 1001 + 1000 0101 b) 1001 0110 + 0111 0001 c) 0100 0011 + 0101 0100 5. Perform the following operations involving hexadecimal numbers: a) 4EB + 7C b) 54 +69 c) 7FF23 d) 6FC+5BC
References: 10. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 11. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits. 12. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER SIX: COMBINATORY LOGIC
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Six
COMBINATORY LOGIC
6.0 Specific objectives: At the end of this chapter, the student will be able to: Design basic combinatory logic circuits such as the adder, the decoder, the encoder, the transcoder, the multiplexer, and the demultiplexer. Give the applications of those circuits in various domains of Engineering Sciences. 6.1 Introduction: Complex digital systems like computers are made up of many simple combinatory, sequential and hybrid (combinatory and sequential) circuits connected together. A combinatory logic circuit is a logic circuit whose outputs depends only on the combination of its inputs logic states. One of the most important circuits of a computer, which is the Arithmetical and Logical Unit (ALU), is made up of simple circuits capable of performing operations such as addition, multiplication, subtraction and division. The aim of this chapter is to learn how to design simple combinatory circuits used in the conception of digital systems.
6.2 Principle of addition in digital systems: Computers can add only two binary numbers at once. These numbers can have up to 64 bits, with respect to the width of the data bus of the mother board. Let us consider two binary numbers of 5 bits each to be added. 10111 + 00101 11100 00111 Number A Number B Sum (A + B) Carry out
We start the operation by adding the two LSB of the numbers A and B: 1 + 1 = 102 (Sum = 0; Carry out = 1). The carry out is added to the bits of the rank situated immediately at the left.
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The same operation will be repeated for the other ranks, until the addition is completed. There is a special circuit which is able to perform this operation: It is the full adder. The following figure gives us the principle of the addition involving many full adders: B2 B1 B0
C3
C2 FA2 FA1
C1 FA0
C0
...
S2
A2
S1
A1
S0
A0
Figure 6.1: Principle of addition Each element of the circuit above represents a full adder. Each full adder is intended to add one bit of the number A to the bit of the number B having the same weight. The two numbers to be added should have the same number of bits. So, if the two numbers to be added have five bits each, the addition will be performed using five full adders connected in parallel as shown above.
6.3 The full adder: As presented above, the full adder is combinatory logic circuit intended to add two bits. The principle diagram of a full adder is given by the figure bellow: A
S FA Cout
Cin
Figure 6.2: Principle diagram of a full adder B
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The full adder has three inputs: A: bit from number A; B: Bit from number B; Cin: Carry out coming from the previous rank.
And two outputs: • A 0 0 0 0 1 1 1 1 • S: the bit of sum; Cout: The carry out (to be added to the bits of the next rank).
Truth table:
B 0 0 1 1 0 0 1 1
Ci 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
Co 0 0 0 1 0 1 1 1
Equations of the outputs : We can either use Boolean algebra or kmap to determine the equations of
the outputs. Using Boolean algebra:
S = A.BCi + ABCi + AB.Ci + ABCi
) ( = A(B ⊕ C ) + A(B ⊕ C ) Let X = (B ⊕ C )
in i i
= A BCi + BCi + A B.Ci + BCi
(
)
S = AX + A X
= A⊕ X = A ⊕ B ⊕ Ci
S = A ⊕ B ⊕ Ci
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Co = A.BCi + ABCi + ABCi + ABCi
The expression will not change if one of the elements of the sum of products is duplicated (After the Boolean additive identity according to which A + A = A, A being a Boolean variable). So we will duplicate the product ABCi three times in order to simplify the expression easily.
Co = A.BCi + ABCi + ABCi + ABCi + ABCi + ABCi
= BCi A + A + ACi B + B + AB Ci + Ci = BCi + ACi + AB
Co = BCi + ACi + AB S
A BCi
(
)
(
)
(
)
Using kmap: 00 01 1 0 11 0 1 10 1 0
0 1
0 1
S = A.BCi + ABCi + AB.Ci + ABCi
S = A ⊕ B ⊕ Ci
Co
A
BCi
00 0 1 0 0
01 0 1
11 1 1
10 0 1
Co = BCi + ACi + AB
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•
A B
Logic diagram
Ci Ri
S
Ro Co
6.4 The half adder: The half adder has two inputs A and B which are the two bits to be added, and two outputs which are the sum output S and the carry output Co. The principle diagram of the half adder is given by the following diagram.
A HA B
S
Co
Figure 6.3: Principle diagram of a half adder •
Truth table: A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 Co 0 0 0 1
•
Equations of the outputs
S = A.B + A.B S = A⊕ B Co = A.B
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Exercise 6.1: Consider the following digital system made up of two half adders and an OR gate. Establish the truth table of the system and draw a conclusion. A B DA So
Co
S DA
Ci Co
6.4 The Subtractor: As we have seen in the previous chapter, the subtraction of a number B from a number A can be treated as the addition of the number A with the two’s complement of the number B. A − B = A + (− B) = A + C2 ( B) = A + ( B + 1) 6.4.1 The half subtractor: The half Subtractor performs the subtraction of a number having one bit from another number having one bit. It has two inputs which are the two numbers A and B to be added, and two outputs Di and Co which are respectively the difference and the carry out. • Truth table
A 0 0 1 1 Remark 6.1:
B 0 1 0 1
Di 0 1 1 0
Co 0 1 0 0
0 – 1 = 1 = 11(Two’s complement notation) ⇒ 1 and carry out of 1
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•
Equations of the outputs:
Di = A.B + A.B = A ⊕ B
Co = AB
•
Logic diagram:
A
Di
B Ro Co
6.4.2 The full subtractor : The structure above can be modified to achieve subtractions involving numbers having more than one bit. In fact, such operation is performed by a full subtractor. It has then an additional input Ci which is the Carry in (from the previous rank). • A 0 0 0 0 1 1 1 1 Truth table: B 0 0 1 1 0 0 1 1 Ci 0 1 0 1 0 1 0 1 Di 0 1 1 0 1 0 0 1 Co 0 1 1 1 0 0 0 1
Remark 6.2: 0 – 1 – 1 = 1102 (210 in two’s complement notation) ⇒ 0 and carry out of 1.
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•
Di
A BCi
Equations of the outputs:
00 0 1 0 1
01 1 0
11 0 1
10 1 0
Di = A.B.Ci + A.B.Ci + AB.Ci + ABCi
) ( = A(B ⊕ C ) + A(B ⊕ C )
i
= A B.Ci + B.Ci + A B.Ci + BCi
(
)
= A ⊕ B ⊕ Ci Di = A ⊕ B ⊕ Ci
Co
A
BCi
00 0 1 0 0
01 1 0
11 1 1
10 1 0
Co = A.Ci + A.B + BCi
•
A B
Logic diagram
Ri Ci
Di
Co Ro
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6.5 The comparator A comparator is a combinatory logic circuit which is intended to detect among two binary numbers the one which is the greater (or the smaller). It detects also the equality of the two numbers. The numbers to be compared should have the same number of bits. Let us design a comparator for two numbers having one bit each. • Truth table: • S2 S3 Equations of the outputs
S1 A 0 0 1 1 •
A B
B 0 1 0 1
(A>B) (A=B) (A<B) 0 0 1 0 1 0 0 1 0 1 0 0
S1 = A.B S2 = A ⊕ B S3 = A.B
Logic diagram
S1
S2
S3
Exercise 6.2: Design a logic circuit which is able to compare two numbers having two bits each.
6.6 The decoder: The decoder is a combinatory logic circuit which functions in such a way that for a given input address, only one of its outputs is activated. The principle diagram of the decoder is presented by the following figure:
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I0 . . . IN1 . . .
O0
Decoder N to M
OM1 M outputs, only one is activated
N inputs
Figure 6.4: Principle diagram of a decoder. The Input address is a binary code of N bits. For N bits, there are 2N possible input addresses. So, the decoder has M = 2N outputs such that, for each input address, only one output can be activated among the 2N available. Let us design a decoder having three inputs (And therefore 2N = 8 outputs). Such a decoder is also called a 3 to 8 decoder. • A 0 0 0 0 1 1 1 1 •
Truth table:
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
O0 1 0 0 0 0 0 0 0
O1 0 1 0 0 0 0 0 0
O2 0 0 1 0 0 0 0 0
O3 0 0 0 1 0 0 0 0
O4 0 0 0 0 1 0 0 0
O5 0 0 0 0 0 1 0 0
O6 0 0 0 0 0 0 1 0
O7 0 0 0 0 0 0 0 1
Equations of the outputs:
O4 = A.B .C O5 = A.B .C O6 = A.B.C O7 = A.B.C
O0 = A.B .C O1 = A.B .C O2 = A.B.C O3 = A.B.C
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•
A
Logic diagram:
B C
O0
O1
. . .
O7
•
Applications of decoders The applications of decoders are found in many digital systems. Here are
some of them.
a) Addressing of a memory: A memory is made up of registers which contain memory words. Addressing a memory consist of allocate to each register a particular code which permits to identify it and also to get access to the data stored within it. Let us consider a memory having 16 registers, each register storing a memory word of 8 bits (1 byte). We want to address that memory so that, for each address code sent to the memory, only one register will be accessible. To solve this problem, we can use a decoder having 4 inputs and 24 = 16 outputs. Each output will be connected to one of the 16 registers such that, for each of the 16 possible input addresses, only one register can be selected. The following figure presents the synoptic diagram of the system.
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Ligne 0
10100110
Address Decoder 4 to 16
Register storing one byte
4
Ligne 15
. . .
Chip select
Figure 6.5: Addressing of a memory having a capacity of 16 bytes b) DCB – seven segments decoder: In many systems, seven segments displays are used to represent numbers from 0 to 9 and sometimes alphabetical characters.
Each segment is made up of one or two LED
Figure 6.6: Seven segment display. The DCB  seven segments decoder accepts at its inputs a DCB code of four bits, and activate its outputs which will permit to enlighten the LEDs representing the corresponding cipher (corresponding to the DCB code). Protective resistor
a b DCD input codes DCB – 7 Segments decoder c . . . g
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Let us design a DCB – Seven segment segments decoder which will permit us to represent digital numbers from 0 to 9 on a 7 segments display.
D 0 0 0 0 0 0 0 0 1 1
Truth table: C 0 0 0 0 1 1 1 1 0 0
a
B 0 0 1 1 0 0 1 1 0 0
A 0 1 0 1 0 1 0 1 0 1
a 1 0 1 1 0 1 1 1 1 1
b 1 1 1 1 1 0 0 1 1 1
c 1 1 0 1 1 1 1 1 1 1
d 1 0 1 1 0 1 1 0 1 1
e 1 0 1 0 0 0 1 0 1 0
f 1 0 0 0 1 1 1 1 1 1
g 0 0 1 1 1 1 1 0 1 1
•
f g b
Equations of the outputs :
a = D.C.B. A + D.B.C. A
a = D+C + B+ A. D+C + B+ A
(
)(
)
e
c
d
Exercise 6.3: Determine the Boolean expressions for the others outputs.
Exercise 6.4: The following system uses a 3 bits – segments decoder to represent the letters ABCDEFGH on a seven segments display. Design that decoder after filling its truth table.
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a
A B C
3 to seven segment decoder
f g
b
e
c
d
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
a 1
b 1
c 1
d 0
e 1
f 1
g 1
Display A B C D E F G H
a) Fill the truth table; b) Determine the Boolean expressions of the output a,b,c,d,e,f,g; c) Draw the logic diagram of the circuit.
Exercise 6.5: Design a DCB – Decimal decoder. It is a decoder whose inputs are the four bits of the DCB code and who has ten outputs.
6.7 The encoder: The encoder is a combinatory logic circuit which outputs an exclusive binary code when each of its inputs is activated. When one of its inputs is activated, a binary
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code corresponding to that input is sent to the output. The encoder does the reverse of the decoder. Encoder circuits are used in the conception of keyboards.
I0
O0
. . . IM1
Encoder
. . . ON1
M inputs, only one among them is high
Binary code at the output
Figure 6.7: Principle diagram of an encoder
Let us realise an 8 to 3 encoder. It is a combinatory logic circuit having 8 inputs an 3 outputs which functions in such a way that, when an input is activated, a corresponding binary number coded in three bits is sent to the output. • I0 1 0 0 0 0 0 0 0
Truth table: Only one among the eight inputs should be activated at once. I1 0 1 0 0 0 0 0 0 I2 0 0 1 0 0 0 0 0 I3 0 0 0 1 0 0 0 0 I4 0 0 0 0 1 0 0 0 I5 0 0 0 0 0 1 0 0 I6 0 0 0 0 0 0 1 0 I7 0 0 0 0 0 0 0 1 O2 0 0 0 0 1 1 1 1 O1 0 0 1 1 0 0 1 1 O0 0 1 0 1 0 1 0 1
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•
Equations of the outputs: The equation of each output is simply the Boolean addition of all the inputs for
which that outputs is at the high logic level. Hence, O2 = I 4 + I 5 + I 6 + I 7 O1 = I 2 + I 3 + I 6 + I 7 O0 = I1 + I 3 + I 5 + I 7 •
Logic diagram:
I0 I1
O0
I2 I3 I4 I5 I6 I7
O1
O2
When no input is activated, the circuit outputs automatically 000. That is why the input I0 is not connected.
Exercise 6.6: Design a decimal – DCB encoder. It is an encoder having 10 inputs representing the 10 digits of the decimal system of numeration, and 4 outputs intended to produce DCB codes corresponding to each input when it is activated.
Remark 6.2: encoder with priority The encoder designed above would produce a wrong result if two inputs were activated at the same time. There are encoders with priority circuits which functions in such a way that, if two or more inputs are activated at once, the binary code sent to the output is that of the input having the highest value. For instance, if the inputs I2, I5 and I6 are activated the same time, the encoder will output the binary code 110 corresponding to the input I6.
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Exercise 6.7: Design a digital system which permits to display the 10 symbols of the decimal system of numeration on a 7 segments display using a 10 buttons keyboard.
6.8 The transcoder: The transcoder is a combinatory logic circuit which converts a given binary code into another binary code. For instance, let us design binary to Gray encoder. It is a circuit which receives at its inputs binary numbers and outputs corresponding Gray codes.
Binary system
Binary to Gray transcoder
Gray Code
Figure 6.8: Principle diagram of a binary to Gray transcoder •
Truth table:
Binary code A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 X 0 0 0 0 1 1 1 1
Gray code Y 0 0 1 1 1 1 0 0 Z 0 1 1 0 0 1 1 0
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•
X
A BC
Equations of the outputs:
00 0 1 0 1
01 0 1
11 0 1
10 0 1 X=A
Y
A
BC
00 0 1 0 1
01 0 1
11 1 0
10 1 0
Y = A.B + A.B Y = A⊕ B
Z
A
BC
00 0 1 • 0 0
01 1 1
11 0 0
10 1 1
Z = B .C + B.C Z = B⊕C
Logic diagram:
A
X Y
B
C
6.9 : The multiplexer:
Z
A multiplexer also called data selector is a combinatory logic circuit which permits to direct towards single output information coming from many inputs. According to the address received by the multiplexer, only one among the information available at its inputs is selected and directed toward the output. A multiplexer can be
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considered as a commutator having multiple poles which are switched according to the address sent to the multiplexer. 2n data inputs
n address inputs
MUX E
Output Figure 6.9: Principle diagram of a multiplexer
E is the enable input. It enable the multiplexer to function when the right logic
signal level is sent to it (For the principle diagram above, the right signal level is slow). For an address bus having n lines, up to 2n data can be addressed such that for each of these addresses, one among the 2n data is selected and directed towards the output. Let us design an elementary multiplexer. It is a multiplexer having two data inputs I0 and I1 and one address input A. I0 I1
Address A
Mux
Output
The address can be either 0 or 1. When the address is 0, the datum I0 is selected and sent to the output. When the address is 1, I1 is selected and directed towards the output.
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•
Truth table:
A 0 1
S I0 I1
S = I 0 A + I1 A
When A = 0, we have:
S = I 0 . 0 + I1.0 S = I0
The information I0 is therefore directed to the output. That information can be a logic state or even a set of data coded in many bits. When A = 1, we have:
•
I1
1 3 2
S = I 0 . 1 + I1.1 S = I1
Logic diagram:
S
I0
A
Let us design now a more complex multiplexer; it is a multiplexer having four data inputs. For 4 data, we need 2 address lines to address all the information.
•
Truth table:
A 0 0 1 1 B 0 1 0 1 S I0 I1 I2 I3
S = A .B .I 0 + A.B.I1 + A.B .I 2 + A.B.I 3
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•
I0
Logic diagram:
I1 S I2
I3
A
B
Exercise 6.8: Design a multiplexer having 8 data inputs •
Application of multiplexer:
The applications of multiplexers are found in many digital systems. These are some of those applications:

Parallel to series conversion: In many digital systems, the treatment of information is done in parallel;
however, when those information are to be transferred on a long distance, this cannot be done in parallel. In fact, parallel transfer of information is not effective because it requires a large number of lines trough which data will flow; on the other hand, its causes a lot of errors in data transfer. The parallel to series conversion permits to make in such a way that the information treated in parallel can be transferred in series trough a single line. A parallel to series converter can be realised using a multiplexer as shown by the following figure:
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I0 I1 I2 I3 I4 I5 I6 I7 Multiplexer with 8 data inputs The modulo 8 counter
generate successively addresses from 000 to 111. Each of those Series output addresses permits to direct
towards the series output one of the 8 bits stored in the register.
Register containing data in parallel
Modulo 8 counter
Figure 6.10: Parallel to series converter

Realisation of logic functions: Logic functions can be realised using multiplexers. Let us consider a logic
function described by the following truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S 0 1 0 0 0 1 1 0 I0 I1 I2 I3 I4 I5 I6 I7
This function can be realised without using logic gates. We can use a single multiplexer integrated circuit having 8 data inputs. The principle consist in connecting the outputs having low logic level to the earth and those having high logic level to the positive probe of the supply Vcc, as shown by the following figure:
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Vcc
E
A B C
I0 I1 I2 I3 I4 I5 I6 I7 MUX
S Figure 6.11: Realisation of a logic function using a multiplexer.
Exercise 6.9: Consider a combinatory logic circuit described the following truth table:
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
S 1 1 0 1 0 1 0 1
a. Design the circuit and draw its logic diagram using logic gates. b. Realise the same logic function using a multiplexer.
Exercise 6.10: Realise a multiplexer having 4 data inputs using a 2 to 4 decoder and logic gates of your choice.
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6.10 The demultiplexer: The demultiplexer is a combinatory logic circuit which permits to direct towards many outputs information coming from a single input. The demultiplexer has n address inputs and 2n outputs such that, when an address is sent to it, the information is directed towards the corresponding output (the information is sent to only one among the 2n available outputs).
One data input
n address inputs
DEMUX
2n Outputs Figure 6.12: Principle diagram of a multiplexer.
Let us realise a multiplexer having four outputs (and therefore 2 address inputs). • A 0 0 1 1 Truth table: B 0 1 0 1 O0 I 0 0 0 O1 0 I 0 0 O2 0 0 I 0 O3 0 0 0 I
O0 = A.B .I O1 = A.B.I O2 = A.B .I O3 = A.B.I
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•
Logic diagram:
A B
I
O0
O1
O2
O3
Exercise 6.11: Design a demultiplexer having 8 outputs.
6.11 Conclusion: The present chapter has permitted us to study many of the most common combinatory circuits. The particularity of those type of circuits was that the logic state of their outputs at a given instant depends only on the combination of the logic states of their inputs. The next chapter will deal with sequential logic. The output of a sequential logic circuit depends not only on the combination of its inputs logic states, but also on the memory of the circuit. The chapter will start with the study of multivibrators (latches and flipflops) which are tools used in the conception of sequential logic circuits.
REVIEW QUESTIONS
1. (From Probatoire F3, 2009 session). Full adder. The figure 6.13 below represents the circuit of a full adder, where A1 and B1 are the variable inputs. R1 is the carry while So and Ro are the sum and the reminder respectively. A1 B1 R1 So Ro
Full adder Figure 6.13: Full adder.
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a. Complete the truth table below.
A1 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1
R1 0 1 0 1 0 1 0 1
So
Ro
b. Simplify the expressions of So and Ro using the Boolean algebra method. c. Simplify the expressions of S0 and Ro using kmaps. d. Using the logic gates, draw the logigram of this full adder.
2. (From Probatoire F3, 2011 session). Parity detector We desire to realise a 3bit parity detector of bits B1, B2 and B3. The operation is as follows: If 0 or 2 bits are at high logic level (logic level 1), the output is at the high logic level (logic level 1). If 1 or 3 bits are at high logic level, the output is at low logic level (level 0).
a. Establish the corresponding truth table. b. Give the Boolean expression of the output S in terms of B1, B2 and B3. c. Write the expression of S using the operator ExclusiveOR. d. Draw the logic diagram of S.
3. (From Probatoire F3, 2007 session). Electronic multiplicator circuit. The figure 6.14 below shows the block diagram of an electronic circuit which accepts two binary numbers of two bits X1X0 and Y1Y0 and gives at the output the binary number Z3Z2Z1Z0 which is equal to the arithmetic product of the two input numbers. For the inputs, X0 and Y0 are the least significant bits (LSB) while fore the outputs, Z3 is the most significant bit (MSB) and Z0 is the least significant bit.
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X1 X0 Multiplicator circuit Y1 Y0
Z3 Z2
Z1 Z0
Figure 6.14: Multiplicator circuit.
a. What do you understand by the statements “Least Significant Bit” and “Most Significant Bit”? b. Establish the truth table of the system. c. Write the expression of each of the outputs Z3, Z2, Z1 and Z0 as function of X1, X0, Y1 and Y0. d. Using kmaps, simplify the output equations obtained from above. e. Draw the logic diagram of the electronic multiplicator circuit using the simplified output equations from the kmaps: Using AND gates only Using NAND and NOR gates only.
4. (From Probatoire 2007). Multiplexer circuit. Consider the diagram of the figure 6.14 bellow. It is a multiplexer connected as a function generator.
GND (0) Vcc (1)
A B C D E0 A1 A2 A3 E1 E2 E3 E4 E5 E6 E7
V
S
Figure 6.14: Multiplexer as function generator.
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a. Identify the inputs of this multiplexer and give their roles. b. Give the output equation of the function S. c. Simplify that equation using kmap d. Realise the simplified function using twoinputs NAND gates exclusively.
5. (From GCE A Level, 2000 session). A factory crane operator is to control red and green safety lights by four switches A, B, C and D. Design a simple logic system which will operate under the following conditions: Red light ON for: Switch A ON and switch B OFF or Switch C ON.
Green light ON for: Switches A and B ON and Switches C and D OFF.
NB: In designing you should respect the following steps: a. Establish the truth table. b. Write the equations of the outputs. c. Simplify the equations if possible. d. Draw the logic circuit.
References: 13. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 14. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits. 15. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER SEVEN: SEQUENTIAL LOGIC PART A: MULTIVIBRATORS
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Seven
MULTIVIBRATORS
7.0 Specific objectives: At the end of this chapter, the student will be able to: Define sequential logic and differentiate it from combinatory logic; Master the functioning of different types latches and flipflops; Use the IC NE555 as monostable and as astable multivibrator.
7.1 Introduction: The sequential logic studies digital circuits which functions in such a way that their outputs logic states depend not only on the logical combination of their inputs states, but also on the memory of the circuit. In fact, at a given instant, sequential circuits always store the status of their output and that status cannot change unless new logic signals are sent to its inputs: this is the memory effect. The simplest sequential logic circuit is the latch which is a circuit capable of storing one bit of information. It has two outputs, one being the reverse of the other. A flipflop is an edge triggered latch; it means that it cannot function unless the right signal edge (either rising or falling edge) is available at its clock input. This chapter is an introduction to sequential logic; it is focused on the study of latches and flipflops which are tools used in the designing of sequential circuits.
7.2 Multivibrators: Let us consider the following circuit:
Input A
Output
According to the functioning of the OR gate, if A = 1, the output must be 1. However, if A is in low logic state, we cannot guarantee the logic state of the output.
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Since the output feeds back to one of the OR gate inputs, this circuit will “latch” (That is to remain unchanged) in the 1 output state after any time that A is 1. In fact, when A = 0, the output could be 0 or 1 depending on the circuit previous state. So the output maintains (or memorises) its last state when A is 0. The truth table of our circuit can be given as follow.
Input A 0 1
Output latch 1
Any circuit employing feed back is called multivibrator. A bistable multivibrator can hold stable in one of two possible states (either 0 or 1). Monostable multivibrator holds stable only in one output state, the other state being momentary. Astable multivibrator has no stable state. It oscillates back and forth between an output of 0 and 1. One of the most common multivibrators is the integrated circuit NE555, which can work as well as monostable or astable.
7.2.1 Latches: Many latches exist, but their common characteristic is that they can store one bit of information. 7.2.1.1 The SR latch: The SR latch is a bistable multivibrator having two stable states: Set and Reset. So SR latch means SetReset latch. To create an SR latch, can wire two NOR gates in such a way that the output of one feeds back the input of another, and vice versa.
R
Q
S
/Q
Figure 7.1: Principle diagram of an SR latch.
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• S 0 0 1 1
Truth table:
R 0 1 0 1
Q
/Q Latch
0 1
1 0 invalid

The outputs Q and /Q should always be in opposite logic states. Making both S and R inputs equal to 1 results in both Q and /Q being 0: this is why this inputs combination is forbidden, it produces an invalid or illegal state.
•
Making S = 1 and R = 0 sets the multivibrator so that Q = 1 and /Q = 0. Making R = 1 and S = 0 resets the multivibrator so that /Q = 1 and Q = 0. When R = 0 and S = 0 the multivibrator outputs lath in their previous states.
Circuit diagram:
S
Q
R
/Q
Exercise 7.1: The following waveforms are applied at the inputs of an SR latch. Deduce the waveform of the output assuming that the initial state of the output is Q = 0.
S
t R
t Q
t
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The waveforms of the output Q of the exercise above can be given as follows:
S
t R
t Q
t
7.2.1.2 The gated SR latch: The gated SR latch has an enable input E which must be activated in order to allow the latch to take into consideration the combinations available at its inputs. The latch would not function properly unless the right logic level is sent to the input E. the principle diagram of a gated SR latch is given bellow.
R Q E /Q S
Figure 7.2: Principle diagram of a gated SR latch.
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• E 0 1 1 1 1
Truth table: S X 0 0 1 1 R X 0 1 0 1 0 1 Invalid Q /Q Latch Latch 1 0
When E = 0, the outputs of the two AND gates are forced to 0, regardless of the states of either S or R. The previous states of the outputs are therefore memorised. Only when the enable input is activated (by sending a 1 to it) will the latch respond to the S an R inputs. •
Circuit diagram:
S E R
Q
/Q
Exercise 7.2: The following waveforms are applied at the inputs of a gated SR latch. Deduce the waveform of the output assuming that the initial state of the output is Q = 0.
S
t R
E
t
Q
t
t
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The waveform of the output Q of the exercise 7.2 above can be given as follows:
S
t R
E
t
Q
t
Invalid interval: The previous state is memorised.
t
7.2.1.3 The D latch: The D latch has no illegal input state because the inputs S and R are always in opposite state. The principle diagram of a D latch is given bellow:
Q E /Q D
Figure 7.3: Principle diagram of a D latch. • E 0 1 1
Truth table: D X 0 1 0 1 Q Latch 1 0 /Q
When the enable input is high, the output Q copies the state available at the input. When E = 0, the circuit remain latched in its previous state.
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•
D E
Circuit Diagram:
Q
/Q
An application for D latch is a 1 bit memory circuit. You can store a 0 or 1 bit in a D latch by making the enable input high and setting the input D to whatever you want the stored bit to be.
Remark 7.1: Designing a D latch using an SR latch. The D latch is nothing more than a gated SR latch with an inverter added to make the complement of S, as shown in the following diagram.
S D Q
E R /Q
Exercise 7.3: The following waveforms are applied at the inputs of a D latch. Deduce the waveform of the output assuming that the initial state of the output is Q = 0.
D
t E
t Q
t
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The waveform of the output Q of the exercise 7.3 above can be given as follows.
D
t E
t Q
Valid interval
t Valid interval
We can notice that within the valid interval, the output of the D latch just copies the waveform of the input. When the enable input is made low, the latch ignores the status of the D input and merrily holds the stored bit value.
7.2.2 The edge triggered latches: Flipflops We have studied both SR and D latch circuits with an enabling input. The latch responds to input’s data only when the enabling input E is activated. In many digital applications however, it is desirable to limit the responsiveness of a latch circuit to a very short period of time instead of the entire duration that the enabling input is activated. Another method of enabling a multivibrator circuit is called edge triggering. For this method, the circuit’s data inputs have control only during the time during which the enabling input is transitioning from one state to another. There are two types of edge triggering: If the enabling input functions when transitioning from low state to high state (from 0 to 1), the latch is said to be positive edge triggered. If the enabling input functions when transitioning from high state to low state, the latch is said to be negative edge triggered.
1 0 Positive edge 1 0 Negative edge
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Any latch whose enable input is edge triggered is a flipflop. So we can say that a flip flop is an edge triggered latch. An SR flipflop is an edge triggered SR latch and a D flipflop is an edge triggered D latch.
7.2.2.1 Edge triggered D latch: D flipflop: Let us study a positive edge triggered D latch. It responds to the D input only during the brief instant when the enabling signal transitions from low to high. The principle diagram of D flipflop is given as follows.
D
Q
Clock signal
Pulse detector
E /Q
Figure 7.4: Principle diagram of a D flipflop.
Remark 7.2: The pulse detector A pulse detector is connected to the enable input of the latch. It is a circuit that outputs a brief pulse when the right transition of the clock signal occurs (either rising or falling transition).
Clock signal
Clock Signal
Pulse detector
Enabling input
t
Enabling input
t
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The pulse detector enables the latch for a brief moment; after the pulse, the latch holds its output at the same state till another pulse occurs. • Clock Truth table:
D X 0 1
Q Latch 0 1
/Q
1 0
The input D will have no effect unless the clock signal is transitioning from low to high. Otherwise, the flipflop’s outputs latch in their previous states. •
Circuit diagram:
D Clock
Q
/Q
If we had a negative edge triggered D flipflop, the circuit diagram would have been as follows.
D Clock
Q
/Q
Exercise 7.4: The following waveform is applied at the inputs of a positive edge triggered D flipflop. Determine the waveform of the output Q assuming that it is initially at low logic state.
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Clock
t
D
t
Q
t
The waveform of the output Q of the exercise 7.4 above can be given as follows.
Clock
t D
t Q
t
7.2.2.2 SR Flipflop: An SR flip flop is an edge triggered SR latch. A pulse detector is connected to its enable input in order to detect rising or falling edges of the clock signal. The principle diagram is as follows.
S Q
Clock signal
Pulse detector
E /Q
R
Figure 7.5: Principle diagram of an SR flipflop.
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• Clock
Truth table: S X 0 0 1 1 R X 0 1 0 1 0 1 Invalid Q Latch Latch 1 0 /Q
Only when the clock signal is transitioning from low to high is the circuit responsive to the S and R inputs. For any other condition of the clock signal, the circuit will be latched.
Exercise 7.5: The following waveforms are applied at the inputs of an SR flipflop. Determine that of the output Q assuming that it is initially at low logic state.
Clock
t S
t R
t Q
t
7.2.2.3 The JK flipflop: The JK flip flop is a modified version of an SR flipflop with no invalid output state. When J = 1 and K = 1,and the clock input is pulsed, instead of an invalid state at the output, the circuit will toggle to a state opposite of that was previously available at its output: if the output was previously 1, it toggles to 0 and vice versa. The principle diagram of a JK flipflop is given as follows.
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K Pulse detector J
Figure 7.6: Principle diagram of a JK flipflop.
Q E
Clock
/Q
What used to be S and R inputs are now J and K inputs respectively. The previous two inputs AND gates have been replaced by three inputs AND gates. The third input of each gate receives feedback from Q and /Q outputs. • Clock
Truth table:
J X 0 0 1 1
K X 0 1 0 1
Q Latch Latch 0 1
/Q
1 0
Toggle
•
J Clock
Circuit diagram:
Q
J Clock Q
K Positive edge triggered JK flipflop
/Q
K Negative edge triggered JK flipflop
/Q
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Exercise 7.6: The following waveforms are applied at the inputs of a positive edge triggered JK flipflop. Determine that of the output Q assuming that it is initially at low logic state.
J
t K
t Clock
Q
t
t
The waveform of the output Q of the exercise 7.6 above can be given as follows:
J
t K
t Clock
Q
t
t
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Exercise 7.7: Let us consider the following digital system:
1
J
J
J
K
K
K
Clock
Q1
Q2
Q3
1. Draw the waveforms of the outputs Q1, Q2 and Q3. 2. Express the frequency f1, f2 and f3 of the waveforms of the outputs Q1, Q2 and Q3 respectively, in function of the frequency fc of the clock signal. 3. Using the principle of the circuit above, design a digital system capable of dividing the frequency of the clock signal by 32.
7.2.3 Asynchronous flipflop’s inputs: The normal data inputs to a flipflop (D, S and R or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and /Q) only in synchronism with the clock signal transitions. Asynchronous inputs are some types of extra inputs which can set or reset the flipflop regardless of the status of the clock signal. Typically, they are called PRESET and CLEAR.
PRE PRE PRE
J Clock K
J
Q
D Clock
J
Q
S Clock
J
Q
K
/Q
K
/Q
R
K
/Q
CLR
CLR
CLR
Figure 7.7: Asynchronous flipflop’s inputs.
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When the preset input is activated, the flipflop will be set (Q = 1, /Q = 0) regardless of the status of any of the synchronous inputs or the clock. When the clear input is activated, the flipflop will be reset (Q = 0, /Q = 1) regardless of the status of any of the synchronous inputs or the clock. If both preset and clear inputs are activated, we have an invalid state on the outputs where Q and /Q go to the same state. Preset and clear inputs find their use in the designing of counters (asynchronous and synchronous). Asynchronous inputs, just like synchronous inputs can be engineered to be active high or active low. If they are active low, there will be an inverting bubble at that input lead on the block symbol.
PRE PRE PRE
J Clock
Q
D Clock
Q
S Clock
Q
K
/Q
/Q
R
/Q
CLR
CLR
CLR
Figure 7.8: Asynchronous inputs active low.
7.2.4 Monostable and astable multivibrator: As we said above, a monostable multivibrator has only one stable state, the other state being momentary. An astable multivibrator has no stable state; it oscillates back and forth between two states. The integrated circuit NE555 is a multivibrator which cans both function as monostable and as astable.
7.2.4.1 IC NE555: The 555 integrated circuit is the most popular ship ever manufactured. Independently manufactured by more than 10 manufacturers, still in current production, and almost 40 years old, this little circuit has withstood the test of time. It has been used in many things from toys to spacecraft. The IC 555 integrates a flipflop circuit, and also operational amplifiers. The basic internal constitution of the IC 555 is given as follows.
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Figure 7.9: Internal diagram of the IC 555.
8
7
6
5
IC 555
1
2
3
4
Figure 7.10: External appearance of the IC 555.
7.2.4.2 IC 555 as monostable: A mechanical analogy of a monostable multivibrator would be a momentary contact push button switch which returns to its normal (stable) position when pressure is removed from its button actuator. In order to work as monostable multivibrator, the IC 555 should be connected as follows. The circuit is designed here using the electronic simulation software ISIS Professional edited by Labcenter. Values of component appearing on the diagram are just suggested.
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R3(1)
R1
8
U1
Q DC 3 7
330
R
10k 5
VCC
R3
4
R2
4k
CV
D1
LEDRED GND TH 6
2
TR
1
555
C2
3n3
C1
1000u
Figure 7.11: Simulation diagram for the IC 555 connected as monostable.
Probes 2 and 3 being respectively trigger and output, waveforms expected from them are as follows.
V2 1 0
t
V3 1 0
t
Tp
Anytime the circuit is triggered, that is by sending a brief low level logic signal at the lead number 2, the output 3 pass from its stable state which is low (0) to a
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momentary high logic level that delays for a duration Tp. The duration Tp depends on the values of R2 and C1and is given by the following formula.
TP = R2C1 ln 3 = 1.1R2C1
For our example the duration of the temporisation Tp will be calculated as follows: R2 = 4kΩ C1 = 1000 µF TP = 4000 × 1000 × 10 −6 × 1.1 = 4.4 So, the duration of the temporisation is 4.4 seconds.
7.2.4.3 IC 555 as astable: Astable multivibrator has no stable state and oscillates back and forth between an output of 0 and 1. In order to function as an astable, the IC 555 should be connected as follows:
R2(1)
R2
1k
8
U1
Q DC 3 7
R
VCC
4
R0
330
5
CV
R1
1k GND 6
2
TR
TH
D1
LEDRED
1
555
C2
3n3
C1
1000u
Figure 7.12: Simulation diagram for the IC 555 connected as an astable.
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Once the circuit is supplied by a 5 V DC source, the output begins to oscillate between 0 and 1 logic levels. The led goes on and off alternatively. The waveform expected from the output is given as follows:
V3 t1 t2
t
T
The period of the signal generated by the output is given as follows:
t1 = R1C1 ln 2
T = 0.693(R2 + 2 R1 )C1
T = t1 + t2 = (R2 + 2 R1 )C1 ln 2
t 2 = (R1 + R2 )C1 ln 2
For our example the duration of the period of the signal can therefore be calculated:
R1 = R2 = 1kΩ C1 = 1000 µF T = 0.693 × 3000 × 1000 × 10 − 6 = 2.079
So, the period of the signal generated by the output is 2.079 seconds.
7.3 Conclusion: This chapter has permitted us to study latches and flipflops which are elementary tools used in the designing of many sequential circuits. The notion of multivibrator has been introduced and discussed. The IC 555 has been presented and its functioning as monostable and stable multivibrator studied. The focus of the following chapter is the study of counters, which are of great importance in many digital circuits.
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REVIEW QUESTIONS
1. Define the following terms: Flipflop, sequential logic. 2. What is the difference between an RS flipflop and a JK flipflop? 3. Show with the aid of a diagram how a D flipflop can be obtained from RS and JK flipflops. 4. With the aid of a diagram, show how you would obtain RS and D flip flop from a clocked JK flipflop.
References: 16. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 17. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com , www.ibiblio.org/obp/electricCircuits. 18. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER EIGHT: SEQUENTIAL LOGIC PART B: COUNTERS
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Eight
COUNTERS
8.0 Specific objectives: At the end of this chapter, the student will be able to: Define asynchronous and synchronous counters; Design asynchronous and synchronous counters using flipflops; Know the use of counters in digital systems.
8.1 Introduction: A counter is an electronic device which is able to generate an orderly sequence of binary numbers. The addresses which command digital circuits as decoder, multiplexer, demultiplexer etc. are most of the time generated by counters. There two main basic types of counters: asynchronous counter and synchronous counter. Counters are designed using flipflops, usually JK flipflops. Asynchronous counters functions in such a way that the clock signal does not affect all the flipflops at the same instant; in fact, the clock signal triggers the first flipflop which in his turn trigger the second flipflop using its output signal. The second flipflop in his turn will trigger the third one, and so on, till the last flipflop. It is just like the triggering signal was being propagated from the first flipflop to the last. For this reason, asynchronous counters are also called propagation counters. The flipflops of a synchronous counter are all triggered by the same clock signal at the same instant. In fact, all the flipflops function in synchronism with the clock signal. The outputs of all the flipflops change their status at the same instant.
8.2 Asynchronous counters: Let us consider the following binary count sequence. The numbers are coded in four bits. Q0 is the LSB and Q3 is the MSB.
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Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
It can be noticed that each bit in this four bit sequence toggles when the bit before it (the bit having a lesser significance or place weight), toggles from 1 to 0. Small arrows are used to indicate those places in the above count sequence. So, to design an asynchronous counter which is able to generate the above sequence of numbers, we need to determine how to connect the clock inputs of each of the four JK flipflops ( each flipflop generating one bit) in such a way that each bit will toggle only when the bit just before it is transitioning from 1 to 0. The easier way of doing that is to use flipflops with negative edge triggering. The clock input of each flipflop will simply be connected to the non complemented output Q of the flipflop situated just before it (Flipflop having one lesser place weight). In this condition, each flipflop will toggle any time the output of the flipflop
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one place lesser weighted than it is transitioning from 1 to 0 (negative edge). Such a connection is done as shown in the following figure.
Vcc
J
Q
J
Q
J
Q
J
Q
K
K
K
K
Q0
Q1
Q2
Q3
Figure 8.1: Four bits asynchronous counter.
From the functioning of this asynchronous counter, the following waveforms can be generated.
Clock
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LSB
Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
Each of the signals generated by the outputs of the flipflops is used as the clock signal for the following flipflop. So, the falling edge of each signal causes the output of the following flipflop to toggle. It can also be clearly observed that those waveforms sketch the count sequence from 010 (0000) to 1510 (1111). When the maximum number of the sequence is reached, the counter is automatically reset (brought back to 0).
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8.3 Counter modulus: The modulus of a counter can be defined as the number of different states that it occupies within a count sequence. The four bits counter above has 16 different states (from 0000 to 1111), therefore its modulus is 16. In general, N being the number of flipflops used to design a counter, the modulus of the counter is given by the following formula: Modulus = 2N
Therefore, to add the modulus of a counter, we just need to add the number of counters used to design it. Exercise 8.1: Conceive an asynchronous counter modulus 8, modulus 32. 8.4 Counters having modulus < 2N: It is possible to conceive a counter which is such that its modulo is not a power of 2 as in the cases above. For this issue, asynchronous inputs presented in the previous chapter will be used. Let us realise an asynchronous counter modulo 5 ( the count sequence goes from 000 to 100). 22 = 4 < 5; 23 = 8 > 5. Therefore, we cannot use 2 flipflops to design the counter. The suitable number of flipflops is 3. The three flipflops should be connected in such a way that, the count sequence will end at 410 (100) instead of ending at 710 (111) as expected. It means that the counter should be obliged to reset when the binary number 101 (510) occurs. 1 Q2 0 Q1 1 Q0
To achieve this task, one method consists in gathering all the bits of the number which are in high logic state to the input of a NAND gate. The output of that NAND gate (which is low only when all its inputs are high) will be used to reset the counter when the number 101 occurs. The NAND gate is used in the case were the asynchronous inputs CLR of the flipflops function in low logic level. If they were
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functioning at high logic level, AND gate would have been used in such a way that, when all its inputs are high, it outputs a high logic level that reset the counter. The following figure shows how the connection can be done.
Q0 Vcc Q1 Q2
J
Q
J
Q
J
Q
K
K
CLR CLR
K
CLR
Clock
Z
Figure 8.2: Asynchronous counter modulo 5. From the functioning of the above asynchronous counter modulus 5, the following waveforms can be generated.
Clock
Q0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
Q1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
Q2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
Z
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The output Z of the NAND gate is connected to the CLR input of the three JK flipflops. When Z = 1, the counter is not affected. However, when Z = 0 (Q0 = 1 and Q2 = 1), the counter is reset. Therefore, a new count sequence can start. The count sequence is as follows: Q2 0 0 0 0 1 0 0 Q1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 0 1 The number 101 does not occur, for the counter is immediately reset after 1002.
Exercise 8.2: Conceive an asynchronous counter modulus 10, modulus 15, modulus 20.
8.5 Advantages and disadvantages of asynchronous counters: The main advantage of the synchronous counter is its simplicity as far as the conception is concern. However, this type of counter has a great problem: the ripple effect. This is the time delay due to the propagation of the signal throughout the flipflops which the counter is made up of. The ripple effect can cause error in computer circuits. To avoid the ripple effect, another type of counter has been designed: The synchronous counter.
8.6 Synchronous counter: A synchronous counter, in contrary to an asynchronous counter functions in such a way that all its flipflops toggle at the same instant, because they are triggered by the same clock signal.
8.6.1 Principle of an asynchronous counter: Let us consider again a four bit count sequence:
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Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
While examining this count sequence, it can be noticed that, for a bit belonging to a given rank to toggle (Q0, Q1, Q2, Q3), the bits of all the previous rank lesser weighted than it should be at high logic level. This property can be exploited to design a synchronous counter, as shown by the following diagram.
Vcc
Q2
J
Q1
J
Q0
J
K
K
K
Clock
Q2
Q1
Q0
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The flipflop Q0 toggles on every rising edge of the clock pulse. The flipflop Q1 toggles only when Q0 is high. The flipflop Q2 toggles only when Q0 and Q1 are high. We can also notice that all the flipflops are triggered by the same clock signal. Each of the higher order flipflops are made ready to toggle (both J and K inputs are high) if the Q input of all the previous flipflops are high. Otherwise, the J and K inputs for that flipflop will be both low, placing it into the latch mode where it will maintain its present output state. Since the first flipflop (LSB) needs to toggle at every clock pulse, its J and K inputs are connected to Vcc. The following equations can be deduced. J0 = K 0 = 1 J1 = K 1 = Q 0 J2 = K2 = Q0Q1 J3 = K3 = Q0Q1Q2 Generally… Jn =Kn = Q0Q1Q3…Qn1 Exercise 8.3: Design a synchronous counter modulo 8.
Remark 8.1: For the conception of synchronous counters having modulo < 2N, N being an integer, asynchronous inputs should be used in the same manner as they were used for asynchronous counters.
Exercise 8.4: Design a synchronous counter modulus 6.
8.6.2 Shift register A register can be defined as a set of flipflops connected together and intended to store a memory word. Each flipflop of the register store one bit. A shift register is a set of register connected together and intended to be used for the transfer of data. The transfer of data can be serial or parallel. In serial transfer, data are sent one bit after another over long distances. In parallel transfer, a whole memory word is transmitted at once, over a relatively short distance.
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Serial data transmission over a distance of meters to kilometres, uses shift registers to convert parallel data to serial form. Serial data transmission replaces many slow parallel wires with a single high speed transmission line. Basic shift registers are classified by structure according to the following types: • • • • • Serial in / Serial out; Parallel in / Serial out; Serial in / Parallel out; Parallel in / Parallel out; Ring counters.
a. Serial in/ serial out shift register: Data are sent in the register one bit after another and are sent out from it one bit after another. The following diagram illustrates this type of transfer.
Data in
D
Q0
D
Q1
D
Q2
Data out
Clock
Clock
Clock
Clock
Figure 8.3: Serial in / serial out shift register using D flipflops.
Once the pulse of the clock signal occurs, the bit available at the input of the first flipflop is shifted to that of the next flipflop. The same process is repeated till the last flipflop. JK flipflops can also be used to achieve the same task. The diagram is done as follows.
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Data in
J
Q0
J
Q1
J
Q2
Data out
Clock
Clock
Clock
K
/Q0
K
/Q1
K
/Q2
Clock
Figure 8.4: Serial in/ Serial out shift register using JK flipflops.
b. Ring counter: A ring counter is obtained when the output of a shift register is fed back to the input. One of the most known ring counter is the Johnson counter. The principle of the Johnson counter is presented by the following diagram.
D
Q0
D
Q1
J
Q2
Clock
Clock
Clock
Clock
Figure 8.5: Johnson counter.
During the functioning of the Johnson counter, a single bit is being transferred from one flipflop to another in a ring made up of the flipflops connected together. This functioning can be described using the following table ( it is assumed that initially Q0 = 1, Q1 = Q2 = Q3 = 0).
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Q0 1 0 0 0 1 0 0 0
Q1 0 1 0 0 0 1 0 0
Q2 0 0 1 0 0 0 1 0
Q3 0 0 0 1 0 0 0 1
Clock 1 2 3 4 5 6 7 8
The following waveforms can be deduced from the functioning of the Johnson counter.
1 Clock 2 3 4 5 6 7 8 9 10 11 12 13
Q0
Q1
Q2
Q3
8.7 Conclusion: The topic of this chapter was the counter, which is a direct application of the flipflops studied in the previous chapter. Asynchronous and synchronous counters have been studied. The notions of memory and data transmission have been introduced through the study of the shift register. The following chapter is focused on the study of storage devices and the presentation of the properties of integrated circuits.
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REVIEW QUESTIONS
1. Give the difference between a synchronous counter and an asynchronous counter. 2. Give the difference between serial transmission and parallel transmission of data. 3. Give two advantages of series transmission over parallel transmission. 4. Which type of transmission is used by the following: USB flash, LPT port? 5. Conceive a synchronous counter modulus 9. 6. Conceive an asynchronous modulus 10.
Problem 1: Study of a seven segments display. The circuit below is used to display the first 8 symbols of the digital system of numeration. The system is composed of: A modulo 8 JK flip flop asynchronous binary counter; A 3/7 (3 inputs and 7 outputs) decoder; A seven segments display used to display used to display the first 8 symbols as shown below.
01234567
a a b c d e f g
Q3 COUNTER Q2 Q1
f g
b
e d
c
3/7 Decoder
Display
a, b, c, d, e, f, g are the seven segments of the display. Q3, Q2 and Q1 are the outputs of the asynchronous counter (Q3 is the most significant bit while Q1 is the least significant bit). 1. Draw the truth table of the JK flip flop. 2. Draw the complete electric diagram of the asynchronous counter using the JK flip flops.
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3. Draw the truth table of the decoder following the model given below. Q3 0 0 Inputs Q2 0 0 Q1 0 1 a 1 b 1 c 1 Outputs d 1 Display e 1 f 1 g 0 0 1
4. Using the Karnaugh’s map, give the simplified logic expression of each output of the decoder. 5. Draw the logigram of the display 0 using NAND gates of two inputs, taking Q1, Q2 and Q3 as inputs variables.
Problem 2: Study of a JK flipflop According to the JK flipflop truth table established in the previous exercise, complete the following chronogram. Initially, Q = 0.
Clk
t J 1 0 K 1 0 Q t t
0
t
Problem 3: Counter The circuit of the following figure represents a counter. The flipflops are positive edge triggered.
D H
Q3
D H
Q2
D H
Q1
D H
Q0
/Q3 Clock
/Q2
/Q1
/Q0
Figure 1.
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1. Precise the nature of this counter (synchronous or asynchronous). 2. State the difference between series transfer and parallel transfer. 3. Draw the wave forms of Q3, Q2, Q1, Q0 knowing the initial state Q3 = 1, Q2 = Q1= Q0 = 0.
References: 19. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 20. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com , www.ibiblio.org/obp/electricCircuits. 21. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005. 22. Past questions of official examinations by the Cameroon General Certificate of Education board.
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Courses In Electrical Engineering
Volume II DIGITAL ELECTRONICS CHAPTER NINE: DIGITAL STORAGE
By JP. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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Chapter Nine
DIGITAL STORAGE
9.0 Specific objectives: At the end of this chapter, the student will be able to: Define the concept of memory know the structure of a digital storage device; Master the definition of various concepts related to the digital storage; Calculate the capacity of a memory; Know various technologies used for the manufacture of digital storage devices and the specific characteristics of those technologies; Know the functioning and the technologies of Read Only Memories; Know the principle and the functioning of Read/Write Memories; Give fields of application of digital storage devices.
9.1 Introduction: We are living nowadays in a civilisation that produces a lot of information which are intended to be stored: movies, pictures, data base concerning criminality, information to be used for meteorological previsions, programs controlling computers (operating systems), software in various domains of study etc…To be efficient and reliable, the storage of those in formations should be done using systems or tools which are resistant to corruption and are flexible. In fact, those systems should permit the storage of huge quantity of information over a long period of time without any losses or destruction. We should also be able to modify eventually the information stored. Traditional tools of storage like paper (information written in books) have shown their limits and have been replaced by new systems which are digital storage devices. Many technologies of digital storage exist, each having advantages and also disadvantages. The aim of this chapter is to make an overview of those technologies and to present applications of memory systems.
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9.2 General structure of digital storage systems: All the memories, no matter their types have the same general principle of functioning. They are surrounded by many lines having the following functions: 1. Select the address of de data within the memory; 2. Choose the type of operation which is to be achieved: read or write; 3. Lines intended to transfer the information to be written into the memory; 4. Lines intended to transfer information out of the memory… The figure below illustrates those functions using a 32 X 8 memory. That is a memory which is able to store 32 memory words of one byte each (1 byte = 8 bits). Given that there are 32 memory locations, 5 address lines are needed (32 = 25). The information is sent in using 8 lines, the same number of lines is used to send out data.
Data inputs
I1 A3 A2 A1
I2
I3 I3
I4
I5
I6
I7
I8
R/W Address inputs 32 X 8 Memory
Chip select
A0 O1 O2 O3 O4 O5 O6 O7 O8
Data outputs
Figure 9.1: General principle of a memory.
The R/W line permits to determine the type of operation to be done: either writing or reading. The chip select terminal permits to allow or to prevent the memory from functioning.
9.3 Terms and concepts related to digital storage: There are many concepts and specific terms which are used while dealing with digital storage world. These are some of those terms: Elementary memory or memory cell: This is an electrical circuit or a system which is able to store one bit of information. A flipflop is an elementary memory.
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Memory word: Group of bits which can be stored in one register of a memory. The length of a memory word in nowadays computers goes from 4 bits to 64 bits (eventually 128). But the most common length is 8 bits, which is a byte.
Capacity of a memory: It is the quantity of information that a memory device can store. The capacity of a memory is expressed in terms of bytes. It can also be expressed in terms of multiples of byte such as kilobyte (KB), megabyte (MB), gigabyte (GB) and even terabyte (TB). 1B = 8 bits; 1KB = 210 bytes = 1024 bytes; 1MB = 210 KB =220 bytes; 1GB = 210 MB = 230 bytes; 1TB = 210 GB = 240 bytes.
Exercise 9.1: The following information is written on a memory: 4MB X 8. Give the length of a memory word in that memory and determine its capacity in terms of bytes and in terms of bits. Solution: 1. The length of a memory word is 8 bits. 2. The capacity of the memory is calculated as follows: C = 4 X 220 X 8 B = 33 554 432 B = 268 435 456 bits.
Remark 9.1: Length of the memory word. The capacity of a memory is most of the time given using the following format: C = A X L, where L is the length of the memory word. For example, if we consider a memory on which it is written 4KB X 8, we can simply deduce that the length of the memory word 8 bits. Exercise 9.2: The following information is written on a digital storage device: 4GB X 4. a. Give the length of the memory word in that device; b. Determine the capacity of the memory in terms of bytes and also in terms of bits.
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Address: Number used to specify the location of a word in a memory. The address is normally a binary number but computer engineer use to convert them in hexadecimal or octal while working theoretically, in order to reduce the number of ciphers to handle ( binary number are expressed in a large number of cipher).
Reading operation: Operation during which a word located at a given address is found and transferred to another location.
Writing operation: Operation during which a new word is installed at a given address of a memory.
Volatile memory: It is a memory that saves the information that it contains only when supplied with electrical current. Once the supply is removed, all the information is lost.
Read only memory: Memory which is particularly designed for reading operation. There are however special ROM which can be written and also read.
Static memory: Semiconductor memory which saves data as long as they are supplied; data don’t need to be rewritten periodically.
Dynamic memory: Semiconductor memory for which data to be saved need to be rewritten periodically. The process of rewriting data periodically is called refreshment.
9.4 Technologies of semiconductor memories: As far as technology is concerned, semiconductor memories can be classified in two groups: Bipolar memories (memories containing bipolar transistors) and MOS memories (memories containing MOS transistors).The following chart gives an overview of various technologies of semiconductor memories.
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Semiconductor memories
Bipolar memories
MOS memories
TTL
STTL
ECL
PMOS
NMOS
CMOS
SOS
Figure 9.2: Semiconductor memory technologies.
Each type of semiconductor memory has its particular characteristics, however they can be compared using following criteria: • • • • • Density (scale of integration); Speed; Power consumption; Cost; Immunity to noise. Any type of semiconductor memory has advantages but also disadvantages, however it is generally known that bipolar memories are faster than MOS memories and that the performances of MOS memories are better than those of bipolar memories for all the other criteria specified above.
9.4.1 Technologies of bipolar memories: Bipolar memories use electronic components such as resistance, diodes, and bipolar transistor to form their memorisation circuit on integrated circuit chips. Because of the high complexity of those circuits, a great number of them cannot be integrated on a chip. That is why bipolar technology does not permit to obtain great capacity of memory.
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TTL and STTL technologies (TTL: Transistor Transistor Logic; STTL: Schottky TTL) are mostly used in the realisation of bipolar memories. TTL memories are characterised by: • • • • • • High speed; Capacity of medium size; High power consumption; High cost; Low noise immunity; Low integration density ( SSI, MSI) STTL memories have almost the same performances with TTL memories. The only difference is that STTL memories work faster than TTL memories. TTL memories are suitable for applications requiring high speed, medium size capacities and for which high power consumption is not a hindrance to the functioning. ECL memories (ECL: Emitted Coupled Logic) work faster than TTL and Schottky TTL memories; however their characteristics are poorer in all the other domains. ECL memories are therefore used essentially for applications which require very high speed without being disturbed by the poor performances in all the other domains.
9.4.2 Technologies of MOS memories: Memorisation circuits of MOS memories are realised using MOS transistors. Generally MOS technology memories have the following characteristics: • • • • • • Low speed; Low power consumption; High capacity; High immunity to noise; Low cost, High density of integration ( LSI, VLSI, ULSI) SOS technology (Silicium On Saphir) is an amelioration of CMOS technology having the best performances among all the MOS memories; however its cost is the highest.
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The following table summarises and compares the performances of semiconductor memories: Power Technology TTL/STTL ECL NMOS Speed Fast Very fast Medium
(near
Immunity Capacity Low Very low Very high to noise Low Very low High Cost High Very high Very low
consumption High Very high Low
to that
of TTL)
CMOS/SOS
Very low
Very low
High
Very high
Low
Remark 9.1: Scale of integration of ICs The scale of integration indicates the number of transistor integrated on one chip of IC. There are many scales of integration: • • • • • SSI: Small scale integration; MSI: Medium scale integration; LSI: Large scale integration; VLSI: Very large scale integration; ULSI: Ultra large scale integration.
9.5 Read only memories: These are memories in which data can only be read; in fact, once data are stored in the memory, they are saved permanently and are not supposed to be often modified. However, there are some types of read only memories in which data can be written and read several times. There are many types of read only memories, these are some of them: MROM: Read Only Memory programmable by Mask. Data are written during the process of fabrication of the memory using a mask, according to the specifications of the client (program given by the client). PROM: Programmable Read Only Memory. This type of memory is programmed by the user himself (not by the manufacturer as for the MROM). However, once a PROM is programmed, it can no more be modified. EPROM: Erasable Programmable Read Only Memory. This memory can be erased several times by the user and reprogrammed. The inconvenient of this type of
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memory is that not part but the entire program has to be cancelled anytime the used want to modify the program. EEPROM: Electrically Erasable PROM. This type of memory can be erased several times by the user. Its major advantage is that, it allows the programmer to modify the program without be obliged to cancel the entire program as it is the case for the EPROM.
9.6 Random Access Memory: Data can be written and read in random access memories as long as they are supply by an electrical voltage. There are two principal types of RAM: Static RAM and DRAM. A static RAM save data as long as it is supplied by an electrical voltage, without any need of rewrite the information periodically. SRAM should be periodically refreshed in order to save data stored within it.
9.7 Conclusion: The aim of this chapter was to make an overview of various technologies of digital storage devices. Concepts and notions related to digital storage have been presented and defined. Bipolar and MOS technologies of semiconductor memories have been presented with their various subcategories. Calculation of memory capacity has also been made.
REVIEW QUESTIONS
1. A semiconductor memory has the indication: 3MB X 8. a. How many words can be stored in this memory? b. What is the length of the word to be stored in this memory? c. How many bits can this memory contain?
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2. What are the advantages of MOS semiconductor memories over bipolar semiconductor memories? 3. Give the meaning of the following: a. TTL; b. CMOS; c. EEPROM; d. Capacity of a memory; e. Memory word; f. Register; g. SSI, MSI, LSI, VLSI.
4. What is the difference between a static RAM and a dynamic RAM? 5. What is the advantage of EEPROM memories over EPROM memories?
6. A memory has the following indication: ROM BIOS 10MB X 8 a. Give the signification of ROM BIOS and its role in a computer. b. Calculate the capacity of this memory in terms of bytes and in terms of bits.
References: 23. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, PrenticeHall inc., Englewood Cliffs, New Jersey , USA,1985. 24. Lessons In Electric Circuits Volume IV – Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com , www.ibiblio.org/obp/electricCircuits. 25. Cours de systèmes logiques, Notes de cours, Première année du génie électrique, ENSET de Douala, J.C Tsokezo, 20042005. 26. Past questions of official examinations by the Cameroon General Certificate of Education board.
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ABOUT THE AUTHOR
NGOUNE JeanPaul was born in ForekéDschang, Republic of Cameroon in 1984. He is a holder of a Master Degree in electrical engineering, obtained in 2010 in the Doctorate School of the University of Douala. He is also a holder of a DIPET II and a DIPET I respectively obtained in 2009 an 2007 in the Advance Teaching School for Technical Education (ENSET de Douala). He is currently a permanent teacher of Electrical Engineering at the Government Technical High School of Kumbo, NorthWest region, Cameroon. His domain of research concerns the improvement of energy
conversion techniques for an efficient generation of electrical energy from renewable sources (especially wind and solar energy, small and medium scale hydropower). The author is looking for a Ph.D program in his domain of research (he has not yet found it). Any suggestion for this issue will be warmly welcome.
NGOUNE JeanPaul, P.O. Box: 102 NSO, Kumbo, Cameroon. Phone: (+237) 7506 2458. Email : jngoune@yahoo.fr Web site : www.scribd.com/jngoune
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