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Experiment No.

03 Name of the Experiment: To construct a Set-Reset (S-R) and Clocked Set-Reset (Clocked S-R) Flip-Flop and verify their truth table. Set-Reset Flip-Flop: NOR Latch S-R Flip-Flop:

S 0 0 1 1

R 0 1 0 1

Qa No Change 0 1 Invalid

Qb No Change 1 0 Invalid

RESET SET

NAND Latch S-R Flip-Flop:

Clocked R-S Flip-Flop:

CLK 0 0 0 0 1 1 1 1 7402 7400

S 0 0 1 1 0 1 0 1

R 0 1 0 1 0 0 1 1

Q No Change No Change No Change No Change No Change 1 0 Invalid

7408

7411, 3 Input AND Gate

No. of Experiment: 04 Name of the Experiment: To construct a D Flip-Flop, J-K Flip-Flop and J-K Master Slave Flip-Flip and verify its operation. D Flip-Flop:

J-K Flip-Flop:

T-Flip-Flop:

J-K Master Slave Flip-Flop: