Verilog Interview Questions

How to model Transport and Inertial Delays in Verilog? Author : Rajesh Bawankule Following simple example can illustrate the concept. module delay(in,transport,inertial); input in; output transport; output inertial; reg wire transport; inertial;

// behaviour of delays always @(in) begin transport <= #10 in; end assign #10 inertial = in; endmodule // delay The timing Diagram for input and outputs _______ __ in _____| |_____||_______ _______ __ _________| |_____||_____ _______ _________| |____________



Non blocking assignment gives you transport delay. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified "transport" delay. In Continuous assign statement the latest event overrides the earlier event in the queue. I am attaching rudimentary testbench and its output. Hope this helps. module test; reg in; wire transport, inertial; // instantiate delay module delay my_delay(in,transport,inertial); // apply inputs initial begin in = 0;

#20 #20 #30 #5 #30 #30

in = 1; in = 0; in = 1; in = 0; in = 1; $finish;

end // monitor signals initial begin $monitor($time," in = %b transport = %b inertial = %b", in,transport, inertial); end endmodule // test log file Compiling source file "delay.v" Highest level modules: test 0 in = 0 transport = 10 in = 0 transport = 20 in = 1 transport = 30 in = 1 transport = 40 in = 0 transport = 50 in = 0 transport = 70 in = 1 transport = 75 in = 0 transport = 80 in = 0 transport = 85 in = 0 transport = 105 in = 1 transport = 115 in = 1 transport = L35 "delay.v": $finish at simulation time 81 simulation events x inertial 0 inertial 0 inertial 1 inertial 1 inertial 0 inertial 0 inertial 0 inertial 1 inertial 0 inertial 0 inertial 1 inertial 135 = = = = = = = = = = = = x 0 0 1 1 0 0 0 0 0 0 1

How to display the system date in $display or $write?
(Answers contributed by Swapnajit Mittra and Noman Hassan) Support of $system() task in Verilog-XL, NC-Verilog and VCS not only allows you to display the system date but also gives you the ability to call any command that you would normally type on the UNIX prompt (C executable, script, standard UNIX command etc.), and would make sense in executing from within Verilog source code. $system is not an IEEE Standard(1364-1995), but is supported by both XL and VCS. You could read back in the output of $system, by writing it to another file and reading it back in using $readmemh() as illustrated in following example. module top; reg [23:0] today [0:1];

initial begin $system("date +%m%d%y > date_file"); // output is 073199 for july 31st 1999 $readmemh("date_file", today); $display("Today is: %x", today[0]); end endmodule

How to display bold characters? Using following program bold characters can be displayed. Note that this program takes help of UNIX facilities. This may not work on PC based simulators. module bold; initial begin $display $display $display $display $display ("Normal Text"); ("\033[1mBold Text"); ("\033[mSwitch back to Normal Text....."); ("\033[7mInverse Text."); ("\033[mSwitch back to Normal Text.....");

$display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text \033[m"); end

endmodule Sample Verilog Questions asked in Interviews. Please contribute with your questions. If you are looking for answers please refer to website Site FAQ Differentiate between Inter assignment Delay and Inertial Delay. What are the different State machine Styles ? Which is better ? Explain disadvantages and advantages. What is the difference between the following lines of code ?
• •

reg1<= #10 reg2 ; reg3 = # 10 reg4 ; What is the value of Var1 after the following assignment ?

reg Var1; initial begin Var1<= "-"

end In the below code, Assume that this statement models a flop with async reset. In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?
1 2 3 4 5 6 7 8 9 10 11 12 module which_clock (x,y,q,d); input x,y,d; output q; reg q; always @ (posedge x or posedge y) if (x) q <= 1'b0; else q <= d; endmodule

What is the output of the two codes below ?
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 module quest_for_out(); integer i; reg clk; initial begin clk = 0; #4 $finish; end always #1 clk = ! clk;

always @ (posedge clk) begin : FOR_OUT for (i=0; i < 8; i = i + 1) begin if (i == 5) begin disable FOR_OUT; end $display ("Current i : ‰g",i); end end endmodule module quest_for_in(); integer i; reg clk; initial begin clk = 0; #4 $finish; end always #1 clk = ! clk;

event based and cycle based simulators ? What is code coverage and what are the different types of code coverage that one does ? How do I generate clock in Verilog ? . What is the difference between === and == ? What is defparam used for ? What is the difference between unary and logical operators ? What is the difference between tasks and functions ? What is the difference between transport and inertial delays ? What is the difference between casex and case statements ? What is the difference between $monitor and $display ? What is the difference between compiled. end end endmodule Why cannot initial statement be synthesizeable ? Consider a 2:1 mux. interpreted. what will the output F be if the Select (sel) is "X" ? What is the difference between blocking and nonblocking assignments ? What is the difference between wire and reg data type ? Write code for async reset D-Flip-Flop. Write code for a parallel encoder and a priority encoder. i < 8. Write code for 2:1 MUX using different coding methods. end $display ("Current i : ‰g". i = i + 1) begin : FOR_IN if (i == 5) begin disable FOR_IN.i).12 13 14 15 16 17 18 19 20 21 22 always @ (posedge clk) begin for (i=0.

5 end 6 end Method #3 1 2 3 4 5 6 7 8 initial begin clk = 0. Please refer to the Verilog tutorial section in "Art of Writing Test Bench" for more details. 3 forever begin 4 #5 clk = ~clk. writing test benches is as difficult as designing itself. end There are many ways to generate clocks: you may introduce jitter. change duty cycle. What is the difference between blocking and nonblocking assignment ? . end Method #2 1 initial begin 2 clk = 0. you could use one of the following methods: Method #1 1 2 3 4 5 6 7 8 initial begin clk = 0. end always begin #5 clk = 0.There are many ways to generate clock in Verilog. you need to have a test bench. end always begin #5 clk = ~clk. What is the difference between wire and reg ? Please refer to tidbits section for the difference between wire and reg. How do I test my design xyz ? To test or verify or validate any design. #5 clk = 1.

Please refer to tidbits section for difference between blocking and nonblocking statement. Bad Code 1 2 3 4 5 6 always @ (b or c) begin if (b) begin a = c. How do I avoid Latch in Verilog ? Latches are always bad (I don't like that statement). end end In the code above. end end . and it gets changed only when b is set to '1'. if (b) begin a = c. This results in a latch. value of a is retained. latches are caused when all the possible cases of assignment to variable are not covered. Well this rule applies to combinational blocks (blocks with edge sensitive lists are sequential blocks). a gets value of '0' first and if b is set to '1' and c is set to '1'. (Need to phrase it right) Good Code #1 1 2 3 4 5 6 7 always @ (b or c) begin a = 0. end end In the code above. end else begin a = 0. How do I write a state machine in Verilog ? Please refer to tidbits section for "writing FSM in Verilog". let's look at the following example. no matter what the value of b is. Good Code #2 1 2 3 4 5 6 7 8 always @ (b or c) begin if (b) begin a = c. This is the best way to avoid latches. only then a gets '1'.

For writing we use $writememh. Not all synthesis tools support this. we can have both blocking and nonblocking code in same always block. What is this `timescale compiler directive ? `timescale is used for specifying the reference time unit for the simulator. (Design compiler supports this). You could refer to the Verilog tutorial section for more details. where h stands for hex decimal. $fmonitor. How do I read and write from a file ? To Read from a file we use $readmemh. You can refer to Actel HDL coding Style. b = 1 and b = 0 case). More details can be found in the Verilog tutorial section "Modeling memories and FSM". One should not assign a variable in the same always block with both blocking and nonblocking assignments. Can we mix blocking and nonblocking in one always block ? Yes. How do I implement Memories in Verilog ? You can implement them by declaring 2-dimension arrays. How does this xyz code get synthesized ? Well it is a long story. inside level sensitive always blocks results in combo logic.In the above code. Syntax of the `timescale is as below: `timescale <reference_time_unit>/<time_precision> example : `timescale 10ns/1ns Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation. let me cover that in the synthesis part of Verilog tutorial.e. all the possible cases are covered (i. Some things that one should know to use this are: • • • Blocking assignments are treated as combinational logic. $fdisplay. . results in flip-flops and assign. One simple logic is: any code inside always blocks with edge sensitive sensitivity list.

when A and B are as in waveform? Tp is the gate delay of respective gate. What is the current through the resistor R1 (Ic) ? . Identify the circuit below.What is the output of AND gate in the circuit below. and its limitation.

. duty cycle. How do we solve this problem if the propagation delay in path B can not be reduced ? What is the function of a D flip-flop. briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A.Referring to the diagram below. whose inverted output is connected to its input ? Design a circuit to divide input frequency by 2. Design a divide-by-3 sequential circuit with 50&#37.

Design a divide-by-5 sequential circuit with 50&#37. What is the purpose of the buffer in the circuit below. Give the truth table for a Half Adder. duty cycle. is it necessary/redundant to have a buffer ? What is the output of the circuit below. What are the different types of adder implementations ? Draw a Transmission Gate-based D-Latch. assuming that value of 'X' is not known ? . Give a gate level implementation of it.

Design a circuit with minimum number of gates to detect the direction of rotation. Y and a blue shade painted on the disk for an angle of 45 degree. Design an OR gate from 2:1 MUX. Design an XOR gate from 2:1 MUX and a NOT gate .Consider a circular disk as shown in the figure below with two sensors mounted X.

What is the difference between a LATCH and a FLIP-FLOP ? • • • • Latch is a level sensitive device while flip-flop is an edge sensitive device. Design a D Flip-Flop from two latches. . Latch is sensitive to glitches on enable pin. Latches are faster than flip-flops. Latches take less gates (also less power) to implement than flip-flops. whereas flip-flop is immune to glitches.

Design a 2 bit counter using D Flip-Flop. . What are the two types of delays in any digital system ? Design a Transparent Latch using a 2:1 Mux. Design a 4:1 Mux using 2:1 Muxes and some combo logic.

Design a divide by two counter using D-Latch.What is metastable state ? How does it occur ? What is metastability ? Design a 3:8 decoder Design a FSM to detect sequence "101" in input sequence. . use of other components not allowed. Design a D and T flip flop using 2:1 mux. Convert NAND gate into Inverter. in two different ways. just the mux.

. Design a 16 byte Asynchronous FIFO. Design a Read on Reset System ? Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain. Positive Clock Skew. What is the difference between an EEPROM and a FLASH ? What is the difference between a NAND-based Flash and a NOR-based Flash ? You are given a 100 MHz clock. Asynchronous counter. duty cycle. Design a 33. Design 4-bit Synchronous counter.3 MHz clock with and without 50&#37. What is Race Condition ? Design a 4 bit Gray Counter. Negative Clock Skew.Design D Latch from SR flip-flop. Define Clock Skew .

Design a State machine for Traffic Control at a Four point Junction. a task can enable other tasks or functions. a task can contain time-controlling statements. What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ? How can you generate random sequences in digital circuits? Q: What is the difference between a Verilog task and a Verilog function? A:The following rules distinguish tasks from functions: A function shall execute in one simulation time unit. A function cannot enable a task. $display(a). a task shall not return a value. end A: This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time: . a <= 1. Verilog Answer 2 Q: Given the following Verilog code. A function shall have at least one input type argument and shall not have an output or inout type argument. A function shall return a single value. what value of "a" is displayed? always @(clk) begin a = 0. a task can have zero or more arguments of any type.

and then the display shows a = 0. Since the "a = 0" is an active event. The "a <= 1" is a non-blocking event. If we were to look at the value of a in the next sim cycle. so it's placed into the 3rd queue. #5 a = 1.1: 2: 3: 4: Active Events Inactive Events Non-Blocking Assign Updates Monitor Events (blocking statements) (#0 delays. Verilog Answer 3 Q: Given the following snipet of Verilog code. Only events in the active queue are completed this sim cycle. $monitor. and you'd get 10 30 50 70 90 110 130 ___ ___ ___ ___ ___ ___ ___ clk ___| |___| |___| |___| |___| |___| |___| |___ ___ a _______________________| |___________________| Verilog Answer 4 Q: What is the difference between the following two lines of Verilog code? #5 a = b. draw out the waveforms for clk and a always @(clk) begin a = 0. it would show 1. you could use "always @ (posedge clk)" instead. etc). so the "a = 0" happens. Finally. etc) (non-blocking statements) ($display. end A: 10 30 50 70 90 110 130 ___ ___ ___ ___ ___ ___ ___ clk ___| |___| |___| |___| |___| |___| |___| |___ a ___________________________________________________________ This obviously is not what we wanted. the display statement is placed into the 4th queue. so to get closer. it is scheduled into the 1st "queue". ___ |_______ .

(2) always @(clk) a = #10 clk. Wait five time units before doing the action for "a = b. i. a = 'b10. so for instance if foo = 1'bx. and if (foo) c = a. (5) assign #10 a = clk. A: The ? merges answers if the condition is "x". draw the waveforms for the following versions of a (each version is separate.a = #5 b. you'd get c = 'b1x. Verilog Answer 6 Q: What is the difference between: c = foo ? a : b. The value assigned to a will be the value of b 5 time units The value of b is calculated and stored in an internal temp After five time units.e. register. change a to wire. so you'd always get c = b. (6) assign #15 a = clk. if treats Xs or Zs as FALSE. . not in the same run): reg clk.". a = #5 b. hence. On the other hand. else c = b. (3) always @(clk) a = #15 clk. (1) always @(clk) a = #5 clk. A: #5 a = b. reg a. assign this stored value to a. and b = 'b11. always #10 clk = ~clk. Now. (Back) Verilog Answer 7 Q: Using the given. and draw for: (4) assign #5 a = clk.

#10. task_one().A: 10 30 50 70 90 110 130 ___ ___ ___ ___ ___ ___ ___ clk ___| |___| |___| |___| |___| |___| |___| |___ ___ (1)a ____| (2)a ______| |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |_ ___ (3)a __________________________________________________________ Since the #delay cancels future events when it activates... } task task_one() { . 10 30 50 70 90 110 130 ___ ___ ___ ___ ___ ___ ___ clk ___| |___| |___| |___| |___| |___| |___| |___ (4)a ____| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |_ ___ (5)a ______| |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ |___| ___ (6)a __________________________________________________________ Vera Answer 1 Q: What is the difference between a Vera task and a Verilog task? A: Vera Answer 2 Q: What is the difference between running the following snipet of code on Verilog vs Vera? fork { task_one(). With changing a to a wire and using assign. we just accomplish the same thing. any delay over the actual 1/2 period time of the clk flatlines...

j++) { . i < lim. } } A: (Back) Programming Answer 1 Q: Given $a = "5. for (i = 0. i < 50. (@temp) = split (/. $lowest = $temp[0]. A: /* BEGIN C SNIPET */ void bubblesort (int x[]. i++) { cnt++.-3. } } Programming Answer 2 Q: Write the code to sort an array of integers. for (i = 0./.-1. $i++) { if ($temp[$i] < $lowest) { $lowest = $temp[$i]. j.-5.cnt = 0. int lim) { int i. for ($i=0. A: // BEGIN PERL SNIPET $a = "5.12.0. $i<6. temp. // END PERL SNIPET NOTE: You could also replace the for loop with this: foreach $value (@temp) { if ($value < $lowest) { $lowest = $value. j < lim-1-i. } } print "Lowest value found was: $lowest\n". $a).12". i++) { for (j = 0.-3".7.-5. Write a program to find the lowest number in the string.0.

x[j] = x[j+1]. the "for i" loop only needs to go from 0 to lim-1. * is the indirection operator. and it creates pointer values. the complete array has been sorted. therefore.1 ). if ( $y > 1 ) { return $y * &factorial( $y . A: & is the address operator. Example: . Next. and we do not need to continue. we go through the entire array WITHOUT performing a swap. Use a recursive subroutine. } } // END PERL SNIPET Programming Answer 4 Q: In C. We can watch for this by adding a variable to keep track of whether we have performed a swap on this iteration. explain the difference between the & operator and the * operator. Programming Answer 3 Q: Write the code for finding the factorial of a passed integer. x[j+1] = temp. } } /* /* /* /* end end end end if for j for i bubblesort */ */ */ */ } } /* END C SNIPET */ Some optimizations that can be made are that a single-element array does not need to be sorted. and it dereferences pointers to access the object pointed to.if (x[j] > x[j+1]) { temp = x[j]. } else { return 1. A: // BEGIN PERL SNIPET sub factorial { my $y = shift. if at some point during the iterations.

i++ ) { *tmp_str[length-i-1] = *in_str[i]. int i. A: /* BEGIN C SNIPET */ #include <string. j = *ip. /* j now has the value 22 */ *ip = 17.h> void is_palindrome ( char *in_str ) { char *tmp_str. ip = &i. *ip. } /* END C SNIPET */ Programming Answer 6 Q: Write a function to output a diamond shape according to the given (odd) input. Examples: Input is 5 * *** ***** *** * Input is 7 * *** ***** ******* ***** . j. i < length. length.In the following example. for ( i = 0. } if ( 0 == strcmp ( *tmp_str. After that assignment. else printf ("String is not a palindrome"). length = strlen ( *in_str ). the pointer ip is assigned the address of variable i (&i). i = 22. /* i now has the value 17 */ Programming Answer 5 Q: Write a function to determine whether a string is a palindrome (same forward as reverse. such as "radar" or "mom"). the expression *ip refers to the same object denoted by i: int i. *in_str ) ) printf ("String is a palindrome").

} while ($stars--) { print "*". } ### END PERL SNIPET ### General Answer 1 Q: Given the following FIFO and rules. $i <= (($input * 2) . } } else { $spaces = ($i . $spaces = ($input . while ($spaces--) { print " ". $stars = $input . how deep does the FIFO need to be to prevent underflowing or overflowing? RULES: 1) frequency(clk_A) = frequency(clk_B) / 4 2) period(en_B) = period(clk_A) * 100 3) duty_cycle(en_B) = 25% A: Assume clk_B = 100MHz (10ns) .1). $i += 2) { if ($i <= $input) { $stars = $i.($spaces * 2). } while ($stars--) { print "*".$input) / 2.$stars) / 2. } } print "\n". while ($spaces--) { print " ".*** * A: ### BEGIN PERL SNIPET ### for ($i = 1.

clk_A = 25MHz (40ns) From (2). period(en_B) = 40ns * 100 = 4000ns. so 3000ns of the enable we are doing no output work.From (1). FIFO size = 3000ns/40ns = 75 entries. due to (3). General Answer 2 Q: Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up (the leading 0s cannot be used in more than one sequence). Therefore. A: . but we only output for 1000ns.

and "Set Associative" caches. "Fully Associative".General Answer 3 Q: Explain the differences between "Direct Mapped". A: .

A block is first mapped onto a set. the cache is said to be fully associative. we For instance... If we then get a "0". the cache is said to be set associative. so we output another "1" (and so on). The mapping is usually (block-frame address) modulo (number of blocks in cache). the cache is said to be direct mapped.If each block has only one place it can appear in the cache. and then the block can be placed anywhere within the set. The set is usually chosen by bit selection. if the input stream output a "1" (since 101 is 5). the cache placement is called n-way set associative. is 1. A: We don't need to keep track of the entire string of numbers . If a block can be placed in a restricted set of places in the cache. General Answer 4 Q: Design a four-input NAND gate using only two-input NAND gates.if something . A: Basically. 1. (block-frame address) modulo (number of sets in cache). that is. If a block can be placed anywhere in the cache. If there are n blocks in a set. A set is a group of two or more blocks in the cache. so. the aggregate total is 10. 0. you can tie the inputs of a NAND gate together to get an inverter. (Back) General Answer 5 Q: Draw the state diagram for a circuit that outputs a "1" if the aggregate serial binary input is divisible by 5.

in 1) Write a verilog code to swap contents of two registers with and without a temporary register? With temp reg . so we can just reset to 0. always @ (posedge clock) begin a <= b. always @ (posedge clock) begin temp=b. b=a. b <= a. end 2) Difference between blocking and non-blocking?(Verilog interview questions that is most commonly asked) The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. From ASIC. it doesn't matter if it's 250 or 0. The blocking assignment statement (= operator) acts much like in traditional programming . So we really only need to keep track of "0" through "4". end Without temp divisible by 5. The two are distinguished by the = and <= assignment operators.

languages. The whole statement is done before control passes on to the next statement. the following Verilog program // testing blocking and non-blocking assignment module blocking. delay or timing control statements are permitted In the invocation of a function their must be at least one argument to be passed. ( The program time will not be incremented during the function routine) Within a function. B ). A. B. no event. Functions will only return a single value and can not use either output or inout . // blocking procedural assignment B = A + 1. A. For example. #1 A <= A + 1. A function will carry out its required duty in zero simulation time. B ). // non-blocking procedural assignment B <= A + 1. #1 $display("Non-blocking: A= %b B= %b". This reflects how register transfers occur in some hardware systems. blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential Click to view more 3) Difference between task and function? Function: A function is unable to enable a task however functions can enable other functions. #1 A = A + 1. reg [0:7] A. initial begin: init1 A = 3. end endmodule produces the following output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100 The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. $display("Blocking: A= %b B= %b". The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. A = 3.

end 5) What is delta simulation time? 6) Difference between $monitor. They are much less convenient than waveform display tools like cwaves?. #5 b = temp_ac. b. A task is allowed to use zero or more arguments which are of type output.statements. c = 0. evaluate //a + c and then wait 5 time units to assign value //to b. 4) Difference between inter statement and intra statement delay? //define register variables reg a. Tasks are allowed to contain any of these statements. temp_ac = a + c. input or inout. c = 0.$display & $strobe? These commands have the same syntax. Even though a and c //might change between 0 and 5. //the value assigned to b at time 5 is unaffected. //Take value of a and c at the time=0. A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements . c. and display text on the screen during simulation. //intra assignment delays initial begin a = 0. $display and $strobe display once every time they are executed. end //Equivalent method with temporary variables and regular delay control initial begin a = 0. b = #5 a + c. whereas $monitor displays every time one of its parameters changes. Tasks: Tasks are capable of enabling a function as well as enabling other versions of a Task Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time. //Take value of a + c at the current time and //store it in a temporary variable. .

Format characters include %d (decimal).. %s (string) and %t (time). %b (binary). . h.. %5d.The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than exactly where it is executed. 2'd1 : out = i1.a latch is inferred because to reproduce the previous value when unknown branch is specified. The format string is like that in C/C++. par_1. o to the task name to change default format to binary. par_1. endcase in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred .. The same may be observed in IF statement in case an ELSE IF is not specified." A "parallel" case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If a case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items. %m (hierarchy level).. and may contain format characters. To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided. par_2. would give exactly 5 spaces for the number instead of the space needed. the previous stored value is reproduced for this storing a latch is inferred.s0}=3 . the matching case items are called "overlapping" case items and the case statement is not "parallel. Append b. $monitor (“format_string”. . the case statement is not "full. par_1. For example in above case if {s1." 8) What is meant by inferring to avoid it? Consider the following : always @(s1 or s0 or i0 or i1 or i2 or i3) case ({s1. 7) What is difference between Verilog full case and parallel case? A "full" case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If it is possible to find a case expression that would match more than one case item. octal or hexadecimal. s0}) 2'd0 : out = i0. ). Syntax: $display (“format_string”. 2'd2 : out = i2. $strobe (“format_string”... %h (hexadecimal). . ). ). %5b etc. par_2. par_2. 9) Tell me how blocking and non blocking statements get executed? Execution of blocking assignments can be viewed as a one-step process: . %c (character).

// internal signal. why? Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch. // single bit inputs output [msb:lsb] out.(only assigned outside always statements) wire net variable 1. // Input output declarations input in1.1.pin2 (net2).register types (only assigned within always statements). // a bus output // internal signal register type declaration . net type declaration . // parameter declarations parameter parameter_name = parameter value. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement.pin1 (net1). 13) Tell me structure of Verilog code you follow? A good template for your Verilog file is shown below. A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed Execution of nonblocking assignments can be viewed as a two-step process: 1. // timescale directive tells the simulator the base units and precision of the simulation `timescale 1 ns / 10 ps module name (input and outputs). reg register variable 1. 12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes.instantiating another module reference name instance name ( . 10) Variable and signal which will be Updated first? Signals 11) What is sensitivity list? The sensitivity list indicates that when a change occurs to any one of elements in the list change. begin…end statement inside that always block will get executed. // hierarchy . Evaluate the RHS of nonblocking statements at the beginning of the time step. reg [msb:lsb] register variable 2. Update the LHS of nonblocking statements at the end of the time step. . input in2. 2. .

The choice of which data types to use should be considered wisely. VHDL may be preferred because it allows a multitude of language or user defined data types to be used. but has not changed the original nature of the language. clearer to read and avoid unnecessary conversion functions that can clutter the code. However. especially enumerated (abstract) data types. all data types used in a Verilog model are defined by the Verilog language and not by the user. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. There are net data types. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files.pinn (netn) ). that is signals. for example wire. Verilog. endmodule 14) Difference between Verilog and vhdl? Compilation VHDL. Verilog data types a re very simple. . Unlike VHDL. Objects. easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Multiple design-units (entity/architecture pairs). that reside in the same system file. Verilog. // synchronous procedures always @ (posedge clock) begin . This will make models easier to write.. Compared to VHDL. Data types VHDL. . may be separately compiled if so desired. end assign net variable = combinational logic. and a register data type called reg. it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue. Simulation results can change by simply changing the order of compilation. The Verilog language is still rooted in it's native interpretative mode. A multitude of language or user defined data types can be used. end // combinatinal procedures always @ (signal1 or signal2 or signal3) begin . This may mean dedicated conversion functions are needed to convert objects from one type to another. Compilation is a means of speeding up simulation.

Verilog may be preferred because of it's simplicity. This removes typo mistakes and thus avoids simulation and synthesis mismatches. $displayh. --. $finish exits the simulator back to the operating system 17) Can you list out some of enhancements in Verilog 2001? In earlier version of Verilog . Functions and procedures used within a model must be defined in the module.This can be used for displaying strings. $display(" The count is %b". // Verilog 2k example for usage of comma always @ (i1.i3. Here are some examples of usage. $write. Verilog. $writeh.output: 460 counter = 4'b10. --. expression or values of variables. The most useful of these is $display. --. $displayb. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.i2. $writeo.of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. $display("Hello oni"). 15) What are different styles of Verilog coding I mean gate-level. Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below module memory ( .output: The count is 0010 $reset resets the simulation back to time 0.output: Hello oni $display($time) // current simulation time.i4) Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . In Verilog 2001. There is no concept of packages in Verilog. $writeb. Design reusability VHDL. $stop halts the simulator and puts it in interactive mode where the user can enter commands. counter). $displayo.we use 'or' to specify more than one element in sensitivity list .continuous level and others explain in detail? 16) Can you tell me some of system tasks and their purpose? $display. we can use comma as shown in the example below. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

synchronous means clock dependent so reset must not be present in sensitivity disk eg: always @ (posedge clk ) begin if (reset) . . end Asynchronous means clock independent so reset must be present in sensitivity list. value).using PLI. It also provides mechanism to access internal databases of the simulator from the C program.input r. 18)Write a Verilog code for synchronous and asynchronous reset? Synchronous reset. you can take advantage of both the paradigms . . output [7:0] data_out ). PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. let’s say one is represented by 1 and another by 0. . input [3:0] addr. 20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide? Ants can move only along edges of triangle in either of direction. when all ants are going in same direction they won’t collide that is 111 or 000 so probability of collision is 2/8=1/4 21) Tell me about file I/O? 21)What is difference between freeze deposit and force? $deposit(variable. . since there are 3 sides eight combinations are possible. Or. in other words.parallel and hardware related features of Verilog and sequential flow of C . input [7:0] data_in. Eg Always @(posedge clock or posedge reset) begin if (reset) . . end 19) What is pli?why is it used? Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. input wr.

// Priority encoded mux. what value of "a" is displayed? . Therefore casex or casez are required. The value remains until there is a subsequent driver transaction or another $deposit task for the same register or net. then -freeze is assumed for unresolved signals and -drive is assumed for resolved signals. Verilog interview Questions 24)Given the following Verilog code. But if you prefer -freeze as the default for both resolved and unresolved signals. When none of these is specified. This is designed to provide compatibility with force files.which is preferable. CASEX should never be used.This system task sets a Verilog register or net to the specified value. 2'b01: r = b. This is because: Don’t cares are not allowed in the "case" statement. variable is the register or net to be changed. Verilog interview Questions 22)Will case infer priority register if yes how give an example? yes case can infer priority register depending on coding style reg r. Casex will automatically match any x or z with anything in the case statement. The force command has -freeze.x’s require an absolute match. endcase end Verilog interview Questions 23)Casex. value is the new value for the register or net. case (select2) 2'b00: r = a. Casez will only match z’s -. and -deposit options. otherwise use of CASE is required.why? CASEZ : Special version of the case statement which uses a Z logic value to represent don't-care bits. always @ (a or b or c or select2) begin r = c.z difference. -drive. CASEX : Special version of the case statement which uses Z or X logic values to represent don'tcare bits. This system task operates identically to the ModelSim force -deposit command. CASEZ should be used for case statements with wildcard don’t cares.

and then the display shows a = 0. . it would show 1. so for instance if foo = 1'bx. etc). a = #5 b.always @(clk) begin a = 0. and b = 'b11. Wait five time units before doing the action for "a = b. a <= 1. 25) What is the difference between the following two lines of Verilog code? #5 a = b. $display(a). Finally. so it's placed into the 3rd queue. the display statement is placed into the 4th queue.After five time units. a = 'b10. you'd get c = 'b1x. If we were to look at the value of a in the next sim cycle. if treats Xs or Zs as FALSE. else c = b. assign this stored value to a. a = #5 b. #5 a = b. and if (foo) c = a. so the "a = 0" happens. so you'd always get c = b. end This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time: 1: Active Events (blocking statements) 2: Inactive Events (#0 delays. 27)What are Intertial and Transport Delays ?? 28)What does `timescale 1 ns/ 1 ps signify in a verilog code? 'timescale directive is a compiler directive.". The value of b is calculated and stored in an internal temp register. Usage : `timescale / reference_time_unit : Specifies the unit of measurement for times and delays. The "a <= 1" is a non-blocking event. $monitor. etc) 3: Non-Blocking Assign Updates (non-blocking statements) 4: Monitor Events ($display. Only events in the active queue are completed this sim cycle.It is used to measure simulation time or delay time. time_precision: specifies the precision to which the delays are rounded off. Since the "a = 0" is an active event. The ? merges answers if the condition is "x". it is scheduled into the 1st "queue". 26)What is the difference between: c = foo ? a : b. On the other hand.

inout [7:0] bidir. bidir). reg [7:0] b. But reg can hold the value even if there in no connection.reg is x.It can't compare Xs.29) What is the difference between === and == ? output of "==" can be 1. if there is no connection in a and b. When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x" then the output would be "X" . output [7:0] outp. input clk. reg [7:0] a. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b. A === B will give 0 as output. // Port Declaration input oe. real time) represents abstract data storage element. real. assign outp = b. outp. "==" is used for comparison of only 1's and 0's .g A = 3'b1x0 B = 3'b10x A == B will give X as output. input [7:0] inp. Register type: (reg. If any bit of the input is X output will be X "===" is used for comparison of X also. Default values:wire is Z. wire loose value. But if use "===" outpout would be 0 or 1. // Always Construct always @ (posedge clk) begin . time. integer. assign bidir = oe ? a : 8'bZ . 0 or X. inp. Assigned values only within an always statement or an initial statement. 31) What is the difference between wire and reg? Net types: (wire.tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. output of "===" can only be 0 or 1. e. 30)How to generate sine wav using verilog coding style? A: The easiest and efficient way to generate sine wave is using CORDIC Algorithm. clk. 32 )How do you implement the bi-directional ports in Verilog HDL? module bidirec (oe.

end endmodule 33)How to write FSM is verilog? there r mainly 4 ways 2 write fsm code 1) using 1 process where all input decoder. So here. x[3]: SOMETHING4. a <= inp. always @(. 2) using 2 process where all comb ckt and sequential ckt separated in different process 3) using 2 process where input decoder and persent state r combine and output decoder seperated in other process 4) using 3 process where all three." doesn't run the true case? This is a popular coding error.b <= bidir. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&)..) begin case (1'b1) x[0]: SOMETHING1. Event Driven Cycle Based . x[1]: SOMETHING2. if the lowest 1-bit of x is bit 2. 36)What are Different types of Verilog Simulators ? There are mainly two types of simulators available. input decoder. present state.. x[2]: SOMETHING3. and output decoder r combine in one process... then something3 is the statement that will get executed (or selected by the logic). endcase end The case statement walks down the list of cases and executes the first one that matches. present state and output decoder r separated in 3 process. Click to view more 34)what is verilog case (1) ? wire [3:0] x. 35) Why is it that "if (2'b01 & 2'b10).

By limiting the calculations.) The digital logic is the only part of the design simulated (no timing calculations). This can lead to costly re-spins or. missed market windows. they do a poor job of covering corner cases. Traditionally verification IP works in a directed-test environment by acting on specific testbench commands such as read. more complex bus standards to handle the massive volume of data traffic there has also been a renewed significance for verification IP to speed the time taken to develop advanced testbench environments that include randomization of bus traffic. This has created a trend in RTL verification techniques to employ constrained-random verification. which shifts the emphasis from hand-authored tests to utilization of compute resources. full timing calculations for all devices. gate.) Results are only examined at the end of every clock cycle. there is an equal or greater increase in the size of the verification effort required to achieve functional coverage goals.Event-based Simulator: This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagates through during a clock cycle. RTL HDL. and transistor representations. With the corresponding emergence of faster. Event-based simulators are like a Swiss Army knife with many different features but none are particularly fast. simulation of Behavioral HDL. Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the lost timing information coverage. Since directed tests only cover conditions that have been anticipated by the verification team. write or burst to generate transactions for whichever . Directed-Test Methodology Building a directed verification environment with a comprehensive set of directed tests is extremely time-consuming and difficult. worse still. and the full HDL standard. Cycle based Simulators can provide huge increases in performance over conventional Event-based simulators. Cycle based simulators are more like a high speed electric carving knife in comparison because they focus on a subset of the biggest problem: logic verification. and 2. 37)What is Constrained-Random Verification ? Introduction As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity. Full Event-based simulators support 4-28 states. Cycle Based Simulator: This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge performance gains in verifying Boolean logic: 1.

However. leading to poorly tested interfaces. in this directed methodology. Constrained-Random Verification Methodology The advent of constrained-random verification gives verification engineers an effective method to achieve coverage goals faster and also help find corner-case problems. while monitors snoop the interfaces to provide coverage information. New or revised constraints focus verification on the uncovered parts of the design under test. It shifts the emphasis from writing an enormous number of directed tests to writing a smaller set of constrained-random scenarios that let the compute resources do the work. As verification progresses. .protocol is being tested. which are then retained as regression tests to create a set of scenarios. the bigger issue is that directed tests only test for predicted behavior and it is typically the unforeseen that trips up design teams and leads to extremely costly bugs found in silicon. and seeds that provide high coverage of the design. the simulation tool identifies the best seeds. Scoreboards are used to verify that data has successfully reached its destination. Coverage goals are achieved not by the sheer weight of manual labor required to hand-write directed tests but by the number of processors that can be utilized to run random seeds. The drawback is that. The verification team frequently runs out of time before a mandated tape-out date. This directed traffic is used to verify that an interface behaves as expected in response to valid transactions and error conditions. the task of writing the command code and checking the responses across the full breadth of a protocol is an overwhelming task. constraints. This significantly reduces the time required to achieve the coverage goals.

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