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Introduction to SDH

Introduction to SDH

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Introduction to the Synchronous Digital Hierarchy (SDH

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The History of Digital Transmission

’70s - introduction of PCM into Telecom networks 32 PCM streams are Synchronously Multiplexed to 2.048 Mbit/s (E1) Multiplexing to higher rates via PDH 1985 Bellcore proposes SONET 1988 SDH standard introduced.

PDH: Plesiochronous Digital Hierarchy

Multiplex levels:
2.048 Mbit/s 8.448 Mbit/s 34.368 Mbit/s 139.264 Mbit/s

Uses Positive justification to adapt frequency differences Overheads: CRC Defects: LOS, LOF, AIS

Plesiochronous Multiplexing

Before SDH transmission networks were based on the PDH hierarchy. Plesiochronous means nearly synchronous. 2 Mbit/s service signals are multiplexed to 140 Mbit/s for transmission over optical fiber or radio. Multiplexing of 2 Mbit/s to 140 Mbit/s requires two intermediate multiplexing stages of 8 Mbit/s and 34 Mbit/s. Multiplexing of 2 Mbit/s to 140 Mbit/s requires multiplex equipment known as 2, 3 and 4 DME. Alarm and performance management requires separate equipment in PDH.

312 Mbit/s x4 x 4 1.264Mbit/s x 4 34.544 M bit/s 2.312 M bit/s x4 274.728 M bit/s x3 32. SDH Hierarchy PDH transmission rates: SDH is designed to unify all transmission rates into a single Mapping hierarchy Japan North America Europe 397.738 M bit/s x7 6.176 M bit/s x6 44.2 M bit/s x4 97.084 M bit/s x5 6.448 M bit/s .048 M bit/s 139.PDH vs.368 Mbit/s x 4 8.

PDH Multiplexing PDH Multiplexing of 2 Mbit/s to 140 Mbit/s requires 22 PDH multiplexers: 16 x 2DME 4 x 3DME 1 x 4DME Also a total of 106 cables required. 2 Mb it/s 8 Mbi t/s 3 4 Mb it/s 140 Mbi t/s 1 2 D M E 3 D M E 4 D M E 3 D M E 64 2 D M E .

PDH Add/Drop If a small number of 2 Mbit/s streams passing through a site need to be dropped then in PDH this requires large amount of equipment to multiplex down to 2Mbit/s. .

In SDH the multiplexed channels are in fixed locations relative to the framing byte.What is SDH? The basis of Synchronous Digital Hierarchy (SDH) is synchronous multiplexing . Demultiplexing is achieved by gating out the required bytes from the digital stream. . This allows a single channel to be ‘dropped’ from the data stream without demultiplexing intermediate rates as is required in PDH.data from multiple tributary sources is byte interleaved.

32 Mbit/s 9953.SDH Rates SDH is a transport hierarchy based on multiples of 155.28 Mbit/s Each rate is an exact multiple of the lower rate therefore the hierarchy is synchronous.52 Mbit/s 622. .52 Mbit/s The basic unit of SDH is STM-1: STM-1 STM-4 STM-16 STM-64 = = = = 155.08 Mbit/s 2588.

SDH Hierarchy SDH defines a multiplexing hierarchy that allows all existing PDH rates to be transported synchronously. The following diagram shows these multiplexing paths: x1 STM-N xN x3 AUG AU-4 VC-4 x3 x1 TUG-3 TU-3 VC-3 44736 kb/s (DS3) 34368 kb/s HOP 139264 kb/s C-4 AU-3 VC-3 x7 x7 TUG-2 x3 TU-12 C-3 x1 TU-2 VC-2 C-2 6312 kb /s (DS2) LOP 204 8 kb/s TU-11 VC-12 C12 x4 VC-11 C-11 154 4 kb/s (DS1) .

Example: Multiplex path for the E1 xN STM-N AUG AU-4 VC-4 x3 TUG-3 x7 TUG-2 x3 TU-12 VC-12 C-12 Section overhead Pointer processor HO path overhead Pointer processor LO path overhead .

. A mechanism is required to map PDH rates into the STM frame. The synchroniser adapts the rate of an incoming PDH signal to SDH rate. A PDH channel must be synchronised before it can be mapped into a container. This function is performed by the container (C).Transport of PDH payloads SDH is essentially a transport mechanism for carrying a large number of PDH payloads.

Bit stuffing PDH SDH .SDH and non-synchronous signals At the PDH/SDH boundary Bit stuffing is performed when the PDH signal is mapped into its container.

path overhead byte are added to create a virtual container.SDH virtual Containers Once a container has been created. Path overheads contain alarm. . A path through an SDH network exists from the point where a PDH signal is put into a container to where the signal is recovered from the container. performance and other management information. The path overheads travel with the container over the path.

Phase alignment between the unshaded and shaded areas is defined by the pointer (PTR) and is indicated by the arrow.Mapping Virtual Containers C-4 container being mapped into an STM frame via a VC-4 virtual container Container-4 VC-4 POH Container-4 VC-4 AU-4 PTR VC-4 AU-4 AU-4 PTR VC-4 AUG SOH Logical association Physical association AUG AUG STM-N T1517990-95 NOTE – Unshaded areas are phase aligned. .

As with PCM. the SDH frame rate in 125 us per frame. the SDH has 8 bits per time slot. As with PCM.2 Mbit/s PCM30 frame structure The SDH frame rate is inherited from PCM. The following diagram shows the PCM30 frame: 125 us TS0 TS1 TS15 TS16 TS17 TS30 TS31 TS0 .

The three main areas of the STM-N frame are indicated: SOH. Administrative Unit pointer(s). 270 × N columns (bytes) 9×N 261 × N 1 Section overhead SOH Administrative unit pointer(s) STM-N payload Section overhead SOH 9 rows 3 4 5 9 T15180 00-9 5 . Information payload.Basic SDH frame structure STM-N frame structure is shown in the Figure below.

Pointer processing ocurrs here STM -N NE #1 S TM -N N E #2 STM -N f f +δf .Different clock rates in SDH SDH will still work if there are two different clocks in the network and the network becomes asynchronous. Pointers are used adjust for the new frequency.

1 F ix e d st u f f C .4 -X c X × 260 X × 2 6 1 b y te s T 1 5 18 2 3 0 . The VC-4 associated with each AU-4 does not have a fixed phase with respect to the STM-N frame.Administrative Units in the STM-N The VC-4 is mapped into an STM frame via the administrative group (AU). The location of the first byte of the VC-n is indicated by the AU-n pointer. N × 2 7 0 b yt e s N × 9 N × 2 6 1 b yt e s S T M -N 3 RS OH 1 A U -n P T R s J1 B3 V C -4 -X c 5 M SO H C2 G 1 F2 H4 F3 K3 N1 1 X.95 P TR P o in t e r .

Tributary Units in a VC-4 The VC-4 can carry a container -4 (C-4). The VC-n associated with each TU-n does not have a fixed phase relationship with respect to the start of the VC4. The TUs are then multiplexed into a VC-4. The VC-4 forms what is known as an high order path. The TU-n pointer is in a fixed location in the VC-4 and the location of the first byte of the VC-n is indicated by the TUn pointer. . The C4 carries a 140 Mbit/s PDH signal. If lower speed PDH signals need to be transported these are mapped into a tributary unit (TU).

..... PTR Pointer 3 VC-12s or 4 VC-11s in 1 × TUG-2 T1518100-95 ... . POH VC-2 VC-1 ..Tributary Units in a VC-4 86 Columns TUG-2 TU-1 PTRs .. .. TUG-2 TUG-3 (7 × TUG-2) POH TU-2 PTR Fixed stuff Fixed stuff POH . .

The figure shows this over a period of 500 µs. VC-12s are distributed over four frames known as a VC multiframe. V5 byte: V5 RR R RR RR R 32 bytes RR R RR RR R J2 C1 C2 O O O O R R 32 bytes R RR RR RR R N2 C1 C2 O O O O R R 140 bytes 32 bytes R RR RR RR R K4 C 1 C2 R R R R R S 1 S2 D D D D D D D 31 bytes R RR RR RR R T1523020-96 D R O S C Data bit Fix ed stuff bit Overhead bit Justification opportunity bit Justification c ontrol bit BIP-2 1 2 REI 3 RFI 4 5 Signal Label 6 7 RDI 8 .Tributary units 2 Mbit/s are mapped asynchronously into a VC-12.

STM Section Overheads 9 Bytes Nine rows of nine bytes at the front of the SDH frame form the section overhead. The last six rows are the multiplex section overhead. A1 A1 A1 A2 A2 A2 J0 B1 D1 9 rows B2 B2 B2 K1 D4 D7 D10 D5 D8 D11 K2 D6 D9 D12 MSOH E1 E1 D2 F1 D3 RSOH S1 Z1 Z1 Z2 Z2 M1 E2 E2 . The first three rows are the regenerator section overhead.

The overheads have been modified in the latest release of G.VC-4 path overheads The first column of the VC-4 is the VC-4 path overhead.707 Old VC-4 POH J1 B3 C2 G1 9 rows F2 H4 Z3 Z4 Z5 new VC-4 POH J1 B3 C2 G1 9 rows F2 H4 F3 K3 N1 .

707 V5 J2 125 us 35 by tes J2 125 us 35 by tes Z6 125 us 35 by tes N2 125 us 35 by tes Z7 125 us 35 by tes K4 125 us 35 by tes . The VC-12 frame is spread over four frames to form a VC-12 multiframe. The overheads have been modified in the latest release of G. Each of the four frames in the multiframe contains an overhead byte.VC-12 overhead old VC-12 OH VC-12 new VC-12 OH VC-12 V5 125 us 35 by tes 125 us 35 by tes The first byte of the VC-12 is the VC-12 path overhead.

V5 Byte The bits in the V5 byte are allocated as follows: BIP-2 1 2 REI 3 RFI 4 5 Signal Label 6 7 RDI 8 .

Framing bytes (A1 & A2) The framing byte locate the beginning of the STM frame Byte A1 A2 comments First framing byte A1:11110110 Second framing byte A2:00101000 .

812 1000 Traceable to Local G.812 1011 Derived from SETS 1111 Don't use for Synchronisation. .Synchronisation status marker byte (S1).811 0100 Traceable to Transit G. The synchronisation status marker byte contains information about the quality of the embedded timing Byte S1 comments Synchronistion status marker byte S1 Byte: bit 5 -8 0000 Quality unknown 0010 Traceable to PRC G. Other bytes are reserved.

Entire frame B2 parity: Mux OH + AU-4 Regen OH 9 rows AU-4 9 rows Regen OH AU-4 Mux OH Mux OH 9 column s 261 co lumns 9 columns 26 1 columns B3 parity . B3) The BIP is calculated over the previous frame/multiframe BIP Bits & Bytes Coverage B1 parity .Bit interleaved parity (B1.Virtual Container AU-4 Regen OH VC-4 V5 bits 1 & 2: TU-12 frame AU-4 Regen OH 9 rows Path TU-1 2 poin ter VC-4 Path OH VC-4 Payload 9 rows Path VC-4 Payload T U-12 Mux OH OH Mux OH OH Payload 9 column s 261 co lumns 9 columns 26 1 columns . B2.

Bit interleaved parity (B1. Bit interleaved parity . The BIP is calculated over the previous VC-4. VC-12 path bit interleaved parity .2. V3. Three bytes of a 24 bit multiplex section bit interleaved parity . B2.Calculated over the previous STM-1 frame excluding the first three rows of the SOH before scrambling. .3 B3 V5 comments Bit interleaved parity .8 bits for entire previous frame before scrambling. V2.2 bits for previous frame The BIP is calculated over the previous VC-12 frame including VC-12 path overheads but excludes V1. B3) Byte B1 B2 #1.8 bits for entire previous frame before scrambling.

Orderwire (E1 & E2) The E byte carry the orderwire channels. The relief byte is used for ring protection E1 – Regenerator section orderwire E2 – Multiplex section orderwire .

DCC channels (D1 to D3 and D4 to D12) The DCC channels are used Element Management Software to pass management information between sites. Multiplex section data communications channel The D4 to D12 bytes are a 576 kbit/s DCC channel. Byte D1 to D3 comments Regenerator section data communications channel (DCC) The D1 to D3 bytes are a 192 kbit/s DCC channel. D4 to D12 .

F3 & N2) The user channels appear at a front panel connector for use by the network operator. The FLX150/600 supports either G. VC-4 path user channel VC-4 path user channel Network operator byte - F2 Z3 (F3) Z6 (N2) . Byte F1 User channel comments 64 kbit/s user channel.User channels (F1.703 co-directional or contradirectional interface. This user channel can be passed through at a regenerator. F2.

Section/Path trace bytes (J0. Trace value can be entered for section id between national boundaries. Path trace byte J1 J2 . J1. ITU-T: High order path access point identifier. J2) The section/path trace supports a string assigned to a path. this verifies continued connection to the intended transmitter Byte J0 comments Regenerator section trace use is not defined in ITU-T.

Remote error indication MS REI (M1) Indicates the count of the interleaved bit blocks (1 to N) that have detected an error. Byte M1 comments Multiplex section remote error indication (MS REI) .

This byte is sent from the receiver back to the originator.High order path management Signal label (C2) Byte C2 com m en ts Signal label: This byte indicates the composition of the VC-4 . Indicates the multiframe position indicator for the VC-12 . Path Status Byte G1 comments Path status byte. Multiframe Pointer Byte H4 comments VC-4 multiframe pointer.

Low order path management The VC-12 path overhead signals are held in the V5 byte. Byte V5 bit 3 V5 bit 4 V5 bit 5-7 V5 bit 8 Comments Remote error indication (REI): set to one if one or more error is detected at receiver in the BIP-2. Standard implementation on FLX and FLM Remote failure indication (RFI). Set to one if a failure is declared . VC-12 signal label. VC-12 path remote defect indication (RDI) Set to 1 if an AIS or a signal failure condition is received. .

SDH Low er O rder Pat h Lay er PDH LPA Cr os s Connec tion 1 LPT LPC HPA Higher O rder Pat h Lay er Cross Connec tion HPT H PC M ultiple xer S ection Lay er M SA M ST Regenerator S ection Lay er P hys ica l M edia Lay er RSA R ST S PI PPI . The transmission path passes through five layers in this connection.SDH layers The following diagram shows 2Mbit/s multiplexed to STM1.

Termination points Within a layer each path ends at a ‘termination point’ A path in SDH can be visualised as a pipe. In the diagram the 140Mbit/s path passes unaltered through the multiplex section0 hi gh or de r p ath M ux se ctio n 1 40 Mb it/s A DM A DM 14 0 M bi t/s S TM-1 ring A DM A DM 140 Mbit/ s in S ection O H in Se ction O H out 140 M bit/s out .

Example V C .12 te rm in atio n V C -1 2 X -c o n ne c t V C -4 X .1 E1 ST M-4 L ow e r O rd e r P a th L a ye r H ig h e r O rd e r P a th L a ye r M u ltip le x S e c tio n L a ye r R eg e ne r ato r S e c tio n L a ye r P hy s ic a l in ter fac e L a ye r V C .Layers .c on n ec t R e ge n V C -1 2 T e rm in atio n .12 P at h r e m a in s u n in te r r u p te d b e tw e e n te r m in a tio n p o in ts M u x s e ct io n M u x se ct io n E1 AD M M ux s e ct io n R egen s e c tio n R egen s e c tio n E1 S T M -1 r in g A DM D X C 4 /4 Te rm in a l ST M .

Alarms and layers STM Physical Media Layer R eg en er ator Sectio n Layer Mu ltiplexer Sectio n Layer LO S LOS LO F RS-BIP LOF RS-BIP Each defect indication is associated with a layer MS-AIS MS-BIP MS-RDI AU-AIS AU-LO P MS-AIS MS-BIP MS-RDI AU-AIS AU-LOP VC-4 BIP VC-4 RE I VC-4 RDI VC-4 LOM E1 E1 ADM Low order path Mux section H igher Order Path Layer VC-4 BIP VC-4 REI VC-4 RDI VC-4 LOM Lo wer Order Path Layer VC-12 AIS VC-12 LO P VC-12 BIP VC-12 REI VC-12 RFI VC-12 RDI VC-12 AIS VC-12 LOP VC-12 BIP VC-12 REI VC-12 RFI VC-12 RDI LOS STM-1 ring ADM PDH Physical In terface Layer LO S .

B IP E rr o r ( B 2 ) M S.UN EQ H P .Ex c Er ro r (B 2 ) A U .FE R F LP .FE R F LP .FE R F "1 " A U .7 8 2 1 0 N o v e m b e r 1 9 92 .LO P H O P a t h s ig n a l p a s s e d H O V C w it h PO H a n d th r o u g h p a y lo a d "1 " U n u se d H PC O u t p u t / HP.A IS "1 " L O P a t h s ig n a l p a s s e d t h r o u g h L O VC w it h P O H a n d u n s p e c if ie d L O u n e q u ip p e d sig n a l LP .SL M H P -B IP E rr o r ( B 3) H P .FE B E LP .TIM H P .FE B E SD H M a in t e n a n c e Sig n a l In t e r a c t io n G .A IS A U .B IP E r ro r ( B 1 ) R e g e n s ig n a l p a s se d "1 " th ro u g h "1 " M S. These are described in the G.Signalling interactions Each signal has a consequent action.SLM L P -B IP Er ro r ( V 5 ) LP .LO M / TU -L O P U n u se d LP C O u t p u t / L P -U N EQ p a y lo a d "1 " "1 " TU .A IS "1 " A IS F EB E F ER F LO S LO F LO M LO P T IM SL M U N EQ D e te c ti o n G e n e ra ti o n In s e rti o n o f A IS s i g n a l A l a rm In d i c a t o n Si g n a l i F a r e n d b l o c k e rr o r F a r e n d re c e i v e f a i l u r e Lo s s of s ig na l L o s s o f fr a m e L o ss o f m u l t i fra m e L o s s o f p o i n te r T ra c e i d e n ti f i e r m i s m a tc h Si g n a l l a b e l M i s m a tc h Un e q u p p e d si g n a l p e r G 7 0 9 i M S.FE B E H P .782 diagram P h y s ic a l Se c tio n Re g e n Se c tio n M u ltip le x Se c t io n H ig h e r O rd e r P a t h Lo w e r O rd e r P a t h SPI RST N o te 1 M ST M SA HPO M H UG H PC HPT HPA LP O M LU G LP C L PT LP A LO S "1 " LO F R S.FE R F M S.FE B E TU .UN EQ u n s p e c if ie d H O u n e q u ip p e d s ig n a l HP.A I S M S.TIM LP .FE R F H P .U N EQ "1 " LP .FE R F H P .A IS H P .

SETS: Synchronous Equipment Timing Source The SETS function controls the selection of the timing source to be used as a reference in the SDH equipment The SETG function is a DPLL function that smoothes the clock and provides holdover on loss of clock. Select A Select C Output clk STM-N in PDH in Ext ref Select B Sys clk SETG .

PRC PRC 1 NE st 1 NE st 2 NE nd 2 NE nd Timing recovery N NE th N NE th G.812 clock G. In this case a SETG (DPLL) is in the clock path at each network element (NE) Timing The PRC is the network recovery providers primary reference clock The G.Sync distribution in the SDH network SDH can be used as a timing transport in a telecommunications network.812 clock .812 clock is the network providers exchange clock.

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