TRNG I HC S PHM K THUT HNG YN KHOA CNG NGH THNG TIN --------- oOo ---------

Bo Co

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Nghin cu v VHDL & FPGA
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Hng Yn Thng 3 nm 2011

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I.

VHDL

I.1. VHDL l g ? L ngn ng m phng phn cng s dng thit k cc vi mch, thit b.... in t da trn m t cc h thng k thut s v tn hiu hn hp.
1. u im.
C tnh cng cng H tr nhiu bi nhiu cng ngh v nhiu phng php thit k. c lp vi cng ngh. Kh nng m t m rng. Kh nng trao i kt qu Kh nng h tr thit k mc ln v kh nng s dng li cc thit k.

2. ng dng.
Gm 2 ng dng chnh v trc tip l cc ng dng trong cc thit b c th lp trnh c : FPGA & ASIC.

3. Quy trnh thit k mch. Gm 3 giai on: Th nht: Thit k bng vit m VHDL, m ny c lu vo file c ui l .vhd v c tn cng tn vi tn thc th. Th hai : Bc u tin l bin dch, m VHDL s c chuyn vo netlist tng cng. Bc tip theo l ti u v tc v phm vi trn Netlist Kim tra li pht sinh. Th ba : ng gi phn mm, s sp xp vt l din ra to ra mt n cho ASIC hoc FPGA. 4. Cng c pht trin. Cng c Active HDL : To m VHDL v m phng.
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Cng c EDA : l cng c t thit k mch in t. Dng thc thi mch v m phng. Cng c ng gi.

I.2. Cu trc m.
1. Package (Khi)
Lu tr d liu chung cho cc Entity, gm 2 phn : m t giao din v phn thn n nh cc hot ng c th ca Package. Tt c cc i tng khai bo trong package c th c truy bi bt k mt thit k no bng cch s dng mnh use v khai bo library. Khai bo th vin :

Library library_name; Use library_name.package_name.package_part;

Mt s th vin chun: Ieee.std_logic_1164 Standard Work

2. Entity (Thc th)

M t ng vo , ra ca mt thit k. Mc cao nht ca bt k mt thit k VHDL l mt khai bo entity n, khi thit k VHDL tn ca file lu tr phi trng vi tn theo sau t kho entity. IN : M t ng vo OUT : M t ng ra. INOUT m t tn hiu 2 chiu , BUFFER m t tin hiu t bn trong. M t trong khai bo Port.

3. ARCHITECTURE. (Cu trc)

M t mi lin h gia ng vo v ra, gm 3 kiu biu din chnh. M t cu trc (Structure) M t dng d liu (Data Flow) 3/7 Phin bn: 1.0

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4. Khai bo trong VHDL

a. Cc kiu h tr Kiu lit k (STD_ULOGIC , STAGE_TYPE (mc tru tng cao hn)) Kiu nguyn. Kiu dy mt chiu. Kiu bn ghi. Tiu chun IEEE.

b. Cc kiu khng h tr. c. Cc kiu con.

5. Cc i tng trong VHDL a. Hng s. Constant constant_name: type_name [:=value]; b. Khai bo bin s v tn hiu. Bin s : Variable variable_name : type_name [:=value]; Khai bo tn hiu : Singal singal_name: type_name[:=value]; c. Cc gi tr khi ng.
C 3 gi tr ban u. -

Mc nh t nh ngha kiu hay kiu con. Gi tr ban u khi i tng c khai bo Gi tr c gn khi s dng mt pht biu lc bt u qu trnh.

d. Cc ton t s hc. L lun ( Or and nor xnor xor nand)

L kiu thp nht. Ton t not chp nhn cc kiu d liu Bit, BOOLEAN, Vector vi kch thc ging nhau.

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 n 3 Ton t nand v nor khng kt hp vi nhau trong c php lien tc, phi ngn cch nhau bng du (). Quan h (= /= > < >= <=)

Lun tr v kiu BOOLEAN 0 v 1 v l kt qu ca s so snh hai ton hng cng mt kiu c bn. Cng (+ - &)

Ton t cng v tr nh ngha cho cc ton hng s nguyn. Tt c cng c tng hp u ci t cc ton t ny v thng s dng vi mt s rng buc. Dch (Sll Srl Sla SRA Rol Ror) Ton t nhn (/ , mod, rem ) Hn hp.

e. Php gn bin s Bin s 1 := Bin s 2 f. Php gn tn hiu. Ging php gn bin, ch xy ra sau lnh ng b (lnh wait). Singal <= mt tn hiu sau lnh ng b. g. Lnh ng b. (Lnh wait) C 2 cch dung lnh wait khc nhau l : i mt s kin trn mt tn hiu tu thuc vo danh sch. Danh sch ca wait phi bao gm tt c tn hiu c c trong qu trnh. i s kin xy ra trn tn hiu ng h (Clock). Tn hiu ny l duy nht, cc clock c xc nh bng cc s kin v sn xung.

h. Lnh iu kin. Lnh if (elseif v else) : lnh ch ra cc mc thc hin u tin trong r nhnh. Lnh case : cc gi tr l duy nht, khng c tnh u tin.

i. Lnh lp. For, While Loop..end loop : Vng lp v hn

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II. FPGA
Field-programmable gate array (FPGA) l vi mch dng cu trc mng phn t logic m ngi dng c th lp trnh c.Vi mch FPGA c cu thnh t cc b phn: Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...

FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit hn ch c th ti cu trc li khi ang s dng, cng on thit k n gin do vy chi ph gim, rt ngn thi gian a sn phm vo s dng. Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v ti lp trnh ca FPGA thc hin n gin hn; kh nng lp trnh linh ng hn; v khc bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha khi lng ln cng logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n. Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln nh Xilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnh thit k, cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny nh Synopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bc ca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi l m RTL). 1.1. Cu trc ca FPGA.

Mi nh sn xut FPGA c ring cu trc FPGA, nhng nhn chung cu trc c th hin ging nh trong hnh bn trn. Cu trc FPGA bao gm c configuration logic blocks (CLBs), configurable I/O blocks (IOB), v programmable interconnect. V tt nhin, chng c mch clock truyn tn hiu clock ti cc logic block, v thm vo c cc logic resources nh ALUs, memory v c th c c decoders. Cc phn t lp trnh c ca FPGA c 2 dng c bn l cc RAM tnh (Static RAM) v anti-fuses.

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1. Configurable Logic Blocks (CLBs)

Configurable Logic Blocks (CLBs) bao gm cc Look-Up Tables (LUTs) rt linh ng c chc nng thc thi cc logic v cc phn t nh dng nh l cc flip-flop hoc cc cht (latch). CLB thc hin phn ln cc chc nng logic nh l lu tr d liu,..

2. Configurable I/O Blocks

Input/Output Blocks (IOBs) iu khin dng d liu gia cc chn vo ra I/O v cc logic bn trong ca FPGA. N bao gm c cc b m vo v ra vi 3 trng thi v iu khin ng ra dng open collector. Phn ln l c trko ln ng ra v thnh thong li c tr ko xung.IOBs h tr lung dliu 2 chiu (bidirectional data flow) v hot ng logic 3 trng thi (3 state). H tr phn ln cc chun tn hiu, bao gm mt vi chun tc cao, nh Double Data-Rate (DDR).

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