1X4 DEMULTIPLEXER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux is Port ( input : in STD_LOGIC; s : in STD_LOGIC_VECTOR (01 downto 00); o : out STD_LOGIC_VECTOR (03 downto 00)); end dmux; architecture Behavioral of dmux is begin process(input,s) begin case s is when "00" => o<=('0','0','0',input); when "01" => o <=('0','0',input,'0'); when "10" => o<= ('0',input,'0','0'); when "11" => o<= (input,'0','0','0');

end case. end Behavioral. . end process.when others => null.

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