Features

• High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 16K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K Byte Internal SRAM – Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages – 2.7 - 5.5V for ATmega16L – 4.5 - 5.5V for ATmega16 Speed Grades – 0 - 8 MHz for ATmega16L – 0 - 16 MHz for ATmega16 Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA

8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega16 ATmega16L Summary

• • • •

2466HS–AVR–12/03

Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.

Pin Configurations

Figure 1. Pinouts ATmega16
PDIP
(XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)

TQFP/MLF
PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2

PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO)

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2

ATmega16(L)
2466HS–AVR–12/03

(INT1) (OC1B) (OC1A) (ICP1) (OC2)

PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3

PB7 PD0 .ATmega16(L) Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. & TIMING RESET INSTRUCTION DECODER Y Z CONTROL LINES ALU INTERRUPT UNIT INTERNAL CALIBRATED OSCILLATOR AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP.PD7 3 2466HS–AVR–12/03 . Block Diagram PA0 . By executing powerful instructions in a single clock cycle.PA7 VCC PC0 .PC7 Block Diagram PORTA DRIVERS/BUFFERS PORTC DRIVERS/BUFFERS GND PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE AVCC MUX & ADC AREF PROGRAM COUNTER ADC INTERFACE TWI STACK POINTER TIMERS/ COUNTERS OSCILLATOR PROGRAM FLASH SRAM INTERNAL OSCILLATOR XTAL1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X WATCHDOG TIMER OSCILLATOR XTAL2 MCU CTRL. INTERFACE PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 . Figure 2. the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The Power-down mode saves the register contents but freezes the Oscillator. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip. the crystal/resonator Oscillator is running while the rest of the device is sleeping. allowing the user to maintain a timer base while the rest of the device is sleeping. A/D Converter. the Asynchronous Timer continues to run. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities. This allows very fast start-up combined with low-power consumption. they will source current if the internal pull-up resistors are activated. in-circuit emulators.. by a conventional nonvolatile memory programmer. On-chip Debugging support and programming. or by an On-chip Boot program running on the AVR core. a serial programmable USART. Ground. 512 bytes EEPROM. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers. 10-bit ADC with optional differential input stage with programmable gain (TQFP package only). if the A/D Converter is not used. disabling all other chip functions until the next External Interrupt or Hardware Reset. an 8-channel. The Port A pins are tri-stated when a reset condition becomes active.PA0) Digital supply voltage. In Extended Standby mode. The boot program can use any interface to download the application program in the Application Flash memory. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC. and evaluation kits. and interrupt system to continue functioning. program debugger/simulators. a JTAG interface for Boundary-scan. SRAM. The Idle mode stops the CPU while allowing the USART. 4 ATmega16(L) 2466HS–AVR–12/03 . the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. 1K byte SRAM. 32 general purpose working registers. a programmable Watchdog Timer with Internal Oscillator. Pin Descriptions VCC GND Port A (PA7.The AVR core combines a rich instruction set with 32 general purpose working registers. When pins PA0 to PA7 are used as inputs and are externally pulled low. macro assemblers. Port A also serves as an 8-bit bi-directional I/O port. even if the clock is not running. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. 32 general purpose I/O lines. In Standby mode. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. Timer/Counters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU). The device is manufactured using Atmel’s high density nonvolatile memory technology. to minimize switching noise during ADC conversions. Two-wire interface. an SPI serial port. providing true Read-While-Write operation. Software in the Boot Flash section will continue to run while the Application Flash section is updated. Internal and External Interrupts. Port A serves as the analog inputs to the A/D Converter. both the main Oscillator and the Asynchronous Timer continue to run. three flexible Timer/Counters with compare modes. In Power-save mode. and six software selectable power saving modes. SPI port. a byte oriented Two-wire Serial Interface.

A low level on this pin for longer than the minimum pulse length will generate a reset. Port D (PD7.. RESET Reset Input. PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. the pull-up resistors on pins PC5(TDI). As inputs. The Port B pins are tri-stated when a reset condition becomes active.PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port B pins that are externally pulled low will source current if the pull-up resistors are activated. it should be connected to VCC through a low-pass filter. Port B also serves the functions of various special features of the ATmega16 as listed on page 56. Output from the inverting Oscillator amplifier. Shorter pulses are not guaranteed to generate a reset.PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). AREF is the analog reference pin for the A/D Converter.PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port C also serves the functions of the JTAG interface and other special features of the ATmega16 as listed on page 59.. even if the ADC is not used. If the ADC is used. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. even if the clock is not running. even if the clock is not running. even if the clock is not running. If the JTAG interface is enabled. As inputs.ATmega16(L) Port B (PB7. Port C (PC7. XTAL1 XTAL2 AVCC AREF 5 2466HS–AVR–12/03 .. Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Port D also serves the functions of various special features of the ATmega16 as listed on page 61. The Port D pins are tri-stated when a reset condition becomes active. The Port C pins are tri-stated when a reset condition becomes active. even if the clock is not running. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. AVCC is the supply voltage pin for Port A and the A/D Converter. The minimum pulse length is given in Table 15 on page 36. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. It should be externally connected to VCC.

219 109 112 113 113 113 113 113 113 114 114 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – URSEL URSEL – – – – UMSEL – – – – UPM1 – – WDTOE – UPM0 – USBS – – AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 – UCPOL EEAR8 TCR2UB WDP0 127 129 129 130 41 165 164 17 17 17 EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC RXCIE ACD REFS1 ADEN WCOL SPE TXC TXCIE ACBG REFS0 ADSC – DORD UDRE UDRIE ACO ADLAR ADATE – MSTR FE RXEN ACI MUX4 ADIF – CPOL DOR TXEN ACIE MUX3 ADIE – CPHA PE UCSZ2 ACIC MUX2 ADPS2 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 17 64 64 64 64 64 64 65 65 65 65 65 65 140 140 138 161 162 163 165 200 215 217 218 218 180 USART I/O Data Register USART Baud Rate Register Low Byte ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 180 6 ATmega16(L) 2466HS–AVR–12/03 . 67 68 83.Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31(1) ($51)(1) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(2) ($40)(2) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) Name SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR Bit 7 I – SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SM2 JTD FOC0 Bit 6 T – SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SE ISC2 WGM00 Bit 5 H – SP5 INT2 INTF2 TICIE1 ICF1 – TWSTA SM1 – COM01 Bit 4 S – SP4 – – OCIE1A OCF1A RWWSRE TWSTO SM0 JTRF COM00 Bit 3 V – SP3 – – OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01 Bit 2 N SP10 SP2 – – TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02 Bit 1 Z SP9 SP1 IVSEL – OCIE0 OCF0 PGERS – ISC01 EXTRF CS01 Bit 0 C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 Page 7 10 10 83 46.133. 132 249 178 30. 229 81 83 28 225 Timer/Counter0 Output Compare Register Timer/Counter0 (8 Bits) Oscillator Calibration Register On-Chip Debug Register ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 ADTS0 COM1B1 – – COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10 55.86.199. 67. 114. 66 39. 115. 132 84.

3. 2. thus clearing the flag. 7 2466HS–AVR–12/03 . Some of the Status Flags are cleared by writing a logical one to them. The CBI and SBI instructions work with registers $00 to $1F only. writing a one back into any flag read as set. 4. the OSCCAL Register is always accessed on this address. Reserved I/O memory addresses should never be written. Refer to the USART description for details on how to access UBRRH and UCSRC. reserved bits should be written to zero if accessed. Note that the CBI and SBI instructions will operate on all bits in the I/O Register.ATmega16(L) Address $01 ($21) $00 ($20) Name TWSR TWBR Bit 7 TWS7 Bit 6 TWS6 Bit 5 TWS5 Bit 4 TWS4 Bit 3 TWS3 Bit 2 – Bit 1 TWPS1 Bit 0 TWPS0 Page 179 178 Two-wire Serial Interface Bit Rate Register Notes: 1. Refer to the debugger specific documentation for details on how to use the OCDR Register. When the OCDEN Fuse is unprogrammed. For compatibility with future devices.

C.C Rdh:Rdl ← Rdh:Rdl .K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF .N. Rr Rd.V Z.C.N. Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg.N. Rr Rd. Rr Rd.K Rd.Rr Rd.N.K Rd.H Z.K . Rr Rdl.H Z. K Rd. Rr Rd.N.C.C.V Z.C. b P.S Z.V.C.V.N.N.N. Rr Rd.V.V. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare.C.N.N.V.C Rd ← Rd .V Z.N.H Z.V. K Rdl. b P.V.K Rd. Rr Rd. Rr Rd. Rr Rd Rd Rd. Signed Branch if Less Than Zero.V.N.K Rd Rd Rd Rd Rd Rd.V Z.N.C. N.Rr Rd. N.V. Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd .N.C Z.C Z.N. K Rd.N.V Z.V Z.H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← k PC ← PC + k + 1 PC ← Z PC ← k PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 R1:R0 ← (Rd x Rr) << BRANCH INSTRUCTIONS 8 ATmega16(L) 2466HS–AVR–12/03 .K Rr.C None None None None None None None I None Z. k k k k k k k k k k k k k k k k k k k k Operands Rd.H Z. b Rr.C.C.C.K Rd ← Rd .C Z.C.N.Rr Rd ← Rd .H Z.Rr Rd.V Z. k s. Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal.H Z.K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr Flags Z.V Z. K Rd.V Z.N.N.V Z. b s.Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd.H Z. Rr Rd.C Z.N.N.V.C.S Z. Rr Rd.H Z.H Z.Rr . N.V. Rr Rd.V Z.V.V None Z.C Z.

b Rd.b P. Rd(7) ← 0 Rd(0)←C.. Rr . Rr Y+. Rr Rr Rd P.b) ← 0 Rd(n+1) ← Rd(n). k X.C. Rr Rd. Y Rd.V Z. Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr. Z ← Z+1 Z ← Z .Rd(n)← Rd(n+1). Z+ Operands k k Rd. Store Indirect and Pre-Dec.N. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Load Indirect and Pre-Dec.1.C.X. Rr Z+.C←Rd(0) Rd(n) ← Rd(n+1). .1. Y+ Rd. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Rr X+.Y.1.N.V Z. Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z). Z ← Z + 1 Z ← Z . (X) ← Rr (Y) ← Rr (Y) ← Rr. Rr Rd. Rr -Z. Rr Description Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect Load Indirect and Post-Inc.1.b) ← 1 I/O(P. (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z).Rd(n+1)← Rd(n).. n=0.V Z. X Rd. Operation if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X). . Z+q Rd.. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc.C←Rd(7) Rd(7)←C..N. Rr . Y ← Y + 1 Y ← Y . -Z Rd. Rr Y+q..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I← 0 S←1 S←0 V←1 Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z. P P. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc.0)←Rd(7. Store Indirect and Pre-Dec.4)←Rd(3. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc.V None SREG(s) SREG(s) T None C C N N Z Z I I S S V #Clocks 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS CLV SET CLT SEH Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG V←0 T←1 T←0 H←1 V T T H 1 1 1 1 9 2466HS–AVR–12/03 . b Rd. Z+ Rd. Z Rd.Rr k. X ← X + 1 X ← X .X Rd. Load Indirect and Pre-Dec.b Rd Rd Rd Rd Rd Rd s s Rr.ATmega16(L) Mnemonics BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV Rd.1. Rr Z+q.Rd(7.C.4).C.6 Rd(3.C. X+ Rd.N.Y Rd. (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr. X ← X + 1 X ← X . Rr Y. Y ← Y + 1 Y ← Y .V Z. K Rd. Load Indirect and Pre-Dec.Y+q Rd. Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK I/O(P. Z Rd.Rr Z. Rd ← (X) Rd ← (Y) Rd ← (Y).1. Rd(0) ← 0 Rd(n) ← Rd(n+1).N.

Mnemonics Operands Description Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Break Operation H←0 H Flags #Clocks 1 1 1 1 N/A CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-Chip Debug Only None None None None 10 ATmega16(L) 2466HS–AVR–12/03 .

Thin (1.5V Ordering Code ATmega16L-8AC ATmega16L-8PC ATmega16L-8MC ATmega16L-8AI ATmega16L-8PI ATmega16L-8MI 16 4.ATmega16(L) Ordering Information Speed (MHz) 8 Power Supply 2.5 . Plastic Dual Inline Package (PDIP) 44-pad.7 . 0.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin.600” Wide.0 mm body.50 mm. Micro Lead Frame Package (MLF) 11 2466HS–AVR–12/03 .5V ATmega16-16AC ATmega16-16PC ATmega16-16MC ATmega16-16AI ATmega16-16PI ATmega16-16MI Package 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 Operation Range Commercial (0oC to 70oC) Industrial (-40oC to 85oC) Commercial (0oC to 70oC) Industrial (-40oC to 85oC) Package Type 44A 40P6 44M1 44-lead. 7 x 7 x 1.5. lead pitch 0.5.

Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0. 44-lead.75 Note 2 Note 2 NOTE A2 A Notes: 1. Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO.75 9. Dimensions D1 and E1 do not include mold protrusion.10 0. This package conforms to JEDEC reference MS-026.25 mm per side.0 mm Body Thickness. B R 12 ATmega16(L) 2466HS–AVR–12/03 . E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose.10 12.30 0.25 10.05 12.10 mm maximum.75 9. 44A REV. 1.00 12. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. CA 95131 TITLE 44A.8 mm Lead Pitch.20 0.00 – – – 0. Lead coplanarity is 0. Allowable protrusion is 0. Variation ACB.09 0. 2.15 1.00 12.90 0.00 10.05 0.00 10. 10 x 10 mm Body Size.90 11.45 NOM – – 1.80 TYP MAX 1. 0.95 11.45 0.25 10.20 0.

559 1.048 0.494 NOM – – – – – – – – – – 2. Variation AC. 40P6 REV.070 15. B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose.25 mm (0.556 0.651 3.462 0.540 TYP MAX 4.381 17.826 – 52. 40-lead (0.970 0.356 1.600"/15. B R 13 2466HS–AVR–12/03 .381 52. CA 95131 TITLE 40P6. Mold Flash or Protrusion shall not exceed 0.578 15.ATmega16(L) 40P6 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.875 13. This package conforms to JEDEC reference MS-011.041 3. Dimensions D and E1 do not include mold Flash or Protrusion.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.203 15.010"). 2.526 Note 2 Note 2 NOTE Notes: 1.240 13.

30 b BOTTOM VIEW e D2 E E2 e 5. 44-pad.23 7.00 BSC 0. Lead Pitch 0.00 5.55 0. 1 (SAW Singulation) VKKD-1.0 mm Body.18 0.00 BSC 5.20 0. 44M1 REV.25 REF MAX 1.80 – NOM 0.50 BSC 5.90 0. JEDEC Standard MO-220.50 mm Micro Lead Frame Package (MLF) DRAWING NO.02 0.20 7.44M1 D Marked Pin# 1 ID E SEATING PLANE TOP VIEW A1 A3 A L D2 Pin #1 Corner SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) E2 SYMBOL A A1 A3 b D MIN 0.00 0.75 01/15/03 2325 Orchard Parkway San Jose.40 Notes: 1.35 0. CA 95131 TITLE 44M1. Fig. 7 x 7 x 1.40 5.05 NOTE 0. C R 14 ATmega16(L) 2466HS–AVR–12/03 .00 5. L 0.

the problem is not visible. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. the problem is not visible. G • IDCODE masks data from TDI input 1. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. the problem is not visible.ATmega16(L) Errata ATmega16(L) Rev. – ATmega16(L) Rev. Problem Fix / Workaround – – If ATmega16 is the only device in the scan chain. Data to succeeding devices are replaced by all-ones during Update-DR. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. Problem Fix / Workaround – – If ATmega16 is the only device in the scan chain. the ATmega16 must be the fist device in the chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. I The revision letter in this section refers to the revision of the ATmega16 device. 15 2466HS–AVR–12/03 . Problem Fix / Workaround – – If ATmega16 is the only device in the scan chain. Data to succeeding devices are replaced by all-ones during Update-DR. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously. • IDCODE masks data from TDI input 1. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. the ATmega16 must be the fist device in the chain. H • IDCODE masks data from TDI input 1. – ATmega16(L) Rev. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain.

– If the Device IDs of all devices in the boundary scan chain must be captured simultaneously. 16 ATmega16(L) 2466HS–AVR–12/03 . the ATmega16 must be the fist device in the chain.

Updated “Calibrated Internal RC Oscillator” on page 27. 3. Added note 2 to Figure 126 on page 251. 1. 8. 2. Updated description for the JTD bit on page 229. Added a note regarding JTAGEN fuse to Table 105 on page 259. Removed “Preliminary” from the datasheet. Changed ICP to ICP1 in the datasheet. Added a proposal for solving problems regarding the JTAG instruction IDCODE in “Errata” on page 15. 2.ATmega16(L) Datasheet Change Log for ATmega16 Changes from Rev. Updated Table 15 on page 36. All page numbers refer to this document. 7. 10. 17 2466HS–AVR–12/03 . 13. 9. Table 82 on page 215 and Table 115 on page 274. 5. Updated “JTAG Interface and On-chip Debug System” on page 34. Updated “ATmega16 Typical Characteristics” on page 297. Updated assembly and C code examples in “Watchdog Timer Control Register – WDTCR” on page 41. 2466E-10/02 to Rev. Fixed typo for 16 MHz MLF package in “Ordering Information” on page 11. 2466F-02/03 to Rev. 2466F-02/03 All page numbers refer to this document. Updated Figure 46 on page 101. 4. 2466G-10/03 This section contains a log on the changes made to the datasheet for ATmega16. 2466H-12/03 Changes from Rev. 11. Updated “Test Access Port – TAP” on page 220 regarding JTAGEN. Added the section “Unconnected pins” on page 53. 1. 12. All page numbers refer to this document. 3. 14. Added note about masking out unused bits when reading the Program Counter in “Stack Pointer” on page 10. 2466G-10/03 to Rev. 1. Added Chip Erase as a first step in “Programming the Flash” on page 286 and “Programming the EEPROM” on page 287. 6. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page 289. Changes from Rev.

2466C-03/02 18 All page numbers refer to this document. 2466B-09/01 to Rev. 2. Added section “EEPROM Write During Power-down Sleep Mode” on page 20. 7. 5. Updated the following tables: Table 4 on page 24. Added note about frequency variation when using an external clock. Added Table 73. 2466D-09/02 to Rev. 3. Table 15 on page 36. 9. Table 121 on page 293. and Table 122 on page 295. 2466C-03/02 to Rev. 15. Note added in “External Clock” on page 29. 12. Table 42 on page 83. Table 67 on page 165. 1. “DC Characteristics” on page 289. 1. Added updated “Packaging Information” on page 12. Changes from Rev. ATmega16(L) 2466HS–AVR–12/03 . Updated “DC Characteristics” on page 289. 2466E-10/02 Changes from Rev. Table 59 on page 141. which do not exist. 16. Changed all Flash write/erase cycles from 1. Various minor TWI corrections. Added note about Differential Mode with Auto Triggering in “Prescaling and Conversion Timing” on page 205. Removed ADHSM completely. “TWI Bit Rate Prescaler. Added section “Default Clock Source” on page 23. 6. Table 119 on page 291.” on page 180 to describe the TWPS bits in the “TWI Status Register – TWSR” on page 179. Removed reference to the “Multi-purpose Oscillator” application note and “32 kHz Crystal Oscillator” application note. Table 1 on page 18. Updated “Errata” on page 15. Added note in “Filling the Temporary Buffer (Page Loading)” on page 252 about writing to the EEPROM during an SPM Page Load. 1. 8. 10. Table 102 on page 257. All page numbers refer to this document. Added information about PWM symmetry for Timer0 and Timer2. Changes from Rev. Updated typical EEPROM programming time. Added tips on how to disable the OCD system in “On-chip Debug System” on page 34. 2466D-09/02 All page numbers refer to this document.000 to 10. Table 90 on page 233. Table 45 on page 110. 11.4. An extra row and a note added in Table 118 on page 291. Table 46 on page 110. 13. 14. Added “Power Consumption” data in “Features” on page 1.000.

Added JTAG version number for rev. Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 278 and “PROG_PAGEREAD ($7)” on page 278. and Table 122 on page 295. 15.ATmega16(L) 2. Removed alternative algortihm for leaving JTAG Programming mode. 13.” on page 233. Corrected ordering code for MLF package (16MHz) in “Ordering Information” on page 11. 14. Removed some of the TBD's in the following tables and pages: Table 15 on page 36. Updated TWI Chapter. Table 119 on page 291. Updated Programming Figures: Figure 127 on page 261 and Figure 136 on page 272 are updated to also reflect that AVCC must be connected during Programming mode. and Table 10 on page 28. 9. “Scan Signals for the Oscillators(1)(2)(3). Updated Table 17 on page 41 with typical WDT Time-out. Improved description on how to do a polarity check of the ADC doff results in “ADC Conversion Result” on page 214. Table 5 on page 25. 7. Added Calibrated RC Oscillator characterization curves in section “ATmega16 Typical Characteristics” on page 297. 6. H in Table 87 on page 227. Table 9 on page 27. 19 2466HS–AVR–12/03 . Added not regarding OCDEN Fuse below Table 105 on page 259. Table 116 on page 272 (table removed in document review #D). See “Leaving Programming Mode” on page 286. Table 16 on page 40. Added the note at the end of the “Bit Rate Generator Unit” on page 176. Table 121 on page 293. Updated typical start-up time in the following tables: Table 3 on page 23. Added Some Preliminary Test Limits and Characterization Data. 5. Figure 131 on page 268 added to illustrate how to program the fuses. 3. 10. Table 6 on page 26. 12. “Electrical Characteristics” on page 289. 4. 8. Corrected Table 90. Table 8 on page 27. 11. Corrected description of ADSC bit in “ADC Control and Status Register A – ADCSRA” on page 217.

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