Computer

University of Technology Engineering and Information Technology Department Final Examinations for Year 2010/2011 Class: Third Time allowed: 180 min.

SUbject: Microprocessor Systems Design Examiner: Dr. Hassan A. Jeiad

Notes: Answer Any Six Questions includes Qt.
QlI (must be answered) 20 marks There was a simple interface circuit connected to 8088 MPU, and used as a calculator that adds two BCD values (with range from 0000 to 0100) stored at memory locations ADDRI and ADDR2, while the result of the addition is stored at memory location ADDR3. The bytes stored in the above memory addresses have been formulated as shown in figure (I) in the back. The circuit is required to display the contents of ADDR 1, ADDR2, and ADDR3 in five-digit seven-segment displays as shown in figure (2) in the back. The displays are interfaced to the 8088 MPU via single 8255 parallel port. Now, answer the following: 1- Draw the complete required interface circuit. 2- In few words, suggest an efficient method to make any of the displayed numbers in digits 1, 3, and 5 represents the decimal value of the equivalent BCD value stored in the corresponding memory addresses (i.e. the BCD value 0010 in ADDRI will be displayed in the first digit as 2, while 0011 will be displayed as 3, and so on). Q2/ 10 marks Draw the minimum-mode 8-bit memory write bus cycle for the 8086 microprocessor. Be careful that the accuracy in illustrating the different events in your drawing is essential. Q3/10 marks Define each of the dedicated, reserved, and general used memories. Which one is the larger size in usual? Q4/10 marks Draw the internal structure of 256x I DRAM, the structure of DRAM consists of four blocks of 64 arrays (8x8) for each. Determine the size of Decoder and multiplexers used by your design. Q5/10 marks Make a drawing that can be used as the parity-checker/generator in the data storage memory subsystem of an 8086 MPU system. Assume that parity checking is performed independently for the upper and lower banks of the memory array and that the parity error outputs for the two banks are combined to form a single parity error signal.

it is required to receive a character in serial from Input device. Value of \ ADDR2 i -. write a continues instruction sequence that do the following: 1. show the necessary control signals in your design. 0000 4·bil BCD value 8 bits Figure (I) for QI Valu e of ADDRI -: means Pluse / R 2 3 . 3. then send it in parallel to Output device. and then draw a block diagram shows your suggestion for connecting the interface components to the 8088 microprocessor to achieve the mentioned objective.Read the status register (816). Q7/10 marks F or the 8237 DMA controller located at address 2000H in the 110 address space.--. Determine the appropriate interface components for inputting and outputting the character. means Equal :orrespondiug :IispJay a f b Value of ADDRJ \ e d c Figure (2) for Q 1 . Q8/10 marks For a certain interface circuit.J---o: I 4 5 I I Jigit no.Q6/ 10 marks Make a diagram showing how 2764 (8Kx8) EPROMs can be connected to form a 16Kxl6 program storage memory subsystem. 2. then write the values 0116 for the command register (816) and the value 8616 for the mode register (816).Write the address value 235316 to the base and current address registers of this channel (416).If channel 2 had accomplished its last data transfer task. Notice that the address of the internal flip flop is (CI6).

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