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5

CPU DC/DC

Spears Intel UMA Block Diagram

2007/08/29

ISL6262A
INPUTS

Project code : 91.4W001.001


PCB P/N : 07211
Revision : -1

Intel CPU
D

Merom 4M
FSB:667MHz/800MHz

CLK GEN
ICS9LPRS365
4

CRT

INPUTS

17

1D05V_S0
1D8V_S3

LVDS

LCD

18

SYSTEM DC/DC

DDR I/F

SVIDEO

S-Vedio
(Upsell)

SDVO

SiI 1392
(Upsell)

TPS51120

16

INPUTS

INTEGRATED GRAHPICS

DDR II 667 Channel B

LVDS, CRT I/F

8,9,10,11,12,13

PCIE x 16

HDMI
(Upsell)

23

1394

26

INTEL

PCI

PCIE x 1 & USB 2.0 x 1

AZALIA

ICH8-M

CardReader

PCIE x 1

High Definition Audio


31

PCIE x 1 & USB 2.0 x 1

ATA 66/100

AZALIA

USB 2.0 x 1

USB 2.0

LPC I/F

Azalia
CODEC

MIC IN
HP1

PCI/PCI BRIDGE

OUTPUTS

1D8V_S3

USB 2.0 x 1

KBC
Winbond WPC8763L

PATA

32

Internal Analog MIC

New Card

0D9V_S3

28

SYSTEM DC/DC
LDO
INPUTS

Mini-Card X2
802.11a/b/g
BT/UWB/Robson

29
30

Mini-Card X1

30

OUTPUTS

3D3V

2D5V

1D8V

1D5V_S0

CAMERA
(Option)

SYSTEM DC/DC

Lift Side: USB x 2

OUTPUTS

DCBATOUT

3D3V_AUX_S5

Right Side:
24
USB x 1
USB x 1(Upsell)

SPI

LDO

24

INPUTS

LPC Bus

19,20,21,22

Sigmatel
STAC 9228

HP2

TPS51100
INPUTS

WWAN(Upsell)

ACPI 1.1

Digital Mic Array

SATA

SYSTEM DC/DC

28

RJ45 CONN 28

27

PCIE x 2 & USB 2.0 x 1

PCIE

ETHERNET (10/100/1000Mb)

MDC MODEM
31
(Option)

10/100 NIC
Marvell 88E8040

10 USB 2.0/1.1 ports

RJ11 CONN
(Option)

5V_AUX_S5
5V_S5
3D3V_S5

DCBATOUT

25,26

Ricoh
R5C833

SD/SDIO/MMC
MS/MS Pro/xD26

TI TPS2231

OUTPUTS

16

Power SW

DMI I/F
100MHz
1394

OUTPUTS

DCBATOUT

Crestline-GM
AGTL+ CPU I/F

DDRII Slot 1
15
533/667

TPS5117

Host BUS
533/667MHz
DDRII 667 Channel A

VCC_CORE

SYSTEM DC/DC

5,6,7

RGB CRT

DDRII Slot 0
14
533/667

OUTPUTS

DCBATOUT

1D5V_S0

MAXIM CHARGER
MAX8731A

34

INPUTS

OUTPUTS

AD+

DCBATOUT

BAT+

2CH
SPEAKER

OP AMP
MAX9789A

HDD
33

24

ODD
24

Capacity
Button37

Touch
Pad 37

Int.
KB37

S/W
CIR

Thermal
& Fan
G792 36

Flash ROM
1MB 35
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DS2 System Block Diagram


Size
A3

Document Number

Rev

Spears-Intel

Date: Wednesday, September 12, 2007


5

Sheet
1

-1
1

of

47

TI TPS51120
3D3V/5V

CPU_CORE
ISL6262A
VID Setting

VID0
D

VID0(I / 3.3V)

VID1

1D5V_S0
Input Signal

Output Signal
VROK()

VRPWRGD

3V/5V_EN

51120_EN2

VID1(I / 3.3V)

VID2

51120_EN1

VID2(I / 3.3V)

VID3

VID3(I / 3.3V)

VID4

VID4(I / 3.3V)

VID5

VCC_CORE_PWR(O)

VSS_SENSE

PGOUT1(OD / 5V)

FOR
5.0V

CPUCORE_ON(Pull High 3D3V)

PGOUT2(OD / 3D3V)

5V_S0

EN (I / 3.3V)
DCBATOUT

VIN
5V(O)

5V_AUX_S5

VSEN(I / Vcore)

3D3V_S0

5V_S5

VCNTL

PM_SLP_S3#

VOUT(O)

VCC(I)

Input Signal

EN

(O)

(I)

AD_IN

Output Power
VCC(O)

VCC(I)

Input Signal

AD+
BAT+SENSE

VCC(I)

BT_SCL
BT_SDA

Output Signal

CLS (I / 3.3V)

XTAL2/PB4 (O/5V)
BATT (I / 3.3V)

XTAL1/PB3 (O/5V)

SCL (IO / 5V)


SDA (IO / 5V)

Output Power

DCBATOUT

VCC (O)
Input Signal

Output Signal

EN_PSV(I / 5V)

PGOUT(OD / 5V)

Output Power
VCC(O)

0D9V_DDR_VTT

5V_S5
DCBATOUT

VCC(O)

VCC

Input Power

CPUCORE_ON

Output Power
1D8V_PWR

1D8V_S3

AC_IN

AD+

BT+

VCC (O)
PB0/MOSI/AIN0
Input Power
DCIN (I)

VIN

DDR_VREF_S3

TPS51117_1D05V

VCC(I)
PM_SLP_S3#

5V_S5
DCBATOUT

Input Signal
EN_PSV(I / 5V)

VCC

<Core Design>

Output Signal
PGOUT(OD / 5V)

Input Power

Output Power
1D05V_PWR

CPUCORE_ON

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D05V_S0 (15A)

Power Block Diagram


Size
A3

VIN

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


5

MAX8731_LDO

LDO (O / 5.4V)

TPS51117_1D8V_S3
PM_SLP_S4#

CPUCORE_ON

Charger_MAX8731A

S5

VCC(I)

POK

G971

Output Signal

TI TPS51100
0.9V/DDR_VREF_S3

S3

1D5V_S0

VIN

Adapter

5V_AUX_S5

5V_S5

G9131

3D3V_S5 (5A)

VCC(I)

Input Signal

2D5V_S0

1D25V_S0

1D8V_S3

OUT

3D3V(O)

AD_JK

INPUT

5V_S5 (6A)

CHARGE_OFF

DCBATOUT

CPUCORE_ON

V5FILT(I / 5V)

RGND(I / Vcore)

Input Power

POK

2D5V_S0

3D3V_AUX_S5

Input Power

PM_SLP_S3#

EN

5V_AUX_S5
Output Power

Input Power

AD_OFF

PM_SLP_S4#

VIN

VIN

VCC(I)

3D3V_S0

1D5V_S0

VOUT(O)

1D8V_S3

PM_SLP_S3#

Input Power
DCBATOUT

VCNTL

APL5915
DCBATOUT

Voltage Sense

FOR
3.3V

5V_S5

VCC_CORE_S0(Imax=35A)

Input Signal

VCC_SENSE

Output Signal

Output Power

VID5(I / 3.3V)

CPUCORE_ON

-1
Sheet
1

of

47

INTEL ICH8-M STRAP PIN

20,22 +RTCVCC
5,6,7,8,10,11,12,20,22,34,43,47

Signal

Usage/When Sampled

HDA_SDOUT

XOR Chain Entrance/


PCIE Port Config 1 bit1,
Rising Edge of PWROK

Comment
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
Sets bit0 of RPC.PC(Config Registers:Offset 224h)

HDA_SYNC

PCIE Port Config 1 bit0,


Rising Edge of PWROK.

GNT2#

PCIE Port Config 2 bit0,


Rising Edge of PWROK.

Sets bit2 of RPC.PC(Config Registers:Offset 224h)

GPIO20

Reserved

Weak Internal PULL-DOWN.NOTE:This signal should


not be pull HIGH.

1D05V_S0

8,11,22,45 1D25V_S0

1D25V_S0

XOR Chain Entrance Strap


ICH_RSVDtp3

AZ_DOUT_ICH

0
0
1
1

0
1
0
1

Description
RSVD
Enter XOR Chain
Normal Operation(default)
Set PCIE port cofig bit1

27 1D2V_LAN_S5

1D2V_LAN_S5

28 1D5V_NEW_S0

1D5V_NEW_S0

6,11,20,21,22,28,29,30,45

GNT0#
SPI_CS1#

INTVRMEN

Top-Block Swap Override.


Rising Edge of PWROK.

Boot BIOS Destination


Selection.
Rising Edge of PWROK.
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.

Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
cycles targeting FWH BIOS space).
PCI_GNT#3 low = A16 swap override enable
Note: Software will not be able to clear the
high = default
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1
BOOT BIOS Location
Controllable via Boot BIOS Destination bit
0
1
SPI
(Config Registers:Offset 3410h:bit 11:10).
PCI
1
0
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Enables integrated VccSus1_05,VccSus1_5 and


VccCL1_5 VRM when sampled high

Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.

Enables integrated
when sampled high

PCIE LAN REVERSAL.Rising


Edge of PWROK.

This signal has weak internal pull-up.


set bit27 of MPC.LR(Device28:Function0:Offset D8)

SPKR

No Reboot.
Rising Edge of PWROK.

If sampled high, the system is strapped to the


"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)

TP3

XOR Chain Entrance.


Rising Edge of PWROK.

This signal should not be pull low unless using


XOR Chain testing.

SATALED#

GPIO33/
HDA_DOCK_EN#

VccLAN1_05,VccCL1_05 VRM

LAN100_SLP

High=Enable

3D3V_AUX_S5
3D3V_LAN_S5

3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S5

18,39,40,47 5V_AUX_S5

LPC(Default)

SM_INTVRMEN High=Enable

2D5V_LAN_S5

3D3V_AUX_S5

19,21,22,27,28,31,35,38,40,46,47

5V_AUX_S5

16,17,18,22,24,33,35,36,37,41,45,46,47

5V_S0

5V_S0

22,24,29,30,31,35,38,40,43,44,45,46,47

5V_S5

5V_S5

38,39,47 AD+

integrated VccSus1_05,VccSus1_5,VccCL1_5

18,39,40,41,42,43,44,46,47

Low=Disable
Low=Disable

AD+

DCBATOUT

DCBATOUT

14,15,45,47 DDR_VREF_S0

DDR_VREF_S0

8,14,15,45 DDR_VREF_S3

DDR_VREF_S3

18 +LCDVDD

DEFAULE HIGH

+LCDVDD

6,7,42 VCC_CORE_S0

VCC_CORE_S0

No Reboot Strap
SPKR
LOW = Defaule
High=No Reboot

Internal Pull-Up.If sampled low,the Flash Descriptor


Flash Descriptor Security Security will be overidden.if high,the Security
Override Strap
measures defined in the Flash Descriptor will be in
8.2K PULL HIGH
Rising Edge of PWROK.
effect.
This should only be used in manufacturing
environments

INTEL ICH8-M INTEGRATED


PULL-UPS and PULL-DOWNS
SIGNAL

Resistor Type/Value

HDA_BIT_CLK

PULL-DOWN 20K

HDA_RST#

NONE

HDA_SDIN[3:0]

PULL-DOWN 20K

HDA_SDOUT

PULL-DOWN 20K

HDA_SYNC

PULL-DOWN 20K

GNT[3:0]

PULL-UP 20K

GPIO[20]

PULL-DOWN 20K

LDA[3:0]#/FHW[3:0]#

PULL-UP 20K

LAN_RXD[2:0]

PULL-UP 20K

LDRQ[0]

PULL-UP 20K

LDRQ[1]/GPIO23

PULL-UP 20K

PME#

PULL-UP 20K

CFG 20

Normal Operation Reserved Lane


Only PCIE or SDVO
PCIE and SDVO are
is operation
operation simultaneous

PWRBTN#

PULL-UP 20K

SATALED#

PULL-UP 20K

SDVO_CTRL_DATA

NO SDVO Card
Present

SPI_CS1#

PULL-UP 20K

SPI_CLK

PULL-UP 20K

XOR/ALL-Z

SPI_MOSI

PULL-UP 20K

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation

SPI_MISO

PULL-UP 20K

Wistron Corporation

TACH_[3:0]

PULL-UP 20K

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

SPKR

PULL-DOWN 20K

TP[3]

PULL-UP 20K

USB[9:0][P,N]

PULL-DOWN 15K

CL_RST#

TBD

INTEL CRESTLINE STRAP PIN


CFG Strap
CFG 5
CFG 8

Low Power PCI Express

CFG 9

PCI Express Graphics


Lane Reversal

CFG 16

FSB Dynamic ODT

CFG 19

DMI Lane Reserved


Concurrent SDVO/PCIE

LOW 0

CFG 12
CFG 13
LL(00)
LH(01)
HL(10)
HH(11)

HIGH 1

DMI X 2

DMI X 4

Normal

Low Power mode

Lane Reversal

Disabled

SDVO Present

1D8V_S3

27,28 3D3V_LAN_S5
4,8,10,11,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,40,41,43,45,46,47

1D5V_S0

1D8V_S3

27,28 2D5V_LAN_S5

integrated VccLan1_05VccCL1_05
LAN100_SLP

1D5V_S0

8,11,12,14,15,44,45,46,47

20,31,34,35,36,38,39,40,47

GNT3#

+RTCVCC

1D05V_S0

Normal Mode(Lanes
number in order)
Enabled

SDVO Card Present

<Core Design>

Title

Table of Content
Size
A3

Document Number

Date: Wednesday, September 12, 2007

Rev

DS2-Intel
Sheet

-1
of

47

3D3V_S0_CK505

2
3D3V_S0_CK505

CLK_XTAL_OUT

C211
SC15P50V2JN-2-GP

VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
C566 SC4D7P50V2CN-1GP

3
2

FSA

17

USB_48MHZ/FSLA

21 H_STP_PCI#
21 H_STP_CPU#

45
44

PCI_STOP#
CPU_STOP#

14,15,21 ICH_SMBCLK
14,15,21 ICH_SMBDATA

7
6

2 33R2J-2-GP
2 33R2J-2-GP
2 33R2J-2-GP

8
10
PCI2_TME
11
PCLK_PCM_R 12
27_SEL
13
ITP_EN
14

FSB
FSC

21 CLKSATAREQ#
8 CLKREQ#_B

R355

58
57

CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8

54
53

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

CLK_PCIE_MINI3_1
CLK_PCIE_MINI3_1#

RN27

1
2

4 SRN22-3-GP
3

CLK_PCIE_MINI3 30
CLK_PCIE_MINI3# 30

SRCT7/CR#_F
SRCC7/CR#_E

51
50

CLK_PCIE_LAN1
CLK_PCIE_LAN1#

RN28

1
2

4 SRN0J-6-GP
3

SRCT6
SRCC6

48
47

CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#

RN29

1
2

4 SRN22-3-GP
3

SRCT10
SRCC10

41
42

CLK_PCIE_NEW1
CLK_PCIE_NEW1#

2
1

3
4

SRCT11/CR#_H
SRCC11/CR#_G

40
39

SRCT9
SRCC9

37
38

CLK_PCIE_MINI2_1
CLK_PCIE_MINI2_1#

SRCT4
SRCC4

34
35

CLK_MCH_3GPLL1
CLK_MCH_3GPLL1#

SRCT3/CR#_C
SRCC3/CR#_D

31
32

CLK_PCIE_ICH1
CLK_PCIE_ICH1#

SRCT2/SATAT
SRCC2/SATAC

28
29

CLK_PCIE_SATA1
CLK_PCIE_SATA1#

33R2J-2-GP

27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2

24
25

MCH_SSCDREFCLK1
MCH_SSCDREFCLK1#

SRCT0/DOTT_96
SRCC0/DOTC_96

20
21

PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN

64
5

FSLB/TEST_MODE
REF0/FSLC/TEST_SEL

55

NC#55
GND48
GNDPCI
GNDREF

C526

Please place R10 near U1 pin5

18
15
1

C552

1
2

C545

1
2

1
2

4 SRN0J-6-GP
3

2
1

3
4

2
1

3
4

2
1

3
4

2
1
RN34
CLK_MCH_DREFCLK1
2
CLK_MCH_DREFCLK1#
1
RN33

3
4

3
4

CLK_PCIE_NEW 28
CLK_PCIE_NEW# 28
3D3V_S0
10KR2J-3-GP
NEWCARD_CLKREQ# 28
2
10KR2J-3-GP
CLK_PCIE_MINI2 30
CLK_PCIE_MINI2# 30

SRN22-3-GP
SRN0J-6-GP

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8

SRN0J-6-GP

CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21

CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20

SRN0J-6-GP

MCH_SSCDREFCLK 8
MCH_SSCDREFCLK# 8

SRN0J-6-GP

CLK_MCH_DREFCLK 8
CLK_MCH_DREFCLK# 8

SRN0J-6-GP

SRC8
CPU_ITP

6 CPU_BSEL2
6 CPU_BSEL1
6 CPU_BSEL0

R360
R353
R386

100M
133M
200M
166M

EC165

DY

FSC

EC166

DY

EC119
SC22P50V2JN-4GP

1
R378
10KR2J-3-GP

CPU
2

1
1
0
1

FS_A

SC47P50V2JN-3GP

Overclocking of CPU and SRC not allowed

0
0
1
1

CLK_MCH_DREFCLK#

SC47P50V2JN-3GP

1
0
0
0

NEWCARD_CLKREQ#

Overclocking of CPU and SRC allowed

Output

FS_B

Output

ITP_EN

0
1

RN35

SC:08/11 Add EC165,EC166 on


CLK_MCH_DREFCLK -/+ pair .

27_SEL

FS_C

3
4

RN36

SRN0J-6-GP
1
R371
R375 1

DY
2
1

RN32

CLK_PCIE_MINI1 29
CLK_PCIE_MINI1# 29

CLK_MCH_DREFCLK

PCI2_TME

R380
10KR2J-3-GP

RN31

Main source : 71.09365.A03 ICS9LPRS365CKLFT


2nd source:71.00875.A03 RTM875N-606-LF

R373
10KR2J-3-GP

ITP_EN

RN30

CLK_PCIE_LAN 27
CLK_PCIE_LAN# 27

ICS9LPRS365BKLFT-GP

DY

CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5

RN26

CK_PWRGD/PD#

SC4D7P50V2CN-1GP

PCI2_TME

SC4D7P50V2CN-1GP

R374
10KR2J-3-GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

3D3V_S0_CK505

C540

21 CLK_14M_ICH

CPUT1_F
CPUC1_F

CLK_MCH_BCLK1
CLK_MCH_BCLK1#

SCLK
SDATA

63

R370 1
R379 1
R382 1

RN25

33R2J-2-GP

21 CK_PWRGD

25 PCLK_PCM
34 PCLK_KBC
19 CLK_PCI_ICH

4 SRN0J-6-GP
3

GND

R383

1
2

65

CLK_CPU_BCLK1
CLK_CPU_BCLK1#

X1
X2

GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND

21 CLK_48M_ICH

61
60

CPUT0
CPUC0

22
30
36
49
59
26

C550

1
2

SCD1U16V2ZY-2GP

C548
SCD1U16V2ZY-2GP

C533
SCD1U16V2ZY-2GP

C524
SCD1U16V2ZY-2GP

C525
SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP

SC1U10V3KX-3GP

DY

C227

2
1
R128 0R0603-PAD

CLK_XTAL_IN
CLK_XTAL_OUT

U24

19
27
43
52
33
56

4
16
9
46
62
23

C214
SC15P50V2JN-2-GP

X-14D31818M-37GP

3D3V_S0_CK505_IO

C231

3D3V_S0_CK505_IO

X3
CLK_XTAL_IN

3D3V_S0

C537
SCD1U16V2ZY-2GP

C529
SCD1U16V2ZY-2GP

C523
SCD1U16V2ZY-2GP

C549
SCD1U16V2ZY-2GP

C527
SCD1U16V2ZY-2GP

C219
SC10U6D3V5KX-1GP

C222
SC1U10V3KX-3GP

2
1
R127 0R0603-PAD

VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO

3D3V_S0

27_SEL strap 0:For 965GM, 1:For 965PM

2K2R2J-2-GP
FSB

27_SEL

PIN 20

PIN 21

0
1

DOT96T
SRCT0

DOT96C
SRCC0

PIN 24

PIN 25

0R0402-PAD
FSA
2K2R2J-2-GP

R385 1

2 0R0402-PAD

MCH_CLKSEL0 8

R352 1

2 0R0402-PAD

MCH_CLKSEL1 8

R359 1

2 0R0402-PAD

MCH_CLKSEL2 8

SRCT1/LCDT_100
27M_NSS

SRCT1/LCDT_100
27M_SS

965GM
965PM

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SA:0430

Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock,
so put 0 ohm serial resistor in the schematic.

Title

Clock generator ICS9LPRS365


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

-1
4

of

47

8 H_A#[3..35]
U45A 1 OF 4

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

8 H_ADSTB#1

20
20
20
20

H_STPCLK#
H_INTR
H_NMI
H_SMI#

TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28

TP14
TP16
TP6
TP12
TP4
TP10
TP5
TP20
TP11
TP18

CPU_RSVD01
CPU_RSVD02
CPU_RSVD03
CPU_RSVD04
CPU_RSVD05
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#

A6
A5
C4

A20M#
FERR#
IGNNE#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
B1

RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6

H5
F21
E1

H_DEFER#
H_DRDY#
H_DBSY#

F1

H_BR0#

IERR#
INIT#

D20
B3

H_IERR#
H_INIT#

LOCK#

H4

H_LOCK#

RESET#
RS0#
RS1#
RS2#
TRDY#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

HIT#
HITM#

G6
E4

H_HIT#
H_HITM#

BR0#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_ADS# 8
H_BNR# 8
H_BPRI# 8

1D05V_S0

D
1

H_ADS#
H_BNR#
H_BPRI#

H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
H_BR0# 8

R235
56R2J-4-GP

CONTROL

DEFER#
DRDY#
DBSY#

H1
E2
G5

H_INIT# 20
H_LOCK# 8
H_RESET# 8
H_RS#0 8
H_RS#1 8
H_RS#2 8
H_TRDY# 8

XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
C20 XDP_DBRESET#

H_HIT# 8
H_HITM# 8
TP15
TP13
TP3
TP9
TP7
TP2

TP8
TP19

THERMAL
PROCHOT#
THRMDA
THRMDC

ICH

20 H_A20M#
20 H_FERR#
20 H_IGNNE#

H_A20M#
H_FERR#
H_IGNNE#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADDR GROUP 1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

K3
H2
K2
J3
L1

ADS#
BNR#
BPRI#

XDP/ITP SIGNALS

8
8
8
8
8

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#

THERMTRIP#

HCLK

BCLK0
BCLK1

D21
A24
B25

CPU_PROCHOT
H_THERMDA
H_THERMDC

C7

H_THERMTRIP#

A22
A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

1
R236

2
56R2J-4-GP

1D05V_S0
H_THERMDA 36
H_THERMDC 36

H_THERMDA, H_THERMDC routing together,


Trace width / Spacing = 10 / 10 mil

H_THERMTRIP# 8,20,34,46

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
1D05V_S0

RESERVED

8 H_ADSTB#0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP 0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

XDP_TDI
R7
XDP_TMS

layout note:Zo =55


ohm , 0.5" MAX for
GTLREF

R5

150R2F-1-GP
39R2F-GP

KEY_NC
SKT-CPU478P-GP

XDP_TRST#
R6
XDP_TCK
R4
CPU_PROCHOT
R237

0R2J-2-GP

649R2F-GP
27D4R2F-L1-GP

CPU_PROCHOT# 41

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Meron(1/3)-AGTL+/XDP
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

of

47

8 H_D#[0..63]

VCC_CORE_S0

VCC_CORE_S0

U45B 2 OF 4

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

4 CPU_BSEL0
4 CPU_BSEL1
4 CPU_BSEL2

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_CPUSLP#
PSI#

H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8
R233
R234
R3
R2

1
1
1
1

2
2 27D4R2F-L1-GP
2 54D9R2F-L1-GP
2 27D4R2F-L1-GP
54D9R2F-L1-GP

H_DPRSTP# 8,20,41
H_DPSLP# 20
H_DPWR# 8
H_PWRGOOD 20,46
H_CPUSLP# 8
PSI# 41

SKT-CPU478P-GP

PLACE C25 close to the TEST4 PIN,


make sure TEST3,TEST4,TEST5 trace
routing is reference to GND and
away other noisy signals

B
CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

166

200

1D05V_S0

R239
1KR2F-3-GP

1D05V_S0

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA
VCCA

B26
C26

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AD6
AF5
AE5
AF4
AE3
AF3
AE2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

VCCSENSE

AF7

VCC_SENSE

VSSSENSE

AE7

VSS_SENSE

C20
SC10U6D3V5KX-1GP

1D5V_S0

CPU_VID[0..6]

41

C394

VCC_SENSE 41
VSS_SENSE 41

layout note:
place C3 near
PIN B26
C397
SC10U6D3V5KX-1GP

Length match within


25 mils . The trace
width/space/other is
20/7/25 .

SKT-CPU478P-GP

VCC_SENSE

1
R201

VSS_SENSE

1
R199

Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .

VCC_CORE_S0

100R2F-L1-GP-U
100R2F-L1-GP-U

Close to CPU pin


within 500mils

1 1

V_CPU_GTLREF

Wistron Corporation

R238

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

2KR2F-3-GP

SCD1U16V2KX-3GP

C635

Place C635 near


R238 and R239

<Core Design>

Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
toggling signal .
COMP[0,2] trace
width is 18 mils.
COMP[1,3] trace
width is 4 mils .

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

TPAD28 TP85
TPAD28 TP87

MISC

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#

H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

2 C395

DY

AD26
C23
D25
C24
AF26
AF1
A26

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP
1

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

V_CPU_GTLREF
TPAD28 TP21
TPAD28 TP23
TPAD28 TP22

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#

8 H_DSTBN#1
8 H_DSTBP#1
8 H_DINV#1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

DATA GRP1

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

DATA GRP3

8 H_DSTBN#0
8 H_DSTBP#0
8 H_DINV#0

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

DATA GRP2

U45C 3 OF 4

Title

Meron(2/3)-AGTL+/PWR
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

of

47

1
2

1
2

C349
SC10U6D3V5KX-1GP

C358
SC10U6D3V5KX-1GP

C361
SC10U6D3V5KX-1GP

C371
SC10U6D3V5KX-1GP

C374
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C376

C23
SC10U6D3V5KX-1GP

C25
SC10U6D3V5KX-1GP

C24

C35

SC10U6D3V5KX-1GP

C17

C36

SC10U6D3V5KX-1GP

C33

SC10U6D3V5KX-1GP

C34

SC10U6D3V5KX-1GP

Place these capacitors on L1


(North side ,Secondary Layer)

VCC_CORE_S0

C633

VCC_CORE_S0

C634
SC10U6D3V5KX-1GP

Mid Frequencd
Decoupling

2
C45
SCD1U16V2KX-3GP

2
C39
SCD1U16V2KX-3GP

2
C10
SCD1U16V2KX-3GP

2
C12
SCD1U16V2KX-3GP

2
C16
SCD1U16V2KX-3GP

1D05V_S0

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

C377

SC10U6D3V5KX-1GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SC10U6D3V5KX-1GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C382

SC10U6D3V5KX-1GP

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

Place these capacitors on L1


(North side ,Secondary Layer)

SC10U6D3V5KX-1GP

4 OF 4

SC10U6D3V5KX-1GP

U45D

VCC_CORE_S0

C37
SCD1U16V2KX-3GP

Place these
inside socket
cavity on L1
(North side
Secondary)

SKT-CPU478P-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Meron(3/3)-GND&Bypass
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

of

47

B9
A9

H_AVREF
H_DVREF

H_VREF

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

L7
K2
AC2
AJ10

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

M14
E13
A11
H13
B12

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

E12
D7
D8

H_RS#0
H_RS#1
H_RS#2

2
1
2

6
6
6
6

4 MCH_CLKSEL0
4 MCH_CLKSEL1
4 MCH_CLKSEL2

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

6
6
6
6

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

6
6
6
6

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

CFG[17:3] have internal pull up


CFG[19:18] have internal pull down

5
5
5
5
5

TP33
TP29
TP32
TP26
TP27
TP31
TP34
TP25
TP35

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13

TP24

CFG16

TP39
TP36
TP37

CFG18
CFG19
CFG20

H_RS#0 5
H_RS#1 5
H_RS#2 5
21 PM_BMBUSY#
6,20,41 H_DPRSTP#
14 PM_EXTTS#0
15 PM_EXTTS#1

NB:71.GM965.A0U
CRESTLINE-GP-U-NF

layout note :
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

5,20,34,46 H_THERMTRIP#
21,41 DPRSLPVR

Spec: H_SWING=0.3125 X
VTT +/- 1%

Layout Note :
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

R86

21,36 PM_PWROK
1D05V_S0

21,41 VGATE_PWRGD

Layout Note :
Place C32 within 100 mils of NB

R255
R52
PLT_RST_R#
H_SWNG

PLT_RST1# 19,23,24,28,29,30,34

100R2J-2-GP

R254

B44
C44
A35
B37
B36
B34
C34

RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

G41
L39
L36
J36
AW49
AV20
N20
G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#0
PM_EXT_TS#1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC#BJ51
NC#BK51
NC#BK50
NC#BL50
NC#BL49
NC#BL3
NC#BL2
NC#BK1
NC#BJ1
NC#E1
NC#A5
NC#C51
NC#B50
NC#A50
NC#A49
NC#BK2

SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4

BE29 DDR_CKE0_DIMMA
AY32 DDR_CKE1_DIMMA
BD39 DDR_CKE2_DIMMB
BG37 DDR_CKE3_DIMMB

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

14
14
15
15

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

BG20 DDR_CS0_DIMMA#
BK16 DDR_CS1_DIMMA#
BG16 DDR_CS2_DIMMB#
BE13 DDR_CS3_DIMMB#

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

14
14
15
15

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

BH18
BJ15
BJ14
BE16

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP_VOH
SM_RCOMP_VOL

BK31
BL31

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_RCOMP
SM_RCOMP#

BL15
BK14

SM_RCOMP
SM_RCOMP#

SM_VREF#AR49
SM_VREF#AW4

AR49
AW4

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

3D3V_S0

Layout Note :
Place C33 near
pin B3 of NB

RN18

10 TV_DCONSEL0
10 TV_DCONSEL1

PM_EXTTS#0
PM_EXTTS#1
TV_DCONSEL0
TV_DCONSEL1

1
2
3
4

8
7
6
5

B42
C42
H48
H47

M_ODT0
M_ODT1
M_ODT2
M_ODT3

14
14
15
15

14
14
15
15
1D8V_S3

1
R264 1
R261

2
2 20R2F-GP
20R2F-GP
DDR_VREF_S3

DDR_VREF_S3

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

PEG_CLK
PEG_CLK#

K44 CLK_MCH_3GPLL
K45 CLK_MCH_3GPLL#

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AN47
AJ38
AN42
AN46

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AM47
AJ39
AN41
AN45

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AJ46
AJ41
AM40
AM44

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AJ47
AJ42
AM39
AM43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DFGT_VID0
DFGT_VID1
DFGT_VID2
DFGT_VID3
DFGT_VR_EN

CLK_MCH_DREFCLK 4
CLK_MCH_DREFCLK# 4
MCH_SSCDREFCLK 4
MCH_SSCDREFCLK# 4
CLK_MCH_3GPLL 4
CLK_MCH_3GPLL# 4

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

21
21
21
21

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

21
21
21
21

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

21
21
21
21

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

21
21
21
21

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VR_EN

E35
A39
C38
B39
E36

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AM49
AK50
AT43
AN49
AM50

PM_POK_R

H35
K36
G39
G40

SDVO_CTRLCLK 23
SDVO_CTRLDATA 23
CLKREQ#_B 4
MCH_ICH_SYNC#
MCH_ICH_SYNC#

TP38
TP94
TP92
TP93
TP40

1D25V_S0

R84
1KR2F-3-GP

CL_CLK0 21
CL_DATA0 21
CL_RST# 21

CL_VREF

R85
392R2F-GP

C182
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLKREQ#
ICH_SYNC#

C415
SCD1U16V2ZY-2GP

100R2F-L1-GP-U

R250
24D9R2F-L-GP
2

SCD1U16V2ZY-2GP

1
2

C426

PM_POK_R

0R2J-2-GP

221R2F-2-GP
2
1

1
2
1

R262
2KR2F-3-GP

H_RCOMP

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST_R#
H_THERMTRIP#
DPRSLPVR

RSVD#BH39
RSVD#AW20
RSVD#BK20

NC

H_VREF

2 0R2J-2-GP

R87

1D05V_S0

R263
1KR2F-3-GP

DY

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

BH39
AW20
BK20

14
14
15
15

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

CLK

2
1

C442
SCD01U25V2KX-3GP

1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AW30 M_CLK_DDR#0
BA23 M_CLK_DDR#1
AW25 M_CLK_DDR#2
AW23 M_CLK_DDR#3

DDR MUXING

C437
SCD01U25V2KX-3GP

1
2
1

H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5
H_BNR# 5
H_BPRI# 5
H_BR0# 5
H_DEFER# 5
H_DBSY# 5
CLK_MCH_BCLK 4
CLK_MCH_BCLK# 4
H_DPWR# 6
H_DRDY# 5
H_HIT# 5
H_HITM# 5
H_LOCK# 5
H_TRDY# 5

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24

AV29
BB23
BA25
AV23

SM_CK#0
SM_CK#1
SM_CK#3
SM_CK#4

DMI

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

C444
SC2D2U6D3V3KX-GP

R273
1KR2F-3-GP

PM

M7
K3
AD2
AH11

SM_CK0
SM_CK1
SM_CK3
SM_CK4

H_CPURST#
H_CPUSLP#

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

RSVD#P36
RSVD#P37
RSVD#R35
RSVD#N35
RSVD#AR12
RSVD#AR13
RSVD#AM12
RSVD#AN13
RSVD#J12
RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

B6
E5

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

R268
1KR2F-3-GP

R272
3K01R2F-3-GP

SM_RCOMP_VOL

FOR Calero: 80.6 ohm


Crestline: 20 ohm

U50B 2 OF 10

1D8V_S3

H_RESET#
H_CPUSLP#

K5
L2
AD13
AE13

SM_RCOMP_VOH

TEST1
TEST2

A37 TEST1_GMCH
R32 TEST2_GMCH1
2
R65
20KR2J-L2-GP

21

1 R64
2
0R0402-PAD

H_SCOMP
H_SCOMP#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

C435
SC2D2U6D3V3KX-GP

H_SWING
H_RCOMP

W1
W2

H_ADS#
G12
H_ADSTB#0
H17
H_ADSTB#1
G20
H_BNR#
C8
H_BPRI#
E8
H_BR0#
F12
H_DEFER#
D6
H_DBSY#
C10
CLK_MCH_BCLK
AM5
CLK_MCH_BCLK#
AM7
H_DPWR#
H8
H_DRDY#
K7
H_HIT#
E4
H_HITM#
C6
H_LOCK#
G10
H_TRDY#
B7

H_A#[3..35] 5

SCD1U16V2KX-3GP
2

B3
C2

H_SCOMP
H_SCOMP#

GRAPHICS VID

5 H_RESET#
6 H_CPUSLP#

H_SWNG
H_RCOMP

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

ME

54D9R2F-L1-GP

R248 R249

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

CFG

54D9R2F-L1-GP
2

1D05V_S0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

MISC

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

HOST

E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13

RSVD

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U50A 1 OF 10

6 H_D#[0..63]

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SRN10KJ-6-GP
CLKREQ#_B
R69

2
10KR2J-3-GP

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size
Document Number
Custom

Date: Wednesday, September 12, 2007

Sheet

Rev

-1

DS2-Intel
8

of

47

DDR_A_D[0..63]

14

DDR_A_BS[0..2]

14

DDR_A_DM[0..7]

DDR_B_D[0..63]

15

DDR_B_BS[0..2]

15

DDR_B_DM[0..7]

15

14

DDR_A_DQS[0..7]

DDR_B_DQS[0..7]
DDR_A_DQS#[0..7]

BB19
BK19
BF29

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_CAS#

BL17

DDR_A_CAS#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

SA_RAS#
SA_RCVEN#

BE18
AY20

DDR_A_RAS#
SA_RCVEN#

SA_WE#

BA19

DDR_A_WE#

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

15

U50E 5 OF 10

SA_BS0
SA_BS1
SA_BS2

DDR_A_CAS# 14

DDR_A_RAS# 14
TP30
DDR_A_WE# 14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

DDR SYSTEM MEMORY B

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYSTEM MEMORRY A

U50D 4 OF 10

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

15

14
DDR_B_MA[0..14]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

15

14
DDR_B_DQS#[0..7]

DDR_A_MA[0..14]

14

SB_BS0
SB_BS1
SB_BS2

AY17
BG18
BG36

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

SB_CAS#

BE17

DDR_B_CAS#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

SB_RAS#
SB_RCVEN#

AV16
AY18

DDR_B_RAS#
SB_RCVEN#

SB_WE#

BC17

DDR_B_WE#

DDR_B_CAS# 15

DDR_B_RAS# 15
TP28
DDR_B_WE# 15

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRESTLINE(2/6)-DDR2 A/B CH

Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

of

47

For Crestline : 2.4 Kohm


For Calero : 1.5Kohm

R74

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

18 VGA_TXAOUT018 VGA_TXAOUT118 VGA_TXAOUT2-

G51
E51
F49
C48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

18 VGA_TXAOUT0+
18 VGA_TXAOUT1+
18 VGA_TXAOUT2+

G50
E50
F48
D47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

18 VGA_TXBOUT018 VGA_TXBOUT118 VGA_TXBOUT2-

G44
B47
B45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2

18 VGA_TXBOUT0+
18 VGA_TXBOUT1+
18 VGA_TXBOUT2+

E44
A47
A45

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2

DY

18 LDDC_CLK
18 LDDC_DATA
18 LCDVDD_EN

Chang R68 from


64.24015.6DL to 64.33015.6DL
18
18
18
18

SRN10KJ-5-GP

2
3K3R2F-2-GP

LVDS_IBG
TP41

VGA_TXACLKVGA_TXACLK+
VGA_TXBCLKVGA_TXBCLK+

1
2

R53
150R2F-1-GP

1
R55
150R2F-1-GP

R54
150R2F-1-GP

TV_DCONSEL0
TV_DCONSEL1

E27
G27
K27

TVA_DAC
TVB_DAC
TVC_DAC

F27
J27
L27

TVA_RTN
TVB_RTN
TVC_RTN

M35
P33

TV_DCONSEL0
TV_DCONSEL1

TV

35 M_COMP
35 M_LUMA
35 M_CRMA

8 TV_DCONSEL0
8 TV_DCONSEL1

1
2

R61
150R2F-1-GP

R57
150R2F-1-GP

1
17
17
17
17

GMCH_DDCCLK
GMCH_DDCDATA
GMCH_VSYNC
GMCH_HSYNC

RN54

1
2

4
3

SRN33J-5-GP-U
1
R60

CRT_VSYNC
CRT_HSYNC

H32
G32
K29
J29
F29
E29

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

K33
G35
E33
C32
F33

CRT_DDC_CLK
CRT_DDC_DATA
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC

VGA

R56
150R2F-1-GP
2
1

M_BLUE
M_GREEN
M_RED

17 M_BLUE
17 M_GREEN
17 M_RED

PEG_COMPI
PEG_COMPO

M_COMP
M_LUMA
M_CRMA

2
1

CRTIREF
2
1K3R2F-1-GP
SA:0428

FOR Calero: 255 ohm


Crestline: 1.3k ohm

PCI_EXPRESS GRAPHICS

L41
L43
N41
N40
D46
C45
D44
E42

RN56

3
4

LVDS

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

18 LBKLT_CTL
34 GMCH_BL_ON
3D3V_S0

D-1:0908

N43
M43

PEGCOMP

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

NB_SDVOB_RNB_SDVOB_GNB_SDVOB_BNB_SDVOB_C-

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

NB_SDVOB_R+
NB_SDVOB_G+
NB_SDVOB_B+
NB_SDVOB_C+

CRESTLINE-GP-U-NF

2
24D9R2F-L-GP

U50C 3 OF 10

J40
H39
E39
E40
C37
D35
K40

R68

1D05V_S0

PEGCOMP trace
width and spacing
is 20/25 mils.

SDVOB_INT- 23

Strap Pin Table


010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

CFG[2:0] FSB Freq select


CFG5 (DMI select)

0 = DMI x 2
1 = DMI x 4

CFG6

Reserved
0 = Reserved
1 = Mobile CPU

CFG7 (CPU Strap)

0 = Normal mode
1 = Low Power mode

CFG8 (Low power PCIE)


CFG9
(PCIE Graphics Lane Reversal)

0 = Reverse Lane
1 = Normal Operation

SDVOB_INT+ 23

CFG[11:10]

Reserved
00
01
10
11

CFG[13:12] (XOR/ALLZ)
CFG[15:14]

0 = Disable
1 = Enable *

CFG[18:17]

0 = No SDVO Device Present *


1 = SDVO Device Present
0 = Normal Operation
(Lane number in Order)
1 = Reverse lane

CFG19(DMI Lane Reversal)

SDVOB_R- 23

1 SCD1U10V2KX-4GP

SDVOB_G- 23

NB_SDVOB_B- C474 2

1 SCD1U10V2KX-4GP

SDVOB_B- 23

NB_SDVOB_C- C480 2

1 SCD1U10V2KX-4GP

SDVOB_C- 23

NB_SDVOB_R+ C470 2

1 SCD1U10V2KX-4GP

SDVOB_R+ 23

NB_SDVOB_G+ C468 2

1 SCD1U10V2KX-4GP

SDVOB_G+ 23

NB_SDVOB_B+ C478 2

1 SCD1U10V2KX-4GP

SDVOB_B+ 23

NB_SDVOB_C+ C484 2

1 SCD1U10V2KX-4GP

SDVOB_C+ 23

0 = Only PCIE or SDVO is operational *


1 = PCIE/SDVO are operating simu.

CFG20(PCIE/SDVO consurrent)

1 SCD1U10V2KX-4GP

Reversed

SDVO_CTRLDATA

NB_SDVOB_G- C464 2

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation (Default)*

Reserved

CFG16 (FSB Dynamic ODT)

NB_SDVOB_R- C469 2

=
=
=
=

NB:71.GM965.A0U

3D3V_S0

RN55

3
4

2
1

LDDC_CLK
LDDC_DATA

SRN10KJ-5-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

CRESTLINE(3/6)-VGA/LVDS/TV
Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

10

of

47

5
3D3V_S0_DAC_BG

3D3V_S0
R58

1
3D3V_S0
1D25V_S0_DPLLB

1
2

1
2

1
2

1
2

1
2

2
1
2

1
2

1
2

1
2

2
D12

1D05V_S0_D

3D3V_S0

1D25V_S0

C411 BLM18AG121SN-1GP

C407

Place
C95,C99,C112
near Pin
AD51,W50,W51

C179

C180

3D3V_S0_HV

R70

3
BAS16-1-GP

R71 1
0R0402-PAD

10R2J-2-GP

1
2

1
2

SC1U10V3KX-3GP

1
2
1
2

1
2
1

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SCD47U16V3ZY-3GP
SC10U6D3V5KX-1GP
2
1
2
1

2
1
2

1D05V_S0

R82
2
0R0603-PAD
C164
SC1U10V3KX-3GP

1D8V_S3

1 R79
2
0R0603-PAD
C162

1D8V_S3

VCCA_TVDAC

3D3V_S0

C144
SCD1U16V2KX-3GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

L19

1
2
BLM18PG181SN-3GP

L85 2nd source


68.00214.101/68.00217.141

C169

C447
SC10U6D3V5KX-1GP

Title

40mil

C172

C422

L17

1D8V_S0_TXLVDS

1
2

Place C108,C109
Pin N28

C105near

SC10U6D3V5KX-1GP

SC1U10V3KX-3GP

1
2
2

CRESTLINE-GP-U-NF

1D8V_S0_LVDS

VCCA_TVDAC

C114

SM CK
PEG

TV

NB:71.GM965.A0U

C406

Place C96
near Pin
AN2

20mil

C404

C60

1D25V_S0_MPLL

VCCD_LVDS
VCCD_LVDS

1D25V_S0

C492

J41
H42

2
L-10UH-11-GP

1D05V_S0

VCCD_PEG_PLL

1D8V_S0_LVDS

A7
F2
AH1

VTTLF1
VTTLF2
VTTLF3

C490

1D25V_S0_PEGPLL

VTTLF
VTTLF
VTTLF

AH50
AH51

SCD47U16V3ZY-3GP

VCCD_HPLL

U48

1D05V_S0

AN2

VCC_RXR_DMI
VCC_RXR_DMI

AD51
W50
W51
V49
V50

SCD47U16V3ZY-3GP
2

1D25V_S0

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

Place C82,C83
near Pin
M32,L29

1D25V_S0

1
L25

3D3V_S0_HV

VCCD_QDAC

1D25V_S0_DPLLA

C139

DMI

N28

HV

A CK

1D5V_S0

C40
B40

C153

C96

AXF

A PEG
A SM

1
2

VCCD_CRT
VCCD_TVDAC

TV/CRT

1
2

SC1U10V3KX-3GP

M32
L29

A43

1D8V_S0_TXLVDS

VCCA_TVA_DAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_TVC_DAC

VCC_HV
VCC_HV

1D8V_S3

LVDS

2
SCD22U10V3KX-2GP
SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP

2
1
2

1
2

1
2

SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

1
2

SC10U6D3V5KX-1GP
2
1

1
2
1

VCC_TX_LVDS

VCCA_SM_CK
VCCA_SM_CK

1D5V_S0

1D5V_S0

2
1

BK24
BK23
BJ24
BJ23

C125

SCD1U16V2ZY-2GP

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

C119

SC10U6D3V5KX-1GP

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM_NCTF
VCCA_SM_NCTF

1D25V_S0

1D25V_S0

BLM18PG121SN-1GP

SC10U6D3V5KX-1GP

AJ50

1D25V_S0

SC10U6D3V5KX-1GP

3D3V_S0_TVDACC

VCC_DMI

SC10U6D3V5KX-1GP

3D3V_S0_TVDACB

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD022U16V2KX-3GP

3D3V_S0_TVDACA

B23
B21
A21

C176

SCD1U16V2ZY-2GP

AT22
AT21
AT19
AT18
AT17
AR17
AR16

C25
B25
C27
B27
B28
A28

VCC_AXF
VCC_AXF
VCC_AXF

DY
C181

SCD1U16V2ZY-2GP

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM

SCD1U16V2ZY-2GP

VCCA_TVDAC

3D3V_S0_TVDACB
R269 1
2
0R0603-PAD
C439

AW18
AV19
AU19
AU18
AU17

BC29
BB29

C104

SCD022U16V2KX-3GP

SCD1U16V2ZY-2GP
C434

SCD022U16V2KX-3GP

R267 1
2
0R0603-PAD
C433

C118

C167

SCD1U16V2ZY-2GP

VCCA_TVDAC
R271 1
2
C445 0R0603-PAD

C94

AR29

C102

1D5V_S0

L4

SC10U6D3V5KX-1GP

C101

SCD1U16V2ZY-2GP

SCD022U16V2KX-3GP

C115

VCC_AXD_NCTF

1D25V_S0_PEGPLL

C110
SC10U6D3V5KX-1GP

C126

SCD1U16V2ZY-2GP

VCCA_PEG_PLL

C117

Place C75,C76 near


Pin
BK24,BK23,BJ24,BJ23

1D25V_S0

SCD022U16V2KX-3GP

U51

1D25V_S0

SC1KP50V2KX-1GP

C82

3D3V_S0_TVDACC

C440

VSSA_PEG_BG

AT23
AU28
AU24
AT29
AT25
AT30

SCD1U16V2ZY-2GP

C89

-1:0909

1D25V_S0

VCCA_PEG_BG

K49

VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD

C399 BLM18AG121SN-1GP

SCD1U16V2ZY-2GP

20mil
SCD1U16V2ZY-2GP

1D25V_S0

3D3V_S0_TVDACA

K50

POWER

SC10U6D3V5KX-1GP

C171
SCD1U16V2ZY-2GP
1D25V_S0_PEGPLL

C446

VSSA_LVDS

400uA

VCCA_LVDS

B41

SC1KP50V2KX-1GP

VCCA_MPLL

A41

A LVDS

C157
3D3V_S0

VCCA_HPLL

1
C396

1
2

SC22U6D3V5MX-2GP

1D8V_S0_TXLVDS

AL2
AM2

C107
SC1U16V3ZY-GP

L16

SCD1U16V2ZY-2GP

DY

150mA

C99

1D8V_S3
1D25V_S0_HPLL

C76

SC10U6D3V5KX-1GP

1D25V_S0_HPLL
1D25V_S0_MPLL

TC21

VTTLF

VCCA_DPLLB

AXD

VCCA_DPLLA

H49

PLL

B49

1D25V_S0_DPLLB

C170

SCD1U16V2ZY-2GP

1D25V_S0_DPLLA

C137

C168

C493

SC10U6D3V5KX-1GP

3D3V_S0

C75

C83

VSSA_DAC_BG

Place TC21 near R58 and R59

C106

SCD47U16V3ZY-3GP
2

VCCA_DAC_BG

B32

VTT

3D3V_S0_DAC_BG

CRT

A30

0R3-0-U-GP
C127

SCD1U16V2ZY-2GP

VCCA_CRT_DAC
VCCA_CRT_DAC

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

Place C69,C70
near Pin
B23,B21,A21

1D25V_S0
SC10U6D3V5KX-1GP

3D3V_S0_DAC_CRT

A33
B33

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

2
L-10UH-11-GP

SCD1U16V2ZY-2GP

VCC_SYNC

SCD1U16V2ZY-2GP

R59

J32

U50H 8 OF 10

C124
SCD1U16V2ZY-2GP

3D3V_S0

1
L26
SC10U6D3V5KX-1GP

3D3V_S0_DAC_CRT

1D05V_S0

SB:07/01 Change R58,R59 from


0602 close pad to
63.00000.00L

C121

SCD1U16V2ZY-2GP

1D25V_S0

0R3-0-U-GP

Size
A3

CRESTLINE(4/6)-PWR
Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

11

of

47

4
1D05V_S0

LIB C
1D05V_S0

U50G 7 OF 10

VSS NCTF

VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF
VCC_AXM_NCTF

VSS SCB

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

A3
B2
C1
BL1
BL51
A51

VSS AXM

POWER

VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

NCTF_U56-1

TP89

NCTF_U56-2
NCTF_U56-4
NCTF_U56-3

TP88
TP96
TP95

1D05V_S0

2
1
2

1
2

1
2

VSS AXM NCTF

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

VCC NCTF

1
2

1
2

1
2

1
2

1
2

1
2

ST220U2VBM-3GP

1
2

SCD22U10V2KX-1GP

1
2

SCD1U16V2ZY-2GP

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

C155
1

C143
1

C93

C62

C71

C66

C156

SC1U10V3KX-3GP

SC1U10V3KX-3GP
2

2
SCD47U16V3ZY-3GP

SCD22U10V2KX-1GP
2

SCD22U10V2KX-1GP
2

2
SCD1U16V2ZY-2GP

NB:71.GM965.A0U

<Core Design>
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

VCC GFX NCTF


VCC SM LF

1
2

SC1U10V3KX-3GP

VCC SM

SCD01U16V2KX-3GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP

1
2

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP

C141

C140

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

SCD1U16V2ZY-2GP

VCC GFX

1
2

1
2

1
2

ST220U2VBM-3GP

1
2

1
2

C92
SC10U6D3V5KX-1GP

C116

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

CRESTLINE-GP-U-NF
SCD22U10V2KX-1GP

CRESTLINE-GP-U-NF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

C158

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

SCD22U10V2KX-1GP

SC10U6D3V5KX-1GP

C111

SCD1U16V2ZY-2GP

C87

R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

1D05V_S0

C160

C129

C100

C134

SCD22U10V2KX-1GP

DY
SCD22U10V2KX-1GP

1D05V_S0

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

C79

C130

C131

C133

C142

C132

DY

AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30

C120

1D05V_S0

C128

POWER
1D8V_S3

C90

TC15

C402

VCC

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

C403

R30

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

C136

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC CORE

-1:0909
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

U50F 6 OF 10

TC17

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRESTLINE(5/6)-PWR/GND
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

12

of

47

U50I

A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 10

VSS

U50J10 OF 10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

VSS

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

CRESTLINE(6/6)-PWR/GND

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

13

of

47

DM2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1
2

C421
SCD1U16V2ZY-2GP

C85
SCD1U16V2ZY-2GP

C427
SCD1U16V2ZY-2GP

C438
SCD1U16V2ZY-2GP

C430
SCD1U16V2ZY-2GP

C423
SCD1U16V2ZY-2GP

C63
SCD1U16V2ZY-2GP

C73
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

C95

C112

DDR_VREF_S0

change to 8P4R
Layout Note:
Place these resistors
closely DM1,all
trace length Max=1.5"

DDR_VREF_S0

1
2
3
4

DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

8
7
6
5

1
2
3
4

8
7
6
5

SRN56J-5-GP

SRN56J-5-GP

RN11

RN50

1
2
3
4

DDR_A_CAS#
DDR_A_MA13
M_ODT1
DDR_CS1_DIMMA#

1
2
3
4

8
7
6
5

1
2
3
4

8
7
6
5

SRN56J-5-GP

SRN56J-5-GP

RN9

RN48

8
7
6
5

1
2
3
4

SRN56J-5-GP

8
7
6
5

DDR_A_MA12
DDR_A_BS2
DDR_CKE0_DIMMA

8 DDR_CS0_DIMMA#
8 DDR_CS1_DIMMA#
8 DDR_CKE0_DIMMA
8 DDR_CKE1_DIMMA
9 DDR_A_RAS#
9 DDR_A_CAS#
9 DDR_A_WE#

DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_MA6

4,15,21 ICH_SMBCLK
4,15,21 ICH_SMBDATA
M_ODT0
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_BS1

DDR_VREF_S3

8
7
6
5

CS0#
CS1#
CKE0
CKE1
RAS#
CAS#
WE#

ICH_SMBCLK
ICH_SMBDATA

197
195

SCL
SDA

114
119

ODT0
ODT1

C184

DDR_A_MA7
DDR_A_MA11
DDR_A_MA14
DDR_CKE1_DIMMA

SCD1U16V2ZY-2GP

C185

201

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

SA0
SA1

198
200

VDD_SPD

199

SA0
SA1

1
1

R37
R39

110
115
79
80
108
113
109

30
32
164
166

SC10P50V2JN-4GP

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

CK0
CK0#
CK1
CK1#

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

50
69
83
120
163

10
26
52
67
130
147
170
185

put near connector


M_CLK_DDR1
M_CLK_DDR#1

C388

M_CLK_DDR0 8
M_CLK_DDR#0 8
M_CLK_DDR1 8
M_CLK_DDR#1 8

2 0R0402-PAD
2 0R0402-PAD

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SB:0707 For EMI request

C477

C391

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

DDR_VREF_S3

SRN56J-5-GP

1
2
3
4

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M_ODT0
M_ODT1

8 M_ODT0
8 M_ODT1

RN52

BA0
BA1

8 PM_EXTTS#0

DDR_A_MA9
DDR_A_MA5
DDR_A_MA8
DDR_A_MA3

RN15

107
106

SA:0428
3D3V_S0

1D8V_S3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VREF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

GND

GND

202

C41
SCD1U16V2ZY-2GP

C46
SC2D2U6D3V3KX-GP

DY
C

SKT-SODIMM200-38GP

RN13

DDR_A_BS0
DDR_A_BS1

C476

SC10P50V2JN-4GP

1
2

C122
SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

C69

C98
SCD1U16V2ZY-2GP

C81
SCD1U16V2ZY-2GP

C84
SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

C77

C123
SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

C91

1D8V_S3

DDR_A_BS2

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SC10P50V2JN-4GP
2

9 DDR_A_BS[0..2]

Layout Note:
Place near DM1

13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186

9 DDR_A_MA[0..14]
D

M_CLK_DDR0
M_CLK_DDR#0

MH2

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

SC10P50V2JN-4GP
2

9 DDR_A_DQS[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2

9 DDR_A_DM[0..7]

MH2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

9 DDR_A_D[0..63]

9 DDR_A_DQS#[0..7]

MH1

MH1

SC2D2U16V5ZY-2GP
A

Main Source:62.10017.E31
2nd Source: 62.10017.A41

SRN56J-5-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDRII-SODIMM SLOT1
Size
Custom
Date:
5

Document Number

Rev

DS2-Intel

Wednesday, September 12, 2007

Sheet
1

-1
14

of

47

M_CLK_DDR2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
C

1
2

C74
SCD1U16V2ZY-2GP

C429
SCD1U16V2ZY-2GP

C425
SCD1U16V2ZY-2GP

C97
SCD1U16V2ZY-2GP

C443
SCD1U16V2ZY-2GP

C441
SCD1U16V2ZY-2GP

C419
SCD1U16V2ZY-2GP

C113
SCD1U16V2ZY-2GP

C64
SCD1U16V2ZY-2GP

DY

C86
SCD1U16V2ZY-2GP

DDR_VREF_S0

Layout Note:
Place these resistors
closely DM2,all
trace length Max=1.5"

DDR_VREF_S0
RN49

M_ODT3
DDR_CS3_DIMMB#
DDR_B_CAS#
DDR_B_WE#

1
2
3
4

SRN56J-5-GP

8
7
6
5

DDR_B_MA14
DDR_B_MA6
DDR_B_MA2
DDR_B_MA4

SRN56J-5-GP

RN12

RN51

8
7
6
5

1
2
3
4

SRN56J-5-GP

8
7
6
5

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5

SRN56J-5-GP

RN47

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

11
29
49
68
129
146
167
186

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

1
2

4
3

DDR_B_MA13
M_ODT2

DDR_VREF_S3

8 M_ODT2
8 M_ODT3

M_ODT2
M_ODT3

114
119

OTD0
OTD1

1
2

DDR_VREF_S3

SRN56J-4-GP

SRN56J-5-GP
C499

RN16

1
2
3
4

8
7
6
5

SCD1U16V2ZY-2GP

DDR_CKE3_DIMMB
DDR_B_MA7
DDR_B_MA11

C503
SC2D2U16V5ZY-2GP

M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 8
M_CLK_DDR#2 8

CK1
CK1#

164
166

M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 8
M_CLK_DDR#3 8

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SDA
SCL

195
197

ICH_SMBDATA
ICH_SMBCLK

VDDSPD

199

SA0
SA1

198
200

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

30
32

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

CK0
CK0#

SC10P50V2JN-4GP

BA0
BA1

CKE0
CKE1

DDR_CKE2_DIMMB 8
DDR_CKE3_DIMMB 8

put near connector

M_CLK_DDR3
M_CLK_DDR#3

SB:0707 For EMI request


C50

ICH_SMBDATA 4,14,21
ICH_SMBCLK 4,14,21

107
106

C51

3D3V_S0
R36
R38

1
1

2 0R0402-PAD
2 10KR2J-3-GP
SA:0428

C44
SCD1U16V2ZY-2GP

3D3V_S0
PM_EXTTS#1 8

C38
SC2D2U6D3V3KX-GP

DY

1D8V_S3

VREF
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

202

GND

GND

201

MH1

MH1

MH2

MH2

RN10

8
7
6
5

1
2
3
4

1
2
3
4

DDR_CS2_DIMMB#
DDR_B_BS1
DDR_B_RAS#
DDR_B_MA0

8
7
6
5

1
2
3
4

DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

RN14

DDR_B_BS0
DDR_B_BS1

DDR_CS2_DIMMB# 8
DDR_CS3_DIMMB# 8

DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

SC10P50V2JN-4GP

1
2

C108
SC10U6D3V5KX-1GP

C72
SCD1U16V2ZY-2GP

C78
SCD1U16V2ZY-2GP

C103
SCD1U16V2ZY-2GP

C70
SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

C67

C109

C88
SC2D2U16V5ZY-2GP

1D8V_S3

DDR_B_BS2

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

79
80

C174

9 DDR_B_BS[0..2]

110
115

Layout Note:
Place near DM2

CS0#
CS1#

C175

DDR_B_RAS# 9
DDR_B_WE# 9
DDR_B_CAS# 9

SC10P50V2JN-4GP
2

9 DDR_B_MA[0..14]
D

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

9 DDR_B_DQS[0..7]

108
109
113

9 DDR_B_DM[0..7]

RAS#
WE#
CAS#

9 DDR_B_D[0..63]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

9 DDR_B_DQS#[0..7]

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

SC10P50V2JN-4GP
2
1

M_CLK_DDR#2

DM1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

SKT-SODIMM200-37GP

SRN56J-5-GP

Main Source:62.10017.E21
2nd Source: 62.10017.A51
RN53

1
2

4
3

Wistron Corporation

DDR_CKE2_DIMMB
DDR_B_BS2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

SRN56J-4-GP
Title

DDRII-SODIMM SLOT2
Size
Custom
Date:
5

Document Number

Rev

DS2-Intel

Wednesday, September 12, 2007

Sheet
1

-1
15

of

47

HDMI I/F & CONNECTOR

3D3V_S0
5V_S0

1
HDMI_TXD#1_C

R278 1
23 HDMI_TXD#0

2 0R0603-PAD

HDMI_TXD#0

HDMI_TXD#0_C

R444

RN19

DY

0R2J-2-GP

SRN2K2J-1-GP

DY
4
3

2 0R0603-PAD

HDMI_TXD#1

SB:06/23 Add
R444,R445(63.R0034.1DL)

DY
R73
10KR2J-3-GP

R288 1
23 HDMI_TXD#1

1
2

4
L21
ACM2012H-900-GP

DY

DY

HDMI_SCLK

23 HDMI_TXD1

HDMI_TXD1
R292

HDMI_TXD1_C

23 HDMI_TXD0

HDMI_SDATA_C

R285

4
2N7002SPT

HDMI_TXD0

0R0603-PAD

HDMI_SDATA

connect to 5V_S0
directly.

R445

1
R299

HDMI_TXD#1_C
HDMI_TXD1_C

+5V_POWER

9
7

TMDS_DATA0TMDS_DATA0+

6
4

TMDS_DATA1TMDS_DATA1+

SB:06/22 Change R66,R67 from


63.R0034.1DL to ZZ.R0402.ZZZ

18

SDA

16

HDMI_SDATA_C

SCL

15

HDMI_SCLK_C

CEC

13

HDMI_CEC

R67

R66
TP91 TPAD28

HDMI_TXD#2_C
HDMI_TXD2_C

3
1

TMDS_DATA2TMDS_DATA2+

DY

DY

14

TP90 TPAD28

12
10

RESERVED#14

HDMI_CNC

HDMI_TX#C_C
HDMI_TXC_C

TMDS_CLOCKTMDS_CLOCK+

HOT_PLUG_DETECT

19

HDMI_DP_C2

8
5
2
11

DDC/CEC_GROUNG
GND
TMDS_DATA0_SHIELD
GND
TMDS_DATA1_SHIELD
GND
TMDS_DATA2_SHIELD
GND
TMDS_CLOCK_SHIELD

17
20
21
22
23

L20
ACM2012H-900-GP

23 HDMI_TXC

HDMI_TXC

HDMI_TXC_C

1
R277

0R0603-PAD

0R0603-PAD

SB:06/23 Add
R444,R445(63.R0034.1DL)

RN17
SRN1KJ-7-GP

L24
ACM2012H-900-GP

HDMI_TXD2_C

HDMI_TXD#0_C
HDMI_TXD0_C

HDMI_TX#C_C

DY

HDMI_SDATA 23
HDMI_SCLK 23

HDMI_HDP
2
1KR2J-1-GP

HDMI_HDP 23

R63

HDMI_SDATA
0R0402-PAD
HDMI_SCLK
0R0402-PAD

R62
15K4R2F-GP

HDMI_TXD2

2 0R0603-PAD

HDMI_TX#C

23 HDMI_TXD2

R276 1
23 HDMI_TX#C

HDMI_TXD#2_C

0R2J-2-GP

3
4

2 0R0603-PAD

R295 1
HDMI_TXD#2

CH751H-40PT
5V_S0

HDMI1

23 HDMI_TXD#2

Add D31 CH751H for HDMI


SM bus clock pull up to 5V_S0.

D11

HDMI CONN

0R0603-PAD

CH751H-40PT SB:06/21

5V_HDMI_D 1

DY SB:06/21 HDMI1 pin18

HDMI_TXD0_C

HDMI_SCLK_C

2
1

4
L23
ACM2012H-900-GP

5V_HDMI_C

5V_S0

D31

U16

-1:0909

SKT-USB-169-GP
62.10027.661

TV OUT CONN (Optional) Move to Right I/O Board


2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HDMI/TV Connector
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

-1
Sheet
E

16

of

47

CRT I/F & CONNECTOR


4

5V_CRT_S0

5V_S0

SB:0630 Change CRT1 from


20.20334.015 to 20.20735.015.

Layout Note:
Place these resistors

D4
L3

2 BLM18BB470SN1-GP

CRT_R

C18
SCD01U16V2KX-3GP

CH751H-40PT

CRT1

close to the CRT-out


connector

10 M_RED

5V_CRT_S0

17
2 BLM18BB470SN1-GP

CRT_G

6
11

1
2

L2

10 M_GREEN

MH1
CRT_R

RN3

JVGA_HS

13

4
3

C14

SRN2K2J-1-GP

12

CRT_G

CRT_B

C26

1
2

1
2

C29

SC8P250V2CC-GP

150R2F-1-GP

C15

CRT_B
SC8P250V2CC-GP

150R2F-1-GP

C27

SC8P250V2CC-GP

150R2F-1-GP

C30

SC8P250V2CC-GP

R19

SC8P250V2CC-GP

R23

SC8P250V2CC-GP

R32

2 BLM18BB470SN1-GP

L1

10 M_BLUE

9
14

JVGA_VS

4
10
15
5

MH2
16

DDC_DATA_CON

VIDEO-15-84-GP-U
20.20735.015

5V_S0

CRT_R

TSAHCT125PW-GP

U9A

1
2

VSYNC_5

DY
4
3

JVGA_HS
JVGA_VS

2
CRT_G

DY
4
3

BAV99PT-GP-U

3D3V_S0

RN2

BAV99PT-GP-U
D5

SRN33J-5-GP-U

TSAHCT125PW-GP

3D3V_S0

5V_S0

RN6

10 GMCH_VSYNC

D7
HSYNC_5

6
U9B

14

10 GMCH_HSYNC

C359

DY

C47
SCD1U16V2ZY-2GP

14

Hsync & Vsync level shift

C334
SC22P50V2JN-4GP

DY

C347

1
1

1
C354
SC33P50V2JN-3GP

SC33P50V2JN-3GP
2

DDC_CLK_CON

SC22P50V2JN-4GP
2
2

SB:07/09 ChangeC14,C15,C26,C27,C9,C30
from 78.3R374.1FL to 78.8R274.1FL

1
2

D3

SRN2K2J-1-GP
CRT_B

DY

U3

BAV99PT-GP-U
10 GMCH_DDCDATA

DDC_CLK_CON

DDC_DATA_CON

GMCH_DDCCLK

10

5V @ ext. CRT side

<Core Design>

2N7002SPT

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT Connector
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

-1
Sheet
E

17

of

47

1
2
1
2

SC:08/13 Add EC167,EC168(78.10034.1FL),


R460,R461(63.R0034.1DL) place cross LVDS CLK
A,Bpair. Default is DY.This is for RF request.

1
2

+LCDVDD

SC:08/03 Add D32 ,R456 connect to


U49 pin3 and delete R46 that are for
LCD test function.

U49

34 LCD_TST_EN

R456

BAT54CPT-GP

C61

IN#1
OUT
EN
GND

GND
IN#8
IN#7
IN#6
IN#5

9
8
7
6
5

G5281RC1U-GP

ENVDD

1
2
3
4

C417

SC:08/13 Add
EC169,EC170,EC171,
R462,R463,R464 on
LVDS channel A each
data pairs. This is
for RF request
.Default is DY.

3D3V_S0

D32
10 LCDVDD_EN

SCD1U16V2ZY-2GP
2
1

1
2

SC5D6P50V2CN-1GP

AUD_DMIC_IN0_R

EC186

100KR2J-1-GP

1
2

SC5D6P50V2CN-1GP

1
2

SC:08/09 Add
EC161(78.10491.4FL)
for EMI request
.Default is DUMMY

-1:08/29 Change
LVDS channel A and
channel B EMI
solution. this is
for antena team
request.

EC184

AUD_DMIC_CLK_G_R

SC220P50V2KX-3GP

SC:08/09 Add
EC151(78.22124.2FL)
for EMI request
.Default is DUMMY

EC152

DY

EC151

DY

DY

SC:08/09 Add
EC153(78.10491.4FL)
for EMI request
.Default is DUMMY

SC220P50V2KX-3GP

EC153
SCD1U16V2ZY-2GP

SCD1U10V2KX-4GP

C342

1 R186
2
0R0603-PAD

1
2

C341
SC4D7U6D3V3KX-GP

1
2

SCD1U16V2ZY-2GP

SC:08/09 Add
EC154(78.10491.4FL)
for EMI request
.Default is DUMMY

5V_S0

INVERTER POWER

SC1U16V3ZY-GP

EC154

DY
2

+5V_RUN_CARMERA

SC5D6P50V2CN-1GP

EC171

EC185
SC5D6P50V2CN-1GP

1
2
1
2

EC168

SC5D6P50V2CN-1GP

EC170

CAMERA Power
V_AUD_DMIC

VGA_TXBCLKEC183

VGA_TXAOUT2-

Mic Power

VGA_TXBCLK+

VGA_TXAOUT1-

VGA_TXACLK+ 10

SC5D6P50V2CN-1GP

EC167

VGA_TXAOUT1+

VGA_TXACLK- 10

VGA_TXACLK+

VGA_TXAOUT2- 10
VGA_TXAOUT2+ 10

VGA_TXACLK-

VGA_TXAOUT2VGA_TXAOUT2+

EC182
SC5D6P50V2CN-1GP

VGA_TXAOUT1- 10
VGA_TXAOUT1+ 10

VGA_TXAOUT0- 10
VGA_TXAOUT0+ 10

VGA_TXAOUT1VGA_TXAOUT1+

VGA_TXACLK-

VGA_TXAOUT0VGA_TXAOUT0+

34

VGA_TXACLK+

VGA_TXAOUT2+

600ohm 100MHz
200mA 0.5ohm DC

FUSE-3A32V-7-GP
C58
SCD1U50V3KX-GP

EC161
BRIGHTNESS

0R2J-2-GP

VGA_TXAOUT0EC169

LBKLT_CTL 10

0R2J-2-GP

DY

VGA_TXBCLK- 10
VGA_TXBCLK+ 10

DY

VGA_TXAOUT0+

VGA_TXBOUT2- 10
VGA_TXBOUT2+ 10

VGA_TXBCLKVGA_TXBCLK+

2
R247

SCD1U16V2ZY-2GP

VGA_TXBOUT1- 10
VGA_TXBOUT1+ 10

VGA_TXBOUT2VGA_TXBOUT2+

1
2

VGA_TXBOUT1VGA_TXBOUT1+

DY

2
R245

IPEX-CONN40-2R-GP
20.F1093.040

1 R189
2
0R0603-PAD

DCBATOUT
F2

5V_AUX_S5

-1:09/02 Add R460 to


prevent power short
to GND via
"LCD_CBL_DET#"

48

3D3V_S0

VBL19
EC60
SC33P50V2JN-3GP

10KR2J-3-GP

41

DY

EC59
SC33P50V2JN-3GP

3D3V_S0

R246

-1:08/29 Change LCD1 pin 31 from GND to NC


BAT_SDA
BAT_SDA 34,38,39
BAT_SCL
BAT_SCL 34,38,39
BACKLITEON
LCD_TST
LCD_TST 34
LDDC_CLK
LDDC_CLK 10
LDDC_DATA
LDDC_DATA 10
LCD_DET_G
R460 1
2100R2J-2-GP
VGA_TXBOUT0VGA_TXBOUT0- 10
VGA_TXBOUT0+
VGA_TXBOUT0+ 10

1
50

LCD_TST

C56
SC1KP50V2KX-1GP

SC5D6P50V2CN-1GP

42

+LCDVDD

SC5D6P50V2CN-1GP

43

3D3V_S0

C57

44

34

SC5D6P50V2CN-1GP

45

LCD_CBL_DET#
5V_AUX_S5

SC1U10V3KX-3GP

LCD_CBL_DET#

46

VBL19

51
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

SCD1U10V2KX-4GP
EC16

47

DY

BACKLITEON

SC:08/05 Change C57 from


78.10423.5FL to
78.10523.5BL

SC:08/15 Rename "LCD2" to


"LCD1"

LCD1

49

SC:08/09 Add LCD2 (20.F1093.040) ,please check LCD1 and


LCD 2 layout overlap possibility.

SC:08/09 Add
EC152(78.22124.2FL)
for EMI request
.Default is DUMMY

LCD POWER

+5V_RUN_CARMERA

-1:09/11

V_AUD_DMIC
CAMERA1

1
R193

1
R195 1
R196 1

2 33R2J-2-GP
2 33R2J-2-GP

AUD_DMIC_CLK_G 32
AUD_DMIC_IN0 32

SC:08/09 Add EC157(78.33034.1FL)


for EMI request .Default is DUMMY

EC157
SC33P50V2JN-3GP

DY

DY

EC155
SC33P50V2JN-3GP

1
R188

SC:08/09 Add EC156(78.33034.1FL)


for EMI request .Default is DUMMY

SC:08/09 Add EC155(78.33034.1FL)


for EMI request .Default is DUMMY

EC156
SC33P50V2JN-3GP

DY

MLX-CON9-1-GP

DMIC_DET# 34

10

CAMERA_USB1CAMERA_USB1+

AUD_DMIC_CLK_G_R
AUD_DMIC_IN0_R

2
0R0603-PAD

2
3
4
5
6
7
8
9

11

USB_PN6 21

SC:08/13 Change L12


pin connection.pin
1 connect to
"USB_PN6", pin4
DY
connect to
DLW21SN900SQ2LUGP
"USB_PP6" . This
L12
change is for
layout request.

<Core Design>

Wistron Corporation

USB_PP6 21

2
0R0603-PAD

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

-1:09/11

Title

LCD/Inverter Connector
Size
Custom
Date:
A

Document Number

Rev

DS2-Intel
Sheet

Wednesday, September 12, 2007


E

-1
18

of

47

PCI_AD[0..31]

RN37

1
2
3
4

8
7
6
5

PCI_GNT1#
PCI_REQ1#
PCI_REQ2#
PCI_FRAME#

SRN8K2J-4-GP
RN39

1
2
3
4

8
7
6
5

PCI_PIRQG#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQE#

SRN8K2J-4-GP
RN41

1
2
3
4

8
7
6
5

PCI_IRDY#
PCI_GNT#0
PCI_PERR#
PCI_PLOCK#

1
2
3
4

SRN8K2J-4-GP
RN42
8
7
6
5

PCI_PIRQB#
PCI_PIRQC#
PCI_REQ#0
PCI_PIRQH#

1
2
3
4

SRN8K2J-4-GP
RN40
8
7
6
5

PCI_GNT3#
PCI_TRDY#
PCI_REQ3#
PCI_PIRQD#

1
2
3
4

SRN8K2J-4-GP
RN38
8
7
6
5

PCI_GNT2#
PCI_DEVSEL#
PCI_PIRQF#
PCI_STOP#

25 PCI_PIRQA#
25 PCI_PIRQC#

U27C 3 OF 6
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

F9
B5
C5
A10

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
GNT3#/GPIO55
REQ3#/GPIO54

A4
D7
E18
C18
B19
F18
C10
A11

C/BE0#
C/BE1#
C/BE2#
C/BE3#

C17
E15
F16
E17

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
FRAME#
PLOCK#
SERR#
STOP#
TRDY#

C8
D9
G6
D16
A7
A17
B7
F10
C16
C9

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_FRAME#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLTRST#
PCICLK
PME#

AG24
B10
G7

PCI_PLTRST#
CLK_PCI_ICH

PCI

PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_GNT3#
PCI_REQ3#

PCI_REQ#0 25
PCI_GNT#0 25
TP129
D

TP125

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

R398 1

25
25
25
25

Place closely pin B10


CLK_PCI_ICH

PCI_IRDY# 25
PCI_PAR 25

3D3V_S0

R425
10R2J-2-GP

PCI_DEVSEL# 25
PCI_PERR# 25
PCI_FRAME# 25

DY

PCI_SERR# 25
PCI_STOP# 25
PCI_TRDY# 25

C599
SC8P250V2CC-GP

1 1

25 PCI_AD[0..31]

DY
2

CLK_PCI_ICH 4
ICH_PME# 25

2 10KR2J-3-GP
3D3V_S5

-1:0909

Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

F8
G11
F12
B3

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

ICH8-M-1-GP-U-NF

SB:71.ICH8M.C0U
PCI_PCIRST#

PCIRST1# 25,27

SRN8K2J-4-GP

DY

R415
100KR2J-1-GP

A16 swap override Strap

Boot BIOS Strap

Low= A16 swap override Enable


High= Default *

PCI_GNT3#

PCI_GNT0#

SPI_CS#1

Boot BIOS Location


3D3V_S5

SPI

PCI

LPC *

U33B

14

PCI_GNT3#
R424

4
6

PLT_RST1#

PLT_RST1# 8,23,24,28,29,30,34

5
7

1KR2J-1-GP

DY

PCI_PLTRST#

R419 2

DY

SSLVC08APWR-GP

R416
100KR2J-1-GP

1 33R2J-2-GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH8(1/4)-PCI/INT
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
1

19

of

47

+RTCVCC

-1:0909
1
R365

LAN100_SLP
2
330KR2J-L1-GP

1
R364

SM_INTRUDER#
2
1MR2J-1-GP

1
R356

ICH_INTVRMEN
2
330KR2J-L1-GP

+RTCVCC
U27A1 OF 6

LPC_LAD[0..3]

34
D

2
G26
GAP-OPEN

ICH_RTCRST#

AF23

RTCRST#

SM_INTRUDER#

AD22

INTRUDER#

AF25
AD21

INTVRMEN
LAN100_SLP

ICH_INTVRMEN
LAN100_SLP

R368 1
R367 1
R366 1

233R2J-2-GP

HDA_SDOUT
G62
1

GAP-OPEN TP101

C520 1
C521 1

2SC3900P50V2KX-2GP
2SC3900P50V2KX-2GP

SATA_TXN0_C
SATA_TXP0_C

-1:0912

1
C203

ICH_RTCX2

2
SC12P50V2JN-3GP

4 CLK_PCIE_SATA#
4 CLK_PCIE_SATA
R119
1
2

CL=12.5pF

24D9R2F-L-GP
R111
10MR2J-L-GP

X-32D768KHZ-40GPU
X1

LAN_RSTSYNC

C21
B21
C22

LAN_RXD0
LAN_RXD1
LAN_RXD2

D21
E20
C20

LAN_TXD0
LAN_TXD1
LAN_TXD2

D25
C25
AJ16
AJ15

HDA_RST#

35 SATA_LED#
24 SATA_RXN0_C
24 SATA_RXP0_C
24 SATA_TXN0
24 SATA_TXP0

LPC_LFRAME#

LDRQ0#
LDRQ1#/GPIO23

G9
E6

LPC_DRQ0#
LPC_DRQ1#

A20GATE
A20M#

AF13
AG26

H_A20M#

DPRSTP#
DPSLP#

AF26
AE26

1D05V_S0
LPC_LFRAME# 34

R124
H_FERR#

TP123
TP127

GLAN_DOCK#/GPIO13
GLAN_COMPI
GLAN_COMPO
HDA_BIT_CLK
HDA_SYNC

AE14

HDA_RST#

AJ17
AH17
AH15
AD13

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AE13

HDA_SDOUT

AE10
AG14

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6
AF5
AH5
AH6

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AG3
AG4
AJ4
AJ3

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AF2
AF1
AE4
AE3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AB7
AC6

SATA_CLKN
SATA_CLKP

AG1
AG2

SATARBIAS#
SATARBIAS

KA20GATE 34
H_A20M# 5

H_DPRSTP#

H_DPRSTP#

FERR#

AD24

CPUPWRGD/GPIO49

AG29

H_PWRGOOD

H_PWRGOOD 6,46

IGNNE#

AF27

H_IGNNE#

H_IGNNE# 5

INIT#
INTR
RCIN#

AE24
AC20
AH14

H_INIT#

NMI
SMI#

AD23
AG28

H_NMI

H_NMI 5
H_SMI# 5

STPCLK#

AA24

H_STPCLK#

H_STPCLK# 5

THRMTRIP#

AE27

THRMTRIP_ICH#
1
R122

TP8

AA23

Within 500 mils

TP105

H_DPRSTP# 6,8,41

H_DPSLP#
H_FERR#

H_DPSLP# 6
H_FERR# 5

H_DPSLP#

TP108

within 2" from R184

H_INIT# 5
H_INTR 5
KBRCIN# 34

KBRCIN#

1
56R2J-4-GP

1D05V_S0

GLAN_COMP

HDA_BITCLK_R
HDA_SYNC

233R2J-2-GP
233R2J-2-GP
233R2J-2-GP

R363 1

GLAN_CLK

AH21

233R2J-2-GP

R348 1

31 ICH_SDIN_MDC
23 ICH_SDIN_S1392
32 ICH_SDIN_CODEC
23,31,32 ICH_SDOUT_CODEC

C4

R123
56R2J-4-GP

31 ICH_AZ_MDC_RST#
23 ICH_AZ_S1392_RST#
32 ICH_AZ_CODEC_RST#

FWH4/LFRAME#

CPU

R414
24D9R2F-L-GP

33R2J-2-GP

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

IDE

B24
D22

LAN/GLAN

1D5V_S0

R454

23,31,32 ICH_AZ_CODEC_SYNC

E5
F5
G8
F6

IHDA

SB: 0702 Add R454 in "HDA_BITCLK" for EMI request.

23,31,32 HDA_BITCLK

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

C205
SC1U10V3KX-3GP

RTCX1
RTCX2

SATA

2
20KR2J-L2-GP
1

1
R120

AG25
AF24

LPC

ICH_RTCX1
ICH_RTCX2

-1:0909

RTC

IDE_PDD[0..15]

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

H_THERMTRIP# 5,8,34,46

24R2J-GP

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

DA0
DA1
DA2

AA4
AA1
AB3

IDE_PDA0 24
IDE_PDA1 24
IDE_PDA2 24

DCS1#
DCS3#

Y6
Y5

IDE_PDCS1# 24
IDE_PDCS3# 24

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

W4
W3
Y2
Y3
Y1
W5

IDE_PDIOR# 24
IDE_PDIOW# 24
IDE_PDDACK# 24
INT_IRQ14 24
IDE_PDIORDY 24
IDE_PDDREQ 24

placed within 2" from ICH8M

24

SB:71.ICH8M.C0U

ICH8-M-1-GP-U-NF

-1: 0904 change to DY


3D3V_AUX_S5

1
C202

2
SC12P50V2JN-3GP

ICH_RTCX1

RTC1

W=20mils
+RTCVCC

HDA_BITCLK

U60

1
2
MH1
MH2

BATT1.1

W=20mils
2

1
R437

DY

1
C625
SC1U10V3ZY-6GP

W=20mils

RTCVCC_R
2
3
100R2J-2-GP W=20mils

R438

1
CH715FPT-GP

BATT_R 1

BAT-CON2-U3-GP

1KR2J-1-GP

2
A

SC22P50V2JN-4GP

C636

PWR
GND
MH1
MH2

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Please Place C636 near R454


Title

ICH8(2/4) LAN,HD,IDE,LPC
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


5

Sheet
1

-1
20

of

47

3D3V_S0

3D3V_S5

Place closely pin G5

Place closely pin AG9

RN69

RSMRST#_KBC
10KR2J-3-GP

27,28 PCIE_WAKE#
25,34 INT_SERIRQ
36 THRM#

GPIO26
PM_BATLOW#_R
OCP#
SMLINK1

8
7
6
5

SRN10KJ-6-GP

3D3V_S0

SRN10KJ-6-GP
RN68
8
7
6
5

GPIO22
USB_OC#6
USB_OC#4
USB_OC#2

1
2
3
4

8
7
6
5

SRN10KJ-6-GP
RN66
SMLINK0
1
USB_OC#5
2
USB_OC#7
3
USB_OC#9
4

8
7
6
5

SRN10KJ-6-GP
RN67
USB_OC#8
1
DBRESET#
2
ECSMI#
3
USB_OC#1
4

WAKE#
SERIRQ
THRM#

AJ20

VRMPWRGD

AJ22

AJ8
AJ9
AH9
AE16
AC19
GPIO17
AG8
TP98
GPIO18
AH12
TP69
GPIO20
AE11
TP112
GPIO22
AG10
AH25
TP63
AD16
TP111
CLKSATAREQ# AG13
4 CLKSATAREQ#
GPIO38
AF9
TP104
GPIO39
AJ11
TP70
IDE_RESET# AD10
TP109

34 ECSCI#
34 ECSMI#
34 ECSWI#

SB:06/27 Change RN68 pin1


define from"ECSWI#" to
"GPIO22", pin 8
connection from 3D3V_S5
to 3D3V_S0.

SB_SPKR

32 SB_SPKR

AD9

MCH_ICH_SYNC# AJ13

8 MCH_ICH_SYNC#

ICH_RSVD

TP68

AJ21

TP7
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SPKR
MCH_SYNC#
TP3

Low--> default

1 2

GPIO

SATA

SMB

AE17
AF12
AC13

GPIO1
GPIO6
ECSCI#
ECSMI#

TP72
TP71

CLOCKS

CLKRUN#

INT_SERIRQ
THRM#

DY

SMB_LINK_ALERT#
PCIE_WAKE#
ICH_RI#
USB_OC#0

8
7
6
5

AH11

VRMPWRGD
2
0R2J-2-GP
SST_CTL
TP67

1
R342

8,41 VGATE_PWRGD

RN65
1
2
3
4

STP_PCI#
STP_CPU#

25,34 PM_CLKRUN#

RN64
1
2
3
4

SMBALERT#/GPIO11

AE20
AG18

D3
AG23
AF21
AD18

S4_STATE#/GPIO26

AH27

GPIO26

PWROK

AE23

PM_PWROK

DPRSLPVR/GPIO16

AJ14

DPRSLPVR

BATLOW#

AE21

PM_BATLOW#_R

PWRBTN#

C2

LAN_RST#

AH20

RSMRST#

AG27

PM_PWROK 8,36

DY

DPRSLPVR 8,41

2
0R0402-PAD

EC_RMRST#

CK_PWRGD

E1

CLPWROK

E3

CL_PWRGD_R

SLP_M#

AJ25

SLP_M#

CL_CLK0
CL_CLK1

F23
AE18

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

F22
AF19

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

D24
AH23

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST#

AJ23

CLGPIO0/GPIO24
CLGPIO1/GPIO10
CLGPIO2/GPIO14
CLGPIO3/GPIO9

AJ27
AJ24
AF22
AG19

CK_PWRGD 4
R411 1
TP66

DY

2 0R2J-2-GP
0R2J-2-GP

CL_CLK0 8
TP110
CL_DATA0 8
TP103

R422
1

GPIO24
GPIO10
GPIO14
GPIO9

C598

TP73
TP64
TP99
TP100

3D3V_S0

4
3

Mini Card 2
RN61
SRN2K2J-1-GP

Mini Card 3
3D3V_S0

1
2

New Card

29 PCIE_RXN2
29 PCIE_RXP2
29 PCIE_TXN2
29 PCIE_TXP2

1C238
1C236

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

30 PCIE_RXN3
30 PCIE_RXP3
30 PCIE_TXN3
30 PCIE_TXP3

1C242
1C240

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

30 PCIE_RXN4
30 PCIE_RXP4
30 PCIE_TXN4
30 PCIE_TXP4

1C247
1C244

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

28 PCIE_RXN5
28 PCIE_RXP5
28 PCIE_TXN5
28 PCIE_TXP5

1C254
1C251

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PCIE_C_TXN2
PCIE_C_TXP2

M27
M26
L29
L28

PERN2
PERP2
PETN2
PETP2

PCIE_C_TXN3
PCIE_C_TXP3

K27
K26
J29
J28

PCIE_C_TXN4
PCIE_C_TXP4

H27
H26
G29
G28

PERN4
PERP4
PETN4
PETP4

PCIE_C_TXN5
PCIE_C_TXP5

F27
F26
E29
E28

PERN5
PERP5
PETN5
PETP5

D27
D26
C29
C28

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SD

C23
B23
E22

SPI_CLK
SPI_CS0#
SPI_CS1#

D23
F21

SPI_MOSI
SPI_MISO

SPI_CS1#

TP128

2N7002SPT
38
38
35
35

3D3V_S5

32K suspend clock output


1

3D3V_S0

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

3D3V_S5

R351
2K2R2J-2-GP

R91
10KR2J-3-GP

R327
U20A

14

DY

1
3

ICH_SUSCLK

ICH_32KHZ

1
R93

2
10R2J-2-GP

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

0R2J-2-GP
D28

G792_CLK 36

EC_RMRST#

TSLVC08APW-1-GP

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

PERN3
PERP3
PETN3
PETP3

V27
V26
U29
U28

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

8
8
8
8

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

8
8
8
8

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA29
AA28

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

T26
T25

DMI_ZCOMP
DMI_IRCOMP

Y23
Y24

USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

USBRBIAS#
USBRBIAS

F2
F3

ICH8-M-1-GP-U-NF

DY
3

DY

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

PERN1
PERP1
PETN1
PETP1

SMB_DATA 28,29,30

ICH_SMBCLK 4,14,15

3D3V_S0

PCIE_C_TXN1
PCIE_C_TXP1

P27
P26
N29
N28

R116
330R2J-3-GP
R117 1
0R2J-2-GP

1C234
1C232

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

U55

28,29,30 SMB_CLK

3D3V_S5

DY

R118 1
0R2J-2-GP

Mini Card 1

4,14,15 ICH_SMBDATA

2
3K24R2F-GP

R107
453R2F-1-GP

CK_PWRGD

VRMPWRGD

Q12
2N7002PT-U
1

41 CLK_EN#
G

LAN

U27B 2 OF 6
27 PCIE_RXN1
27 PCIE_RXP1
27 PCIE_TXN1
27 PCIE_TXP1

Direct Media Interface

R102 2

R423
453R2F-1-GP

R110

10KR2J-3-GP
SB_SPKR
1
2
R361
DY

3D3V_S0

3D3V_S0

SB:06/27 Add R450 for


"ECSWI#" pull up to 3D3V_S5

DPRSLPVR
1
100KR2J-1-GP
GPIO9
1
100KR2J-1-GP

R341 2

3K24R2F-GP

SB:71.ICH8M.C0U

PCI-Express

2 ECSWI#
10KR2J-3-GP

VGATE_PWRGD 8,41
PM_PWROK

R346

CL_RST# 8

SPI

R450 1

DY

PM_PWRBTN# 34
1
R112

C201
2 USB_OC#3
10KR2J-3-GP

C522
SC4D7P50V2CN-1GP

2 R347
10KR2J-3-GP

SRN10KJ-6-GP
R369 1

DY

ICH8-M-1-GP-U-NF

High--> No boot

DY

C589
SC4D7P50V2CN-1GP

PM_SLP_S3# 28,34,43,45,46
PM_SLP_S4# 28,34,40,44,45

AG22

H_STP_PCI#
H_STP_CPU#

R349
10R2J-2-GP

DY

1
R96

OCP#

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

SCD1U16V2KX-3GP
2
1

DY

BMBUSY#/GPIO0

R400
10R2J-2-GP

ICH_SUSCLK

1
2
4 H_STP_PCI#
4 H_STP_CPU#

SUS_STAT#/LPCPD#
SYS_RESET#

AG12

CLK_14M_ICH 4
CLK_48M_ICH 4

DY
3D3V_S5

F4
AD15

PM_BMBUSY#

AG9
G5

CLK14
CLK48

SCD1U16V2KX-3GP
2
1

8 PM_BMBUSY#

RI#

SYSGPIO

RN70
SRN2K2J-1-GP

AF17

PM_SUS_STAT#
DBRESET#

SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3

AJ12
AJ10
AF11
AG11

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
GPIO37

POWER MGT

TP124

4
3

ECSCI#
2
10KR2J-3-GP

R449 1

ICH_RI#

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

GPIO

3D3V_S0

AJ26
AD19
AG21
AC17
AE19

Controller Link

SB:06/27 Delete RN74, add


R449 for "ECSCI#" pull up to
3D3V_S0

SMB_CLK
SMB_DATA
SMB_LINK_ALERT#
SMLINK0
SMLINK1

MISC

SRN10KJ-6-GP

1
2

SATA0_R0
SATA0_R1
THRM#
CLKSATAREQ#

8
7
6
5

1 2

U27D 4 OF 6

SRN10KJ-6-GP
RN62
1
2
3
4

CLK_14M_ICH

RN63
SRN2K2J-1-GP

CLK_48M_ICH

PM_CLKRUN#
SATA0_R3
SATA0_R2
INT_SERIRQ

8
7
6
5

4
3

1
2
3
4

CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP 1
R376

USBRBIAS 1
R403

S
B

CLK_PCIE_ICH# 4
CLK_PCIE_ICH 4

Within 500 mils


2
24D9R2F-L-GP
USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
USB_PN6
USB_PP6
TP118
TP117
USB_PN8
USB_PP8
USB_PN9
USB_PP9

USB_PN7
USB_PP7

8
8
8
8

2
20R2F-GP

1D5V_S0

38
38
38
38
35
35
35
35
30
30
31
31
18
18

USB1
USB2
USB3
USB4
MINICARD2
BlUETOOTH
CAMERA

28
28
30
30

New Card
MINICARD3
SB:0710 Change R403 from
22.6 Ohm to 22 Ohm

Within 500 mils

SB:71.ICH8M.C0U
RSMRST#_KBC 34

2
2

SB:06/20 Add 2N7002 Q35 for G792


"G792_CLK"

BAS16-1-GP
R350
100KR2J-1-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Q35
2N7002PT-U

RUN_POWER_ON

Title

ICH8(3/4) PM,USB,GPIO
Size
Custom

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


5

Sheet
1

-1
21

of

47

+RTCVCC

U27F 6 OF 6

20 mils

1
2

C574
SCD1U16V2ZY-2GP

1D5V_S0
TP126
TP121

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

1
C584

1D5V_S0

3D3V_S0

VCCHDA

SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP

VCC1_5_A
VCC1_5_A

VCCSUS1_05
VCCSUS1_05

VCC1_5_A
VCC1_5_A
VCC1_5_A

VCCSUS1_5

AC16

VCCSUS1_5_ICH_1

VCCSUS1_5

J7

VCCSUS1_5_ICH_2

VCC1_5_A
VCC1_5_A

VCCSUS3_3

C3

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

AC18
AG20
AC21
AC22
AH28

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

P6
P7
N7
C1
P1
R1
P2
P3
R3
P4
P5
R5
R6

F1
L6
L7
M6
M7

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

W23

VCC1_5_A

F17
G18

VCCLAN1_05
VCCLAN1_05

F19
G20

VCCLAN3_3
VCCLAN3_3

A24

VCCGLANPLL

A26
A27
B26
B27
B28

VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5

B25

VCCGLAN3_3

1
2

SC1U10V3ZY-6GP

1
2

1
2

C536
SCD1U16V2ZY-2GP

AC12
AD11
J6
AF20

VCCUSBPLL

SCD1U16V2ZY-2GP

1
2

C596

SCD1U16V2ZY-2GP

VCCSUSHDA

D1

C541

3D3V_S5

TP119

C571

TP113

3D3V_S0

C583

TP120
TP102

3D3V_S5

SCD1U16V2ZY-2GP
C567

AC7
AD7

SC1U10V3ZY-6GP

1
2

1
2

SCD1U16V2ZY-2GP
2

1
2

SCD1U16V2ZY-2GP

1
2

SCD1U16V2ZY-2GP

1
2

SCD1U16V2ZY-2GP

3D3V_S0

SCD1U16V2ZY-2GP

C558
SCD1U16V2ZY-2GP

G12
G17
H7

SCD1U16V2ZY-2GP

C546
SCD1U16V2ZY-2GP

AA5
AA6

C554

VCC1_5_A
VCC1_5_A

(SATA)
C600

AC10
AC9

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

C579

(DMI)
C595

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

AA3
U7
V7
W1
W6
W7
Y7

3D3V_S0
3D3V_S0

CORE

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

1D5V_S0

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

GLAN POWER

C216
SC10U6D3V5KX-1GP

1D5V_S0

C212
SC1U10V3ZY-6GP

1
2

SC10U6D3V5KX-1GP

C235

AC8
AD8
AE8
AF8

C273

1D05V_S0

3D3V_S0

AC1
AC2
AC3
AC4
AC5

SCD1U16V2ZY-2GP

VCC3_3
VCC3_3
VCC3_3
VCC3_3

C272

C228
SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP 3D3V_S0
SCD1U16V2ZY-2GP

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

3D3V_S0

AD2

1D5V_S0
C547

AF29

VCC3_3

3D3V_S5

1D5V_S0

SCD1U16V2ZY-2GP

VCC3_3

C195

1D25V_S0
C208

VCCCL1_05

G22

VCCCL1_05_ICH

VCCCL1_5

A22

VCCCL1_5_ICH

VCCCL3_3
VCCCL3_3

F20
G21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
ICHGND1
A1
A2
A28
A29 ICHGND2
AJ28
AH1
AH29
AJ1 ICHGND3
AJ2
AJ29 ICHGND4
B1
B29

TP78
TP77

TP65
TP74
B

ICH8-M-1-GP-U-NF

C224

SC1U10V3ZY-6GP

AC23
AC24

C199

V_CPU_IO
V_CPU_IO

C196

1D5V_S0

AE28
AE29

C551

L5
1
2
IND-1UH-36-GP

C226
SCD01U16V2KX-3GP

SC4D7U6D3V3KX-GP

SC1U10V3ZY-6GP

AE7
AF7
AG7
AH7
AJ7

C233

1D5V_S0

C200
SC10U6D3V5KX-1GP

1
2

1
2

SC1U10V3ZY-6GP

C198

C573

R29

VCC_DMI
VCC_DMI

VCCSATAPLL

C576

1D5V_DMIPLL_S0

AJ6

1D5V_S0

C580

C588
SCD1U16V2ZY-2GP

VCCPSUS

ICH_V5REF_SUS

20 mils

VCCPUSB

D20

100R2J-2-GP

VCCDMIPLL

VCCP CORE

C221
SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

BAS16-1-GP

2
2

1
R147

C197

SC2D2U10V3ZY-1GP
2
1

SC2D2U10V3ZY-1GP

2
3D3V_S5

5V_S5

C220

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

SC10U6D3V5KX-1GP

C217

VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B

ATX

3
1

20 mils
ICH_V5REF_RUN
C555
SCD1U16V2ZY-2GP

V5REF_SUS

IDE

R387
100R2J-2-GP

AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25

V5REF
V5REF

PCI

1
2

1
2

C213
SC1U10V3ZY-6GP

BAS16-1-GP
D18

C262
SC1U10V3ZY-6GP

3D3V_S0

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

5V_S0

C215

C260

1D5V_S0

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCCA3GP

G4

ARX

ICH_V5REF_SUS

5 OF 6

VCCRTC

SC10U6D3V5KX-1GP

T7
A16

USB CORE

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1D05V_S0
U27E

AD25
ICH_V5REF_RUN

SC10U6D3V5KX-1GP

A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6

C532

C530

TP122
TP79

R399 1 3D3V_S0
2
0R0603-PAD

ICH8-M-1-GP-U-NF

SB:71.ICH8M.C0U

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH8(4/4) POWER&GND
Size
A2
Date:
5

Document Number

Rev

DS2-Intel
Wednesday, September 12, 2007
1

Sheet

-1
22

of

47

SB:06/22 Change R279,R280,R281,R282 from 63.30134.1DL


to 63.12134.1DL
HDMI_TXD#1

16 HDMI_TXD#1

16 HDMI_TXD1
4

HDMI_TXD0

HDMI_TXD#1_1 1
2
120R2J-2-GP
C455
HDMI_TXD1

1
R281

2
SCD1U10V2KX-4GP

HDMI_TXD#2

16 HDMI_TXD#2

16 HDMI_TXD2

2
SCD1U10V2KX-4GP
HDMI_TXD#0 16

HDMI_TXC

HDMI_TXD#2_2 1
2
120R2J-2-GP
C456
HDMI_TXD2

1
R282

HDMI_TXD0 16

2 HDMI_TXD#0_0
1
120R2J-2-GP
C454
HDMI_TXD#0

1
R280

2
SCD1U10V2KX-4GP

HDMI_TXC 16

2 HDMI_TX#C_C1 1
120R2J-2-GP
C453
HDMI_TX#C

1
R279

2
SCD1U10V2KX-4GP
HDMI_TX#C 16

HDMI_HDP 16

41
45
53
59
62

SPGND

63

1
2

1
2

3D3V_S0

PVCC2

R314
1
0R0603-PAD

C495
SC1KP50V2KX-1GP

1
2

C496
SCD1U10V2KX-4GP

C150
SCD1U10V2KX-4GP

2
2

C489
SC1U6D3V2KX-GP

C151
SC1KP50V2KX-1GP

2
1
2
1

C497
SC10U10V5KX-2GP

R311
1
1D8V_S0
0R0603-PAD

2 R283
1
0R0603-PAD

1D8V_S0

R72
2
1
0R0603-PAD

1D8V_S0
2

ICH_AZ_S1392_BITCLK
2
0R2J-2-GP

1
R345

20,31,32 HDA_BITCLK

39
37

SII1392CNU-GP-U

TEST

44

SPVCC

C494
SC1KP50V2KX-1GP

SB: 0710 Change R345 from 33 Ohm to 0


Ohm

SCLROM
SDAROM

SPDIF/HDASDO
LSCL/DCEN
LSDA/PREEMP
LINT#

14
13

2
C491

GND
GND
SGND
SGND
SPVCC

SDADDC
SCLDDC

DY

SVCC

12
11

PVCC1

3D3V_S0

C457
SC10U6D3V5KX-1GP

C462
SC1U6D3V2KX-GP

50
56

A1

R287
2
1
0R0603-PAD

C152
SC1U6D3V2KX-GP

SVCC
SVCC

34
4
3
15

16 HDMI_SDATA
16 HDMI_SCLK

A1
2
1KR2J-1-GP
HDMI_SDATA
HDMI_SCLK

HDASYNC

1
R81

DY
SC10U6D3V5KX-1GP

PVCC2
AVCC33V
VCC_PWR

RESET#
SDSCL
SDSDA

31
32
33

1
7
6

C451
SCD1U10V2KX-4GP

PVCC2
AVCC3.3
VCC

8,19,24,28,29,30,34 PLT_RST1#
8 SDVO_CTRLCLK
8 SDVO_CTRLDATA

C488

PVCC1

EXT_RES

17

49

OVCC

30mA

PVCC1

2 EXT_RES
1KR2J-1-GP

SDC+
SDC-

40

1
R312

60
61

AVCC33V

OVCC

64

SDVOB_C+
SDVOB_C-

10 SDVOB_C+
10 SDVOB_C-

DY
SC10U6D3V5KX-1GP
R313
2
1
3D3V_S0
0R0603-PAD

18
24
30
65

1D8V_S0

AGND
AGND
AGND
GND

1
0R0603-PAD

SDB+
SDB-

R77

2
C154

C459
C452
SC1KP50V2KX-1GP SC1KP50V2KX-1GP

57
58

SDVOB_B+
SDVOB_B-

10 SDVOB_B+
10 SDVOB_B-

AVCC

21
27

LAYOUT must support


connectors from JAE,
Molex, and Acon

AVCC
AVCC

1D8V_S0

C481
SC10U6D3V5KX-1GP

C149
SC1KP50V2KX-1GP

SDG+
SDG-

R309
2
1
0R0603-PAD

54
55

SDVOB_G+
SDVOB_G-

HDARST#
HDASDI

10 SDVOB_G+
10 SDVOB_G-

35
36

C466
SCD1U10V2KX-4GP

5
10

GND
GND

C485
SCD1U10V2KX-4GP

SDR+
SDR-

C472
SC1KP50V2KX-1GP

51
52

SDVOB_R+
SDVOB_R-

HDABCLK
HDAVCC

10 SDVOB_R+
10 SDVOB_R-

SDI+
SDI-

46
47

550mA

VCC_PWR

SC10U6D3V5KX-1GP

2
43
9
48
38

42
16

20
19
TXC+
TXC-

23
22
TX0+
TX0-

VCC
VCC
VCC
VCC
VCC

C471
SC100P50V2JN-3GP

2SCD1U10V2KX-4GP S_INT+
2SCD1U10V2KX-4GP S_INT-

AVCC
2
560R2F-GP

1
R291

SB:06/22 Change R291 from 64.75005.6DL to


64.56005.6DL

HTPLG
EXT_SWING

10 SDVOB_INT+
10 SDVOB_INT-

C482 1
C487 1

TX1+
TX1-

TX2+
TX2-

29
28

U52

26
25

EXT_SWING1

R294
R303

R75
HDAVCC

DY

1 AUD_SPDIF_OUT
22R2J-2-GP
ICH_AZ_S1392_SDOUT

ICH_AZ_S1392_SYNC

3D3V_S0

2D5V_S0

AUD_SPDIF_OUT

32

ICH_SDOUT_CODEC
ICH_AZ_CODEC_SYNC

RN57
SRN4K7J-8-GP

20,31,32
20,31,32

4K7R2J-2-GP

R304
0R0603-PAD

1
4K7R2J-2-GP

4
3

3D3V_S0

R306

DY

ICH_AZ_S1392_SDIN2_C 2
R297
ICH_AZ_S1392_RST#

DY

1
33R2J-2-GP

ICH_SDIN_S1392

SDVO_CTRLCLK
SDVO_CTRLDATA

20

1
2

R80
4K7R2J-2-GP

DY

ICH_AZ_S1392_RST# 20

4K7R2J-2-GP

C161
SCD1U10V2KX-4GP

-1:09/06 Change EC83 from ASM to DUMMY.

<Core Design>

EC83
SC22P50V2JN-4GP

Wistron Corporation

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

ICH_AZ_S1392_BITCLK

Title

SiI 1392 HDMI


Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
E

23

of

47

SATA HD Connector

CD-ROM Connector
IDE_PDD[0..15]

HDD1

23
NP1
1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP2
24

C253
SCD1U16V2ZY-2GP

DY

DY

C258
SC10U6D3V5KX-1GP

C268
SCD1U16V2ZY-2GP

-1:09/02 Change HDD power


net from "5V-S0" to
"ODD_5V_S0" for Sniffer
function circuit.

C264
SC10U10V5ZY-1GP

HDD_5V_S0

20 IDE_PDDREQ
20 IDE_PDIOR#
20 IDE_PDDACK#

-1:09/02 Change ODD power


net from "5V-S0" to
"ODD_5V_S0" for Sniffer
function circuit.

IDE_PDA2

20 IDE_PDA2
20 IDE_PDCS3#

ODD_5V_S0
C186
SC10U10V5ZY-1GP

C191
SCD1U16V2ZY-2GP

4
3

RSTDRV#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

RN23
SRN8K2J-3-GP

1
2

SC3900P50V2KX-2GP
3D3V_S0

SATA_RXN0
SATA_RXP0

2
2

3D3V_S0

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
51

49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

C564 1
C568 1

20 SATA_RXN0_C
20 SATA_RXP0_C

2
3
4
5
6
7

SC3900P50V2KX-2GP

20 SATA_TXP0
20 SATA_TXN0

20

CDROM1

IDE_PDIOW#

20
IDE_PDIORDY 20
INT_IRQ14 20

IDE_PDA1
IDE_PDA0

IDE_PDA1 20
IDE_PDA0 20
IDE_PDCS1# 20

ODD_5V_S0
CSEL

-1:09/02 Change ODD power


net from "5V-S0" to
"ODD_5V_S0" for Sniffer
function circuit.

GND : Master
Open: Slave

SYN-CON22-GP-U
FOX-CONN50-4R-4GP

Main Source:20.80919.022
5V_S0

8,19,23,28,29,30,34

Close to Connector

10

14

3D3V_S0

PLT_RST1#

IDE_RST_MOD#1
R100

2 RSTDRV#_5
56R2J-4-GP

R97
U9C

IDE_PDIOW#
2
4K7R2J-2-GP

TSAHCT125PW-GP
5V_S0

ODD_5V_S0

5V_S5

5V_S0

HDD_5V_S0

DY

U68

DY

5V_S5

R461
100KR2J-1-GP

2 0R3-0-U-GP

R464 1

2 0R3-0-U-GP

DY

HDD_5V_EN 34

5V_S0

DY

HDD_5V_S0

R467
100KR2J-1-GP
U35

8
7
6
5

RUN_POWER_ON

2N7002SPT

-1:09/02 Add ODD 5V power control


circuit for Sniffer function,
default is DY

DY

ODD_5V_S0

2N7002SPT

R462
100KR2J-1-GP

Q38

SI4800BDY-T1

DY
1

1
2
3
4

ODD_PWR_EN

-1:0910

HDD_PWR_EN

FDC655BN-GP

-1:0910

-1:0906 Add C639 for


"ODD_5V_EN#"

DY

2 0R3-0-U-GP

5V_S0

RUN_POWER_ON

-1:09/02 Add HDD 5V power control


circuit for Sniffer function,
default is DY

C639

SCD1U25V3KX-GP

HDD_5V_EN_R

2 0R3-0-U-GP

R471 1

HDD_5V_EN 34

U67

R463 1

2 0R3-0-U-GP

R469 1

D
D
D
D

ODD_5V_EN_R

2 0R3-0-U-GP

R468 1

G
S
S
S

DY

R466
100KR2J-1-GP

R470 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HD/CDROM/USB
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

-1
24

of

47

3D3V_S0

3D3V_S0

PCI_AD25

R180
10KR2J-3-GP

1 2

R179

1
2
0R2J-2-GP

34 GBRST#_KBC

DY

C331
SCD1U16V2ZY-2GP

PCI_C/BE#3
19 PCI_C/BE#3
PCI_C/BE#2
19 PCI_C/BE#2
PCI_C/BE#1
19 PCI_C/BE#1
PCI_C/BE#0
19 PCI_C/BE#0
1
2 R5C834_IDSEL
R150
10R2J-2-GP

19 PCI_REQ#0
19 PCI_GNT#0
19 PCI_FRAME#
19 PCI_IRDY#
19 PCI_TRDY#
19 PCI_DEVSEL#
19 PCI_STOP#
19 PCI_PERR#
19 PCI_SERR#
GBRST#
19,27 PCIRST1#

4 PCLK_PCM

SHIELD
GND

19 ICH_PME#

DY

1
0R2J-2-GP

124
123
23
24
25
26
29
30
31

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

71
119

GBRST#
PCIRST#

121

PCICLK

70
117

PME#

86

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

4
13
22
28
54
62
63
68
118
122

AGND1
AGND2
AGND3
AGND4
AGND5

99
102
103
107
111

C
3D3V_S0

R177
4K7R2J-2-GP

HWSPND#

69

MSEN

58

3D3V_S0

XDEN

55

UDIO5

57

UDIO3
UDIO4

65
59

UDIO2

56

UDIO1

60

UDIO0/SRIRQ#

72

8
7
6
5

DY

RN43

1
2
3
4

EC44
SCD1U16V2ZY-2GP

SRN10KJ-6-GP

1
R164

2
100KR2J-1-GP

3D3V_S0

INT_SERIRQ 21,34

INTA#

115

PCI_PIRQA# 19

INTB#

116

PCI_PIRQC#

19

1394 : INTA#
4in1 : INTB#
TEST

66

CLKRUN#

R151
10KR2J-3-GP

DY

C290
SC10U6D3V5KX-1GP

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

C283

R178

VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5

21,34 PM_CLKRUN#

125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8

67

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

3D3V_S0

VCC_RIN

VCC_MD

19 PCI_AD[0..31]

19 PCI_PAR

61

VCC_3V

PCI / OTHER

1
2

C280

SCD01U16V2KX-3GP

SCD47U16V3ZY-3GP

C278

SCD47U16V3ZY-3GP

1
2

C319

SCD01U16V2KX-3GP
2
1

1
2

1
2

C297

SCD1U16V2ZY-2GP

VCC_PCI1
VCC_PCI2
VCC_PCI3
VCC_PCI4
VCC_PCI5
VCC_PCI6

16
34
64
114
120

VCC_ROUT
C282

10
20
27
32
41
128

SCD01U16V2KX-3GP

C326

SCD01U16V2KX-3GP

C312

SCD01U16V2KX-3GP

C279

SCD01U16V2KX-3GP
2
1

SCD01U16V2KX-3GP
2
1

3D3V_S0

C281

SCD01U16V2KX-3GP

C288

DY

U37B
C325
SC10U6D3V5KX-1GP

R173
100KR2J-1-GP

R5C833-GP

DY

C293
SC10P50V2JN-4GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

R5C833/PCI
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

-1
25

of

47

3D3V_PHY
3D3V_S0
2 R174
1
0R0603-PAD

C303
SCD01U16V2KX-3GP

-1:09/11

113

94
X4
X-24D576MHZ-70GP

XI

1
C324

1
R170

95

XO

RICHO_FILO
2
SCD01U16V2KX-3GP

96

2RICHO_REXT
10KR2F-2-GP

101

REXT

RICHO_VREF
2
SCD01U16V2KX-3GP

100

VREF

IEEE1394/SD

1394_XO
2
SC12P50V2JN-3GP

FIL0

TPBN0

104

TPB0N

TPBP0

105

TPB0P

TPAN0

108

TPA0N

TPAP0

109

TPA0P

C190

R90

CLOSE TO CHIP

DY
TPA0-

6
5
4
3
2
1

GND
GND
TPA0+
TPA0TPB0+
TPB0-

2
C330
1

TPBIAS0

SB:06/13 Change X4 from


82.30023.561 to 82.30023.611

TPBIAS0

R89

C189

3
4
DLW21HN900SQ2LGP

SCD01U16V2KX-3GP

TPB0+

R316

2
0R0402-PAD

R321

2
0R0402-PAD

TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N

SC12P50V2JN-3GP
1394_XI
2

C329
1

TPA0+

L27

SKT-1394-4P-26-GP-U

SCD1U16V2ZY-2GP

2
0R0402-PAD

R318

C308

GUARD GND

C323
SC10U6D3V5KX-1GP

98
106
110
112

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

Reserve R547,R548,R550,R551 for co-layout

3D3V_PHY

U37A

SCD33U10V3KX-3GP

-1:09/11
1

CN8

3L28

SB:06/16 change 1394 CONN CN8


from 22.10218.M01 to
22.10218.T41.

TPB0-

R95
2
5K1R2F-2-GP
56R2J-4-GP 1394_TPB1_R
1
2
1
2 C192
R94
SC270P50V2JN-2GP
56R2J-4-GP

1
R92

DY

1
DLW21HN900SQ2LGP
1

R319

2
0R0402-PAD

SC:08/20 Change R95 from


64.51115.6DL to 64.51015.6DL.

-1:09/11
3D3V_CARD

SRN47J-5-GP

MDIO17

87

XD_DATA7

MDIO16

92

XD_DATA6

MDIO15

89

XD_DATA5

MDIO14

91

XD_DATA4

MDIO13

90

SD/XD/MS_DATA3

MDIO12

93

SD/XD/MS_DATA2

MDIO11

81

SD/XD/MS_DATA1

MDIO10

82

SD/XD/MS_DATA0

MDIO05

75

XD_WP#

MDIO08

88

SD/XD/MS_CMD

MDIO19

83

XD_ALE

MDIO18

85

XD_CLE

MDIO02

78

XD_CE#

MDIO03

77

SD_WP#(XDR/B#)

MDIO00

80

SD_CD#

MDIO01

79

MS_INS#

MDIO09

84

SD/XD/MS_CLK

MDIO04

76

MC_PWR_CTRL_0

MDIO06

74

MS_LED#

MDIO07

73

C271
SCD1U16V2ZY-2GP

1SD/XD/MS_DATA0_1
2SD/XD/MS_DATA1_1
3SD/XD/MS_DATA2_1
4SD/XD/MS_DATA3_1

RN71
XD_ALE
2
SD/XD/MS_CMD 1

3D3V_CARD

3
4

XD_ALE_1
SD/XD/MS_CMD_1

CARD1

23
14
33

SD_VCC
MS_VCC
XD_VCC

SD/XD/MS_DATA0_1
SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1
XD_DATA4_1
XD_DATA5_1
XD_DATA6_1
XD_DATA7_1

8
9
26
27
28
30
31
32

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

SD_WP#(XDR/B#)
SD/XD/MS_CLK_1
XD_CE#_1
XD_CLE_1
XD_ALE_1
SD/XD/MS_CMD_1
XD_WP#
XD_SW#

1
2
3
4
5
6
7
34

XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW

SRN33J-5-GP-U

XD_CE#
XD_CLE

2
1

3
4

XD_CE#_1
XD_CLE_1

SRN33J-5-GP-U

D19

SB:06/20 Rename U37 Pin79


from"XD/MS_CD#" to "MS_INS#"

MS_INS#

SD_CD#

SD/XD/MS_CLK_1

NP2
NP1

BAT54CPT-GP

SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

25
29
10
11

SD/XD/MS_DATA0_1
SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1

SD_CMD
SD_CLK
SD_CD_SW
SD_WP_SW

12
24
36
35

SD/XD/MS_CMD_1
SD/XD/MS_CLK_1
SD_CD#
SD_WP#(XDR/B#)

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

19
20
18
16

SD/XD/MS_DATA0_1
SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1

MS_BS
MS_INS
MS_SCLK

21
17
15

SD/XD/MS_CMD_1
MS_INS#
SD/XD/MS_CLK_1

NP2
NP1

4IN1_GND
4IN1_GND

13
22

GROUND
GROUND

38
37

33R2J-2-GP
TP82
TPAD30

R176
100KR2J-1-GP

CARD-PUSH-36P-1-GP-U1

SB:06/20 Remove U35,R148 and change D19 from


83.R0304.A8H to 83.R2003.E81.

RSV

SRN47J-5-GP

R175

97

C269
SC2D2U10V3ZY-1GP

RN45
SD/XD/MS_DATA08
SD/XD/MS_DATA17
SD/XD/MS_DATA26
SD/XD/MS_DATA35

RN72

DY
C261
SCD1U16V2ZY-2GP

GUARD GND

DY
C597
SCD1U16V2ZY-2GP

XD_DATA4_1
XD_DATA5_1
XD_DATA6_1
XD_DATA7_1

1
2
3
4

8
7
6
5

XD_DATA4
XD_DATA5
XD_DATA6
XD_DATA7

RN44

1
C315

R5C833-GP

For SD Card Power


3D3V_CARD

20mil

1
2
3

3D3V_S0

OUT
GND
SET

IN

ON#

<Core Design>

DY

SCD1U16V2ZY-2GP
C609

AAT4610AIGV-GP
R426
15KR2J-1-GP

R418
C601
10KR2J-3-GP
SC1U10V3ZY-6GP

SB:06/20 Remove R427 and change U57


pin4 connect to "MC_PWR_CTRL_0"
1

R426

U57

-1:08/29 Change R426


default from ASM to DY,
because change U57 main
source, it don't need
R426.

AAT4610AIGV
RT9711DPBG
G5240D2T1U

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

15K
DY

Title

DY

Size
A3

R5C832/IEEE1394/SD
Document Number

Date: Wednesday, September 12, 2007


A

Rev

DS2-Intel
Sheet
E

26

-1
of

47

R394

1.91K

49.9

49.9

49.9

49.9

0.01u

0.01u

4.7K

2K

DY

DY

DY

DY

DY

DY

Note:Default is 88E8040
1
WAKE#
PERST#
REFCLKP
REFCLKN

6
5
55
56

PCIE_TXN
PCIE_TXP

50
49

PCIE_RXN
PCIE_RXP

53
54

LED_LINK#
NC#62
LED_SPEED#
LED_ACT#

63
62
60
59

PCIE_WAKE# 21,28
PCIRST1# 19,25
CLK_PCIE_LAN 4
CLK_PCIE_LAN# 4
LAN_RXN1 C230 1
LAN_RXP1 C229 1

PCIE_TXN1 21
PCIE_TXP1 21

3D3V_LAN_S5
3D3V_LAN_S5

TPAD30

ACT_LED# 28
LANX1
LANX2

1
2
3
4

DY

MDI0+
MDI1+

R394 1

LAN10M_LED#

2
4K7R2J-2-GP
2
4K7R2J-2-GP

R393 1

MDI0+
EC160

DY
2

R50
100KR2J-1-GP

DY

DY

C563
LAN10M_LED# 28
C531

2
2

2 C528

SCD01U16V2KX-3GP
49D9R2F-GP
MDIS1_LAN
49D9R2F-GP

2 C544

SCD01U16V2KX-3GP
49D9R2F-GP

DY

2
SC1U6D3V2KX-GP

2
SCD1U10V2KX-4GP

2 C538
SC1000P50V2JN-GP

2 C557
SC1000P50V2JN-GP

2
SC1U6D3V2KX-GP

SA:04/23 Change C411 from


78.10523.5FL to 78.10520.5FL

C565

C561

C542

2
SC1U6D3V2KX-GP

2 C562
SC1000P50V2JN-GP

2
SC1U6D3V2KX-GP

2 C534
SC1000P50V2JN-GP

2
SC1U6D3V2KX-GP

2 C535
SC1000P50V2JN-GP

1
3

C256
SC4D7U6D3V5KX-3GP
SCD1U10V2KX-4GP

CTRL12

Q17
2SB772PT-1-GP 1D2V_LAN_S5

C592

8053:2.5V.
8055:1.8V.

SCD1U10V2KX-4GP

C590

2D5V_LAN_S5
C246

DY

DY
Q15
2SB772PT-1-GP

3
2

CTRL25

C593

DY

1
R417
4K7R2J-2-GP

DY

SCD1U10V2KX-4GP

R397
4K7R2J-2-GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

C259

8053:CTRL25.
8055:CTRL18.

DY

3D3V_LAN_S5

C560

SCD1U10V2KX-4GP
2
1

C241
SC10U6D3V5KX-1GP

AO3403-GP

1
2
3

SCD1U10V2KX-4GP
2
1

Q14

DY

MDIS0_LAN
49D9R2F-GP

PLACE PNP TO CHIP ACAP


CTRL12 PIN TRACE IS 25MIL

3D3V_LAN_S5

1
C543

C553

PLACE PNP TO CHIP ACAP


CTRL25 PIN TRACE IS 25MIL

2
0R3-0-U-GP

DY

DY

DY
2

1D2V_LAN_S5

2
SC1U6D3V2KX-GP

SA:04/23 Change C402,C408 from


78.10523.5FL to 78.10520.5FL

3D3V_S5

34 PM_LAN_ENABLE

SC1000P50V2JN-GP

SB:06/13

3D3V_LAN_S5

Q16
2N7002PT-U

LED_LINK#

MDI1-

DY

2D5V_LAN_S5

1
C539

R49
100KR2J-1-GP

R1

R2
PDTC124EU-1-GP

R139
10KR2J-3-GP

MDI1+

1
R357
1
R362
1
R372
1
R377

LAN100M_LED# 28

B
2

MDI0-

3D3V_LAN_S5

LAN100M_LED#
3D3V_LAN_S5

C239

DY

TPAD30

Q4

R137 1

R409
0R2J-2-GP

65

3D3V_LAN_S5

DY

R408
EEWP

VPD_CLK
VPD_DATA

2SB772PT

DY

EEWP
VPD_CLK
VPD_DATA

AT24C08AN-1-GP

C255
SC4D7U6D3V5KX-3GP

DY

0R2J-2-GP

Pull up for AT24C08 another pull low

Q17

4K7

8
7
6
5

DY

R406
4K7R2J-2-GP

88E8040

2SB772PT

VCC
WP
SCL
SDA

TP116

MDI0MDI1-

4K7

A0
A1
A2
GND

SC:08/09 Add
EC160(78.10234.1F1) for EMI
request .Default is DUMMY

R407
4K7R2J-2-GP

DY

LAN100M_LED#

DY

DY

2
2

15
14

XTALI
XTALO

TP75

1
1

LED_LINK#

88E8039

C209
SC12P50V2JN-3GP

PCIE_RXN1 21
PCIE_RXP1 21

R417

2 LANX1

XTAL-25MHZ-96GP
C210
SC12P50V2JN-3GP

SB:06/13 Change C209,C210 from 27P to 12P

2SCD1U10V2KX-4GP
2SCD1U10V2KX-4GP

3D3V_LAN_S5

Q15

DY

X2
LANX2 1

SA:4/30

R397

R121
1
2
10MR2J-L-GP

33
39
44
48
58
2
7
13

88E8040

SC1000P50V2JN-GP

28 MDI0+
28 MDI1+

DY

28 MDI028 MDI1-

88E8039

GND

RXN
TXN
NC#27
NC#31
18
21
27
31

88E8039-A0-GP
3

C544

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD25
AVDD

HSDACP
HSDACN

Marvell recommend:
2K Ohm(64.20015.6DL)

C528

U31

PU_VDDO_TTL#42
PU_VDDO_TTL#43

24
25

R377

SB:06/13

42
43

1LANHP
1LANHN

LOM_DISABLE#
VAUX_AVLBL
SWITCH_VCC
VMAIN_AVLBL
SWITCH_VAUX
RSET
CTRL12
CTRL25

TSTPT
TESTMODE

TPAD30 TP115
TPAD30 TP114

10
12
11
47
9
16
3
4

29
46

3D3V_S0

TPAD30
TP106 1LANSC
LANPWR
1 R395
2
0R0402-PAD
TP107
1LANSV
TPAD30
LANRSET
1
2
R354
2KR2F-3-GP CTRL12
CTRL25

NC#36
NC#37

VPD_DATA
VPD_CLK

3D3V_LAN_S5 LOM_DISABLE#

36
37

41
38

R358

NC#34
NC#35

RXP
TXP
NC#26
NC#30

17
20
26
30

2
4K7R2J-2-GP

R372

3D3V_LAN_S5

34
35

64
23

1
8
40
45
61
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

57
52
51
32
28
22
19
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL

R362

3D3V_LAN_S5
1D2V_LAN_S5

U25

R357

2D5V_LAN_S5

R354

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN MARVELL
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

-1
Sheet
E

27

of

47

RJ45 Connector
2D5V_LAN_S5

10/100M Lan Transformer


XF1

27 MDI1+

RJ45-3

16

RN8
RJ45-1
RJ45-2
RJ45-3
RJ45-6

27 MDI0+

15
14

RJ45-6

10

RJ45-1

XFR_RXC

LAN100M_LED#

SRN0J-5-GP

EC17
SC1KP50V2KX-1GP

A1
A2

330R2J-3-GP
ACT_LED# 27

PM_SLP_S3# 21,34,43,45,46

1
2

1
2

C611
SCD1U16V2ZY-2GP

C620
SCD1U16V2ZY-2GP
NEW1

31
NP1
1
TPAD30 TP144

4 NEWCARD_CLKREQ#

CPPE#
NEWCARD_CLKREQ#

3
5
7
9
11
13
15
17
19
21
23
25
27
29
NP2
32

3D3V_NEW_S0

20
8
9
10
6

21,29,30 SMB_DATA
21,29,30 SMB_CLK
PM_SLP_S4# 21,34,40,44,45
RN73
4
3

PERST#
CPUSB#
CPPE#
NRST

Use Card and No Card

15
17
11
12
3
2

1
2

SRN100KJ-6-GP

2
R435

PLTRST#
1
0R2J-2-GP

PCIE_RXP5 21
PCIE_RXN5 21
CLK_PCIE_NEW
CLK_PCIE_NEW#

PLT_RST1# 8,19,23,24,29,30,34

TPS2231RGP-GP

2
SC22P50V2JN-4GP

2nd: 74.02231.A73

1D5V_S0

SB:07/04 For EMI request

EC145

EC144

DY

1
C626

DY

3D3V_S0

+1.5V_CARD Max. 650mA, Average 500mA.


+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA

C624

SCD1U16V2ZY-2GP

C621

<Core Design>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN connector/NEW CARD/SIM


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

USB_PP8 21
USB_PN8 21

3D3V_S0
3D3V_NEW_S0

4
4

CPUSB#

FOX-CONN30A-9GP

3D3V_S5
1D5V_NEW_S0

1CONN_TP2
1CONN_TP3

3D3V_S5

DY
3D3V_NEW_LAN_S5

TPAD30 TP137
TPAD30 TP138

PCIE_TXP5 21
PCIE_TXN5 21

Test circuit

DY

4
6
8
10
12
14
16
18
20
22
24
26
28
30

+1.5VVIN
+1.5VOUT
+3VOUT
+3VIN

SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#

SC4D7U6D3V5KX-3GP

NC#16
NC#14
NC#13
NC#5
NC#4

1D5V_NEW_S0

AUXOUT
AUXIN
1.5VOUT
1.5VIN
3.3VOUT
3.3VIN

16
14
13
5
4

3D3V_NEW_LAN_S5
21,27 PCIE_WAKE#

GND

THERMAL_PAD
OC#
RCLKEN
STBY#

21
19
18
1

PERST#
U58

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C610

SC5P50V2CN-2GP

TPAD30

C612

3D3V_NEW_LAN_S5

SC5P50V2CN-2GP
2

1D5V_NEW_S0

SC10U6D3V5KX-1GP

NEWCARD_OC#

C613
SC10U6D3V5KX-1GP

1
TP143

C318

1D5V_S0
1D5V_NEW_S0
3D3V_NEW_S0
3D3V_S0

RJ45-6_L
RJ45-7

Green : Link up
Blinking : TX/RX activity

2
SC1500P2KV8KX-3GP

3D3V_NEW_S0

SCD1U16V2ZY-2GP

-1:09/01 Change R43,R47 from


63.47134.1DL to 63.33134.1DL

Place them Near to Connector

1
2

C617

5
6
7
8

4
3
2
1

1
2

DY

LAN100M_LED# 27

RJ45-1_L
RJ45-2_L
RJ45-3_L
RJ45-4

Place them Near to Chip

DY

2 330R2J-3-GP

RJ45+RJ11-5GP

NEWCARD Connector
1D5V_S0

LAN10M_LED# 27
R47

A3
RJ45_1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
B1
R43
B2
10

EC11
SC1KP50V2KX-1GP

DY

RN7
SRN75J-1-GP

LAN_TERMINAL 1
C416

3D3V_S5

SA:04/23 change CN13 pin3,4 net


name from "GND" to NC

9
RJ11_1
RJ11_2

ACT_LED#

XFORM-257-GP

C392
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C401

3
MLX-CON2-9-GP-U

RJ45-2
XFR_CMT

9
11
12
13

3D3V_LAN_S5

RJ45-7
RJ45-4

8
6
4
5

4
2

RJ1

DY

27 MDI0-

CN7

8 RJ45-1_L
7 RJ45-2_L
6 RJ45-3_L
5 RJ45-6_L

1
2
3
4

27 MDI1-

2
3

1.route on bottom as differential pairs.


2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

-1
Sheet
E

28

of

47

Mini Card Connector 1(802.11a/b/g)


SB:06/22 Change MINI1,2,3 slot from
62.10043.431 to 62.10043.551(only
modify properties)

MINI1
1D5V_S0

3D3V_S0

53
NP1
1MINI_2_WAKE# 1

TP142
TPAD30

2
30,31 WLAN_ACT

30 BT_ACT

4
6

TP141
TPAD30

7
8
9
10

4 CLK_PCIE_MINI1#

11

4 CLK_PCIE_MINI1

13

12
14
15
16
17
18

19
20

WIFI_RF_EN

21

PLT_RST1#

22
23

21 PCIE_RXN2

24

PLT_RST1# 8,19,23,24,28,30,34

3D3V_S0

25

21 PCIE_RXP2

34

26
27
28
29

21 PCIE_TXN2

31

21 PCIE_TXP2

33

30

SMB_CLK

32

SMB_DATA

SMB_CLK 21,28,30
SMB_DATA 21,28,30

34
35
36
37
38
39

3D3V_S0

40
41
42

43

TP131TPAD30

44

WLAN_LED 35

45
46

47

TP132TPAD30

48
49

R432
5V_S5

DY

50
2
0R3-0-U-GP

51
52
NP2
54

SKT-MINI52P-18-GP

Main Source:62.10043.431
2nd Source: 20.F0992.052

3D3V_S0

5V_S5

3D3V_S0

1D5V_S0
WLAN_ACT

-1:0909

<Core Design>

SC10U6D3V5KX-1GP

C603
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP

DY

C275

DY

DY

C284 SCD1U16V2ZY-2GP
C291

C604
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C616

DY

Wistron Corporation

EC175
SC220P50V2KX-3GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI CARD CONN 1


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

-1

Sheet
E

29

of

47

Mini Card Connector


Mini Card Connector 2(WWAN)
TP80
TPAD30

Mini Card Connector 3(Robson)


SB:06/22 Change MINI1,2,3 slot from
62.10043.431 to 62.10043.551(only
modify properties)

MINI2
1D5V_S0

3D3V_S0

53

NP1
MINI_WAKE# 1

MINI3

1D5V_S0

3D3V_S0

53

3D3V_S0

UIM_DATA

12

UIM_CLK

14

UIM_RESET

16

UIM_VPP

13
15

TP81
TPAD30

UIM_CLK 35

WWAN_RF_EN
PLT_RST1#

22
24

11

4 CLK_PCIE_MINI3

13

34 E51_RXD

R431 1

2 0R2J-2-GP E51_RXD_R17

34 E51_TXD

R428 1

2 0R2J-2-GP E51_TXD_R 19

21 PCIE_RXN4

USB_PN4 21

21 PCIE_TXN4

31

38

USB_PP4 21

21 PCIE_TXP4

33

-1:0905 Add C637,C638 for SIM


CLK and DATA.

42

44

49

R429
UIM_CLK

DY

50
2
0R3-0-U-GP

52
NP2
54

3D3V_S0

5V_S5

3D3V_S0

C615

C289

DY

1
2

C607

SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP

Place TC35 near MINI 2

SCD1U16V2ZY-2GP
C285

DY

SC10U6D3V5KX-1GP

1D5V_S0

C286

DY

C605

3D3V_S0

DY

SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP

C608

C606
SCD1U16V2ZY-2GP

DY
Place C451 near MINI 3 pin24

SCD1U16V2ZY-2GP

1
2

1
2

DY

C602

SCD01U16V2KX-3GP
2

ST220U6D3VDM-13GP

1
2

DY

C287

SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

5V_S5

C277

Main Source:62.10043.431
2nd Source: 20.F0992.052

SKT-MINI52P-18-GP

SC33P50V2JN-3GP

SC33P50V2JN-3GP

C638

1D5V_S0

51

5V_S5

C637

C274

BT_ACT_WPAN# 35

48

UIM_DATA

3D3V_S0

TP135TPAD30

46
47

NP2

SC:08/11 Add R192,R194


pull low resistor for
bluetooth active signal
to

TP136TPAD30

45

52

R194

40
43

50

C614

2
USB_PP9 21

R192

41

TP130TPAD30

Main Source:62.10043.431
2nd Source: 20.F0992.052

USB_PN9 21

38
39

3D3V_S0

TP133TPAD30

54

36

51

TC5

SMB_DATA 21,28,29

46

SKT-MINI52P-18-GP

SMB_DATA

44

48

DY

32

SMB_CLK 21,28,29

37

TP134TPAD30

49

SMB_CLK

47

2
0R3-0-U-GP

BT_ACT_2

30

WWAN_LED

45

DY

BT_ACT_1

35

42

R160
100KR2J-1-GP

34

40

R430

BT_ACT 29

PLT_RST1# 8,19,23,24,28,29,34

28

36

43

3D3V_S0

29

41

5V_S5

26

34

39

GND

27

35

3D3V_S0

BLUETOOTH_EN 31,34
PLT_RST1#

25

21 PCIE_RXP4

SMB_CLK 21,28,29

37

18

24

SMB_DATA 21,28,29

33

21 PCIE_TXP3

0R2J-2-GP

VCC

DY

22

SMB_DATA

0R2J-2-GP

74LVC1G32GW-1GP

20
23

SMB_CLK

16

21

32

14

28
30

15

26

31

34

PLT_RST1# 8,19,23,24,28,29,34

3D3V_S0

29

12

27

21 PCIE_TXN3

BT_ACT_2

31 BT_ACT_1

25

4 CLK_PCIE_MINI3#

DY
DY
U62

SC:07/30 Add "WWAN_RF_EN" GPIO pin


connect to MINI2 pin20

20
23

7
10

UIM_VPP 35

19

21 PCIE_RXP3

18

21 PCIE_RXN3

UIM_RESET 35

17

21

1
R155
1
R161

4 CLK_PCIE_MINI2

BT_ACT_2

UIM_DATA 35

10

9
11

4 CLK_PCIE_MINI2#

SC:08/09 Delete D21,add


U62(73.01G32.AHH) to replace D21

2
3

29,31 WLAN_ACT

UIM_PWR 35

100KR2J-1-GP

UIM_PWR

NP1
MINI_WAKE# 1

TP140
TPAD30

6
1

100KR2J-1-GP

4
5
TP139
TPAD30

SB:06/22 Change MINI1,2,3 slot from


62.10043.431 to 62.10043.551(only
modify properties)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI CARD CONN 2 & 3


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

-1

Sheet
E

30

of

47

-1:0910

3D3V_S5

3D3V_AUX_S5

4
3
2
1

OUT
VS
GND
GND

SNIFFER1

7
1

34 WLAN/BT_BTN#

2
3
4
5
6

34 SNIFFER_PWR_SW#

TSOP36136-GP

34 SNIFFER_YELLOW#
34 SNIFFER_BLUE#
5V_S5

SC4D7U6D3V5KX-3GP

C332

FRIEE_CIRRX
SIO_CIRRX_VS

SC:07/26 Rename
"SNIFFER_BD1" to
"SNIFFER1"

R458
100KR2J-1-GP

R181

100R2J-2-GP

SCD1U10V2KX-4GP
C333

34 CIRRX

3D3V_S5

U61

R182
10KR2J-3-GP

SC:08/12 Add R458


(63.10434.1DL) pull up for
"WLAN/BT_BTN#. Because
sniffer is option feaature.

C578
SCD1U10V2KX-4GP

R205
10KR2J-3-GP

CIR

3D3V_AUX_S5

DY

8
MLX-CON6-11-GP

MDC1

MH1
14
15
2

SNIFFER_BLUE#

HDA_BITCLK 20,23,32

C432

Main Source:20.F0677.012
2nd Source: 20.F0676.012

R265

EC110

DY

SC220P50V2KX-3GP

0R2J-2-GP

EC111

DY

SC220P50V2KX-3GP

EC115

DY

SC220P50V2KX-3GP

ICH_ACZ_MDC_BITCLK

SC220P50V2KX-3GP

R343

AMP-CONN12A-1GP

C204
SC22P50V2JN-4GP

DY

Bluetooth Module conn.

SNIFFER_YELLOW#

1
2

3D3V_S5

C428
SC22P50V2JN-4GP

EC114

DY

4
6
8
10
12
18
17
MH2

1
2 ACSDATAIN1_A
R266 39R2J-L-GP

SNIFFER_PWR_SW#

100KR2J-1-GP

3
5
7
9
11
16

20,23,32 ICH_SDOUT_CODEC
20,23,32 ICH_AZ_CODEC_SYNC
20 ICH_SDIN_MDC
20 ICH_AZ_MDC_RST#

WLAN/BT_BTN#

SC4D7U6D3V5KX-3GP
2
1

13
1

BT1

11
1
2
3
4
5
6
7
8
9
10

21 USB_PP5
21 USB_PN5
30 BT_ACT_1
30,34 BLUETOOTH_EN
29,30 WLAN_ACT

3D3V_S0

BT_LED

12

C424

SCD1U10V2KX-4GP

R259
10KR2J-3-GP

FOX-CON10-GP

20.F0711.010

BT_ACT_1

BLUETOOTH_EN

USB_PP5

USB_PN5

EC173

SC:08/14 Add
EC173(78.22034.1FL) on
"USB_PP5" for
EMI team request.

EC174

DY
2

DY

SC22P50V2JN-4GP

1
EC62

DY

SC22P50V2JN-4GP

SC:08/14 Add
EC172(78.22124.2FL) on
"BT_ACT1" for
EMI team request.

SC220P50V2KX-3GP

EC172

DY

SC220P50V2KX-3GP

R2
PDTC124EU-1-GP
R258
10KR2J-3-GP

R1

Q28
35 BT_ACT_K#

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SC:08/14 Add
EC174(78.22034.1FL) on
"USB_PN5" for
EMI team request.

Title

MDC&RJ11 CONN
Size
A3

Document Number

Date: Wednesday, September 12, 2007


5

Rev

DS2-Intel
Sheet
1

31

-1
of

47

+VDDA

60ohm 100MHz
3000mA 0.05ohm DC
R421
5K1R2F-2-GP

2
1
2

AVDD1
AVDD2
SENSE_A
SENSE_B

13
34

PORT_A_L
PORT_A_R
VREFOUT_A

39
41
37

PORT_B_L
PORT_B_R
VREFOUT_B

21
22
28

PORT_C_L
PORT_C_R
VREFOUT_C

23
24
29

PORT_D_L
PORT_D_R
VREFOUT_D

35
36
32

AUD_LINE_OUT_L
AUD_LINE_OUT_R

PORTE_L
PORTE_R
VREFOUT_E

14
15
31

AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_E

PORTF_L
PORTF_R
VREFOUT_F

16
17
30

PORTG_L
PORTG_R

43
44

PORTH_L
PORTH_R

45
46

CD_L
CD_GND
CD_R

18
19
20

PC_BEEP

12

CAP2
VREFFILT

33
27

AVSS1
AVSS2

26
42

DVDD_CORE
DVDD_CORE
DVDD

1
SC1KP50V2KX-1GP

R154
5K1R2F-2-GP

SDATA_OUT

20,23,31 ICH_AZ_CODEC_SYNC

10

SYNC

20 ICH_AZ_CODEC_RST#

11

RESET#

3D3V_S0

U34

AUD_DMIC_CLK_G

VCC

1
2
3

OE#
A
GND

74LVC1G125DC-GP

2
R149

SB: Change R149 from

AUD_DMIC_CLK

1
33R2J-2-GP

63.R0034.1DL to 63.33034.1DL
AUD_DMIC_IN0

18 AUD_DMIC_IN0
R455

35 SPDIF_D

VOLUME UP/DMIC_0/GPIO1
VOLUME DN/DMIC_1/GPIO2

47
48

SPDIF_IN/GPIO0/DMIC_CLK
SPDIF_OUT

1 200R2F-L-GP
AUD_DMIC_CLK

AUD_SPDIF_OUT

23 AUD_SPDIF_OUT

2
3

EXT_MIC_JD#

A---> HP1
E---> Ext Mic
D---> Speaker
F---> HP2
C--->Int Mic

PC BEEP
AUD_PC_BEEP

C299

71.09228.00G

SB:07/02 Change EC36 from ASM to DUMMY

From SB

R141

1AUD_BEEP
C267
SCD1U10V2KX-4GP
2

AUD_CAP2
AUD_VREFFLT

1
2

STAC9228X5TAEA2-GP

R157 1
39K2R2F-L-GP

SB_SPKR 21

47KR2F-GP

C300

R412

R413
1
2
47KR2F-GP

KBC_BEEP 34

From EC
2

SA:0428

Internal Microphone

SB:06/26 Add
EC129(78.22034.1FL) by EMI
request

Azalia I/F EMI

-1:09/06 Change Int. MIC from


23.42132.001 to 23.42143.001

MIC IN

Azalia I/F EMI

ICH_SDOUT_CODEC

CN4

ICH_AZ_CODEC_BITCLK

INT_MIC

MIC1

1
2
2
0R3-0-U-GP
2
0R3-0-U-GP

MIC_IN_L_C

MIC_IN_R_C

SB:07/02 Change R168 from 63.R0034.1DL to 63.00000.00L

600ohm 100MHz
200mA 0.5ohm DC

C265
SCD1U10V2KX-4GP

EC49
SC100P50V2JN-3GP

1
R169
1
R168

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5
7
8
9
10

Title

AUDIO CODEC STAC9228


AUDIO-JK89-GP-U

DY

Size
A3

Document Number

Date: Wednesday, September 12, 2007


A

MICROPHONE-40-GP-U

EXT_MIC_JD#

C302
SC1U10V3KX-3GP

EC48
SC100P50V2JN-3GP
2
1

AUD_EXT_MIC_R

MIC_IN_L_2
2 C306
SC1U10V3KX-3GP
MIC_IN_R_2
2 C307
SC1U10V3KX-3GP

1
1

1
2
AUD_EXT_MIC_L

R163
4K7R2J-2-GP

2
1

DY

2
1
2

C263
SCD1U10V2KX-4GP

ICH_AZ_CODEC_BITCLK1

ICH_AZ_CODEC_SDOUT1

DY

R162
4K7R2J-2-GP

R144
47R2J-2-GP

DY

EC52
SC1KP50V2KX-1GP

AUD_VREFOUT_E

R145
47R2J-2-GP

33

Port
Port
Port
Port
Port

AUD_HP2_OUT_L 33
AUD_HP2_OUT_R 33

10KR2J-3-GP

EC36
SC22P50V2JN-4GP

AUD_HP2_JD#

AUD_LINE_OUT_L 33
AUD_LINE_OUT_R 33

SC10U10V5KX-2GP

DY

2SC1U10V3KX-3GP
R1531
2
4K7R2J-2-GP

SC10U10V5KX-2GP

EC129
SC22P50V2JN-4GP

INT_MIC

R158 1
20KR2J-L2-GP

TO Audio OP

ICH_AZ_CODEC_BITCLK

AUD_DMIC_CLK_G

DVSS1
DVSS2

2SC1U10V3KX-3GP

4
7

C292 1
AUD_INT_MIC_L
AUD_INT_MIC_R C294 1
AUD_VREFOUT_B

18 AUD_DMIC_CLK_G

DY

AUD_HP1_OUT_L 33
AUD_HP1_OUT_R 33

SDATA_IN

20,23,31 ICH_SDOUT_CODEC

BIT_CLK

AUD_HP1_OUT_L
AUD_HP1_OUT_R

20 ICH_SDIN_CODEC

33

+VDDA
AUD_SENSE_A
AUD_SENSE_B

20,23,31 HDA_BITCLK

AUD_HP1_JD#

TO Audio OP
ICH_AZ_CODEC_BITCLK
6
0R2J-2-GP
SB_AZ_CODEC_SDIN0_R 8
2
1
R146
33R2J-2-GP
5

1
R344

C298

SB:07/10 Change R344 from 33 Ohm to 0 Ohm

1+3V_RUN_DVDD_CORE3
100KR2J-1-GP

25
38

R420 1
39K2R2F-L-GP

R152 2

C296
SC1U10V3KX-3GP

1
2
U36

1
9
40

C320
SCD1U10V2KX-4GP

C270
SC1U6D3V2KX-GP

1
2

1
2
4

C276
SCD1U10V2KX-4GP

+VDDA

C266
SCD1U10V2KX-4GP

3D3V_S0

Rev

-1

DS2-Intel
Sheet
E

32

of

47

3D3V_S0

Main source: TPA6040A

5V_S0

1
1

C619
SC1U10V3KX-3GP

C628
SCD033U16V3KX-GP

SC:08/13 Change R441pin1


connection
from"AMP_MUTE#" to 5V_S0

0R0603-PAD
0R0603-PAD
0R0603-PAD
0R0603-PAD

AUD_SPK_L2_R
AUD_SPK_L1_R
AUD_SPK_R2_R
AUD_SPK_R1_R

No ASM

2AUD_CPVSS
SC1U10V3KX-3GP

2nd source: MAX9789A

0 Ohm

DY

MLX-CON4-15-GP

LINE1 OUT

74.06040.013
74.09789.013

AUD_HP2_EN
AUD_HP2_JACK_L
AUD_HP2_JACK_R

3D3V_S0

LOUT1

0 Ohm
1

MAX4411ETP-1-GP

10dB

15.6dB

21.6dB

AUD_HP2_JD# 2

3AUD_SPK_ENABLE
NB_SPK_EN#

AUD_SPK_ENABLE#

AMP_MUTE#

BAW56PT-U
2N7002SPT

AUD_HP1_EN

600ohm 100MHz
200mA 0.5ohm DC
5V_S0

R457
10MR2J-L-GP

R166
33KR2J-3-GP
U39

SC:08/11 Delete Q18, Add


U64 circuit for Speaker

AUD_HP2_JD

AUD_HP2_JD#

AMP_MUTE#

AUD_HP2_JD

AUD_HP2_EN

2N7002SPT

EC51
SC100P50V2JN-3GP

DY

AUD_HP2_JACK_L2

AUD_HP2_JACK_R2

3
4

AUD_HP1_JD

2
L9
BLM18BD601SN1D-GP
AUD_HP2_JACK_R
1
2
L8
BLM18BD601SN1D-GP

DY

2
AMP_MUTE#

2
3

OUTL
OUTR
2

2N7002SPT

EC50
SC100P50V2JN-3GP

9
11

14
18

EC47
SC100P50V2JN-3GP

AUD_HP1_JD# 1

AUD_HP1_JD#

AUD_HP2_JD#

32 AUD_HP2_JD#
AUD_HP2_JACK_L

SA:4/28

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AUDIO AMP/SPEAKER
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007


B

AUDIO-JK89-GP-U

<Core Design>

R165
10MR2J-L-GP

5
7
8
9
10

6dB

GAIN

AUD_HP1_JD

LOUT2

GAIN2

U64

SC:08/11 Delete
Q19, Add U63,R457
circuit for HP1

R159
100KR2J-1-GP

D22

GAIN1

U63

R459
100KR2J-1-GP

AUDIO-JK89-GP-U

EC46
SC100P50V2JN-3GP

5V_S0

5V_S0

R172
100KR2J-1-GP

DY

+VDDA
R436
100KR2J-1-GP

SA:4/28

R167
100KR2J-1-GP

AUD_AMP_GAIN2

R433
100KR2J-1-GP

DY

5
7
8
9
10

5V_S0

SC:08/12 Add R459


(63.10434.1DL) pull up
for U64 pin4 "NB_SPK_EN".

AUD_AMP_GAIN1

Signal inverter for speaker shutdown

R439
100KR2J-1-GP

1
2

R434
100KR2J-1-GP

SC2D2U6D3V3KX-GP

LINE2 OUT

This pin should be FLOAT.


Do NOT connect to GND.

AUD_PVSS

AUD_HP1_JACK_R1

DY

C304
1
2

DY

2nd source: MAX4411EPT+ 74.04411.A13

5V_S0
2

600ohm 100MHz
200mA 0.5ohm DC

74.04411.AE3

Main source: TPA4411MRTJ

4
6
8
12
16
20

AUD_HP1_JACK_L1

INL
INR

SB:70213

GAIN SETTING

SHDNR#
SHDNL#

2
13
15

2
L10
BLM18BD601SN1D-GP
AUD_HP1_JACK_R
1
2
L11
BLM18BD601SN1D-GP

NC#4
NC#6
NC#8
NC#12
NC#16
NC#20

SGND
PGND

1
C305 1
C301

C1P
C1N

GND

AUD_HP2_OUT_L
AUD_HP2_OUT_R

SC2D2U6D3V3KX-GP
AUD_HP2_OUT_L2
2
AUD_HP2_OUT_R2
2 SC10U10V5KX-2GP
SC10U10V5KX-2GP

1
3

AUD_HP1_JD#

32 AUD_HP1_JD#
AUD_HP1_JACK_L

17
2

32 AUD_HP2_OUT_L
32 AUD_HP2_OUT_R

AMP2_C1P

21

AMP2_C1N

No ASM

C295
1
2

SVSS

0.33uF

-1:0909

C628

No ASM

SVDD
PVDD

0.33uF

U38

PVSS

C631

C313
SC1U6D3V2KX-GP

100K

No ASM

10
19

No ASM

R441

1
2
3
4

DY

2
2
2
2

EC8
SC100P50V2JN-3GP

AMP_MUTE# 34

DY

R441 2
1
100KR2J-1-GP

DY

1
1
1
1

EC6
SC100P50V2JN-3GP
2
1

From EC

1 0R2J-2-GP

R11
R14
R13
R10

DY

5V_S0

+VDDA

C321
SC1U10V3KX-3GP

AUD_SPK_L2
AUD_SPK_L1
AUD_SPK_R2
AUD_SPK_R1

AUD_LINE_OUT_R 32
AUD_LINE_OUT_L 32

EC9
SC100P50V2JN-3GP
2
1

2
2SCD033U16V3KX-GP
SCD033U16V3KX-GP

No ASM
1
C316

R440

C311
SC1U10V3KX-3GP

1
2

1
2

R440

C631
SCD033U16V3KX-GP

DY
MAX9789A-GP

PVSS
14

CPVSS

CPGND
11

21
5

13

HP_INR
HP_INL

MAX9789A

R171

1
C630 1
C629

AUD_SPK_ENABLE#
AMP_MUTE#_R
R171 2
AUD_HP1_EN
DY
AMP_REGEN
AMP_C1P
1
2
AMP_C1N
C317
SC1U10V3KX-3GP
AUD_BIAS
AUD_SET

0R2J-2-GP

100K

R156

SPK1

23
25
22
4
10
12
29
24
1

SC:08/11 Change SPK1 pin define that


follow ME request

SPKR_EN#
MUTE#
HP_EN
REGEN
C1P
C1N
VOUT
BIAS
SET

60ohm 100MHz
3000mA 0.05ohm DC

EC7
SC100P50V2JN-3GP
2
1

2
3

C618
SC1U6D3V2KX-GP

1
2

SC10U6D3V5KX-1GP

AUD_LIN_R
AUD_LIN_L

SPKR_INR
SPKR_INL

Default
TPA6040A

C627
SCD1U10V2KX-4GP

C328
SC1U10V3KX-3GP
2
1

17

30

18

GAIN1
GAIN2

GND
GND

AUD_HP1_OUT_R126
2
2SC10U10V5KX-2GPAUD_HP1_OUT_L1 27
SC10U10V5KX-2GP

1
C309 1
C310

C622

R156 2
1
100KR2J-1-GP

PGND
PGND

31
32

U59

VDD

HPR
HPL

HPVDD

15
16

CPVDD

AUD_HP1_JACK_R
AUD_HP1_JACK_L

PVDD

OUTL+
OUTLOUTROUTR+

PVDD

6
7
19
20

AUD_AMP_GAIN1
AUD_AMP_GAIN2

Close to U30.9

32 AUD_HP1_OUT_R
32 AUD_HP1_OUT_L

AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R2
AUD_SPK_R1

C314
SC1U6D3V2KX-GP

3D3V_S0

28
33

C322
SC1U10V3KX-3GP

Close to U37.8

Speaker

3D3V_S0
5V_S0

60ohm 100MHz
3000mA 0.05ohm DC

5V_S0

C623
SCD1U10V2KX-4GP

C327
SC10U10V5KX-2GP

Close to U27.18

Sheet
E

33

of

47

20 LPC_LAD[0..3]

TP60
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

TP61

PLACE CAP NEAR PIN46,19,115,76,88,104


TP52
ECRST#

TPAD30

TP50

LCD_TST_EN
CLKOUT

25 GBRST#_KBC

SHBM PIPN83 Shared Host BIOS Memory.

SC:08/03 Change Pin27 from"BLON_OUT" to"


LCD_TST_EN", delete TP45 test pad.

HIGH:NO SHARED(internal resistor)


LOW:SHARED BIOS memory.
R98

2 BLUETOOTH_EN
4K7R2J-2-GP
WPC8763LDG-1-GP

SB:06/27 Change R98 from 63.10334.1DL to


63.47234.1DL
.

1D05V_S0

TPAD30

LRESET#
LFRAME#
ECSCI#

7
3
29

75
83
110
111
112
GPO72
GPO76/SHBM
GPO82/HGPO00/TRIS#
GPO83/SOUT_CR/BADDR1
GPO84/HGPO01/BADDR0

101
105

106
107
GPI96
GPI97

GPI94/DA0
GPI95/DA1

97
98
99
100
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3

126
127
128
1
LAD0
LAD1
LAD2
LAD3

85

86
87
92
90

SDA1
SCL1

69
70

BAT_SDA 18,38,39
BAT_SCL 18,38,39

PSDAT1
PSCLK1

71
72

TPDATA 37
TPCLK 37

10KR2J-3-GP
R88 2
TPAD28
TPAD28
DY
TPAD28
TPAD28

TP44
TP49

TPAD28
TPAD28

KCOL[0..16]

C
SPIDI 35
SPIDO 35
SPICLK 35
SPICS# 35

<-----BATTERY

1
R103

1
2

RN21

DY

2
C183
SCD1U16V2ZY-2GP

3D3V_AUX_S5

FOR Thermal AND


Capacity Button Module

R323 1

SNIFFER_PWR_SW#
2
100KR2J-1-GP

R101 1

LID_CLOSE#
2
10KR2J-3-GP

R443 1

LCD_CBL_DET#
2
10KR2J-3-GP

R447 1

KB_DET#
2
10KR2J-3-GP

R448 1

DMIC_DET#
2
10KR2J-3-GP

ACDC_ID:from Adapter Conn


U54
36 G792_SDA

KBC_PWRBTN#:from power button

KBC_SDA1

DC_BATFULL#:for Battery charge LED 1


6

G792_SCL 36

2
0R2J-2-GP

WLAN_TEST:for WKS test WLAN LED


CAP_SCL 37

AD_OFF:enable AC adapter power source


S5_ENABLE

CHARGE_LED#:for Battery charge LED 2

1
ECSWI#_KBC

WIRELESS_EN:Disable/Enable Wireless Module

ECRST#

3D3V_AUX_S5

BLUETOOTH_EN:Disable/Enable Bluetooth

21 ECSCI#

1
ECSCI#_KBC

1
2

C507

BAS16-1-GP
<Core Design>

Wistron Corporation

D16

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

1
3

DY

21 ECSMI#

C519
SC4D7P50V2CN-1GP

1
3

ECSMI#_KBC

Title

KBC_Winbond WPC8763L

2
Size
A2

BAS16-1-GP

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

ECRST#_C B

4
3

SRN10KJ-5-GP

1
2
1
2

1
2

36,46 PURE_HW_SHUTDOWN#

AC_IN#:From Charge

PCLK_KBC
R340
0R2J-2-GP

DY

X-32D768KHZ-40GPU

CCD_ON:Webcam power on/off


D29

C516
SC1U10V3KX-3GP

KBC_XI

10MR2J-L-GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

Q30
CH3906PT-GP

RN58

BAS16-1-GP

KBC CLK EMI

X5

2
10KR2J-3-GP

GMCH_BL_ON:Sense The Backlight On/Off Status from VGA Chip

D30
21 ECSWI#

-1:0912
KBC_XO_R

R331
1

WLAN/BT_BTN#:from Wlan on/off button

PCLK_KBC_RC

R330
33KR2J-3-GP

C510

10MR2J-L-GP

BAT_IN#:from Battery Conn

R322

R451
KBC_XI_R

KBC_PWRBTN#
INSTEAD_BTN#

R106 1

2 0R2J-2-GP

2N7002SPT

VER1
0
1
0
1

KBC_XO

R326

4
3

SRN10KJ-5-GP

2
1
2

SRN10KJ-6-GP
RN60
1
2

USB_PWR_EN#:to on/off USB power switch

KBC_SCL1
KBC_SDA1
BAT_SDA
BAT_SCL

WPC8763L XTAL

8
7
6
5

1
2
1

SA
SB
SC
-1

1
2
3
4

EC32

KBRCIN#

KBC_SCL1

10KR2J-3-GP
R338

R339
10KR2J-3-GP

10KR2J-3-GP
R335

DY

KA20GATE
KBRCIN#

4
3

3D3V_AUX_S5

KBC_XI
KBC_XO

KA20GATE

MB VERSION ID
VER0
0
0
1
1

E51_RxD

SRN10KJ-5-GP

ADIA:to Charger

PCB_VER0
PCB_VER1

2
10KR2J-3-GP

RN59

3D3V_S0

37 CAP_SDA

R337
10KR2J-3-GP

DY

KBC_THERMTRIP#

3D3V_S0

MB VERSION ID

37

KBC DEBUG POINT

E51_RxD

Q34
CH3904PT-GP

DY

VDD

ECSMI#_KBC

20 KA20GATE
21,25 INT_SERIRQ
20 KBRCIN#
4 PCLK_KBC

2
SCD1U16V2ZY-2GP

B
E

F_SDI
F_SDO
F_SCK
F_CS0#

TP47
TP42
TP48
TP43

KBC_BEEP 32

29 WIFI_RF_EN
33 AMP_MUTE#
30 E51_RxD
C632

5,8,20,46 H_THERMTRIP#

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15

21,28,40,44,45 PM_SLP_S4#
31 SNIFFER_YELLOW#
TPAD30 TP53
R442
2K2R2J-2-GP

TP56

KCOL17
TP51
KCOL16
TP46
KBC_SCL1
KBC_SDA1
ECSWI#_KBC
GPIO64

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35

37

3D3V_S0

VBAT
KBC_BEEP
VCORF

TPAD30
TPAD30

33
34
67
68
123
9
81
73
74
82
84
91
113

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT

KROW[0..7]

TP57

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

AGND

TPAD30

PLT_RST1# 8,19,23,24,28,29,30

103

38 PSID_DISABLE#
31 WLAN/BT_BTN#
18 LCD_TST_EN
10 GMCH_BL_ON

DY

54
55
56
57
58
59
60
61

GND
GND
GND
GND
GND
GND

-1: 08/29 change Pin24 from "WWAN_RF_EN"


to NC, because pin24 is H/W straping
pin. it has H/W concern.

CHARGE_LED

1 R336
0R2J-2-GP

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

5
18
45
78
89
116

SB:06/24 Change R104 from


63.10334.1DL to 63.47234.1DL.Base on
Winbond FAE recommend to fix system
will hang up after Thermal T8
shutdown

32KX2
32KX1/32KCLKIN

E51_TxD

R104
4K7R2J-2-GP

NUM_LED
CAP_LED

79
77

DY PIN 111

35 NUM_LED
35 CAP_LED
35 LED_MASK#
31 SNIFFER_BLUE#
18 LCD_TST
46 S5_ENABLE
21 RSMRST#_KBC
38 AD_OFF
27 PM_LAN_ENABLE
35 CHARGE_LED
37 CAPA_INT#
35 WLAN_LED_TEST

LCLK
VREF
VCORF
A_PWM0
RESERVED

R105
10KR2J-3-GP

2
104
44
32
80

-1:08/30 Change Pin11 from NC to be"HDD_5V_EN"

GPIO01
GPIO03
GPIO04
GPIO05
GPIO06/HGPIO06
GPIO07/HGPIO07
GPIO10/HGPIO00/LPCPD#
GPIO11/HGPIO02/CLKRUN#
GPIO12/PSDAT3
GPIO13/B_PWM0
GPIO14/HGPIO04/TB1
GPIO16/HGPIO04
GPIO20/TA2
GPIO21/A_PWM1
GPIO23
GPIO24/HGPIO01
GPIO26/PSCLK2
GPIO27/PSDAT2
GPIO25/PSCLK3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO36
GPIO40
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45
GPIO46/TRST#
GPO47/JEN0#
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO55/CLKOUT
GPIO56/TA1

GA20
SERIRQ
KBRST#

-1:08/30 Change Pin10 from NC to be"WWAN_RF_EN"

INSTEAD_BTN#

64
95
96
108
93
94
124
8
13
62
63
114
117
118
119
6
10
11
12
109
120
65
66
14
15
16
17
20
21
22
23
24
25
26
27
28
30
31

121
125
122

10K external pull-down


resistor on BADDR1: Core defined

KBC_PWRBTN#
KBC_THERMTRIP#

18 LCD_CBL_DET#
39 AC_IN#
35 LID_CLOSE#
35 INSTEAD_BTN#
21,25 PM_CLKRUN#
38 BAT_IN#
18 BRIGHTNESS
31 CIRRX
35 BATFULL_LED
38 ACDC_ID
35 PWRLED
21 PM_PWRBTN#
35 SCRLK_LED
30 WWAN_RF_EN
24 HDD_5V_EN
TPAD30 TP55

BADDR1-0 (PIN 111, 112) I/O Base Address.

3D3V_S0

102

1
21,28,43,45,46 PM_SLP_S3#
35 KBC_PWRBTN#

Forces the device to float all its output and I/O pins,if an
external 10 K pull-down resistor is conected.

D
2

C514

AVCC

10K PD

TRIS#(Pin 110) TRI-STATE

-1:08/29 Change U22 pin110 define from NC


to"USB_PWR_EN" or USB power control.

LPC_LFRAME# 20

ECSCI#_KBC

U22

31

PLT_RST1#_1

C517
SC10U6D3V5KX-1GP

VCC_POR#

NO PD

Keyboard Scan
Keyboard Scan
JTAG signals

46
19
115
76
88

GPIO Port
JTAG signals
GPIO Port

VCC
VCC
VCC
VCC
VCC

NO PD

Functionality of Pins
47, 48, 50, 51, 52

GPIO57/HGPIO03/KBSOUT17
GPIO60/KBSOUT16
GPIO61/SCL2
GPIO62/SDA2
GPIO63/PWUREQ#
GPIO64/SMI#
GPIO66/SWD
GPIO70
GPIO71
GPIO75
GPIO77
GPIO81
GPIO87/SIN_CR

10K PD

DMIC_DET# 18
TPAD28 SNIFFER_PWR_SW#

BLUETOOTH_EN 30,31
USB_PWR_EN# 35,38
E51_TxD 30
TP97 TPAD28

3D3V_S0

Functionality of Pins
17, 20, 21, 23 25, 27

NO PD RES

VBAT

1 R329
2
0R0603-PAD

JENK
(Pin 53)

USB_PWR_EN#
E51_TxD

SCD1U16V2ZY-2GP

D WPC8763L STRAP PIN

AD_IA 39
KB_DET# 37

3D3V_AUX_S5

TPAD28
TPAD30

PCB_VER0
PCB_VER1

SC470P50V2KX-3GP

C504

SCD1U16V2ZY-2GP

C512

SCD1U16V2ZY-2GP
2
1

C505

SCD1U16V2ZY-2GP
2
1

1
2

C515

SCD1U16V2ZY-2GP
2
1

1
2

1
2

SC1U16V3ZY-GP

SCD1U16V2ZY-2GP

C513

PLACE CAP NEAR PIN80 AND PIN102

JEN0
(Pin 24)

C518

SCD1U16V2ZY-2GP

C193

SC1U16V3ZY-GP

C194

3D3V_AUX_S5

VBAT

Sheet

34

of

47

Power Dash Board to Board CONN

SA:04/22 change C532,C533,C534


connection power from "3D3V_S0" to
"3D3V_AUX_S5"

SPI

Q3

3D3V_AUX_S5

R2
PDTC124EU-1-GP

1
2

R2
PDTC124EU-1-GP

EMI REQUEST

DY

D
R2
PDTC124EU-1-GP

LED_PWR#

R1

2
2

30 UIM_VPP

UIM_VPP

30 UIM_CLK
30 UIM_DATA

UIM_CLK
UIM_DATA

3
5
7
9
11
13
15
17
19
21
23
25
27

4
6
8
10
12
14
16
18
20
22
24
26
28

-1:0910
TV_LUMA
TV_COMP
TV_CRMA

32 SPDIF_D

1
2
3
4

1
2

ST100U6D3VBM-9GP

SC220P50V2KX-3GP

at least 80 mil
8
7
6
5

OC1#
OUT1
OUT2
OC2#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

SC220P50V2KX-3GP

SC220P50V2KX-3GP

USB_OC#3 21

<Core Design>

EC27

DY

USB_OC#2 21

TPS2062D-GP

1
C

GND
IN
EN1#
EN2#

34,38 USB_PWR_EN#

WIFI_LED#

EC30

DY

EC31

DY

EC128
SCD1U50V3ZY-GP

1
2

R1
R2

DY

PDTC124EU-1-GP

LED_CHARGE#

EC29

C166
SCD1U16V2ZY-2GP

DY
TC8

C
LED_BAT#

SC220P50V2KX-3GP

3D3V_S0

C163
SCD1U16V2ZY-2GP

LED_PWR#

5V_S0

C165
SCD1U16V2ZY-2GP

5V_S5

5V_USB2_S5

at least 80 mil

Q5

EC150

DY

SC:08/09 Add
EC150(78.22124.2FL) for EMI
request, deault is dummy.

LED_CHARGE#

R2
PDTC124EU-1-GP

BAW56PT-U
83.00056.E11

SC220P50V2KX-3GP

R1

-1:08/31 Change CN6 pin26


from "5V_S5" to
"5V_USB2_S5"

U65
WLAN_LED_TEST 34

5V_USB2_S5
3D3V_S0

-1:08/29 Add U65 power switch to controll


"5V_USB2_S5".

WLAN_LED 29

LED_BAT#

Q6
34 CHARGE_LED

USB_PP3 21
USB_PN3 21

LED_MASK#

SC220P50V2KX-3GP

R2
PDTC124EU-1-GP

USB_PP2 21
USB_PN2 21
UIM_RESET 30

UIM_RESET

SC:08/09 Add
EC149(78.22124.2FL) for EMI
request, deault is dummy.

1
R1

become

-1:0910

MLX-CONN28A-2-GP

Q7

-1:08/29 Rename CN6


pin2,pin4 power net
"5V_USB2_S5".

D14
WIFI_LED#

34 BATFULL_LED

DY

5V_S5

EC53

1
2

EC149
SC220P50V2KX-3GP

Q37
2N7002PT-U

UIM_PWR

SATA_LED# 20
BAS16-1-GP

Q8

34 PWRLED

SC220P50V2KX-3GP

2
3
2

30 UIM_PWR

10 M_LUMA
10 M_COMP
10 M_CRMA

DY

DY

SC47P50V2JN-3GP

SC:08/11 Add EC163 on


"LID_CLOSE" for RF team
20.K0227.012 Request.

EC54

5V_USB2_S5

1
2

14
MLX-CON12-11GP

DY

CONN 28PIN

LED_MASK# 34

EC55

LED_NUM#

Right I/O Board to Board CONN

BT_ACT_K# 31

D15
DRVIE_LED#

DY

2
2

LID_CLOSE# 34

EC163

EC2

LED_CAP#

CN6

LID_CLOSE#
DRVIE_LED#
WIFI_LED#
BT_LED#

LED_SCRLK#

BAW56PT-U
83.00056.E11

BT_ACT_WPAN# 30

Q36
2N7002PT-U

SC:08/09 Add
EC148(78.22124.2FL) for EMI
request, deault is dummy.

LED_BAT#
LED_CHARGE#

BT_LED#_R

0R2J-2-GP

SC220P50V2KX-3GP

1
LED_PWR#

EC3

D13

EC148

2
2
3
4
5
6
7
8
9
10
11
12

INSTEAD_BTN#

DY

R446

KBC_PWRBTN#

SPICLK 34

SC220P50V2KX-3GP

150R2J-L1-GP-U
EC98
SC4D7P50V2CN-1GP

SPIDO 34

SC220P50V2KX-3GP

DY

DY

20.K0227.008

Main Source:20.K0227.008
2nd Source: 20.K0237.008

R333
150R2F-1-GP

BT_LED#
3D3V_S5

MLX-CON8-10-GP-U

R334 1

LED Board to Board CONN


13

LED_NUM#

SPI_HOLD#

VCC
HOLD#
CLK
DIO

R1

SC220P50V2KX-3GP

CS#
DO
WP#
GND

-1:09/02 Change CN3(LED


Board) pin assignment.
5V_S0 5V_S5

LED_SCRLK#
LED_CAP#
LED_NUM#

R2
PDTC124EU-1-GP

SPI_WP#

150R2J-L1-GP-U

8
7
6
5

EC97
SC4D7P50V2CN-1GP

CN3

34 NUM_LED

U21

1
2
3
4

W25X80-VSSI-GP

LED_CAP#

R1

SCD1U16V2ZY-2GP

8M Bits 3D3V_AUX_S5

EC34
SC4D7P50V2CN-1GP

C506
34 CAP_LED

2
3
4
5
6
7
8
10

34 KBC_PWRBTN#
34 INSTEAD_BTN#

Q1

SCD1U16V2ZY-2GP

CN2

9
1

C5
SCD1U16V2ZY-2GP

SPI_HOLD# 4
3
2
1

5V_S5

-1:09/02 Change
CN2(Power Dash Board)
pin assignment.

Q2

SPICS# SPICS#
R99

DY

SRN10KJ-6-GP
RN24

34 SPICS#
34 SPIDI

C509

5
6
7
8

C508
SC10U6D3V5MX-3GP

3D3V_AUX_S5

LED_SCRLK#

R1

34 SCRLK_LED

SPI FLASH ROM

Title

FWH and Board to Board CONN


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


D

Sheet
E

-1
35

of

47

FAN1_VCC

5V_S0

1
3

1
C8
SC10U10V5ZY-1GP

R187
10KR2J-3-GP

D24
BAS16-1-GP

FAN1_VCC
FAN1

C346
SCD1U16V2ZY-2GP

*Layout* 15 mil

FAN1_FG1

3
2
1

RN20

4
3

1
2

G792_SCL
G792_SDA

*Layout* 15 mil

3D3V_S0

SRN10KJ-5-GP

C337
SC1KP50V2KX-1GP

5
MLX-CON3-6-GP

SC:08/10 Change C337


from 78.10234.1BL to
78.10224.2FL
U19

SC4D7U6D3V5KX-3GP

C473
SCD1U16V2ZY-2GP
R310
100KR2J-1-GP

C479

VCC
DVCC

7
9
11

DXP1
DXP2
DXP3

15
13
3
2

ALERT#
THERM#
THERM_SET
RESET#

DY

2 0R2J-2-GP

THRM#_R
V_DEGREE

-1:0909
R83
21 THRM#
34,46 PURE_HW_SHUTDOWN#

1
R301
47KR2F-GP

G792SFUF-GP

1
4
14
16
18
19

DGND
DGND

5
17

SGND1
SGND2
SGND3

8
10
12

G792_SDA
G792_SCL

G792_CLK 21
G792_SDA 34
G792_SCL 34

H_THERMDA 5
C173
SC2200P50V2KX-2GP

H_THERMDC 5

Place on reverse side of CPU


G792_DXP2

C178
SC2200P50V2KX-2GP

G792_DXN2
R300

G51

Place near G792 chip as close


as possible

Place G14 near U36


GAP-CLOSE

R298
10KR2J-3-GP

Place near CPU and NB (Orignal Q25


location)
1

G792_DXP3

Q33
CH3904PT-GP

B
E

C177
SC2200P50V2KX-2GP

G792_RESET#
2
4K7R2J-2-GP
SA:4/28

G792_DXN3
G64

Place G15 near U36


GAP-CLOSE

8,21 PM_PWROK

DXP1:108 Degree
DXP2:H/W Setting (85 Degree)
DXP3:88 Degree

Q25
CH3904PT-GP

B
E

V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC

FAN1
FG1
CLK
SDA
SCL
NC#19

Setting T8 as
85 Degree

3D3V_AUX_S5
SA:4/28

1
R305
30KR2F-GP

C486
SC1U10V3ZY-6GP

5V_S0

6
20

5V_G792_S0

R308
2
200R2F-L-GP

*Layout* 30 mil
1

5V_S0

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Fan Controllor G792


Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

-1
36

of

47

SB:06/27 Change K/B connector from 20.F0694.025


to 20.K0291.027 .

TouchPad Connector
5V_S0

34

C148
SCD1U16V2ZY-2GP

C135
SC1U10V3ZY-6GP

2
1

KCOL10
KCOL11
KCOL9
KCOL14
KCOL13
KCOL15
KCOL16
KCOL12
KCOL0
KCOL2
KCOL1
KCOL3
KCOL8
KCOL6
KCOL7
KCOL4
KCOL5
KROW0
KROW3
KROW1
KROW5
KROW2
KROW4
KROW6
KROW7

KCOL[0..16]

5V_S0

RN22
SRN10KJ-5-GP
TPAD1

Internal KeyBoard Connector

3
4

SB:06/13
5
1

1
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

34

2
3
4
6

34 TPCLK
34 TPDATA
C187
SC33P50V2JN-3GP

C188
SC33P50V2JN-3GP

FOX-CON4-12-GP

2
2

29

KROW[0..7]

KB1

SA: 04/15 change TPAD conn to 20.K0179.004

KB_DET# 34

28
JAE-CON27-GP

CAPACITY BUTTON

EC86

KCOL16

3D3V_S0

R190

5V_S0

R191

DY

2 0R3-0-U-GP

CN1

2 0R3-0-U-GP

1
2
3
4
5
6

CAP_SCL
CAP_SDA

34 CAP_SCL
34 CAP_SDA

EC68

KROW3
KROW2
KROW1
KROW0

EC77

EC75

EC78

EC80

KCOL11
KCOL10
KCOL9
KCOL8

EC89

EC91

EC90

EC85

KCOL3
KCOL2
KCOL1
KCOL0

EC73

EC84

EC72

for EMI

20.K0227.006
CAP_SCL

Main Source:20.K0227.006
2nd Source: 20.K0228.006

CAP_SDA

DY

DY

SC220P50V2KX-3GP

EC159

EC158

SC220P50V2KX-3GP
2

8
MLX-CON6-11-GP

SC220P50V2KX-3GP

EC67

EC76

EC66

EC65

KROW7
KROW6
KROW5
KROW4

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

EC81

EC88

EC82

EC87

KCOL15
KCOL14
KCOL13
KCOL12

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

EC70

EC69

EC79

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

EC71

KCOL7
KCOL6
KCOL5
KCOL4

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2
SC220P50V2KX-3GP
2

34 CAPA_INT#

-1:09/02 Change CN1(Capacity


button) pin2 from GND to NC

SC:08/09 Add
EC158,EC159(78.22124.2FL)
for EMI request .Default is
DUMMY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

KeyBoard-CONN
Size
A3

Document Number

Date: Wednesday, September 12, 2007

Rev

DS2-Intel
Sheet

37

-1
of

47

U66

5V_S5

5V_USB1_S5

DY

5V_S5

3D3V_S5

R206
100KR2J-1-GP

USB_OC#1 21

2
1
CH3904PT-GP
Q21

D26
BAV99PT-GP-U

PSID_DISABLE# 34

R225
2K2R2J-2-GP

2
3

D25
BAV99PT-GP-U

R222
10KR2J-3-GP

USB_OC#0 21

R221
15KR2J-1-GP
EC176
SCD1U16V2ZY-2GP

DY
TC6
ST100U6D3VBM-9GP

DY

TPS2062D-GP

OC1#
OUT1
OUT2
OC2#

GND
IN
EN1#
EN2#

at least 80 mil

8
7
6
5

34,35 USB_PWR_EN#

1
2
3
4

at least 80 mil

5V_S5

R220

ACDC_ID 34

2N7002PT-U
Q20

DY1

R2
R1

Reserved for EMI


3 OUT

AD+_JK
R1

1
2

C
R260
47KR3J-L-GP

DY

2 GND

R2

C4
SCD01U50V2KX-1GP

1
IN

34 AD_OFF

C398

PDTA124EU-1-GP
Q27

C408

SC10U25V6KX-1GP

Q26

C410

SCD01U50V2KX-1GP

P2003EVG-GP

Id=17A
Qg=100~150nC
Rdson=5.4~6.5mohm

This cap should be used


only as last resort for
EMI suppression.

MLX-CONN24A-1-GP

C409

R9
240KR3-GP

C7
SC1U25V5KX-1GP

8
7
6
5

SCD01U50V2KX-1GP

DY

D
D
D
D

C3
SCD1U50V3KX-GP

U47
S
S
S
G

AD+

1
2
3
4

AD+_JK

4
6
8
10
12
14
16
18
20
22
24
29
27

3
5
7
9
11
13
15
17
19
21
23
NP2
25

SCD01U50V2KX-1GP

CONN 24PIN(AC-In+USB)

28
30
2

21 USB_PP1
21 USB_PN1

21 USB_PP0
21 USB_PN0

26
NP1
1

Left I/O Connector

R207

33R2J-2-GP

CN5

5V_USB1_S5

DDTC124EUA-7F-GP

33R2J-2-GP

SB: 06/27 Change CN5 from


20.F1089.028 to 20.F1134.024

1
S

PD_ID

-1:08/30 Add U66 power switch to


control USB power

DY

Place near DCIN1

Left I/O Board to Board CONN

3D3V_AUX_S5

D23
B

2
BAT_SCL

3
1

Batt Connecter

BAV99PT-GP-U
D1

BATT1
BAT_SDA

GND
GND
GND2
GND1
BAT_ALERT
SYS_PRES#
BATT_PRS#
DAT_SMB
CLK_SMB
BATT2+
BATT1+

11
10
9
8
7
6
5
4
3
2
1

SB:07/09 Change R21 from 100K to 470K for


power team request
PBAT_ALARM#
PBAT_PRES1#
R22
PBAT_SMBDAT1
PBAT_SMBCLK1

1
BAV99PT-GP-U

TP17

R21

2 100R2J-2-GP

2 470KR2J-2-GP

RN1

1
2

4
3

SRN100J-3-GP
R1

3D3V_AUX_S5
BAT_IN# 34
BAT_SDA 18,34,39
BAT_SCL 18,34,39

D6

2
BAT_IN#

BT+

1 0R0603-PAD

1
BATT_SENSE 39

SYN-CON9-1-GP-U1

BAV99PT-GP-U
<Core Design>
D2

Battery CONN. Main source:20.80953.009

C2
SCD1U50V3KX-GP

C1
SC2200P50V2KX-2GP

PBAT_ALARM#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

3
1

2nd source:20.80626.009

Title

AD/BATT CONN

BAV99PT-GP-U
Size
A3

Document Number

Date: Wednesday, September 12, 2007


5

Rev

DS2-Intel
Sheet
1

38

-1
of

47

MAX8731_LDO
1

SB:06/29 Add
EC130,EC131,EC132,EC133(78.10494.4BL)
for "BT+" by EMI request
BT+

EC133
4

EC132

SCD1U50V3ZY-GP

NEAR

5V_AUX_S5

EC131

SCD1U50V3ZY-GP

15K4R2F-GP

EC130

SCD1U50V3ZY-GP

R45
4

SCD1U50V3ZY-GP

ACAV_IN

R44
10KR2F-2-GP

R48
100KR2J-1-GP
2

Adaptor In Soft-Start Circuit

AC_IN#

1
2
R229
D01R2512F-4-GP

CHG_AGND

C390

BAT_SCL

10

SCL

SCD1U25V3KX-GP

CHG_AGND
18,34,38 BAT_SCL

DHI

24

BAT_SDA

23

DLO

20

SDA

1
2

1
1
2

CHG_AGND

DY

U8
SI4800BDY-T1
1
2
C48
SC1U10V3KX-3GP

2nd:FDS8884(84.8884.A37)

MAX8731_DHI
R224
1R3F-GP
1
2
MAX8731_LX 1
C42
2
SCD1U25V3KX-GP
1
2
C381
SC220P50V2JN-3GP
MAX8731_DLO

MAX8731_LX1

BT+

CHG_PWR

L14

Layout Trace 300mil

1
2
R204
D01R2512F-4-GP

IND-5D8UH-GP

68.5R850.101

15

74.08731.A73

2 BATT_SENSE
100R2F-L1-GP-U

BAT_SENSE 1
R228

MAX8731AETI-GP

GND

CCV
CCI
CCS
REF
DAC
GND

29

1
2

C389
SCD1U16V2ZY-2GP

1
2

C49
SC1U10V3KX-3GP

1
2

C384
SCD01U50V2ZY-1GP

1
2

1MAX8731_CCV1

MAX8731_CCV
6
MAX8731_CCI
5
MAX8731_CCS
4
MAX8731_REF
3
MAX8731_DAC 7
12

2
4K7R2F-GP

C385
SCD01U50V2ZY-1GP

C387
SCD01U50V2ZY-1GP

10KR2F-2-GP

R230

C393
SCD1U16V2ZY-2GP

2nd:FDS8884(84.8884.A37)
1
R227

FBSA

INP

GAP-CLOSE-PWR-3-GP

FBSB

16

U7
SI4800BDY-T1

MAX8731_CSIN

17

G45

MAX8731_CSIP

CSIN

GAP-CLOSE-PWR-3-GP

18

19

CSIP

4
3
2
1

34 AD_IA

PGND

G46

BATSEL

G
S
S
S

14
CHG_AGND

D
D
D
D

18,34,38 BAT_SDA

LX

R42
0R3-0-U-GP
MAX8731_BST 1
2MAX8731_BST1 1
MAX8731_LDO
D8
1SS400PT

25
21

5
6
7
8

BST
LDO

MAX8731_VCC

C32
SCD1U25V3KX-GP

ACOK

R223

C373
SC10U25V0KX-3GP
2
1

13

C380
SC1U10V3KX-3GP

C375
SC10U25V0KX-3GP
2
1

ACAV_IN

CSSN
VCC

27
26

VDD

28

CHG_AGND

33R2J-2-GP

NEAR KBC POWER


11

CSSP

SCD1U25V3KX-GP

D
D
D
D

ACIN

NEAR INPUT AD+

G
S
S
S

DCIN

2nd:A04433(84.04433.A37)

4
3
2
1

22

MAX8731_ACIN

BT+

8
7
6
5

C379

MAX8731_DCIN

D
D
D
D

5
6
7
8

3D3V_AUX_S5

1
2

49K9R2F-L-GP

C383
SCD01U50V2ZY-1GP

2
1

R226

U46

ASNS

C43
SC1U25V5KX-1GP

365KR3F-GP

CHG_AGNDCHG_AGND

R41

R40

2
0R2J-2-GP

S
1

U5
S
S
S
G

P2003EVG-GP

R18
470KR2J-2-GP

SCD1U25V3KX-GP

MAX8731_CSSN

C378

MAX8731_CSSP

2
S

Q24
2N7002PT-U

G
ACAV_IN

1
AD+

GAP-CLOSE-PWR-3-GP

2
100KR2J-1-GP

DCIN_GATE2 1
2
49K9R2F-L-GP
R231

1
R241

DCIN_GATE1
D

Q22
2N7002PT-U

G49

DC_IN_D
D

G50

2nd:A04433(84.04433.A37)

GAP-CLOSE-PWR-3-GP

P2003EVG-GP

R240
10KR2J-3-GP

G
S

1
2
3
4

AD+

ACAV_IN

Layout Trace 300mil

DCBATOUT

Layout Trace 300mil

C13
SC10U25V6KX-1GP

AD+_TO_SYS

1
2
3
4

3
Q23
2N7002PT-U

U48
S
S
S
G

D
D
D
D

8
7
6
5

C335
SC10U25V0KX-3GP
2
1

Trace 250mil

C336
SC10U25V0KX-3GP

AD+ Layout

C68
SC1U10V3KX-3GP

34 AC_IN#

DY

BATT_SENSE 38

C386
SCD01U50V2ZY-1GP
1

<Core Design>

1
2
G48
GAP-CLOSE-PWR

Wistron Corporation

CHG_AGND

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

CHARGER MAX8731
Size
Document Number
Custom

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
E

39

of

47

1
2

1
2

1
2

C218
SCD1U10V2KX-4GP

2
1

C581
SC18P50V2JN-1-GP

1
1

GAP-CLOSE-PWR
2

G27

GAP-CLOSE-PWR
2

G29

GAP-CLOSE-PWR
2

GAP-CLOSE-PWR

1
2

1
2

C257
SCD1U50V3KX-GP

L7
1
2
IND-3D3UH-57GP

1
R132

2
0R2J-2-GP

51120_GND

DY

1
1

C575

DY
2

51120_VREF2
0R2J-2-GP

R401
13K3R3F-GP

SC330P50V3KX-GP

1
2
G63
GAP-CLOSE-PWR

+VCC_TPS51120

G42

GAP-CLOSE-PWR
2

G41

GAP-CLOSE-PWR
2

G43

GAP-CLOSE-PWR
2

G40

GAP-CLOSE-PWR
2

GAP-CLOSE-PWR

1
2

1
C248

51120_VFB2

C586
SCD1U10V2KX-4GP

+VCC_TPS51120

2
0R2J-2-GP

1
R404
30K9R3F-GP

4
3
2
1

2
0R2J-2-GP

DY 2
DY

R396

2D2R5F-2-GP

U32
AO4712-GP

DY
DY

GAP-CLOSE-PWR
2

SC18P-GP

7
2

5
6
7
8

+3.3V_ALWP

51120_DRVH2
51120_LL2

51120_VREF2
2
0R0402-PAD

1
R390

2
G44

5
6
7
8
51120_TONSEL1
R135

SC:08/13 Change R135 from


63.R0034.1DL to
ZZ.R0402.ZZZ

1
R131

DY

C587
SC2200P50V2KX-2GP

SA:04/23 Change C733 to DUMMY


for power team request

SI4800BDY-T1
U29

51120_DRVL2
2

C252
SC10U25V6KX-1GP

51120_DRVH1
51120_DRVH2

27
14

3D3V_S5
G39

TC20
ST220U6D3VDM-13GP

DY

Iout = 5A
OCP < 10A
+3.3V_ALWP

CPUCORE_ON 41,43,44,45

32
31

24
17
5
33
1
2

1
2

DRVH1
DRVH2

0R2J-2-GP

DY

DY

1
R130

51120_GND

2
0R0402-PAD

51120_GND

51120_GND

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L


Inductor: 3.3UH CYNTEC 11Arms 14.5Apeak
O/P cap: 220U6.3V 6TPE220M 25mOhm 2.4Arms/ 77.22271.17L
H/S: AO4468 SO-8/ 30mOhm/ 4.5Vgs
L/S: AO4712 SO-8/ 7.3mOhm/ 4.5Vgs

SC:08/13 Change R130 from


63.R0034.1DL to
ZZ.R0402.ZZZ

DY

TC4
ST220U6D3VDM-13GP

1
DRVL1
DRVL2

51120_DRVL1
51120_DRVL2

S
S
S
G

G32

DCBATOUT_TPS51120

D
D
D
D

TP0610T-T1-E3-GP
R125
3
1
D

RUN_ON

C225
SCD1U50V3KX-GP

D
D
D
D

2
1

30
11
25
16

1
R134

R126

TPAD30 TP76

GAP-CLOSE-PWR
2

G31

7K5R2F-1-GP
SC330P50V3KX-GP

R143
100KR2J-1-GP

PGOOD1
PGOOD2

Q32
S

S
51120_GND

51120_LL2
51120_LL1

15
26

C243
SC1KP50V2KX-1GP

R391

VREF2

R381
Q13
200KR2F-L-GP
2N7002PT-U

C570

+VCC_TPS51120

DY

51120_DRVL1

51120_GND

2
SC1KP50V2KX-1GP

51120_VFB1

D
D
D
D

51120_VREF2

51120_GND

30KR3F-GP

DY

G
S
S
S

VO1
VO2

51120_CS1
2
12K1R2F-L1-GP
51120_CS2
2
11K3R2F-2-GP

1
C591

GAP-CLOSE-PWR
2

4
3
2
1

1
8

2
SC1KP50V2KX-1GP

1
R389
1
R405

R392
2D2R5F-2-GP

4
3
2
1

+5V_ALWP
+3.3V_ALWP

DY

R384

VFB2
VFB1

5
6
7
8

1
6
3

G30

51120_GND

LL2
LL1

TI suggest R<=15Kohm

+VCC_TPS51120
1
C572

4
3
2
1

G
S
S
S
C245
SCD1U10V2KX-4GP

DY
2

EN1
EN2
EN3
EN5

2 0R2J-2-GP 51120_VFB2
2 0R2J-2-GP 51120_VFB1

DY
DY

1
1

C237
SCD1U10V2KX-4GP
2
1

R138
R136

29
12
10
9

3D3V_S0

COMP2
COMP1

2
0R2J-2-GP
R129
51120_EN1
1
2
0R0402-PAD

46 3V/5V_EN

+VCC_TPS51120

VREG3
VREG5

21,28,34,44,45 PM_SLP_S4#

DY

U56
TPS51120RHBR-GPU1

SKIPSEL
TONSEL

DY R133

U26
AO4712-GP

5V_S5
G28
1

+5V_ALWP
1
2
IND-3D3UH-57GP

+VCC_TPS51120

51120_SKIPSEL

SC:08/13 Change R129 from


63.R0034.1DL to
ZZ.R0402.ZZZ

1
2

C249
SC10U10V5KX-2GP

+5V_ALWP

S
S
S
G

3D3V_AUX_S5

2 51120_VBST1
0R3-0-U-GP

GAP-CLOSE-PWR

1
2

51120_LL1 1
2 51120_VBST1_11
C569
R388
SCD1U50V3KX-GP

C559
SC2200P50V2KX-2GP

L6

D
D
D
D

GAP-CLOSE-PWR
2

G36
1

C577
SCD1U50V3KX-GP

Iout =6A
OCP < 12A

DY

SA:04/23 Change C746 to DUMMY


for power team request

SI4800BDY-T1
U28

51120_DRVH1
51120_LL1

V5FILT
VIN

GAP-CLOSE-PWR
2

G37
1

2 51120_VBST2
0R3-0-U-GP

CS1
CS2

DCBATOUT_TPS51120
51120_LL2 1
2 51120_VBST2_11
C594
R410
SCD1U50V3KX-GP

28
13

GAP-CLOSE-PWR
2

20
22

G35

PGND1
PGND2
GND
GND

C585
SC1U10V3KX-3GP

VBST1
VBST2

GAP-CLOSE-PWR
2

2
5D1R3J-GP

23
18

G34

1
R402

19
21

GAP-CLOSE-PWR
2

5
6
7
8
2

G33

C250
SC10U10V5KX-2GP

C556
SC10U25V6KX-1GP

+VCC_TPS51120

5V_AUX_S5

G38

C582
SC10U25V6KX-1GP

DCBATOUT_TPS51120

DCBATOUT

C223
SC10U25V6KX-1GP

DCBATOUT_TPS51120

2
0R2J-2-GP

Vout=1V*(R1+R2)/R2
GND
SKIPSEL

AUTOSKIP
N/A

COMP
TONSEL
1

VFB1
VFB2
EN1,EN2
EN3,EN5

VREF2
AUTOSKIP
/FAULTS
OFF
N/A

380k/CH1
580k/CH2
N/A

280k/CH1
430k/CH2
not use

N/A

not use

Switcher OFF
LDO OFF

not use
not use

FLOAT
PWM
CURRENT
MODE
220k/CH1
330k/CH2
ADJ.
ADJ.
Swithchr ON
LDO ON

V5FILT
PWM
D-Cap
MODE
180k/CH1
2870k/CH2
5V
Fixed Output
3.3V
Fixed Output
Switcher ON
VREG3 on

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC to DC 3.3V & 5V
Size
Custom

Document Number

Rev

Date: Wednesday, September 12, 2007


A

-1

DS2-Intel
Sheet
E

40

of

47

6262_AGND
6262_VCC

6262_FB

6262_AGND

2
48

1
2

3V3

PGOOD

25

6262_AGND

VSUM

19

6262_VSUM

11K3R2F-2-GP

VO

18

6262_VO

R218
2K61R3F-GP

1 2

R215
C372
11KR2F-L-GP
SCD068U10V2KX-1GP

R216

2
1R3F-GP

6262_ISENN2 42

R214
6262_ISEN1

10KR3F-L-GP

R183
NTC-10K-9-GP

1
2

C368

6262_ISENP2 42

C370

R20

6262_OCSET

10KR3F-L-GP

SB:06/22 Change R20 from


64.12725.6DL to
64.11325.6DL

SB:06/23 Change C372 from


78.47323.2FL to 78.68323.5FL

Place close to phase 1 chocke


1

C364

3K65R3F-GP

1
R217

R33
1KR3F-GP

R29

When test without cpu,


R483 & R486 change to 0 ohms

R219
6262_VSUM

6262_ISEN2

1
C28

C365
SCD22U10V2KX-1GP

6262_AGND

2
3K6R2F-GP

C369
SCD01U25V2KX-3GP

20

VW

10KR3F-L-GP

6262_PHASE2 42
6262_LGATE2 42

C363
SCD01U25V2KX-3GP

SCD01U25V2KX-3GP

SC:08/13 Change R27 from


63.00000.00L to ZZ.R0603.ZZZ

COMP

2
0R0603-PAD

1
R27

NC#25

U43

6262_ISENN1 42

2
0R0603-PAD

6262_ISEN2

C356
SCD22U25V3KX-GP

ISL6262ACRZ-T-GP-U
FB

2
1R3F-GP
R35
1
2

FB2

6262_ISENP1 42

6262_VW

SC1KP50V2KX-1GP

R28

1
2
R210 0R3-0-U-GP 1

10KR3F-L-GP

1
R34

6262_UGATE2 42
6262_BOOT2

2
SC4D7U6D3V3KX-GP

2
6K81R2F-1-GP
2

1
C350

6262_COMP

SC:08/13 Change R28 from


63.00000.00L to ZZ.R0603.ZZZ

28
30
29
23

C362
SCD22U10V3KX-2GP

SCD22U10V2KX-1GP

C357

1
R209
C355
1

PHASE2
LGATE2
PGND2
ISEN2

5V_S0

10

2
SC470P50V2KX-3GP

26

OCSET8

9
1

SC220P50V2KX-3GP

6 VCC_SENSE

11

BOOT2

R24
6262_ISEN1

C360
2
1
1
2
R212
SC1KP50V2KX-1GP
255R2F-L-GP
R213
1
2
1KR2F-3-GP

6 VSS_SENSE

VDIFF

6262_VDIFF
6262_FB212

1
2
1KR2F-3-GP

1 R208
2
97K6R2F-GP
C351
1

13

27

3K65R3F-GP
6262_VSUM 1 R26

DFB

6262_VID6
2
0R2J-2-GP

DPRSLPVR
DPRSTP#
CLK_EN#

UGATE2

17

1
R197

6262_VID4
6262_VID5

R211

45
46
47

PVCC

31

6262_DFB

CPU_VID6

6262_VID1
6262_VID0

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON

DROOP

CPU_VID4
CPU_VID5

SRN0J-5-GP
RN4
SRN0J-6-GP
RN5
1
4
2
3

6 CPU_VID[0..6]

5
6
7
8

37
38
39
40
41
42
43
44

VSEN

4
3
2
1

24

PHASE1

1
R200
6262_BOOT1

SCD22U10V3KX-2GP

CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

ISEN1

PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT

16

6262_LGATE1 42

33

2
3
4
5
6
7

14

If NTC=330Kohm, R10=8.66K

32

PGND1

36

6262_VSEN

470K /0402 size

6262_NTC
6262_SOFT
1
2
6262_AGND
C19
SCD015U25V3KX-GP
SCD01U16V2KX-3GP
6262_VID0
2
6262_VID1
6262_VID2
SB:06/17 Change R12,R16,R17 R198 from 0402 0
6262_VID3
Ohm to 0402 close pad.
6262_VID4
6262_VID5
6262_VID6
R198 1
CPUVCORE_ON_R
2
40,43,44,45 CPUCORE_ON
0R0402-PAD
6262_DPRSLP
1
2
8,21 DPRSLPVR
R16
0R0402-PAD
1
2 6262_DPRSTP#
6,8,20 H_DPRSTP#
R17
0R0402-PAD
6262_VID3
21 CLK_EN#
6262_VID2

VIN

VDD
R185
4K02R3F-GP
C11 1

1 R184
2
NTC-470K-1-GP

34

LGATE1

35

BOOT1

RTN

6262_PSI#
6262_PMON
6262_RBIAS

UGATE1

GND_T

15

6262_AGND

0R0402-PAD
2
147KR2F-GP

2
0R3-0-U-GP
1
C345
SCD22U25V3KX-GP
2
6262_PHASE1 42

GND

49

5 CPU_PROCHOT#

6262_UGATE1 42

21

6262_RTN

2
1
R15

VGATE_PWRGD 8,21

C9
SCD01U25V2KX-3GP

22

1
1
R12
TPAD30 TP86
6262_AGND

6 PSI#

R203
1K91R2F-1-GP

6262_AGND

6262_AGND

Place close to phase 1 chocke

6262_3V3

R202

6262_VIN

C366

C367
SC1U10V3KX-3GP

1
SCD01U25V2KX-3GP
2
1

1
2

R30
10R3J-3-GP

10R3J-3-GP

R25
10R3J-3-GP

SB:06/17 Remove R205,C348,TP86


power monitor circuit.

DCBATOUT 3D3V_S0

5V_S0

6262_DROOP

SB:06/23 Change R29 from 64.32415.55L


to 64.36015.6DL

G47

6262_VO

GAP-CLOSE-PWR

SC180P50V2JN-1GP

6262_AGND

6262_AGND

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC-DC VCCCPUCORE 1/2


Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
1

41

of

47

DCBATOUT
DCBATOUT

EC127

EC126
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

1
2

SCD1U50V3ZY-GP

1
2

SCD1U25V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

TC7
SE100U25VM-14GP

1
2

SC10U25V6KX-1GP

1
2

C21

Panasonic ETQP4LR36WFC
10*11.5*4mm
0.34uH / 24A
DCR=1.1mohm

4
3
2
1

SCD1U50V3ZY-GP

1
2

SCD1U50V3ZY-GP

5
6
7
8

5
6
7
8
4
3
2
1

C352

EC125

SB:06/26 Add
EC120~EC127(78.10494.4BL),total 8
pcs CAP for EMI team request.

Iomax=47A
VCC_CORE_S0

L13

41 6262_UGATE1

41 6262_PHASE1

6262_ISENP1 41

ST330U2D5VDM-9GP

TC1

DY

1
2

6262_ISENN1 41

TC9
ST330U2D5VDM-9GP

1
2

4
3
2
1

4
3
2
1

S
S
S
G

S
S
S
G

C6
SC330P50V3KX-GP

DY

TC10
ST330U2D5VDM-9GP

G1
GAP-CLOSE-PWR-3-GP

Id=14.5A
Qg=25~35nC
Rdson=5.9~7.25mohm

G2
GAP-CLOSE-PWR-3-GP

ST330U2D5VDM-9GP

DY

TC12

U1
POWERPAK-8P-1-GP

R8
2D2R5F-2-GP

D
D
D
D

D
D
D
D

U40
POWERPAK-8P-1-GP

-1:0912
5
6
7
8

-1:0912

IND-D36UH-9-GP

5
6
7
8

41 6262_LGATE1

C22

EC124

SCD1U50V3ZY-GP

C353

EC123

SCD1U50V3ZY-GP

S
S
S
G

S
S
S
G

Id=13A
DY
Qg=10~14nC
Rdson=9.4~12mohm

U41
POWERPAK-8P-GP

EC146

EC122

SCD1U50V3ZY-GP

U2
POWERPAK-8P-GP

D
D
D
D

D
D
D
D

EC147

EC121
SCD1U50V3ZY-GP

EC120

DY

SCD1U50V3ZY-GP

SC:08/09 Add EC146,EC147 (78.10492.4BL) for EMI request .


Please place EC146 near C352, EC147 near U1

C40
SCD1U50V3ZY-GP

PANASONIC
330uF / 2V / V size
ESR=6mohm / Iripple=3.7A

41 6262_UGATE2

1
2

SC10U25V6KX-1GP

C338
SCD1U25V3KX-GP

1
2

C344

DY

Panasonic ETQP4LR36WFC
10*11.5*4mm
0.34uH / 24A
DCR=1.1mohm

41 6262_PHASE2

SC10U25V6KX-1GP

C339

L15

4
3
2
1

ST330U2D5VDM-9GP

1
C31
SC330P50V3KX-GP

DY

1
2

2
G3

DY
TC2

ST330U2D5VDM-9GP

G4

GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

S
S
S
G

S
S
S
G

4
3
2
1

TC11

DY

U6
POWERPAK-8P-1-GP

R31
2D2R5F-2-GP

D
D
D
D

D
D
D
D

U44
Id=14.5A
Qg=25~35nC POWERPAK-8P-1-GP
Rdson=5.9~7.25mohm

-1:0912
5
6
7
8

-1:0912

IND-D36UH-9-GP

5
6
7
8

41 6262_LGATE2

SC10U25V6KX-1GP

C343

4
3
2
1

4
3
2
1

S
S
S
G

S
S
S
G

SC10U25V6KX-1GP

U42
POWERPAK-8P-GP

D
D
D
D

D
D
D
D

Id=13A
DY
Qg=10~14nC
Rdson=9.4~12mohm

5
6
7
8

5
6
7
8

C340
U4
POWERPAK-8P-GP

DCBATOUT

SA: 04/11 Add depend on PW team

If VCC_SENSE and VSS_SENSE pins have pulled


resistors to VCC_CORE_S0
==> Remove R44/R45/R46/R47.

41 6262_ISENP2
41 6262_ISENN2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC-DC VCCCPUCORE 2/2


Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
1

42

of

47

DCBATOUT

+1.05V_PWR_SRC
G23

GAP-CLOSE-PWR
G22
1
2

Iout = 10A
OCP>20A

GAP-CLOSE-PWR
G21
1
2

+1.05V_SUSP

C461
SC2200P50V2KX-2GP

C460
SC10U25V6KX-1GP

SI4800BDY-T1

SB: 06/27 Change L22


from 68.2R210.20C to
84.04800.D37

GAP-CLOSE-PWR
G61
2

GAP-CLOSE-PWR
G60
2

GAP-CLOSE-PWR
G53
2

GAP-CLOSE-PWR
G54
2

TPS51117PWR-GP

3D3V_S0

U18
AO4712-GP

SB: 06/27 Change U18 from


84.06676.A37 to
84.04800.D37

SB:06/22 Change R76 from


64.12125.55L to 64.17425.55L

DY

GAP-CLOSE-PWR
G52
2

2D2R5F-2-GP
+1.05V_VFB

DY

GAP-CLOSE-PWR
G56
2

GAP-CLOSE-PWR
G55
2

COIL-2D2UH-11-GP
R290
12KR2F-L-GP

R302

40,41,44,45

4
3
2
1

R76
17K4R3F-GP

TC16
SE220U2D5VDM-6GP

C475

R296
30KR2F-GP

DY
2

DY R78
1
2
100KR2J-1-GP

CPUCORE_ON

7
8

+1.05V_SUSP

+1.05V_SUSP

GND
PGND

TON
TRIP

+1.05V_DRVL
1.05V_SUS_PWRGD

9
3
6

DRVL
VOUT
PGOOD

L22

+1.05V_LL

+1.05V_DRVH

12

EN_PSV

13

LL

S
S
S
G

SB:06/17 Change R284


from 0402 1K Ohm to
0402 close pad.

2
R286

VBST
VFB

DRVH

D
D
D
D

+1.05V_EN
1
0R0402-PAD
+1.05V_TON
1
2
200KR2J-L1-GP +1.05V_TRIP 11

1
R284

21,28,34,45,46 PM_SLP_S3#

V5FILT
V5DRV

5
6
7
8

4
10
+1.05V_VBST 14
+1.05V_VFB
5

C448
SCD1U10V2KX-4GP

U17

SB: 06/27 Change U15 from


84.08880.037 to
84.04800.D37

SC330P50V3KX-GP

GAP-CLOSE-PWR

2
R289

Cyntec 10*10
Irating=14A, Isat=16A
DCR=7mohm

C467
SC18P50V2JN-1-GP

+1.05V__LL1 2
1
1
0R3-0-U-GP
C463 SCD1U16V2KX-3GP

G
S
S
S

C138
SC1U10V3KX-3GP

4
3
2
1

GAP-CLOSE-PWR
G57
2

+1.05V_V5FILT

D10
CH551H-30PT-GP
C

5
6
7
8
D
D
D
D

GAP-CLOSE-PWR
U15

5V_S5

GAP-CLOSE-PWR
G59
2

DY

1
2

C147
SCD1U50V3KX-GP

1
2

1
R293
3D3R3J-L-GP

C146
SC10U25V6KX-1GP

GAP-CLOSE-PWR
G24
1
2

+1.05V_PWR_SRC

GAP-CLOSE-PWR
G25
1
2

C159
SC1U10V3KX-3GP

1D05V_S0
G58

GAP-CLOSE-PWR
G20
1
2
5V_S5

Vout=0.75V*(R1+R2)/R2

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L


Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I
O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161
H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037
L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037
Ton = 200KOhm --> 330KHz

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DCDC 1.05V
Size
A3

Document Number

Rev

-1

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet
1

43

of

47

DCBATOUT

+1.8V_PWR_SRC
G13

Iout=7A
OCP<14A

2
GAP-CLOSE-PWR
G12
2

+1.8V_SUSP

1
+1.8V_PWR_SRC

GAP-CLOSE-PWR
G10
1
2

GAP-CLOSE-PWR
G15
2

GAP-CLOSE-PWR
G19
2

GAP-CLOSE-PWR
G16
2

GAP-CLOSE-PWR
G66
2

GAP-CLOSE-PWR
G67
2

2
1

U12
FDS6676AS-GP

R51

R242
42K2R2F-L-GP

2D2R5F-2-GP

+1.8V_VFB

4
3
2
1

SB: 06/27 Change U12 from


84.04712.037 to 84.06676.A37

SB:06/22 Change R243 from


64.12125.55L to
64.17425.55L

1
2

40,41,43,45

CPUCORE_ON

C431
SCD1U10V2KX-4GP

1
+1.8V_SUSP

2 TON
GND 7
11 TRIP
8
SB:06/17
Change R253 PGND
from 0402 1K Ohm to 0402 close pad.
TPS51117PWR-GP

+1.8V_SUSP
C400
SC33P50V2JN-3GP

DRVL
VOUT
PGOOD

+1.8V_DRVL

9
3
6

L18
1
2
IND-2D2UH-46-GP-U

+1.8V_LL

R243
9K31R3F-GP

2
12

LL

TC3
SE220U2D5VDM-6GP

GAP-CLOSE-PWR
C

EN_PSV

DRVH

+1.8V_DRVH

GAP-CLOSE-PWR
G14
2

C80

R232
30KR2F-GP

SC330P50V3KX-GP

C420
SC10U25V6KX-1GP

Cyntec 10*10
Irating=14A, Isat=16A
DCR=7mohm

S
S
S
G

SB:06/17 Change R253


from 0402 1K Ohm to
0402 close pad.

2
R251

+1.8V_EN
0R0402-PAD
+1.8V_TON
1
200KR2J-L1-GP
+1.8V_TRIP

VBST
VFB

13

5
6
7
8

V5FILT
V5DRV

14
5

SB: 06/27 Change U13 from


84.04800.D37 to 84.08880.037

D
D
D
D

R253

4
10

C418
SC2200P50V2KX-2GP

5
6
7
8
2
1
C405 SCD1U16V2KX-3GP

U10

+1.8V_VBST
+1.8V_VFB

+1.8V_LL1
1
0R3-0-U-GP

4
3
2
1

2
R252

DY

S
S
S
G

C53
SC1U10V3KX-3GP

D9
CH551H-30PT-GP

21,28,34,40,45 PM_SLP_S4#

U13
FDS8880-NL-GP

+1.8V_V5FILT

5V_S5

C65
SCD1U50V3KX-GP

GAP-CLOSE-PWR

R244
3D3R3J-L-GP

C59
SC10U25V6KX-1GP

GAP-CLOSE-PWR
G17
1
2

D
D
D
D

C52
SC1U10V3KX-3GP

GAP-CLOSE-PWR
G65
2

5V_S5

1D8V_S3
G18

GAP-CLOSE-PWR
G11
1
2

Vout=0.75V*(R1+R2)/R2

SC:08/13 Change
R51(64.2R205.16L) and
C80(78.33124.2BL) from
No ASM to ASM

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L


Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I
O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161
H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037
L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037
Ton = 200KOhm --> 330KHz
B

<Variant Name>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC/DC 1D8V
Size
A3
Date:
5

Document Number

Rev

DS2-Intel
Wednesday, September 12, 2007
Sheet
44
1

-1
of

47

1
C500
SC10U10V5ZY-1GP

C501
SC10U10V5ZY-1GP

C498
SC1U10V3ZY-6GP

1D5V_SB

1D8V_S3

5V_S0

DY
4

2D5V/300mA

1D5V/3A

APL5912-KAC-GP

SO-8-P

R317

1K13R2F-1-GP

VOUT

GND

VIN

TC19
ST100U4VBM-L1-GP

C458
SCD1U10V2KX-4GP

TC18

DY
2

R320

GND

ST100U4VBM-L1-GP

1KR2F-3-GP

FB

C502

3
4

2D5V_S0
U51

VOUT
VOUT

3D3V_S0

1D5V_S0

5
9

EN

Vo=0.8*(1+(R1/R2))

VIN
VIN

21,28,34,43,46 PM_SLP_S3#

POK

2
7
0R0402-PAD

SCD01U16V2KX-3GP

1
R315

40,41,43,44 CPUCORE_ON

U53

VCNTL

SB:06/17 Change R315 from 0402 0


Ohm to 0402 close pad.

C465
SC4D7U6D3V5KX-3GP

G9131-25T73UF-GP

-1:0909

KEMET
100uF, 4V, B2 Size
Iripple=1.1A, ESR=70mohm

SSID = PWR.Plane.Regulator_0.9V
1D8V_S3

1
C450
SC1U10V3ZY-6GP

SB:06/17 Change R275 from 0402 0


Ohm to 0402 close pad.

RT9018A-25PSP-GP

GAP-CLOSE-PWR
G5
1
2

DY
R270
C436
1K13R2F-1-GP

SO-8-P
1

Vo=0.8*(1+(R1/R2))

GAP-CLOSE-PWR

TC14

R274
2KR2F-3-GP

TC13

NC#5
VOUT
ADJ
GND

0R0402-PAD

VDD
VIN
EN
PGOOD

SCD01U16V2KX-3GP

40,41,43,44 CPUCORE_ON

1
R275

5
6
7
8

21,28,34,43,46 PM_SLP_S3#

GAP-CLOSE-PWR
G7
1
2

4
3
2
1

1D25V_S0

GAP-CLOSE-PWR
G6
1
2

GND

U14

1D25V/2A

DY

C449
SC10U10V5ZY-1GP

C145
SC10U10V5ZY-1GP

1
1
2

C413
SC10U4V3MX-GP

11

+0.9V_P

1
2
3
4
5

U11
TPS51100DGQ-1-GP
74.51110.B79

SA:04/23 Change TC24,TC33 P/N for


power team request.

ST100U4VBM-L1-GP

C414
SCD1U10V2KX-4GP

DDR_VREF_S0
G8

5V_S0

ST100U4VBM-L1-GP

DDR_VREF_S3

1D8V_S3

0.9 Volt +/- 5%


Design Current: 1.05A
Peak current 1.5A

C412
SC10U4V3MX-GP

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS

2
GAP-CLOSE-PWR

10
9
8
7
6

21,28,34,43,46 PM_SLP_S3#

DDR_ON_0.9V
0R0402-PAD
0.9V_DDR_VTT_ON_R
2
0R0402-PAD

GND

21,28,34,40,44 PM_SLP_S4#

5V_S5

1
R257
1
R256

TPS51100_LDOIN
C54
SCD1U10V2KX-4GP

1
2

SB:06/17 Change R256,R257 from 0402 0


Ohm to 0402 close pad.

C55
SC10U4V3MX-GP

G9

KEMET
100uF, 4V, B2 Size
Iripple=1.1A,
ESR=70mohm

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC/DC 1D8V
Size
A3

Document Number

Rev

Date: Wednesday, September 12, 2007


A

-1

DS2-Intel
Sheet
E

45

of

47

H_THERMTRIP# 5,8,20,34

DY

R328
1
2
1KR2J-1-GP

H_PWRGD_R

Q31
CHT2222APT-GP

DY

DY C511
SCD1U10V2KX-4GP

6,20 H_PWRGOOD

2
D27
BAS16-1-GP

PURE_HW_SHUTDOWN#

34,36

1
1
R324

R325
200KR2J-L1-GP

40 3V/5V_EN

2
1KR2J-1-GP

S5_ENABLE 34

Run Power
5V_S5

5V_S0

DY

C207
1
DCBATOUT

SCD1U25V3KX-GP
Q11

Z_12V_D4

8
7
6
5

D
D
D
D

8
7
6
5

AO4468-GP
84.04468.037

R108

D17
BZX384-C9V1-GP
83.9R103.B3F

3D3V_S0

3D3V_S5

1
2
3
4

1
2

C206
R109
10KR2J-3-GP

1
G

R114
100KR2J-1-GP
Z_12V_D3 2

U30
S
S
S
G
AO4468-GP
84.04468.037

DY

-1:0909

1 Z_12V_G3
330KR2J-L1-GP

DY

SCD1U25V3KX-GP

2
R115

D
D
D
D

D
100KR2J-1-GP

Z_12V
2
S
10KR2J-3-GP
NDS0610-NL-GP
84.S0610.B31

RUN_POWER_ON

1
R113

1
2
3
4

U23
S
S
S
G

1D8V_S3

1D8V_S0

Q9
2N7002PT-U

Q29

1
G

Q10
2N7002PT-U

G
S

<Core Design>

R307

Wistron Corporation

10KR2J-3-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

FDC655BN-GP

1
2

21,28,34,43,45 PM_SLP_S3#

C483
SCD01U25V2KX-3GP

DY

SA:0329 Add for SiI1392 1.8V_S0

Title

PWRPLANE&RESETLOGIC
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007

Sheet

-1
46

of

47

3D3V_AUX_S5

3D3V_S5

AD+

5V_S5

-1:0904 Add EC187(78.10422.2BL) for


DCBATOUT decoupling , this is for
1D05V_S0
EMI request.

DCBATOUT

-1:0909

14

H17

DY

DY

H18

H19

DY
H20

DY
H21

DY
H22

DY

DY

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

1
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

DY
DY
EC95 EC63 EC4

DY
EC100

DY
EC117

SCD1U16V2ZY-2GP
2

DY
EC33

SCD1U16V2ZY-2GP
2

DY
EC45

DY
EC38

SCD1U16V2ZY-2GP
2

DY
EC37

DY
EC28

SCD1U16V2ZY-2GP
2

DY
EC12

DY
EC143

SCD1U16V2ZY-2GP
2

DY

DY
EC142

DY
EC141

SCD1U16V2ZY-2GP
2

DY
EC96

H16

DY

H15

DY

SCD1U16V2ZY-2GP
2

H14

DY

SCD1U16V2ZY-2GP
2

H13

DY

SCD1U16V2ZY-2GP
2

H12

DY

DY
DY
EC19 EC25

SB:06/22 Change EC1,EC5 from


DUMMY to ASM by EMI request.

H11

DY

H10

DY
DY
DY
DY
EC24 EC21 EC23 EC22

5V_S0

DY

H9

5V_S0

TSAHCT125PW-GP

DY

U9D

DY
DY
EC20 EC18

SB:06/29 Add
EC141,EC142,EC143(78.10491.4FL)
for EMI request

11

12

SCD1U16V2ZY-2GP
2

H8

SCD1U16V2ZY-2GP
2

H7

SCD1U16V2ZY-2GP

H6

H5

SCD1U16V2ZY-2GP

H4

1D8V_S3

DY
EC15

DY
DY
EC13 EC14

DY

SCD1U16V2ZY-2GP
2

H3

SCD1U25V3KX-GP

TSLVC08APW-1-GP

SCD1U16V2ZY-2GP
2

DY

13

H2

14

H1

SCD1U16V2ZY-2GP
2

1
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

1
2

TSLVC08APW-1-GP

DY

DDR_VREF_S0

5V_S0
3

5
1

TSLVC08APW-1-GP

DY

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
2

SC47P50V2JN-3GP

SCD1U16V2ZY-2GP

SSLVC08APWR-GP

DY

EC187

U20B

8
10

SSLVC08APWR-GP

EC1

11
13

SSLVC08APWR-GP

DY

3
2

EC26

3D3V_S5

8
10

U20C

12

11

3D3V_S5

U20D

14

U33A

EC39

DY

for RF

3D3V_S5

14

U33C

13

SCD1U16V2ZY-2GP
2

3D3V_S5

14

14

U33D

12

SC:08/11 Add EC164 on 5V_S5


team Request.

3D3V_S5

EC57

14

SC:08/11 Add EC162 on 3D3V_S5


for RF team Request.
3D3V_S5

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SC47P50V2JN-3GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

EC58

DY

DY

DY

EC164

DY
EC140

DY
EC139

DY
EC138

DY DY
DY
DY
EC108 EC107 EC112 EC105

EC162

DY
DY
DY
EC56 EC10 EC94 EC118

SCD1U16V2ZY-2GP
2

DY
DY
DY
DY
DY
DY
EC64 EC93 EC74 EC102 EC106 EC99

-1:0909

H23
3D3V_S0

3D3V_S0

DY
EC113

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SC:08/11 Change K7 from


34.39S07.001 to
34.41P18.001.This change is
for EMI request

Title

MISC
Size
A3

Document Number

Rev

DS2-Intel

Date: Wednesday, September 12, 2007


A

SCD1U16V2ZY-2GP

DY
EC177

SPRING-35-GP

K7

SPRING-24-GP

K6

SPRING-51-GP

K5

SPRING-24-GP

K2

SC:08/15 Add EC177(78.10491.4FL) on 3D3V_S0


,this is for EMI request. Default is DY

3D3V_S0

5V_AUX_S5

DY
DY
DY
DY
DY
DY
DY
DY
EC35 EC43 EC61 EC40 EC103 EC101 EC92 EC116 EC109 EC104

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

DY
EC137

SCD1U16V2ZY-2GP
2

Place this spring near


U40(bottom side)

DY
EC136

SC:08/09 Change K5 spring


from 34.45T31.001to
34.4B312.002 for ME
request

DY
EC135

SCD1U16V2ZY-2GP
2

SB:06/29 Add
EC134,EC135,EC136,EC137(78.10491.4FL)
for EMI request

DY
EC134

DY

DY
EC42

SCD1U16V2ZY-2GP
2

DY
EC41

Sheet
E

-1
47

of

47