Mohanad - System on Chip (SOC)

System On Chip - SoC

Mohanad Shini JTAG course 2005

Agenda
• • • • • • • Introduction . What is SoC ? SoC characteristics . Benefits and drawbacks . Solution . Major SoC Applications . Summary .

– hence the development of System-On-Chip design .Introduction • Technological Advances – today’s chip can contains 100M transistors . – approximately every 18 months the number of transistors on a chip doubles – Moore’s law . . – transistor gate lengths are now in term of nano meters . • The Consequences – components connected on a Printed Circuit Board can now be integrated onto single chip .

Summary . Solution . . What is SoC ? SoC characteristics . Major SoC Applications .Agenda • • • • • • • Introduction . Benefits and drawbacks .

People C: SoC is the efforts to integrate heterogeneous or different types of silicon IPs on to the same chip. like memory. but not very accurate!!! .What is SoC ? People A: The VLSI manufacturing technology advances has made possible to put millions of transistors on a single die. since we can program and give instruction to the uP to do whatever you want to do. random logics. uP. People B: SoC is a high performance microprocessor. All of the above are partially right. It enables designers to put systemson-a-chip that move everything from the board onto the chip eventually. and analog circuitry.

compiler. simulator. but more on “system”. protocol stackIntegrated development environment (debugger. assembly) The SoC Integration includes : The whole system solution Manufacture consultant Technical Supporting . linker. SoC = Chip + Software + Integration The SoC chip includes: Embedded processor ASIC Logics and analog circuitry Embedded memory The SoC Software includes: OS.What is SoC ? SoC not only chip. firmware. ICE)Application interface (C/C++. driver.

Agenda • • • • • • • Introduction . . Summary . Solution . What is SoC ? SoC characteristics . Benefits and drawbacks . Major SoC Applications .

System on Chip architecture ASIC Typical Design Steps Top Level Design Unit Block Design Unit Block Verification Integration and Synthesis Trial Netlists Timing Convergence & Verification System Level Verification Fabrication • Typical ASIC design can take up to two years to complete DVT Prep DVT 6 12 12 48 4 14 ?? 5 8 Time in Weeks 61 Time to Mask order .

IC Vendor steps of Placement.System on Chip architecture SoC Typical Design Steps Top Level Design Unit Block Design Unit Block Verification Integration and Synthesis Trial Netlists Timing Convergence & Verification System Level Verification Fabrication • With increasing Complexity of IC’s and decreasing Geometry. Layout and Fabrication are unlikely to be greatly reduced • In fact there is a greater risk that Timing Convergence steps will involve more iteration. DVT Prep DVT 4 4 2 14 24 5 4 Time in Weeks Time to Mask order 33 . • Need to reduce time before Vendor Steps. • Need to consider Layout issues upfront.

• All cores connect to the bus via a standard interface . – Global clocking scheme . • Any-to-any connections easy but … – Not all connections are necessary .System on Chip interconnection • Design reuse is facilitated if “standard” internal connection buses are used . – Power consumption . • Standardization is being addressed by the Virtual Socket Interface Alliance (VSIA) .

• APB (Advanced Peripheral Bus): simple strobedaccess bus with minimal interface complexity. • ASB (Advanced System Bus): a multimaster synchronous system bus. • AHB (Advanced High Performance Bus): a highthroughput synchronous system backbone. Burst transfers and split transactions.System on Chip interconnection • AMBA (Advanced Microcontroller Bus Architecture) is a collection of buses from ARM for satisfying a range of different criteria. Suitable for hosting peripherals. .

System on Chip cores • One solution to the design productivity gap is to make ASIC designs more standardized by reusing segments of previously manufactured chips. “cores” or “cells”. • Cores are the basic building blocks . • These segments are known as “blocks”. . • The blocks can either be developed in-house or licensed from an IP company. “macros”.

.System on Chip cores • Soft Macro – Reusable synthesizable RTL or netlist of generic library elements – User of the core is responsible for the implementation and layout • Firm Macro – Structurally and topologically optimized for performance and area through floor planning and placement – Exist as synthesized code or as a netlist of generic library elements • Hard Macro – Reusable blocks optimized for performance. power. size and mapped to a specific process technology – Exist as fully placed and routed netlist and as a fixed layout such as in GDSII format .

time to market .System on Chip cores Soft core Firm core Hard core Reusability portability flexibility Predictability. performance.

royalty. tool costs – Core integration.System on Chip cores • Locating the required cores and associated contract discussions can be a lengthy process – – – – – Identification of IP vendors Evaluation criteria Comparative evaluation exercise Choice of core Contract negotiations • Reuse restrictions • Costs: license. simulation and verification .

Major SoC Applications . Benefits and drawbacks . Solution .Agenda • • • • • • • Introduction . What is SoC ? SoC characteristics . . Summary .

Faster circuit operation . More reliable implementation . . Greater design security . Lower power consumption .The Benefits • There are several benefits in integrating a large digital system into a single integrated circuit . Smaller physical size . • These include – – – – – – Lower cost per gate .

Increased system complexity .The Drawbacks • The principle drawbacks of SoC design are associated with the design pressures imposed on today’s engineers . Exponential fabrication cost . . Increased verification requirements . such as : – – – – Time-to-market demands .

Design gap .

Solution . What is SoC ? SoC characteristics . Major SoC Applications . . Benefits and drawbacks .Agenda • • • • • • • Introduction . Summary .

• Done on such a scale that a new industry has been developed.Solution is Design Re-use • Overcome complexity and verification issues by designing Intellectual Property (IP) to be re-usable . – IP Integrators – consumers . evaluate. • IP Authors produce fully verified IP libraries – Thus making overall verification task more manageable • IP Integrators select. • Design activity is split into two groups: – IP Authors – producers . integrate IP from multiple vendors – IP integrated onto Integration Platform designed with specific application in mind .

Benefits and drawbacks . . Major SoC Applications . What is SoC ? SoC characteristics . Solution . Summary .Agenda • • • • • • • Introduction .

Major SoC Applications • Speech Signal Processing . DVD controller. IDE. • Data Communication – Wireline Communication: 10/100 Based-T...PCI-Express. WiMax. 2G/3G/4G.etc) Computer peripheries (printer control.. • Image and Video Signal Processing . • Information Technologies – PC interface (USB...etc . Gigabit Ethernet. xDSL. …. Etc – Wireless communication: BlueTooth. LCD monitor controller.etc) . WLAN. UWB. PCI.

Summary . Major SoC Applications .Agenda • • • • • • • Introduction . Benefits and drawbacks . What is SoC ? SoC characteristics . . Solution .

• The benefits that this brings are significant in terms of speed . area and power . • The drawbacks are that these systems are extremely complex requiring amounts of verification . .Summary • Technological advances mean that complete systems can now be implemented on a single chip . • The solution is to design and verify re-useable IP .

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