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Computer Processing

Computer Processing

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Published by: Osama_32 on Oct 23, 2011
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CPU Memory Buses Cache

The part of the computer performs the bulk of data processing operations is called the central processing unit
The CPU is made up of three major parts:
◦ Register set ◦ ALU ◦ Control units

The central processing unit (CPU) of a computer is the main unit that dictates the rest of the computer organization

1. Register set: Stores intermediate data during the execution of instructions; 2. Arithmetic logic unit (ALU): Performs the required microoperations for executing the instructions; 3. Control unit: supervises the transfer of information among the registers and instructs the ALU as to which operation to perform by generating control signals.

Control Unit Arithmetic Logic Unit Registers

Main memory (primary memory) is held on chips

Backing storage is not main memory

Backing storage is sometimes called secondary memory

• holds data/application programs from input devices/backing storage • can hold the operating system • all data is lost when the computer is switched off

Static RAM (SRAM) Contents of memory will be retained as long as power is applied to the chips
Dynamic RAM (DRAM) A continuous signal is needed to refresh (re-write) its contents

Static RAM has faster access speeds than DRAM
RAM is mainly made up of DRAM because it needs less power and its circuitry is simpler

SDRAM Synchronous dynamic random access memory takes advantage of the burst mode concept to greatly improve performance. It does this by staying on the row containing the requested bit and moving rapidly through the columns, reading each bit as it goes. The idea is that most of the time the data needed by the CPU will be in sequence. SDRAM is about five percent faster than EDO RAM and is the most common form in desktops today. Maximum transfer rate to L2 cache is approximately 528 MBps. DDR SDRAM Double data rate synchronous dynamic RAM is just like SDRAM except that is has higher bandwidth, meaning greater speed. Maximum transfer rate to L2 cache is approximately 1,064 MBps (for DDR SDRAM 133 MHZ).

• has contents which are fixed when the chip is manufactured • holds the bootstrap loader part of the operating system • retains its data when the computer is switched off

Programmable ROM (PROM)Empty of data when the chip is manufactured, can be programmed by the user. Once programmed the data cannot be erased.
Erasable PROM (EPROM)Like PROM only the chip can be removed from the computer and the program erased and another stored in its place using ultraviolet light. Electrically EPROM (EEPROM) Like EPROM but electricity is used to erase and reprogram selected contents.

Why? Reading / writing data to and from memory can slow down the system performance

Solution To combat this problem, the processor can store data in cache memory or its internal registers instead of the RAM

Virtual Memory
Part of the backing storage (hard disk) is set aside for virtual memory This disk area is used as a temporary location for programs and data It is useful when the computer does not have enough RAM to store the entire program and its data It is slower to access data held in virtual memory than data held in main memory

Definition: a collection of wires with a

common purpose

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Each wire is called a line Typically, buses carry information from one place to another

bus Printer Mouse Keyboard Ports Disk controller

Modem
CPU

Graphics card
Sound card Network card

Monitor Speakers

RAM

Computer

Point-to-point
Serial port
Modem

Control unit

ALU

•Multipoint
Computer Computer

Computer

Computer

CPU Disk controller

Memory
Video controller

Daisy chain

Device controller

Device

Device

Device

Terminator

Data bus Address bus Control bus CPU I/O Module Memory

Motherboard
•Many configurations possible

I/O Device

Carries data between the CPU and memory or I/O devices Bi-directional
◦ Data transferred “out of” the CPU for write operations ◦ Data transferred “into” the CPU for read operations


Typical sizes: 8, 16, 32, 64 lines Signal names:
◦ D0, D1, D2, D3, etc.

Carries an address from the CPU to Memory or I/O devices Unidirectional
◦ The address is always supplied by the CPU
(There is one exception to this, which we’ll discuss later.)

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Typical sizes: 16, 20, 24 lines Signal names:
◦ A0, A1, A2, A3, etc.


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Collection of signals for coordinating CPU activities Each signal has a unique purpose Typical sizes: 10-20 lines Signals are output, input, or bi-directional Typical signals
◦ ◦ ◦ ◦ ◦ /RD (read) /WR (write CLK (clock) /IRQ (interrupt request) etc.

Cache Memory
Due to increasing gap between CPU and main Memory, small SRAM memory called L1 cache inserted. L1 caches can be accessed almost as fast as the registers, typically in 1 or 2 clock cycle Due to even more increasing gap between CPU and main memory, Additional cache: L2 cache inserted between L1 cache and main memory : accessed in fewer clock cycles.

L2 cache attached to the memory bus or to its own cache bus Some high performance systems also include additional L3 cache which sits between L2 and main memory . It has different arrangement but principle same. The cache is placed both physically closer and logically closer to the CPU than the main memory.

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