LATHA MATHAVAN POLYTECHNIC COLLEGE KIDARIPATTI, MADURAI-625301 DEPARTMENT OF ELECTRICAL & ELECTRONINCS ENGINEERING II YEAR / IV SEMESTER (K-SCHEME) ANALOG

AND DIGITAL ELECTRONICS LAB MANUAL S.No NAME OF THE EXPERIMENT 1. INVERTING AMPLIFIER & NON INVERTING AMPLIFIER WITH DC & AC SIGNAL USING OPAMP 2. SUMMING AMPLIFIER, DIFFERENCE AMPLIFIER& VOLTAGE COMPARATOR USING OPAMP 3. INTEGRATOR & DIFFERENTIATOR 4. ASTABLE & MONOSTABLE MULTIVIBRATOR USING IC 555 5. IC VOLTAGE REGULATOR POWER SUPPLIES USING IC 7805,IC7912&LH317 FOR 1.2V TO 12V 6. VERIFICAION OF TRUTH TABLE OF OR.AND ,NOT,NOR,NANDAND XOR GATE 7. REALIZATION OF BASIC GATES USING NAND & NOR GATES 8. REALIZATION OF LOGIC CIRCUIT FOR A GIVEN BOOLEAN EXPRESSION 9. HALF ADDER,FULL ADDER AND 4 BIT FULL ADDER USING DISCRETE ICs 10. HALF SUBTRACTOR ,FULL SUBTRACTOR AND 4 BIT SUBTRACTOR USING DISCRETE ICs 11. CONSTRUCTION AND VERIFICATION OF TRUTH TABLE FOR DECODER,ENCODER 12. MULTIPLEXER,DEMULTIPLEXER USING CMOS 4051 13. PARITY GENERATOR AND CHECKER 14. CONSTRUCTION AND VERIFICATION OF TRUTH TABLE FOR D,T & JK FLIPFLOP 15. 4 BIT RIPPLE COUNTER USING FLIP FLOP WITH FEEDBACK 16. SINGLE DIGIT COUNTER USING 7490,7475,7447 AND SEVEN SEGMENT LED 17. CONSTRUCT & TEST DIGITAL DATA GENERATOR USING PARELLEL AND SERIAL SHIFT REGISTER 18. DAC USING R-2R NETWORK,BINARY WEIGHTED REGISTER NETWORK 19. A/D CONVERTER USING ADC0808 IC 20 DAC USING IC DAC 0808 PAGE NO 3 7 11 15 19 23 27 33 37 41 45 47 51 55 59 63 69 73 77 79

1

CIRCUIT DIAGRAM: INVERTING AMPLIFIER

Rf = 10 kΩ , Ri = 5 kΩ

TABULATION: INVERTING AMPLIFIER: INPUT VOLTAGE ( VIN Volts) THEORITICAL O/P (V) PRACTICAL O/P (V)

FORMULA: INVERTING AMPLIFIER: Vo = -( Rf / Ri) x Vi NON- INVERTING AMPLIFIER: Vo = [ 1 + ( Rf / Ri) ]x Vi

EX.NO:1
2

INVERTING AMPLIFIER & NON INVERTING AMPLIFIER WITH DC & AC SIGNAL USING OPAMP AIM: To construct and set up inverting amplifier & non inverting amplifier with dc & ac signal using op-amp IC 741. APPARATUS REQUIRED: Sl.No 1. 2. 3. 4. 5. THEORY: The op amp is a high gain, direct-coupled differential linear amplifier. Its response characteristics are controlled by external negative feedback from output to input. They are widely used in all phased of electronics. Negative input is the inverting input. When the signal is applied to this input, the output is 180° out of phase with the input. The +(plus) input is non-inverting. The output is in phase with the input when the input is applied to this terminal. One other importance fact about the op amp: Most require a dual power source, although some units operate satisfactorily with a single supply. PROCEDURE: 1. The Connections are given as shown in the circuit diagram. 2. Excitation voltage of +12V and -12V from regulated power supply is connected to Operational Amplifier terminals 7 & 4. 3. The corresponding input voltage are given and the output voltage are measured. Components Resistor Bread Board IC Fixed Power Supply CRO Range 5KΩ,10kΩ IC 741 +12v,-12V Quantity Each1 1 1 1 1

PIN DIAGRAM

3

NON-INVERTING AMPLIFIER Rf = 10 kΩ . Ri = 5 kΩ TABULATION : NON-INVERTING AMPLIFIER INPUT VOLTAGE ( VIN Volts) THEORITICAL O/P (V) PRACTICAL O/P (V) 4 .

RESULT: Thus the inverting amplifier. Non-inverting amplifier are designed using IC 741 and their performance are tested. CIRCUIT DIAGRAM: SUMMING AMPLIFIER 5 .

R1.NO:2 SUMMING AMPLIFIER. R3 = 5 kΩ . R2. Rf = 10 kΩ Vo = . DIFFERENCE AMPLIFIER& VOLTAGE COMPARATOR USING OPAMP 6 .(V1 + V2 + V3) V1 (v) V2 (v) V3(v) THEORITICAL O/P (V) PRACTICAL O/P (V) DIFFERENCE AMPLIFIER EX.

When V1 is equal to V2 . V1 is generated than V2.10kΩ IC 741 +12v. 2.AIM: To construct and set up summing amplifier. APPARATUS REQUIRED: Sl. 2. 4. Calculation : R1. typically equal or less than the negative supply voltage (negative saturation). A basic difference amplifier with all the resistor having equal value is used a subtractor. the input differential voltage is negative and the output goes to maximum negative. R4 = 10 kΩ VOUT = V1 – V2 V1 (v) V2 (v) THEORITICAL O/P (V) PRACTICAL O/P (V) 7 . the output voltage is the non inverted weighted sum of inputs. 3.No 1. difference amplifier & voltage comparator using op amp IC 741 and test its performance. 5. Similarly when V2 is greater than V1 the input differential voltage is positive and the output goes to maximum positive. THEORY: Components Resistor Bread Board IC Power Supply CRO Range 5KΩ. Excitation voltage of +12V and -12V from regulated power supply is connected to Operational Amplifier terminals 7 & 4. R3. The corresponding input voltage are given and the output voltage are measured. 3. typically equal to or less than the positive supply (positive saturation). output goes to zero PROCEDURE: 1.-12V Quantity Each1 1 1 1 1 A Summer that gives a non inverted sum is the non inverting summing amplifier. R2. The Connections are given as shown in the circuit diagram.

VOLTAGE COMPARATOR: Vi = 50µv Vi = -50µv Vo = 12v Vo = -12v FORMULA: Summing Vo = [ 1+ Rf / Ri ] x [ (V1/R1) + (V2/R2) + (V3/R3) / (1/R1) + (1/R2) + (1/R3) ] Difference Vo = [R2 / R1] (V1-V2) When R2=R1 8 .

difference amplifier & voltage comparator using op amp IC 741 is constructed and their performance are tested.NO:3 CIRCUIT DIAGRAM: DIFFERENTIATOR: 9 .RESULT: Thus the summing amplifier. EX.

10 .INTEGRATOR: EX.NO:3 INTEGRATOR & DIFFERENTIATOR Aim: To design and set up i) Differentiator ii) Integrator using an Operational Amplifier.

5. 4. 11 . 6.0. 2.Set the circuit after verifying the condition of the IC using analog tester or by voltage follower circuit.1mf.01mf 10K. Give input and output waveforms.Apparatus Required: Sl No 1. 2. 3.100 K Quantity 1No Each 1 no 1 Each 1 no 1 1 Procedure: 1. IC Capacitor DC Source Resistor Function Generator CRO Components Specification 741 0.

12 .

Result: Thus the integrator and differentiator circuits were constructed and the output waveforms were studied. 13 .

CIRCUIT DIAGRAM: ASTABLE MULTIVIBRATOR: MODEL GRAPH: 14 .

5.2 1 Each 1 no 1 1 1 Procedure: Astable Multivibrator: 1.NO:4 ASTABLE & MONOSTABLE MULTIVIBRATOR USING IC 555 Aim: To Construct and test the performance of Astable and monostable Multivibrator using IC 555.69 [Ra+2Rb] C Seconds F= 1/T hz MONOSTABLE MULTIVIBRATOR: 15 . 2. 2. Description Timer IC Capacitor IC Power Supply Resistor Function Generator CRO Bread Board 555 1000mf. The time for ON and OFF period are noted clesrly Calculation: T= 0.2K.22K 1Mhz 20Mhz Range Quantity 1No 1. 7.01mf +5V 1K. 4.10 K.EX. 3. 6. The oscilloscope is connected at the output terminals the waveform is observed and recorded. 3. 4. A Supply of +5V is given from the RPS to the circuit. The circuit is rigged upto the group board as per the connection diagram given.2. Apparatus Required: Sl No 1.0.

Output Waveform: Procedure: 16 .

Triggering is applied by pressing the push button. 6. IC 7805 17 . The circuit is rigged up to the group board as per the connection diagram given. Note the LED connected at the output terminal as shown as the switch pressed. 2. 4. A Supply of +5V is given from the RPS to the circuit. 5. Note the duration of the time during which LED glows. 3.1xRxC Sec Result: Thus the Astable and Monostable from the above calculation the theoretical trigger is rectified with the practical trigger of 555 IC.Monostable Multivibrator: 1. Verify timing obtain with the theoretical timing obtained by the application of timing formula Calculation: Tp = 1.

IC7912 LM317 Voltage Regulator Circuit: 18 .

EX. Apparatus Requires: Sl No 1. IC7912&LH317 FOR 1. 2. TABULATION: IC 7805 19 . 240 ohm Quantity Each 1No Each 1 no 1 Procedure: 1. Give the connections as per the circuit diagram on bread board. 0. 1mf. 7912. The unregulated voltage is given as input & for the difference settings the regulated voltage is taken at output are tabulated.1mf 3K. 7912. 3.33mf. LM317 0. 2.2V TO 12V Aim: To construct and test voltage regulator power supply using IC 7805.NO:5 IC VOLTAGE REGULATOR POWER SUPPLIES USING IC 7805. IC Capacitor Resistor Component Range 7805. LM 317.

NO Load Resistance in Ohms Output Voltage 20 .NO Load Resistance in Ohms Load Current Output Voltage IC 7912 SI.NO Load Resistance in Ohms Load Current Output Voltage LM 317 SI.SI.

7912. NOR. NAND & XOR GATE 21 .AND.NO:6 VERIFICAION OF TRUTH TABLE OF OR. EX. NOT.Result: Thus the voltage regulator power supplies using IC 7805. tested and the readings are tabulated. LM =317 are constructed.

NOT.EX. NOR.NO:6 VERIFICAION OF TRUTH TABLE OF OR. NAND & XOR GATE 22 .AND.

IC 7400. 3.IC 7404.Aim: To verify the truth table of the following logic gates using IC 74xx (i)OR gate (ii) AND gate (iii) NOT gate (iv) NOR gate (iv) NAND gate (v) Ex-OR gate. The same procedure is repeated for all the above mentioned ICs. 23 . 5. Trainer Kit Connecting wires 1No As required Procedure: 1.IC7402&IC 7486 Quantity Each 1No 2. Apparatus Required: Sl No 1. 3. Components IC 7408.IC 7432. 4. Output for different input conditions is verified as shown in the truth table. Inputs are applied to the proper pins of the IC. The supply voltage +5v is given to the IC. 2. Connections are made as per the Circuit diagram.

24 .

7402. 25 .Result: Thus the truth tables of OR.7400 & 7486 respectively. AND. NOT.7408. NAND&EX-OR gates are verified using ICs 7432. 7404. NOR.

UNIVERSAL NAND GATE CIRCUIT DIAGRAM: 26 .

27 . 3.NO:7 REALIZATION OF BASIC GATES USING NAND & NOR GATES Aim: To verify the Universal property of NAND & NOR gate using IC 7400 & IC 7402 Apparatus Required: Sl. 2. IC 7402 Trainer Kit Connecting wires Quantity 2 Nos 1No As required Procedure: 1. Connections are made as per the Circuit diagram. Components IC 7400. Outputs for different input conditions are verified as shown in the truth table.EX. The supply voltage +5v is given to the ICs. 2.No 1. 4. 3. Inputs are applied to the proper pins of the IC.

UNIVERSAL NOR GATE 28 .

29 .

30 .

Result: Thus the Universal property of NAND gate and NOR gate is verified using IC7400 & IC 7402. 31 .

Ex No: 8 32 .

4. If any isolated 1s remains.NO:8 REALIZATION OF LOGIC CIRCUITS FOR A GIVEN BOOLEAN EXPRESSION Aim: To realize the logic circuit for a given Boolean expression f(A. 2. Encircle the possible Octets. IC 7408 & 7432 Trainer Kit Connecting wires Components Quantity Each 1No 1No As required Steps for simplification of Boolean Expression: Construct a Karnaugh map and place 1s as per the min terms given in the expression and Place 0s in the other columns.EX. encircle each. Eliminate any redundant group. 3. Write the Boolean expression for the Octets. Quads and Pairs available in the map. Inputs are applied to the proper pins of the IC. Outputs for different input conditions are verified as shown in the truth table.C) Apparatus Required: Sl No 1. Quads and Pairs. The supply voltage +5v is given to the ICs.B. 33 . Procedure: 1. Connections are made as per the Circuit diagram. 2. 3.

Truth Table A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 0 0 1 0 1 1 1 34 .

Result: Thus the circuit for given problem f (A. 35 . B. C) is constructed and the truth table is verified.

NO:9 HALF ADDER 36 .EX.

7432 & IC 7486 Trainer Kit Connecting wires Quantity Each 1No 1No As required Procedure: 1. 4. The supply voltage +5v is given to the ICs. 3. Inputs are applied to the proper pins of the IC. 4 Bit full adder circuits using ICs 74xxs and verify the truth table. 2. 3.NO:9 HALF ADDER. FULL ADDER AND 4 BIT FULL ADDER USING DISCRETE ICs Aim: To construct the Half Adder. Apparatus Required: Sl No 1. Full Adder. 2. Components IC 7408. 37 . Outputs for different input conditions are verified as shown in the truth table. Connections are made as per the Circuit diagram.EX.

FULL ADDER +5V A B C 1 2 6 5 7486 3 4 220Ω A B C SUM CARRY 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 4 7 5 9 1 1 3 2 7408 7 220Ω 1 1 1 1 7432 14 +5V 38 .

39 .Full Adder and 4 bit full adder is constructed using 7408.7486 and 7432 ICs and the truth table is verified.Result: Thus the Half Adder.

NO:10 40 .EX.

The supply voltage +5v are given to the ICs. 2. Components IC 7408. Inputs are applied to the proper pins of the IC. 7404. Full subtractor and 4 bit Subtractor is constructed using 7408. 7404 & 7486 ICs and the truth table is verified. 3. 7432. 2. Outputs for different input conditions are verified as shown in the truth table.NO:10 HALF SUBTRACTOR. FULL SUBTRACTOR AND 4 BIT FULL SUBTRACTOR USING DISCRETE ICs Aim: To construct the half subtractor. Full subtractor and 4 bit Subtractor circuit using ICs 74xxs and verify the truth table. Apparatus Required: Sl No 1.EX. 3. Connections are made as per the Circuit diagram. 7432 & IC 7486 Trainer Kit Connecting wires Quantity Each 1No 1No As required Procedure: 1. 4. Result: Thus the Half subtractor. 41 .

S D F.S LOGIC DIAGRAM 220Ω BARROW A B C DIFFRENCE 220Ω CIRCUIT DIAGRAM TRUTH TABLE A B C 1 2 6 3 7486 7 4 5 14 1 2 4 14 7404 220Ω A 0 0 +5v B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 0 B 0 1 1 1 0 0 0 1 0 1 3 2 7432 1 14 3 2 7408 4 6 14 0 1 220Ω 1 1 1 42 .FULL SUBTRACTOR A B C B F.

Result: Thus the Half subtractor. Full subtractor and 4 bit Subtractor is constructed using 7408. 7432. 7404 & 7486 ICs and the truth table is verified. 43 .

NO:11 TRUTH TABLE: DIAGRAM B 0 0 1 1 A 0 1 0 1 Y0 1 0 0 0 Y1 0 1 0 0 Y2 0 0 1 0 Y3 0 0 0 1 0 1 2 3 ENCODER LOGIC +5v A1 A2 A3 ENCODER OUTPUT F1 INPUT F2 0 1 0 1 0 1 2 3 F0 1 4 3 2 14 F0 7432 F1 0 0 1 1 F1 44 .EX.

Components IC 7408. 2. 3. 0100. & 7432 ICs and the truth table is verified. Encoder is constructed using 7408.EX. 7404. 4.NO:11 CONSTRUCTION AND VERIFICATION OF TRUTH TABLE FOR DECODER. The same method used to encode is usually just reversed in order to decode Encoder : A single bit 4 to 2 encoder takes in 4 bits and outputs 2 bits. Inputs are applied to the proper pins of the IC. 0010. 3. It is assumed that there are only 4 types of input signals: 0001. 45 . IC 7404 & IC 7432 Trainer Kit Connecting wires Quantity Each 1No 1No As required THEORY : Decoder : It is a device which does the reverse of an encoder. 1000 Procedure: 1. Connections are made as per the Circuit diagram. 2. ENCODER Aim: To construct the Decoder and Encoder circuits using ICs 74xx and verify the truth table. undoing the encoding so that the original information can be retrieved. Result: Thus the Decoder. Apparatus Required: Sl No 1. Outputs for different input conditions are verified as shown in the truth table. The supply voltage +5v is given to the ICs.

EX.NO:12 MULTIPLEXER. DEMULTIPLEXER USING CMOS 4051 CIRCUIT DIAGRAM: MULTIPLEXER 46 .

Connections are made as per the Circuit diagram. 2. The multiplexer has several data input lines and a single output line. It also have data selected input that helps to choose any one of the inputs to be switched to the output line.NO:12 MULTIPLEXER. Procedure: 1. The supply voltage +5v is given to the ICs. DEMULTIPLEXER USING CMOS 4051 AIM: To Study the operation of a Multiplexer. 3.EX. Thus Demux has one input and many output. 47 . De multiplexer Using CMOS 4051 THEORY: Multiplexer: Multiplexer means many in to one A digital multiplexer is a combinational circuit that selects binary information from one of several input lines and directs it to a single line for transmission to a common destination the selection of a particular four input line is controlled by a set of selected lines. Outputs for different input conditions are verified as shown in the truth table. De multiplexer: A demultiplexer performs the reverse axtion of a multiplexer it takes data from one line and distributes it to a given number of output lines. Clock pulse is applied to the proper pin of the IC. 4.

DEMULTIPLEXER: PIN DIAGRAM: 48 .

Result: Thus the function of multiplexer and de multiplexer are verified. 49 .

NO:13 CONSTRUCTION OF PARITY GENERATOR AND CHECKER PARITY CHECKER: 50 .EX.

Parity checking: Parity checking is nothing but checking the even parity or odd parity of binary word which is used for transmission of data one place to another place in a digital system. Apparatus Required: Sl No 1. Such an extra parity bit can be earily generated using an EX-OR gate. 2.NO:13 CONSTRUCTION OF PARITY GENERATOR AND CHECKER Aim: To verify the parity generator for both odd and even parity and checker using logic gates and to get test its performance.etc in a computer. IC 74180 Trainer Kit Connecting wires Components Quantity 1No 1No As required THEORY: Parity generation: A binary number may represent an instruction that tells the computer to add. subtract and soon. Letter . For parity checking and generation a TTL IC 74180 is designed and used in parity application. In either case an extra bit is added to the original binary number to produce a binary number with even or odd parity. 51 .EX. The parity checking is also performed by using XOR logic diagram. 3. The binary number may also represent data to be processed like a number.

PARITYGENERATOR: TRUTH TABLE: INPUT D0 D1 D2 D3 D4 D5 D6 D6 OUTPUT EVEN ODD 52 .

53 . Result: Thus the parity generator and parity checker performences are verified. The supply voltage +5v is given to the ICs.Procedure: 1. 2. 4. 3. Clock pulse is applied to the proper pin of the IC. Outputs for different input conditions are verified as shown in the truth table. Connections are made as per the Circuit diagram.

NO:14 54 .NO:14 EX.EX.

2. 3. Connections are made as per the Circuit diagram. 2. 3. T & JK FLIPFLOP Aim: To verify the truth tables of JK. Components IC 7473. Clock pulse is applied to the proper pin of the IC. Apparatus Required: Sl No 1. T and D Flip Flops.CONSTRUCTION AND VERIFICATION OF TRUTH TABLE FOR D. 55 . 4. Outputs for different input conditions are verified as shown in the truth table. The supply voltage +5v is given to the ICs. & IC 7400 Trainer Kit Connecting wires Quantity Each 1No 1No As required Procedure: 1.7404.

T FLIPFLOP symb (a) Logic Circuit (b) Graphical (c) Truth table 56 .

NO:15 4 BIT RIPPLE COUNTER USING FLIP FLOP WITH FEEDBACK 57 .Result: Thus the truth tables JK FlipFlop. EX. T FlipFlop and D Flipflop are verified.

CIRCUIT DIAGRAM: +5v 1 16 7 9 IC 10 CLK 14 2 13 74161 PIN DIAGRAM: EX.NO:15 4 BIT RIPPLE COUNTER USING FLIP FLOP WITH FEEDBACK 58 .

Aim: To construct 4 bit ripple counter by using IC 74161 Apparatus Required: Sl No 1. Clock pulse is applied to the proper pin of the IC. Outputs for different input conditions are verified as shown in the truth table. IC 74161 Trainer Kit Connecting wires Components Quantity 1No 1No As required Procedure: 1. 3. The supply voltage +5v is given to the ICs. TABULATION: 59 . Connections are made as per the Circuit diagram. 3. 2. 2. 4.

3.CLOCK INPUT RESET 1. 8. QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OUTPUT QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 60 . 7. 4. 15. 6. 10. 5. 11. 14. 2. 12. 13. 9.

Result: Thus the 4 bit ripple counter is constructed by using IC 74161 and the corresponding truth tables are verified.NO:16 61 . EX.

NO:16 62 . 7447 AND SEVEN SEGMENT LED CIRCUIT DIAGRAM: EX.SINGLE DIGIT COUNTER USING 7490. 7475.

Procedure: 1. 4. 7495and 7447 seven segment LED display. 3. 7475. 7475. 7447 and seven segment LED display for counting ( constructing ) one digit counter. 7447 AND SEVEN SEGMENT LED Aim: To construct and test the performance of one digit counter using7490. 4. The IC 7447 converts the BCD code to its equivalent seven segment pattern for displaying the digit in a seven segment display unit. which will count the values from 0 to 9. 5. 3. PIN DIAGRAMS: 63 . The latch circuit connected in between counter and display section is used for controlling the signal flow. The supply voltage +5v is given to the ICs. Outputs for different input conditions are verified as shown in the truth table. 2. Connections are made as per the Circuit diagram. The decade counter will count the binary values from 0000 to 1001. Apparatus Required: Sl No 1. After that it will reset at the 10th clock pulse. Components Decade counter Latch circuit BCD to seven segment Decoder Seven segment LED display IC trainer board Range 7490 7475 7447 Common anode type Digital Quantity 1 1 1 1 1 THEORY: One digit counter is a counter.SINGLE DIGIT COUNTER USING 7490. 2. Clock pulse is applied to the proper pin of the IC. We need IC 7490.

64 .

Clock Input Reset 1 2 3 4 5 6 7 8
65

Digital Output

9

66

Result: Thus the digital data generator using parallel to serial shift register IC 74165 receiving the serial data to parallel output using IC 74164 are verified

EX.NO:17 CONSTRUCT & TEST DIGITAL DATA GENERATOR USING PARALLEL TO SERIAL SHIFT REGISTER
67

CIRCUIT DIAGRAM EX.NO:17 CONSTRUCT & TEST DIGITAL DATA GENERATOR USING PARALLEL TO SERIAL SHIFT REGISTER 68 .

The ic receives the parallel input data and stores it in a register inside it. 3. The stored data is serially transmitted from one place to another place because of the economical reason. Data from the input switches given as input to a parallel in serial shift register 74165. Components IC74194 Trainer kit Multimeter Connecting wire Quantity 1No 1No 1No 1No Theory: In digital system data is generated at one point serially transmitted to other place for data processing data generated by some encoding device and decoding obtain their 8 bit or 16 bit data and stored in sound register. Where it is against stored in a register inside a IC the data such stored can be verified by the glowing LEDS connected to the output of 74164. Since transmission of parallel data is proved to be costlier for this purpose shift register are used for carrying out the above job. 69 .Aim: To construct and test the digital data generator using parallel to serial shift register IC 74165 receiving the serial data to parallel output using IC 74164 Apparatus Required: Sl No 1. In this experiment data is generated by operating 8 input switches. By suitable application of clock in other signals the data stored in a 74165 is shifted serially to another 74164. 4. 2.

PROCEDURE: For right shift 70 .

terminal Apply clock pulse at clock1 terminal after each data bit observe output QA QB QC QD Verify operations as right shift register (data shifted from QA to QB). For left shift 1.NO:18 71 . 3. 4. QC to B. Connect mode control line to logic 0 and apply serial data at serial input starting from LSB. 3.1. EX. Connect mode control line to logic 1 and apply serial data at D input starting from LSB Connect QD to C. 2. 2. QB to A Apply clock pulse at clock2 ( pin8 ) Observe output QA QB QC QD and verify its operation as left shift register Result: Thus the digital data generator using parallel to serial shift register using IC 74194 are verified.

NO:18 72 . BINARY WEIGHTED REGISTER NETWORK CIRCUIT DIAGRAM: TABULATION: Digital Input C B A Analog Output -Vo Volts EX.DAC USING R-2R NETWORK.

DAC USING R-2R NETWORK.C are binary inputs.4k 15V (0-30)V (0-15)V 2-way switch Quantity 1No 1No 1No 1No 1No 3Nos Theory: The digital to analog converter converts the applied input are in input terminal which are digital signal to its equivalent analog signal the applied input are in binary form. 2. Components Op-amp Resister Linear IC power supply Regulated power supply Voltmeter Digital controlled switch Range IC 741 1k.[22b2+21b1+20b0] = . BINARY WEIGHTED REGISTER NETWORK Aim: To construct and test the performance of 3 digit binary weighted resistor digital to analog converted. (2k & 4k resistors are formed by connecting two & four 1k resistor serially) WEIGHTED REGISTER NETWORK 73 . Apparatus Required: Sl No 1. 3.B&C are switch positions.B. The summing amplifier multiplies each input voltage by the ratio of feedback resister to its corresponding input resister the output voltage Vo = -Rf\R * V\ 23-1 [23-1b3-1+23-2b3-2+23-3b3-3 = -Rf\R * V\ 22 [22b2+21b1+20b0] Choose the value = R L V= 4V(22) Vo= .[4c+2b+1a] Where A. 5. The operational amplifier act as a summing amplifier. 6.2k. 4. which are assumed to have values of 0or 1V. The A.

TABULATION: Digital Input C B A Analog Output -Vo Volts Procedure: 74 .

2. The supply voltage +5v is given to the ICs.1. Connections are made as per the Circuit diagram.NO:19 ADC USING IC ADC 0808 75 . Result: Thus the 3 bit binary weighted resister D\A converter is constructed and its performance was tested. EX. Outputs for different input conditions are verified as shown in the truth table. 4. 3. Clock pulse is applied to the proper pin of the IC.

CIRCUIT DIAGRAM: 76 .

EX.NO:19 A/D CONVERTER USING ADC0808 IC AIM: To verify the analog to digital conversion using ADC 0808 by study. RESULT: Thus the analog to digital conversion using ADC 0808 is studied. Counter type converter 3. Where conversion speed is important successive approximation and comparator type are faster but generally less accurate then integrating type convertors. The two most widely used integrating types converters are 1. THEORY: The A/D conversion is a quantizing process an analog signal is converted in to equivalent binary word. band meter and monitoring systems where the conversion accuracy is critical. Tracking or servo converter 4. the flash type is expensive for higher degree of accuracy. Flash type converter 2. Dual slope ADC The most commonly used ADCs are successive approximation and the integrated type the successive approximation ADCs are used in applications such as data loggers and instrumentation. ADC are classified broadly in to two groups according to their conversion technique direct type ADCs are integrating type ADCs direct type ADCs compare a given analog signal with the internally generated equivalent signal this groups includes 1. The integrating type convertor is used in applications such as digital meter. Thus the A/D converter is exactly opposite function that of the D/A converted.NO:20 DAC USING IC DAC 0808 77 . Successive approximation type converter Integrating type ADCs performs conversion in a indirect manner by first changing the analog input signal to the linear function of time or frequency.EX. Charge balancing ADC 2. And then to a digital code.

Digital Output Analog Output Volts D7 0 0 1 1 1 1 D6 0 0 1 1 1 1 D5 0 0 1 1 1 1 D4 0 0 1 1 1 1 D3 0 1 1 0 1 1 D2 0 1 1 0 1 1 D1 0 1 0 0 0 1 D0 0 1 0 0 0 1 0V - EX.NO:20 DAC USING IC DAC 0808 78 .

2. 79 . of inputs given to DAC. The digital inputs are switched to DAC 0808 inputs in. Name of the Apparatus IC trainer kit Resistances Voltmeter DAC 7411C Multimeter Range 4 0 to 15v 0 to 5v Quantity 1no 1no 2no 1no 1no 1no 5. 4. Digital signals are applied at the input of DAC and analog voltage is obtained as output. Theory: The DAC is a digital to analog Voltage encoder. The corresponding obtained analog voltage is obtained as output. 5. 4. The IC no. 6. Procedure: 1. DAC is designated by the no. The reading are noted and tabulated. 2. sequential steps from 00000000 to 11111111 as shown in the tabular column. Therefore it is called as 8 bit DAC. The connection as per the circuit diagram.no 1. Result: Thus the operation DAC using IC DAC 0808 is constructed and tested. 3. 3.Aim: To verify the operation DAC using IC DAC 0808 Apparatus Requied: Sl. In this experiment 8 digit inputs are connected in to analog signal. Power supply is connected to the circuit. is DAC0808.

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