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05/09/2014

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PCI ,PCI-X & PCI-Express Technology

What is BUS? The Bus is simply a common set of wires that connect all the computer devices and chips together. Some of these wires are used to transmit data. Some send housekeeping signals, like the clock pulse. Some transmit a number (the "address") that identifies a particular device or memory location Types of Bus 1)      The system bus or local bus connects the microprocessor (central processing unit) and the system memory.
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2) The second one is a slower bus for communicating with things like hard disks and sound cards. One very common bus of this type is known as the PCI bus. Quick History ISA:ISA is a 16-bit interface, which means that data can be transferred only two bytes at a time. More importantly, the ISA bus runs at only 8 MHz and it typically requires two or three clock ticks to transfer those two bytes of data

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MCA In 1987 IBM introduced a new Micro channel. Its 10 MHz clock was slightly faster. The cards could be automatically configured with a utility program instead of setting physical switches and jumpers EISA An EISA slot contained the older ISA interface, and then an extra socket with additional connections. The user could plug either an old ISA card or a new EISA card into the slot. The newer cards supported a 32-bit data interface.  
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VL-BUS or VESA It was 32 bits wide and operated at the speed of the local bus, which was normally the speed of the processor itself. The VL-Bus essentially tied directly into the CPU. Connecting more than two devices to the VL-Bus introduced the possibility of interference with the performance of the CPU. The VL-Bus was typically used only for connecting a graphics card

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PCI (Peripheral Component Interconnect)
The PCI bus was developed by Intel in 1992. The objective was an interface that was fast and inexpensive. PCI presents a hybrid of sorts between ISA and VL-Bus  The PCI specification covers the physical size of the bus (including wire spacing), electrical characteristics, bus timing, and protocols. The specification can be purchased from the PCI Special Interest Group (PCISIG).  These devices can take the form of: integrated circuits fitted on the motherboard itself (called planar devices in the PCI specification); or 10/18/08 Product Engineering 5

The PCI bus is able to work with so few pins because of hardware multiplexing, which means that the device sends more than one signal over a single pin. PCI supports devices that use either 5 volts or 3.3 volts. PCI can connect more devices than VL-Bus, up to five external components. PCI devices can also be self-configuring and operate in a Plug and Play mode

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Speed:- 
PCI originally operated at 33 MHz using a 32-bit-wide path. Revisions to the standard include increasing the speed from 33 MHz to 66 MHz and doubling the bit count to 64 . PCI PCI-X: The latest version 64 bits at: PCI-X 66, PCI-X 133, PCI-X 266 and PCI-X 533 [4.3GBps]

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)

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PCI / PCI-X Performance vs Demand

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PCI-E (PCI –Express)
It was developed by Intel (and formerly know as 3GIO or 3rd Generation I/O). The PCIe link is built around a bidirectional, serial (1-bit), point-to-point connection known as a "lane". This is in sharp contrast to the PCI connection, which is a bus-based system where all the devices share the same unidirectional, 32-bit, parallel bus. At the electrical level, each lane utilizes two unidirectional low voltage differential signaling 10/18/08 (LVDS) pairs at 2.5Product Engineering gigabaud. Transmit and 10

A connection between any two PCIe devices is known as a "link", and is built up from a collection of 1 or more lanes PCIe sends all control messages, including interrupts, over the same links used for data Data transmitted on multiple lane links is interleaved, The PCIe specification refers to this interleaving as "data striping".

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PCI Express Architecture

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Physical Layer The fundamental PCI Express link consists of two, lowvoltage, differentially driven pairs of signals: a transmit pair and a receive pair A data clock is embedded using the 8b/10b encoding scheme to achieve very high data rates. The initial frequency is 2.5 Giga transfers/second/direction

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The bandwidth of a PCI Express link may be linearly scaled by adding signal pairs to form multiple lanes

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Link Layer The primary role of a link layer is to ensure reliable delivery of the packet across the PCI Express link. The link layer is responsible for data integrity and adds a sequence number and a CRC to the transaction layer

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Transaction Layer Transaction Layer receives read and write requests from the software layer and creates request packets for transmission to the link layer.

Software Layers The run-time software model supported by PCI is a load-store, shared memory model – this is maintained within the PCI Express. Architecture which will enable all existing software to execute unchanged.
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Summary 
The PCI Express Architecture meets all of the requirements of a third generation I/O bus. It’s advanced features and scalable performance will enable it to become a unifying I/O solution across a broad range of platforms – desktop, mobile, server, communications, workstations and embedded devices. PCI Express is software compatible with all existing PCI-based software to enable smooth integration within future systems.
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