Diode-Transistor Logic (DTL

)

University of Connecticut

56

Diode Logic
VA VB OR GATE VOUT AND GATE VA VB VCC

VOUT

n

n n

Diode Logic suffers from voltage degradation from one stage to the next. Diode Logic only permits the OR and AND functions. Diode Logic is used extensively but not in integrated circuits!

University of Connecticut

57

Level-Shifted Diode Logic
AND GATE VA VB VCC=5V RH x VOUT DL RL
With either input at 0V, Vx=0.7V, DL is just cut off, and VOUT=0V. With both inputs at 1V, VX=1.7V and VOUT=1V. With VA=VB=5V, both input diodes are cut off. Then

VOUT
n n n

 VCC − 0.7V  = RL    RH + RL 

Level shifting eliminates the voltage degradation from the input to the ouput. However, the logic swing falls short of rail-to-rail, and the inverting function still is not available without using a transistor!
58

University of Connecticut

the transistor cuts off and VOUT goes high.Diode-Transistor Logic (DTL) VCC VA VB VC Q1 RC VOUT Primitive Precursor to DTL n n n n If any input goes high. If all inputs are low. 59 University of Connecticut . This is a NOR gate. the transistor saturates and VOUT goes low. “Current Hogging” is a problem because the bipolar transistors can not be matched precisely.

This is a NAND gate. The transistor cuts off and VOUT goes high.7V. The gate works marginally because VD = VBEA = 0. If any input goes low. the transistor saturates and VOUT goes low. the base current is diverted out through the input diode.Diode-Transistor Logic (DTL) VCC RB VA VB VC If all inputs are high. 60 RC VOUT Q1 Improved gate with reversed diodes. n n n n University of Connecticut .

61 University of Connecticut . Vx=0. to provide a reasonable tPLH. Vx = 2.9V. If any input goes low (0.2V and the transistor is saturated. n n n If all inputs are high.Diode-Transistor Logic (DTL) VCC RB RC VA VB VC x Q1 RD VOUT Basic DTL NAND gate. The added resistor RD provides a discharge path for stored base charge in the BJT. and the transistor cuts off.2V).

DTL VTC VCC VOUT RB RC 5 4 VA VB VC x Q1 RD VOUT 3 2 1 0 0 1 2 3 4 5 VIN VOH = VOL = n VIL = VIH = The noise margins are more symmetric than in the RTL case. 62 University of Connecticut .

8kΩ RD=1.4kΩ RC=4. P= 63 University of Connecticut .6kΩ RB VCC RC PL = VOUT Q1 VA VB VC x RD PH = n Scaling RB and RC involves a direct tradeoff between speed and power.DTL Power Dissipation RB=3.

4kΩ RC=4.DTL Fanout RB=3. University of Connecticut . large RD /RB.8kΩ RD=1.6kΩ βF=50 VCC RB RC I CS = VA VB VC x Q1 RD VOUT I BS = I CS = N max = 64 n Good fanout requires high β F.

D.5V / 1.930 Series DTL (ca 1964 A.4V VIH / VIL 45 Fanout 10mW Dissipation 75ns tP 65 University of Connecticut .0V / 0.2V VOH / VOL 1. Does Q1 saturate? 930 DTL Characteristics 5. providing more base drive for Q2 and improving the fanout (Nmax = 45).75kΩ 2kΩ VCC 6kΩ n VA VB VC Q1 Q2 5kΩ VOUT n One of the series diodes is replaced by Q1.) βF=50 1.

930 DTL Propagation Delays βF =50 CL=5pF 1.75kΩ 2kΩ VCC 6kΩ n tPLH >> tPHL tPLH = tS+tr /2 n ts = Q1 Q2 5kΩ VA VB VC VOUT tr ≈ University of Connecticut 66 .

Transistor-Transistor Logic (TTL) University of Connecticut 67 .

a single multi-emitter BJT replaces the input diodes.Why TTL? VA VB VC n n DTL The DTL input uses a number of diodes which take up considerable chip area. VA VB VC TTL n University of Connecticut 68 . In TTL. resulting in a more area-efficient design. DTL was ousted by faster TTL gates by 1974.

• QI is saturated. • VOH = VCC Multi-emitter transistor. • QI is reverse active. University of Connecticut 69 . Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents. VCC=5V RB D1 RCP VOUT QO RD n n ALL INPUTS HIGH. • QO is saturated.Basic TTL NAND Gate. • VOL = VCES VA VB VC QI ANY INPUT LOW. • QO is cut off.

and The capactive load must be charged to VCC.TTL Switching Speed: tPLH VCC=5V RB RC RCP VOUT QO RD CL n n n n VA VB VC QI QS The depletion capacitance of the QI EB junction must discharge. Ditto for QO. University of Connecticut 70 . Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents. Multi-emitter transistor. Base charge must be removed from the saturated QS.

The time required to extract the QS base charge is also << 1ns: • QI becomes forward active.TTL Switching Speed: tPLH VCC=5V RB RC RCP VOUT QO RD CL n n VA VB VC QI QS The time required to discharge the QI depletion layers is << 1ns. 71 University of Connecticut . • |IBR| becomes large for QS n Removal of base charge from QO is similar to the DTL case. With RD = 1 kΩ. ts = 10ns (these are typical values for 7400 series TTL).

g..3RC = 173 ns! 72 University of Connecticut .TTL Switching Speed: tPLH VCC=5V RB RC RCP 3 5 4 VOUT VA VB VC QI QS QO RD VOUT CL 2 1 0 0 100 200 t (ns) 300 n Charging of the capacitive load can be slow with “passive pullup. with a 5kΩ pull-up resistor and a 15 pF load (ten TTL gates) RC = 75 ns and tr = 2.” e.

VCC RC QP VOUT QO RD n With active pullup. QP is cutoff. 73 University of Connecticut . QP becomes forward active to provide maximum drive current for a quick rise time. we can achieve the best of both worlds: n When the output is low. when the output goes high. A small pullup resistance will improve the switching speed but will also increase the power and reduce the fanout. minimizing the power and maximizing the fanout. the dominant switching speed limitation was the charging of capacitive loads through the pullup resistor.TTL with Active Pullup n n In the previous example.

University of Connecticut 74 . n QS is saturated n QP should be cutoff VCC=5V RB RC QP VOUT QO RD The low output case is unsatisfactory with this circuit: VBP = VBEP = VEP = VA VB VC QI QS The “Totem Pole Output” solves this problem. n QS is cutoff n QP is forward active With a low output.TTL with Active Pullup n n With a high output.

6V Initially. DL VOUT I BP = RCP limits the collector current to a safe value. QP begins to conduct when VCS = VCESO+VD+VBEAP = 1.TTL with “Totem Pole Output” VCC=5V RB RC QP RCP n n VA VB VC QI QS QO RD n During turn-off. QS switches off before QO. University of Connecticut 75 .

7V. they turn on if an input goes more negative than -0. I. 76 University of Connecticut .Typical 74xx Series TTL VCC=5V 4kΩ 1. During switching transients. 7410 triple 3-input NAND The anti-ringing diodes at the input are normally cut off.6kΩ 130Ω QP VA VB VC QI QS QO 1kΩ DL VOUT 74xx TTL Characteristics 12 ns tPLH 8 ns tPHL 10 Fanout 10 mW Dissipation 100 pJ PDP 1/3 T.

6kΩ n VIN=0. QS turns on. QI is saturated. QS. VIL = (at the edge of conduction. VOH = 130Ω QP VIN QI QS QO 1kΩ DL VOUT n (the drop in the base resistor is small) First Breakpoint. IC=0) 77 1/6 NSC 7404 Hex Inverter University of Connecticut .Standard TTL: VTC β F =70 β R = 0. QO are cutoff. QP is forward active.1 4kΩ VCC=5V RC 1.

6kΩ n Second Breakpoint.1 4kΩ VCC=5V RC 1. QO saturates. QO turns on. VIN = VOUT = 130Ω QP VIN QI QS QO 1kΩ DL VOUT n Third Breakpoint.Standard TTL: VTC β F =70 β R = 0. VIH = 1/6 NSC 7404 Hex Inverter University of Connecticut 78 .

1 QI QS QO 1kΩ DL VOUT 2 1 0 VIN 1 2 3 4 5 VNML = University of Connecticut VNMH = 79 .Standard TTL: VTC 1/6 NSC 7404 Hex Inverter 4kΩ VCC=5V RC 1.6kΩ VOUT 5 4 3 130Ω QP VIN β F =70 β R = 0.

1 0.5 collector-emitter voltage (V) University of Connecticut . the output impedance is 60 21 mA ROL = The very low output impedance means that noise currents are translated into tiny noise voltages.6 mA collector current (mA) 80 0.2 mA 0.2 0. 80 40 IB = 0. 0 0.4mA 20 Characteristics for a 0 Texas Instruments junction isolated digital npn BJTat 25 oC.4 mA.Standard TTL: Low State ROUT 100 2.08V 1.4 mA 2 mA 1.3 0.8 mA For the saturated BJT with IB = 2. Thus only a small noise margin is neccesary.4 0.

Standard TTL: Input Current 1/4 TI 7400 Quad VCC=5V 2-input NAND 4kΩ RC 1.1 I IL = University of Connecticut 81 .6kΩ 130Ω n IIH (QI is reverse active) I BI = QP VA VB QI QS QO 1kΩ n DL VOUT I IH = IIL (QI is saturated) β F =70 β R = 0.

N max = AC considerations usually limit the fanout to a much lower number. I CI = I CS = I BO = n QP VA VB QI QS QO 1kΩ DL VOUT β F =70 β R = 0.Standard TTL: DC Fanout 1/4 TI 7400 Quad VCC=5V 2-input NAND 4kΩ RC 1. University of Connecticut 82 .1 To keep QO saturated.6kΩ 130Ω n With high inputs.

1 N = 10 P= University of Connecticut 83 .6kΩ 130Ω PH = QP VA VB QI QS QO 1kΩ DL VOUT PL = β F =70 β R = 0.Standard TTL: DC Dissipation 1/4 TI 7400 Quad VCC=5V 2-input NAND 4kΩ RC 1.

have steadily reduced parasitic capacitances and reduced RC time constants. this maximum drive is maintained over a wider range of VOUT than with a single pullup transistor. University of Connecticut 84 . This greatly improves tPLH. n Squaring Circuit. Active pull-down for the base of the output transistor squares the VTC.Advanced TTL Designs n n Schottky Clamping. Smaller devices. improving the low noise margin. An added benefit is faster charge removal for the output transistor. The Darlington pullup arrangement increases the average output drive current for charging a capacitive load. Although RCP limits the maximum output current. n Improved Fabrication. QS and QO may be Schottky clamped. and oxide isolation. Darlington Pullup. preventing saturation.

so Schottky clamping is not neccessary. The EB junction of QP2 introduces a 0. approaching RC /β 2. QP2 can not saturate. The Darlington emitter follower provides a very low output impedance.5kΩ n VOUT n QP2 is added. This greatly reduces the rise time. forming a Darlington pair with QP. University of Connecticut 85 . so DL can be eliminated. REP is needed to provide a discharge path for QP2 base charge.7V level shift.Darlington Pullup VCC=5V RC 900Ω n RCP 50Ω n QP QP2 REP 3.

” VIL is increased. in other words. improving the low noise margin. QS and QO begin to conduct simultaneously. BP1 is eliminated from the VTC. 86 University of Connecticut . the VTC is “squared.Squaring Circuit VOUT QS QO RBD 500Ω VOUT RCD 250Ω 5 VIL BP2 VOH 4 3 2 7400 74S00 QD VOL 1 0 1 BP3 VIH 2 3 4 5 VIN n n n n There is no path for QS emitter current until QD and QO turn on.

Schottky TTL (74S / 54S Series) 1/4 74S00 quad 2-input NAND RB 2.5kΩ Schottky clamping Schottky anti-ringing diodes Darlington pullup circuit Squaring circuit Scaled resistors VOUT QO RBD 500Ω Performance: n n n RCD 250Ω QD P = 20 mW tP = 3 ns (15 pF) PDP = 60 pJ 87 University of Connecticut .8kΩ VCC=5V RCP 50Ω Features: n n n n n RC 900Ω QP QP2 VA VB QI QS REP 3.

Sign up to vote on this title
UsefulNot useful