VLSI PRACTICAL FILE

Rahul Purohit

Assignment 1 Object: Design following Circuit using “DataFlow” approach of VHDL. A) AND B) OR C) NOT D) NAND E) NOR F) EX-OR G) Ex-NOR

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VLSI PRACTICAL FILE

Rahul Purohit

A) AND Truth Table: INPUT(X) 0 0 1 1 Function: Z = X.Y VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ands is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end ands; architecture Dataflow of ands is begin Z <= X and Y; end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 0 0 1

VLSI PRACTICAL FILE

Rahul Purohit

RTL Design:

Waveform:

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VLSI PRACTICAL FILE

Rahul Purohit

B) OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = X+Y VHDL Code: library IEEE;

INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 1 1 1

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ors is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end ors; architecture Dataflow of ors is begin Z <= X or Y; end Dataflow;
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VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 5|Page .

OUTPUT(Y) 1 0 6|Page .STD_LOGIC_ARITH. end Dataflow.STD_LOGIC_UNSIGNED. use IEEE. end nores.ALL.STD_LOGIC_1164.ALL. use IEEE. Y : out std_logic).ALL. architecture Dataflow of nores is begin Y <= not(X). entity nores is Port ( X : in std_logic. use IEEE.VLSI PRACTICAL FILE Rahul Purohit C) NOT Truth Table: INPUT(X) 0 1 Function: Z = ~(Y) VHDL Code: library IEEE.

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 7|Page .

ALL. use IEEE.ALL. use IEEE.STD_LOGIC_1164. Y : in std_logic.ALL. Z : out std_logic). use IEEE. end Dataflow.STD_LOGIC_ARITH. entity Nandss is Port ( X : in std_logic. end Nandss. architecture Dataflow of Nandss is begin Z <= not(X and Y).Y) VHDL Code: library IEEE.VLSI PRACTICAL FILE Rahul Purohit D) NAND Truth Table: INPUT(X) 0 0 1 1 Function: Z = ~(X.STD_LOGIC_UNSIGNED. 8|Page INPUT(Y) 0 1 0 1 OUTPUT(Z) 1 1 1 0 .

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 9|Page .

VLSI PRACTICAL FILE Rahul Purohit E) NOR Truth Table: INPUT(X) 0 0 1 1 Function: Z = ~(X+Y) VHDL Code: library IEEE. Z : out std_logic).ALL.ALL.ALL. entity nord is Port ( X : in std_logic. use IEEE.STD_LOGIC_1164. End nord.STD_LOGIC_ARITH. use IEEE. architecture Dataflow of nord is begin Z <= not(X or Y). 10 | P a g e INPUT(Y) 0 1 0 1 OUTPUT(Z) 1 0 0 0 . end Dataflow.STD_LOGIC_UNSIGNED. Y : in std_logic. use IEEE.

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 11 | P a g e .

use IEEE. Y : in std_logic. entity ExORD is Port ( X : in std_logic.ALL. end Dataflow. use IEEE.VLSI PRACTICAL FILE Rahul Purohit F) EX-OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = (X. architecture Dataflow of ExORD is begin Z <= (X and not(Y))or(Y and not(X)).ALL. 12 | P a g e INPUT(Y) 0 1 0 1 OUTPUT(Z) 0 1 1 0 .STD_LOGIC_UNSIGNED.~(Y))+(Y.~(X)) VHDL Code: library IEEE. Z : out std_logic).STD_LOGIC_1164.STD_LOGIC_ARITH. End ExORD. use IEEE.ALL.

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 13 | P a g e .

ALL. use IEEE. 14 | P a g e INPUT(Y) 0 1 0 1 OUTPUT(Z) 1 0 0 1 .STD_LOGIC_UNSIGNED.Y)+(~(X). Y : in std_logic.ALL.~(Y)) VHDL Code: library IEEE. use IEEE.STD_LOGIC_ARITH. entity ExnorD is Port ( X : in std_logic.STD_LOGIC_1164.ALL.VLSI PRACTICAL FILE Rahul Purohit G) EX-NOR Truth Table: INPUT(X) 0 0 1 1 Function: Z = (X. architecture Dataflow of ExnorD is begin Z <= (X and Y)or(not(X) and not(Y)). use IEEE. End ExnorD. end Dataflow. Z : out std_logic).

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 15 | P a g e .

VLSI PRACTICAL FILE Rahul Purohit Assignment 2 Object: Design following Circuit using “Behaviour” approach of VHDL. A) AND B) OR A) AND Truth Table: INPUT(X) 0 0 1 1 Function: Z = X.ALL. use IEEE.ALL.STD_LOGIC_UNSIGNED.ALL. 16 | P a g e INPUT(Y) 0 1 0 1 OUTPUT(Z) 0 0 0 1 .Y VHDL Code: library IEEE. use IEEE. use IEEE.STD_LOGIC_ARITH. Y : in std_logic.STD_LOGIC_1164. entity AB is Port ( X : in std_logic.

Y) begin if((X='1')and(Y='1')) then Z <= '1'. else Z <= '0'.VLSI PRACTICAL FILE Rahul Purohit Z : out std_logic). architecture Behavioral of AB is begin process(X. RTL Design: Waveform: 17 | P a g e . end if. end process. end AB. end Behavioral.

STD_LOGIC_ARITH.STD_LOGIC_UNSIGNED.VLSI PRACTICAL FILE Rahul Purohit B) OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = X+Y VHDL Code: library IEEE. use IEEE.Y) begin 18 | P a g e .ALL.ALL. use IEEE. INPUT(Y) 0 1 0 1 OUTPUT(Z) 0 1 1 1 use IEEE.STD_LOGIC_1164. end OB. Z : out std_logic). entity OB is Port ( X : in std_logic. Y : in std_logic. architecture Behavioral of OB is begin process(X.ALL.

end process. end if. end Behavioral. else Z <= '1'. RTL Design: Waveform: 19 | P a g e .VLSI PRACTICAL FILE Rahul Purohit if((X='0')and(Y='0')) then Z <= '0'.

STD_LOGIC_UNSIGNED. entity HA is Port ( A : in std_logic.ALL. use IEEE. use IEEE. B : in std_logic.STD_LOGIC_ARITH.VLSI PRACTICAL FILE Rahul Purohit Assignment 3 Object: Design following Circuit using “DataFlow” approach of VHDL. 20 | P a g e B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1 .ALL.STD_LOGIC_1164.ALL. A) Half-Adder B) Half-Subtractor A) Half-Adder Truth Table: A 0 0 1 1 Function: SUM = A xor B CARRY A and B VHDL Code: library IEEE. use IEEE.

VLSI PRACTICAL FILE Rahul Purohit SUM : out std_logic. CARRY : out std_logic). RTL Design: Waveform: 21 | P a g e . end HA. end Dataflow. CARRY <= A and B. architecture Dataflow of HA is begin SUM <= A xor B.

STD_LOGIC_ARITH.STD_LOGIC_1164. end HS. use IEEE. SUM : out std_logic.STD_LOGIC_UNSIGNED.VLSI PRACTICAL FILE Rahul Purohit B) Half Subtractor Truth Table: A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 BORROW 0 1 0 0 Function: SUM = A xor B BORROW = ~(A) and B VHDL Code: library IEEE. B : in std_logic.ALL. entity HS is Port ( A : in std_logic. use IEEE. 22 | P a g e . BORROW : out std_logic).ALL. use IEEE.ALL. BORROW <= not(A) and B. architecture Dataflow of HS is begin SUM <= A xor B.

RTL Design: Waveform: 23 | P a g e .VLSI PRACTICAL FILE Rahul Purohit end Dataflow.

use IEEE.STD_LOGIC_1164. A) Full-Adder B) Full-Subtractor A) Full-Adder Truth Table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1 Function: SUM = A xor B xor C CARRY = A and B and C VHDL Code: library IEEE. use IEEE. use IEEE.ALL.ALL.STD_LOGIC_UNSIGNED. 24 | P a g e .ALL.STD_LOGIC_ARITH.VLSI PRACTICAL FILE Rahul Purohit Assignment 4 Object: Design following Circuit using “DataFlow” approach of VHDL.

C : in std_logic. B : in std_logic. end FA.VLSI PRACTICAL FILE Rahul Purohit entity FA is Port ( A : in std_logic. RTL Design: 25 | P a g e . CARRY : out std_logic). CARRY <= A and B and C. architecture Dataflow of FA is begin SUM <= A xor B xor C. end Dataflow. SUM : out std_logic.

VLSI PRACTICAL FILE Rahul Purohit Waveform: 26 | P a g e .

BORROW : out std_logic). C : in std_logic.ALL. SUM : out std_logic. use IEEE.STD_LOGIC_1164.ALL. use IEEE. use IEEE. 27 | P a g e .STD_LOGIC_UNSIGNED.STD_LOGIC_ARITH. entity FS is Port ( A : in std_logic.ALL.VLSI PRACTICAL FILE Rahul Purohit B) Full-Subtractor Truth Table: A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 BORROW 0 1 1 1 0 0 0 1 Function: SUM = A xor B xor C BORROW = (B and C) or (~(A) and C) or (~(A) and B) VHDL Code: library IEEE. B : in std_logic. end FS.

BORROW <= (B and C) or (not(A) and C) or (not(A) and B). RTL Design: Waveform: 28 | P a g e .VLSI PRACTICAL FILE Rahul Purohit architecture Dataflow of FA is begin SUM <= A xor B xor C. end Dataflow.

A) 4X1 MUX B) 1X4 DEMUX A) 4X1 MUX Truth Table: INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D0 D1 D2 D3 Function: Y = ((d0 and (not s0) and (not s1)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s0 and s1)) 29 | P a g e .VLSI PRACTICAL FILE Rahul Purohit Assignment 5 Object: Design following Circuit using “DataFlow” approach of VHDL.

STD_LOGIC_1164.STD_LOGIC_UNSIGNED. 30 | P a g e .VLSI PRACTICAL FILE Rahul Purohit VHDL Code: library IEEE. D2 : in std_logic. end mux4. end dataflow. use IEEE. use IEEE. architecture dataflow of mux4 is begin Y <=((D0 and (not S0) and (not S1)) or (D1 and (not S0) and S1) or (D2 and S0 and (not S1)) or (D3 and S0 and S1)). Y : out std_logic). S1 : in std_logic.ALL.ALL. D3 : in std_logic. use IEEE. D0 : in std_logic.STD_LOGIC_ARITH. entity mux4 is Port ( S0 : in std_logic.ALL. D1 : in std_logic.

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 31 | P a g e .

D : in std_logic).S0. Y1 : out std_logic.S0.VLSI PRACTICAL FILE Rahul Purohit B) 1X4 DEMUX Truth Table: INPUT S0 S1 Y0 0 0 D 0 1 0 1 0 0 1 1 0 Function: Y0 = D.~(S1) Y3 = D.STD_LOGIC_ARITH.STD_LOGIC_UNSIGNED.STD_LOGIC_1164.~(S0). S1 : in std_logic. Y2 : out std_logic. 32 | P a g e .~(s1) Y1 = D. Y3 : out std_logic. use IEEE.S1 Y2 = D. entity demux4 is Port ( Y0 : out std_logic.ALL. use IEEE.ALL.S1 OUTPUT Y1 Y2 0 0 D 0 0 D 0 0 Y3 0 0 0 D VHDL Code: library IEEE. S0 : in std_logic.ALL. use IEEE.~(S0).

RTL Design: 33 | P a g e .VLSI PRACTICAL FILE Rahul Purohit end demux4. end Dataflow. Y1 <= (D and (not S0) and S1). Y3 <= (D and S0 and S1). Y2 <= (D and S0 and (not S1)). architecture Dataflow of demux4 is begin Y0 <= (D and (not S0) and (not S1)).

VLSI PRACTICAL FILE Rahul Purohit Waveform: 34 | P a g e .

ALL.STD_LOGIC_1164.VLSI PRACTICAL FILE Rahul Purohit Assignment 6 Object: Design following Circuit using “Behaviour” approach of VHDL.STD_LOGIC_ARITH. use IEEE. use IEEE. use IEEE. A) 4X1 MUX B) 8X1 MUX A) 4X1 MUX Truth Table: INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D0 D1 D2 D3 Function: Y = ((d0 and (not s0) and (not s1)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s0 and s1)) VHDL Code: library IEEE.ALL. entity mux4 is 35 | P a g e .STD_LOGIC_UNSIGNED.ALL.

D1 : in std_logic. end if. end Behavioral. elsif(S0 = '0' and S1 = '1') then Y <= D1. end process. Y : out std_logic). end mux4. S1 : in std_logic. elsif(S0 = '1' and S1 = '0') then Y <= D2.S0.D1. 36 | P a g e . D2 : in std_logic.VLSI PRACTICAL FILE Rahul Purohit Port ( S0 : in std_logic. elsif(S0 = '1' and S0 = '1') then Y <= D3.D2. architecture Behavioral of mux4 is begin process(D0. D3 : in std_logic. D0 : in std_logic.D3.S1) begin if(S0 = '0' and S1 = '0') then Y <= D0.

VLSI PRACTICAL FILE Rahul Purohit RTL Design: Waveform: 37 | P a g e .

use IEEE. use IEEE.C.D1 or ~(A).~(C).D7 VHDL Code: library IEEE.D4 or A.~(B).STD_LOGIC_ARITH.C.VLSI PRACTICAL FILE Rahul Purohit B) 8X1 MUX Truth Table: A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT Y D0 D1 D2 D3 D4 D5 D6 D7 Function: Y = ~(A).ALL.~(B).~(C).STD_LOGIC_UNSIGNED.D5 or A.C.B.ALL.D3 or A.D0 or ~(A).~(B). use IEEE. entity mux8 is Port ( A : in std_logic.~(B). B : in std_logic.B.ALL. C : in std_logic.~(C). D0 : in std_logic.~(C).D6 or A.D2 or ~(A).C. 38 | P a g e .B.STD_LOGIC_1164.B.

D5.D6.D1. D5 : in std_logic. architecture Behavioral of mux8 is begin process(D0. D6 : in std_logic.D4.B. elsif(A = '1' and B = '1' and C = '0') then Y <= D6.D2. D7 : in std_logic. elsif(A = '1' and B = '0' and C = '0') then Y <= D4. elsif(A = '0' and B = '1' and C = '1') then Y <= D3. Y : out std_logic). 39 | P a g e .D7. elsif(A = '0' and B = '1' and C = '0') then Y <= D2.C) begin if(A = '0' and B = '0' and C = '0') then Y <= D0.A. D2 : in std_logic. D3 : in std_logic. D4 : in std_logic. elsif(A = '0' and B = '0' and C = '1') then Y <= D1. elsif(A = '1' and B = '0' and C = '1') then Y <= D5. end mux8.VLSI PRACTICAL FILE Rahul Purohit D1 : in std_logic.D3.

RTL Design: 40 | P a g e . end if. end Behavioral.VLSI PRACTICAL FILE Rahul Purohit elsif(A = '1' and B = '1' and C = '1') then Y <= D7. end process.

VLSI PRACTICAL FILE Rahul Purohit Waveform: 41 | P a g e .

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