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pwm vhdl

pwm vhdl

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Published by Tuấn Ka Ka

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Published by: Tuấn Ka Ka on Nov 11, 2011
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02/28/2013

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entity Counter is Generic ( C_COUNTER_WIDTH : integer := 5; C_UP_DOWN : boolean := true ); Port ( clk : in std_logic; ena : in std_logic; reset : in std_logic; count : out std_logic_vector(C_COUNTER_WIDTH-1 downto 0) --zero : out std_logic ); end Counter; architecture Behavioral of Counter is constant UP_TC : std_logic_vector(C_COUNTER_WIDTH-1 downto 0 ) := (others => '1'); signal Q : std_logic_vector(C_COUNTER_WIDTH-1 downto 0) := (others => '0'); signal up : std_logic; begin up_down_counter : if C_UP_DOWN = true generate begin process(reset, clk) begin if (clk'event and clk = '1' ) then if ( reset = '1' ) then Q <= (others => '0' ) ; up <= '0' ; else if( ena = '1' ) then if ( up = '1' ) then if( Q = UP_TC ) then up <= '0' ; else Q <= Q + 1 ; end if; else if( Q = 0 ) then up <= '1' ; else Q <= Q - 1 ; end if; end if; end if; end if; end if; end process; end generate; up_counter : if C_UP_DOWN = false generate

reset : in std_logic. C_CENTERED : boolean := TRUE ). ena : in std_logic. cmp : in std_logic_vector(C_WIDTH-1 downto 0). deadband : in std_logic_vector(C_WIDTH-1 downto 0). architecture Behavioral of Compare is signal compare_value : std_logic_vector(C_WIDTH downto 0 ) := (others => '0'). begin asserted <= '1' when (C_ACTIVE_HIGH = TRUE) else '0'. else if( ena = '1' ) then Q <= Q + 1. end generate. end if.begin process(reset. end process. C_ACTIVE_HIGH : boolean := TRUE. non_centered_pwm : if C_CENTERED = FALSE generate begin process( clk ) begin if( reset = '1' or ena = '0' ) then top <= not asserted. count : in std_logic_vector(C_WIDTH-1 downto 0). signal asserted : std_logic := '0'. count <= Q. end Behavioral. top : out std_logic. end Compare. end if. --zero <= '1' when (Q = 0) else '0'. end if. --load : in std_logic. bottom <= not asserted. . bottom : out std_logic --deadband_active : out std_logic ). Port ( clk : in std_logic. clk) begin if (clk'event and clk = '1' ) then if ( reset = '1' ) then Q <= (others => '0' ) . entity Compare is Generic ( C_WIDTH : integer := 2.

if( conv_integer(count) >= top_cmp ) then --deadband_active <= '0' after 1 ns. bottom <= not asserted. variable bot_cmp : integer. centered_pwm : if C_CENTERED = TRUE generate begin process(clk.compare_value <= '0' & cmp. elsif( conv_integer(count) < bot_cmp ) then --deadband_active <= '0' after 1 ns. bottom <= not asserted . bottom <= not asserted . bot_cmp := conv_integer(compare_value) . top_cmp := conv_integer(compare_value) + (conv_integer(deadband)/2). end Behavioral. top <= not asserted . end if. else top <= not asserted . elsif (clk'event and clk ='1') then --if( load = '1' ) then compare_value <= '0' & cmp . begin if( reset = '1' or ena = '0' ) then --deadband_active <= '0'. elsif (clk'event and clk ='1') then --if( load = '1' ) then compare_value <= '0' & cmp . end process. bottom <= asserted . --end if. end generate. bottom <= not asserted . compare_value <= '0' & cmp. reset. --end if. end generate. . bottom <= asserted . end process. else --deadband_active <= '1' after 1 ns. top <= asserted . top <= not asserted. ena) variable top_cmp : integer. top <= not asserted .(conv_integer(deadband)/2). end if. end if. end if. if( count < compare_value ) then top <= asserted after 1 ns.

END COMPONENT.entity PWM is Generic ( C_COUNTER_WIDTH : integer := 2. count : OUT std_logic_vector(C_COUNTER_WIDTH-1 downto 0) --zero : OUT std_logic ). . C_CENTERED : boolean := C_CENTERED ). deadband : in std_logic_vector(C_COUNTER_WIDTH-1 downto 0). reset : IN std_logic. end PWM. PORT( clk : IN std_logic. deadband : IN std_logic_vector(C_COUNTER_WIDTH-1 downto 0). duty : in std_logic_vector(C_COUNTER_WIDTH-1 downto 0). C_ACTIVE_HIGH : boolean := TRUE. cmp : IN std_logic_vector(C_COUNTER_WIDTH-1 downto 0). top : out std_logic. C_CENTERED : boolean := TRUE ). Port( clk : in std_logic. count : IN std_logic_vector(C_COUNTER_WIDTH-1 downto 0). reset : in std_logic. ena : IN std_logic. architecture Behavioral of PWM is COMPONENT Counter Generic ( C_COUNTER_WIDTH : integer := C_COUNTER_WIDTH. ena : IN std_logic. bottom : out std_logic --deadband_active : out std_logic ). signal count : std_logic_vector( C_COUNTER_WIDTH-1 downto 0) := (others => '0'). C_UP_DOWN : boolean := C_CENTERED ). END COMPONENT. reset : IN std_logic. C_ACTIVE_HIGH : boolean := C_ACTIVE_HIGH. --load : IN std_logic. bottom : OUT std_logic --deadband_active : OUT std_logic ). COMPONENT Compare Generic ( C_WIDTH : integer := C_COUNTER_WIDTH. top : OUT std_logic. ena : in std_logic. PORT( clk : IN std_logic.

. bottom => bottom --deadband_active => deadband_active ).--signal zero : std_logic := '0'. begin Inst_counter: counter PORT MAP( clk => clk. ena => ena. top => top. count => count. end Behavioral. ena => ena. reset => reset. deadband => deadband. --load => zero. Inst_compare: compare PORT MAP( clk => clk. count => count --zero => zero ). cmp => duty. reset => reset.

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